diff --git a/.idea/.gitignore b/.idea/.gitignore new file mode 100644 index 0000000..26d3352 --- /dev/null +++ b/.idea/.gitignore @@ -0,0 +1,3 @@ +# Default ignored files +/shelf/ +/workspace.xml diff --git a/.idea/inspectionProfiles/profiles_settings.xml b/.idea/inspectionProfiles/profiles_settings.xml new file mode 100644 index 0000000..105ce2d --- /dev/null +++ b/.idea/inspectionProfiles/profiles_settings.xml @@ -0,0 +1,6 @@ + + + + \ No newline at end of file diff --git a/.idea/misc.xml b/.idea/misc.xml new file mode 100644 index 0000000..a2e120d --- /dev/null +++ b/.idea/misc.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/.idea/modules.xml b/.idea/modules.xml new file mode 100644 index 0000000..c8cd3c7 --- /dev/null +++ b/.idea/modules.xml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/.idea/risc-v-boris-basic-execution-environment.iml b/.idea/risc-v-boris-basic-execution-environment.iml new file mode 100644 index 0000000..317dedf --- /dev/null +++ b/.idea/risc-v-boris-basic-execution-environment.iml @@ -0,0 +1,10 @@ + + + + + + + + + + \ No newline at end of file diff --git a/CONTRIBUTORS.md b/CONTRIBUTORS.md index ab8fd9b..edcb935 100644 --- a/CONTRIBUTORS.md +++ b/CONTRIBUTORS.md @@ -22,4 +22,4 @@ Mihir Maringanti Marwan Ismail (marwannismail) -Tony Zhu (RunzeZhu28) \ No newline at end of file +Tony Zhu (RunzeZhu28) diff --git a/Dockerfile.riscv-toolchain b/Dockerfile.riscv-toolchain old mode 100755 new mode 100644 index dc256a1..3898670 --- a/Dockerfile.riscv-toolchain +++ b/Dockerfile.riscv-toolchain @@ -1,65 +1,65 @@ -FROM public.ecr.aws/lts/ubuntu:22.04_stable AS builder - -ARG DEBIAN_FRONTEND=noninteractive -ARG KEYRING_PATH=/usr/share/keyrings -ARG APT_SOURCES_PATH=/etc/apt/sources.list.d - -# update and upgrade -RUN apt update && apt upgrade -y - -# install essentialls -RUN apt update && \ - apt install -y \ - man make build-essential git zsh vim curl wget procps gnupg gnupg2 ca-certificates zip \ - software-properties-common - -# unminimize the system -RUN bash -c "yes | unminimize" - -# create dev sudo user -RUN useradd --create-home dev && \ - usermod --append --groups sudo dev && \ - apt update && apt install -y sudo && \ - echo '%sudo ALL=(ALL) NOPASSWD:ALL' >> /etc/sudoers - -# build riscv toolchain -RUN sudo apt-get install -y \ - autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk \ - build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev && \ - cd /tmp && \ - git clone --recursive https://github.com/riscv/riscv-gnu-toolchain.git && \ - git clone --recursive https://github.com/riscv/riscv-opcodes.git && \ - cd riscv-gnu-toolchain && \ - ./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi=ilp32 && \ - sudo make - -# main image stage -FROM public.ecr.aws/lts/ubuntu:22.04_stable - -ARG DEBIAN_FRONTEND=noninteractive -ARG KEYRING_PATH=/usr/share/keyrings -ARG APT_SOURCES_PATH=/etc/apt/sources.list.d - -# update and upgrade -RUN apt update && apt upgrade -y - -# install essentialls -RUN apt update && \ - apt install -y \ - man make build-essential git zsh vim curl wget procps gnupg gnupg2 ca-certificates zip \ - software-properties-common - -# unminimize the system -RUN bash -c "yes | unminimize" - -# create dev sudo user -RUN useradd --create-home dev && \ - usermod --append --groups sudo dev && \ - apt update && apt install -y sudo && \ - echo '%sudo ALL=(ALL) NOPASSWD:ALL' >> /etc/sudoers - -# get toolchain artifacts from builder stage -COPY --from=builder /opt/riscv /opt/riscv -ENV PATH="/opt/riscv/bin:${PATH}" - -USER dev +FROM public.ecr.aws/lts/ubuntu:22.04_stable AS builder + +ARG DEBIAN_FRONTEND=noninteractive +ARG KEYRING_PATH=/usr/share/keyrings +ARG APT_SOURCES_PATH=/etc/apt/sources.list.d + +# update and upgrade +RUN apt update && apt upgrade -y + +# install essentialls +RUN apt update && \ + apt install -y \ + man make build-essential git zsh vim curl wget procps gnupg gnupg2 ca-certificates zip \ + software-properties-common + +# unminimize the system +RUN bash -c "yes | unminimize" + +# create dev sudo user +RUN useradd --create-home dev && \ + usermod --append --groups sudo dev && \ + apt update && apt install -y sudo && \ + echo '%sudo ALL=(ALL) NOPASSWD:ALL' >> /etc/sudoers + +# build riscv toolchain +RUN sudo apt-get install -y \ + autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk \ + build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev && \ + cd /tmp && \ + git clone --recursive https://github.com/riscv/riscv-gnu-toolchain.git && \ + git clone --recursive https://github.com/riscv/riscv-opcodes.git && \ + cd riscv-gnu-toolchain && \ + ./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi=ilp32 && \ + sudo make + +# main image stage +FROM public.ecr.aws/lts/ubuntu:22.04_stable + +ARG DEBIAN_FRONTEND=noninteractive +ARG KEYRING_PATH=/usr/share/keyrings +ARG APT_SOURCES_PATH=/etc/apt/sources.list.d + +# update and upgrade +RUN apt update && apt upgrade -y + +# install essentialls +RUN apt update && \ + apt install -y \ + man make build-essential git zsh vim curl wget procps gnupg gnupg2 ca-certificates zip \ + software-properties-common + +# unminimize the system +RUN bash -c "yes | unminimize" + +# create dev sudo user +RUN useradd --create-home dev && \ + usermod --append --groups sudo dev && \ + apt update && apt install -y sudo && \ + echo '%sudo ALL=(ALL) NOPASSWD:ALL' >> /etc/sudoers + +# get toolchain artifacts from builder stage +COPY --from=builder /opt/riscv /opt/riscv +ENV PATH="/opt/riscv/bin:${PATH}" + +USER dev diff --git a/envs/de1-soc/memory_map.sv b/envs/de1-soc/memory_map.sv index ab7a872..cd4ee73 100644 --- a/envs/de1-soc/memory_map.sv +++ b/envs/de1-soc/memory_map.sv @@ -7,6 +7,8 @@ module memory_map #( parameter SIZE = 1024 ) , input data_t write_data , input logic [3:0] write_enable , output data_t read_data + , input logic [31:0] dbg_regs [0:31] + , input addr_t dbg_pc , output reg [9:0] LEDR ); @@ -26,36 +28,45 @@ module memory_map #( parameter SIZE = 1024 ) $readmemh("poc/poc3.mem", M3); end `endif + reg [31:0] mem_rdata; - reg [31:0] M [0:SIZE - 1]; - reg [31:0] mem_rdata; + localparam bit [31:0] LEDR_ADDRESS = 32'h1000_0000; + localparam bit [31:0] DBG_REG_BASE = 32'h2000_0000; // x0..x31 + localparam bit [31:0] DBG_PC_ADDR = 32'h2000_0080; // to see where is the current pc - localparam bit [31:0] LEDR_ADDRESS = 32'h10000000; + localparam int ADDR_LSB = 2; + localparam int ADDR_WIDTH = $clog2(SIZE); + wire [ADDR_WIDTH - 1 : 0] mem_index = address[ADDR_LSB + ADDR_WIDTH - 1 : ADDR_LSB]; - localparam int ADDR_LSB = 2; - localparam int ADDR_WIDTH = $clog2(SIZE); - wire [ADDR_WIDTH - 1:0] mem_index = address[ADDR_LSB + ADDR_WIDTH - 1 : ADDR_LSB]; // I think this way may save some resources + wire dbg_reg_hit = (address[31:12] == DBG_REG_BASE[31:12]) && (address[11:7] == 5'd0); //between REG_BASE and use only 31 words + wire [4:0] dbg_reg_idx = address[6:2]; - always @(*) begin - case (address) - LEDR_ADDRESS: read_data = {22'b0, LEDR}; - default: read_data = mem_rdata; - endcase - end + always @(*) begin + case (address) + LEDR_ADDRESS: read_data = {22'b0, LEDR}; + DBG_PC_ADDR: read_data = dbg_pc; + default: begin + if (dbg_reg_hit && (dbg_reg_idx < 5'd32)) read_data = dbg_regs[dbg_reg_idx]; + else read_data = mem_rdata; + end + endcase + end - always @(posedge clk) begin - mem_rdata <= { M3[mem_index], M2[mem_index], M1[mem_index], M0[mem_index] }; - case (address) - LEDR_ADDRESS: begin - if (|write_enable) LEDR <= write_data[9:0]; - end - default: begin - if (write_enable[0]) M0[mem_index] <= write_data[7:0]; - if (write_enable[1]) M1[mem_index] <= write_data[15:8]; - if (write_enable[2]) M2[mem_index] <= write_data[23:16]; - if (write_enable[3]) M3[mem_index] <= write_data[31:24]; - end - endcase - end + always @(posedge clk) begin + mem_rdata <= { M3[mem_index], M2[mem_index], M1[mem_index], M0[mem_index] }; + + case (address) + LEDR_ADDRESS: begin + if (|write_enable) LEDR <= write_data[9:0]; + end + + default: begin + if (write_enable[0]) M0[mem_index] <= write_data[7:0]; + if (write_enable[1]) M1[mem_index] <= write_data[15:8]; + if (write_enable[2]) M2[mem_index] <= write_data[23:16]; + if (write_enable[3]) M3[mem_index] <= write_data[31:24]; + end + endcase + end endmodule diff --git a/envs/de1-soc/memory_map.sv.bak b/envs/de1-soc/memory_map.sv.bak new file mode 100644 index 0000000..f34dc5d --- /dev/null +++ b/envs/de1-soc/memory_map.sv.bak @@ -0,0 +1,44 @@ +`include "src/types.svh" + +module memory_map #( parameter SIZE = 1024 ) + ( input wire clk + + , input addr_t address + , input data_t write_data + , input logic [3:0] write_enable + , output data_t read_data + + , output reg [9:0] LEDR + ); + + reg [31:0] M[0:SIZE -1]; + + // need to run make in the poc directory before this command can succeed + initial $readmemh("poc/poc.mem", M); + + localparam bit [31:0] LEDR_ADDRESS = 32'h10000000; + + wire [31:0] mem_index = address[31:2] % SIZE; + + always @(*) begin + case (address) + LEDR_ADDRESS: read_data = {22'b0, LEDR}; + default: read_data = M[mem_index]; + endcase + end + + always @(posedge clk) begin + case (address) + LEDR_ADDRESS: begin + if (|write_enable) LEDR <= write_data[9:0]; + end + default: begin + // this is not compliant with our write_enable mechanism, and essentially breaks the + // sub-word writing instructions (e.g. sb); however i could not get the per-byte writes on + // de1-soc for some reason + if (|write_enable) M[mem_index] <= write_data; + end + endcase + end + +endmodule diff --git a/envs/de1-soc/poc/poc.c b/envs/de1-soc/poc/poc.c index 9a11d43..f0d8e5f 100644 --- a/envs/de1-soc/poc/poc.c +++ b/envs/de1-soc/poc/poc.c @@ -13,4 +13,4 @@ int main(void) { } return 0; -} \ No newline at end of file +} diff --git a/envs/de1-soc/poc/poc.mem.bak b/envs/de1-soc/poc/poc.mem.bak new file mode 100644 index 0000000..754079e --- /dev/null +++ b/envs/de1-soc/poc/poc.mem.bak @@ -0,0 +1,6 @@ +@00000000 +FE010113 00112E23 00812C23 02010413 +FE042623 FEC42783 02A78793 FEF42623 +FEC42783 01678793 FEF42623 100007B7 +FEC42703 00E7A023 00000793 00078513 +01C12083 01812403 02010113 00008067 diff --git a/envs/de1-soc/poc/poc0.mem b/envs/de1-soc/poc/poc0.mem new file mode 100644 index 0000000..8579aa8 --- /dev/null +++ b/envs/de1-soc/poc/poc0.mem @@ -0,0 +1,20 @@ +13 +23 +23 +23 +13 +93 +93 +93 +B7 +23 +23 +6F +83 +93 +23 +03 +B7 +93 +E3 +6F diff --git a/envs/de1-soc/poc/poc0.mem.bak b/envs/de1-soc/poc/poc0.mem.bak new file mode 100644 index 0000000..6bf14ac --- /dev/null +++ b/envs/de1-soc/poc/poc0.mem.bak @@ -0,0 +1,6 @@ +@00000000 +FE010113 00112E23 00812C23 02010413 +FE042623 FEC42783 02A78793 FEF42623 +FEC42783 01678793 FEF42623 100007B7 +FEC42703 00E7A023 00000793 00078513 +01C12083 01812403 02010113 00008067 \ No newline at end of file diff --git a/envs/de1-soc/poc/poc1.mem b/envs/de1-soc/poc/poc1.mem new file mode 100644 index 0000000..7ebeb94 --- /dev/null +++ b/envs/de1-soc/poc/poc1.mem @@ -0,0 +1,20 @@ +01 +2E +2C +2A +04 +04 +87 +F4 +07 +A0 +26 +00 +27 +87 +26 +27 +47 +87 +D4 +F0 diff --git a/envs/de1-soc/poc/poc1.mem.bak b/envs/de1-soc/poc/poc1.mem.bak new file mode 100644 index 0000000..6bf14ac --- /dev/null +++ b/envs/de1-soc/poc/poc1.mem.bak @@ -0,0 +1,6 @@ +@00000000 +FE010113 00112E23 00812C23 02010413 +FE042623 FEC42783 02A78793 FEF42623 +FEC42783 01678793 FEF42623 100007B7 +FEC42703 00E7A023 00000793 00078513 +01C12083 01812403 02010113 00008067 \ No newline at end of file diff --git a/envs/de1-soc/poc/poc2.mem b/envs/de1-soc/poc/poc2.mem new file mode 100644 index 0000000..8ac56c2 --- /dev/null +++ b/envs/de1-soc/poc/poc2.mem @@ -0,0 +1,20 @@ +01 +11 +81 +91 +01 +00 +14 +F7 +00 +97 +04 +00 +C4 +17 +F4 +C4 +0F +F7 +E7 +DF diff --git a/envs/de1-soc/poc/poc2.mem.bak b/envs/de1-soc/poc/poc2.mem.bak new file mode 100644 index 0000000..6bf14ac --- /dev/null +++ b/envs/de1-soc/poc/poc2.mem.bak @@ -0,0 +1,6 @@ +@00000000 +FE010113 00112E23 00812C23 02010413 +FE042623 FEC42783 02A78793 FEF42623 +FEC42783 01678793 FEF42623 100007B7 +FEC42703 00E7A023 00000793 00078513 +01C12083 01812403 02010113 00008067 \ No newline at end of file diff --git a/envs/de1-soc/poc/poc3.mem b/envs/de1-soc/poc/poc3.mem new file mode 100644 index 0000000..7c29bd2 --- /dev/null +++ b/envs/de1-soc/poc/poc3.mem @@ -0,0 +1,20 @@ +FE +00 +00 +00 +02 +00 +00 +3F +10 +00 +FE +01 +FE +00 +FE +FE +00 +23 +FE +FC diff --git a/envs/de1-soc/poc/poc3.mem.bak b/envs/de1-soc/poc/poc3.mem.bak new file mode 100644 index 0000000..6bf14ac --- /dev/null +++ b/envs/de1-soc/poc/poc3.mem.bak @@ -0,0 +1,6 @@ +@00000000 +FE010113 00112E23 00812C23 02010413 +FE042623 FEC42783 02A78793 FEF42623 +FEC42783 01678793 FEF42623 100007B7 +FEC42703 00E7A023 00000793 00078513 +01C12083 01812403 02010113 00008067 \ No newline at end of file diff --git a/envs/de1-soc/quartus/output_files/utoss-risc-v.cdf b/envs/de1-soc/quartus/output_files/utoss-risc-v.cdf old mode 100755 new mode 100644 index 0e81c83..82fc8c6 --- a/envs/de1-soc/quartus/output_files/utoss-risc-v.cdf +++ b/envs/de1-soc/quartus/output_files/utoss-risc-v.cdf @@ -1,15 +1,15 @@ -/* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ -JedecChain; - FileRevision(JESD32A); - DefaultMfr(6E); - - P ActionCode(Ign) - Device PartName(SOCVHPS) MfrSpec(OpMask(0)); - P ActionCode(Cfg) - Device PartName(5CSEMA5F31) Path("./") File("utoss-risc-v.sof") MfrSpec(OpMask(1)); - -ChainEnd; - -AlteraBegin; - ChainType(JTAG); -AlteraEnd; +/* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Ign) + Device PartName(SOCVHPS) MfrSpec(OpMask(0)); + P ActionCode(Cfg) + Device PartName(5CSEMA5F31) Path("./") File("utoss-risc-v.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/envs/de1-soc/quartus/top.sdc b/envs/de1-soc/quartus/top.sdc new file mode 100644 index 0000000..4a729e9 --- /dev/null +++ b/envs/de1-soc/quartus/top.sdc @@ -0,0 +1,19 @@ +# Timing constraints for UTOSS RISC-V processor + +# Create base clock constraint for 50MHz input +create_clock -name {CLOCK_50} -period 20.000 [get_ports {CLOCK_50}] + +set_false_path -from [get_ports KEY[0]] +set_false_path -to [get_ports KEY[0]] + +set_false_path -from [get_ports LEDR] +set_false_path -to [get_ports LEDR] + +# Set input/output delays relative to the 5MHz clock +# Assume external signals are synchronized to the 5MHz domain +#set_input_delay -clock {clk_5mhz} -max 50.0 [get_ports {KEY[*]}] +#set_input_delay -clock {clk_5mhz} -min 10.0 [get_ports {KEY[*]}] + +#set_output_delay -clock {clk_5mhz} -max 50.0 [get_ports {LEDR[*]}] +#set_output_delay -clock {clk_5mhz} -min -10.0 [get_ports {LEDR[*]}] + diff --git a/envs/de1-soc/quartus/utoss-risc-v.qpf b/envs/de1-soc/quartus/utoss-risc-v.qpf old mode 100755 new mode 100644 index 17b246a..8b1bb92 --- a/envs/de1-soc/quartus/utoss-risc-v.qpf +++ b/envs/de1-soc/quartus/utoss-risc-v.qpf @@ -1,30 +1,30 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2018 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition -# Date created = 23:32:36 October 29, 2025 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "18.1" -DATE = "23:32:36 October 29, 2025" - -# Revisions - -PROJECT_REVISION = "utoss-risc-v" +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 23:32:36 October 29, 2025 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "23:32:36 October 29, 2025" + +# Revisions + +PROJECT_REVISION = "utoss-risc-v" diff --git a/envs/de1-soc/quartus/utoss-risc-v.qsf b/envs/de1-soc/quartus/utoss-risc-v.qsf old mode 100755 new mode 100644 index ff1a451..08808d6 --- a/envs/de1-soc/quartus/utoss-risc-v.qsf +++ b/envs/de1-soc/quartus/utoss-risc-v.qsf @@ -1,331 +1,331 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2018 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition -# Date created = 23:32:36 October 29, 2025 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# utoss-risc-v_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus Prime software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSEMA5F31C6 -set_global_assignment -name TOP_LEVEL_ENTITY top -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:32:36 OCTOBER 29, 2025" -set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name SEARCH_PATH ../../../ -set_global_assignment -name VERILOG_MACRO UTOSS_RISCV_SYNTHESIS - -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_location_assignment PIN_AJ4 -to ADC_CS_N -set_location_assignment PIN_AK4 -to ADC_DIN -set_location_assignment PIN_AK3 -to ADC_DOUT -set_location_assignment PIN_AK2 -to ADC_SCLK -set_location_assignment PIN_K7 -to AUD_ADCDAT -set_location_assignment PIN_K8 -to AUD_ADCLRCK -set_location_assignment PIN_H7 -to AUD_BCLK -set_location_assignment PIN_J7 -to AUD_DACDAT -set_location_assignment PIN_H8 -to AUD_DACLRCK -set_location_assignment PIN_G7 -to AUD_XCK -set_location_assignment PIN_AF14 -to CLOCK_50 -set_location_assignment PIN_AA16 -to CLOCK2_50 -set_location_assignment PIN_Y26 -to CLOCK3_50 -set_location_assignment PIN_K14 -to CLOCK4_50 -set_location_assignment PIN_AK14 -to DRAM_ADDR[0] -set_location_assignment PIN_AH14 -to DRAM_ADDR[1] -set_location_assignment PIN_AG15 -to DRAM_ADDR[2] -set_location_assignment PIN_AE14 -to DRAM_ADDR[3] -set_location_assignment PIN_AB15 -to DRAM_ADDR[4] -set_location_assignment PIN_AC14 -to DRAM_ADDR[5] -set_location_assignment PIN_AD14 -to DRAM_ADDR[6] -set_location_assignment PIN_AF15 -to DRAM_ADDR[7] -set_location_assignment PIN_AH15 -to DRAM_ADDR[8] -set_location_assignment PIN_AG13 -to DRAM_ADDR[9] -set_location_assignment PIN_AG12 -to DRAM_ADDR[10] -set_location_assignment PIN_AH13 -to DRAM_ADDR[11] -set_location_assignment PIN_AJ14 -to DRAM_ADDR[12] -set_location_assignment PIN_AF13 -to DRAM_BA[0] -set_location_assignment PIN_AJ12 -to DRAM_BA[1] -set_location_assignment PIN_AF11 -to DRAM_CAS_N -set_location_assignment PIN_AK13 -to DRAM_CKE -set_location_assignment PIN_AH12 -to DRAM_CLK -set_location_assignment PIN_AG11 -to DRAM_CS_N -set_location_assignment PIN_AK6 -to DRAM_DQ[0] -set_location_assignment PIN_AJ7 -to DRAM_DQ[1] -set_location_assignment PIN_AK7 -to DRAM_DQ[2] -set_location_assignment PIN_AK8 -to DRAM_DQ[3] -set_location_assignment PIN_AK9 -to DRAM_DQ[4] -set_location_assignment PIN_AG10 -to DRAM_DQ[5] -set_location_assignment PIN_AK11 -to DRAM_DQ[6] -set_location_assignment PIN_AJ11 -to DRAM_DQ[7] -set_location_assignment PIN_AH10 -to DRAM_DQ[8] -set_location_assignment PIN_AJ10 -to DRAM_DQ[9] -set_location_assignment PIN_AJ9 -to DRAM_DQ[10] -set_location_assignment PIN_AH9 -to DRAM_DQ[11] -set_location_assignment PIN_AH8 -to DRAM_DQ[12] -set_location_assignment PIN_AH7 -to DRAM_DQ[13] -set_location_assignment PIN_AJ6 -to DRAM_DQ[14] -set_location_assignment PIN_AJ5 -to DRAM_DQ[15] -set_location_assignment PIN_AB13 -to DRAM_LDQM -set_location_assignment PIN_AE13 -to DRAM_RAS_N -set_location_assignment PIN_AK12 -to DRAM_UDQM -set_location_assignment PIN_AA13 -to DRAM_WE_N -set_location_assignment PIN_AA12 -to FAN_CTRL -set_location_assignment PIN_J12 -to FPGA_I2C_SCLK -set_location_assignment PIN_K12 -to FPGA_I2C_SDAT -set_location_assignment PIN_AC18 -to GPIO_0[0] -set_location_assignment PIN_AH18 -to GPIO_0[10] -set_location_assignment PIN_AH17 -to GPIO_0[11] -set_location_assignment PIN_AG16 -to GPIO_0[12] -set_location_assignment PIN_AE16 -to GPIO_0[13] -set_location_assignment PIN_AF16 -to GPIO_0[14] -set_location_assignment PIN_AG17 -to GPIO_0[15] -set_location_assignment PIN_AA18 -to GPIO_0[16] -set_location_assignment PIN_AA19 -to GPIO_0[17] -set_location_assignment PIN_AE17 -to GPIO_0[18] -set_location_assignment PIN_AC20 -to GPIO_0[19] -set_location_assignment PIN_Y17 -to GPIO_0[1] -set_location_assignment PIN_AH19 -to GPIO_0[20] -set_location_assignment PIN_AJ20 -to GPIO_0[21] -set_location_assignment PIN_AH20 -to GPIO_0[22] -set_location_assignment PIN_AK21 -to GPIO_0[23] -set_location_assignment PIN_AD19 -to GPIO_0[24] -set_location_assignment PIN_AD20 -to GPIO_0[25] -set_location_assignment PIN_AE18 -to GPIO_0[26] -set_location_assignment PIN_AE19 -to GPIO_0[27] -set_location_assignment PIN_AF20 -to GPIO_0[28] -set_location_assignment PIN_AF21 -to GPIO_0[29] -set_location_assignment PIN_AD17 -to GPIO_0[2] -set_location_assignment PIN_AF19 -to GPIO_0[30] -set_location_assignment PIN_AG21 -to GPIO_0[31] -set_location_assignment PIN_AF18 -to GPIO_0[32] -set_location_assignment PIN_AG20 -to GPIO_0[33] -set_location_assignment PIN_AG18 -to GPIO_0[34] -set_location_assignment PIN_AJ21 -to GPIO_0[35] -set_location_assignment PIN_Y18 -to GPIO_0[3] -set_location_assignment PIN_AK16 -to GPIO_0[4] -set_location_assignment PIN_AK18 -to GPIO_0[5] -set_location_assignment PIN_AK19 -to GPIO_0[6] -set_location_assignment PIN_AJ19 -to GPIO_0[7] -set_location_assignment PIN_AJ17 -to GPIO_0[8] -set_location_assignment PIN_AJ16 -to GPIO_0[9] -set_location_assignment PIN_AB17 -to GPIO_1[0] -set_location_assignment PIN_AG26 -to GPIO_1[10] -set_location_assignment PIN_AH24 -to GPIO_1[11] -set_location_assignment PIN_AH27 -to GPIO_1[12] -set_location_assignment PIN_AJ27 -to GPIO_1[13] -set_location_assignment PIN_AK29 -to GPIO_1[14] -set_location_assignment PIN_AK28 -to GPIO_1[15] -set_location_assignment PIN_AK27 -to GPIO_1[16] -set_location_assignment PIN_AJ26 -to GPIO_1[17] -set_location_assignment PIN_AK26 -to GPIO_1[18] -set_location_assignment PIN_AH25 -to GPIO_1[19] -set_location_assignment PIN_AA21 -to GPIO_1[1] -set_location_assignment PIN_AJ25 -to GPIO_1[20] -set_location_assignment PIN_AJ24 -to GPIO_1[21] -set_location_assignment PIN_AK24 -to GPIO_1[22] -set_location_assignment PIN_AG23 -to GPIO_1[23] -set_location_assignment PIN_AK23 -to GPIO_1[24] -set_location_assignment PIN_AH23 -to GPIO_1[25] -set_location_assignment PIN_AK22 -to GPIO_1[26] -set_location_assignment PIN_AJ22 -to GPIO_1[27] -set_location_assignment PIN_AH22 -to GPIO_1[28] -set_location_assignment PIN_AG22 -to GPIO_1[29] -set_location_assignment PIN_AB21 -to GPIO_1[2] -set_location_assignment PIN_AF24 -to GPIO_1[30] -set_location_assignment PIN_AF23 -to GPIO_1[31] -set_location_assignment PIN_AE22 -to GPIO_1[32] -set_location_assignment PIN_AD21 -to GPIO_1[33] -set_location_assignment PIN_AA20 -to GPIO_1[34] -set_location_assignment PIN_AC22 -to GPIO_1[35] -set_location_assignment PIN_AC23 -to GPIO_1[3] -set_location_assignment PIN_AD24 -to GPIO_1[4] -set_location_assignment PIN_AE23 -to GPIO_1[5] -set_location_assignment PIN_AE24 -to GPIO_1[6] -set_location_assignment PIN_AF25 -to GPIO_1[7] -set_location_assignment PIN_AF26 -to GPIO_1[8] -set_location_assignment PIN_AG25 -to GPIO_1[9] -set_location_assignment PIN_AE26 -to HEX0[0] -set_location_assignment PIN_AE27 -to HEX0[1] -set_location_assignment PIN_AE28 -to HEX0[2] -set_location_assignment PIN_AG27 -to HEX0[3] -set_location_assignment PIN_AF28 -to HEX0[4] -set_location_assignment PIN_AG28 -to HEX0[5] -set_location_assignment PIN_AH28 -to HEX0[6] -set_location_assignment PIN_AJ29 -to HEX1[0] -set_location_assignment PIN_AH29 -to HEX1[1] -set_location_assignment PIN_AH30 -to HEX1[2] -set_location_assignment PIN_AG30 -to HEX1[3] -set_location_assignment PIN_AF29 -to HEX1[4] -set_location_assignment PIN_AF30 -to HEX1[5] -set_location_assignment PIN_AD27 -to HEX1[6] -set_location_assignment PIN_AB23 -to HEX2[0] -set_location_assignment PIN_AE29 -to HEX2[1] -set_location_assignment PIN_AD29 -to HEX2[2] -set_location_assignment PIN_AC28 -to HEX2[3] -set_location_assignment PIN_AD30 -to HEX2[4] -set_location_assignment PIN_AC29 -to HEX2[5] -set_location_assignment PIN_AC30 -to HEX2[6] -set_location_assignment PIN_AD26 -to HEX3[0] -set_location_assignment PIN_AC27 -to HEX3[1] -set_location_assignment PIN_AD25 -to HEX3[2] -set_location_assignment PIN_AC25 -to HEX3[3] -set_location_assignment PIN_AB28 -to HEX3[4] -set_location_assignment PIN_AB25 -to HEX3[5] -set_location_assignment PIN_AB22 -to HEX3[6] -set_location_assignment PIN_AA24 -to HEX4[0] -set_location_assignment PIN_Y23 -to HEX4[1] -set_location_assignment PIN_Y24 -to HEX4[2] -set_location_assignment PIN_W22 -to HEX4[3] -set_location_assignment PIN_W24 -to HEX4[4] -set_location_assignment PIN_V23 -to HEX4[5] -set_location_assignment PIN_W25 -to HEX4[6] -set_location_assignment PIN_V25 -to HEX5[0] -set_location_assignment PIN_AA28 -to HEX5[1] -set_location_assignment PIN_Y27 -to HEX5[2] -set_location_assignment PIN_AB27 -to HEX5[3] -set_location_assignment PIN_AB26 -to HEX5[4] -set_location_assignment PIN_AA26 -to HEX5[5] -set_location_assignment PIN_AA25 -to HEX5[6] -set_location_assignment PIN_AA30 -to IRDA_RXD -set_location_assignment PIN_AB30 -to IRDA_TXD -set_location_assignment PIN_AA14 -to KEY[0] -set_location_assignment PIN_AA15 -to KEY[1] -set_location_assignment PIN_W15 -to KEY[2] -set_location_assignment PIN_Y16 -to KEY[3] -set_location_assignment PIN_V16 -to LEDR[0] -set_location_assignment PIN_W16 -to LEDR[1] -set_location_assignment PIN_V17 -to LEDR[2] -set_location_assignment PIN_V18 -to LEDR[3] -set_location_assignment PIN_W17 -to LEDR[4] -set_location_assignment PIN_W19 -to LEDR[5] -set_location_assignment PIN_Y19 -to LEDR[6] -set_location_assignment PIN_W20 -to LEDR[7] -set_location_assignment PIN_W21 -to LEDR[8] -set_location_assignment PIN_Y21 -to LEDR[9] -set_location_assignment PIN_AD7 -to PS2_CLK -set_location_assignment PIN_AE7 -to PS2_DAT -set_location_assignment PIN_AD9 -to PS2_CLK2 -set_location_assignment PIN_AE9 -to PS2_DAT2 -set_location_assignment PIN_AB12 -to SW[0] -set_location_assignment PIN_AC12 -to SW[1] -set_location_assignment PIN_AF9 -to SW[2] -set_location_assignment PIN_AF10 -to SW[3] -set_location_assignment PIN_AD11 -to SW[4] -set_location_assignment PIN_AD12 -to SW[5] -set_location_assignment PIN_AE11 -to SW[6] -set_location_assignment PIN_AC9 -to SW[7] -set_location_assignment PIN_AD10 -to SW[8] -set_location_assignment PIN_AE12 -to SW[9] -set_location_assignment PIN_H15 -to TD_CLK27 -set_location_assignment PIN_D2 -to TD_DATA[0] -set_location_assignment PIN_B1 -to TD_DATA[1] -set_location_assignment PIN_E2 -to TD_DATA[2] -set_location_assignment PIN_B2 -to TD_DATA[3] -set_location_assignment PIN_D1 -to TD_DATA[4] -set_location_assignment PIN_E1 -to TD_DATA[5] -set_location_assignment PIN_C2 -to TD_DATA[6] -set_location_assignment PIN_B3 -to TD_DATA[7] -set_location_assignment PIN_A5 -to TD_HS -set_location_assignment PIN_F6 -to TD_RESET_N -set_location_assignment PIN_A3 -to TD_VS -set_location_assignment PIN_AF4 -to USB_B2_CLK -set_location_assignment PIN_AH4 -to USB_B2_DATA[0] -set_location_assignment PIN_AH3 -to USB_B2_DATA[1] -set_location_assignment PIN_AJ2 -to USB_B2_DATA[2] -set_location_assignment PIN_AJ1 -to USB_B2_DATA[3] -set_location_assignment PIN_AH2 -to USB_B2_DATA[4] -set_location_assignment PIN_AG3 -to USB_B2_DATA[5] -set_location_assignment PIN_AG2 -to USB_B2_DATA[6] -set_location_assignment PIN_AG1 -to USB_B2_DATA[7] -set_location_assignment PIN_AF5 -to USB_EMPTY -set_location_assignment PIN_AG5 -to USB_FULL -set_location_assignment PIN_AF6 -to USB_OE_N -set_location_assignment PIN_AG6 -to USB_RD_N -set_location_assignment PIN_AG7 -to USB_RESET_N -set_location_assignment PIN_AG8 -to USB_SCL -set_location_assignment PIN_AF8 -to USB_SDA -set_location_assignment PIN_AH5 -to USB_WR_N -set_location_assignment PIN_B13 -to VGA_B[0] -set_location_assignment PIN_G13 -to VGA_B[1] -set_location_assignment PIN_H13 -to VGA_B[2] -set_location_assignment PIN_F14 -to VGA_B[3] -set_location_assignment PIN_H14 -to VGA_B[4] -set_location_assignment PIN_F15 -to VGA_B[5] -set_location_assignment PIN_G15 -to VGA_B[6] -set_location_assignment PIN_J14 -to VGA_B[7] -set_location_assignment PIN_F10 -to VGA_BLANK_N -set_location_assignment PIN_A11 -to VGA_CLK -set_location_assignment PIN_J9 -to VGA_G[0] -set_location_assignment PIN_J10 -to VGA_G[1] -set_location_assignment PIN_H12 -to VGA_G[2] -set_location_assignment PIN_G10 -to VGA_G[3] -set_location_assignment PIN_G11 -to VGA_G[4] -set_location_assignment PIN_G12 -to VGA_G[5] -set_location_assignment PIN_F11 -to VGA_G[6] -set_location_assignment PIN_E11 -to VGA_G[7] -set_location_assignment PIN_B11 -to VGA_HS -set_location_assignment PIN_A13 -to VGA_R[0] -set_location_assignment PIN_C13 -to VGA_R[1] -set_location_assignment PIN_E13 -to VGA_R[2] -set_location_assignment PIN_B12 -to VGA_R[3] -set_location_assignment PIN_C12 -to VGA_R[4] -set_location_assignment PIN_D12 -to VGA_R[5] -set_location_assignment PIN_E12 -to VGA_R[6] -set_location_assignment PIN_F13 -to VGA_R[7] -set_location_assignment PIN_C10 -to VGA_SYNC_N -set_location_assignment PIN_D11 -to VGA_VS - -set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/Logger.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/utils.svh -set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/types.svh -set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/params.svh -set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/ALU_ALUdecoder/ALUdecoder.sv -set_global_assignment -name VERILOG_FILE ../../../src/ALU_ALUdecoder/ALU.v -set_global_assignment -name VERILOG_FILE ../../../src/Instruction_Decode/RegisterFile.v -set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/Instruction_Decode/MemoryLoader.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/Instruction_Decode/Instruction_Decode.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/utoss_riscv.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/fetch.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/ControlFSM.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../top.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../memory_map.sv -set_global_assignment -name SDC_FILE "utoss-risc-v.sdc" +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 23:32:36 October 29, 2025 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# utoss-risc-v_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA5F31C6 +set_global_assignment -name TOP_LEVEL_ENTITY top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:32:36 OCTOBER 29, 2025" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name SEARCH_PATH ../../../ +set_global_assignment -name VERILOG_MACRO UTOSS_RISCV_SYNTHESIS + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_AJ4 -to ADC_CS_N +set_location_assignment PIN_AK4 -to ADC_DIN +set_location_assignment PIN_AK3 -to ADC_DOUT +set_location_assignment PIN_AK2 -to ADC_SCLK +set_location_assignment PIN_K7 -to AUD_ADCDAT +set_location_assignment PIN_K8 -to AUD_ADCLRCK +set_location_assignment PIN_H7 -to AUD_BCLK +set_location_assignment PIN_J7 -to AUD_DACDAT +set_location_assignment PIN_H8 -to AUD_DACLRCK +set_location_assignment PIN_G7 -to AUD_XCK +set_location_assignment PIN_AF14 -to CLOCK_50 +set_location_assignment PIN_AA16 -to CLOCK2_50 +set_location_assignment PIN_Y26 -to CLOCK3_50 +set_location_assignment PIN_K14 -to CLOCK4_50 +set_location_assignment PIN_AK14 -to DRAM_ADDR[0] +set_location_assignment PIN_AH14 -to DRAM_ADDR[1] +set_location_assignment PIN_AG15 -to DRAM_ADDR[2] +set_location_assignment PIN_AE14 -to DRAM_ADDR[3] +set_location_assignment PIN_AB15 -to DRAM_ADDR[4] +set_location_assignment PIN_AC14 -to DRAM_ADDR[5] +set_location_assignment PIN_AD14 -to DRAM_ADDR[6] +set_location_assignment PIN_AF15 -to DRAM_ADDR[7] +set_location_assignment PIN_AH15 -to DRAM_ADDR[8] +set_location_assignment PIN_AG13 -to DRAM_ADDR[9] +set_location_assignment PIN_AG12 -to DRAM_ADDR[10] +set_location_assignment PIN_AH13 -to DRAM_ADDR[11] +set_location_assignment PIN_AJ14 -to DRAM_ADDR[12] +set_location_assignment PIN_AF13 -to DRAM_BA[0] +set_location_assignment PIN_AJ12 -to DRAM_BA[1] +set_location_assignment PIN_AF11 -to DRAM_CAS_N +set_location_assignment PIN_AK13 -to DRAM_CKE +set_location_assignment PIN_AH12 -to DRAM_CLK +set_location_assignment PIN_AG11 -to DRAM_CS_N +set_location_assignment PIN_AK6 -to DRAM_DQ[0] +set_location_assignment PIN_AJ7 -to DRAM_DQ[1] +set_location_assignment PIN_AK7 -to DRAM_DQ[2] +set_location_assignment PIN_AK8 -to DRAM_DQ[3] +set_location_assignment PIN_AK9 -to DRAM_DQ[4] +set_location_assignment PIN_AG10 -to DRAM_DQ[5] +set_location_assignment PIN_AK11 -to DRAM_DQ[6] +set_location_assignment PIN_AJ11 -to DRAM_DQ[7] +set_location_assignment PIN_AH10 -to DRAM_DQ[8] +set_location_assignment PIN_AJ10 -to DRAM_DQ[9] +set_location_assignment PIN_AJ9 -to DRAM_DQ[10] +set_location_assignment PIN_AH9 -to DRAM_DQ[11] +set_location_assignment PIN_AH8 -to DRAM_DQ[12] +set_location_assignment PIN_AH7 -to DRAM_DQ[13] +set_location_assignment PIN_AJ6 -to DRAM_DQ[14] +set_location_assignment PIN_AJ5 -to DRAM_DQ[15] +set_location_assignment PIN_AB13 -to DRAM_LDQM +set_location_assignment PIN_AE13 -to DRAM_RAS_N +set_location_assignment PIN_AK12 -to DRAM_UDQM +set_location_assignment PIN_AA13 -to DRAM_WE_N +set_location_assignment PIN_AA12 -to FAN_CTRL +set_location_assignment PIN_J12 -to FPGA_I2C_SCLK +set_location_assignment PIN_K12 -to FPGA_I2C_SDAT +set_location_assignment PIN_AC18 -to GPIO_0[0] +set_location_assignment PIN_AH18 -to GPIO_0[10] +set_location_assignment PIN_AH17 -to GPIO_0[11] +set_location_assignment PIN_AG16 -to GPIO_0[12] +set_location_assignment PIN_AE16 -to GPIO_0[13] +set_location_assignment PIN_AF16 -to GPIO_0[14] +set_location_assignment PIN_AG17 -to GPIO_0[15] +set_location_assignment PIN_AA18 -to GPIO_0[16] +set_location_assignment PIN_AA19 -to GPIO_0[17] +set_location_assignment PIN_AE17 -to GPIO_0[18] +set_location_assignment PIN_AC20 -to GPIO_0[19] +set_location_assignment PIN_Y17 -to GPIO_0[1] +set_location_assignment PIN_AH19 -to GPIO_0[20] +set_location_assignment PIN_AJ20 -to GPIO_0[21] +set_location_assignment PIN_AH20 -to GPIO_0[22] +set_location_assignment PIN_AK21 -to GPIO_0[23] +set_location_assignment PIN_AD19 -to GPIO_0[24] +set_location_assignment PIN_AD20 -to GPIO_0[25] +set_location_assignment PIN_AE18 -to GPIO_0[26] +set_location_assignment PIN_AE19 -to GPIO_0[27] +set_location_assignment PIN_AF20 -to GPIO_0[28] +set_location_assignment PIN_AF21 -to GPIO_0[29] +set_location_assignment PIN_AD17 -to GPIO_0[2] +set_location_assignment PIN_AF19 -to GPIO_0[30] +set_location_assignment PIN_AG21 -to GPIO_0[31] +set_location_assignment PIN_AF18 -to GPIO_0[32] +set_location_assignment PIN_AG20 -to GPIO_0[33] +set_location_assignment PIN_AG18 -to GPIO_0[34] +set_location_assignment PIN_AJ21 -to GPIO_0[35] +set_location_assignment PIN_Y18 -to GPIO_0[3] +set_location_assignment PIN_AK16 -to GPIO_0[4] +set_location_assignment PIN_AK18 -to GPIO_0[5] +set_location_assignment PIN_AK19 -to GPIO_0[6] +set_location_assignment PIN_AJ19 -to GPIO_0[7] +set_location_assignment PIN_AJ17 -to GPIO_0[8] +set_location_assignment PIN_AJ16 -to GPIO_0[9] +set_location_assignment PIN_AB17 -to GPIO_1[0] +set_location_assignment PIN_AG26 -to GPIO_1[10] +set_location_assignment PIN_AH24 -to GPIO_1[11] +set_location_assignment PIN_AH27 -to GPIO_1[12] +set_location_assignment PIN_AJ27 -to GPIO_1[13] +set_location_assignment PIN_AK29 -to GPIO_1[14] +set_location_assignment PIN_AK28 -to GPIO_1[15] +set_location_assignment PIN_AK27 -to GPIO_1[16] +set_location_assignment PIN_AJ26 -to GPIO_1[17] +set_location_assignment PIN_AK26 -to GPIO_1[18] +set_location_assignment PIN_AH25 -to GPIO_1[19] +set_location_assignment PIN_AA21 -to GPIO_1[1] +set_location_assignment PIN_AJ25 -to GPIO_1[20] +set_location_assignment PIN_AJ24 -to GPIO_1[21] +set_location_assignment PIN_AK24 -to GPIO_1[22] +set_location_assignment PIN_AG23 -to GPIO_1[23] +set_location_assignment PIN_AK23 -to GPIO_1[24] +set_location_assignment PIN_AH23 -to GPIO_1[25] +set_location_assignment PIN_AK22 -to GPIO_1[26] +set_location_assignment PIN_AJ22 -to GPIO_1[27] +set_location_assignment PIN_AH22 -to GPIO_1[28] +set_location_assignment PIN_AG22 -to GPIO_1[29] +set_location_assignment PIN_AB21 -to GPIO_1[2] +set_location_assignment PIN_AF24 -to GPIO_1[30] +set_location_assignment PIN_AF23 -to GPIO_1[31] +set_location_assignment PIN_AE22 -to GPIO_1[32] +set_location_assignment PIN_AD21 -to GPIO_1[33] +set_location_assignment PIN_AA20 -to GPIO_1[34] +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AC23 -to GPIO_1[3] +set_location_assignment PIN_AD24 -to GPIO_1[4] +set_location_assignment PIN_AE23 -to GPIO_1[5] +set_location_assignment PIN_AE24 -to GPIO_1[6] +set_location_assignment PIN_AF25 -to GPIO_1[7] +set_location_assignment PIN_AF26 -to GPIO_1[8] +set_location_assignment PIN_AG25 -to GPIO_1[9] +set_location_assignment PIN_AE26 -to HEX0[0] +set_location_assignment PIN_AE27 -to HEX0[1] +set_location_assignment PIN_AE28 -to HEX0[2] +set_location_assignment PIN_AG27 -to HEX0[3] +set_location_assignment PIN_AF28 -to HEX0[4] +set_location_assignment PIN_AG28 -to HEX0[5] +set_location_assignment PIN_AH28 -to HEX0[6] +set_location_assignment PIN_AJ29 -to HEX1[0] +set_location_assignment PIN_AH29 -to HEX1[1] +set_location_assignment PIN_AH30 -to HEX1[2] +set_location_assignment PIN_AG30 -to HEX1[3] +set_location_assignment PIN_AF29 -to HEX1[4] +set_location_assignment PIN_AF30 -to HEX1[5] +set_location_assignment PIN_AD27 -to HEX1[6] +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_AE29 -to HEX2[1] +set_location_assignment PIN_AD29 -to HEX2[2] +set_location_assignment PIN_AC28 -to HEX2[3] +set_location_assignment PIN_AD30 -to HEX2[4] +set_location_assignment PIN_AC29 -to HEX2[5] +set_location_assignment PIN_AC30 -to HEX2[6] +set_location_assignment PIN_AD26 -to HEX3[0] +set_location_assignment PIN_AC27 -to HEX3[1] +set_location_assignment PIN_AD25 -to HEX3[2] +set_location_assignment PIN_AC25 -to HEX3[3] +set_location_assignment PIN_AB28 -to HEX3[4] +set_location_assignment PIN_AB25 -to HEX3[5] +set_location_assignment PIN_AB22 -to HEX3[6] +set_location_assignment PIN_AA24 -to HEX4[0] +set_location_assignment PIN_Y23 -to HEX4[1] +set_location_assignment PIN_Y24 -to HEX4[2] +set_location_assignment PIN_W22 -to HEX4[3] +set_location_assignment PIN_W24 -to HEX4[4] +set_location_assignment PIN_V23 -to HEX4[5] +set_location_assignment PIN_W25 -to HEX4[6] +set_location_assignment PIN_V25 -to HEX5[0] +set_location_assignment PIN_AA28 -to HEX5[1] +set_location_assignment PIN_Y27 -to HEX5[2] +set_location_assignment PIN_AB27 -to HEX5[3] +set_location_assignment PIN_AB26 -to HEX5[4] +set_location_assignment PIN_AA26 -to HEX5[5] +set_location_assignment PIN_AA25 -to HEX5[6] +set_location_assignment PIN_AA30 -to IRDA_RXD +set_location_assignment PIN_AB30 -to IRDA_TXD +set_location_assignment PIN_AA14 -to KEY[0] +set_location_assignment PIN_AA15 -to KEY[1] +set_location_assignment PIN_W15 -to KEY[2] +set_location_assignment PIN_Y16 -to KEY[3] +set_location_assignment PIN_V16 -to LEDR[0] +set_location_assignment PIN_W16 -to LEDR[1] +set_location_assignment PIN_V17 -to LEDR[2] +set_location_assignment PIN_V18 -to LEDR[3] +set_location_assignment PIN_W17 -to LEDR[4] +set_location_assignment PIN_W19 -to LEDR[5] +set_location_assignment PIN_Y19 -to LEDR[6] +set_location_assignment PIN_W20 -to LEDR[7] +set_location_assignment PIN_W21 -to LEDR[8] +set_location_assignment PIN_Y21 -to LEDR[9] +set_location_assignment PIN_AD7 -to PS2_CLK +set_location_assignment PIN_AE7 -to PS2_DAT +set_location_assignment PIN_AD9 -to PS2_CLK2 +set_location_assignment PIN_AE9 -to PS2_DAT2 +set_location_assignment PIN_AB12 -to SW[0] +set_location_assignment PIN_AC12 -to SW[1] +set_location_assignment PIN_AF9 -to SW[2] +set_location_assignment PIN_AF10 -to SW[3] +set_location_assignment PIN_AD11 -to SW[4] +set_location_assignment PIN_AD12 -to SW[5] +set_location_assignment PIN_AE11 -to SW[6] +set_location_assignment PIN_AC9 -to SW[7] +set_location_assignment PIN_AD10 -to SW[8] +set_location_assignment PIN_AE12 -to SW[9] +set_location_assignment PIN_H15 -to TD_CLK27 +set_location_assignment PIN_D2 -to TD_DATA[0] +set_location_assignment PIN_B1 -to TD_DATA[1] +set_location_assignment PIN_E2 -to TD_DATA[2] +set_location_assignment PIN_B2 -to TD_DATA[3] +set_location_assignment PIN_D1 -to TD_DATA[4] +set_location_assignment PIN_E1 -to TD_DATA[5] +set_location_assignment PIN_C2 -to TD_DATA[6] +set_location_assignment PIN_B3 -to TD_DATA[7] +set_location_assignment PIN_A5 -to TD_HS +set_location_assignment PIN_F6 -to TD_RESET_N +set_location_assignment PIN_A3 -to TD_VS +set_location_assignment PIN_AF4 -to USB_B2_CLK +set_location_assignment PIN_AH4 -to USB_B2_DATA[0] +set_location_assignment PIN_AH3 -to USB_B2_DATA[1] +set_location_assignment PIN_AJ2 -to USB_B2_DATA[2] +set_location_assignment PIN_AJ1 -to USB_B2_DATA[3] +set_location_assignment PIN_AH2 -to USB_B2_DATA[4] +set_location_assignment PIN_AG3 -to USB_B2_DATA[5] +set_location_assignment PIN_AG2 -to USB_B2_DATA[6] +set_location_assignment PIN_AG1 -to USB_B2_DATA[7] +set_location_assignment PIN_AF5 -to USB_EMPTY +set_location_assignment PIN_AG5 -to USB_FULL +set_location_assignment PIN_AF6 -to USB_OE_N +set_location_assignment PIN_AG6 -to USB_RD_N +set_location_assignment PIN_AG7 -to USB_RESET_N +set_location_assignment PIN_AG8 -to USB_SCL +set_location_assignment PIN_AF8 -to USB_SDA +set_location_assignment PIN_AH5 -to USB_WR_N +set_location_assignment PIN_B13 -to VGA_B[0] +set_location_assignment PIN_G13 -to VGA_B[1] +set_location_assignment PIN_H13 -to VGA_B[2] +set_location_assignment PIN_F14 -to VGA_B[3] +set_location_assignment PIN_H14 -to VGA_B[4] +set_location_assignment PIN_F15 -to VGA_B[5] +set_location_assignment PIN_G15 -to VGA_B[6] +set_location_assignment PIN_J14 -to VGA_B[7] +set_location_assignment PIN_F10 -to VGA_BLANK_N +set_location_assignment PIN_A11 -to VGA_CLK +set_location_assignment PIN_J9 -to VGA_G[0] +set_location_assignment PIN_J10 -to VGA_G[1] +set_location_assignment PIN_H12 -to VGA_G[2] +set_location_assignment PIN_G10 -to VGA_G[3] +set_location_assignment PIN_G11 -to VGA_G[4] +set_location_assignment PIN_G12 -to VGA_G[5] +set_location_assignment PIN_F11 -to VGA_G[6] +set_location_assignment PIN_E11 -to VGA_G[7] +set_location_assignment PIN_B11 -to VGA_HS +set_location_assignment PIN_A13 -to VGA_R[0] +set_location_assignment PIN_C13 -to VGA_R[1] +set_location_assignment PIN_E13 -to VGA_R[2] +set_location_assignment PIN_B12 -to VGA_R[3] +set_location_assignment PIN_C12 -to VGA_R[4] +set_location_assignment PIN_D12 -to VGA_R[5] +set_location_assignment PIN_E12 -to VGA_R[6] +set_location_assignment PIN_F13 -to VGA_R[7] +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_D11 -to VGA_VS + +set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/Logger.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/utils.svh +set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/types.svh +set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/params.svh +set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/ALU_ALUdecoder/ALUdecoder.sv +set_global_assignment -name VERILOG_FILE ../../../src/ALU_ALUdecoder/ALU.v +set_global_assignment -name VERILOG_FILE ../../../src/Instruction_Decode/RegisterFile.v +set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/Instruction_Decode/MemoryLoader.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/Instruction_Decode/Instruction_Decode.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/utoss_riscv.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/fetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../../../src/ControlFSM.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../top.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../memory_map.sv +set_global_assignment -name SDC_FILE "utoss-risc-v.sdc" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/envs/de1-soc/quartus/utoss-risc-v_description.txt b/envs/de1-soc/quartus/utoss-risc-v_description.txt old mode 100755 new mode 100644 diff --git a/envs/de1-soc/top.sv b/envs/de1-soc/top.sv index d5f222f..69c3c95 100644 --- a/envs/de1-soc/top.sv +++ b/envs/de1-soc/top.sv @@ -1,34 +1,110 @@ -module top - ( input wire CLOCK_50 - , input wire [3:0] KEY - , output wire [9:0] LEDR - ); - - addr_t memory__address; - data_t memory__write_data; - logic [3:0] memory__write_enable; - data_t memory__read_data; - - memory_map #( .SIZE ( 512 ) ) - memory_map - ( .clk ( CLOCK_50 ) - - , .address ( memory__address ) - , .write_data ( memory__write_data ) - , .write_enable ( memory__write_enable ) - , .read_data ( memory__read_data ) - - , .LEDR ( LEDR ) - ); - - utoss_riscv core - ( .clk ( CLOCK_50 ) - , .reset ( ~KEY[0] ) - - , .memory__address ( memory__address ) - , .memory__write_data ( memory__write_data ) - , .memory__write_enable ( memory__write_enable ) - , .memory__read_data ( memory__read_data ) +module top ( + input wire CLOCK_50 + , input wire [3:0] KEY + , output wire [9:0] LEDR + , input wire UART_TX + , output wire UART_RX // FPGA->PC (txd) +); + + wire rst = ~KEY[0]; + + wire [7:0] uart_rx_data; + wire uart_rx_valid; + wire uart_rx_ready; + + wire [7:0] uart_tx_data; + wire uart_tx_valid; + wire uart_tx_ready; + + wire tx_busy, rx_busy, rx_overrun, rx_frame; + + uart #( + .DATA_WIDTH(8) + , .CLK_HZ(50000000) + , .BAUD(115200) + ) + u_uart ( + .clk(CLOCK_50) + , .rst(rst) + , .i_data_s(uart_tx_data) + , .i_valid_s(uart_tx_valid) + , .o_ready_s(uart_tx_ready) + , .o_data_m(uart_rx_data) + , .o_valid_m(uart_rx_valid) + , .i_ready_m(uart_rx_ready) + , .i_rxd(UART_TX) + , .o_txd(UART_RX) + , .o_tx_busy(tx_busy) + , .o_rx_busy(rx_busy) + , .o_rx_overrun_error(rx_overrun) + , .o_rx_frame_error(rx_frame) + ); + + + logic [31:0] dbg_addr, dbg_write_data; + logic [3:0] dbg_write_enable; + wire [31:0] read_data; + + logic hold_core; + + uart_bus_master u_master ( + .clk(CLOCK_50) + , .rst(rst) + , .rx_data(uart_rx_data) + , .rx_valid(uart_rx_valid) + , .rx_ready(uart_rx_ready) + , .tx_data(uart_tx_data) + , .tx_valid(uart_tx_valid) + , .tx_ready(uart_tx_ready) + , .bus_addr(dbg_addr) + , .bus_write_data(dbg_write_data) + , .bus_write_enable(dbg_write_enable) + , .bus_read_data(read_data) + , .dbg_regs(dbg_regs) + , .dbg_pc(dbg_pc) + , .hold_core(hold_core) + ); + + addr_t core_addr; + data_t core_write_data; + logic [3:0] core_write_enable; + + logic [31:0] dbg_regs [0:31]; + addr_t dbg_pc; + + wire core_reset = rst | hold_core; + + addr_t bus_addr; + data_t bus_write_data; + logic [3:0] bus_write_enable; + + assign bus_addr = hold_core ? dbg_addr : core_addr; + assign bus_write_data = hold_core ? dbg_write_data : core_write_data; + assign bus_write_enable = hold_core ? dbg_write_enable : core_write_enable; + + memory_map #( + .SIZE(512) + ) + u_mem ( + .clk(CLOCK_50) + , .address(bus_addr) + , .write_data(bus_write_data) + , .write_enable(bus_write_enable) + , .read_data(read_data) + , .dbg_regs(dbg_regs) + , .dbg_pc(dbg_pc) + , .LEDR(LEDR) + ); + + utoss_riscv core ( + .clk(CLOCK_50) + , .reset(core_reset) + , .memory__address(core_addr) + , .memory__write_data(core_write_data) + , .memory__write_enable(core_write_enable) + , .memory__read_data(read_data) + , .dbg_regs(dbg_regs) + , .dbg_pc(dbg_pc) ); endmodule diff --git a/envs/de1-soc/top.sv.bak b/envs/de1-soc/top.sv.bak new file mode 100644 index 0000000..abba7d7 --- /dev/null +++ b/envs/de1-soc/top.sv.bak @@ -0,0 +1,34 @@ +module top + ( input wire CLOCK_50 + , input wire [3:0] KEY + , output wire [9:0] LEDR + ); + + addr_t memory__address; + data_t memory__write_data; + logic [3:0] memory__write_enable; + data_t memory__read_data; + + memory_map #( .SIZE ( 512 ) ) + memory_map + ( .clk ( CLOCK_50 ) + + , .address ( memory__address ) + , .write_data ( memory__write_data ) + , .write_enable ( memory__write_enable ) + , .read_data ( memory__read_data ) + + , .LEDR ( LEDR ) + ); + + utoss_riscv core + ( .clk ( CLOCK_50 ) + , .reset ( KEY[0] ) + + , .memory__address ( memory__address ) + , .memory__write_data ( memory__write_data ) + , .memory__write_enable ( memory__write_enable ) + , .memory__read_data ( memory__read_data ) + ); + +endmodule diff --git a/envs/de1-soc/top_tb.sv b/envs/de1-soc/top_tb.sv index 0888052..6bc2259 100644 --- a/envs/de1-soc/top_tb.sv +++ b/envs/de1-soc/top_tb.sv @@ -41,4 +41,4 @@ module top_tb; $dumpfile("top_tb.vcd"); $dumpvars(0, top_tb); end -endmodule +endmodule \ No newline at end of file diff --git a/quartus workspace/RegisterFile.sv b/quartus workspace/RegisterFile.sv new file mode 100644 index 0000000..f8e659e --- /dev/null +++ b/quartus workspace/RegisterFile.sv @@ -0,0 +1,40 @@ +module registerFile + ( input [4:0] Addr1 + , input [4:0] Addr2 + , input [4:0] Addr3 + , input clk + , input regWrite + , input [31:0] dataIn + , input reset + , output wire [31:0] baseAddr + , output wire [31:0] writeData + , output logic [31:0] dbg_regs [0:31] + ); + + reg [31:0] RFMem [0:31] /* synthesis ramstyle = M10K*/; + + assign baseAddr = (Addr1 == 5'd0) ? 32'd0 : RFMem[Addr1]; + assign writeData = (Addr2 == 5'd0) ? 32'd0 : RFMem[Addr2]; + + genvar i; + generate + for (i=0;i<32;i=i+1) begin : DBG + always_comb dbg_regs[i] = (i==0) ? 32'd0 : RFMem[i]; + end + endgenerate + + always @(posedge clk) begin + if (reset) begin +`ifndef TESTBENCH + integer k; + for (k = 0; k < 32; k = k + 1) begin + RFMem[k] <= 32'b0; + end +`else + RFMem[0] <= 32'b0; +`endif + end else if (regWrite && Addr3 != 0) begin + RFMem[Addr3] <= dataIn; + end + end + endmodule \ No newline at end of file diff --git a/quartus workspace/RegisterFile.sv.bak b/quartus workspace/RegisterFile.sv.bak new file mode 100644 index 0000000..9c69505 --- /dev/null +++ b/quartus workspace/RegisterFile.sv.bak @@ -0,0 +1,39 @@ +module registerFile + ( input [4:0] Addr1 + , input [4:0] Addr2 + , input [4:0] Addr3 + , input clk + , input regWrite + , input [31:0] dataIn + , input reset + , output wire [31:0] baseAddr + , output wire [31:0] writeData + , output logic [31:0] dbg_regs [0:31] // NEW + ); + + reg [31:0] RFMem [0:31] /* synthesis ramstyle = M10K*/; + + assign baseAddr = (Addr1 == 5'd0) ? 32'd0 : RFMem[Addr1]; + assign writeData = (Addr2 == 5'd0) ? 32'd0 : RFMem[Addr2]; + + genvar i; + generate + for (i=0;i<32;i=i+1) begin : DBG + always_comb dbg_regs[i] = (i==0) ? 32'd0 : RFMem[i]; + end + endgenerate + + always @(posedge clk) begin + if (reset) begin +`ifndef TESTBENCH + integer k; + for (k = 0; k < 32; k = k + 1) begin + RFMem[k] <= 32'b0; + end +`else + RFMem[0] <= 32'b0; +`endif + end else if (regWrite && Addr3 != 0) begin + RFMem[Addr3] <= dataIn; + end + end \ No newline at end of file diff --git a/quartus workspace/c5_pin_model_dump.txt b/quartus workspace/c5_pin_model_dump.txt new file mode 100644 index 0000000..31bb72c --- /dev/null +++ b/quartus workspace/c5_pin_model_dump.txt @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2 +io_4iomodule_c5_index: 54gpio_index: 465 +io_4iomodule_c5_index: 33gpio_index: 6 +io_4iomodule_c5_index: 51gpio_index: 461 +io_4iomodule_c5_index: 27gpio_index: 10 +io_4iomodule_c5_index: 57gpio_index: 457 +io_4iomodule_c5_index: 34gpio_index: 14 +io_4iomodule_c5_index: 28gpio_index: 453 +io_4iomodule_c5_index: 26gpio_index: 19 +io_4iomodule_c5_index: 47gpio_index: 449 +io_4iomodule_c5_index: 29gpio_index: 22 +io_4iomodule_c5_index: 3gpio_index: 445 +io_4iomodule_c5_index: 16gpio_index: 27 +io_4iomodule_c5_index: 6gpio_index: 441 +io_4iomodule_c5_index: 50gpio_index: 30 +io_4iomodule_c5_index: 35gpio_index: 437 +io_4iomodule_c5_index: 7gpio_index: 35 +io_4iomodule_c5_index: 53gpio_index: 433 +io_4iomodule_c5_index: 12gpio_index: 38 +io_4iomodule_c5_index: 1gpio_index: 429 +io_4iomodule_c5_index: 22gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 425 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 30gpio_index: 421 +io_4iomodule_c5_index: 2gpio_index: 51 +io_4iomodule_c5_index: 31gpio_index: 417 +io_4iomodule_c5_index: 39gpio_index: 54 +io_4iomodule_c5_index: 18gpio_index: 413 +io_4iomodule_c5_index: 10gpio_index: 59 +io_4iomodule_c5_index: 42gpio_index: 409 +io_4iomodule_c5_index: 5gpio_index: 62 +io_4iomodule_c5_index: 24gpio_index: 405 +io_4iomodule_c5_index: 37gpio_index: 67 +io_4iomodule_c5_index: 13gpio_index: 401 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 44gpio_index: 397 +io_4iomodule_c5_index: 38gpio_index: 75 +io_4iomodule_c5_index: 52gpio_index: 393 +io_4iomodule_c5_index: 32gpio_index: 78 +io_4iomodule_c5_index: 56gpio_index: 389 +io_4iomodule_a_index: 13gpio_index: 385 +io_4iomodule_c5_index: 4gpio_index: 83 +io_4iomodule_c5_index: 23gpio_index: 86 +io_4iomodule_a_index: 15gpio_index: 381 +io_4iomodule_a_index: 8gpio_index: 377 +io_4iomodule_c5_index: 46gpio_index: 91 +io_4iomodule_a_index: 5gpio_index: 373 +io_4iomodule_a_index: 11gpio_index: 369 +io_4iomodule_c5_index: 41gpio_index: 94 +io_4iomodule_a_index: 3gpio_index: 365 +io_4iomodule_c5_index: 25gpio_index: 99 +io_4iomodule_a_index: 7gpio_index: 361 +io_4iomodule_c5_index: 9gpio_index: 102 +io_4iomodule_a_index: 0gpio_index: 357 +io_4iomodule_c5_index: 14gpio_index: 107 +io_4iomodule_a_index: 12gpio_index: 353 +io_4iomodule_c5_index: 45gpio_index: 110 +io_4iomodule_c5_index: 17gpio_index: 115 +io_4iomodule_a_index: 4gpio_index: 349 +io_4iomodule_c5_index: 36gpio_index: 118 +io_4iomodule_a_index: 10gpio_index: 345 +io_4iomodule_a_index: 16gpio_index: 341 +io_4iomodule_c5_index: 15gpio_index: 123 +io_4iomodule_a_index: 14gpio_index: 337 +io_4iomodule_c5_index: 43gpio_index: 126 +io_4iomodule_c5_index: 19gpio_index: 131 +io_4iomodule_a_index: 1gpio_index: 333 +io_4iomodule_c5_index: 59gpio_index: 134 +io_4iomodule_a_index: 2gpio_index: 329 +io_4iomodule_a_index: 9gpio_index: 325 +io_4iomodule_c5_index: 48gpio_index: 139 +io_4iomodule_a_index: 6gpio_index: 321 +io_4iomodule_a_index: 17gpio_index: 317 +io_4iomodule_c5_index: 40gpio_index: 142 +io_4iomodule_c5_index: 11gpio_index: 147 +io_4iomodule_c5_index: 58gpio_index: 150 +io_4iomodule_c5_index: 21gpio_index: 155 +io_4iomodule_c5_index: 49gpio_index: 158 +io_4iomodule_h_c5_index: 0gpio_index: 161 +io_4iomodule_h_c5_index: 6gpio_index: 165 +io_4iomodule_h_c5_index: 10gpio_index: 169 +io_4iomodule_h_c5_index: 3gpio_index: 173 +io_4iomodule_h_c5_index: 8gpio_index: 176 +io_4iomodule_h_c5_index: 11gpio_index: 180 +io_4iomodule_h_c5_index: 7gpio_index: 184 +io_4iomodule_h_c5_index: 5gpio_index: 188 +io_4iomodule_h_c5_index: 1gpio_index: 192 +io_4iomodule_h_c5_index: 2gpio_index: 196 +io_4iomodule_h_c5_index: 9gpio_index: 200 +io_4iomodule_h_c5_index: 4gpio_index: 204 +io_4iomodule_h_index: 15gpio_index: 208 +io_4iomodule_h_index: 1gpio_index: 212 +io_4iomodule_h_index: 3gpio_index: 216 +io_4iomodule_h_index: 2gpio_index: 220 +io_4iomodule_h_index: 11gpio_index: 224 +io_4iomodule_vref_h_index: 1gpio_index: 228 +io_4iomodule_h_index: 20gpio_index: 231 +io_4iomodule_h_index: 8gpio_index: 235 +io_4iomodule_h_index: 6gpio_index: 239 +io_4iomodule_h_index: 10gpio_index: 243 +io_4iomodule_h_index: 23gpio_index: 247 +io_4iomodule_h_index: 7gpio_index: 251 +io_4iomodule_h_index: 22gpio_index: 255 +io_4iomodule_h_index: 5gpio_index: 259 +io_4iomodule_h_index: 24gpio_index: 263 +io_4iomodule_h_index: 0gpio_index: 267 +io_4iomodule_h_index: 13gpio_index: 271 +io_4iomodule_h_index: 21gpio_index: 275 +io_4iomodule_h_index: 16gpio_index: 279 +io_4iomodule_vref_h_index: 0gpio_index: 283 +io_4iomodule_h_index: 12gpio_index: 286 +io_4iomodule_h_index: 4gpio_index: 290 +io_4iomodule_h_index: 19gpio_index: 294 +io_4iomodule_h_index: 18gpio_index: 298 +io_4iomodule_h_index: 17gpio_index: 302 +io_4iomodule_h_index: 25gpio_index: 306 +io_4iomodule_h_index: 14gpio_index: 310 +io_4iomodule_h_index: 9gpio_index: 314 diff --git a/quartus workspace/db/.cmp.kpt b/quartus workspace/db/.cmp.kpt new file mode 100644 index 0000000..1fe7181 Binary files /dev/null and b/quartus workspace/db/.cmp.kpt differ diff --git a/quartus workspace/db/altsyncram_0or1.tdf b/quartus workspace/db/altsyncram_0or1.tdf new file mode 100644 index 0000000..eca77ac --- /dev/null +++ b/quartus workspace/db/altsyncram_0or1.tdf @@ -0,0 +1,1043 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/top.ram0_memory_map_ee718c45.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2023:07:21:07:12:20:SC cbx_altsyncram 2023:07:21:07:12:21:SC cbx_cycloneii 2023:07:21:07:12:21:SC cbx_lpm_add_sub 2023:07:21:07:12:21:SC cbx_lpm_compare 2023:07:21:07:12:21:SC cbx_lpm_decode 2023:07:21:07:12:20:SC cbx_lpm_mux 2023:07:21:07:12:21:SC cbx_mgl 2023:07:21:07:12:36:SC cbx_nadder 2023:07:21:07:12:21:SC cbx_stratix 2023:07:21:07:12:21:SC cbx_stratixii 2023:07:21:07:12:21:SC cbx_stratixiii 2023:07:21:07:12:21:SC cbx_stratixv 2023:07:21:07:12:21:SC cbx_util_mgl 2023:07:21:07:12:21:SC VERSION_END + + +-- Copyright (C) 2023 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M10K 2 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_0or1 +( + address_a[8..0] : input; + address_b[8..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[8..0] : WIRE; + address_b_wire[8..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[8..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[8..0]); + ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/quartus workspace/db/altsyncram_5lt1.tdf b/quartus workspace/db/altsyncram_5lt1.tdf new file mode 100644 index 0000000..0f0656c --- /dev/null +++ b/quartus workspace/db/altsyncram_5lt1.tdf @@ -0,0 +1,1043 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/top.ram0_memory_map_ee718c45.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="M10K" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2023:07:21:07:12:20:SC cbx_altsyncram 2023:07:21:07:12:21:SC cbx_cycloneii 2023:07:21:07:12:21:SC cbx_lpm_add_sub 2023:07:21:07:12:21:SC cbx_lpm_compare 2023:07:21:07:12:21:SC cbx_lpm_decode 2023:07:21:07:12:20:SC cbx_lpm_mux 2023:07:21:07:12:21:SC cbx_mgl 2023:07:21:07:12:36:SC cbx_nadder 2023:07:21:07:12:21:SC cbx_stratix 2023:07:21:07:12:21:SC cbx_stratixii 2023:07:21:07:12:21:SC cbx_stratixiii 2023:07:21:07:12:21:SC cbx_stratixv 2023:07:21:07:12:21:SC cbx_util_mgl 2023:07:21:07:12:21:SC VERSION_END + + +-- Copyright (C) 2023 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M10K 2 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_5lt1 +( + address_a[8..0] : input; + address_b[8..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a8 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a9 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a10 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a11 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a12 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a13 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a14 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a15 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a16 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a17 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a18 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a19 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a20 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a21 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a22 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a23 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a24 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a25 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a26 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a27 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a28 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a29 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a30 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a31 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + address_a_wire[8..0] : WIRE; + address_b_wire[8..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[8..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[8..0]); + ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/quartus workspace/db/altsyncram_6lr1.tdf b/quartus workspace/db/altsyncram_6lr1.tdf new file mode 100644 index 0000000..33c2448 --- /dev/null +++ b/quartus workspace/db/altsyncram_6lr1.tdf @@ -0,0 +1,299 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/top.ram0_memory_map_ee718c45.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2023:07:21:07:12:20:SC cbx_altsyncram 2023:07:21:07:12:21:SC cbx_cycloneii 2023:07:21:07:12:21:SC cbx_lpm_add_sub 2023:07:21:07:12:21:SC cbx_lpm_compare 2023:07:21:07:12:21:SC cbx_lpm_decode 2023:07:21:07:12:20:SC cbx_lpm_mux 2023:07:21:07:12:21:SC cbx_mgl 2023:07:21:07:12:36:SC cbx_nadder 2023:07:21:07:12:21:SC cbx_stratix 2023:07:21:07:12:21:SC cbx_stratixii 2023:07:21:07:12:21:SC cbx_stratixiii 2023:07:21:07:12:21:SC cbx_stratixv 2023:07:21:07:12:21:SC cbx_util_mgl 2023:07:21:07:12:21:SC VERSION_END + + +-- Copyright (C) 2023 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M10K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_6lr1 +( + address_a[8..0] : input; + address_b[8..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[8..0] : WIRE; + address_b_wire[8..0] : WIRE; + +BEGIN + ram_block1a[7..0].clk0 = clock0; + ram_block1a[7..0].portaaddr[] = ( address_a_wire[8..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[7..0].portawe = wren_a; + ram_block1a[7..0].portbaddr[] = ( address_b_wire[8..0]); + ram_block1a[7..0].portbre = B"11111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[7..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/quartus workspace/db/altsyncram_7lr1.tdf b/quartus workspace/db/altsyncram_7lr1.tdf new file mode 100644 index 0000000..3733979 --- /dev/null +++ b/quartus workspace/db/altsyncram_7lr1.tdf @@ -0,0 +1,299 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/top.ram1_memory_map_ee718c45.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2023:07:21:07:12:20:SC cbx_altsyncram 2023:07:21:07:12:21:SC cbx_cycloneii 2023:07:21:07:12:21:SC cbx_lpm_add_sub 2023:07:21:07:12:21:SC cbx_lpm_compare 2023:07:21:07:12:21:SC cbx_lpm_decode 2023:07:21:07:12:20:SC cbx_lpm_mux 2023:07:21:07:12:21:SC cbx_mgl 2023:07:21:07:12:36:SC cbx_nadder 2023:07:21:07:12:21:SC cbx_stratix 2023:07:21:07:12:21:SC cbx_stratixii 2023:07:21:07:12:21:SC cbx_stratixiii 2023:07:21:07:12:21:SC cbx_stratixv 2023:07:21:07:12:21:SC cbx_util_mgl 2023:07:21:07:12:21:SC VERSION_END + + +-- Copyright (C) 2023 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M10K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_7lr1 +( + address_a[8..0] : input; + address_b[8..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram1_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram1_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram1_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram1_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram1_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram1_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram1_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram1_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[8..0] : WIRE; + address_b_wire[8..0] : WIRE; + +BEGIN + ram_block1a[7..0].clk0 = clock0; + ram_block1a[7..0].portaaddr[] = ( address_a_wire[8..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[7..0].portawe = wren_a; + ram_block1a[7..0].portbaddr[] = ( address_b_wire[8..0]); + ram_block1a[7..0].portbre = B"11111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[7..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/quartus workspace/db/altsyncram_8lr1.tdf b/quartus workspace/db/altsyncram_8lr1.tdf new file mode 100644 index 0000000..c8a4cfd --- /dev/null +++ b/quartus workspace/db/altsyncram_8lr1.tdf @@ -0,0 +1,299 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/top.ram2_memory_map_ee718c45.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2023:07:21:07:12:20:SC cbx_altsyncram 2023:07:21:07:12:21:SC cbx_cycloneii 2023:07:21:07:12:21:SC cbx_lpm_add_sub 2023:07:21:07:12:21:SC cbx_lpm_compare 2023:07:21:07:12:21:SC cbx_lpm_decode 2023:07:21:07:12:20:SC cbx_lpm_mux 2023:07:21:07:12:21:SC cbx_mgl 2023:07:21:07:12:36:SC cbx_nadder 2023:07:21:07:12:21:SC cbx_stratix 2023:07:21:07:12:21:SC cbx_stratixii 2023:07:21:07:12:21:SC cbx_stratixiii 2023:07:21:07:12:21:SC cbx_stratixv 2023:07:21:07:12:21:SC cbx_util_mgl 2023:07:21:07:12:21:SC VERSION_END + + +-- Copyright (C) 2023 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M10K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_8lr1 +( + address_a[8..0] : input; + address_b[8..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram2_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram2_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram2_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram2_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram2_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram2_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram2_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram2_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[8..0] : WIRE; + address_b_wire[8..0] : WIRE; + +BEGIN + ram_block1a[7..0].clk0 = clock0; + ram_block1a[7..0].portaaddr[] = ( address_a_wire[8..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[7..0].portawe = wren_a; + ram_block1a[7..0].portbaddr[] = ( address_b_wire[8..0]); + ram_block1a[7..0].portbre = B"11111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[7..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/quartus workspace/db/altsyncram_9lr1.tdf b/quartus workspace/db/altsyncram_9lr1.tdf new file mode 100644 index 0000000..3170522 --- /dev/null +++ b/quartus workspace/db/altsyncram_9lr1.tdf @@ -0,0 +1,299 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/top.ram3_memory_map_ee718c45.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2023:07:21:07:12:20:SC cbx_altsyncram 2023:07:21:07:12:21:SC cbx_cycloneii 2023:07:21:07:12:21:SC cbx_lpm_add_sub 2023:07:21:07:12:21:SC cbx_lpm_compare 2023:07:21:07:12:21:SC cbx_lpm_decode 2023:07:21:07:12:20:SC cbx_lpm_mux 2023:07:21:07:12:21:SC cbx_mgl 2023:07:21:07:12:36:SC cbx_nadder 2023:07:21:07:12:21:SC cbx_stratix 2023:07:21:07:12:21:SC cbx_stratixii 2023:07:21:07:12:21:SC cbx_stratixiii 2023:07:21:07:12:21:SC cbx_stratixv 2023:07:21:07:12:21:SC cbx_util_mgl 2023:07:21:07:12:21:SC VERSION_END + + +-- Copyright (C) 2023 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M10K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_9lr1 +( + address_a[8..0] : input; + address_b[8..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram3_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram3_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram3_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram3_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram3_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram3_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram3_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram3_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[8..0] : WIRE; + address_b_wire[8..0] : WIRE; + +BEGIN + ram_block1a[7..0].clk0 = clock0; + ram_block1a[7..0].portaaddr[] = ( address_a_wire[8..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[7..0].portawe = wren_a; + ram_block1a[7..0].portbaddr[] = ( address_b_wire[8..0]); + ram_block1a[7..0].portbre = B"11111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[7..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/quartus workspace/db/altsyncram_elt1.tdf b/quartus workspace/db/altsyncram_elt1.tdf new file mode 100644 index 0000000..b58d15b --- /dev/null +++ b/quartus workspace/db/altsyncram_elt1.tdf @@ -0,0 +1,1045 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/top.ram0_memory_map_ee718c45.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a rden_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2023:07:21:07:12:20:SC cbx_altsyncram 2023:07:21:07:12:21:SC cbx_cycloneii 2023:07:21:07:12:21:SC cbx_lpm_add_sub 2023:07:21:07:12:21:SC cbx_lpm_compare 2023:07:21:07:12:21:SC cbx_lpm_decode 2023:07:21:07:12:20:SC cbx_lpm_mux 2023:07:21:07:12:21:SC cbx_mgl 2023:07:21:07:12:36:SC cbx_nadder 2023:07:21:07:12:21:SC cbx_stratix 2023:07:21:07:12:21:SC cbx_stratixii 2023:07:21:07:12:21:SC cbx_stratixiii 2023:07:21:07:12:21:SC cbx_stratixv 2023:07:21:07:12:21:SC cbx_util_mgl 2023:07:21:07:12:21:SC VERSION_END + + +-- Copyright (C) 2023 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M10K 2 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_elt1 +( + address_a[8..0] : input; + address_b[8..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + rden_b : input; +) +VARIABLE + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[8..0] : WIRE; + address_b_wire[8..0] : WIRE; + wren_a : NODE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[8..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[8..0]); + ram_block1a[31..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); + wren_a = GND; +END; +--VALID FILE diff --git a/quartus workspace/db/altsyncram_i3n1.tdf b/quartus workspace/db/altsyncram_i3n1.tdf new file mode 100644 index 0000000..4ffa536 --- /dev/null +++ b/quartus workspace/db/altsyncram_i3n1.tdf @@ -0,0 +1,283 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2023:07:21:07:12:20:SC cbx_altsyncram 2023:07:21:07:12:21:SC cbx_cycloneii 2023:07:21:07:12:21:SC cbx_lpm_add_sub 2023:07:21:07:12:21:SC cbx_lpm_compare 2023:07:21:07:12:21:SC cbx_lpm_decode 2023:07:21:07:12:20:SC cbx_lpm_mux 2023:07:21:07:12:21:SC cbx_mgl 2023:07:21:07:12:36:SC cbx_nadder 2023:07:21:07:12:21:SC cbx_stratix 2023:07:21:07:12:21:SC cbx_stratixii 2023:07:21:07:12:21:SC cbx_stratixiii 2023:07:21:07:12:21:SC cbx_stratixv 2023:07:21:07:12:21:SC cbx_util_mgl 2023:07:21:07:12:21:SC VERSION_END + + +-- Copyright (C) 2023 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M10K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_i3n1 +( + address_a[8..0] : input; + address_b[8..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[8..0] : WIRE; + address_b_wire[8..0] : WIRE; + +BEGIN + ram_block1a[7..0].clk0 = clock0; + ram_block1a[7..0].portaaddr[] = ( address_a_wire[8..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[7..0].portawe = wren_a; + ram_block1a[7..0].portbaddr[] = ( address_b_wire[8..0]); + ram_block1a[7..0].portbre = B"11111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[7..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/quartus workspace/db/altsyncram_jiv1.tdf b/quartus workspace/db/altsyncram_jiv1.tdf new file mode 100644 index 0000000..4187e3f --- /dev/null +++ b/quartus workspace/db/altsyncram_jiv1.tdf @@ -0,0 +1,1045 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/top.ram0_memory_map_ee718c45.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="M10K" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a rden_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2023:07:21:07:12:20:SC cbx_altsyncram 2023:07:21:07:12:21:SC cbx_cycloneii 2023:07:21:07:12:21:SC cbx_lpm_add_sub 2023:07:21:07:12:21:SC cbx_lpm_compare 2023:07:21:07:12:21:SC cbx_lpm_decode 2023:07:21:07:12:20:SC cbx_lpm_mux 2023:07:21:07:12:21:SC cbx_mgl 2023:07:21:07:12:36:SC cbx_nadder 2023:07:21:07:12:21:SC cbx_stratix 2023:07:21:07:12:21:SC cbx_stratixii 2023:07:21:07:12:21:SC cbx_stratixiii 2023:07:21:07:12:21:SC cbx_stratixv 2023:07:21:07:12:21:SC cbx_util_mgl 2023:07:21:07:12:21:SC VERSION_END + + +-- Copyright (C) 2023 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M10K 2 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_jiv1 +( + address_a[8..0] : input; + address_b[8..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + rden_b : input; +) +VARIABLE + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a8 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a9 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a10 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a11 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a12 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a13 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a14 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a15 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a16 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a17 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a18 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a19 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a20 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a21 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a22 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a23 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a24 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a25 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a26 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a27 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a28 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a29 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a30 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + ram_block1a31 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/top.ram0_memory_map_ee718c45.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 9, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 511, + PORT_A_LOGICAL_RAM_DEPTH = 512, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 9, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 511, + PORT_B_LOGICAL_RAM_DEPTH = 512, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "M10K" + ); + address_a_wire[8..0] : WIRE; + address_b_wire[8..0] : WIRE; + wren_a : NODE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[8..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[8..0]); + ram_block1a[31..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); + wren_a = GND; +END; +--VALID FILE diff --git a/quartus workspace/db/prev_cmp_top.qmsg b/quartus workspace/db/prev_cmp_top.qmsg new file mode 100644 index 0000000..412f25d --- /dev/null +++ b/quartus workspace/db/prev_cmp_top.qmsg @@ -0,0 +1,103 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1768272684387 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition " "Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1768272684387 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 12 21:51:23 2026 " "Processing started: Mon Jan 12 21:51:23 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1768272684387 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272684387 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272684387 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1768272684643 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1768272684643 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "src/logger.sv 1 1 " "Found 1 design units, including 1 entities, in source file src/logger.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Logger " "Found entity 1: Logger" { } { { "src/Logger.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/src/Logger.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689945 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689945 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" { } { { "../envs/de1-soc/top.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689946 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689946 ""} +{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "5 memory_map.sv(114) " "Verilog HDL Expression warning at memory_map.sv(114): truncated literal to match 5 bits" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 114 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1768272689948 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" { { "Info" "ISGN_ENTITY_NAME" "1 memory_map " "Found entity 1: memory_map" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 71 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689949 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689949 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/alu_aludecoder/aludecoder.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/alu_aludecoder/aludecoder.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ALUdecoder " "Found entity 1: ALUdecoder" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689951 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689951 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/alu_aludecoder/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/alu_aludecoder/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Found entity 1: ALU" { } { { "../src/ALU_ALUdecoder/ALU.v" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALU.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689953 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689953 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/registerfile.v 0 0 " "Found 0 design units, including 0 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/registerfile.v" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689955 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/memoryloader.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/memoryloader.sv" { { "Info" "ISGN_ENTITY_NAME" "1 MemoryLoader " "Found entity 1: MemoryLoader" { } { { "../src/Instruction_Decode/MemoryLoader.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/MemoryLoader.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689957 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689957 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/instruction_decode.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/instruction_decode.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Instruction_Decode " "Found entity 1: Instruction_Decode" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689960 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689960 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" { { "Info" "ISGN_ENTITY_NAME" "1 utoss_riscv " "Found entity 1: utoss_riscv" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689963 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689963 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/fetch.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/fetch.sv" { { "Info" "ISGN_ENTITY_NAME" "1 fetch " "Found entity 1: fetch" { } { { "../src/fetch.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/fetch.sv" 10 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689966 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689966 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "MemWrite MEMWRITE ControlFSM.sv(21) " "Verilog HDL Declaration information at ControlFSM.sv(21): object \"MemWrite\" differs only in case from object \"MEMWRITE\" in the same scope" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1768272689968 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/controlfsm.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/controlfsm.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ControlFSM " "Found entity 1: ControlFSM" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 7 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689969 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689969 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_rx.sv 1 1 " "Found 1 design units, including 1 entities, in source file uart_rx.sv" { { "Info" "ISGN_ENTITY_NAME" "1 uart_rx " "Found entity 1: uart_rx" { } { { "uart_rx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689971 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689971 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_tx.sv 1 1 " "Found 1 design units, including 1 entities, in source file uart_tx.sv" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "uart_tx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_tx.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689973 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689973 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.sv 1 1 " "Found 1 design units, including 1 entities, in source file uart.sv" { { "Info" "ISGN_ENTITY_NAME" "1 uart " "Found entity 1: uart" { } { { "uart.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689975 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689975 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "inst_mem.v 1 1 " "Found 1 design units, including 1 entities, in source file inst_mem.v" { { "Info" "ISGN_ENTITY_NAME" "1 inst_mem " "Found entity 1: inst_mem" { } { { "inst_mem.v" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/inst_mem.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689976 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689976 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_bus_master.sv 1 1 " "Found 1 design units, including 1 entities, in source file uart_bus_master.sv" { { "Info" "ISGN_ENTITY_NAME" "1 uart_bus_master " "Found entity 1: uart_bus_master" { } { { "uart_bus_master.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_bus_master.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689978 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689978 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "registerfile.sv 1 1 " "Found 1 design units, including 1 entities, in source file registerfile.sv" { { "Info" "ISGN_ENTITY_NAME" "1 registerFile " "Found entity 1: registerFile" { } { { "RegisterFile.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/RegisterFile.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272689980 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272689980 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1768272690049 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart uart:u_uart " "Elaborating entity \"uart\" for hierarchy \"uart:u_uart\"" { } { { "../envs/de1-soc/top.sv" "u_uart" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690083 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart:u_uart\|uart_tx:uart_tx_inst " "Elaborating entity \"uart_tx\" for hierarchy \"uart:u_uart\|uart_tx:uart_tx_inst\"" { } { { "uart.sv" "uart_tx_inst" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart.sv" 48 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690089 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_tx.sv(48) " "Verilog HDL assignment warning at uart_tx.sv(48): truncated value with size 32 to match size of target (19)" { } { { "uart_tx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_tx.sv" 48 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272690090 "|top|uart:u_uart|uart_tx:uart_tx_inst"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_tx.sv(64) " "Verilog HDL assignment warning at uart_tx.sv(64): truncated value with size 32 to match size of target (19)" { } { { "uart_tx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_tx.sv" 64 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272690090 "|top|uart:u_uart|uart_tx:uart_tx_inst"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_rx uart:u_uart\|uart_rx:uart_rx_inst " "Elaborating entity \"uart_rx\" for hierarchy \"uart:u_uart\|uart_rx:uart_rx_inst\"" { } { { "uart.sv" "uart_rx_inst" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart.sv" 64 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690102 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_rx.sv(78) " "Verilog HDL assignment warning at uart_rx.sv(78): truncated value with size 32 to match size of target (19)" { } { { "uart_rx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv" 78 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272690103 "|top|uart:u_uart|uart_rx:uart_rx_inst"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_rx.sv(91) " "Verilog HDL assignment warning at uart_rx.sv(91): truncated value with size 32 to match size of target (19)" { } { { "uart_rx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv" 91 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272690103 "|top|uart:u_uart|uart_rx:uart_rx_inst"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_rx.sv(109) " "Verilog HDL assignment warning at uart_rx.sv(109): truncated value with size 32 to match size of target (19)" { } { { "uart_rx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272690104 "|top|uart:u_uart|uart_rx:uart_rx_inst"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_rx.sv(112) " "Verilog HDL assignment warning at uart_rx.sv(112): truncated value with size 32 to match size of target (19)" { } { { "uart_rx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv" 112 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272690104 "|top|uart:u_uart|uart_rx:uart_rx_inst"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_bus_master uart_bus_master:u_master " "Elaborating entity \"uart_bus_master\" for hierarchy \"uart_bus_master:u_master\"" { } { { "../envs/de1-soc/top.sv" "u_master" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 74 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690116 ""} +{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "uart_bus_master.sv(164) " "Verilog HDL Case Statement information at uart_bus_master.sv(164): all case item expressions in this case statement are onehot" { } { { "uart_bus_master.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_bus_master.sv" 164 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1768272690128 "|top|uart_bus_master:u_master"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_map memory_map:u_mem " "Elaborating entity \"memory_map\" for hierarchy \"memory_map:u_mem\"" { } { { "../envs/de1-soc/top.sv" "u_mem" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690216 ""} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "20 0 511 memory_map.sv(92) " "Verilog HDL warning at memory_map.sv(92): number of words (20) in memory file does not match the number of elements in the address range \[0:511\]" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 92 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1768272690223 "|top|memory_map:u_mem"} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "20 0 511 memory_map.sv(93) " "Verilog HDL warning at memory_map.sv(93): number of words (20) in memory file does not match the number of elements in the address range \[0:511\]" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 93 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1768272690224 "|top|memory_map:u_mem"} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "20 0 511 memory_map.sv(94) " "Verilog HDL warning at memory_map.sv(94): number of words (20) in memory file does not match the number of elements in the address range \[0:511\]" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 94 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1768272690225 "|top|memory_map:u_mem"} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "20 0 511 memory_map.sv(95) " "Verilog HDL warning at memory_map.sv(95): number of words (20) in memory file does not match the number of elements in the address range \[0:511\]" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 95 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1768272690225 "|top|memory_map:u_mem"} +{ "Warning" "WVRFX_VERI_CANT_ANALYZE_CASE_STATEMENT" "memory_map.sv(110) " "Verilog HDL Case Statement warning at memory_map.sv(110): can't check case statement for completeness because the case expression has too many possible states" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 110 0 0 } } } 0 10762 "Verilog HDL Case Statement warning at %1!s!: can't check case statement for completeness because the case expression has too many possible states" 0 0 "Analysis & Synthesis" 0 -1 1768272690232 "|top|memory_map:u_mem"} +{ "Warning" "WVRFX_VERI_CANT_ANALYZE_CASE_STATEMENT" "memory_map.sv(123) " "Verilog HDL Case Statement warning at memory_map.sv(123): can't check case statement for completeness because the case expression has too many possible states" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 123 0 0 } } } 0 10762 "Verilog HDL Case Statement warning at %1!s!: can't check case statement for completeness because the case expression has too many possible states" 0 0 "Analysis & Synthesis" 0 -1 1768272690233 "|top|memory_map:u_mem"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "utoss_riscv utoss_riscv:core " "Elaborating entity \"utoss_riscv\" for hierarchy \"utoss_riscv:core\"" { } { { "../envs/de1-soc/top.sv" "core" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 118 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690274 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ControlFSM utoss_riscv:core\|ControlFSM:control_fsm " "Elaborating entity \"ControlFSM\" for hierarchy \"utoss_riscv:core\|ControlFSM:control_fsm\"" { } { { "../src/utoss_riscv.sv" "control_fsm" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690307 ""} +{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "ControlFSM.sv(244) " "Verilog HDL Case Statement warning at ControlFSM.sv(244): incomplete case statement has no default case item" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 244 0 0 } } } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "Analysis & Synthesis" 0 -1 1768272690310 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ALUSrcA ControlFSM.sv(146) " "Verilog HDL Always Construct warning at ControlFSM.sv(146): inferring latch(es) for variable \"ALUSrcA\", which holds its previous value in one or more paths through the always construct" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1768272690310 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ALUSrcB ControlFSM.sv(146) " "Verilog HDL Always Construct warning at ControlFSM.sv(146): inferring latch(es) for variable \"ALUSrcB\", which holds its previous value in one or more paths through the always construct" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1768272690310 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALUSrcB\[0\] ControlFSM.sv(146) " "Inferred latch for \"ALUSrcB\[0\]\" at ControlFSM.sv(146)" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690312 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALUSrcB\[1\] ControlFSM.sv(146) " "Inferred latch for \"ALUSrcB\[1\]\" at ControlFSM.sv(146)" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690312 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALUSrcA\[0\] ControlFSM.sv(146) " "Inferred latch for \"ALUSrcA\[0\]\" at ControlFSM.sv(146)" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690312 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALUSrcA\[1\] ControlFSM.sv(146) " "Inferred latch for \"ALUSrcA\[1\]\" at ControlFSM.sv(146)" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690312 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fetch utoss_riscv:core\|fetch:fetch " "Elaborating entity \"fetch\" for hierarchy \"utoss_riscv:core\|fetch:fetch\"" { } { { "../src/utoss_riscv.sv" "fetch" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 92 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690320 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MemoryLoader utoss_riscv:core\|MemoryLoader:MemLoad " "Elaborating entity \"MemoryLoader\" for hierarchy \"utoss_riscv:core\|MemoryLoader:MemLoad\"" { } { { "../src/utoss_riscv.sv" "MemLoad" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 115 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690330 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Instruction_Decode utoss_riscv:core\|Instruction_Decode:instruction_decode " "Elaborating entity \"Instruction_Decode\" for hierarchy \"utoss_riscv:core\|Instruction_Decode:instruction_decode\"" { } { { "../src/utoss_riscv.sv" "instruction_decode" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 131 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690339 ""} +{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "Instruction_Decode.sv(127) " "Verilog HDL Case Statement warning at Instruction_Decode.sv(127): incomplete case statement has no default case item" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "Analysis & Synthesis" 0 -1 1768272690341 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "imm_ext Instruction_Decode.sv(127) " "Verilog HDL Always Construct warning at Instruction_Decode.sv(127): inferring latch(es) for variable \"imm_ext\", which holds its previous value in one or more paths through the always construct" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1768272690342 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[0\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[0\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690343 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[1\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[1\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690344 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[2\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[2\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690344 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[3\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[3\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690344 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[4\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[4\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690344 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[5\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[5\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690344 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[6\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[6\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690344 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[7\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[7\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690344 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[8\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[8\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690344 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[9\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[9\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690344 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[10\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[10\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690344 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[11\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[11\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[12\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[12\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[13\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[13\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[14\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[14\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[15\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[15\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[16\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[16\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[17\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[17\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[18\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[18\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[19\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[19\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[20\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[20\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[21\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[21\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[22\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[22\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[23\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[23\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[24\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[24\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[25\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[25\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[26\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[26\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690345 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[27\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[27\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690346 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[28\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[28\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690346 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[29\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[29\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690346 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[30\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[30\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690346 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[31\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[31\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690346 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALUdecoder utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec " "Elaborating entity \"ALUdecoder\" for hierarchy \"utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec\"" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "instanceALUDec" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 147 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690353 ""} +{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "alu_control ALUdecoder.sv(10) " "Verilog HDL Always Construct warning at ALUdecoder.sv(10): inferring latch(es) for variable \"alu_control\", which holds its previous value in one or more paths through the always construct" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1768272690354 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "alu_control\[0\] ALUdecoder.sv(10) " "Inferred latch for \"alu_control\[0\]\" at ALUdecoder.sv(10)" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690355 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "alu_control\[1\] ALUdecoder.sv(10) " "Inferred latch for \"alu_control\[1\]\" at ALUdecoder.sv(10)" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690355 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "alu_control\[2\] ALUdecoder.sv(10) " "Inferred latch for \"alu_control\[2\]\" at ALUdecoder.sv(10)" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690355 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "alu_control\[3\] ALUdecoder.sv(10) " "Inferred latch for \"alu_control\[3\]\" at ALUdecoder.sv(10)" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690355 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "registerFile utoss_riscv:core\|registerFile:RegFile " "Elaborating entity \"registerFile\" for hierarchy \"utoss_riscv:core\|registerFile:RegFile\"" { } { { "../src/utoss_riscv.sv" "RegFile" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690361 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALU utoss_riscv:core\|ALU:alu " "Elaborating entity \"ALU\" for hierarchy \"utoss_riscv:core\|ALU:alu\"" { } { { "../src/utoss_riscv.sv" "alu" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 152 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690523 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Logger utoss_riscv:core\|Logger:CoreLog " "Elaborating entity \"Logger\" for hierarchy \"utoss_riscv:core\|Logger:CoreLog\"" { } { { "../src/utoss_riscv.sv" "CoreLog" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690532 ""} +{ "Error" "EVRFX_SV_UNSUPPORTED_FEATURE" "declaring string variables outside functions and tasks Logger.sv(21) " "SystemVerilog Unsupported Feature error at Logger.sv(21): Integrated Synthesis does not support declaring string variables outside functions and tasks" { } { { "src/Logger.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/src/Logger.sv" 21 0 0 } } } 0 10911 "SystemVerilog Unsupported Feature error at %2!s!: Integrated Synthesis does not support %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690534 ""} +{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "utoss_riscv:core\|Logger:CoreLog " "Can't elaborate user hierarchy \"utoss_riscv:core\|Logger:CoreLog\"" { } { { "../src/utoss_riscv.sv" "CoreLog" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 213 0 0 } } } 0 12152 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272690534 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.map.smsg " "Generated suppressed messages file E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690575 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 20 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 20 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4824 " "Peak virtual memory: 4824 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1768272690621 ""} { "Error" "EQEXE_END_BANNER_TIME" "Mon Jan 12 21:51:30 2026 " "Processing ended: Mon Jan 12 21:51:30 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1768272690621 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1768272690621 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1768272690621 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272690621 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 20 s " "Quartus Prime Full Compilation was unsuccessful. 4 errors, 20 warnings" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272691318 ""} diff --git a/quartus workspace/db/top.(0).cnf.cdb b/quartus workspace/db/top.(0).cnf.cdb new file mode 100644 index 0000000..e530ece Binary files /dev/null and b/quartus workspace/db/top.(0).cnf.cdb differ diff --git a/quartus workspace/db/top.(0).cnf.hdb b/quartus workspace/db/top.(0).cnf.hdb new file mode 100644 index 0000000..d001605 Binary files /dev/null and b/quartus workspace/db/top.(0).cnf.hdb differ diff --git a/quartus workspace/db/top.(1).cnf.cdb b/quartus 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index 0000000..a1ae676 Binary files /dev/null and b/quartus workspace/db/top.(9).cnf.cdb differ diff --git a/quartus workspace/db/top.(9).cnf.hdb b/quartus workspace/db/top.(9).cnf.hdb new file mode 100644 index 0000000..a02d7c8 Binary files /dev/null and b/quartus workspace/db/top.(9).cnf.hdb differ diff --git a/quartus workspace/db/top.ae.hdb b/quartus workspace/db/top.ae.hdb new file mode 100644 index 0000000..542c5fc Binary files /dev/null and b/quartus workspace/db/top.ae.hdb differ diff --git a/quartus workspace/db/top.asm.qmsg b/quartus workspace/db/top.asm.qmsg new file mode 100644 index 0000000..e2ab72f --- /dev/null +++ b/quartus workspace/db/top.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1768270588101 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition " "Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1768270588102 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 12 21:16:27 2026 " "Processing started: Mon Jan 12 21:16:27 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1768270588102 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1768270588102 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off top -c top " "Command: quartus_asm --read_settings_files=off --write_settings_files=off top -c top" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1768270588102 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1768270588826 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1768270593720 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5270 " "Peak virtual memory: 5270 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1768270594369 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 12 21:16:34 2026 " "Processing ended: Mon Jan 12 21:16:34 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1768270594369 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1768270594369 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1768270594369 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1768270594369 ""} diff --git a/quartus workspace/db/top.asm.rdb b/quartus workspace/db/top.asm.rdb new file mode 100644 index 0000000..203cfee Binary files /dev/null and b/quartus workspace/db/top.asm.rdb differ diff --git a/quartus workspace/db/top.cbx.xml b/quartus workspace/db/top.cbx.xml new file mode 100644 index 0000000..c417f7f --- /dev/null +++ b/quartus workspace/db/top.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/quartus workspace/db/top.cmp.idb b/quartus workspace/db/top.cmp.idb new file mode 100644 index 0000000..0e52aea Binary files /dev/null and b/quartus workspace/db/top.cmp.idb differ diff --git a/quartus workspace/db/top.cmp.logdb b/quartus workspace/db/top.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/quartus workspace/db/top.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/quartus workspace/db/top.cmp.rdb b/quartus workspace/db/top.cmp.rdb new file mode 100644 index 0000000..6b753a1 Binary files /dev/null and b/quartus workspace/db/top.cmp.rdb differ diff --git a/quartus workspace/db/top.cmp_merge.kpt b/quartus workspace/db/top.cmp_merge.kpt new file mode 100644 index 0000000..ea78ac5 Binary files /dev/null and b/quartus workspace/db/top.cmp_merge.kpt differ diff --git a/quartus workspace/db/top.cyclonev_io_sim_cache.ff_0c_fast.hsd b/quartus workspace/db/top.cyclonev_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..49aae9d Binary files /dev/null and b/quartus workspace/db/top.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/quartus workspace/db/top.cyclonev_io_sim_cache.ff_85c_fast.hsd b/quartus workspace/db/top.cyclonev_io_sim_cache.ff_85c_fast.hsd new file mode 100644 index 0000000..a207c34 Binary files /dev/null and b/quartus workspace/db/top.cyclonev_io_sim_cache.ff_85c_fast.hsd differ diff --git a/quartus workspace/db/top.cyclonev_io_sim_cache.tt_0c_slow.hsd b/quartus workspace/db/top.cyclonev_io_sim_cache.tt_0c_slow.hsd new file mode 100644 index 0000000..205f80a Binary files /dev/null and b/quartus workspace/db/top.cyclonev_io_sim_cache.tt_0c_slow.hsd differ diff --git a/quartus workspace/db/top.cyclonev_io_sim_cache.tt_85c_slow.hsd b/quartus workspace/db/top.cyclonev_io_sim_cache.tt_85c_slow.hsd new file mode 100644 index 0000000..a1dd740 Binary files /dev/null and b/quartus workspace/db/top.cyclonev_io_sim_cache.tt_85c_slow.hsd differ diff --git a/quartus workspace/db/top.db_info b/quartus workspace/db/top.db_info new file mode 100644 index 0000000..b9a1b1e --- /dev/null +++ b/quartus workspace/db/top.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition +Version_Index = 553884160 +Creation_Time = Mon Jan 12 15:15:56 2026 diff --git a/quartus workspace/db/top.fit.qmsg b/quartus workspace/db/top.fit.qmsg new file mode 100644 index 0000000..e69de29 diff --git a/quartus workspace/db/top.hier_info b/quartus workspace/db/top.hier_info new file mode 100644 index 0000000..43c5278 --- /dev/null +++ b/quartus workspace/db/top.hier_info @@ -0,0 +1,11635 @@ +|top +CLOCK_50 => CLOCK_50.IN1 +KEY[0] => rst.IN1 +KEY[1] => ~NO_FANOUT~ +KEY[2] => ~NO_FANOUT~ +KEY[3] => ~NO_FANOUT~ +LEDR[0] << memory_map:u_mem.LEDR[0] +LEDR[1] << memory_map:u_mem.LEDR[1] +LEDR[2] << memory_map:u_mem.LEDR[2] +LEDR[3] << memory_map:u_mem.LEDR[3] +LEDR[4] << memory_map:u_mem.LEDR[4] +LEDR[5] << memory_map:u_mem.LEDR[5] +LEDR[6] << memory_map:u_mem.LEDR[6] +LEDR[7] << memory_map:u_mem.LEDR[7] +LEDR[8] << memory_map:u_mem.LEDR[8] +LEDR[9] << memory_map:u_mem.LEDR[9] +UART_TX => UART_TX.IN1 +UART_RX << uart:u_uart.o_txd + + +|top|uart:u_uart +clk => clk.IN2 +rst => rst.IN2 +i_data_s[0] => i_data_s[0].IN1 +i_data_s[1] => i_data_s[1].IN1 +i_data_s[2] => i_data_s[2].IN1 +i_data_s[3] => i_data_s[3].IN1 +i_data_s[4] => i_data_s[4].IN1 +i_data_s[5] => i_data_s[5].IN1 +i_data_s[6] => i_data_s[6].IN1 +i_data_s[7] => i_data_s[7].IN1 +i_valid_s => i_valid_s.IN1 +o_ready_s <= uart_tx:uart_tx_inst.o_ready +o_data_m[0] <= uart_rx:uart_rx_inst.o_data +o_data_m[1] <= uart_rx:uart_rx_inst.o_data +o_data_m[2] <= uart_rx:uart_rx_inst.o_data +o_data_m[3] <= uart_rx:uart_rx_inst.o_data +o_data_m[4] <= uart_rx:uart_rx_inst.o_data +o_data_m[5] <= uart_rx:uart_rx_inst.o_data +o_data_m[6] <= uart_rx:uart_rx_inst.o_data +o_data_m[7] <= uart_rx:uart_rx_inst.o_data +o_valid_m <= uart_rx:uart_rx_inst.o_valid +i_ready_m => i_ready_m.IN1 +i_rxd => i_rxd.IN1 +o_txd <= uart_tx:uart_tx_inst.o_txd +o_tx_busy <= uart_tx:uart_tx_inst.o_busy +o_rx_busy <= uart_rx:uart_rx_inst.o_busy +o_rx_overrun_error <= uart_rx:uart_rx_inst.o_overrun_error +o_rx_frame_error <= uart_rx:uart_rx_inst.o_frame_error + + +|top|uart:u_uart|uart_tx:uart_tx_inst +clk => state.CLK +clk => timer[0].CLK +clk => timer[1].CLK +clk => timer[2].CLK +clk => timer[3].CLK +clk => timer[4].CLK +clk => timer[5].CLK +clk => timer[6].CLK +clk => timer[7].CLK +clk => timer[8].CLK +clk => timer[9].CLK +clk => timer[10].CLK +clk => timer[11].CLK +clk => timer[12].CLK +clk => timer[13].CLK +clk => timer[14].CLK +clk => timer[15].CLK +clk => timer[16].CLK +clk => timer[17].CLK +clk => timer[18].CLK +clk => bit_idx[0].CLK +clk => bit_idx[1].CLK +clk => bit_idx[2].CLK +clk => bit_idx[3].CLK +clk => data_reg[1].CLK +clk => data_reg[2].CLK +clk => data_reg[3].CLK +clk => data_reg[4].CLK +clk => data_reg[5].CLK +clk => data_reg[6].CLK +clk => data_reg[7].CLK +clk => data_reg[8].CLK +clk => data_reg[9].CLK +clk => o_busy~reg0.CLK +clk => o_txd~reg0.CLK +clk => o_ready~reg0.CLK +rst => o_ready.OUTPUTSELECT +rst => o_txd.OUTPUTSELECT +rst => o_busy.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => bit_idx.OUTPUTSELECT +rst => bit_idx.OUTPUTSELECT +rst => bit_idx.OUTPUTSELECT +rst => bit_idx.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => state.OUTPUTSELECT +i_data[0] => data_reg.DATAB +i_data[1] => data_reg.DATAB +i_data[2] => data_reg.DATAB +i_data[3] => data_reg.DATAB +i_data[4] => data_reg.DATAB +i_data[5] => data_reg.DATAB +i_data[6] => data_reg.DATAB +i_data[7] => data_reg.DATAB +i_valid => data_reg.OUTPUTSELECT +i_valid => data_reg.OUTPUTSELECT +i_valid => data_reg.OUTPUTSELECT +i_valid => data_reg.OUTPUTSELECT +i_valid => data_reg.OUTPUTSELECT +i_valid => data_reg.OUTPUTSELECT +i_valid => data_reg.OUTPUTSELECT +i_valid => data_reg.OUTPUTSELECT +i_valid => data_reg.OUTPUTSELECT +i_valid => bit_idx.OUTPUTSELECT +i_valid => bit_idx.OUTPUTSELECT +i_valid => bit_idx.OUTPUTSELECT +i_valid => bit_idx.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => timer.OUTPUTSELECT +i_valid => state.OUTPUTSELECT +i_valid => o_busy.DATAB +i_valid => o_ready.DATAB +i_valid => o_txd.DATAB +o_ready <= o_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_txd <= o_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_busy <= o_busy~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|top|uart:u_uart|uart_rx:uart_rx_inst +clk => data_reg[0].CLK +clk => data_reg[1].CLK +clk => data_reg[2].CLK +clk => data_reg[3].CLK +clk => data_reg[4].CLK +clk => data_reg[5].CLK +clk => data_reg[6].CLK +clk => data_reg[7].CLK +clk => bit_idx[0].CLK +clk => bit_idx[1].CLK +clk => bit_idx[2].CLK +clk => bit_idx[3].CLK +clk => timer[0].CLK +clk => timer[1].CLK +clk => timer[2].CLK +clk => timer[3].CLK +clk => timer[4].CLK +clk => timer[5].CLK +clk => timer[6].CLK +clk => timer[7].CLK +clk => timer[8].CLK +clk => timer[9].CLK +clk => timer[10].CLK +clk => timer[11].CLK +clk => timer[12].CLK +clk => timer[13].CLK +clk => timer[14].CLK +clk => timer[15].CLK +clk => timer[16].CLK +clk => timer[17].CLK +clk => timer[18].CLK +clk => rxd_q1_d.CLK +clk => rxd_q1.CLK +clk => rxd_q0.CLK +clk => o_frame_error~reg0.CLK +clk => o_overrun_error~reg0.CLK +clk => o_busy~reg0.CLK +clk => o_valid~reg0.CLK +clk => o_data[0]~reg0.CLK +clk => o_data[1]~reg0.CLK +clk => o_data[2]~reg0.CLK +clk => o_data[3]~reg0.CLK +clk => o_data[4]~reg0.CLK +clk => o_data[5]~reg0.CLK +clk => o_data[6]~reg0.CLK +clk => o_data[7]~reg0.CLK +clk => state~5.DATAIN +rst => o_data.OUTPUTSELECT +rst => o_data.OUTPUTSELECT +rst => o_data.OUTPUTSELECT +rst => o_data.OUTPUTSELECT +rst => o_data.OUTPUTSELECT +rst => o_data.OUTPUTSELECT +rst => o_data.OUTPUTSELECT +rst => o_data.OUTPUTSELECT +rst => o_valid.OUTPUTSELECT +rst => o_busy.OUTPUTSELECT +rst => o_overrun_error.OUTPUTSELECT +rst => o_frame_error.OUTPUTSELECT +rst => rxd_q0.OUTPUTSELECT +rst => rxd_q1.OUTPUTSELECT +rst => rxd_q1_d.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => timer.OUTPUTSELECT +rst => bit_idx.OUTPUTSELECT +rst => bit_idx.OUTPUTSELECT +rst => bit_idx.OUTPUTSELECT +rst => bit_idx.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +rst => data_reg.OUTPUTSELECT +o_data[0] <= o_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_data[1] <= o_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_data[2] <= o_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_data[3] <= o_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_data[4] <= o_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_data[5] <= o_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_data[6] <= o_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_data[7] <= o_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_valid <= o_valid~reg0.DB_MAX_OUTPUT_PORT_TYPE +i_ready => always0.IN1 +i_rxd => rxd_q0.DATAA +o_busy <= o_busy~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_overrun_error <= o_overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE +o_frame_error <= o_frame_error~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|top|uart_bus_master:u_master +clk => resp[6][0].CLK +clk => resp[6][1].CLK +clk => resp[6][2].CLK +clk => resp[6][3].CLK +clk => resp[6][4].CLK +clk => resp[6][5].CLK +clk => resp[6][6].CLK +clk => resp[6][7].CLK +clk => resp[5][0].CLK +clk => resp[5][1].CLK +clk => resp[5][2].CLK +clk => resp[5][3].CLK +clk => resp[5][4].CLK +clk => resp[5][5].CLK +clk => resp[5][6].CLK +clk => resp[5][7].CLK +clk => resp[4][0].CLK +clk => resp[4][1].CLK +clk => resp[4][2].CLK +clk => resp[4][3].CLK +clk => resp[4][4].CLK +clk => resp[4][5].CLK +clk => resp[4][6].CLK +clk => resp[4][7].CLK +clk => resp[3][0].CLK +clk => resp[3][1].CLK +clk => resp[3][2].CLK +clk => resp[3][3].CLK +clk => resp[3][4].CLK +clk => resp[3][5].CLK +clk => resp[3][6].CLK +clk => resp[3][7].CLK +clk => resp[2][0].CLK +clk => resp[2][1].CLK +clk => resp[2][2].CLK +clk => resp[2][3].CLK +clk => resp[2][4].CLK +clk => resp[2][5].CLK +clk => resp[2][6].CLK +clk => resp[2][7].CLK +clk => resp[1][0].CLK +clk => resp[1][1].CLK +clk => resp[1][2].CLK +clk => resp[1][3].CLK +clk => resp[1][4].CLK +clk => resp[1][5].CLK +clk => resp[1][6].CLK +clk => resp[1][7].CLK +clk => resp[0][0].CLK +clk => resp[0][1].CLK +clk => resp[0][2].CLK +clk => resp[0][3].CLK +clk => resp[0][4].CLK +clk => resp[0][5].CLK +clk => resp[0][6].CLK +clk => resp[0][7].CLK +clk => reg_idx[0].CLK +clk => reg_idx[1].CLK +clk => reg_idx[2].CLK +clk => reg_idx[3].CLK +clk => reg_idx[4].CLK +clk => hold_core~reg0.CLK +clk => resp_idx[0].CLK +clk => resp_idx[1].CLK +clk => resp_idx[2].CLK +clk => resp_len[0].CLK +clk => resp_len[1].CLK +clk => resp_len[2].CLK +clk => chk_calc[0].CLK +clk => chk_calc[1].CLK +clk => chk_calc[2].CLK +clk => chk_calc[3].CLK +clk => chk_calc[4].CLK +clk => chk_calc[5].CLK +clk => chk_calc[6].CLK +clk => chk_calc[7].CLK +clk => wdata[0].CLK +clk => wdata[1].CLK +clk => wdata[2].CLK +clk => wdata[3].CLK +clk => wdata[4].CLK +clk => wdata[5].CLK +clk => wdata[6].CLK +clk => wdata[7].CLK +clk => wdata[8].CLK +clk => wdata[9].CLK +clk => wdata[10].CLK +clk => wdata[11].CLK +clk => wdata[12].CLK +clk => wdata[13].CLK +clk => wdata[14].CLK +clk => wdata[15].CLK +clk => wdata[16].CLK +clk => wdata[17].CLK +clk => wdata[18].CLK +clk => wdata[19].CLK +clk => wdata[20].CLK +clk => wdata[21].CLK +clk => wdata[22].CLK +clk => wdata[23].CLK +clk => wdata[24].CLK +clk => wdata[25].CLK +clk => wdata[26].CLK +clk => wdata[27].CLK +clk => wdata[28].CLK +clk => wdata[29].CLK +clk => wdata[30].CLK +clk => wdata[31].CLK +clk => addr[0].CLK +clk => addr[1].CLK +clk => addr[2].CLK +clk => addr[3].CLK +clk => addr[4].CLK +clk => addr[5].CLK +clk => addr[6].CLK +clk => addr[7].CLK +clk => addr[8].CLK +clk => addr[9].CLK +clk => addr[10].CLK +clk => addr[11].CLK +clk => addr[12].CLK +clk => addr[13].CLK +clk => addr[14].CLK +clk => addr[15].CLK +clk => addr[16].CLK +clk => addr[17].CLK +clk => addr[18].CLK +clk => addr[19].CLK +clk => addr[20].CLK +clk => addr[21].CLK +clk => addr[22].CLK +clk => addr[23].CLK +clk => addr[24].CLK +clk => addr[25].CLK +clk => addr[26].CLK +clk => addr[27].CLK +clk => addr[28].CLK +clk => addr[29].CLK +clk => addr[30].CLK +clk => addr[31].CLK +clk => cmd[0].CLK +clk => cmd[1].CLK +clk => cmd[2].CLK +clk => cmd[3].CLK +clk => cmd[4].CLK +clk => cmd[5].CLK +clk => cmd[6].CLK +clk => cmd[7].CLK +clk => tx_valid~reg0.CLK +clk => tx_data[0]~reg0.CLK +clk => tx_data[1]~reg0.CLK +clk => tx_data[2]~reg0.CLK +clk => tx_data[3]~reg0.CLK +clk => tx_data[4]~reg0.CLK +clk => tx_data[5]~reg0.CLK +clk => tx_data[6]~reg0.CLK +clk => tx_data[7]~reg0.CLK +clk => bus_write_enable[0]~reg0.CLK +clk => bus_write_enable[1]~reg0.CLK +clk => bus_write_enable[2]~reg0.CLK +clk => bus_write_enable[3]~reg0.CLK +clk => bus_write_data[0]~reg0.CLK +clk => bus_write_data[1]~reg0.CLK +clk => bus_write_data[2]~reg0.CLK +clk => bus_write_data[3]~reg0.CLK +clk => bus_write_data[4]~reg0.CLK +clk => bus_write_data[5]~reg0.CLK +clk => bus_write_data[6]~reg0.CLK +clk => bus_write_data[7]~reg0.CLK +clk => bus_write_data[8]~reg0.CLK +clk => bus_write_data[9]~reg0.CLK +clk => bus_write_data[10]~reg0.CLK +clk => bus_write_data[11]~reg0.CLK +clk => bus_write_data[12]~reg0.CLK +clk => bus_write_data[13]~reg0.CLK +clk => bus_write_data[14]~reg0.CLK +clk => bus_write_data[15]~reg0.CLK +clk => bus_write_data[16]~reg0.CLK +clk => bus_write_data[17]~reg0.CLK +clk => bus_write_data[18]~reg0.CLK +clk => bus_write_data[19]~reg0.CLK +clk => bus_write_data[20]~reg0.CLK +clk => bus_write_data[21]~reg0.CLK +clk => bus_write_data[22]~reg0.CLK +clk => bus_write_data[23]~reg0.CLK +clk => bus_write_data[24]~reg0.CLK +clk => bus_write_data[25]~reg0.CLK +clk => bus_write_data[26]~reg0.CLK +clk => bus_write_data[27]~reg0.CLK +clk => bus_write_data[28]~reg0.CLK +clk => bus_write_data[29]~reg0.CLK +clk => bus_write_data[30]~reg0.CLK +clk => bus_write_data[31]~reg0.CLK +clk => bus_addr[0]~reg0.CLK +clk => bus_addr[1]~reg0.CLK +clk => bus_addr[2]~reg0.CLK +clk => bus_addr[3]~reg0.CLK +clk => bus_addr[4]~reg0.CLK +clk => bus_addr[5]~reg0.CLK +clk => bus_addr[6]~reg0.CLK +clk => bus_addr[7]~reg0.CLK +clk => bus_addr[8]~reg0.CLK +clk => bus_addr[9]~reg0.CLK +clk => bus_addr[10]~reg0.CLK +clk => bus_addr[11]~reg0.CLK +clk => bus_addr[12]~reg0.CLK +clk => bus_addr[13]~reg0.CLK +clk => bus_addr[14]~reg0.CLK +clk => bus_addr[15]~reg0.CLK +clk => bus_addr[16]~reg0.CLK +clk => bus_addr[17]~reg0.CLK +clk => bus_addr[18]~reg0.CLK +clk => bus_addr[19]~reg0.CLK +clk => bus_addr[20]~reg0.CLK +clk => bus_addr[21]~reg0.CLK +clk => bus_addr[22]~reg0.CLK +clk => bus_addr[23]~reg0.CLK +clk => bus_addr[24]~reg0.CLK +clk => bus_addr[25]~reg0.CLK +clk => bus_addr[26]~reg0.CLK +clk => bus_addr[27]~reg0.CLK +clk => bus_addr[28]~reg0.CLK +clk => bus_addr[29]~reg0.CLK +clk => bus_addr[30]~reg0.CLK +clk => bus_addr[31]~reg0.CLK +clk => state~16.DATAIN +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_addr.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_data.OUTPUTSELECT +rst => bus_write_enable.OUTPUTSELECT +rst => tx_data.OUTPUTSELECT +rst => tx_data.OUTPUTSELECT +rst => tx_data.OUTPUTSELECT +rst => tx_data.OUTPUTSELECT +rst => tx_data.OUTPUTSELECT +rst => tx_data.OUTPUTSELECT +rst => tx_data.OUTPUTSELECT +rst => tx_data.OUTPUTSELECT +rst => tx_valid.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => state.OUTPUTSELECT +rst => cmd.OUTPUTSELECT +rst => cmd.OUTPUTSELECT +rst => cmd.OUTPUTSELECT +rst => cmd.OUTPUTSELECT +rst => cmd.OUTPUTSELECT +rst => cmd.OUTPUTSELECT +rst => cmd.OUTPUTSELECT +rst => cmd.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => addr.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => wdata.OUTPUTSELECT +rst => chk_calc.OUTPUTSELECT +rst => chk_calc.OUTPUTSELECT +rst => chk_calc.OUTPUTSELECT +rst => chk_calc.OUTPUTSELECT +rst => chk_calc.OUTPUTSELECT +rst => chk_calc.OUTPUTSELECT +rst => chk_calc.OUTPUTSELECT +rst => chk_calc.OUTPUTSELECT +rst => resp_len.OUTPUTSELECT +rst => resp_len.OUTPUTSELECT +rst => resp_len.OUTPUTSELECT +rst => resp_idx.OUTPUTSELECT +rst => resp_idx.OUTPUTSELECT +rst => resp_idx.OUTPUTSELECT +rst => hold_core.OUTPUTSELECT +rst => resp[5][4].ENA +rst => resp[5][3].ENA +rst => resp[5][2].ENA +rst => resp[5][1].ENA +rst => resp[5][0].ENA +rst => resp[6][7].ENA +rst => resp[6][6].ENA +rst => resp[6][5].ENA +rst => resp[6][4].ENA +rst => resp[6][3].ENA +rst => resp[6][2].ENA +rst => resp[6][1].ENA +rst => resp[6][0].ENA +rst => resp[5][5].ENA +rst => resp[5][6].ENA +rst => resp[5][7].ENA +rst => resp[4][0].ENA +rst => resp[4][1].ENA +rst => resp[4][2].ENA +rst => resp[4][3].ENA +rst => resp[4][4].ENA +rst => resp[4][5].ENA +rst => resp[4][6].ENA +rst => resp[4][7].ENA +rst => resp[3][0].ENA +rst => resp[3][1].ENA +rst => resp[3][2].ENA +rst => resp[3][3].ENA +rst => resp[3][4].ENA +rst => resp[3][5].ENA +rst => resp[3][6].ENA +rst => resp[3][7].ENA +rst => resp[2][0].ENA +rst => resp[2][1].ENA +rst => resp[2][2].ENA +rst => resp[2][3].ENA +rst => resp[2][4].ENA +rst => resp[2][5].ENA +rst => resp[2][6].ENA +rst => resp[2][7].ENA +rst => resp[1][0].ENA +rst => resp[1][1].ENA +rst => resp[1][2].ENA +rst => resp[1][3].ENA +rst => resp[1][4].ENA +rst => resp[1][5].ENA +rst => resp[1][6].ENA +rst => resp[1][7].ENA +rst => resp[0][0].ENA +rst => resp[0][1].ENA +rst => resp[0][2].ENA +rst => resp[0][3].ENA +rst => resp[0][4].ENA +rst => resp[0][5].ENA +rst => resp[0][6].ENA +rst => resp[0][7].ENA +rst => reg_idx[0].ENA +rst => reg_idx[1].ENA +rst => reg_idx[2].ENA +rst => reg_idx[3].ENA +rst => reg_idx[4].ENA +rx_data[0] => cmd.DATAB +rx_data[0] => chk_calc.DATAB +rx_data[0] => chk_calc.IN1 +rx_data[0] => addr.DATAB +rx_data[0] => addr.DATAB +rx_data[0] => addr.DATAB +rx_data[0] => addr.DATAB +rx_data[0] => wdata.DATAB +rx_data[0] => wdata.DATAB +rx_data[0] => wdata.DATAB +rx_data[0] => wdata.DATAB +rx_data[0] => reg_idx.DATAB +rx_data[0] => Equal6.IN7 +rx_data[0] => Equal1.IN3 +rx_data[0] => Equal2.IN7 +rx_data[0] => Equal3.IN2 +rx_data[0] => Equal4.IN7 +rx_data[1] => cmd.DATAB +rx_data[1] => chk_calc.DATAB +rx_data[1] => chk_calc.IN1 +rx_data[1] => addr.DATAB +rx_data[1] => addr.DATAB +rx_data[1] => addr.DATAB +rx_data[1] => addr.DATAB +rx_data[1] => wdata.DATAB +rx_data[1] => wdata.DATAB +rx_data[1] => wdata.DATAB +rx_data[1] => wdata.DATAB +rx_data[1] => reg_idx.DATAB +rx_data[1] => Equal6.IN6 +rx_data[1] => Equal1.IN7 +rx_data[1] => Equal2.IN1 +rx_data[1] => Equal3.IN1 +rx_data[1] => Equal4.IN6 +rx_data[2] => cmd.DATAB +rx_data[2] => chk_calc.DATAB +rx_data[2] => chk_calc.IN1 +rx_data[2] => addr.DATAB +rx_data[2] => addr.DATAB +rx_data[2] => addr.DATAB +rx_data[2] => addr.DATAB +rx_data[2] => wdata.DATAB +rx_data[2] => wdata.DATAB +rx_data[2] => wdata.DATAB +rx_data[2] => wdata.DATAB +rx_data[2] => reg_idx.DATAB +rx_data[2] => Equal6.IN5 +rx_data[2] => Equal1.IN2 +rx_data[2] => Equal2.IN6 +rx_data[2] => Equal3.IN7 +rx_data[2] => Equal4.IN1 +rx_data[3] => cmd.DATAB +rx_data[3] => chk_calc.DATAB +rx_data[3] => chk_calc.IN1 +rx_data[3] => addr.DATAB +rx_data[3] => addr.DATAB +rx_data[3] => addr.DATAB +rx_data[3] => addr.DATAB +rx_data[3] => wdata.DATAB +rx_data[3] => wdata.DATAB +rx_data[3] => wdata.DATAB +rx_data[3] => wdata.DATAB +rx_data[3] => reg_idx.DATAB +rx_data[3] => Equal6.IN4 +rx_data[3] => Equal1.IN6 +rx_data[3] => Equal2.IN5 +rx_data[3] => Equal3.IN6 +rx_data[3] => Equal4.IN5 +rx_data[4] => cmd.DATAB +rx_data[4] => chk_calc.DATAB +rx_data[4] => chk_calc.IN1 +rx_data[4] => addr.DATAB +rx_data[4] => addr.DATAB +rx_data[4] => addr.DATAB +rx_data[4] => addr.DATAB +rx_data[4] => wdata.DATAB +rx_data[4] => wdata.DATAB +rx_data[4] => wdata.DATAB +rx_data[4] => wdata.DATAB +rx_data[4] => reg_idx.DATAB +rx_data[4] => Equal6.IN3 +rx_data[4] => Equal1.IN5 +rx_data[4] => Equal2.IN0 +rx_data[4] => Equal3.IN0 +rx_data[4] => Equal4.IN0 +rx_data[5] => cmd.DATAB +rx_data[5] => chk_calc.DATAB +rx_data[5] => chk_calc.IN1 +rx_data[5] => addr.DATAB +rx_data[5] => addr.DATAB +rx_data[5] => addr.DATAB +rx_data[5] => addr.DATAB +rx_data[5] => wdata.DATAB +rx_data[5] => wdata.DATAB +rx_data[5] => wdata.DATAB +rx_data[5] => wdata.DATAB +rx_data[5] => Equal6.IN2 +rx_data[5] => Equal1.IN1 +rx_data[5] => Equal2.IN4 +rx_data[5] => Equal3.IN5 +rx_data[5] => Equal4.IN4 +rx_data[6] => cmd.DATAB +rx_data[6] => chk_calc.DATAB +rx_data[6] => chk_calc.IN1 +rx_data[6] => addr.DATAB +rx_data[6] => addr.DATAB +rx_data[6] => addr.DATAB +rx_data[6] => addr.DATAB +rx_data[6] => wdata.DATAB +rx_data[6] => wdata.DATAB +rx_data[6] => wdata.DATAB +rx_data[6] => wdata.DATAB +rx_data[6] => Equal6.IN1 +rx_data[6] => Equal1.IN4 +rx_data[6] => Equal2.IN3 +rx_data[6] => Equal3.IN4 +rx_data[6] => Equal4.IN3 +rx_data[7] => cmd.DATAB +rx_data[7] => chk_calc.DATAB +rx_data[7] => chk_calc.IN1 +rx_data[7] => addr.DATAB +rx_data[7] => addr.DATAB +rx_data[7] => addr.DATAB +rx_data[7] => addr.DATAB +rx_data[7] => wdata.DATAB +rx_data[7] => wdata.DATAB +rx_data[7] => wdata.DATAB +rx_data[7] => wdata.DATAB +rx_data[7] => Equal6.IN0 +rx_data[7] => Equal1.IN0 +rx_data[7] => Equal2.IN2 +rx_data[7] => Equal3.IN3 +rx_data[7] => Equal4.IN2 +rx_valid => always0.IN0 +rx_ready <= rx_ready.DB_MAX_OUTPUT_PORT_TYPE +tx_data[0] <= tx_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[1] <= tx_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[2] <= tx_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[3] <= tx_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[4] <= tx_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[5] <= tx_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[6] <= tx_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[7] <= tx_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_valid <= tx_valid~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_ready => always0.IN1 +tx_ready => always0.IN1 +bus_addr[0] <= bus_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[1] <= bus_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[2] <= bus_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[3] <= bus_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[4] <= bus_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[5] <= bus_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[6] <= bus_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[7] <= bus_addr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[8] <= bus_addr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[9] <= bus_addr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[10] <= bus_addr[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[11] <= bus_addr[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[12] <= bus_addr[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[13] <= bus_addr[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[14] <= bus_addr[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[15] <= bus_addr[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[16] <= bus_addr[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[17] <= bus_addr[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[18] <= bus_addr[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[19] <= bus_addr[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[20] <= bus_addr[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[21] <= bus_addr[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[22] <= bus_addr[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[23] <= bus_addr[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[24] <= bus_addr[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[25] <= bus_addr[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[26] <= bus_addr[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[27] <= bus_addr[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[28] <= bus_addr[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[29] <= bus_addr[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[30] <= bus_addr[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_addr[31] <= bus_addr[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[0] <= bus_write_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[1] <= bus_write_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[2] <= bus_write_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[3] <= bus_write_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[4] <= bus_write_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[5] <= bus_write_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[6] <= bus_write_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[7] <= bus_write_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[8] <= bus_write_data[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[9] <= bus_write_data[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[10] <= bus_write_data[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[11] <= bus_write_data[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[12] <= bus_write_data[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[13] <= bus_write_data[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[14] <= bus_write_data[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[15] <= bus_write_data[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[16] <= bus_write_data[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[17] <= bus_write_data[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[18] <= bus_write_data[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[19] <= bus_write_data[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[20] <= bus_write_data[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[21] <= bus_write_data[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[22] <= bus_write_data[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[23] <= bus_write_data[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[24] <= bus_write_data[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[25] <= bus_write_data[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[26] <= bus_write_data[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[27] <= bus_write_data[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[28] <= bus_write_data[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[29] <= bus_write_data[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[30] <= bus_write_data[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_data[31] <= bus_write_data[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_enable[0] <= bus_write_enable[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_enable[1] <= bus_write_enable[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_enable[2] <= bus_write_enable[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_write_enable[3] <= bus_write_enable[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +bus_read_data[0] => Selector151.IN3 +bus_read_data[0] => resp.IN0 +bus_read_data[1] => resp.IN0 +bus_read_data[1] => Selector150.IN3 +bus_read_data[2] => resp.IN0 +bus_read_data[2] => Selector149.IN3 +bus_read_data[3] => resp.IN0 +bus_read_data[3] => Selector148.IN3 +bus_read_data[4] => Selector147.IN3 +bus_read_data[4] => resp.IN0 +bus_read_data[5] => resp.IN0 +bus_read_data[5] => Selector146.IN3 +bus_read_data[6] => resp.IN0 +bus_read_data[6] => Selector145.IN3 +bus_read_data[7] => Selector144.IN3 +bus_read_data[7] => resp.IN0 +bus_read_data[8] => resp.IN1 +bus_read_data[8] => Selector159.IN3 +bus_read_data[9] => resp.IN1 +bus_read_data[9] => Selector158.IN3 +bus_read_data[10] => resp.IN1 +bus_read_data[10] => Selector157.IN3 +bus_read_data[11] => resp.IN1 +bus_read_data[11] => Selector156.IN3 +bus_read_data[12] => resp.IN1 +bus_read_data[12] => Selector155.IN3 +bus_read_data[13] => resp.IN1 +bus_read_data[13] => Selector154.IN3 +bus_read_data[14] => resp.IN1 +bus_read_data[14] => Selector153.IN3 +bus_read_data[15] => resp.IN1 +bus_read_data[15] => Selector152.IN3 +bus_read_data[16] => resp.IN1 +bus_read_data[16] => Selector167.IN2 +bus_read_data[17] => resp.IN1 +bus_read_data[17] => Selector166.IN2 +bus_read_data[18] => resp.IN1 +bus_read_data[18] => Selector165.IN2 +bus_read_data[19] => resp.IN1 +bus_read_data[19] => Selector164.IN2 +bus_read_data[20] => resp.IN1 +bus_read_data[20] => Selector163.IN2 +bus_read_data[21] => resp.IN1 +bus_read_data[21] => Selector162.IN2 +bus_read_data[22] => resp.IN1 +bus_read_data[22] => Selector161.IN2 +bus_read_data[23] => resp.IN1 +bus_read_data[23] => Selector160.IN2 +bus_read_data[24] => resp.IN1 +bus_read_data[24] => Selector175.IN2 +bus_read_data[25] => resp.IN1 +bus_read_data[25] => Selector174.IN2 +bus_read_data[26] => resp.IN1 +bus_read_data[26] => Selector173.IN2 +bus_read_data[27] => resp.IN1 +bus_read_data[27] => Selector172.IN2 +bus_read_data[28] => resp.IN1 +bus_read_data[28] => Selector171.IN2 +bus_read_data[29] => resp.IN1 +bus_read_data[29] => Selector170.IN2 +bus_read_data[30] => resp.IN1 +bus_read_data[30] => Selector169.IN2 +bus_read_data[31] => resp.IN1 +bus_read_data[31] => Selector168.IN2 +hold_core <= hold_core~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][0] => Mux39.IN31 +dbg_regs[31][1] => Mux38.IN31 +dbg_regs[31][2] => Mux37.IN31 +dbg_regs[31][3] => Mux36.IN31 +dbg_regs[31][4] => Mux35.IN31 +dbg_regs[31][5] => Mux34.IN31 +dbg_regs[31][6] => Mux33.IN31 +dbg_regs[31][7] => Mux32.IN31 +dbg_regs[31][8] => Mux31.IN31 +dbg_regs[31][9] => Mux30.IN31 +dbg_regs[31][10] => Mux29.IN31 +dbg_regs[31][11] => Mux28.IN31 +dbg_regs[31][12] => Mux27.IN31 +dbg_regs[31][13] => Mux26.IN31 +dbg_regs[31][14] => Mux25.IN31 +dbg_regs[31][15] => Mux24.IN31 +dbg_regs[31][16] => Mux23.IN31 +dbg_regs[31][17] => Mux22.IN31 +dbg_regs[31][18] => Mux21.IN31 +dbg_regs[31][19] => Mux20.IN31 +dbg_regs[31][20] => Mux19.IN31 +dbg_regs[31][21] => Mux18.IN31 +dbg_regs[31][22] => Mux17.IN31 +dbg_regs[31][23] => Mux16.IN31 +dbg_regs[31][24] => Mux15.IN31 +dbg_regs[31][25] => Mux14.IN31 +dbg_regs[31][26] => Mux13.IN31 +dbg_regs[31][27] => Mux12.IN31 +dbg_regs[31][28] => Mux11.IN31 +dbg_regs[31][29] => Mux10.IN31 +dbg_regs[31][30] => Mux9.IN31 +dbg_regs[31][31] => Mux8.IN31 +dbg_regs[30][0] => Mux39.IN30 +dbg_regs[30][1] => Mux38.IN30 +dbg_regs[30][2] => Mux37.IN30 +dbg_regs[30][3] => Mux36.IN30 +dbg_regs[30][4] => Mux35.IN30 +dbg_regs[30][5] => Mux34.IN30 +dbg_regs[30][6] => Mux33.IN30 +dbg_regs[30][7] => Mux32.IN30 +dbg_regs[30][8] => Mux31.IN30 +dbg_regs[30][9] => Mux30.IN30 +dbg_regs[30][10] => Mux29.IN30 +dbg_regs[30][11] => Mux28.IN30 +dbg_regs[30][12] => Mux27.IN30 +dbg_regs[30][13] => Mux26.IN30 +dbg_regs[30][14] => Mux25.IN30 +dbg_regs[30][15] => Mux24.IN30 +dbg_regs[30][16] => Mux23.IN30 +dbg_regs[30][17] => Mux22.IN30 +dbg_regs[30][18] => Mux21.IN30 +dbg_regs[30][19] => Mux20.IN30 +dbg_regs[30][20] => Mux19.IN30 +dbg_regs[30][21] => Mux18.IN30 +dbg_regs[30][22] => Mux17.IN30 +dbg_regs[30][23] => Mux16.IN30 +dbg_regs[30][24] => Mux15.IN30 +dbg_regs[30][25] => Mux14.IN30 +dbg_regs[30][26] => Mux13.IN30 +dbg_regs[30][27] => Mux12.IN30 +dbg_regs[30][28] => Mux11.IN30 +dbg_regs[30][29] => Mux10.IN30 +dbg_regs[30][30] => Mux9.IN30 +dbg_regs[30][31] => Mux8.IN30 +dbg_regs[29][0] => Mux39.IN29 +dbg_regs[29][1] => Mux38.IN29 +dbg_regs[29][2] => Mux37.IN29 +dbg_regs[29][3] => Mux36.IN29 +dbg_regs[29][4] => Mux35.IN29 +dbg_regs[29][5] => Mux34.IN29 +dbg_regs[29][6] => Mux33.IN29 +dbg_regs[29][7] => Mux32.IN29 +dbg_regs[29][8] => Mux31.IN29 +dbg_regs[29][9] => Mux30.IN29 +dbg_regs[29][10] => Mux29.IN29 +dbg_regs[29][11] => Mux28.IN29 +dbg_regs[29][12] => Mux27.IN29 +dbg_regs[29][13] => Mux26.IN29 +dbg_regs[29][14] => Mux25.IN29 +dbg_regs[29][15] => Mux24.IN29 +dbg_regs[29][16] => Mux23.IN29 +dbg_regs[29][17] => Mux22.IN29 +dbg_regs[29][18] => Mux21.IN29 +dbg_regs[29][19] => Mux20.IN29 +dbg_regs[29][20] => Mux19.IN29 +dbg_regs[29][21] => Mux18.IN29 +dbg_regs[29][22] => Mux17.IN29 +dbg_regs[29][23] => Mux16.IN29 +dbg_regs[29][24] => Mux15.IN29 +dbg_regs[29][25] => Mux14.IN29 +dbg_regs[29][26] => Mux13.IN29 +dbg_regs[29][27] => Mux12.IN29 +dbg_regs[29][28] => Mux11.IN29 +dbg_regs[29][29] => Mux10.IN29 +dbg_regs[29][30] => Mux9.IN29 +dbg_regs[29][31] => Mux8.IN29 +dbg_regs[28][0] => Mux39.IN28 +dbg_regs[28][1] => Mux38.IN28 +dbg_regs[28][2] => Mux37.IN28 +dbg_regs[28][3] => Mux36.IN28 +dbg_regs[28][4] => Mux35.IN28 +dbg_regs[28][5] => Mux34.IN28 +dbg_regs[28][6] => Mux33.IN28 +dbg_regs[28][7] => Mux32.IN28 +dbg_regs[28][8] => Mux31.IN28 +dbg_regs[28][9] => Mux30.IN28 +dbg_regs[28][10] => Mux29.IN28 +dbg_regs[28][11] => Mux28.IN28 +dbg_regs[28][12] => Mux27.IN28 +dbg_regs[28][13] => Mux26.IN28 +dbg_regs[28][14] => Mux25.IN28 +dbg_regs[28][15] => Mux24.IN28 +dbg_regs[28][16] => Mux23.IN28 +dbg_regs[28][17] => Mux22.IN28 +dbg_regs[28][18] => Mux21.IN28 +dbg_regs[28][19] => Mux20.IN28 +dbg_regs[28][20] => Mux19.IN28 +dbg_regs[28][21] => Mux18.IN28 +dbg_regs[28][22] => Mux17.IN28 +dbg_regs[28][23] => Mux16.IN28 +dbg_regs[28][24] => Mux15.IN28 +dbg_regs[28][25] => Mux14.IN28 +dbg_regs[28][26] => Mux13.IN28 +dbg_regs[28][27] => Mux12.IN28 +dbg_regs[28][28] => Mux11.IN28 +dbg_regs[28][29] => Mux10.IN28 +dbg_regs[28][30] => Mux9.IN28 +dbg_regs[28][31] => Mux8.IN28 +dbg_regs[27][0] => Mux39.IN27 +dbg_regs[27][1] => Mux38.IN27 +dbg_regs[27][2] => Mux37.IN27 +dbg_regs[27][3] => Mux36.IN27 +dbg_regs[27][4] => Mux35.IN27 +dbg_regs[27][5] => Mux34.IN27 +dbg_regs[27][6] => Mux33.IN27 +dbg_regs[27][7] => Mux32.IN27 +dbg_regs[27][8] => Mux31.IN27 +dbg_regs[27][9] => Mux30.IN27 +dbg_regs[27][10] => Mux29.IN27 +dbg_regs[27][11] => Mux28.IN27 +dbg_regs[27][12] => Mux27.IN27 +dbg_regs[27][13] => Mux26.IN27 +dbg_regs[27][14] => Mux25.IN27 +dbg_regs[27][15] => Mux24.IN27 +dbg_regs[27][16] => Mux23.IN27 +dbg_regs[27][17] => Mux22.IN27 +dbg_regs[27][18] => Mux21.IN27 +dbg_regs[27][19] => Mux20.IN27 +dbg_regs[27][20] => Mux19.IN27 +dbg_regs[27][21] => Mux18.IN27 +dbg_regs[27][22] => Mux17.IN27 +dbg_regs[27][23] => Mux16.IN27 +dbg_regs[27][24] => Mux15.IN27 +dbg_regs[27][25] => Mux14.IN27 +dbg_regs[27][26] => Mux13.IN27 +dbg_regs[27][27] => Mux12.IN27 +dbg_regs[27][28] => Mux11.IN27 +dbg_regs[27][29] => Mux10.IN27 +dbg_regs[27][30] => Mux9.IN27 +dbg_regs[27][31] => Mux8.IN27 +dbg_regs[26][0] => Mux39.IN26 +dbg_regs[26][1] => Mux38.IN26 +dbg_regs[26][2] => Mux37.IN26 +dbg_regs[26][3] => Mux36.IN26 +dbg_regs[26][4] => Mux35.IN26 +dbg_regs[26][5] => Mux34.IN26 +dbg_regs[26][6] => Mux33.IN26 +dbg_regs[26][7] => Mux32.IN26 +dbg_regs[26][8] => Mux31.IN26 +dbg_regs[26][9] => Mux30.IN26 +dbg_regs[26][10] => Mux29.IN26 +dbg_regs[26][11] => Mux28.IN26 +dbg_regs[26][12] => Mux27.IN26 +dbg_regs[26][13] => Mux26.IN26 +dbg_regs[26][14] => Mux25.IN26 +dbg_regs[26][15] => Mux24.IN26 +dbg_regs[26][16] => Mux23.IN26 +dbg_regs[26][17] => Mux22.IN26 +dbg_regs[26][18] => Mux21.IN26 +dbg_regs[26][19] => Mux20.IN26 +dbg_regs[26][20] => Mux19.IN26 +dbg_regs[26][21] => Mux18.IN26 +dbg_regs[26][22] => Mux17.IN26 +dbg_regs[26][23] => Mux16.IN26 +dbg_regs[26][24] => Mux15.IN26 +dbg_regs[26][25] => Mux14.IN26 +dbg_regs[26][26] => Mux13.IN26 +dbg_regs[26][27] => Mux12.IN26 +dbg_regs[26][28] => Mux11.IN26 +dbg_regs[26][29] => Mux10.IN26 +dbg_regs[26][30] => Mux9.IN26 +dbg_regs[26][31] => Mux8.IN26 +dbg_regs[25][0] => Mux39.IN25 +dbg_regs[25][1] => Mux38.IN25 +dbg_regs[25][2] => Mux37.IN25 +dbg_regs[25][3] => Mux36.IN25 +dbg_regs[25][4] => Mux35.IN25 +dbg_regs[25][5] => Mux34.IN25 +dbg_regs[25][6] => Mux33.IN25 +dbg_regs[25][7] => Mux32.IN25 +dbg_regs[25][8] => Mux31.IN25 +dbg_regs[25][9] => Mux30.IN25 +dbg_regs[25][10] => Mux29.IN25 +dbg_regs[25][11] => Mux28.IN25 +dbg_regs[25][12] => Mux27.IN25 +dbg_regs[25][13] => Mux26.IN25 +dbg_regs[25][14] => Mux25.IN25 +dbg_regs[25][15] => Mux24.IN25 +dbg_regs[25][16] => Mux23.IN25 +dbg_regs[25][17] => Mux22.IN25 +dbg_regs[25][18] => Mux21.IN25 +dbg_regs[25][19] => Mux20.IN25 +dbg_regs[25][20] => Mux19.IN25 +dbg_regs[25][21] => Mux18.IN25 +dbg_regs[25][22] => Mux17.IN25 +dbg_regs[25][23] => Mux16.IN25 +dbg_regs[25][24] => Mux15.IN25 +dbg_regs[25][25] => Mux14.IN25 +dbg_regs[25][26] => Mux13.IN25 +dbg_regs[25][27] => Mux12.IN25 +dbg_regs[25][28] => Mux11.IN25 +dbg_regs[25][29] => Mux10.IN25 +dbg_regs[25][30] => Mux9.IN25 +dbg_regs[25][31] => Mux8.IN25 +dbg_regs[24][0] => Mux39.IN24 +dbg_regs[24][1] => Mux38.IN24 +dbg_regs[24][2] => Mux37.IN24 +dbg_regs[24][3] => Mux36.IN24 +dbg_regs[24][4] => Mux35.IN24 +dbg_regs[24][5] => Mux34.IN24 +dbg_regs[24][6] => Mux33.IN24 +dbg_regs[24][7] => Mux32.IN24 +dbg_regs[24][8] => Mux31.IN24 +dbg_regs[24][9] => Mux30.IN24 +dbg_regs[24][10] => Mux29.IN24 +dbg_regs[24][11] => Mux28.IN24 +dbg_regs[24][12] => Mux27.IN24 +dbg_regs[24][13] => Mux26.IN24 +dbg_regs[24][14] => Mux25.IN24 +dbg_regs[24][15] => Mux24.IN24 +dbg_regs[24][16] => Mux23.IN24 +dbg_regs[24][17] => Mux22.IN24 +dbg_regs[24][18] => Mux21.IN24 +dbg_regs[24][19] => Mux20.IN24 +dbg_regs[24][20] => Mux19.IN24 +dbg_regs[24][21] => Mux18.IN24 +dbg_regs[24][22] => Mux17.IN24 +dbg_regs[24][23] => Mux16.IN24 +dbg_regs[24][24] => Mux15.IN24 +dbg_regs[24][25] => Mux14.IN24 +dbg_regs[24][26] => Mux13.IN24 +dbg_regs[24][27] => Mux12.IN24 +dbg_regs[24][28] => Mux11.IN24 +dbg_regs[24][29] => Mux10.IN24 +dbg_regs[24][30] => Mux9.IN24 +dbg_regs[24][31] => Mux8.IN24 +dbg_regs[23][0] => Mux39.IN23 +dbg_regs[23][1] => Mux38.IN23 +dbg_regs[23][2] => Mux37.IN23 +dbg_regs[23][3] => Mux36.IN23 +dbg_regs[23][4] => Mux35.IN23 +dbg_regs[23][5] => Mux34.IN23 +dbg_regs[23][6] => Mux33.IN23 +dbg_regs[23][7] => Mux32.IN23 +dbg_regs[23][8] => Mux31.IN23 +dbg_regs[23][9] => Mux30.IN23 +dbg_regs[23][10] => Mux29.IN23 +dbg_regs[23][11] => Mux28.IN23 +dbg_regs[23][12] => Mux27.IN23 +dbg_regs[23][13] => Mux26.IN23 +dbg_regs[23][14] => Mux25.IN23 +dbg_regs[23][15] => Mux24.IN23 +dbg_regs[23][16] => Mux23.IN23 +dbg_regs[23][17] => Mux22.IN23 +dbg_regs[23][18] => Mux21.IN23 +dbg_regs[23][19] => Mux20.IN23 +dbg_regs[23][20] => Mux19.IN23 +dbg_regs[23][21] => Mux18.IN23 +dbg_regs[23][22] => Mux17.IN23 +dbg_regs[23][23] => Mux16.IN23 +dbg_regs[23][24] => Mux15.IN23 +dbg_regs[23][25] => Mux14.IN23 +dbg_regs[23][26] => Mux13.IN23 +dbg_regs[23][27] => Mux12.IN23 +dbg_regs[23][28] => Mux11.IN23 +dbg_regs[23][29] => Mux10.IN23 +dbg_regs[23][30] => Mux9.IN23 +dbg_regs[23][31] => Mux8.IN23 +dbg_regs[22][0] => Mux39.IN22 +dbg_regs[22][1] => Mux38.IN22 +dbg_regs[22][2] => Mux37.IN22 +dbg_regs[22][3] => Mux36.IN22 +dbg_regs[22][4] => Mux35.IN22 +dbg_regs[22][5] => Mux34.IN22 +dbg_regs[22][6] => Mux33.IN22 +dbg_regs[22][7] => Mux32.IN22 +dbg_regs[22][8] => Mux31.IN22 +dbg_regs[22][9] => Mux30.IN22 +dbg_regs[22][10] => Mux29.IN22 +dbg_regs[22][11] => Mux28.IN22 +dbg_regs[22][12] => Mux27.IN22 +dbg_regs[22][13] => Mux26.IN22 +dbg_regs[22][14] => Mux25.IN22 +dbg_regs[22][15] => Mux24.IN22 +dbg_regs[22][16] => Mux23.IN22 +dbg_regs[22][17] => Mux22.IN22 +dbg_regs[22][18] => Mux21.IN22 +dbg_regs[22][19] => Mux20.IN22 +dbg_regs[22][20] => Mux19.IN22 +dbg_regs[22][21] => Mux18.IN22 +dbg_regs[22][22] => Mux17.IN22 +dbg_regs[22][23] => Mux16.IN22 +dbg_regs[22][24] => Mux15.IN22 +dbg_regs[22][25] => Mux14.IN22 +dbg_regs[22][26] => Mux13.IN22 +dbg_regs[22][27] => Mux12.IN22 +dbg_regs[22][28] => Mux11.IN22 +dbg_regs[22][29] => Mux10.IN22 +dbg_regs[22][30] => Mux9.IN22 +dbg_regs[22][31] => Mux8.IN22 +dbg_regs[21][0] => Mux39.IN21 +dbg_regs[21][1] => Mux38.IN21 +dbg_regs[21][2] => Mux37.IN21 +dbg_regs[21][3] => Mux36.IN21 +dbg_regs[21][4] => Mux35.IN21 +dbg_regs[21][5] => Mux34.IN21 +dbg_regs[21][6] => Mux33.IN21 +dbg_regs[21][7] => Mux32.IN21 +dbg_regs[21][8] => Mux31.IN21 +dbg_regs[21][9] => Mux30.IN21 +dbg_regs[21][10] => Mux29.IN21 +dbg_regs[21][11] => Mux28.IN21 +dbg_regs[21][12] => Mux27.IN21 +dbg_regs[21][13] => Mux26.IN21 +dbg_regs[21][14] => Mux25.IN21 +dbg_regs[21][15] => Mux24.IN21 +dbg_regs[21][16] => Mux23.IN21 +dbg_regs[21][17] => Mux22.IN21 +dbg_regs[21][18] => Mux21.IN21 +dbg_regs[21][19] => Mux20.IN21 +dbg_regs[21][20] => Mux19.IN21 +dbg_regs[21][21] => Mux18.IN21 +dbg_regs[21][22] => Mux17.IN21 +dbg_regs[21][23] => Mux16.IN21 +dbg_regs[21][24] => Mux15.IN21 +dbg_regs[21][25] => Mux14.IN21 +dbg_regs[21][26] => Mux13.IN21 +dbg_regs[21][27] => Mux12.IN21 +dbg_regs[21][28] => Mux11.IN21 +dbg_regs[21][29] => Mux10.IN21 +dbg_regs[21][30] => Mux9.IN21 +dbg_regs[21][31] => Mux8.IN21 +dbg_regs[20][0] => Mux39.IN20 +dbg_regs[20][1] => Mux38.IN20 +dbg_regs[20][2] => Mux37.IN20 +dbg_regs[20][3] => Mux36.IN20 +dbg_regs[20][4] => Mux35.IN20 +dbg_regs[20][5] => Mux34.IN20 +dbg_regs[20][6] => Mux33.IN20 +dbg_regs[20][7] => Mux32.IN20 +dbg_regs[20][8] => Mux31.IN20 +dbg_regs[20][9] => Mux30.IN20 +dbg_regs[20][10] => Mux29.IN20 +dbg_regs[20][11] => Mux28.IN20 +dbg_regs[20][12] => Mux27.IN20 +dbg_regs[20][13] => Mux26.IN20 +dbg_regs[20][14] => Mux25.IN20 +dbg_regs[20][15] => Mux24.IN20 +dbg_regs[20][16] => Mux23.IN20 +dbg_regs[20][17] => Mux22.IN20 +dbg_regs[20][18] => Mux21.IN20 +dbg_regs[20][19] => Mux20.IN20 +dbg_regs[20][20] => Mux19.IN20 +dbg_regs[20][21] => Mux18.IN20 +dbg_regs[20][22] => Mux17.IN20 +dbg_regs[20][23] => Mux16.IN20 +dbg_regs[20][24] => Mux15.IN20 +dbg_regs[20][25] => Mux14.IN20 +dbg_regs[20][26] => Mux13.IN20 +dbg_regs[20][27] => Mux12.IN20 +dbg_regs[20][28] => Mux11.IN20 +dbg_regs[20][29] => Mux10.IN20 +dbg_regs[20][30] => Mux9.IN20 +dbg_regs[20][31] => Mux8.IN20 +dbg_regs[19][0] => Mux39.IN19 +dbg_regs[19][1] => Mux38.IN19 +dbg_regs[19][2] => Mux37.IN19 +dbg_regs[19][3] => Mux36.IN19 +dbg_regs[19][4] => Mux35.IN19 +dbg_regs[19][5] => Mux34.IN19 +dbg_regs[19][6] => Mux33.IN19 +dbg_regs[19][7] => Mux32.IN19 +dbg_regs[19][8] => Mux31.IN19 +dbg_regs[19][9] => Mux30.IN19 +dbg_regs[19][10] => Mux29.IN19 +dbg_regs[19][11] => Mux28.IN19 +dbg_regs[19][12] => Mux27.IN19 +dbg_regs[19][13] => Mux26.IN19 +dbg_regs[19][14] => Mux25.IN19 +dbg_regs[19][15] => Mux24.IN19 +dbg_regs[19][16] => Mux23.IN19 +dbg_regs[19][17] => Mux22.IN19 +dbg_regs[19][18] => Mux21.IN19 +dbg_regs[19][19] => Mux20.IN19 +dbg_regs[19][20] => Mux19.IN19 +dbg_regs[19][21] => Mux18.IN19 +dbg_regs[19][22] => Mux17.IN19 +dbg_regs[19][23] => Mux16.IN19 +dbg_regs[19][24] => Mux15.IN19 +dbg_regs[19][25] => Mux14.IN19 +dbg_regs[19][26] => Mux13.IN19 +dbg_regs[19][27] => Mux12.IN19 +dbg_regs[19][28] => Mux11.IN19 +dbg_regs[19][29] => Mux10.IN19 +dbg_regs[19][30] => Mux9.IN19 +dbg_regs[19][31] => Mux8.IN19 +dbg_regs[18][0] => Mux39.IN18 +dbg_regs[18][1] => Mux38.IN18 +dbg_regs[18][2] => Mux37.IN18 +dbg_regs[18][3] => Mux36.IN18 +dbg_regs[18][4] => Mux35.IN18 +dbg_regs[18][5] => Mux34.IN18 +dbg_regs[18][6] => Mux33.IN18 +dbg_regs[18][7] => Mux32.IN18 +dbg_regs[18][8] => Mux31.IN18 +dbg_regs[18][9] => Mux30.IN18 +dbg_regs[18][10] => Mux29.IN18 +dbg_regs[18][11] => Mux28.IN18 +dbg_regs[18][12] => Mux27.IN18 +dbg_regs[18][13] => Mux26.IN18 +dbg_regs[18][14] => Mux25.IN18 +dbg_regs[18][15] => Mux24.IN18 +dbg_regs[18][16] => Mux23.IN18 +dbg_regs[18][17] => Mux22.IN18 +dbg_regs[18][18] => Mux21.IN18 +dbg_regs[18][19] => Mux20.IN18 +dbg_regs[18][20] => Mux19.IN18 +dbg_regs[18][21] => Mux18.IN18 +dbg_regs[18][22] => Mux17.IN18 +dbg_regs[18][23] => Mux16.IN18 +dbg_regs[18][24] => Mux15.IN18 +dbg_regs[18][25] => Mux14.IN18 +dbg_regs[18][26] => Mux13.IN18 +dbg_regs[18][27] => Mux12.IN18 +dbg_regs[18][28] => Mux11.IN18 +dbg_regs[18][29] => Mux10.IN18 +dbg_regs[18][30] => Mux9.IN18 +dbg_regs[18][31] => Mux8.IN18 +dbg_regs[17][0] => Mux39.IN17 +dbg_regs[17][1] => Mux38.IN17 +dbg_regs[17][2] => Mux37.IN17 +dbg_regs[17][3] => Mux36.IN17 +dbg_regs[17][4] => Mux35.IN17 +dbg_regs[17][5] => Mux34.IN17 +dbg_regs[17][6] => Mux33.IN17 +dbg_regs[17][7] => Mux32.IN17 +dbg_regs[17][8] => Mux31.IN17 +dbg_regs[17][9] => Mux30.IN17 +dbg_regs[17][10] => Mux29.IN17 +dbg_regs[17][11] => Mux28.IN17 +dbg_regs[17][12] => Mux27.IN17 +dbg_regs[17][13] => Mux26.IN17 +dbg_regs[17][14] => Mux25.IN17 +dbg_regs[17][15] => Mux24.IN17 +dbg_regs[17][16] => Mux23.IN17 +dbg_regs[17][17] => Mux22.IN17 +dbg_regs[17][18] => Mux21.IN17 +dbg_regs[17][19] => Mux20.IN17 +dbg_regs[17][20] => Mux19.IN17 +dbg_regs[17][21] => Mux18.IN17 +dbg_regs[17][22] => Mux17.IN17 +dbg_regs[17][23] => Mux16.IN17 +dbg_regs[17][24] => Mux15.IN17 +dbg_regs[17][25] => Mux14.IN17 +dbg_regs[17][26] => Mux13.IN17 +dbg_regs[17][27] => Mux12.IN17 +dbg_regs[17][28] => Mux11.IN17 +dbg_regs[17][29] => Mux10.IN17 +dbg_regs[17][30] => Mux9.IN17 +dbg_regs[17][31] => Mux8.IN17 +dbg_regs[16][0] => Mux39.IN16 +dbg_regs[16][1] => Mux38.IN16 +dbg_regs[16][2] => Mux37.IN16 +dbg_regs[16][3] => Mux36.IN16 +dbg_regs[16][4] => Mux35.IN16 +dbg_regs[16][5] => Mux34.IN16 +dbg_regs[16][6] => Mux33.IN16 +dbg_regs[16][7] => Mux32.IN16 +dbg_regs[16][8] => Mux31.IN16 +dbg_regs[16][9] => Mux30.IN16 +dbg_regs[16][10] => Mux29.IN16 +dbg_regs[16][11] => Mux28.IN16 +dbg_regs[16][12] => Mux27.IN16 +dbg_regs[16][13] => Mux26.IN16 +dbg_regs[16][14] => Mux25.IN16 +dbg_regs[16][15] => Mux24.IN16 +dbg_regs[16][16] => Mux23.IN16 +dbg_regs[16][17] => Mux22.IN16 +dbg_regs[16][18] => Mux21.IN16 +dbg_regs[16][19] => Mux20.IN16 +dbg_regs[16][20] => Mux19.IN16 +dbg_regs[16][21] => Mux18.IN16 +dbg_regs[16][22] => Mux17.IN16 +dbg_regs[16][23] => Mux16.IN16 +dbg_regs[16][24] => Mux15.IN16 +dbg_regs[16][25] => Mux14.IN16 +dbg_regs[16][26] => Mux13.IN16 +dbg_regs[16][27] => Mux12.IN16 +dbg_regs[16][28] => Mux11.IN16 +dbg_regs[16][29] => Mux10.IN16 +dbg_regs[16][30] => Mux9.IN16 +dbg_regs[16][31] => Mux8.IN16 +dbg_regs[15][0] => Mux39.IN15 +dbg_regs[15][1] => Mux38.IN15 +dbg_regs[15][2] => Mux37.IN15 +dbg_regs[15][3] => Mux36.IN15 +dbg_regs[15][4] => Mux35.IN15 +dbg_regs[15][5] => Mux34.IN15 +dbg_regs[15][6] => Mux33.IN15 +dbg_regs[15][7] => Mux32.IN15 +dbg_regs[15][8] => Mux31.IN15 +dbg_regs[15][9] => Mux30.IN15 +dbg_regs[15][10] => Mux29.IN15 +dbg_regs[15][11] => Mux28.IN15 +dbg_regs[15][12] => Mux27.IN15 +dbg_regs[15][13] => Mux26.IN15 +dbg_regs[15][14] => Mux25.IN15 +dbg_regs[15][15] => Mux24.IN15 +dbg_regs[15][16] => Mux23.IN15 +dbg_regs[15][17] => Mux22.IN15 +dbg_regs[15][18] => Mux21.IN15 +dbg_regs[15][19] => Mux20.IN15 +dbg_regs[15][20] => Mux19.IN15 +dbg_regs[15][21] => Mux18.IN15 +dbg_regs[15][22] => Mux17.IN15 +dbg_regs[15][23] => Mux16.IN15 +dbg_regs[15][24] => Mux15.IN15 +dbg_regs[15][25] => Mux14.IN15 +dbg_regs[15][26] => Mux13.IN15 +dbg_regs[15][27] => Mux12.IN15 +dbg_regs[15][28] => Mux11.IN15 +dbg_regs[15][29] => Mux10.IN15 +dbg_regs[15][30] => Mux9.IN15 +dbg_regs[15][31] => Mux8.IN15 +dbg_regs[14][0] => Mux39.IN14 +dbg_regs[14][1] => Mux38.IN14 +dbg_regs[14][2] => Mux37.IN14 +dbg_regs[14][3] => Mux36.IN14 +dbg_regs[14][4] => Mux35.IN14 +dbg_regs[14][5] => Mux34.IN14 +dbg_regs[14][6] => Mux33.IN14 +dbg_regs[14][7] => Mux32.IN14 +dbg_regs[14][8] => Mux31.IN14 +dbg_regs[14][9] => Mux30.IN14 +dbg_regs[14][10] => Mux29.IN14 +dbg_regs[14][11] => Mux28.IN14 +dbg_regs[14][12] => Mux27.IN14 +dbg_regs[14][13] => Mux26.IN14 +dbg_regs[14][14] => Mux25.IN14 +dbg_regs[14][15] => Mux24.IN14 +dbg_regs[14][16] => Mux23.IN14 +dbg_regs[14][17] => Mux22.IN14 +dbg_regs[14][18] => Mux21.IN14 +dbg_regs[14][19] => Mux20.IN14 +dbg_regs[14][20] => Mux19.IN14 +dbg_regs[14][21] => Mux18.IN14 +dbg_regs[14][22] => Mux17.IN14 +dbg_regs[14][23] => Mux16.IN14 +dbg_regs[14][24] => Mux15.IN14 +dbg_regs[14][25] => Mux14.IN14 +dbg_regs[14][26] => Mux13.IN14 +dbg_regs[14][27] => Mux12.IN14 +dbg_regs[14][28] => Mux11.IN14 +dbg_regs[14][29] => Mux10.IN14 +dbg_regs[14][30] => Mux9.IN14 +dbg_regs[14][31] => Mux8.IN14 +dbg_regs[13][0] => Mux39.IN13 +dbg_regs[13][1] => Mux38.IN13 +dbg_regs[13][2] => Mux37.IN13 +dbg_regs[13][3] => Mux36.IN13 +dbg_regs[13][4] => Mux35.IN13 +dbg_regs[13][5] => Mux34.IN13 +dbg_regs[13][6] => Mux33.IN13 +dbg_regs[13][7] => Mux32.IN13 +dbg_regs[13][8] => Mux31.IN13 +dbg_regs[13][9] => Mux30.IN13 +dbg_regs[13][10] => Mux29.IN13 +dbg_regs[13][11] => Mux28.IN13 +dbg_regs[13][12] => Mux27.IN13 +dbg_regs[13][13] => Mux26.IN13 +dbg_regs[13][14] => Mux25.IN13 +dbg_regs[13][15] => Mux24.IN13 +dbg_regs[13][16] => Mux23.IN13 +dbg_regs[13][17] => Mux22.IN13 +dbg_regs[13][18] => Mux21.IN13 +dbg_regs[13][19] => Mux20.IN13 +dbg_regs[13][20] => Mux19.IN13 +dbg_regs[13][21] => Mux18.IN13 +dbg_regs[13][22] => Mux17.IN13 +dbg_regs[13][23] => Mux16.IN13 +dbg_regs[13][24] => Mux15.IN13 +dbg_regs[13][25] => Mux14.IN13 +dbg_regs[13][26] => Mux13.IN13 +dbg_regs[13][27] => Mux12.IN13 +dbg_regs[13][28] => Mux11.IN13 +dbg_regs[13][29] => Mux10.IN13 +dbg_regs[13][30] => Mux9.IN13 +dbg_regs[13][31] => Mux8.IN13 +dbg_regs[12][0] => Mux39.IN12 +dbg_regs[12][1] => Mux38.IN12 +dbg_regs[12][2] => Mux37.IN12 +dbg_regs[12][3] => Mux36.IN12 +dbg_regs[12][4] => Mux35.IN12 +dbg_regs[12][5] => Mux34.IN12 +dbg_regs[12][6] => Mux33.IN12 +dbg_regs[12][7] => Mux32.IN12 +dbg_regs[12][8] => Mux31.IN12 +dbg_regs[12][9] => Mux30.IN12 +dbg_regs[12][10] => Mux29.IN12 +dbg_regs[12][11] => Mux28.IN12 +dbg_regs[12][12] => Mux27.IN12 +dbg_regs[12][13] => Mux26.IN12 +dbg_regs[12][14] => Mux25.IN12 +dbg_regs[12][15] => Mux24.IN12 +dbg_regs[12][16] => Mux23.IN12 +dbg_regs[12][17] => Mux22.IN12 +dbg_regs[12][18] => Mux21.IN12 +dbg_regs[12][19] => Mux20.IN12 +dbg_regs[12][20] => Mux19.IN12 +dbg_regs[12][21] => Mux18.IN12 +dbg_regs[12][22] => Mux17.IN12 +dbg_regs[12][23] => Mux16.IN12 +dbg_regs[12][24] => Mux15.IN12 +dbg_regs[12][25] => Mux14.IN12 +dbg_regs[12][26] => Mux13.IN12 +dbg_regs[12][27] => Mux12.IN12 +dbg_regs[12][28] => Mux11.IN12 +dbg_regs[12][29] => Mux10.IN12 +dbg_regs[12][30] => Mux9.IN12 +dbg_regs[12][31] => Mux8.IN12 +dbg_regs[11][0] => Mux39.IN11 +dbg_regs[11][1] => Mux38.IN11 +dbg_regs[11][2] => Mux37.IN11 +dbg_regs[11][3] => Mux36.IN11 +dbg_regs[11][4] => Mux35.IN11 +dbg_regs[11][5] => Mux34.IN11 +dbg_regs[11][6] => Mux33.IN11 +dbg_regs[11][7] => Mux32.IN11 +dbg_regs[11][8] => Mux31.IN11 +dbg_regs[11][9] => Mux30.IN11 +dbg_regs[11][10] => Mux29.IN11 +dbg_regs[11][11] => Mux28.IN11 +dbg_regs[11][12] => Mux27.IN11 +dbg_regs[11][13] => Mux26.IN11 +dbg_regs[11][14] => Mux25.IN11 +dbg_regs[11][15] => Mux24.IN11 +dbg_regs[11][16] => Mux23.IN11 +dbg_regs[11][17] => Mux22.IN11 +dbg_regs[11][18] => Mux21.IN11 +dbg_regs[11][19] => Mux20.IN11 +dbg_regs[11][20] => Mux19.IN11 +dbg_regs[11][21] => Mux18.IN11 +dbg_regs[11][22] => Mux17.IN11 +dbg_regs[11][23] => Mux16.IN11 +dbg_regs[11][24] => Mux15.IN11 +dbg_regs[11][25] => Mux14.IN11 +dbg_regs[11][26] => Mux13.IN11 +dbg_regs[11][27] => Mux12.IN11 +dbg_regs[11][28] => Mux11.IN11 +dbg_regs[11][29] => Mux10.IN11 +dbg_regs[11][30] => Mux9.IN11 +dbg_regs[11][31] => Mux8.IN11 +dbg_regs[10][0] => Mux39.IN10 +dbg_regs[10][1] => Mux38.IN10 +dbg_regs[10][2] => Mux37.IN10 +dbg_regs[10][3] => Mux36.IN10 +dbg_regs[10][4] => Mux35.IN10 +dbg_regs[10][5] => Mux34.IN10 +dbg_regs[10][6] => Mux33.IN10 +dbg_regs[10][7] => Mux32.IN10 +dbg_regs[10][8] => Mux31.IN10 +dbg_regs[10][9] => Mux30.IN10 +dbg_regs[10][10] => Mux29.IN10 +dbg_regs[10][11] => Mux28.IN10 +dbg_regs[10][12] => Mux27.IN10 +dbg_regs[10][13] => Mux26.IN10 +dbg_regs[10][14] => Mux25.IN10 +dbg_regs[10][15] => Mux24.IN10 +dbg_regs[10][16] => Mux23.IN10 +dbg_regs[10][17] => Mux22.IN10 +dbg_regs[10][18] => Mux21.IN10 +dbg_regs[10][19] => Mux20.IN10 +dbg_regs[10][20] => Mux19.IN10 +dbg_regs[10][21] => Mux18.IN10 +dbg_regs[10][22] => Mux17.IN10 +dbg_regs[10][23] => Mux16.IN10 +dbg_regs[10][24] => Mux15.IN10 +dbg_regs[10][25] => Mux14.IN10 +dbg_regs[10][26] => Mux13.IN10 +dbg_regs[10][27] => Mux12.IN10 +dbg_regs[10][28] => Mux11.IN10 +dbg_regs[10][29] => Mux10.IN10 +dbg_regs[10][30] => Mux9.IN10 +dbg_regs[10][31] => Mux8.IN10 +dbg_regs[9][0] => Mux39.IN9 +dbg_regs[9][1] => Mux38.IN9 +dbg_regs[9][2] => Mux37.IN9 +dbg_regs[9][3] => Mux36.IN9 +dbg_regs[9][4] => Mux35.IN9 +dbg_regs[9][5] => Mux34.IN9 +dbg_regs[9][6] => Mux33.IN9 +dbg_regs[9][7] => Mux32.IN9 +dbg_regs[9][8] => Mux31.IN9 +dbg_regs[9][9] => Mux30.IN9 +dbg_regs[9][10] => Mux29.IN9 +dbg_regs[9][11] => Mux28.IN9 +dbg_regs[9][12] => Mux27.IN9 +dbg_regs[9][13] => Mux26.IN9 +dbg_regs[9][14] => Mux25.IN9 +dbg_regs[9][15] => Mux24.IN9 +dbg_regs[9][16] => Mux23.IN9 +dbg_regs[9][17] => Mux22.IN9 +dbg_regs[9][18] => Mux21.IN9 +dbg_regs[9][19] => Mux20.IN9 +dbg_regs[9][20] => Mux19.IN9 +dbg_regs[9][21] => Mux18.IN9 +dbg_regs[9][22] => Mux17.IN9 +dbg_regs[9][23] => Mux16.IN9 +dbg_regs[9][24] => Mux15.IN9 +dbg_regs[9][25] => Mux14.IN9 +dbg_regs[9][26] => Mux13.IN9 +dbg_regs[9][27] => Mux12.IN9 +dbg_regs[9][28] => Mux11.IN9 +dbg_regs[9][29] => Mux10.IN9 +dbg_regs[9][30] => Mux9.IN9 +dbg_regs[9][31] => Mux8.IN9 +dbg_regs[8][0] => Mux39.IN8 +dbg_regs[8][1] => Mux38.IN8 +dbg_regs[8][2] => Mux37.IN8 +dbg_regs[8][3] => Mux36.IN8 +dbg_regs[8][4] => Mux35.IN8 +dbg_regs[8][5] => Mux34.IN8 +dbg_regs[8][6] => Mux33.IN8 +dbg_regs[8][7] => Mux32.IN8 +dbg_regs[8][8] => Mux31.IN8 +dbg_regs[8][9] => Mux30.IN8 +dbg_regs[8][10] => Mux29.IN8 +dbg_regs[8][11] => Mux28.IN8 +dbg_regs[8][12] => Mux27.IN8 +dbg_regs[8][13] => Mux26.IN8 +dbg_regs[8][14] => Mux25.IN8 +dbg_regs[8][15] => Mux24.IN8 +dbg_regs[8][16] => Mux23.IN8 +dbg_regs[8][17] => Mux22.IN8 +dbg_regs[8][18] => Mux21.IN8 +dbg_regs[8][19] => Mux20.IN8 +dbg_regs[8][20] => Mux19.IN8 +dbg_regs[8][21] => Mux18.IN8 +dbg_regs[8][22] => Mux17.IN8 +dbg_regs[8][23] => Mux16.IN8 +dbg_regs[8][24] => Mux15.IN8 +dbg_regs[8][25] => Mux14.IN8 +dbg_regs[8][26] => Mux13.IN8 +dbg_regs[8][27] => Mux12.IN8 +dbg_regs[8][28] => Mux11.IN8 +dbg_regs[8][29] => Mux10.IN8 +dbg_regs[8][30] => Mux9.IN8 +dbg_regs[8][31] => Mux8.IN8 +dbg_regs[7][0] => Mux39.IN7 +dbg_regs[7][1] => Mux38.IN7 +dbg_regs[7][2] => Mux37.IN7 +dbg_regs[7][3] => Mux36.IN7 +dbg_regs[7][4] => Mux35.IN7 +dbg_regs[7][5] => Mux34.IN7 +dbg_regs[7][6] => Mux33.IN7 +dbg_regs[7][7] => Mux32.IN7 +dbg_regs[7][8] => Mux31.IN7 +dbg_regs[7][9] => Mux30.IN7 +dbg_regs[7][10] => Mux29.IN7 +dbg_regs[7][11] => Mux28.IN7 +dbg_regs[7][12] => Mux27.IN7 +dbg_regs[7][13] => Mux26.IN7 +dbg_regs[7][14] => Mux25.IN7 +dbg_regs[7][15] => Mux24.IN7 +dbg_regs[7][16] => Mux23.IN7 +dbg_regs[7][17] => Mux22.IN7 +dbg_regs[7][18] => Mux21.IN7 +dbg_regs[7][19] => Mux20.IN7 +dbg_regs[7][20] => Mux19.IN7 +dbg_regs[7][21] => Mux18.IN7 +dbg_regs[7][22] => Mux17.IN7 +dbg_regs[7][23] => Mux16.IN7 +dbg_regs[7][24] => Mux15.IN7 +dbg_regs[7][25] => Mux14.IN7 +dbg_regs[7][26] => Mux13.IN7 +dbg_regs[7][27] => Mux12.IN7 +dbg_regs[7][28] => Mux11.IN7 +dbg_regs[7][29] => Mux10.IN7 +dbg_regs[7][30] => Mux9.IN7 +dbg_regs[7][31] => Mux8.IN7 +dbg_regs[6][0] => Mux39.IN6 +dbg_regs[6][1] => Mux38.IN6 +dbg_regs[6][2] => Mux37.IN6 +dbg_regs[6][3] => Mux36.IN6 +dbg_regs[6][4] => Mux35.IN6 +dbg_regs[6][5] => Mux34.IN6 +dbg_regs[6][6] => Mux33.IN6 +dbg_regs[6][7] => Mux32.IN6 +dbg_regs[6][8] => Mux31.IN6 +dbg_regs[6][9] => Mux30.IN6 +dbg_regs[6][10] => Mux29.IN6 +dbg_regs[6][11] => Mux28.IN6 +dbg_regs[6][12] => Mux27.IN6 +dbg_regs[6][13] => Mux26.IN6 +dbg_regs[6][14] => Mux25.IN6 +dbg_regs[6][15] => Mux24.IN6 +dbg_regs[6][16] => Mux23.IN6 +dbg_regs[6][17] => Mux22.IN6 +dbg_regs[6][18] => Mux21.IN6 +dbg_regs[6][19] => Mux20.IN6 +dbg_regs[6][20] => Mux19.IN6 +dbg_regs[6][21] => Mux18.IN6 +dbg_regs[6][22] => Mux17.IN6 +dbg_regs[6][23] => Mux16.IN6 +dbg_regs[6][24] => Mux15.IN6 +dbg_regs[6][25] => Mux14.IN6 +dbg_regs[6][26] => Mux13.IN6 +dbg_regs[6][27] => Mux12.IN6 +dbg_regs[6][28] => Mux11.IN6 +dbg_regs[6][29] => Mux10.IN6 +dbg_regs[6][30] => Mux9.IN6 +dbg_regs[6][31] => Mux8.IN6 +dbg_regs[5][0] => Mux39.IN5 +dbg_regs[5][1] => Mux38.IN5 +dbg_regs[5][2] => Mux37.IN5 +dbg_regs[5][3] => Mux36.IN5 +dbg_regs[5][4] => Mux35.IN5 +dbg_regs[5][5] => Mux34.IN5 +dbg_regs[5][6] => Mux33.IN5 +dbg_regs[5][7] => Mux32.IN5 +dbg_regs[5][8] => Mux31.IN5 +dbg_regs[5][9] => Mux30.IN5 +dbg_regs[5][10] => Mux29.IN5 +dbg_regs[5][11] => Mux28.IN5 +dbg_regs[5][12] => Mux27.IN5 +dbg_regs[5][13] => Mux26.IN5 +dbg_regs[5][14] => Mux25.IN5 +dbg_regs[5][15] => Mux24.IN5 +dbg_regs[5][16] => Mux23.IN5 +dbg_regs[5][17] => Mux22.IN5 +dbg_regs[5][18] => Mux21.IN5 +dbg_regs[5][19] => Mux20.IN5 +dbg_regs[5][20] => Mux19.IN5 +dbg_regs[5][21] => Mux18.IN5 +dbg_regs[5][22] => Mux17.IN5 +dbg_regs[5][23] => Mux16.IN5 +dbg_regs[5][24] => Mux15.IN5 +dbg_regs[5][25] => Mux14.IN5 +dbg_regs[5][26] => Mux13.IN5 +dbg_regs[5][27] => Mux12.IN5 +dbg_regs[5][28] => Mux11.IN5 +dbg_regs[5][29] => Mux10.IN5 +dbg_regs[5][30] => Mux9.IN5 +dbg_regs[5][31] => Mux8.IN5 +dbg_regs[4][0] => Mux39.IN4 +dbg_regs[4][1] => Mux38.IN4 +dbg_regs[4][2] => Mux37.IN4 +dbg_regs[4][3] => Mux36.IN4 +dbg_regs[4][4] => Mux35.IN4 +dbg_regs[4][5] => Mux34.IN4 +dbg_regs[4][6] => Mux33.IN4 +dbg_regs[4][7] => Mux32.IN4 +dbg_regs[4][8] => Mux31.IN4 +dbg_regs[4][9] => Mux30.IN4 +dbg_regs[4][10] => Mux29.IN4 +dbg_regs[4][11] => Mux28.IN4 +dbg_regs[4][12] => Mux27.IN4 +dbg_regs[4][13] => Mux26.IN4 +dbg_regs[4][14] => Mux25.IN4 +dbg_regs[4][15] => Mux24.IN4 +dbg_regs[4][16] => Mux23.IN4 +dbg_regs[4][17] => Mux22.IN4 +dbg_regs[4][18] => Mux21.IN4 +dbg_regs[4][19] => Mux20.IN4 +dbg_regs[4][20] => Mux19.IN4 +dbg_regs[4][21] => Mux18.IN4 +dbg_regs[4][22] => Mux17.IN4 +dbg_regs[4][23] => Mux16.IN4 +dbg_regs[4][24] => Mux15.IN4 +dbg_regs[4][25] => Mux14.IN4 +dbg_regs[4][26] => Mux13.IN4 +dbg_regs[4][27] => Mux12.IN4 +dbg_regs[4][28] => Mux11.IN4 +dbg_regs[4][29] => Mux10.IN4 +dbg_regs[4][30] => Mux9.IN4 +dbg_regs[4][31] => Mux8.IN4 +dbg_regs[3][0] => Mux39.IN3 +dbg_regs[3][1] => Mux38.IN3 +dbg_regs[3][2] => Mux37.IN3 +dbg_regs[3][3] => Mux36.IN3 +dbg_regs[3][4] => Mux35.IN3 +dbg_regs[3][5] => Mux34.IN3 +dbg_regs[3][6] => Mux33.IN3 +dbg_regs[3][7] => Mux32.IN3 +dbg_regs[3][8] => Mux31.IN3 +dbg_regs[3][9] => Mux30.IN3 +dbg_regs[3][10] => Mux29.IN3 +dbg_regs[3][11] => Mux28.IN3 +dbg_regs[3][12] => Mux27.IN3 +dbg_regs[3][13] => Mux26.IN3 +dbg_regs[3][14] => Mux25.IN3 +dbg_regs[3][15] => Mux24.IN3 +dbg_regs[3][16] => Mux23.IN3 +dbg_regs[3][17] => Mux22.IN3 +dbg_regs[3][18] => Mux21.IN3 +dbg_regs[3][19] => Mux20.IN3 +dbg_regs[3][20] => Mux19.IN3 +dbg_regs[3][21] => Mux18.IN3 +dbg_regs[3][22] => Mux17.IN3 +dbg_regs[3][23] => Mux16.IN3 +dbg_regs[3][24] => Mux15.IN3 +dbg_regs[3][25] => Mux14.IN3 +dbg_regs[3][26] => Mux13.IN3 +dbg_regs[3][27] => Mux12.IN3 +dbg_regs[3][28] => Mux11.IN3 +dbg_regs[3][29] => Mux10.IN3 +dbg_regs[3][30] => Mux9.IN3 +dbg_regs[3][31] => Mux8.IN3 +dbg_regs[2][0] => Mux39.IN2 +dbg_regs[2][1] => Mux38.IN2 +dbg_regs[2][2] => Mux37.IN2 +dbg_regs[2][3] => Mux36.IN2 +dbg_regs[2][4] => Mux35.IN2 +dbg_regs[2][5] => Mux34.IN2 +dbg_regs[2][6] => Mux33.IN2 +dbg_regs[2][7] => Mux32.IN2 +dbg_regs[2][8] => Mux31.IN2 +dbg_regs[2][9] => Mux30.IN2 +dbg_regs[2][10] => Mux29.IN2 +dbg_regs[2][11] => Mux28.IN2 +dbg_regs[2][12] => Mux27.IN2 +dbg_regs[2][13] => Mux26.IN2 +dbg_regs[2][14] => Mux25.IN2 +dbg_regs[2][15] => Mux24.IN2 +dbg_regs[2][16] => Mux23.IN2 +dbg_regs[2][17] => Mux22.IN2 +dbg_regs[2][18] => Mux21.IN2 +dbg_regs[2][19] => Mux20.IN2 +dbg_regs[2][20] => Mux19.IN2 +dbg_regs[2][21] => Mux18.IN2 +dbg_regs[2][22] => Mux17.IN2 +dbg_regs[2][23] => Mux16.IN2 +dbg_regs[2][24] => Mux15.IN2 +dbg_regs[2][25] => Mux14.IN2 +dbg_regs[2][26] => Mux13.IN2 +dbg_regs[2][27] => Mux12.IN2 +dbg_regs[2][28] => Mux11.IN2 +dbg_regs[2][29] => Mux10.IN2 +dbg_regs[2][30] => Mux9.IN2 +dbg_regs[2][31] => Mux8.IN2 +dbg_regs[1][0] => Mux39.IN1 +dbg_regs[1][1] => Mux38.IN1 +dbg_regs[1][2] => Mux37.IN1 +dbg_regs[1][3] => Mux36.IN1 +dbg_regs[1][4] => Mux35.IN1 +dbg_regs[1][5] => Mux34.IN1 +dbg_regs[1][6] => Mux33.IN1 +dbg_regs[1][7] => Mux32.IN1 +dbg_regs[1][8] => Mux31.IN1 +dbg_regs[1][9] => Mux30.IN1 +dbg_regs[1][10] => Mux29.IN1 +dbg_regs[1][11] => Mux28.IN1 +dbg_regs[1][12] => Mux27.IN1 +dbg_regs[1][13] => Mux26.IN1 +dbg_regs[1][14] => Mux25.IN1 +dbg_regs[1][15] => Mux24.IN1 +dbg_regs[1][16] => Mux23.IN1 +dbg_regs[1][17] => Mux22.IN1 +dbg_regs[1][18] => Mux21.IN1 +dbg_regs[1][19] => Mux20.IN1 +dbg_regs[1][20] => Mux19.IN1 +dbg_regs[1][21] => Mux18.IN1 +dbg_regs[1][22] => Mux17.IN1 +dbg_regs[1][23] => Mux16.IN1 +dbg_regs[1][24] => Mux15.IN1 +dbg_regs[1][25] => Mux14.IN1 +dbg_regs[1][26] => Mux13.IN1 +dbg_regs[1][27] => Mux12.IN1 +dbg_regs[1][28] => Mux11.IN1 +dbg_regs[1][29] => Mux10.IN1 +dbg_regs[1][30] => Mux9.IN1 +dbg_regs[1][31] => Mux8.IN1 +dbg_regs[0][0] => Mux39.IN0 +dbg_regs[0][1] => Mux38.IN0 +dbg_regs[0][2] => Mux37.IN0 +dbg_regs[0][3] => Mux36.IN0 +dbg_regs[0][4] => Mux35.IN0 +dbg_regs[0][5] => Mux34.IN0 +dbg_regs[0][6] => Mux33.IN0 +dbg_regs[0][7] => Mux32.IN0 +dbg_regs[0][8] => Mux31.IN0 +dbg_regs[0][9] => Mux30.IN0 +dbg_regs[0][10] => Mux29.IN0 +dbg_regs[0][11] => Mux28.IN0 +dbg_regs[0][12] => Mux27.IN0 +dbg_regs[0][13] => Mux26.IN0 +dbg_regs[0][14] => Mux25.IN0 +dbg_regs[0][15] => Mux24.IN0 +dbg_regs[0][16] => Mux23.IN0 +dbg_regs[0][17] => Mux22.IN0 +dbg_regs[0][18] => Mux21.IN0 +dbg_regs[0][19] => Mux20.IN0 +dbg_regs[0][20] => Mux19.IN0 +dbg_regs[0][21] => Mux18.IN0 +dbg_regs[0][22] => Mux17.IN0 +dbg_regs[0][23] => Mux16.IN0 +dbg_regs[0][24] => Mux15.IN0 +dbg_regs[0][25] => Mux14.IN0 +dbg_regs[0][26] => Mux13.IN0 +dbg_regs[0][27] => Mux12.IN0 +dbg_regs[0][28] => Mux11.IN0 +dbg_regs[0][29] => Mux10.IN0 +dbg_regs[0][30] => Mux9.IN0 +dbg_regs[0][31] => Mux8.IN0 +dbg_pc[0] => ~NO_FANOUT~ +dbg_pc[1] => ~NO_FANOUT~ +dbg_pc[2] => ~NO_FANOUT~ +dbg_pc[3] => ~NO_FANOUT~ +dbg_pc[4] => ~NO_FANOUT~ +dbg_pc[5] => ~NO_FANOUT~ +dbg_pc[6] => ~NO_FANOUT~ +dbg_pc[7] => ~NO_FANOUT~ +dbg_pc[8] => ~NO_FANOUT~ +dbg_pc[9] => ~NO_FANOUT~ +dbg_pc[10] => ~NO_FANOUT~ +dbg_pc[11] => ~NO_FANOUT~ +dbg_pc[12] => ~NO_FANOUT~ +dbg_pc[13] => ~NO_FANOUT~ +dbg_pc[14] => ~NO_FANOUT~ +dbg_pc[15] => ~NO_FANOUT~ +dbg_pc[16] => ~NO_FANOUT~ +dbg_pc[17] => ~NO_FANOUT~ +dbg_pc[18] => ~NO_FANOUT~ +dbg_pc[19] => ~NO_FANOUT~ +dbg_pc[20] => ~NO_FANOUT~ +dbg_pc[21] => ~NO_FANOUT~ +dbg_pc[22] => ~NO_FANOUT~ +dbg_pc[23] => ~NO_FANOUT~ +dbg_pc[24] => ~NO_FANOUT~ +dbg_pc[25] => ~NO_FANOUT~ +dbg_pc[26] => ~NO_FANOUT~ +dbg_pc[27] => ~NO_FANOUT~ +dbg_pc[28] => ~NO_FANOUT~ +dbg_pc[29] => ~NO_FANOUT~ +dbg_pc[30] => ~NO_FANOUT~ +dbg_pc[31] => ~NO_FANOUT~ + + +|top|memory_map:u_mem +clk => M3.we_a.CLK +clk => M3.waddr_a[8].CLK +clk => M3.waddr_a[7].CLK +clk => M3.waddr_a[6].CLK +clk => M3.waddr_a[5].CLK +clk => M3.waddr_a[4].CLK +clk => M3.waddr_a[3].CLK +clk => M3.waddr_a[2].CLK +clk => M3.waddr_a[1].CLK +clk => M3.waddr_a[0].CLK +clk => M3.data_a[7].CLK +clk => M3.data_a[6].CLK +clk => M3.data_a[5].CLK +clk => M3.data_a[4].CLK +clk => M3.data_a[3].CLK +clk => M3.data_a[2].CLK +clk => M3.data_a[1].CLK +clk => M3.data_a[0].CLK +clk => M2.we_a.CLK +clk => M2.waddr_a[8].CLK +clk => M2.waddr_a[7].CLK +clk => M2.waddr_a[6].CLK +clk => M2.waddr_a[5].CLK +clk => M2.waddr_a[4].CLK +clk => M2.waddr_a[3].CLK +clk => M2.waddr_a[2].CLK +clk => M2.waddr_a[1].CLK +clk => M2.waddr_a[0].CLK +clk => M2.data_a[7].CLK +clk => M2.data_a[6].CLK +clk => M2.data_a[5].CLK +clk => M2.data_a[4].CLK +clk => M2.data_a[3].CLK +clk => M2.data_a[2].CLK +clk => M2.data_a[1].CLK +clk => M2.data_a[0].CLK +clk => M1.we_a.CLK +clk => M1.waddr_a[8].CLK +clk => M1.waddr_a[7].CLK +clk => M1.waddr_a[6].CLK +clk => M1.waddr_a[5].CLK +clk => M1.waddr_a[4].CLK +clk => M1.waddr_a[3].CLK +clk => M1.waddr_a[2].CLK +clk => M1.waddr_a[1].CLK +clk => M1.waddr_a[0].CLK +clk => M1.data_a[7].CLK +clk => M1.data_a[6].CLK +clk => M1.data_a[5].CLK +clk => M1.data_a[4].CLK +clk => M1.data_a[3].CLK +clk => M1.data_a[2].CLK +clk => M1.data_a[1].CLK +clk => M1.data_a[0].CLK +clk => M0.we_a.CLK +clk => M0.waddr_a[8].CLK +clk => M0.waddr_a[7].CLK +clk => M0.waddr_a[6].CLK +clk => M0.waddr_a[5].CLK +clk => M0.waddr_a[4].CLK +clk => M0.waddr_a[3].CLK +clk => M0.waddr_a[2].CLK +clk => M0.waddr_a[1].CLK +clk => M0.waddr_a[0].CLK +clk => M0.data_a[7].CLK +clk => M0.data_a[6].CLK +clk => M0.data_a[5].CLK +clk => M0.data_a[4].CLK +clk => M0.data_a[3].CLK +clk => M0.data_a[2].CLK +clk => M0.data_a[1].CLK +clk => M0.data_a[0].CLK +clk => LEDR[0]~reg0.CLK +clk => LEDR[1]~reg0.CLK +clk => LEDR[2]~reg0.CLK +clk => LEDR[3]~reg0.CLK +clk => LEDR[4]~reg0.CLK +clk => LEDR[5]~reg0.CLK +clk => LEDR[6]~reg0.CLK +clk => LEDR[7]~reg0.CLK +clk => LEDR[8]~reg0.CLK +clk => LEDR[9]~reg0.CLK +clk => mem_rdata[0].CLK +clk => mem_rdata[1].CLK +clk => mem_rdata[2].CLK +clk => mem_rdata[3].CLK +clk => mem_rdata[4].CLK +clk => mem_rdata[5].CLK +clk => mem_rdata[6].CLK +clk => mem_rdata[7].CLK +clk => mem_rdata[8].CLK +clk => mem_rdata[9].CLK +clk => mem_rdata[10].CLK +clk => mem_rdata[11].CLK +clk => mem_rdata[12].CLK +clk => mem_rdata[13].CLK +clk => mem_rdata[14].CLK +clk => mem_rdata[15].CLK +clk => mem_rdata[16].CLK +clk => mem_rdata[17].CLK +clk => mem_rdata[18].CLK +clk => mem_rdata[19].CLK +clk => mem_rdata[20].CLK +clk => mem_rdata[21].CLK +clk => mem_rdata[22].CLK +clk => mem_rdata[23].CLK +clk => mem_rdata[24].CLK +clk => mem_rdata[25].CLK +clk => mem_rdata[26].CLK +clk => mem_rdata[27].CLK +clk => mem_rdata[28].CLK +clk => mem_rdata[29].CLK +clk => mem_rdata[30].CLK +clk => mem_rdata[31].CLK +clk => M0.CLK0 +clk => M1.CLK0 +clk => M2.CLK0 +clk => M3.CLK0 +address[0] => Equal2.IN54 +address[0] => Equal3.IN54 +address[1] => Equal2.IN53 +address[1] => Equal3.IN53 +address[2] => LessThan0.IN10 +address[2] => Mux0.IN36 +address[2] => Mux1.IN36 +address[2] => Mux2.IN36 +address[2] => Mux3.IN36 +address[2] => Mux4.IN36 +address[2] => Mux5.IN36 +address[2] => Mux6.IN36 +address[2] => Mux7.IN36 +address[2] => Mux8.IN36 +address[2] => Mux9.IN36 +address[2] => Mux10.IN36 +address[2] => Mux11.IN36 +address[2] => Mux12.IN36 +address[2] => Mux13.IN36 +address[2] => Mux14.IN36 +address[2] => Mux15.IN36 +address[2] => Mux16.IN36 +address[2] => Mux17.IN36 +address[2] => Mux18.IN36 +address[2] => Mux19.IN36 +address[2] => Mux20.IN36 +address[2] => Mux21.IN36 +address[2] => Mux22.IN36 +address[2] => Mux23.IN36 +address[2] => Mux24.IN36 +address[2] => Mux25.IN36 +address[2] => Mux26.IN36 +address[2] => Mux27.IN36 +address[2] => Mux28.IN36 +address[2] => Mux29.IN36 +address[2] => Mux30.IN36 +address[2] => Mux31.IN36 +address[2] => M3.waddr_a[0].DATAIN +address[2] => M2.waddr_a[0].DATAIN +address[2] => M1.waddr_a[0].DATAIN +address[2] => M0.waddr_a[0].DATAIN +address[2] => Equal2.IN63 +address[2] => Equal3.IN63 +address[2] => M0.WADDR +address[2] => M0.RADDR +address[2] => M1.WADDR +address[2] => M1.RADDR +address[2] => M2.WADDR +address[2] => M2.RADDR +address[2] => M3.WADDR +address[2] => M3.RADDR +address[3] => LessThan0.IN9 +address[3] => Mux0.IN35 +address[3] => Mux1.IN35 +address[3] => Mux2.IN35 +address[3] => Mux3.IN35 +address[3] => Mux4.IN35 +address[3] => Mux5.IN35 +address[3] => Mux6.IN35 +address[3] => Mux7.IN35 +address[3] => Mux8.IN35 +address[3] => Mux9.IN35 +address[3] => Mux10.IN35 +address[3] => Mux11.IN35 +address[3] => Mux12.IN35 +address[3] => Mux13.IN35 +address[3] => Mux14.IN35 +address[3] => Mux15.IN35 +address[3] => Mux16.IN35 +address[3] => Mux17.IN35 +address[3] => Mux18.IN35 +address[3] => Mux19.IN35 +address[3] => Mux20.IN35 +address[3] => Mux21.IN35 +address[3] => Mux22.IN35 +address[3] => Mux23.IN35 +address[3] => Mux24.IN35 +address[3] => Mux25.IN35 +address[3] => Mux26.IN35 +address[3] => Mux27.IN35 +address[3] => Mux28.IN35 +address[3] => Mux29.IN35 +address[3] => Mux30.IN35 +address[3] => Mux31.IN35 +address[3] => M3.waddr_a[1].DATAIN +address[3] => M2.waddr_a[1].DATAIN +address[3] => M1.waddr_a[1].DATAIN +address[3] => M0.waddr_a[1].DATAIN +address[3] => Equal2.IN62 +address[3] => Equal3.IN62 +address[3] => M0.WADDR1 +address[3] => M0.RADDR1 +address[3] => M1.WADDR1 +address[3] => M1.RADDR1 +address[3] => M2.WADDR1 +address[3] => M2.RADDR1 +address[3] => M3.WADDR1 +address[3] => M3.RADDR1 +address[4] => LessThan0.IN8 +address[4] => Mux0.IN34 +address[4] => Mux1.IN34 +address[4] => Mux2.IN34 +address[4] => Mux3.IN34 +address[4] => Mux4.IN34 +address[4] => Mux5.IN34 +address[4] => Mux6.IN34 +address[4] => Mux7.IN34 +address[4] => Mux8.IN34 +address[4] => Mux9.IN34 +address[4] => Mux10.IN34 +address[4] => Mux11.IN34 +address[4] => Mux12.IN34 +address[4] => Mux13.IN34 +address[4] => Mux14.IN34 +address[4] => Mux15.IN34 +address[4] => Mux16.IN34 +address[4] => Mux17.IN34 +address[4] => Mux18.IN34 +address[4] => Mux19.IN34 +address[4] => Mux20.IN34 +address[4] => Mux21.IN34 +address[4] => Mux22.IN34 +address[4] => Mux23.IN34 +address[4] => Mux24.IN34 +address[4] => Mux25.IN34 +address[4] => Mux26.IN34 +address[4] => Mux27.IN34 +address[4] => Mux28.IN34 +address[4] => Mux29.IN34 +address[4] => Mux30.IN34 +address[4] => Mux31.IN34 +address[4] => M3.waddr_a[2].DATAIN +address[4] => M2.waddr_a[2].DATAIN +address[4] => M1.waddr_a[2].DATAIN +address[4] => M0.waddr_a[2].DATAIN +address[4] => Equal2.IN61 +address[4] => Equal3.IN61 +address[4] => M0.WADDR2 +address[4] => M0.RADDR2 +address[4] => M1.WADDR2 +address[4] => M1.RADDR2 +address[4] => M2.WADDR2 +address[4] => M2.RADDR2 +address[4] => M3.WADDR2 +address[4] => M3.RADDR2 +address[5] => LessThan0.IN7 +address[5] => Mux0.IN33 +address[5] => Mux1.IN33 +address[5] => Mux2.IN33 +address[5] => Mux3.IN33 +address[5] => Mux4.IN33 +address[5] => Mux5.IN33 +address[5] => Mux6.IN33 +address[5] => Mux7.IN33 +address[5] => Mux8.IN33 +address[5] => Mux9.IN33 +address[5] => Mux10.IN33 +address[5] => Mux11.IN33 +address[5] => Mux12.IN33 +address[5] => Mux13.IN33 +address[5] => Mux14.IN33 +address[5] => Mux15.IN33 +address[5] => Mux16.IN33 +address[5] => Mux17.IN33 +address[5] => Mux18.IN33 +address[5] => Mux19.IN33 +address[5] => Mux20.IN33 +address[5] => Mux21.IN33 +address[5] => Mux22.IN33 +address[5] => Mux23.IN33 +address[5] => Mux24.IN33 +address[5] => Mux25.IN33 +address[5] => Mux26.IN33 +address[5] => Mux27.IN33 +address[5] => Mux28.IN33 +address[5] => Mux29.IN33 +address[5] => Mux30.IN33 +address[5] => Mux31.IN33 +address[5] => M3.waddr_a[3].DATAIN +address[5] => M2.waddr_a[3].DATAIN +address[5] => M1.waddr_a[3].DATAIN +address[5] => M0.waddr_a[3].DATAIN +address[5] => Equal2.IN60 +address[5] => Equal3.IN60 +address[5] => M0.WADDR3 +address[5] => M0.RADDR3 +address[5] => M1.WADDR3 +address[5] => M1.RADDR3 +address[5] => M2.WADDR3 +address[5] => M2.RADDR3 +address[5] => M3.WADDR3 +address[5] => M3.RADDR3 +address[6] => LessThan0.IN6 +address[6] => Mux0.IN32 +address[6] => Mux1.IN32 +address[6] => Mux2.IN32 +address[6] => Mux3.IN32 +address[6] => Mux4.IN32 +address[6] => Mux5.IN32 +address[6] => Mux6.IN32 +address[6] => Mux7.IN32 +address[6] => Mux8.IN32 +address[6] => Mux9.IN32 +address[6] => Mux10.IN32 +address[6] => Mux11.IN32 +address[6] => Mux12.IN32 +address[6] => Mux13.IN32 +address[6] => Mux14.IN32 +address[6] => Mux15.IN32 +address[6] => Mux16.IN32 +address[6] => Mux17.IN32 +address[6] => Mux18.IN32 +address[6] => Mux19.IN32 +address[6] => Mux20.IN32 +address[6] => Mux21.IN32 +address[6] => Mux22.IN32 +address[6] => Mux23.IN32 +address[6] => Mux24.IN32 +address[6] => Mux25.IN32 +address[6] => Mux26.IN32 +address[6] => Mux27.IN32 +address[6] => Mux28.IN32 +address[6] => Mux29.IN32 +address[6] => Mux30.IN32 +address[6] => Mux31.IN32 +address[6] => M3.waddr_a[4].DATAIN +address[6] => M2.waddr_a[4].DATAIN +address[6] => M1.waddr_a[4].DATAIN +address[6] => M0.waddr_a[4].DATAIN +address[6] => Equal2.IN59 +address[6] => Equal3.IN59 +address[6] => M0.WADDR4 +address[6] => M0.RADDR4 +address[6] => M1.WADDR4 +address[6] => M1.RADDR4 +address[6] => M2.WADDR4 +address[6] => M2.RADDR4 +address[6] => M3.WADDR4 +address[6] => M3.RADDR4 +address[7] => M3.waddr_a[5].DATAIN +address[7] => M2.waddr_a[5].DATAIN +address[7] => M1.waddr_a[5].DATAIN +address[7] => M0.waddr_a[5].DATAIN +address[7] => Equal2.IN58 +address[7] => Equal3.IN58 +address[7] => Equal1.IN4 +address[7] => M0.WADDR5 +address[7] => M0.RADDR5 +address[7] => M1.WADDR5 +address[7] => M1.RADDR5 +address[7] => M2.WADDR5 +address[7] => M2.RADDR5 +address[7] => M3.WADDR5 +address[7] => M3.RADDR5 +address[8] => M3.waddr_a[6].DATAIN +address[8] => M2.waddr_a[6].DATAIN +address[8] => M1.waddr_a[6].DATAIN +address[8] => M0.waddr_a[6].DATAIN +address[8] => Equal2.IN57 +address[8] => Equal3.IN57 +address[8] => Equal1.IN3 +address[8] => M0.WADDR6 +address[8] => M0.RADDR6 +address[8] => M1.WADDR6 +address[8] => M1.RADDR6 +address[8] => M2.WADDR6 +address[8] => M2.RADDR6 +address[8] => M3.WADDR6 +address[8] => M3.RADDR6 +address[9] => M3.waddr_a[7].DATAIN +address[9] => M2.waddr_a[7].DATAIN +address[9] => M1.waddr_a[7].DATAIN +address[9] => M0.waddr_a[7].DATAIN +address[9] => Equal2.IN56 +address[9] => Equal3.IN56 +address[9] => Equal1.IN2 +address[9] => M0.WADDR7 +address[9] => M0.RADDR7 +address[9] => M1.WADDR7 +address[9] => M1.RADDR7 +address[9] => M2.WADDR7 +address[9] => M2.RADDR7 +address[9] => M3.WADDR7 +address[9] => M3.RADDR7 +address[10] => M3.waddr_a[8].DATAIN +address[10] => M2.waddr_a[8].DATAIN +address[10] => M1.waddr_a[8].DATAIN +address[10] => M0.waddr_a[8].DATAIN +address[10] => Equal2.IN55 +address[10] => Equal3.IN55 +address[10] => Equal1.IN1 +address[10] => M0.WADDR8 +address[10] => M0.RADDR8 +address[10] => M1.WADDR8 +address[10] => M1.RADDR8 +address[10] => M2.WADDR8 +address[10] => M2.RADDR8 +address[10] => M3.WADDR8 +address[10] => M3.RADDR8 +address[11] => Equal2.IN52 +address[11] => Equal3.IN52 +address[11] => Equal1.IN0 +address[12] => Equal2.IN51 +address[12] => Equal3.IN51 +address[12] => Equal0.IN19 +address[13] => Equal2.IN50 +address[13] => Equal3.IN50 +address[13] => Equal0.IN18 +address[14] => Equal2.IN49 +address[14] => Equal3.IN49 +address[14] => Equal0.IN17 +address[15] => Equal2.IN48 +address[15] => Equal3.IN48 +address[15] => Equal0.IN16 +address[16] => Equal2.IN47 +address[16] => Equal3.IN47 +address[16] => Equal0.IN15 +address[17] => Equal2.IN46 +address[17] => Equal3.IN46 +address[17] => Equal0.IN14 +address[18] => Equal2.IN45 +address[18] => Equal3.IN45 +address[18] => Equal0.IN13 +address[19] => Equal2.IN44 +address[19] => Equal3.IN44 +address[19] => Equal0.IN12 +address[20] => Equal2.IN43 +address[20] => Equal3.IN43 +address[20] => Equal0.IN11 +address[21] => Equal2.IN42 +address[21] => Equal3.IN42 +address[21] => Equal0.IN10 +address[22] => Equal2.IN41 +address[22] => Equal3.IN41 +address[22] => Equal0.IN9 +address[23] => Equal2.IN40 +address[23] => Equal3.IN40 +address[23] => Equal0.IN8 +address[24] => Equal2.IN39 +address[24] => Equal3.IN39 +address[24] => Equal0.IN7 +address[25] => Equal2.IN38 +address[25] => Equal3.IN38 +address[25] => Equal0.IN6 +address[26] => Equal2.IN37 +address[26] => Equal3.IN37 +address[26] => Equal0.IN5 +address[27] => Equal2.IN36 +address[27] => Equal3.IN36 +address[27] => Equal0.IN4 +address[28] => Equal2.IN35 +address[28] => Equal3.IN35 +address[28] => Equal0.IN3 +address[29] => Equal2.IN34 +address[29] => Equal3.IN34 +address[29] => Equal0.IN0 +address[30] => Equal2.IN33 +address[30] => Equal3.IN33 +address[30] => Equal0.IN2 +address[31] => Equal2.IN32 +address[31] => Equal3.IN32 +address[31] => Equal0.IN1 +write_data[0] => LEDR.DATAB +write_data[0] => M0.data_a[0].DATAIN +write_data[0] => M0.DATAIN +write_data[1] => LEDR.DATAB +write_data[1] => M0.data_a[1].DATAIN +write_data[1] => M0.DATAIN1 +write_data[2] => LEDR.DATAB +write_data[2] => M0.data_a[2].DATAIN +write_data[2] => M0.DATAIN2 +write_data[3] => LEDR.DATAB +write_data[3] => M0.data_a[3].DATAIN +write_data[3] => M0.DATAIN3 +write_data[4] => LEDR.DATAB +write_data[4] => M0.data_a[4].DATAIN +write_data[4] => M0.DATAIN4 +write_data[5] => LEDR.DATAB +write_data[5] => M0.data_a[5].DATAIN +write_data[5] => M0.DATAIN5 +write_data[6] => LEDR.DATAB +write_data[6] => M0.data_a[6].DATAIN +write_data[6] => M0.DATAIN6 +write_data[7] => LEDR.DATAB +write_data[7] => M0.data_a[7].DATAIN +write_data[7] => M0.DATAIN7 +write_data[8] => LEDR.DATAB +write_data[8] => M1.data_a[0].DATAIN +write_data[8] => M1.DATAIN +write_data[9] => LEDR.DATAB +write_data[9] => M1.data_a[1].DATAIN +write_data[9] => M1.DATAIN1 +write_data[10] => M1.data_a[2].DATAIN +write_data[10] => M1.DATAIN2 +write_data[11] => M1.data_a[3].DATAIN +write_data[11] => M1.DATAIN3 +write_data[12] => M1.data_a[4].DATAIN +write_data[12] => M1.DATAIN4 +write_data[13] => M1.data_a[5].DATAIN +write_data[13] => M1.DATAIN5 +write_data[14] => M1.data_a[6].DATAIN +write_data[14] => M1.DATAIN6 +write_data[15] => M1.data_a[7].DATAIN +write_data[15] => M1.DATAIN7 +write_data[16] => M2.data_a[0].DATAIN +write_data[16] => M2.DATAIN +write_data[17] => M2.data_a[1].DATAIN +write_data[17] => M2.DATAIN1 +write_data[18] => M2.data_a[2].DATAIN +write_data[18] => M2.DATAIN2 +write_data[19] => M2.data_a[3].DATAIN +write_data[19] => M2.DATAIN3 +write_data[20] => M2.data_a[4].DATAIN +write_data[20] => M2.DATAIN4 +write_data[21] => M2.data_a[5].DATAIN +write_data[21] => M2.DATAIN5 +write_data[22] => M2.data_a[6].DATAIN +write_data[22] => M2.DATAIN6 +write_data[23] => M2.data_a[7].DATAIN +write_data[23] => M2.DATAIN7 +write_data[24] => M3.data_a[0].DATAIN +write_data[24] => M3.DATAIN +write_data[25] => M3.data_a[1].DATAIN +write_data[25] => M3.DATAIN1 +write_data[26] => M3.data_a[2].DATAIN +write_data[26] => M3.DATAIN2 +write_data[27] => M3.data_a[3].DATAIN +write_data[27] => M3.DATAIN3 +write_data[28] => M3.data_a[4].DATAIN +write_data[28] => M3.DATAIN4 +write_data[29] => M3.data_a[5].DATAIN +write_data[29] => M3.DATAIN5 +write_data[30] => M3.data_a[6].DATAIN +write_data[30] => M3.DATAIN6 +write_data[31] => M3.data_a[7].DATAIN +write_data[31] => M3.DATAIN7 +write_enable[0] => WideOr0.IN0 +write_enable[0] => M0.DATAA +write_enable[1] => WideOr0.IN1 +write_enable[1] => M1.DATAA +write_enable[2] => WideOr0.IN2 +write_enable[2] => M2.DATAA +write_enable[3] => WideOr0.IN3 +write_enable[3] => M3.DATAA +read_data[0] <= Selector31.DB_MAX_OUTPUT_PORT_TYPE +read_data[1] <= Selector30.DB_MAX_OUTPUT_PORT_TYPE +read_data[2] <= Selector29.DB_MAX_OUTPUT_PORT_TYPE +read_data[3] <= Selector28.DB_MAX_OUTPUT_PORT_TYPE +read_data[4] <= Selector27.DB_MAX_OUTPUT_PORT_TYPE +read_data[5] <= Selector26.DB_MAX_OUTPUT_PORT_TYPE +read_data[6] <= Selector25.DB_MAX_OUTPUT_PORT_TYPE +read_data[7] <= Selector24.DB_MAX_OUTPUT_PORT_TYPE +read_data[8] <= Selector23.DB_MAX_OUTPUT_PORT_TYPE +read_data[9] <= Selector22.DB_MAX_OUTPUT_PORT_TYPE +read_data[10] <= Selector21.DB_MAX_OUTPUT_PORT_TYPE +read_data[11] <= Selector20.DB_MAX_OUTPUT_PORT_TYPE +read_data[12] <= Selector19.DB_MAX_OUTPUT_PORT_TYPE +read_data[13] <= Selector18.DB_MAX_OUTPUT_PORT_TYPE +read_data[14] <= Selector17.DB_MAX_OUTPUT_PORT_TYPE +read_data[15] <= Selector16.DB_MAX_OUTPUT_PORT_TYPE +read_data[16] <= Selector15.DB_MAX_OUTPUT_PORT_TYPE +read_data[17] <= Selector14.DB_MAX_OUTPUT_PORT_TYPE +read_data[18] <= Selector13.DB_MAX_OUTPUT_PORT_TYPE +read_data[19] <= Selector12.DB_MAX_OUTPUT_PORT_TYPE +read_data[20] <= Selector11.DB_MAX_OUTPUT_PORT_TYPE +read_data[21] <= Selector10.DB_MAX_OUTPUT_PORT_TYPE +read_data[22] <= Selector9.DB_MAX_OUTPUT_PORT_TYPE +read_data[23] <= Selector8.DB_MAX_OUTPUT_PORT_TYPE +read_data[24] <= Selector7.DB_MAX_OUTPUT_PORT_TYPE +read_data[25] <= Selector6.DB_MAX_OUTPUT_PORT_TYPE +read_data[26] <= Selector5.DB_MAX_OUTPUT_PORT_TYPE +read_data[27] <= Selector4.DB_MAX_OUTPUT_PORT_TYPE +read_data[28] <= Selector3.DB_MAX_OUTPUT_PORT_TYPE +read_data[29] <= Selector2.DB_MAX_OUTPUT_PORT_TYPE +read_data[30] <= Selector1.DB_MAX_OUTPUT_PORT_TYPE +read_data[31] <= Selector0.DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][0] => Mux31.IN31 +dbg_regs[31][1] => Mux30.IN31 +dbg_regs[31][2] => Mux29.IN31 +dbg_regs[31][3] => Mux28.IN31 +dbg_regs[31][4] => Mux27.IN31 +dbg_regs[31][5] => Mux26.IN31 +dbg_regs[31][6] => Mux25.IN31 +dbg_regs[31][7] => Mux24.IN31 +dbg_regs[31][8] => Mux23.IN31 +dbg_regs[31][9] => Mux22.IN31 +dbg_regs[31][10] => Mux21.IN31 +dbg_regs[31][11] => Mux20.IN31 +dbg_regs[31][12] => Mux19.IN31 +dbg_regs[31][13] => Mux18.IN31 +dbg_regs[31][14] => Mux17.IN31 +dbg_regs[31][15] => Mux16.IN31 +dbg_regs[31][16] => Mux15.IN31 +dbg_regs[31][17] => Mux14.IN31 +dbg_regs[31][18] => Mux13.IN31 +dbg_regs[31][19] => Mux12.IN31 +dbg_regs[31][20] => Mux11.IN31 +dbg_regs[31][21] => Mux10.IN31 +dbg_regs[31][22] => Mux9.IN31 +dbg_regs[31][23] => Mux8.IN31 +dbg_regs[31][24] => Mux7.IN31 +dbg_regs[31][25] => Mux6.IN31 +dbg_regs[31][26] => Mux5.IN31 +dbg_regs[31][27] => Mux4.IN31 +dbg_regs[31][28] => Mux3.IN31 +dbg_regs[31][29] => Mux2.IN31 +dbg_regs[31][30] => Mux1.IN31 +dbg_regs[31][31] => Mux0.IN31 +dbg_regs[30][0] => Mux31.IN30 +dbg_regs[30][1] => Mux30.IN30 +dbg_regs[30][2] => Mux29.IN30 +dbg_regs[30][3] => Mux28.IN30 +dbg_regs[30][4] => Mux27.IN30 +dbg_regs[30][5] => Mux26.IN30 +dbg_regs[30][6] => Mux25.IN30 +dbg_regs[30][7] => Mux24.IN30 +dbg_regs[30][8] => Mux23.IN30 +dbg_regs[30][9] => Mux22.IN30 +dbg_regs[30][10] => Mux21.IN30 +dbg_regs[30][11] => Mux20.IN30 +dbg_regs[30][12] => Mux19.IN30 +dbg_regs[30][13] => Mux18.IN30 +dbg_regs[30][14] => Mux17.IN30 +dbg_regs[30][15] => Mux16.IN30 +dbg_regs[30][16] => Mux15.IN30 +dbg_regs[30][17] => Mux14.IN30 +dbg_regs[30][18] => Mux13.IN30 +dbg_regs[30][19] => Mux12.IN30 +dbg_regs[30][20] => Mux11.IN30 +dbg_regs[30][21] => Mux10.IN30 +dbg_regs[30][22] => Mux9.IN30 +dbg_regs[30][23] => Mux8.IN30 +dbg_regs[30][24] => Mux7.IN30 +dbg_regs[30][25] => Mux6.IN30 +dbg_regs[30][26] => Mux5.IN30 +dbg_regs[30][27] => Mux4.IN30 +dbg_regs[30][28] => Mux3.IN30 +dbg_regs[30][29] => Mux2.IN30 +dbg_regs[30][30] => Mux1.IN30 +dbg_regs[30][31] => Mux0.IN30 +dbg_regs[29][0] => Mux31.IN29 +dbg_regs[29][1] => Mux30.IN29 +dbg_regs[29][2] => Mux29.IN29 +dbg_regs[29][3] => Mux28.IN29 +dbg_regs[29][4] => Mux27.IN29 +dbg_regs[29][5] => Mux26.IN29 +dbg_regs[29][6] => Mux25.IN29 +dbg_regs[29][7] => Mux24.IN29 +dbg_regs[29][8] => Mux23.IN29 +dbg_regs[29][9] => Mux22.IN29 +dbg_regs[29][10] => Mux21.IN29 +dbg_regs[29][11] => Mux20.IN29 +dbg_regs[29][12] => Mux19.IN29 +dbg_regs[29][13] => Mux18.IN29 +dbg_regs[29][14] => Mux17.IN29 +dbg_regs[29][15] => Mux16.IN29 +dbg_regs[29][16] => Mux15.IN29 +dbg_regs[29][17] => Mux14.IN29 +dbg_regs[29][18] => Mux13.IN29 +dbg_regs[29][19] => Mux12.IN29 +dbg_regs[29][20] => Mux11.IN29 +dbg_regs[29][21] => Mux10.IN29 +dbg_regs[29][22] => Mux9.IN29 +dbg_regs[29][23] => Mux8.IN29 +dbg_regs[29][24] => Mux7.IN29 +dbg_regs[29][25] => Mux6.IN29 +dbg_regs[29][26] => Mux5.IN29 +dbg_regs[29][27] => Mux4.IN29 +dbg_regs[29][28] => Mux3.IN29 +dbg_regs[29][29] => Mux2.IN29 +dbg_regs[29][30] => Mux1.IN29 +dbg_regs[29][31] => Mux0.IN29 +dbg_regs[28][0] => Mux31.IN28 +dbg_regs[28][1] => Mux30.IN28 +dbg_regs[28][2] => Mux29.IN28 +dbg_regs[28][3] => Mux28.IN28 +dbg_regs[28][4] => Mux27.IN28 +dbg_regs[28][5] => Mux26.IN28 +dbg_regs[28][6] => Mux25.IN28 +dbg_regs[28][7] => Mux24.IN28 +dbg_regs[28][8] => Mux23.IN28 +dbg_regs[28][9] => Mux22.IN28 +dbg_regs[28][10] => Mux21.IN28 +dbg_regs[28][11] => Mux20.IN28 +dbg_regs[28][12] => Mux19.IN28 +dbg_regs[28][13] => Mux18.IN28 +dbg_regs[28][14] => Mux17.IN28 +dbg_regs[28][15] => Mux16.IN28 +dbg_regs[28][16] => Mux15.IN28 +dbg_regs[28][17] => Mux14.IN28 +dbg_regs[28][18] => Mux13.IN28 +dbg_regs[28][19] => Mux12.IN28 +dbg_regs[28][20] => Mux11.IN28 +dbg_regs[28][21] => Mux10.IN28 +dbg_regs[28][22] => Mux9.IN28 +dbg_regs[28][23] => Mux8.IN28 +dbg_regs[28][24] => Mux7.IN28 +dbg_regs[28][25] => Mux6.IN28 +dbg_regs[28][26] => Mux5.IN28 +dbg_regs[28][27] => Mux4.IN28 +dbg_regs[28][28] => Mux3.IN28 +dbg_regs[28][29] => Mux2.IN28 +dbg_regs[28][30] => Mux1.IN28 +dbg_regs[28][31] => Mux0.IN28 +dbg_regs[27][0] => Mux31.IN27 +dbg_regs[27][1] => Mux30.IN27 +dbg_regs[27][2] => Mux29.IN27 +dbg_regs[27][3] => Mux28.IN27 +dbg_regs[27][4] => Mux27.IN27 +dbg_regs[27][5] => Mux26.IN27 +dbg_regs[27][6] => Mux25.IN27 +dbg_regs[27][7] => Mux24.IN27 +dbg_regs[27][8] => Mux23.IN27 +dbg_regs[27][9] => Mux22.IN27 +dbg_regs[27][10] => Mux21.IN27 +dbg_regs[27][11] => Mux20.IN27 +dbg_regs[27][12] => Mux19.IN27 +dbg_regs[27][13] => Mux18.IN27 +dbg_regs[27][14] => Mux17.IN27 +dbg_regs[27][15] => Mux16.IN27 +dbg_regs[27][16] => Mux15.IN27 +dbg_regs[27][17] => Mux14.IN27 +dbg_regs[27][18] => Mux13.IN27 +dbg_regs[27][19] => Mux12.IN27 +dbg_regs[27][20] => Mux11.IN27 +dbg_regs[27][21] => Mux10.IN27 +dbg_regs[27][22] => Mux9.IN27 +dbg_regs[27][23] => Mux8.IN27 +dbg_regs[27][24] => Mux7.IN27 +dbg_regs[27][25] => Mux6.IN27 +dbg_regs[27][26] => Mux5.IN27 +dbg_regs[27][27] => Mux4.IN27 +dbg_regs[27][28] => Mux3.IN27 +dbg_regs[27][29] => Mux2.IN27 +dbg_regs[27][30] => Mux1.IN27 +dbg_regs[27][31] => Mux0.IN27 +dbg_regs[26][0] => Mux31.IN26 +dbg_regs[26][1] => Mux30.IN26 +dbg_regs[26][2] => Mux29.IN26 +dbg_regs[26][3] => Mux28.IN26 +dbg_regs[26][4] => Mux27.IN26 +dbg_regs[26][5] => Mux26.IN26 +dbg_regs[26][6] => Mux25.IN26 +dbg_regs[26][7] => Mux24.IN26 +dbg_regs[26][8] => Mux23.IN26 +dbg_regs[26][9] => Mux22.IN26 +dbg_regs[26][10] => Mux21.IN26 +dbg_regs[26][11] => Mux20.IN26 +dbg_regs[26][12] => Mux19.IN26 +dbg_regs[26][13] => Mux18.IN26 +dbg_regs[26][14] => Mux17.IN26 +dbg_regs[26][15] => Mux16.IN26 +dbg_regs[26][16] => Mux15.IN26 +dbg_regs[26][17] => Mux14.IN26 +dbg_regs[26][18] => Mux13.IN26 +dbg_regs[26][19] => Mux12.IN26 +dbg_regs[26][20] => Mux11.IN26 +dbg_regs[26][21] => Mux10.IN26 +dbg_regs[26][22] => Mux9.IN26 +dbg_regs[26][23] => Mux8.IN26 +dbg_regs[26][24] => Mux7.IN26 +dbg_regs[26][25] => Mux6.IN26 +dbg_regs[26][26] => Mux5.IN26 +dbg_regs[26][27] => Mux4.IN26 +dbg_regs[26][28] => Mux3.IN26 +dbg_regs[26][29] => Mux2.IN26 +dbg_regs[26][30] => Mux1.IN26 +dbg_regs[26][31] => Mux0.IN26 +dbg_regs[25][0] => Mux31.IN25 +dbg_regs[25][1] => Mux30.IN25 +dbg_regs[25][2] => Mux29.IN25 +dbg_regs[25][3] => Mux28.IN25 +dbg_regs[25][4] => Mux27.IN25 +dbg_regs[25][5] => Mux26.IN25 +dbg_regs[25][6] => Mux25.IN25 +dbg_regs[25][7] => Mux24.IN25 +dbg_regs[25][8] => Mux23.IN25 +dbg_regs[25][9] => Mux22.IN25 +dbg_regs[25][10] => Mux21.IN25 +dbg_regs[25][11] => Mux20.IN25 +dbg_regs[25][12] => Mux19.IN25 +dbg_regs[25][13] => Mux18.IN25 +dbg_regs[25][14] => Mux17.IN25 +dbg_regs[25][15] => Mux16.IN25 +dbg_regs[25][16] => Mux15.IN25 +dbg_regs[25][17] => Mux14.IN25 +dbg_regs[25][18] => Mux13.IN25 +dbg_regs[25][19] => Mux12.IN25 +dbg_regs[25][20] => Mux11.IN25 +dbg_regs[25][21] => Mux10.IN25 +dbg_regs[25][22] => Mux9.IN25 +dbg_regs[25][23] => Mux8.IN25 +dbg_regs[25][24] => Mux7.IN25 +dbg_regs[25][25] => Mux6.IN25 +dbg_regs[25][26] => Mux5.IN25 +dbg_regs[25][27] => Mux4.IN25 +dbg_regs[25][28] => Mux3.IN25 +dbg_regs[25][29] => Mux2.IN25 +dbg_regs[25][30] => Mux1.IN25 +dbg_regs[25][31] => Mux0.IN25 +dbg_regs[24][0] => Mux31.IN24 +dbg_regs[24][1] => Mux30.IN24 +dbg_regs[24][2] => Mux29.IN24 +dbg_regs[24][3] => Mux28.IN24 +dbg_regs[24][4] => Mux27.IN24 +dbg_regs[24][5] => Mux26.IN24 +dbg_regs[24][6] => Mux25.IN24 +dbg_regs[24][7] => Mux24.IN24 +dbg_regs[24][8] => Mux23.IN24 +dbg_regs[24][9] => Mux22.IN24 +dbg_regs[24][10] => Mux21.IN24 +dbg_regs[24][11] => Mux20.IN24 +dbg_regs[24][12] => Mux19.IN24 +dbg_regs[24][13] => Mux18.IN24 +dbg_regs[24][14] => Mux17.IN24 +dbg_regs[24][15] => Mux16.IN24 +dbg_regs[24][16] => Mux15.IN24 +dbg_regs[24][17] => Mux14.IN24 +dbg_regs[24][18] => Mux13.IN24 +dbg_regs[24][19] => Mux12.IN24 +dbg_regs[24][20] => Mux11.IN24 +dbg_regs[24][21] => Mux10.IN24 +dbg_regs[24][22] => Mux9.IN24 +dbg_regs[24][23] => Mux8.IN24 +dbg_regs[24][24] => Mux7.IN24 +dbg_regs[24][25] => Mux6.IN24 +dbg_regs[24][26] => Mux5.IN24 +dbg_regs[24][27] => Mux4.IN24 +dbg_regs[24][28] => Mux3.IN24 +dbg_regs[24][29] => Mux2.IN24 +dbg_regs[24][30] => Mux1.IN24 +dbg_regs[24][31] => Mux0.IN24 +dbg_regs[23][0] => Mux31.IN23 +dbg_regs[23][1] => Mux30.IN23 +dbg_regs[23][2] => Mux29.IN23 +dbg_regs[23][3] => Mux28.IN23 +dbg_regs[23][4] => Mux27.IN23 +dbg_regs[23][5] => Mux26.IN23 +dbg_regs[23][6] => Mux25.IN23 +dbg_regs[23][7] => Mux24.IN23 +dbg_regs[23][8] => Mux23.IN23 +dbg_regs[23][9] => Mux22.IN23 +dbg_regs[23][10] => Mux21.IN23 +dbg_regs[23][11] => Mux20.IN23 +dbg_regs[23][12] => Mux19.IN23 +dbg_regs[23][13] => Mux18.IN23 +dbg_regs[23][14] => Mux17.IN23 +dbg_regs[23][15] => Mux16.IN23 +dbg_regs[23][16] => Mux15.IN23 +dbg_regs[23][17] => Mux14.IN23 +dbg_regs[23][18] => Mux13.IN23 +dbg_regs[23][19] => Mux12.IN23 +dbg_regs[23][20] => Mux11.IN23 +dbg_regs[23][21] => Mux10.IN23 +dbg_regs[23][22] => Mux9.IN23 +dbg_regs[23][23] => Mux8.IN23 +dbg_regs[23][24] => Mux7.IN23 +dbg_regs[23][25] => Mux6.IN23 +dbg_regs[23][26] => Mux5.IN23 +dbg_regs[23][27] => Mux4.IN23 +dbg_regs[23][28] => Mux3.IN23 +dbg_regs[23][29] => Mux2.IN23 +dbg_regs[23][30] => Mux1.IN23 +dbg_regs[23][31] => Mux0.IN23 +dbg_regs[22][0] => Mux31.IN22 +dbg_regs[22][1] => Mux30.IN22 +dbg_regs[22][2] => Mux29.IN22 +dbg_regs[22][3] => Mux28.IN22 +dbg_regs[22][4] => Mux27.IN22 +dbg_regs[22][5] => Mux26.IN22 +dbg_regs[22][6] => Mux25.IN22 +dbg_regs[22][7] => Mux24.IN22 +dbg_regs[22][8] => Mux23.IN22 +dbg_regs[22][9] => Mux22.IN22 +dbg_regs[22][10] => Mux21.IN22 +dbg_regs[22][11] => Mux20.IN22 +dbg_regs[22][12] => Mux19.IN22 +dbg_regs[22][13] => Mux18.IN22 +dbg_regs[22][14] => Mux17.IN22 +dbg_regs[22][15] => Mux16.IN22 +dbg_regs[22][16] => Mux15.IN22 +dbg_regs[22][17] => Mux14.IN22 +dbg_regs[22][18] => Mux13.IN22 +dbg_regs[22][19] => Mux12.IN22 +dbg_regs[22][20] => Mux11.IN22 +dbg_regs[22][21] => Mux10.IN22 +dbg_regs[22][22] => Mux9.IN22 +dbg_regs[22][23] => Mux8.IN22 +dbg_regs[22][24] => Mux7.IN22 +dbg_regs[22][25] => Mux6.IN22 +dbg_regs[22][26] => Mux5.IN22 +dbg_regs[22][27] => Mux4.IN22 +dbg_regs[22][28] => Mux3.IN22 +dbg_regs[22][29] => Mux2.IN22 +dbg_regs[22][30] => Mux1.IN22 +dbg_regs[22][31] => Mux0.IN22 +dbg_regs[21][0] => Mux31.IN21 +dbg_regs[21][1] => Mux30.IN21 +dbg_regs[21][2] => Mux29.IN21 +dbg_regs[21][3] => Mux28.IN21 +dbg_regs[21][4] => Mux27.IN21 +dbg_regs[21][5] => Mux26.IN21 +dbg_regs[21][6] => Mux25.IN21 +dbg_regs[21][7] => Mux24.IN21 +dbg_regs[21][8] => Mux23.IN21 +dbg_regs[21][9] => Mux22.IN21 +dbg_regs[21][10] => Mux21.IN21 +dbg_regs[21][11] => Mux20.IN21 +dbg_regs[21][12] => Mux19.IN21 +dbg_regs[21][13] => Mux18.IN21 +dbg_regs[21][14] => Mux17.IN21 +dbg_regs[21][15] => Mux16.IN21 +dbg_regs[21][16] => Mux15.IN21 +dbg_regs[21][17] => Mux14.IN21 +dbg_regs[21][18] => Mux13.IN21 +dbg_regs[21][19] => Mux12.IN21 +dbg_regs[21][20] => Mux11.IN21 +dbg_regs[21][21] => Mux10.IN21 +dbg_regs[21][22] => Mux9.IN21 +dbg_regs[21][23] => Mux8.IN21 +dbg_regs[21][24] => Mux7.IN21 +dbg_regs[21][25] => Mux6.IN21 +dbg_regs[21][26] => Mux5.IN21 +dbg_regs[21][27] => Mux4.IN21 +dbg_regs[21][28] => Mux3.IN21 +dbg_regs[21][29] => Mux2.IN21 +dbg_regs[21][30] => Mux1.IN21 +dbg_regs[21][31] => Mux0.IN21 +dbg_regs[20][0] => Mux31.IN20 +dbg_regs[20][1] => Mux30.IN20 +dbg_regs[20][2] => Mux29.IN20 +dbg_regs[20][3] => Mux28.IN20 +dbg_regs[20][4] => Mux27.IN20 +dbg_regs[20][5] => Mux26.IN20 +dbg_regs[20][6] => Mux25.IN20 +dbg_regs[20][7] => Mux24.IN20 +dbg_regs[20][8] => Mux23.IN20 +dbg_regs[20][9] => Mux22.IN20 +dbg_regs[20][10] => Mux21.IN20 +dbg_regs[20][11] => Mux20.IN20 +dbg_regs[20][12] => Mux19.IN20 +dbg_regs[20][13] => Mux18.IN20 +dbg_regs[20][14] => Mux17.IN20 +dbg_regs[20][15] => Mux16.IN20 +dbg_regs[20][16] => Mux15.IN20 +dbg_regs[20][17] => Mux14.IN20 +dbg_regs[20][18] => Mux13.IN20 +dbg_regs[20][19] => Mux12.IN20 +dbg_regs[20][20] => Mux11.IN20 +dbg_regs[20][21] => Mux10.IN20 +dbg_regs[20][22] => Mux9.IN20 +dbg_regs[20][23] => Mux8.IN20 +dbg_regs[20][24] => Mux7.IN20 +dbg_regs[20][25] => Mux6.IN20 +dbg_regs[20][26] => Mux5.IN20 +dbg_regs[20][27] => Mux4.IN20 +dbg_regs[20][28] => Mux3.IN20 +dbg_regs[20][29] => Mux2.IN20 +dbg_regs[20][30] => Mux1.IN20 +dbg_regs[20][31] => Mux0.IN20 +dbg_regs[19][0] => Mux31.IN19 +dbg_regs[19][1] => Mux30.IN19 +dbg_regs[19][2] => Mux29.IN19 +dbg_regs[19][3] => Mux28.IN19 +dbg_regs[19][4] => Mux27.IN19 +dbg_regs[19][5] => Mux26.IN19 +dbg_regs[19][6] => Mux25.IN19 +dbg_regs[19][7] => Mux24.IN19 +dbg_regs[19][8] => Mux23.IN19 +dbg_regs[19][9] => Mux22.IN19 +dbg_regs[19][10] => Mux21.IN19 +dbg_regs[19][11] => Mux20.IN19 +dbg_regs[19][12] => Mux19.IN19 +dbg_regs[19][13] => Mux18.IN19 +dbg_regs[19][14] => Mux17.IN19 +dbg_regs[19][15] => Mux16.IN19 +dbg_regs[19][16] => Mux15.IN19 +dbg_regs[19][17] => Mux14.IN19 +dbg_regs[19][18] => Mux13.IN19 +dbg_regs[19][19] => Mux12.IN19 +dbg_regs[19][20] => Mux11.IN19 +dbg_regs[19][21] => Mux10.IN19 +dbg_regs[19][22] => Mux9.IN19 +dbg_regs[19][23] => Mux8.IN19 +dbg_regs[19][24] => Mux7.IN19 +dbg_regs[19][25] => Mux6.IN19 +dbg_regs[19][26] => Mux5.IN19 +dbg_regs[19][27] => Mux4.IN19 +dbg_regs[19][28] => Mux3.IN19 +dbg_regs[19][29] => Mux2.IN19 +dbg_regs[19][30] => Mux1.IN19 +dbg_regs[19][31] => Mux0.IN19 +dbg_regs[18][0] => Mux31.IN18 +dbg_regs[18][1] => Mux30.IN18 +dbg_regs[18][2] => Mux29.IN18 +dbg_regs[18][3] => Mux28.IN18 +dbg_regs[18][4] => Mux27.IN18 +dbg_regs[18][5] => Mux26.IN18 +dbg_regs[18][6] => Mux25.IN18 +dbg_regs[18][7] => Mux24.IN18 +dbg_regs[18][8] => Mux23.IN18 +dbg_regs[18][9] => Mux22.IN18 +dbg_regs[18][10] => Mux21.IN18 +dbg_regs[18][11] => Mux20.IN18 +dbg_regs[18][12] => Mux19.IN18 +dbg_regs[18][13] => Mux18.IN18 +dbg_regs[18][14] => Mux17.IN18 +dbg_regs[18][15] => Mux16.IN18 +dbg_regs[18][16] => Mux15.IN18 +dbg_regs[18][17] => Mux14.IN18 +dbg_regs[18][18] => Mux13.IN18 +dbg_regs[18][19] => Mux12.IN18 +dbg_regs[18][20] => Mux11.IN18 +dbg_regs[18][21] => Mux10.IN18 +dbg_regs[18][22] => Mux9.IN18 +dbg_regs[18][23] => Mux8.IN18 +dbg_regs[18][24] => Mux7.IN18 +dbg_regs[18][25] => Mux6.IN18 +dbg_regs[18][26] => Mux5.IN18 +dbg_regs[18][27] => Mux4.IN18 +dbg_regs[18][28] => Mux3.IN18 +dbg_regs[18][29] => Mux2.IN18 +dbg_regs[18][30] => Mux1.IN18 +dbg_regs[18][31] => Mux0.IN18 +dbg_regs[17][0] => Mux31.IN17 +dbg_regs[17][1] => Mux30.IN17 +dbg_regs[17][2] => Mux29.IN17 +dbg_regs[17][3] => Mux28.IN17 +dbg_regs[17][4] => Mux27.IN17 +dbg_regs[17][5] => Mux26.IN17 +dbg_regs[17][6] => Mux25.IN17 +dbg_regs[17][7] => Mux24.IN17 +dbg_regs[17][8] => Mux23.IN17 +dbg_regs[17][9] => Mux22.IN17 +dbg_regs[17][10] => Mux21.IN17 +dbg_regs[17][11] => Mux20.IN17 +dbg_regs[17][12] => Mux19.IN17 +dbg_regs[17][13] => Mux18.IN17 +dbg_regs[17][14] => Mux17.IN17 +dbg_regs[17][15] => Mux16.IN17 +dbg_regs[17][16] => Mux15.IN17 +dbg_regs[17][17] => Mux14.IN17 +dbg_regs[17][18] => Mux13.IN17 +dbg_regs[17][19] => Mux12.IN17 +dbg_regs[17][20] => Mux11.IN17 +dbg_regs[17][21] => Mux10.IN17 +dbg_regs[17][22] => Mux9.IN17 +dbg_regs[17][23] => Mux8.IN17 +dbg_regs[17][24] => Mux7.IN17 +dbg_regs[17][25] => Mux6.IN17 +dbg_regs[17][26] => Mux5.IN17 +dbg_regs[17][27] => Mux4.IN17 +dbg_regs[17][28] => Mux3.IN17 +dbg_regs[17][29] => Mux2.IN17 +dbg_regs[17][30] => Mux1.IN17 +dbg_regs[17][31] => Mux0.IN17 +dbg_regs[16][0] => Mux31.IN16 +dbg_regs[16][1] => Mux30.IN16 +dbg_regs[16][2] => Mux29.IN16 +dbg_regs[16][3] => Mux28.IN16 +dbg_regs[16][4] => Mux27.IN16 +dbg_regs[16][5] => Mux26.IN16 +dbg_regs[16][6] => Mux25.IN16 +dbg_regs[16][7] => Mux24.IN16 +dbg_regs[16][8] => Mux23.IN16 +dbg_regs[16][9] => Mux22.IN16 +dbg_regs[16][10] => Mux21.IN16 +dbg_regs[16][11] => Mux20.IN16 +dbg_regs[16][12] => Mux19.IN16 +dbg_regs[16][13] => Mux18.IN16 +dbg_regs[16][14] => Mux17.IN16 +dbg_regs[16][15] => Mux16.IN16 +dbg_regs[16][16] => Mux15.IN16 +dbg_regs[16][17] => Mux14.IN16 +dbg_regs[16][18] => Mux13.IN16 +dbg_regs[16][19] => Mux12.IN16 +dbg_regs[16][20] => Mux11.IN16 +dbg_regs[16][21] => Mux10.IN16 +dbg_regs[16][22] => Mux9.IN16 +dbg_regs[16][23] => Mux8.IN16 +dbg_regs[16][24] => Mux7.IN16 +dbg_regs[16][25] => Mux6.IN16 +dbg_regs[16][26] => Mux5.IN16 +dbg_regs[16][27] => Mux4.IN16 +dbg_regs[16][28] => Mux3.IN16 +dbg_regs[16][29] => Mux2.IN16 +dbg_regs[16][30] => Mux1.IN16 +dbg_regs[16][31] => Mux0.IN16 +dbg_regs[15][0] => Mux31.IN15 +dbg_regs[15][1] => Mux30.IN15 +dbg_regs[15][2] => Mux29.IN15 +dbg_regs[15][3] => Mux28.IN15 +dbg_regs[15][4] => Mux27.IN15 +dbg_regs[15][5] => Mux26.IN15 +dbg_regs[15][6] => Mux25.IN15 +dbg_regs[15][7] => Mux24.IN15 +dbg_regs[15][8] => Mux23.IN15 +dbg_regs[15][9] => Mux22.IN15 +dbg_regs[15][10] => Mux21.IN15 +dbg_regs[15][11] => Mux20.IN15 +dbg_regs[15][12] => Mux19.IN15 +dbg_regs[15][13] => Mux18.IN15 +dbg_regs[15][14] => Mux17.IN15 +dbg_regs[15][15] => Mux16.IN15 +dbg_regs[15][16] => Mux15.IN15 +dbg_regs[15][17] => Mux14.IN15 +dbg_regs[15][18] => Mux13.IN15 +dbg_regs[15][19] => Mux12.IN15 +dbg_regs[15][20] => Mux11.IN15 +dbg_regs[15][21] => Mux10.IN15 +dbg_regs[15][22] => Mux9.IN15 +dbg_regs[15][23] => Mux8.IN15 +dbg_regs[15][24] => Mux7.IN15 +dbg_regs[15][25] => Mux6.IN15 +dbg_regs[15][26] => Mux5.IN15 +dbg_regs[15][27] => Mux4.IN15 +dbg_regs[15][28] => Mux3.IN15 +dbg_regs[15][29] => Mux2.IN15 +dbg_regs[15][30] => Mux1.IN15 +dbg_regs[15][31] => Mux0.IN15 +dbg_regs[14][0] => Mux31.IN14 +dbg_regs[14][1] => Mux30.IN14 +dbg_regs[14][2] => Mux29.IN14 +dbg_regs[14][3] => Mux28.IN14 +dbg_regs[14][4] => Mux27.IN14 +dbg_regs[14][5] => Mux26.IN14 +dbg_regs[14][6] => Mux25.IN14 +dbg_regs[14][7] => Mux24.IN14 +dbg_regs[14][8] => Mux23.IN14 +dbg_regs[14][9] => Mux22.IN14 +dbg_regs[14][10] => Mux21.IN14 +dbg_regs[14][11] => Mux20.IN14 +dbg_regs[14][12] => Mux19.IN14 +dbg_regs[14][13] => Mux18.IN14 +dbg_regs[14][14] => Mux17.IN14 +dbg_regs[14][15] => Mux16.IN14 +dbg_regs[14][16] => Mux15.IN14 +dbg_regs[14][17] => Mux14.IN14 +dbg_regs[14][18] => Mux13.IN14 +dbg_regs[14][19] => Mux12.IN14 +dbg_regs[14][20] => Mux11.IN14 +dbg_regs[14][21] => Mux10.IN14 +dbg_regs[14][22] => Mux9.IN14 +dbg_regs[14][23] => Mux8.IN14 +dbg_regs[14][24] => Mux7.IN14 +dbg_regs[14][25] => Mux6.IN14 +dbg_regs[14][26] => Mux5.IN14 +dbg_regs[14][27] => Mux4.IN14 +dbg_regs[14][28] => Mux3.IN14 +dbg_regs[14][29] => Mux2.IN14 +dbg_regs[14][30] => Mux1.IN14 +dbg_regs[14][31] => Mux0.IN14 +dbg_regs[13][0] => Mux31.IN13 +dbg_regs[13][1] => Mux30.IN13 +dbg_regs[13][2] => Mux29.IN13 +dbg_regs[13][3] => Mux28.IN13 +dbg_regs[13][4] => Mux27.IN13 +dbg_regs[13][5] => Mux26.IN13 +dbg_regs[13][6] => Mux25.IN13 +dbg_regs[13][7] => Mux24.IN13 +dbg_regs[13][8] => Mux23.IN13 +dbg_regs[13][9] => Mux22.IN13 +dbg_regs[13][10] => Mux21.IN13 +dbg_regs[13][11] => Mux20.IN13 +dbg_regs[13][12] => Mux19.IN13 +dbg_regs[13][13] => Mux18.IN13 +dbg_regs[13][14] => Mux17.IN13 +dbg_regs[13][15] => Mux16.IN13 +dbg_regs[13][16] => Mux15.IN13 +dbg_regs[13][17] => Mux14.IN13 +dbg_regs[13][18] => Mux13.IN13 +dbg_regs[13][19] => Mux12.IN13 +dbg_regs[13][20] => Mux11.IN13 +dbg_regs[13][21] => Mux10.IN13 +dbg_regs[13][22] => Mux9.IN13 +dbg_regs[13][23] => Mux8.IN13 +dbg_regs[13][24] => Mux7.IN13 +dbg_regs[13][25] => Mux6.IN13 +dbg_regs[13][26] => Mux5.IN13 +dbg_regs[13][27] => Mux4.IN13 +dbg_regs[13][28] => Mux3.IN13 +dbg_regs[13][29] => Mux2.IN13 +dbg_regs[13][30] => Mux1.IN13 +dbg_regs[13][31] => Mux0.IN13 +dbg_regs[12][0] => Mux31.IN12 +dbg_regs[12][1] => Mux30.IN12 +dbg_regs[12][2] => Mux29.IN12 +dbg_regs[12][3] => Mux28.IN12 +dbg_regs[12][4] => Mux27.IN12 +dbg_regs[12][5] => Mux26.IN12 +dbg_regs[12][6] => Mux25.IN12 +dbg_regs[12][7] => Mux24.IN12 +dbg_regs[12][8] => Mux23.IN12 +dbg_regs[12][9] => Mux22.IN12 +dbg_regs[12][10] => Mux21.IN12 +dbg_regs[12][11] => Mux20.IN12 +dbg_regs[12][12] => Mux19.IN12 +dbg_regs[12][13] => Mux18.IN12 +dbg_regs[12][14] => Mux17.IN12 +dbg_regs[12][15] => Mux16.IN12 +dbg_regs[12][16] => Mux15.IN12 +dbg_regs[12][17] => Mux14.IN12 +dbg_regs[12][18] => Mux13.IN12 +dbg_regs[12][19] => Mux12.IN12 +dbg_regs[12][20] => Mux11.IN12 +dbg_regs[12][21] => Mux10.IN12 +dbg_regs[12][22] => Mux9.IN12 +dbg_regs[12][23] => Mux8.IN12 +dbg_regs[12][24] => Mux7.IN12 +dbg_regs[12][25] => Mux6.IN12 +dbg_regs[12][26] => Mux5.IN12 +dbg_regs[12][27] => Mux4.IN12 +dbg_regs[12][28] => Mux3.IN12 +dbg_regs[12][29] => Mux2.IN12 +dbg_regs[12][30] => Mux1.IN12 +dbg_regs[12][31] => Mux0.IN12 +dbg_regs[11][0] => Mux31.IN11 +dbg_regs[11][1] => Mux30.IN11 +dbg_regs[11][2] => Mux29.IN11 +dbg_regs[11][3] => Mux28.IN11 +dbg_regs[11][4] => Mux27.IN11 +dbg_regs[11][5] => Mux26.IN11 +dbg_regs[11][6] => Mux25.IN11 +dbg_regs[11][7] => Mux24.IN11 +dbg_regs[11][8] => Mux23.IN11 +dbg_regs[11][9] => Mux22.IN11 +dbg_regs[11][10] => Mux21.IN11 +dbg_regs[11][11] => Mux20.IN11 +dbg_regs[11][12] => Mux19.IN11 +dbg_regs[11][13] => Mux18.IN11 +dbg_regs[11][14] => Mux17.IN11 +dbg_regs[11][15] => Mux16.IN11 +dbg_regs[11][16] => Mux15.IN11 +dbg_regs[11][17] => Mux14.IN11 +dbg_regs[11][18] => Mux13.IN11 +dbg_regs[11][19] => Mux12.IN11 +dbg_regs[11][20] => Mux11.IN11 +dbg_regs[11][21] => Mux10.IN11 +dbg_regs[11][22] => Mux9.IN11 +dbg_regs[11][23] => Mux8.IN11 +dbg_regs[11][24] => Mux7.IN11 +dbg_regs[11][25] => Mux6.IN11 +dbg_regs[11][26] => Mux5.IN11 +dbg_regs[11][27] => Mux4.IN11 +dbg_regs[11][28] => Mux3.IN11 +dbg_regs[11][29] => Mux2.IN11 +dbg_regs[11][30] => Mux1.IN11 +dbg_regs[11][31] => Mux0.IN11 +dbg_regs[10][0] => Mux31.IN10 +dbg_regs[10][1] => Mux30.IN10 +dbg_regs[10][2] => Mux29.IN10 +dbg_regs[10][3] => Mux28.IN10 +dbg_regs[10][4] => Mux27.IN10 +dbg_regs[10][5] => Mux26.IN10 +dbg_regs[10][6] => Mux25.IN10 +dbg_regs[10][7] => Mux24.IN10 +dbg_regs[10][8] => Mux23.IN10 +dbg_regs[10][9] => Mux22.IN10 +dbg_regs[10][10] => Mux21.IN10 +dbg_regs[10][11] => Mux20.IN10 +dbg_regs[10][12] => Mux19.IN10 +dbg_regs[10][13] => Mux18.IN10 +dbg_regs[10][14] => Mux17.IN10 +dbg_regs[10][15] => Mux16.IN10 +dbg_regs[10][16] => Mux15.IN10 +dbg_regs[10][17] => Mux14.IN10 +dbg_regs[10][18] => Mux13.IN10 +dbg_regs[10][19] => Mux12.IN10 +dbg_regs[10][20] => Mux11.IN10 +dbg_regs[10][21] => Mux10.IN10 +dbg_regs[10][22] => Mux9.IN10 +dbg_regs[10][23] => Mux8.IN10 +dbg_regs[10][24] => Mux7.IN10 +dbg_regs[10][25] => Mux6.IN10 +dbg_regs[10][26] => Mux5.IN10 +dbg_regs[10][27] => Mux4.IN10 +dbg_regs[10][28] => Mux3.IN10 +dbg_regs[10][29] => Mux2.IN10 +dbg_regs[10][30] => Mux1.IN10 +dbg_regs[10][31] => Mux0.IN10 +dbg_regs[9][0] => Mux31.IN9 +dbg_regs[9][1] => Mux30.IN9 +dbg_regs[9][2] => Mux29.IN9 +dbg_regs[9][3] => Mux28.IN9 +dbg_regs[9][4] => Mux27.IN9 +dbg_regs[9][5] => Mux26.IN9 +dbg_regs[9][6] => Mux25.IN9 +dbg_regs[9][7] => Mux24.IN9 +dbg_regs[9][8] => Mux23.IN9 +dbg_regs[9][9] => Mux22.IN9 +dbg_regs[9][10] => Mux21.IN9 +dbg_regs[9][11] => Mux20.IN9 +dbg_regs[9][12] => Mux19.IN9 +dbg_regs[9][13] => Mux18.IN9 +dbg_regs[9][14] => Mux17.IN9 +dbg_regs[9][15] => Mux16.IN9 +dbg_regs[9][16] => Mux15.IN9 +dbg_regs[9][17] => Mux14.IN9 +dbg_regs[9][18] => Mux13.IN9 +dbg_regs[9][19] => Mux12.IN9 +dbg_regs[9][20] => Mux11.IN9 +dbg_regs[9][21] => Mux10.IN9 +dbg_regs[9][22] => Mux9.IN9 +dbg_regs[9][23] => Mux8.IN9 +dbg_regs[9][24] => Mux7.IN9 +dbg_regs[9][25] => Mux6.IN9 +dbg_regs[9][26] => Mux5.IN9 +dbg_regs[9][27] => Mux4.IN9 +dbg_regs[9][28] => Mux3.IN9 +dbg_regs[9][29] => Mux2.IN9 +dbg_regs[9][30] => Mux1.IN9 +dbg_regs[9][31] => Mux0.IN9 +dbg_regs[8][0] => Mux31.IN8 +dbg_regs[8][1] => Mux30.IN8 +dbg_regs[8][2] => Mux29.IN8 +dbg_regs[8][3] => Mux28.IN8 +dbg_regs[8][4] => Mux27.IN8 +dbg_regs[8][5] => Mux26.IN8 +dbg_regs[8][6] => Mux25.IN8 +dbg_regs[8][7] => Mux24.IN8 +dbg_regs[8][8] => Mux23.IN8 +dbg_regs[8][9] => Mux22.IN8 +dbg_regs[8][10] => Mux21.IN8 +dbg_regs[8][11] => Mux20.IN8 +dbg_regs[8][12] => Mux19.IN8 +dbg_regs[8][13] => Mux18.IN8 +dbg_regs[8][14] => Mux17.IN8 +dbg_regs[8][15] => Mux16.IN8 +dbg_regs[8][16] => Mux15.IN8 +dbg_regs[8][17] => Mux14.IN8 +dbg_regs[8][18] => Mux13.IN8 +dbg_regs[8][19] => Mux12.IN8 +dbg_regs[8][20] => Mux11.IN8 +dbg_regs[8][21] => Mux10.IN8 +dbg_regs[8][22] => Mux9.IN8 +dbg_regs[8][23] => Mux8.IN8 +dbg_regs[8][24] => Mux7.IN8 +dbg_regs[8][25] => Mux6.IN8 +dbg_regs[8][26] => Mux5.IN8 +dbg_regs[8][27] => Mux4.IN8 +dbg_regs[8][28] => Mux3.IN8 +dbg_regs[8][29] => Mux2.IN8 +dbg_regs[8][30] => Mux1.IN8 +dbg_regs[8][31] => Mux0.IN8 +dbg_regs[7][0] => Mux31.IN7 +dbg_regs[7][1] => Mux30.IN7 +dbg_regs[7][2] => Mux29.IN7 +dbg_regs[7][3] => Mux28.IN7 +dbg_regs[7][4] => Mux27.IN7 +dbg_regs[7][5] => Mux26.IN7 +dbg_regs[7][6] => Mux25.IN7 +dbg_regs[7][7] => Mux24.IN7 +dbg_regs[7][8] => Mux23.IN7 +dbg_regs[7][9] => Mux22.IN7 +dbg_regs[7][10] => Mux21.IN7 +dbg_regs[7][11] => Mux20.IN7 +dbg_regs[7][12] => Mux19.IN7 +dbg_regs[7][13] => Mux18.IN7 +dbg_regs[7][14] => Mux17.IN7 +dbg_regs[7][15] => Mux16.IN7 +dbg_regs[7][16] => Mux15.IN7 +dbg_regs[7][17] => Mux14.IN7 +dbg_regs[7][18] => Mux13.IN7 +dbg_regs[7][19] => Mux12.IN7 +dbg_regs[7][20] => Mux11.IN7 +dbg_regs[7][21] => Mux10.IN7 +dbg_regs[7][22] => Mux9.IN7 +dbg_regs[7][23] => Mux8.IN7 +dbg_regs[7][24] => Mux7.IN7 +dbg_regs[7][25] => Mux6.IN7 +dbg_regs[7][26] => Mux5.IN7 +dbg_regs[7][27] => Mux4.IN7 +dbg_regs[7][28] => Mux3.IN7 +dbg_regs[7][29] => Mux2.IN7 +dbg_regs[7][30] => Mux1.IN7 +dbg_regs[7][31] => Mux0.IN7 +dbg_regs[6][0] => Mux31.IN6 +dbg_regs[6][1] => Mux30.IN6 +dbg_regs[6][2] => Mux29.IN6 +dbg_regs[6][3] => Mux28.IN6 +dbg_regs[6][4] => Mux27.IN6 +dbg_regs[6][5] => Mux26.IN6 +dbg_regs[6][6] => Mux25.IN6 +dbg_regs[6][7] => Mux24.IN6 +dbg_regs[6][8] => Mux23.IN6 +dbg_regs[6][9] => Mux22.IN6 +dbg_regs[6][10] => Mux21.IN6 +dbg_regs[6][11] => Mux20.IN6 +dbg_regs[6][12] => Mux19.IN6 +dbg_regs[6][13] => Mux18.IN6 +dbg_regs[6][14] => Mux17.IN6 +dbg_regs[6][15] => Mux16.IN6 +dbg_regs[6][16] => Mux15.IN6 +dbg_regs[6][17] => Mux14.IN6 +dbg_regs[6][18] => Mux13.IN6 +dbg_regs[6][19] => Mux12.IN6 +dbg_regs[6][20] => Mux11.IN6 +dbg_regs[6][21] => Mux10.IN6 +dbg_regs[6][22] => Mux9.IN6 +dbg_regs[6][23] => Mux8.IN6 +dbg_regs[6][24] => Mux7.IN6 +dbg_regs[6][25] => Mux6.IN6 +dbg_regs[6][26] => Mux5.IN6 +dbg_regs[6][27] => Mux4.IN6 +dbg_regs[6][28] => Mux3.IN6 +dbg_regs[6][29] => Mux2.IN6 +dbg_regs[6][30] => Mux1.IN6 +dbg_regs[6][31] => Mux0.IN6 +dbg_regs[5][0] => Mux31.IN5 +dbg_regs[5][1] => Mux30.IN5 +dbg_regs[5][2] => Mux29.IN5 +dbg_regs[5][3] => Mux28.IN5 +dbg_regs[5][4] => Mux27.IN5 +dbg_regs[5][5] => Mux26.IN5 +dbg_regs[5][6] => Mux25.IN5 +dbg_regs[5][7] => Mux24.IN5 +dbg_regs[5][8] => Mux23.IN5 +dbg_regs[5][9] => Mux22.IN5 +dbg_regs[5][10] => Mux21.IN5 +dbg_regs[5][11] => Mux20.IN5 +dbg_regs[5][12] => Mux19.IN5 +dbg_regs[5][13] => Mux18.IN5 +dbg_regs[5][14] => Mux17.IN5 +dbg_regs[5][15] => Mux16.IN5 +dbg_regs[5][16] => Mux15.IN5 +dbg_regs[5][17] => Mux14.IN5 +dbg_regs[5][18] => Mux13.IN5 +dbg_regs[5][19] => Mux12.IN5 +dbg_regs[5][20] => Mux11.IN5 +dbg_regs[5][21] => Mux10.IN5 +dbg_regs[5][22] => Mux9.IN5 +dbg_regs[5][23] => Mux8.IN5 +dbg_regs[5][24] => Mux7.IN5 +dbg_regs[5][25] => Mux6.IN5 +dbg_regs[5][26] => Mux5.IN5 +dbg_regs[5][27] => Mux4.IN5 +dbg_regs[5][28] => Mux3.IN5 +dbg_regs[5][29] => Mux2.IN5 +dbg_regs[5][30] => Mux1.IN5 +dbg_regs[5][31] => Mux0.IN5 +dbg_regs[4][0] => Mux31.IN4 +dbg_regs[4][1] => Mux30.IN4 +dbg_regs[4][2] => Mux29.IN4 +dbg_regs[4][3] => Mux28.IN4 +dbg_regs[4][4] => Mux27.IN4 +dbg_regs[4][5] => Mux26.IN4 +dbg_regs[4][6] => Mux25.IN4 +dbg_regs[4][7] => Mux24.IN4 +dbg_regs[4][8] => Mux23.IN4 +dbg_regs[4][9] => Mux22.IN4 +dbg_regs[4][10] => Mux21.IN4 +dbg_regs[4][11] => Mux20.IN4 +dbg_regs[4][12] => Mux19.IN4 +dbg_regs[4][13] => Mux18.IN4 +dbg_regs[4][14] => Mux17.IN4 +dbg_regs[4][15] => Mux16.IN4 +dbg_regs[4][16] => Mux15.IN4 +dbg_regs[4][17] => Mux14.IN4 +dbg_regs[4][18] => Mux13.IN4 +dbg_regs[4][19] => Mux12.IN4 +dbg_regs[4][20] => Mux11.IN4 +dbg_regs[4][21] => Mux10.IN4 +dbg_regs[4][22] => Mux9.IN4 +dbg_regs[4][23] => Mux8.IN4 +dbg_regs[4][24] => Mux7.IN4 +dbg_regs[4][25] => Mux6.IN4 +dbg_regs[4][26] => Mux5.IN4 +dbg_regs[4][27] => Mux4.IN4 +dbg_regs[4][28] => Mux3.IN4 +dbg_regs[4][29] => Mux2.IN4 +dbg_regs[4][30] => Mux1.IN4 +dbg_regs[4][31] => Mux0.IN4 +dbg_regs[3][0] => Mux31.IN3 +dbg_regs[3][1] => Mux30.IN3 +dbg_regs[3][2] => Mux29.IN3 +dbg_regs[3][3] => Mux28.IN3 +dbg_regs[3][4] => Mux27.IN3 +dbg_regs[3][5] => Mux26.IN3 +dbg_regs[3][6] => Mux25.IN3 +dbg_regs[3][7] => Mux24.IN3 +dbg_regs[3][8] => Mux23.IN3 +dbg_regs[3][9] => Mux22.IN3 +dbg_regs[3][10] => Mux21.IN3 +dbg_regs[3][11] => Mux20.IN3 +dbg_regs[3][12] => Mux19.IN3 +dbg_regs[3][13] => Mux18.IN3 +dbg_regs[3][14] => Mux17.IN3 +dbg_regs[3][15] => Mux16.IN3 +dbg_regs[3][16] => Mux15.IN3 +dbg_regs[3][17] => Mux14.IN3 +dbg_regs[3][18] => Mux13.IN3 +dbg_regs[3][19] => Mux12.IN3 +dbg_regs[3][20] => Mux11.IN3 +dbg_regs[3][21] => Mux10.IN3 +dbg_regs[3][22] => Mux9.IN3 +dbg_regs[3][23] => Mux8.IN3 +dbg_regs[3][24] => Mux7.IN3 +dbg_regs[3][25] => Mux6.IN3 +dbg_regs[3][26] => Mux5.IN3 +dbg_regs[3][27] => Mux4.IN3 +dbg_regs[3][28] => Mux3.IN3 +dbg_regs[3][29] => Mux2.IN3 +dbg_regs[3][30] => Mux1.IN3 +dbg_regs[3][31] => Mux0.IN3 +dbg_regs[2][0] => Mux31.IN2 +dbg_regs[2][1] => Mux30.IN2 +dbg_regs[2][2] => Mux29.IN2 +dbg_regs[2][3] => Mux28.IN2 +dbg_regs[2][4] => Mux27.IN2 +dbg_regs[2][5] => Mux26.IN2 +dbg_regs[2][6] => Mux25.IN2 +dbg_regs[2][7] => Mux24.IN2 +dbg_regs[2][8] => Mux23.IN2 +dbg_regs[2][9] => Mux22.IN2 +dbg_regs[2][10] => Mux21.IN2 +dbg_regs[2][11] => Mux20.IN2 +dbg_regs[2][12] => Mux19.IN2 +dbg_regs[2][13] => Mux18.IN2 +dbg_regs[2][14] => Mux17.IN2 +dbg_regs[2][15] => Mux16.IN2 +dbg_regs[2][16] => Mux15.IN2 +dbg_regs[2][17] => Mux14.IN2 +dbg_regs[2][18] => Mux13.IN2 +dbg_regs[2][19] => Mux12.IN2 +dbg_regs[2][20] => Mux11.IN2 +dbg_regs[2][21] => Mux10.IN2 +dbg_regs[2][22] => Mux9.IN2 +dbg_regs[2][23] => Mux8.IN2 +dbg_regs[2][24] => Mux7.IN2 +dbg_regs[2][25] => Mux6.IN2 +dbg_regs[2][26] => Mux5.IN2 +dbg_regs[2][27] => Mux4.IN2 +dbg_regs[2][28] => Mux3.IN2 +dbg_regs[2][29] => Mux2.IN2 +dbg_regs[2][30] => Mux1.IN2 +dbg_regs[2][31] => Mux0.IN2 +dbg_regs[1][0] => Mux31.IN1 +dbg_regs[1][1] => Mux30.IN1 +dbg_regs[1][2] => Mux29.IN1 +dbg_regs[1][3] => Mux28.IN1 +dbg_regs[1][4] => Mux27.IN1 +dbg_regs[1][5] => Mux26.IN1 +dbg_regs[1][6] => Mux25.IN1 +dbg_regs[1][7] => Mux24.IN1 +dbg_regs[1][8] => Mux23.IN1 +dbg_regs[1][9] => Mux22.IN1 +dbg_regs[1][10] => Mux21.IN1 +dbg_regs[1][11] => Mux20.IN1 +dbg_regs[1][12] => Mux19.IN1 +dbg_regs[1][13] => Mux18.IN1 +dbg_regs[1][14] => Mux17.IN1 +dbg_regs[1][15] => Mux16.IN1 +dbg_regs[1][16] => Mux15.IN1 +dbg_regs[1][17] => Mux14.IN1 +dbg_regs[1][18] => Mux13.IN1 +dbg_regs[1][19] => Mux12.IN1 +dbg_regs[1][20] => Mux11.IN1 +dbg_regs[1][21] => Mux10.IN1 +dbg_regs[1][22] => Mux9.IN1 +dbg_regs[1][23] => Mux8.IN1 +dbg_regs[1][24] => Mux7.IN1 +dbg_regs[1][25] => Mux6.IN1 +dbg_regs[1][26] => Mux5.IN1 +dbg_regs[1][27] => Mux4.IN1 +dbg_regs[1][28] => Mux3.IN1 +dbg_regs[1][29] => Mux2.IN1 +dbg_regs[1][30] => Mux1.IN1 +dbg_regs[1][31] => Mux0.IN1 +dbg_regs[0][0] => Mux31.IN0 +dbg_regs[0][1] => Mux30.IN0 +dbg_regs[0][2] => Mux29.IN0 +dbg_regs[0][3] => Mux28.IN0 +dbg_regs[0][4] => Mux27.IN0 +dbg_regs[0][5] => Mux26.IN0 +dbg_regs[0][6] => Mux25.IN0 +dbg_regs[0][7] => Mux24.IN0 +dbg_regs[0][8] => Mux23.IN0 +dbg_regs[0][9] => Mux22.IN0 +dbg_regs[0][10] => Mux21.IN0 +dbg_regs[0][11] => Mux20.IN0 +dbg_regs[0][12] => Mux19.IN0 +dbg_regs[0][13] => Mux18.IN0 +dbg_regs[0][14] => Mux17.IN0 +dbg_regs[0][15] => Mux16.IN0 +dbg_regs[0][16] => Mux15.IN0 +dbg_regs[0][17] => Mux14.IN0 +dbg_regs[0][18] => Mux13.IN0 +dbg_regs[0][19] => Mux12.IN0 +dbg_regs[0][20] => Mux11.IN0 +dbg_regs[0][21] => Mux10.IN0 +dbg_regs[0][22] => Mux9.IN0 +dbg_regs[0][23] => Mux8.IN0 +dbg_regs[0][24] => Mux7.IN0 +dbg_regs[0][25] => Mux6.IN0 +dbg_regs[0][26] => Mux5.IN0 +dbg_regs[0][27] => Mux4.IN0 +dbg_regs[0][28] => Mux3.IN0 +dbg_regs[0][29] => Mux2.IN0 +dbg_regs[0][30] => Mux1.IN0 +dbg_regs[0][31] => Mux0.IN0 +dbg_pc[0] => Selector31.IN4 +dbg_pc[1] => Selector30.IN4 +dbg_pc[2] => Selector29.IN4 +dbg_pc[3] => Selector28.IN4 +dbg_pc[4] => Selector27.IN4 +dbg_pc[5] => Selector26.IN4 +dbg_pc[6] => Selector25.IN4 +dbg_pc[7] => Selector24.IN4 +dbg_pc[8] => Selector23.IN4 +dbg_pc[9] => Selector22.IN4 +dbg_pc[10] => Selector21.IN5 +dbg_pc[11] => Selector20.IN5 +dbg_pc[12] => Selector19.IN5 +dbg_pc[13] => Selector18.IN5 +dbg_pc[14] => Selector17.IN5 +dbg_pc[15] => Selector16.IN5 +dbg_pc[16] => Selector15.IN5 +dbg_pc[17] => Selector14.IN5 +dbg_pc[18] => Selector13.IN5 +dbg_pc[19] => Selector12.IN5 +dbg_pc[20] => Selector11.IN5 +dbg_pc[21] => Selector10.IN5 +dbg_pc[22] => Selector9.IN5 +dbg_pc[23] => Selector8.IN5 +dbg_pc[24] => Selector7.IN5 +dbg_pc[25] => Selector6.IN5 +dbg_pc[26] => Selector5.IN5 +dbg_pc[27] => Selector4.IN5 +dbg_pc[28] => Selector3.IN5 +dbg_pc[29] => Selector2.IN5 +dbg_pc[30] => Selector1.IN5 +dbg_pc[31] => Selector0.IN5 +LEDR[0] <= LEDR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +LEDR[1] <= LEDR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +LEDR[2] <= LEDR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +LEDR[3] <= LEDR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +LEDR[4] <= LEDR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +LEDR[5] <= LEDR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +LEDR[6] <= LEDR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +LEDR[7] <= LEDR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +LEDR[8] <= LEDR[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +LEDR[9] <= LEDR[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|top|utoss_riscv:core +clk => ControlFSM:control_fsm.clk +clk => fetch:fetch.clk +clk => registerFile:RegFile.clk +clk => dataB[0].CLK +clk => dataB[1].CLK +clk => dataB[2].CLK +clk => dataB[3].CLK +clk => dataB[4].CLK +clk => dataB[5].CLK +clk => dataB[6].CLK +clk => dataB[7].CLK +clk => dataB[8].CLK +clk => dataB[9].CLK +clk => dataB[10].CLK +clk => dataB[11].CLK +clk => dataB[12].CLK +clk => dataB[13].CLK +clk => dataB[14].CLK +clk => dataB[15].CLK +clk => dataB[16].CLK +clk => dataB[17].CLK +clk => dataB[18].CLK +clk => dataB[19].CLK +clk => dataB[20].CLK +clk => dataB[21].CLK +clk => dataB[22].CLK +clk => dataB[23].CLK +clk => dataB[24].CLK +clk => dataB[25].CLK +clk => dataB[26].CLK +clk => dataB[27].CLK +clk => dataB[28].CLK +clk => dataB[29].CLK +clk => dataB[30].CLK +clk => dataB[31].CLK +clk => dataA[0].CLK +clk => dataA[1].CLK +clk => dataA[2].CLK +clk => dataA[3].CLK +clk => dataA[4].CLK +clk => dataA[5].CLK +clk => dataA[6].CLK +clk => dataA[7].CLK +clk => dataA[8].CLK +clk => dataA[9].CLK +clk => dataA[10].CLK +clk => dataA[11].CLK +clk => dataA[12].CLK +clk => dataA[13].CLK +clk => dataA[14].CLK +clk => dataA[15].CLK +clk => dataA[16].CLK +clk => dataA[17].CLK +clk => dataA[18].CLK +clk => dataA[19].CLK +clk => dataA[20].CLK +clk => dataA[21].CLK +clk => dataA[22].CLK +clk => dataA[23].CLK +clk => dataA[24].CLK +clk => dataA[25].CLK +clk => dataA[26].CLK +clk => dataA[27].CLK +clk => dataA[28].CLK +clk => dataA[29].CLK +clk => dataA[30].CLK +clk => dataA[31].CLK +clk => alu_out[0].CLK +clk => alu_out[1].CLK +clk => alu_out[2].CLK +clk => alu_out[3].CLK +clk => alu_out[4].CLK +clk => alu_out[5].CLK +clk => alu_out[6].CLK +clk => alu_out[7].CLK +clk => alu_out[8].CLK +clk => alu_out[9].CLK +clk => alu_out[10].CLK +clk => alu_out[11].CLK +clk => alu_out[12].CLK +clk => alu_out[13].CLK +clk => alu_out[14].CLK +clk => alu_out[15].CLK +clk => alu_out[16].CLK +clk => alu_out[17].CLK +clk => alu_out[18].CLK +clk => alu_out[19].CLK +clk => alu_out[20].CLK +clk => alu_out[21].CLK +clk => alu_out[22].CLK +clk => alu_out[23].CLK +clk => alu_out[24].CLK +clk => alu_out[25].CLK +clk => alu_out[26].CLK +clk => alu_out[27].CLK +clk => alu_out[28].CLK +clk => alu_out[29].CLK +clk => alu_out[30].CLK +clk => alu_out[31].CLK +clk => data[0].CLK +clk => data[1].CLK +clk => data[2].CLK +clk => data[3].CLK +clk => data[4].CLK +clk => data[5].CLK +clk => data[6].CLK +clk => data[7].CLK +clk => data[8].CLK +clk => data[9].CLK +clk => data[10].CLK +clk => data[11].CLK +clk => data[12].CLK +clk => data[13].CLK +clk => data[14].CLK +clk => data[15].CLK +clk => data[16].CLK +clk => data[17].CLK +clk => data[18].CLK +clk => data[19].CLK +clk => data[20].CLK +clk => data[21].CLK +clk => data[22].CLK +clk => data[23].CLK +clk => data[24].CLK +clk => data[25].CLK +clk => data[26].CLK +clk => data[27].CLK +clk => data[28].CLK +clk => data[29].CLK +clk => data[30].CLK +clk => data[31].CLK +clk => instruction[0].CLK +clk => instruction[1].CLK +clk => instruction[2].CLK +clk => instruction[3].CLK +clk => instruction[4].CLK +clk => instruction[5].CLK +clk => instruction[6].CLK +clk => instruction[7].CLK +clk => instruction[8].CLK +clk => instruction[9].CLK +clk => instruction[10].CLK +clk => instruction[11].CLK +clk => instruction[12].CLK +clk => instruction[13].CLK +clk => instruction[14].CLK +clk => instruction[15].CLK +clk => instruction[16].CLK +clk => instruction[17].CLK +clk => instruction[18].CLK +clk => instruction[19].CLK +clk => instruction[20].CLK +clk => instruction[21].CLK +clk => instruction[22].CLK +clk => instruction[23].CLK +clk => instruction[24].CLK +clk => instruction[25].CLK +clk => instruction[26].CLK +clk => instruction[27].CLK +clk => instruction[28].CLK +clk => instruction[29].CLK +clk => instruction[30].CLK +clk => instruction[31].CLK +reset => ControlFSM:control_fsm.reset +reset => fetch:fetch.reset +reset => registerFile:RegFile.reset +memory__address[0] <= memory__address[0].DB_MAX_OUTPUT_PORT_TYPE +memory__address[1] <= memory__address[1].DB_MAX_OUTPUT_PORT_TYPE +memory__address[2] <= memory__address[2].DB_MAX_OUTPUT_PORT_TYPE +memory__address[3] <= memory__address[3].DB_MAX_OUTPUT_PORT_TYPE +memory__address[4] <= memory__address[4].DB_MAX_OUTPUT_PORT_TYPE +memory__address[5] <= memory__address[5].DB_MAX_OUTPUT_PORT_TYPE +memory__address[6] <= memory__address[6].DB_MAX_OUTPUT_PORT_TYPE +memory__address[7] <= memory__address[7].DB_MAX_OUTPUT_PORT_TYPE +memory__address[8] <= memory__address[8].DB_MAX_OUTPUT_PORT_TYPE +memory__address[9] <= memory__address[9].DB_MAX_OUTPUT_PORT_TYPE +memory__address[10] <= memory__address[10].DB_MAX_OUTPUT_PORT_TYPE +memory__address[11] <= memory__address[11].DB_MAX_OUTPUT_PORT_TYPE +memory__address[12] <= memory__address[12].DB_MAX_OUTPUT_PORT_TYPE +memory__address[13] <= memory__address[13].DB_MAX_OUTPUT_PORT_TYPE +memory__address[14] <= memory__address[14].DB_MAX_OUTPUT_PORT_TYPE +memory__address[15] <= memory__address[15].DB_MAX_OUTPUT_PORT_TYPE +memory__address[16] <= memory__address[16].DB_MAX_OUTPUT_PORT_TYPE +memory__address[17] <= memory__address[17].DB_MAX_OUTPUT_PORT_TYPE +memory__address[18] <= memory__address[18].DB_MAX_OUTPUT_PORT_TYPE +memory__address[19] <= memory__address[19].DB_MAX_OUTPUT_PORT_TYPE +memory__address[20] <= memory__address[20].DB_MAX_OUTPUT_PORT_TYPE +memory__address[21] <= memory__address[21].DB_MAX_OUTPUT_PORT_TYPE +memory__address[22] <= memory__address[22].DB_MAX_OUTPUT_PORT_TYPE +memory__address[23] <= memory__address[23].DB_MAX_OUTPUT_PORT_TYPE +memory__address[24] <= memory__address[24].DB_MAX_OUTPUT_PORT_TYPE +memory__address[25] <= memory__address[25].DB_MAX_OUTPUT_PORT_TYPE +memory__address[26] <= memory__address[26].DB_MAX_OUTPUT_PORT_TYPE +memory__address[27] <= memory__address[27].DB_MAX_OUTPUT_PORT_TYPE +memory__address[28] <= memory__address[28].DB_MAX_OUTPUT_PORT_TYPE +memory__address[29] <= memory__address[29].DB_MAX_OUTPUT_PORT_TYPE +memory__address[30] <= memory__address[30].DB_MAX_OUTPUT_PORT_TYPE +memory__address[31] <= memory__address[31].DB_MAX_OUTPUT_PORT_TYPE +memory__write_data[0] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[1] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[2] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[3] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[4] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[5] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[6] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[7] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[8] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[9] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[10] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[11] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[12] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[13] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[14] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[15] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[16] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[17] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[18] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[19] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[20] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[21] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[22] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[23] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[24] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[25] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[26] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[27] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[28] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[29] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[30] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_data[31] <= MemoryLoader:MemLoad.__tmp_MemData +memory__write_enable[0] <= ControlFSM:control_fsm.MemWrite[0] +memory__write_enable[1] <= ControlFSM:control_fsm.MemWrite[1] +memory__write_enable[2] <= ControlFSM:control_fsm.MemWrite[2] +memory__write_enable[3] <= ControlFSM:control_fsm.MemWrite[3] +memory__read_data[0] => memory__read_data[0].IN1 +memory__read_data[1] => memory__read_data[1].IN1 +memory__read_data[2] => memory__read_data[2].IN1 +memory__read_data[3] => memory__read_data[3].IN1 +memory__read_data[4] => memory__read_data[4].IN1 +memory__read_data[5] => memory__read_data[5].IN1 +memory__read_data[6] => memory__read_data[6].IN1 +memory__read_data[7] => memory__read_data[7].IN1 +memory__read_data[8] => memory__read_data[8].IN1 +memory__read_data[9] => memory__read_data[9].IN1 +memory__read_data[10] => memory__read_data[10].IN1 +memory__read_data[11] => memory__read_data[11].IN1 +memory__read_data[12] => memory__read_data[12].IN1 +memory__read_data[13] => memory__read_data[13].IN1 +memory__read_data[14] => memory__read_data[14].IN1 +memory__read_data[15] => memory__read_data[15].IN1 +memory__read_data[16] => memory__read_data[16].IN1 +memory__read_data[17] => memory__read_data[17].IN1 +memory__read_data[18] => memory__read_data[18].IN1 +memory__read_data[19] => memory__read_data[19].IN1 +memory__read_data[20] => memory__read_data[20].IN1 +memory__read_data[21] => memory__read_data[21].IN1 +memory__read_data[22] => memory__read_data[22].IN1 +memory__read_data[23] => memory__read_data[23].IN1 +memory__read_data[24] => memory__read_data[24].IN1 +memory__read_data[25] => memory__read_data[25].IN1 +memory__read_data[26] => memory__read_data[26].IN1 +memory__read_data[27] => memory__read_data[27].IN1 +memory__read_data[28] => memory__read_data[28].IN1 +memory__read_data[29] => memory__read_data[29].IN1 +memory__read_data[30] => memory__read_data[30].IN1 +memory__read_data[31] => memory__read_data[31].IN1 +dbg_regs[31][0] <= registerFile:RegFile.dbg_regs[31][0] +dbg_regs[31][1] <= registerFile:RegFile.dbg_regs[31][1] +dbg_regs[31][2] <= registerFile:RegFile.dbg_regs[31][2] +dbg_regs[31][3] <= registerFile:RegFile.dbg_regs[31][3] +dbg_regs[31][4] <= registerFile:RegFile.dbg_regs[31][4] +dbg_regs[31][5] <= registerFile:RegFile.dbg_regs[31][5] +dbg_regs[31][6] <= registerFile:RegFile.dbg_regs[31][6] +dbg_regs[31][7] <= registerFile:RegFile.dbg_regs[31][7] +dbg_regs[31][8] <= registerFile:RegFile.dbg_regs[31][8] +dbg_regs[31][9] <= registerFile:RegFile.dbg_regs[31][9] +dbg_regs[31][10] <= registerFile:RegFile.dbg_regs[31][10] +dbg_regs[31][11] <= registerFile:RegFile.dbg_regs[31][11] +dbg_regs[31][12] <= registerFile:RegFile.dbg_regs[31][12] +dbg_regs[31][13] <= registerFile:RegFile.dbg_regs[31][13] +dbg_regs[31][14] <= registerFile:RegFile.dbg_regs[31][14] +dbg_regs[31][15] <= registerFile:RegFile.dbg_regs[31][15] +dbg_regs[31][16] <= registerFile:RegFile.dbg_regs[31][16] +dbg_regs[31][17] <= registerFile:RegFile.dbg_regs[31][17] +dbg_regs[31][18] <= registerFile:RegFile.dbg_regs[31][18] +dbg_regs[31][19] <= registerFile:RegFile.dbg_regs[31][19] +dbg_regs[31][20] <= registerFile:RegFile.dbg_regs[31][20] +dbg_regs[31][21] <= registerFile:RegFile.dbg_regs[31][21] +dbg_regs[31][22] <= registerFile:RegFile.dbg_regs[31][22] +dbg_regs[31][23] <= registerFile:RegFile.dbg_regs[31][23] +dbg_regs[31][24] <= registerFile:RegFile.dbg_regs[31][24] +dbg_regs[31][25] <= registerFile:RegFile.dbg_regs[31][25] +dbg_regs[31][26] <= registerFile:RegFile.dbg_regs[31][26] +dbg_regs[31][27] <= registerFile:RegFile.dbg_regs[31][27] +dbg_regs[31][28] <= registerFile:RegFile.dbg_regs[31][28] +dbg_regs[31][29] <= registerFile:RegFile.dbg_regs[31][29] +dbg_regs[31][30] <= registerFile:RegFile.dbg_regs[31][30] +dbg_regs[31][31] <= registerFile:RegFile.dbg_regs[31][31] +dbg_regs[30][0] <= registerFile:RegFile.dbg_regs[30][0] +dbg_regs[30][1] <= registerFile:RegFile.dbg_regs[30][1] +dbg_regs[30][2] <= registerFile:RegFile.dbg_regs[30][2] +dbg_regs[30][3] <= registerFile:RegFile.dbg_regs[30][3] +dbg_regs[30][4] <= registerFile:RegFile.dbg_regs[30][4] +dbg_regs[30][5] <= registerFile:RegFile.dbg_regs[30][5] +dbg_regs[30][6] <= registerFile:RegFile.dbg_regs[30][6] +dbg_regs[30][7] <= registerFile:RegFile.dbg_regs[30][7] +dbg_regs[30][8] <= registerFile:RegFile.dbg_regs[30][8] +dbg_regs[30][9] <= registerFile:RegFile.dbg_regs[30][9] +dbg_regs[30][10] <= registerFile:RegFile.dbg_regs[30][10] +dbg_regs[30][11] <= registerFile:RegFile.dbg_regs[30][11] +dbg_regs[30][12] <= registerFile:RegFile.dbg_regs[30][12] +dbg_regs[30][13] <= registerFile:RegFile.dbg_regs[30][13] +dbg_regs[30][14] <= registerFile:RegFile.dbg_regs[30][14] +dbg_regs[30][15] <= registerFile:RegFile.dbg_regs[30][15] +dbg_regs[30][16] <= registerFile:RegFile.dbg_regs[30][16] +dbg_regs[30][17] <= registerFile:RegFile.dbg_regs[30][17] +dbg_regs[30][18] <= registerFile:RegFile.dbg_regs[30][18] +dbg_regs[30][19] <= registerFile:RegFile.dbg_regs[30][19] +dbg_regs[30][20] <= registerFile:RegFile.dbg_regs[30][20] +dbg_regs[30][21] <= registerFile:RegFile.dbg_regs[30][21] +dbg_regs[30][22] <= registerFile:RegFile.dbg_regs[30][22] +dbg_regs[30][23] <= registerFile:RegFile.dbg_regs[30][23] +dbg_regs[30][24] <= registerFile:RegFile.dbg_regs[30][24] +dbg_regs[30][25] <= registerFile:RegFile.dbg_regs[30][25] +dbg_regs[30][26] <= registerFile:RegFile.dbg_regs[30][26] +dbg_regs[30][27] <= registerFile:RegFile.dbg_regs[30][27] +dbg_regs[30][28] <= registerFile:RegFile.dbg_regs[30][28] +dbg_regs[30][29] <= registerFile:RegFile.dbg_regs[30][29] +dbg_regs[30][30] <= registerFile:RegFile.dbg_regs[30][30] +dbg_regs[30][31] <= registerFile:RegFile.dbg_regs[30][31] +dbg_regs[29][0] <= registerFile:RegFile.dbg_regs[29][0] +dbg_regs[29][1] <= registerFile:RegFile.dbg_regs[29][1] +dbg_regs[29][2] <= registerFile:RegFile.dbg_regs[29][2] +dbg_regs[29][3] <= registerFile:RegFile.dbg_regs[29][3] +dbg_regs[29][4] <= registerFile:RegFile.dbg_regs[29][4] +dbg_regs[29][5] <= registerFile:RegFile.dbg_regs[29][5] +dbg_regs[29][6] <= registerFile:RegFile.dbg_regs[29][6] +dbg_regs[29][7] <= registerFile:RegFile.dbg_regs[29][7] +dbg_regs[29][8] <= registerFile:RegFile.dbg_regs[29][8] +dbg_regs[29][9] <= registerFile:RegFile.dbg_regs[29][9] +dbg_regs[29][10] <= registerFile:RegFile.dbg_regs[29][10] +dbg_regs[29][11] <= registerFile:RegFile.dbg_regs[29][11] +dbg_regs[29][12] <= registerFile:RegFile.dbg_regs[29][12] +dbg_regs[29][13] <= registerFile:RegFile.dbg_regs[29][13] +dbg_regs[29][14] <= registerFile:RegFile.dbg_regs[29][14] +dbg_regs[29][15] <= registerFile:RegFile.dbg_regs[29][15] +dbg_regs[29][16] <= registerFile:RegFile.dbg_regs[29][16] +dbg_regs[29][17] <= registerFile:RegFile.dbg_regs[29][17] +dbg_regs[29][18] <= registerFile:RegFile.dbg_regs[29][18] +dbg_regs[29][19] <= registerFile:RegFile.dbg_regs[29][19] +dbg_regs[29][20] <= registerFile:RegFile.dbg_regs[29][20] +dbg_regs[29][21] <= registerFile:RegFile.dbg_regs[29][21] +dbg_regs[29][22] <= registerFile:RegFile.dbg_regs[29][22] +dbg_regs[29][23] <= registerFile:RegFile.dbg_regs[29][23] +dbg_regs[29][24] <= registerFile:RegFile.dbg_regs[29][24] +dbg_regs[29][25] <= registerFile:RegFile.dbg_regs[29][25] +dbg_regs[29][26] <= registerFile:RegFile.dbg_regs[29][26] +dbg_regs[29][27] <= registerFile:RegFile.dbg_regs[29][27] +dbg_regs[29][28] <= registerFile:RegFile.dbg_regs[29][28] +dbg_regs[29][29] <= registerFile:RegFile.dbg_regs[29][29] +dbg_regs[29][30] <= registerFile:RegFile.dbg_regs[29][30] +dbg_regs[29][31] <= registerFile:RegFile.dbg_regs[29][31] +dbg_regs[28][0] <= registerFile:RegFile.dbg_regs[28][0] +dbg_regs[28][1] <= registerFile:RegFile.dbg_regs[28][1] +dbg_regs[28][2] <= registerFile:RegFile.dbg_regs[28][2] +dbg_regs[28][3] <= registerFile:RegFile.dbg_regs[28][3] +dbg_regs[28][4] <= registerFile:RegFile.dbg_regs[28][4] +dbg_regs[28][5] <= registerFile:RegFile.dbg_regs[28][5] +dbg_regs[28][6] <= registerFile:RegFile.dbg_regs[28][6] +dbg_regs[28][7] <= registerFile:RegFile.dbg_regs[28][7] +dbg_regs[28][8] <= registerFile:RegFile.dbg_regs[28][8] +dbg_regs[28][9] <= registerFile:RegFile.dbg_regs[28][9] +dbg_regs[28][10] <= registerFile:RegFile.dbg_regs[28][10] +dbg_regs[28][11] <= registerFile:RegFile.dbg_regs[28][11] +dbg_regs[28][12] <= registerFile:RegFile.dbg_regs[28][12] +dbg_regs[28][13] <= registerFile:RegFile.dbg_regs[28][13] +dbg_regs[28][14] <= registerFile:RegFile.dbg_regs[28][14] +dbg_regs[28][15] <= registerFile:RegFile.dbg_regs[28][15] +dbg_regs[28][16] <= registerFile:RegFile.dbg_regs[28][16] +dbg_regs[28][17] <= registerFile:RegFile.dbg_regs[28][17] +dbg_regs[28][18] <= registerFile:RegFile.dbg_regs[28][18] +dbg_regs[28][19] <= registerFile:RegFile.dbg_regs[28][19] +dbg_regs[28][20] <= registerFile:RegFile.dbg_regs[28][20] +dbg_regs[28][21] <= registerFile:RegFile.dbg_regs[28][21] +dbg_regs[28][22] <= registerFile:RegFile.dbg_regs[28][22] +dbg_regs[28][23] <= registerFile:RegFile.dbg_regs[28][23] +dbg_regs[28][24] <= registerFile:RegFile.dbg_regs[28][24] +dbg_regs[28][25] <= registerFile:RegFile.dbg_regs[28][25] +dbg_regs[28][26] <= registerFile:RegFile.dbg_regs[28][26] +dbg_regs[28][27] <= registerFile:RegFile.dbg_regs[28][27] +dbg_regs[28][28] <= registerFile:RegFile.dbg_regs[28][28] +dbg_regs[28][29] <= registerFile:RegFile.dbg_regs[28][29] +dbg_regs[28][30] <= registerFile:RegFile.dbg_regs[28][30] +dbg_regs[28][31] <= registerFile:RegFile.dbg_regs[28][31] +dbg_regs[27][0] <= registerFile:RegFile.dbg_regs[27][0] +dbg_regs[27][1] <= registerFile:RegFile.dbg_regs[27][1] +dbg_regs[27][2] <= registerFile:RegFile.dbg_regs[27][2] +dbg_regs[27][3] <= registerFile:RegFile.dbg_regs[27][3] +dbg_regs[27][4] <= registerFile:RegFile.dbg_regs[27][4] +dbg_regs[27][5] <= registerFile:RegFile.dbg_regs[27][5] +dbg_regs[27][6] <= registerFile:RegFile.dbg_regs[27][6] +dbg_regs[27][7] <= registerFile:RegFile.dbg_regs[27][7] +dbg_regs[27][8] <= registerFile:RegFile.dbg_regs[27][8] +dbg_regs[27][9] <= registerFile:RegFile.dbg_regs[27][9] +dbg_regs[27][10] <= registerFile:RegFile.dbg_regs[27][10] +dbg_regs[27][11] <= registerFile:RegFile.dbg_regs[27][11] +dbg_regs[27][12] <= registerFile:RegFile.dbg_regs[27][12] +dbg_regs[27][13] <= registerFile:RegFile.dbg_regs[27][13] +dbg_regs[27][14] <= registerFile:RegFile.dbg_regs[27][14] +dbg_regs[27][15] <= registerFile:RegFile.dbg_regs[27][15] +dbg_regs[27][16] <= registerFile:RegFile.dbg_regs[27][16] +dbg_regs[27][17] <= registerFile:RegFile.dbg_regs[27][17] +dbg_regs[27][18] <= registerFile:RegFile.dbg_regs[27][18] +dbg_regs[27][19] <= registerFile:RegFile.dbg_regs[27][19] +dbg_regs[27][20] <= registerFile:RegFile.dbg_regs[27][20] +dbg_regs[27][21] <= registerFile:RegFile.dbg_regs[27][21] +dbg_regs[27][22] <= registerFile:RegFile.dbg_regs[27][22] +dbg_regs[27][23] <= registerFile:RegFile.dbg_regs[27][23] +dbg_regs[27][24] <= registerFile:RegFile.dbg_regs[27][24] +dbg_regs[27][25] <= registerFile:RegFile.dbg_regs[27][25] +dbg_regs[27][26] <= registerFile:RegFile.dbg_regs[27][26] +dbg_regs[27][27] <= registerFile:RegFile.dbg_regs[27][27] +dbg_regs[27][28] <= registerFile:RegFile.dbg_regs[27][28] +dbg_regs[27][29] <= registerFile:RegFile.dbg_regs[27][29] +dbg_regs[27][30] <= registerFile:RegFile.dbg_regs[27][30] +dbg_regs[27][31] <= registerFile:RegFile.dbg_regs[27][31] +dbg_regs[26][0] <= registerFile:RegFile.dbg_regs[26][0] +dbg_regs[26][1] <= registerFile:RegFile.dbg_regs[26][1] +dbg_regs[26][2] <= registerFile:RegFile.dbg_regs[26][2] +dbg_regs[26][3] <= registerFile:RegFile.dbg_regs[26][3] +dbg_regs[26][4] <= registerFile:RegFile.dbg_regs[26][4] +dbg_regs[26][5] <= registerFile:RegFile.dbg_regs[26][5] +dbg_regs[26][6] <= registerFile:RegFile.dbg_regs[26][6] +dbg_regs[26][7] <= registerFile:RegFile.dbg_regs[26][7] +dbg_regs[26][8] <= registerFile:RegFile.dbg_regs[26][8] +dbg_regs[26][9] <= registerFile:RegFile.dbg_regs[26][9] +dbg_regs[26][10] <= registerFile:RegFile.dbg_regs[26][10] +dbg_regs[26][11] <= registerFile:RegFile.dbg_regs[26][11] +dbg_regs[26][12] <= registerFile:RegFile.dbg_regs[26][12] +dbg_regs[26][13] <= registerFile:RegFile.dbg_regs[26][13] +dbg_regs[26][14] <= registerFile:RegFile.dbg_regs[26][14] +dbg_regs[26][15] <= registerFile:RegFile.dbg_regs[26][15] +dbg_regs[26][16] <= registerFile:RegFile.dbg_regs[26][16] +dbg_regs[26][17] <= registerFile:RegFile.dbg_regs[26][17] +dbg_regs[26][18] <= registerFile:RegFile.dbg_regs[26][18] +dbg_regs[26][19] <= registerFile:RegFile.dbg_regs[26][19] +dbg_regs[26][20] <= registerFile:RegFile.dbg_regs[26][20] +dbg_regs[26][21] <= registerFile:RegFile.dbg_regs[26][21] +dbg_regs[26][22] <= registerFile:RegFile.dbg_regs[26][22] +dbg_regs[26][23] <= registerFile:RegFile.dbg_regs[26][23] +dbg_regs[26][24] <= registerFile:RegFile.dbg_regs[26][24] +dbg_regs[26][25] <= registerFile:RegFile.dbg_regs[26][25] +dbg_regs[26][26] <= registerFile:RegFile.dbg_regs[26][26] +dbg_regs[26][27] <= registerFile:RegFile.dbg_regs[26][27] +dbg_regs[26][28] <= registerFile:RegFile.dbg_regs[26][28] +dbg_regs[26][29] <= registerFile:RegFile.dbg_regs[26][29] +dbg_regs[26][30] <= registerFile:RegFile.dbg_regs[26][30] +dbg_regs[26][31] <= registerFile:RegFile.dbg_regs[26][31] +dbg_regs[25][0] <= registerFile:RegFile.dbg_regs[25][0] +dbg_regs[25][1] <= registerFile:RegFile.dbg_regs[25][1] +dbg_regs[25][2] <= registerFile:RegFile.dbg_regs[25][2] +dbg_regs[25][3] <= registerFile:RegFile.dbg_regs[25][3] +dbg_regs[25][4] <= registerFile:RegFile.dbg_regs[25][4] +dbg_regs[25][5] <= registerFile:RegFile.dbg_regs[25][5] +dbg_regs[25][6] <= registerFile:RegFile.dbg_regs[25][6] +dbg_regs[25][7] <= registerFile:RegFile.dbg_regs[25][7] +dbg_regs[25][8] <= registerFile:RegFile.dbg_regs[25][8] +dbg_regs[25][9] <= registerFile:RegFile.dbg_regs[25][9] +dbg_regs[25][10] <= registerFile:RegFile.dbg_regs[25][10] +dbg_regs[25][11] <= registerFile:RegFile.dbg_regs[25][11] +dbg_regs[25][12] <= registerFile:RegFile.dbg_regs[25][12] +dbg_regs[25][13] <= registerFile:RegFile.dbg_regs[25][13] +dbg_regs[25][14] <= registerFile:RegFile.dbg_regs[25][14] +dbg_regs[25][15] <= registerFile:RegFile.dbg_regs[25][15] +dbg_regs[25][16] <= registerFile:RegFile.dbg_regs[25][16] +dbg_regs[25][17] <= registerFile:RegFile.dbg_regs[25][17] +dbg_regs[25][18] <= registerFile:RegFile.dbg_regs[25][18] +dbg_regs[25][19] <= registerFile:RegFile.dbg_regs[25][19] +dbg_regs[25][20] <= registerFile:RegFile.dbg_regs[25][20] +dbg_regs[25][21] <= registerFile:RegFile.dbg_regs[25][21] +dbg_regs[25][22] <= registerFile:RegFile.dbg_regs[25][22] +dbg_regs[25][23] <= registerFile:RegFile.dbg_regs[25][23] +dbg_regs[25][24] <= registerFile:RegFile.dbg_regs[25][24] +dbg_regs[25][25] <= registerFile:RegFile.dbg_regs[25][25] +dbg_regs[25][26] <= registerFile:RegFile.dbg_regs[25][26] +dbg_regs[25][27] <= registerFile:RegFile.dbg_regs[25][27] +dbg_regs[25][28] <= registerFile:RegFile.dbg_regs[25][28] +dbg_regs[25][29] <= registerFile:RegFile.dbg_regs[25][29] +dbg_regs[25][30] <= registerFile:RegFile.dbg_regs[25][30] +dbg_regs[25][31] <= registerFile:RegFile.dbg_regs[25][31] +dbg_regs[24][0] <= registerFile:RegFile.dbg_regs[24][0] +dbg_regs[24][1] <= registerFile:RegFile.dbg_regs[24][1] +dbg_regs[24][2] <= registerFile:RegFile.dbg_regs[24][2] +dbg_regs[24][3] <= registerFile:RegFile.dbg_regs[24][3] +dbg_regs[24][4] <= registerFile:RegFile.dbg_regs[24][4] +dbg_regs[24][5] <= registerFile:RegFile.dbg_regs[24][5] +dbg_regs[24][6] <= registerFile:RegFile.dbg_regs[24][6] +dbg_regs[24][7] <= registerFile:RegFile.dbg_regs[24][7] +dbg_regs[24][8] <= registerFile:RegFile.dbg_regs[24][8] +dbg_regs[24][9] <= registerFile:RegFile.dbg_regs[24][9] +dbg_regs[24][10] <= registerFile:RegFile.dbg_regs[24][10] +dbg_regs[24][11] <= registerFile:RegFile.dbg_regs[24][11] +dbg_regs[24][12] <= registerFile:RegFile.dbg_regs[24][12] +dbg_regs[24][13] <= registerFile:RegFile.dbg_regs[24][13] +dbg_regs[24][14] <= registerFile:RegFile.dbg_regs[24][14] +dbg_regs[24][15] <= registerFile:RegFile.dbg_regs[24][15] +dbg_regs[24][16] <= registerFile:RegFile.dbg_regs[24][16] +dbg_regs[24][17] <= registerFile:RegFile.dbg_regs[24][17] +dbg_regs[24][18] <= registerFile:RegFile.dbg_regs[24][18] +dbg_regs[24][19] <= registerFile:RegFile.dbg_regs[24][19] +dbg_regs[24][20] <= registerFile:RegFile.dbg_regs[24][20] +dbg_regs[24][21] <= registerFile:RegFile.dbg_regs[24][21] +dbg_regs[24][22] <= registerFile:RegFile.dbg_regs[24][22] +dbg_regs[24][23] <= registerFile:RegFile.dbg_regs[24][23] +dbg_regs[24][24] <= registerFile:RegFile.dbg_regs[24][24] +dbg_regs[24][25] <= registerFile:RegFile.dbg_regs[24][25] +dbg_regs[24][26] <= registerFile:RegFile.dbg_regs[24][26] +dbg_regs[24][27] <= registerFile:RegFile.dbg_regs[24][27] +dbg_regs[24][28] <= registerFile:RegFile.dbg_regs[24][28] +dbg_regs[24][29] <= registerFile:RegFile.dbg_regs[24][29] +dbg_regs[24][30] <= registerFile:RegFile.dbg_regs[24][30] +dbg_regs[24][31] <= registerFile:RegFile.dbg_regs[24][31] +dbg_regs[23][0] <= registerFile:RegFile.dbg_regs[23][0] +dbg_regs[23][1] <= registerFile:RegFile.dbg_regs[23][1] +dbg_regs[23][2] <= registerFile:RegFile.dbg_regs[23][2] +dbg_regs[23][3] <= registerFile:RegFile.dbg_regs[23][3] +dbg_regs[23][4] <= registerFile:RegFile.dbg_regs[23][4] +dbg_regs[23][5] <= registerFile:RegFile.dbg_regs[23][5] +dbg_regs[23][6] <= registerFile:RegFile.dbg_regs[23][6] +dbg_regs[23][7] <= registerFile:RegFile.dbg_regs[23][7] +dbg_regs[23][8] <= registerFile:RegFile.dbg_regs[23][8] +dbg_regs[23][9] <= registerFile:RegFile.dbg_regs[23][9] +dbg_regs[23][10] <= registerFile:RegFile.dbg_regs[23][10] +dbg_regs[23][11] <= registerFile:RegFile.dbg_regs[23][11] +dbg_regs[23][12] <= registerFile:RegFile.dbg_regs[23][12] +dbg_regs[23][13] <= registerFile:RegFile.dbg_regs[23][13] +dbg_regs[23][14] <= registerFile:RegFile.dbg_regs[23][14] +dbg_regs[23][15] <= registerFile:RegFile.dbg_regs[23][15] +dbg_regs[23][16] <= registerFile:RegFile.dbg_regs[23][16] +dbg_regs[23][17] <= registerFile:RegFile.dbg_regs[23][17] +dbg_regs[23][18] <= registerFile:RegFile.dbg_regs[23][18] +dbg_regs[23][19] <= registerFile:RegFile.dbg_regs[23][19] +dbg_regs[23][20] <= registerFile:RegFile.dbg_regs[23][20] +dbg_regs[23][21] <= registerFile:RegFile.dbg_regs[23][21] +dbg_regs[23][22] <= registerFile:RegFile.dbg_regs[23][22] +dbg_regs[23][23] <= registerFile:RegFile.dbg_regs[23][23] +dbg_regs[23][24] <= registerFile:RegFile.dbg_regs[23][24] +dbg_regs[23][25] <= registerFile:RegFile.dbg_regs[23][25] +dbg_regs[23][26] <= registerFile:RegFile.dbg_regs[23][26] +dbg_regs[23][27] <= registerFile:RegFile.dbg_regs[23][27] +dbg_regs[23][28] <= registerFile:RegFile.dbg_regs[23][28] +dbg_regs[23][29] <= registerFile:RegFile.dbg_regs[23][29] +dbg_regs[23][30] <= registerFile:RegFile.dbg_regs[23][30] +dbg_regs[23][31] <= registerFile:RegFile.dbg_regs[23][31] +dbg_regs[22][0] <= registerFile:RegFile.dbg_regs[22][0] +dbg_regs[22][1] <= registerFile:RegFile.dbg_regs[22][1] +dbg_regs[22][2] <= registerFile:RegFile.dbg_regs[22][2] +dbg_regs[22][3] <= registerFile:RegFile.dbg_regs[22][3] +dbg_regs[22][4] <= registerFile:RegFile.dbg_regs[22][4] +dbg_regs[22][5] <= registerFile:RegFile.dbg_regs[22][5] +dbg_regs[22][6] <= registerFile:RegFile.dbg_regs[22][6] +dbg_regs[22][7] <= registerFile:RegFile.dbg_regs[22][7] +dbg_regs[22][8] <= registerFile:RegFile.dbg_regs[22][8] +dbg_regs[22][9] <= registerFile:RegFile.dbg_regs[22][9] +dbg_regs[22][10] <= registerFile:RegFile.dbg_regs[22][10] +dbg_regs[22][11] <= registerFile:RegFile.dbg_regs[22][11] +dbg_regs[22][12] <= registerFile:RegFile.dbg_regs[22][12] +dbg_regs[22][13] <= registerFile:RegFile.dbg_regs[22][13] +dbg_regs[22][14] <= registerFile:RegFile.dbg_regs[22][14] +dbg_regs[22][15] <= registerFile:RegFile.dbg_regs[22][15] +dbg_regs[22][16] <= registerFile:RegFile.dbg_regs[22][16] +dbg_regs[22][17] <= registerFile:RegFile.dbg_regs[22][17] +dbg_regs[22][18] <= registerFile:RegFile.dbg_regs[22][18] +dbg_regs[22][19] <= registerFile:RegFile.dbg_regs[22][19] +dbg_regs[22][20] <= registerFile:RegFile.dbg_regs[22][20] +dbg_regs[22][21] <= registerFile:RegFile.dbg_regs[22][21] +dbg_regs[22][22] <= registerFile:RegFile.dbg_regs[22][22] +dbg_regs[22][23] <= registerFile:RegFile.dbg_regs[22][23] +dbg_regs[22][24] <= registerFile:RegFile.dbg_regs[22][24] +dbg_regs[22][25] <= registerFile:RegFile.dbg_regs[22][25] +dbg_regs[22][26] <= registerFile:RegFile.dbg_regs[22][26] +dbg_regs[22][27] <= registerFile:RegFile.dbg_regs[22][27] +dbg_regs[22][28] <= registerFile:RegFile.dbg_regs[22][28] +dbg_regs[22][29] <= registerFile:RegFile.dbg_regs[22][29] +dbg_regs[22][30] <= registerFile:RegFile.dbg_regs[22][30] +dbg_regs[22][31] <= registerFile:RegFile.dbg_regs[22][31] +dbg_regs[21][0] <= registerFile:RegFile.dbg_regs[21][0] +dbg_regs[21][1] <= registerFile:RegFile.dbg_regs[21][1] +dbg_regs[21][2] <= registerFile:RegFile.dbg_regs[21][2] +dbg_regs[21][3] <= registerFile:RegFile.dbg_regs[21][3] +dbg_regs[21][4] <= registerFile:RegFile.dbg_regs[21][4] +dbg_regs[21][5] <= registerFile:RegFile.dbg_regs[21][5] +dbg_regs[21][6] <= registerFile:RegFile.dbg_regs[21][6] +dbg_regs[21][7] <= registerFile:RegFile.dbg_regs[21][7] +dbg_regs[21][8] <= registerFile:RegFile.dbg_regs[21][8] +dbg_regs[21][9] <= registerFile:RegFile.dbg_regs[21][9] +dbg_regs[21][10] <= registerFile:RegFile.dbg_regs[21][10] +dbg_regs[21][11] <= registerFile:RegFile.dbg_regs[21][11] +dbg_regs[21][12] <= registerFile:RegFile.dbg_regs[21][12] +dbg_regs[21][13] <= registerFile:RegFile.dbg_regs[21][13] +dbg_regs[21][14] <= registerFile:RegFile.dbg_regs[21][14] +dbg_regs[21][15] <= registerFile:RegFile.dbg_regs[21][15] +dbg_regs[21][16] <= registerFile:RegFile.dbg_regs[21][16] +dbg_regs[21][17] <= registerFile:RegFile.dbg_regs[21][17] +dbg_regs[21][18] <= registerFile:RegFile.dbg_regs[21][18] +dbg_regs[21][19] <= registerFile:RegFile.dbg_regs[21][19] +dbg_regs[21][20] <= registerFile:RegFile.dbg_regs[21][20] +dbg_regs[21][21] <= registerFile:RegFile.dbg_regs[21][21] +dbg_regs[21][22] <= registerFile:RegFile.dbg_regs[21][22] +dbg_regs[21][23] <= registerFile:RegFile.dbg_regs[21][23] +dbg_regs[21][24] <= registerFile:RegFile.dbg_regs[21][24] +dbg_regs[21][25] <= registerFile:RegFile.dbg_regs[21][25] +dbg_regs[21][26] <= registerFile:RegFile.dbg_regs[21][26] +dbg_regs[21][27] <= registerFile:RegFile.dbg_regs[21][27] +dbg_regs[21][28] <= registerFile:RegFile.dbg_regs[21][28] +dbg_regs[21][29] <= registerFile:RegFile.dbg_regs[21][29] +dbg_regs[21][30] <= registerFile:RegFile.dbg_regs[21][30] +dbg_regs[21][31] <= registerFile:RegFile.dbg_regs[21][31] +dbg_regs[20][0] <= registerFile:RegFile.dbg_regs[20][0] +dbg_regs[20][1] <= registerFile:RegFile.dbg_regs[20][1] +dbg_regs[20][2] <= registerFile:RegFile.dbg_regs[20][2] +dbg_regs[20][3] <= registerFile:RegFile.dbg_regs[20][3] +dbg_regs[20][4] <= registerFile:RegFile.dbg_regs[20][4] +dbg_regs[20][5] <= registerFile:RegFile.dbg_regs[20][5] +dbg_regs[20][6] <= registerFile:RegFile.dbg_regs[20][6] +dbg_regs[20][7] <= registerFile:RegFile.dbg_regs[20][7] +dbg_regs[20][8] <= registerFile:RegFile.dbg_regs[20][8] +dbg_regs[20][9] <= registerFile:RegFile.dbg_regs[20][9] +dbg_regs[20][10] <= registerFile:RegFile.dbg_regs[20][10] +dbg_regs[20][11] <= registerFile:RegFile.dbg_regs[20][11] +dbg_regs[20][12] <= registerFile:RegFile.dbg_regs[20][12] +dbg_regs[20][13] <= registerFile:RegFile.dbg_regs[20][13] +dbg_regs[20][14] <= registerFile:RegFile.dbg_regs[20][14] +dbg_regs[20][15] <= registerFile:RegFile.dbg_regs[20][15] +dbg_regs[20][16] <= registerFile:RegFile.dbg_regs[20][16] +dbg_regs[20][17] <= registerFile:RegFile.dbg_regs[20][17] +dbg_regs[20][18] <= registerFile:RegFile.dbg_regs[20][18] +dbg_regs[20][19] <= registerFile:RegFile.dbg_regs[20][19] +dbg_regs[20][20] <= registerFile:RegFile.dbg_regs[20][20] +dbg_regs[20][21] <= registerFile:RegFile.dbg_regs[20][21] +dbg_regs[20][22] <= registerFile:RegFile.dbg_regs[20][22] +dbg_regs[20][23] <= registerFile:RegFile.dbg_regs[20][23] +dbg_regs[20][24] <= registerFile:RegFile.dbg_regs[20][24] +dbg_regs[20][25] <= registerFile:RegFile.dbg_regs[20][25] +dbg_regs[20][26] <= registerFile:RegFile.dbg_regs[20][26] +dbg_regs[20][27] <= registerFile:RegFile.dbg_regs[20][27] +dbg_regs[20][28] <= registerFile:RegFile.dbg_regs[20][28] +dbg_regs[20][29] <= registerFile:RegFile.dbg_regs[20][29] +dbg_regs[20][30] <= registerFile:RegFile.dbg_regs[20][30] +dbg_regs[20][31] <= registerFile:RegFile.dbg_regs[20][31] +dbg_regs[19][0] <= registerFile:RegFile.dbg_regs[19][0] +dbg_regs[19][1] <= registerFile:RegFile.dbg_regs[19][1] +dbg_regs[19][2] <= registerFile:RegFile.dbg_regs[19][2] +dbg_regs[19][3] <= registerFile:RegFile.dbg_regs[19][3] +dbg_regs[19][4] <= registerFile:RegFile.dbg_regs[19][4] +dbg_regs[19][5] <= registerFile:RegFile.dbg_regs[19][5] +dbg_regs[19][6] <= registerFile:RegFile.dbg_regs[19][6] +dbg_regs[19][7] <= registerFile:RegFile.dbg_regs[19][7] +dbg_regs[19][8] <= registerFile:RegFile.dbg_regs[19][8] +dbg_regs[19][9] <= registerFile:RegFile.dbg_regs[19][9] +dbg_regs[19][10] <= registerFile:RegFile.dbg_regs[19][10] +dbg_regs[19][11] <= registerFile:RegFile.dbg_regs[19][11] +dbg_regs[19][12] <= registerFile:RegFile.dbg_regs[19][12] +dbg_regs[19][13] <= registerFile:RegFile.dbg_regs[19][13] +dbg_regs[19][14] <= registerFile:RegFile.dbg_regs[19][14] +dbg_regs[19][15] <= registerFile:RegFile.dbg_regs[19][15] +dbg_regs[19][16] <= registerFile:RegFile.dbg_regs[19][16] +dbg_regs[19][17] <= registerFile:RegFile.dbg_regs[19][17] +dbg_regs[19][18] <= registerFile:RegFile.dbg_regs[19][18] +dbg_regs[19][19] <= registerFile:RegFile.dbg_regs[19][19] +dbg_regs[19][20] <= registerFile:RegFile.dbg_regs[19][20] +dbg_regs[19][21] <= registerFile:RegFile.dbg_regs[19][21] +dbg_regs[19][22] <= registerFile:RegFile.dbg_regs[19][22] +dbg_regs[19][23] <= registerFile:RegFile.dbg_regs[19][23] +dbg_regs[19][24] <= registerFile:RegFile.dbg_regs[19][24] +dbg_regs[19][25] <= registerFile:RegFile.dbg_regs[19][25] +dbg_regs[19][26] <= registerFile:RegFile.dbg_regs[19][26] +dbg_regs[19][27] <= registerFile:RegFile.dbg_regs[19][27] +dbg_regs[19][28] <= registerFile:RegFile.dbg_regs[19][28] +dbg_regs[19][29] <= registerFile:RegFile.dbg_regs[19][29] +dbg_regs[19][30] <= registerFile:RegFile.dbg_regs[19][30] +dbg_regs[19][31] <= registerFile:RegFile.dbg_regs[19][31] +dbg_regs[18][0] <= registerFile:RegFile.dbg_regs[18][0] +dbg_regs[18][1] <= registerFile:RegFile.dbg_regs[18][1] +dbg_regs[18][2] <= registerFile:RegFile.dbg_regs[18][2] +dbg_regs[18][3] <= registerFile:RegFile.dbg_regs[18][3] +dbg_regs[18][4] <= registerFile:RegFile.dbg_regs[18][4] +dbg_regs[18][5] <= registerFile:RegFile.dbg_regs[18][5] +dbg_regs[18][6] <= registerFile:RegFile.dbg_regs[18][6] +dbg_regs[18][7] <= registerFile:RegFile.dbg_regs[18][7] +dbg_regs[18][8] <= registerFile:RegFile.dbg_regs[18][8] +dbg_regs[18][9] <= registerFile:RegFile.dbg_regs[18][9] +dbg_regs[18][10] <= registerFile:RegFile.dbg_regs[18][10] +dbg_regs[18][11] <= registerFile:RegFile.dbg_regs[18][11] +dbg_regs[18][12] <= registerFile:RegFile.dbg_regs[18][12] +dbg_regs[18][13] <= registerFile:RegFile.dbg_regs[18][13] +dbg_regs[18][14] <= registerFile:RegFile.dbg_regs[18][14] +dbg_regs[18][15] <= registerFile:RegFile.dbg_regs[18][15] +dbg_regs[18][16] <= registerFile:RegFile.dbg_regs[18][16] +dbg_regs[18][17] <= registerFile:RegFile.dbg_regs[18][17] +dbg_regs[18][18] <= registerFile:RegFile.dbg_regs[18][18] +dbg_regs[18][19] <= registerFile:RegFile.dbg_regs[18][19] +dbg_regs[18][20] <= registerFile:RegFile.dbg_regs[18][20] +dbg_regs[18][21] <= registerFile:RegFile.dbg_regs[18][21] +dbg_regs[18][22] <= registerFile:RegFile.dbg_regs[18][22] +dbg_regs[18][23] <= registerFile:RegFile.dbg_regs[18][23] +dbg_regs[18][24] <= registerFile:RegFile.dbg_regs[18][24] +dbg_regs[18][25] <= registerFile:RegFile.dbg_regs[18][25] +dbg_regs[18][26] <= registerFile:RegFile.dbg_regs[18][26] +dbg_regs[18][27] <= registerFile:RegFile.dbg_regs[18][27] +dbg_regs[18][28] <= registerFile:RegFile.dbg_regs[18][28] +dbg_regs[18][29] <= registerFile:RegFile.dbg_regs[18][29] +dbg_regs[18][30] <= registerFile:RegFile.dbg_regs[18][30] +dbg_regs[18][31] <= registerFile:RegFile.dbg_regs[18][31] +dbg_regs[17][0] <= registerFile:RegFile.dbg_regs[17][0] +dbg_regs[17][1] <= registerFile:RegFile.dbg_regs[17][1] +dbg_regs[17][2] <= registerFile:RegFile.dbg_regs[17][2] +dbg_regs[17][3] <= registerFile:RegFile.dbg_regs[17][3] +dbg_regs[17][4] <= registerFile:RegFile.dbg_regs[17][4] +dbg_regs[17][5] <= registerFile:RegFile.dbg_regs[17][5] +dbg_regs[17][6] <= registerFile:RegFile.dbg_regs[17][6] +dbg_regs[17][7] <= registerFile:RegFile.dbg_regs[17][7] +dbg_regs[17][8] <= registerFile:RegFile.dbg_regs[17][8] +dbg_regs[17][9] <= registerFile:RegFile.dbg_regs[17][9] +dbg_regs[17][10] <= registerFile:RegFile.dbg_regs[17][10] +dbg_regs[17][11] <= registerFile:RegFile.dbg_regs[17][11] +dbg_regs[17][12] <= registerFile:RegFile.dbg_regs[17][12] +dbg_regs[17][13] <= registerFile:RegFile.dbg_regs[17][13] +dbg_regs[17][14] <= registerFile:RegFile.dbg_regs[17][14] +dbg_regs[17][15] <= registerFile:RegFile.dbg_regs[17][15] +dbg_regs[17][16] <= registerFile:RegFile.dbg_regs[17][16] +dbg_regs[17][17] <= registerFile:RegFile.dbg_regs[17][17] +dbg_regs[17][18] <= registerFile:RegFile.dbg_regs[17][18] +dbg_regs[17][19] <= registerFile:RegFile.dbg_regs[17][19] +dbg_regs[17][20] <= registerFile:RegFile.dbg_regs[17][20] +dbg_regs[17][21] <= registerFile:RegFile.dbg_regs[17][21] +dbg_regs[17][22] <= registerFile:RegFile.dbg_regs[17][22] +dbg_regs[17][23] <= registerFile:RegFile.dbg_regs[17][23] +dbg_regs[17][24] <= registerFile:RegFile.dbg_regs[17][24] +dbg_regs[17][25] <= registerFile:RegFile.dbg_regs[17][25] +dbg_regs[17][26] <= registerFile:RegFile.dbg_regs[17][26] +dbg_regs[17][27] <= registerFile:RegFile.dbg_regs[17][27] +dbg_regs[17][28] <= registerFile:RegFile.dbg_regs[17][28] +dbg_regs[17][29] <= registerFile:RegFile.dbg_regs[17][29] +dbg_regs[17][30] <= registerFile:RegFile.dbg_regs[17][30] +dbg_regs[17][31] <= registerFile:RegFile.dbg_regs[17][31] +dbg_regs[16][0] <= registerFile:RegFile.dbg_regs[16][0] +dbg_regs[16][1] <= registerFile:RegFile.dbg_regs[16][1] +dbg_regs[16][2] <= registerFile:RegFile.dbg_regs[16][2] +dbg_regs[16][3] <= registerFile:RegFile.dbg_regs[16][3] +dbg_regs[16][4] <= registerFile:RegFile.dbg_regs[16][4] +dbg_regs[16][5] <= registerFile:RegFile.dbg_regs[16][5] +dbg_regs[16][6] <= registerFile:RegFile.dbg_regs[16][6] +dbg_regs[16][7] <= registerFile:RegFile.dbg_regs[16][7] +dbg_regs[16][8] <= registerFile:RegFile.dbg_regs[16][8] +dbg_regs[16][9] <= registerFile:RegFile.dbg_regs[16][9] +dbg_regs[16][10] <= registerFile:RegFile.dbg_regs[16][10] +dbg_regs[16][11] <= registerFile:RegFile.dbg_regs[16][11] +dbg_regs[16][12] <= registerFile:RegFile.dbg_regs[16][12] +dbg_regs[16][13] <= registerFile:RegFile.dbg_regs[16][13] +dbg_regs[16][14] <= registerFile:RegFile.dbg_regs[16][14] +dbg_regs[16][15] <= registerFile:RegFile.dbg_regs[16][15] +dbg_regs[16][16] <= registerFile:RegFile.dbg_regs[16][16] +dbg_regs[16][17] <= registerFile:RegFile.dbg_regs[16][17] +dbg_regs[16][18] <= registerFile:RegFile.dbg_regs[16][18] +dbg_regs[16][19] <= registerFile:RegFile.dbg_regs[16][19] +dbg_regs[16][20] <= registerFile:RegFile.dbg_regs[16][20] +dbg_regs[16][21] <= registerFile:RegFile.dbg_regs[16][21] +dbg_regs[16][22] <= registerFile:RegFile.dbg_regs[16][22] +dbg_regs[16][23] <= registerFile:RegFile.dbg_regs[16][23] +dbg_regs[16][24] <= registerFile:RegFile.dbg_regs[16][24] +dbg_regs[16][25] <= registerFile:RegFile.dbg_regs[16][25] +dbg_regs[16][26] <= registerFile:RegFile.dbg_regs[16][26] +dbg_regs[16][27] <= registerFile:RegFile.dbg_regs[16][27] +dbg_regs[16][28] <= registerFile:RegFile.dbg_regs[16][28] +dbg_regs[16][29] <= registerFile:RegFile.dbg_regs[16][29] +dbg_regs[16][30] <= registerFile:RegFile.dbg_regs[16][30] +dbg_regs[16][31] <= registerFile:RegFile.dbg_regs[16][31] +dbg_regs[15][0] <= registerFile:RegFile.dbg_regs[15][0] +dbg_regs[15][1] <= registerFile:RegFile.dbg_regs[15][1] +dbg_regs[15][2] <= registerFile:RegFile.dbg_regs[15][2] +dbg_regs[15][3] <= registerFile:RegFile.dbg_regs[15][3] +dbg_regs[15][4] <= registerFile:RegFile.dbg_regs[15][4] +dbg_regs[15][5] <= registerFile:RegFile.dbg_regs[15][5] +dbg_regs[15][6] <= registerFile:RegFile.dbg_regs[15][6] +dbg_regs[15][7] <= registerFile:RegFile.dbg_regs[15][7] +dbg_regs[15][8] <= registerFile:RegFile.dbg_regs[15][8] +dbg_regs[15][9] <= registerFile:RegFile.dbg_regs[15][9] +dbg_regs[15][10] <= registerFile:RegFile.dbg_regs[15][10] +dbg_regs[15][11] <= registerFile:RegFile.dbg_regs[15][11] +dbg_regs[15][12] <= registerFile:RegFile.dbg_regs[15][12] +dbg_regs[15][13] <= registerFile:RegFile.dbg_regs[15][13] +dbg_regs[15][14] <= registerFile:RegFile.dbg_regs[15][14] +dbg_regs[15][15] <= registerFile:RegFile.dbg_regs[15][15] +dbg_regs[15][16] <= registerFile:RegFile.dbg_regs[15][16] +dbg_regs[15][17] <= registerFile:RegFile.dbg_regs[15][17] +dbg_regs[15][18] <= registerFile:RegFile.dbg_regs[15][18] +dbg_regs[15][19] <= registerFile:RegFile.dbg_regs[15][19] +dbg_regs[15][20] <= registerFile:RegFile.dbg_regs[15][20] +dbg_regs[15][21] <= registerFile:RegFile.dbg_regs[15][21] +dbg_regs[15][22] <= registerFile:RegFile.dbg_regs[15][22] +dbg_regs[15][23] <= registerFile:RegFile.dbg_regs[15][23] +dbg_regs[15][24] <= registerFile:RegFile.dbg_regs[15][24] +dbg_regs[15][25] <= registerFile:RegFile.dbg_regs[15][25] +dbg_regs[15][26] <= registerFile:RegFile.dbg_regs[15][26] +dbg_regs[15][27] <= registerFile:RegFile.dbg_regs[15][27] +dbg_regs[15][28] <= registerFile:RegFile.dbg_regs[15][28] +dbg_regs[15][29] <= registerFile:RegFile.dbg_regs[15][29] +dbg_regs[15][30] <= registerFile:RegFile.dbg_regs[15][30] +dbg_regs[15][31] <= registerFile:RegFile.dbg_regs[15][31] +dbg_regs[14][0] <= registerFile:RegFile.dbg_regs[14][0] +dbg_regs[14][1] <= registerFile:RegFile.dbg_regs[14][1] +dbg_regs[14][2] <= registerFile:RegFile.dbg_regs[14][2] +dbg_regs[14][3] <= registerFile:RegFile.dbg_regs[14][3] +dbg_regs[14][4] <= registerFile:RegFile.dbg_regs[14][4] +dbg_regs[14][5] <= registerFile:RegFile.dbg_regs[14][5] +dbg_regs[14][6] <= registerFile:RegFile.dbg_regs[14][6] +dbg_regs[14][7] <= registerFile:RegFile.dbg_regs[14][7] +dbg_regs[14][8] <= registerFile:RegFile.dbg_regs[14][8] +dbg_regs[14][9] <= registerFile:RegFile.dbg_regs[14][9] +dbg_regs[14][10] <= registerFile:RegFile.dbg_regs[14][10] +dbg_regs[14][11] <= registerFile:RegFile.dbg_regs[14][11] +dbg_regs[14][12] <= registerFile:RegFile.dbg_regs[14][12] +dbg_regs[14][13] <= registerFile:RegFile.dbg_regs[14][13] +dbg_regs[14][14] <= registerFile:RegFile.dbg_regs[14][14] +dbg_regs[14][15] <= registerFile:RegFile.dbg_regs[14][15] +dbg_regs[14][16] <= registerFile:RegFile.dbg_regs[14][16] +dbg_regs[14][17] <= registerFile:RegFile.dbg_regs[14][17] +dbg_regs[14][18] <= registerFile:RegFile.dbg_regs[14][18] +dbg_regs[14][19] <= registerFile:RegFile.dbg_regs[14][19] +dbg_regs[14][20] <= registerFile:RegFile.dbg_regs[14][20] +dbg_regs[14][21] <= registerFile:RegFile.dbg_regs[14][21] +dbg_regs[14][22] <= registerFile:RegFile.dbg_regs[14][22] +dbg_regs[14][23] <= registerFile:RegFile.dbg_regs[14][23] +dbg_regs[14][24] <= registerFile:RegFile.dbg_regs[14][24] +dbg_regs[14][25] <= registerFile:RegFile.dbg_regs[14][25] +dbg_regs[14][26] <= registerFile:RegFile.dbg_regs[14][26] +dbg_regs[14][27] <= registerFile:RegFile.dbg_regs[14][27] +dbg_regs[14][28] <= registerFile:RegFile.dbg_regs[14][28] +dbg_regs[14][29] <= registerFile:RegFile.dbg_regs[14][29] +dbg_regs[14][30] <= registerFile:RegFile.dbg_regs[14][30] +dbg_regs[14][31] <= registerFile:RegFile.dbg_regs[14][31] +dbg_regs[13][0] <= registerFile:RegFile.dbg_regs[13][0] +dbg_regs[13][1] <= registerFile:RegFile.dbg_regs[13][1] +dbg_regs[13][2] <= registerFile:RegFile.dbg_regs[13][2] +dbg_regs[13][3] <= registerFile:RegFile.dbg_regs[13][3] +dbg_regs[13][4] <= registerFile:RegFile.dbg_regs[13][4] +dbg_regs[13][5] <= registerFile:RegFile.dbg_regs[13][5] +dbg_regs[13][6] <= registerFile:RegFile.dbg_regs[13][6] +dbg_regs[13][7] <= registerFile:RegFile.dbg_regs[13][7] +dbg_regs[13][8] <= registerFile:RegFile.dbg_regs[13][8] +dbg_regs[13][9] <= registerFile:RegFile.dbg_regs[13][9] +dbg_regs[13][10] <= registerFile:RegFile.dbg_regs[13][10] +dbg_regs[13][11] <= registerFile:RegFile.dbg_regs[13][11] +dbg_regs[13][12] <= registerFile:RegFile.dbg_regs[13][12] +dbg_regs[13][13] <= registerFile:RegFile.dbg_regs[13][13] +dbg_regs[13][14] <= registerFile:RegFile.dbg_regs[13][14] +dbg_regs[13][15] <= registerFile:RegFile.dbg_regs[13][15] +dbg_regs[13][16] <= registerFile:RegFile.dbg_regs[13][16] +dbg_regs[13][17] <= registerFile:RegFile.dbg_regs[13][17] +dbg_regs[13][18] <= registerFile:RegFile.dbg_regs[13][18] +dbg_regs[13][19] <= registerFile:RegFile.dbg_regs[13][19] +dbg_regs[13][20] <= registerFile:RegFile.dbg_regs[13][20] +dbg_regs[13][21] <= registerFile:RegFile.dbg_regs[13][21] +dbg_regs[13][22] <= registerFile:RegFile.dbg_regs[13][22] +dbg_regs[13][23] <= registerFile:RegFile.dbg_regs[13][23] +dbg_regs[13][24] <= registerFile:RegFile.dbg_regs[13][24] +dbg_regs[13][25] <= registerFile:RegFile.dbg_regs[13][25] +dbg_regs[13][26] <= registerFile:RegFile.dbg_regs[13][26] +dbg_regs[13][27] <= registerFile:RegFile.dbg_regs[13][27] +dbg_regs[13][28] <= registerFile:RegFile.dbg_regs[13][28] +dbg_regs[13][29] <= registerFile:RegFile.dbg_regs[13][29] +dbg_regs[13][30] <= registerFile:RegFile.dbg_regs[13][30] +dbg_regs[13][31] <= registerFile:RegFile.dbg_regs[13][31] +dbg_regs[12][0] <= registerFile:RegFile.dbg_regs[12][0] +dbg_regs[12][1] <= registerFile:RegFile.dbg_regs[12][1] +dbg_regs[12][2] <= registerFile:RegFile.dbg_regs[12][2] +dbg_regs[12][3] <= registerFile:RegFile.dbg_regs[12][3] +dbg_regs[12][4] <= registerFile:RegFile.dbg_regs[12][4] +dbg_regs[12][5] <= registerFile:RegFile.dbg_regs[12][5] +dbg_regs[12][6] <= registerFile:RegFile.dbg_regs[12][6] +dbg_regs[12][7] <= registerFile:RegFile.dbg_regs[12][7] +dbg_regs[12][8] <= registerFile:RegFile.dbg_regs[12][8] +dbg_regs[12][9] <= registerFile:RegFile.dbg_regs[12][9] +dbg_regs[12][10] <= registerFile:RegFile.dbg_regs[12][10] +dbg_regs[12][11] <= registerFile:RegFile.dbg_regs[12][11] +dbg_regs[12][12] <= registerFile:RegFile.dbg_regs[12][12] +dbg_regs[12][13] <= registerFile:RegFile.dbg_regs[12][13] +dbg_regs[12][14] <= registerFile:RegFile.dbg_regs[12][14] +dbg_regs[12][15] <= registerFile:RegFile.dbg_regs[12][15] +dbg_regs[12][16] <= registerFile:RegFile.dbg_regs[12][16] +dbg_regs[12][17] <= registerFile:RegFile.dbg_regs[12][17] +dbg_regs[12][18] <= registerFile:RegFile.dbg_regs[12][18] +dbg_regs[12][19] <= registerFile:RegFile.dbg_regs[12][19] +dbg_regs[12][20] <= registerFile:RegFile.dbg_regs[12][20] +dbg_regs[12][21] <= registerFile:RegFile.dbg_regs[12][21] +dbg_regs[12][22] <= registerFile:RegFile.dbg_regs[12][22] +dbg_regs[12][23] <= registerFile:RegFile.dbg_regs[12][23] +dbg_regs[12][24] <= registerFile:RegFile.dbg_regs[12][24] +dbg_regs[12][25] <= registerFile:RegFile.dbg_regs[12][25] +dbg_regs[12][26] <= registerFile:RegFile.dbg_regs[12][26] +dbg_regs[12][27] <= registerFile:RegFile.dbg_regs[12][27] +dbg_regs[12][28] <= registerFile:RegFile.dbg_regs[12][28] +dbg_regs[12][29] <= registerFile:RegFile.dbg_regs[12][29] +dbg_regs[12][30] <= registerFile:RegFile.dbg_regs[12][30] +dbg_regs[12][31] <= registerFile:RegFile.dbg_regs[12][31] +dbg_regs[11][0] <= registerFile:RegFile.dbg_regs[11][0] +dbg_regs[11][1] <= registerFile:RegFile.dbg_regs[11][1] +dbg_regs[11][2] <= registerFile:RegFile.dbg_regs[11][2] +dbg_regs[11][3] <= registerFile:RegFile.dbg_regs[11][3] +dbg_regs[11][4] <= registerFile:RegFile.dbg_regs[11][4] +dbg_regs[11][5] <= registerFile:RegFile.dbg_regs[11][5] +dbg_regs[11][6] <= registerFile:RegFile.dbg_regs[11][6] +dbg_regs[11][7] <= registerFile:RegFile.dbg_regs[11][7] +dbg_regs[11][8] <= registerFile:RegFile.dbg_regs[11][8] +dbg_regs[11][9] <= registerFile:RegFile.dbg_regs[11][9] +dbg_regs[11][10] <= registerFile:RegFile.dbg_regs[11][10] +dbg_regs[11][11] <= registerFile:RegFile.dbg_regs[11][11] +dbg_regs[11][12] <= registerFile:RegFile.dbg_regs[11][12] +dbg_regs[11][13] <= registerFile:RegFile.dbg_regs[11][13] +dbg_regs[11][14] <= registerFile:RegFile.dbg_regs[11][14] +dbg_regs[11][15] <= registerFile:RegFile.dbg_regs[11][15] +dbg_regs[11][16] <= registerFile:RegFile.dbg_regs[11][16] +dbg_regs[11][17] <= registerFile:RegFile.dbg_regs[11][17] +dbg_regs[11][18] <= registerFile:RegFile.dbg_regs[11][18] +dbg_regs[11][19] <= registerFile:RegFile.dbg_regs[11][19] +dbg_regs[11][20] <= registerFile:RegFile.dbg_regs[11][20] +dbg_regs[11][21] <= registerFile:RegFile.dbg_regs[11][21] +dbg_regs[11][22] <= registerFile:RegFile.dbg_regs[11][22] +dbg_regs[11][23] <= registerFile:RegFile.dbg_regs[11][23] +dbg_regs[11][24] <= registerFile:RegFile.dbg_regs[11][24] +dbg_regs[11][25] <= registerFile:RegFile.dbg_regs[11][25] +dbg_regs[11][26] <= registerFile:RegFile.dbg_regs[11][26] +dbg_regs[11][27] <= registerFile:RegFile.dbg_regs[11][27] +dbg_regs[11][28] <= registerFile:RegFile.dbg_regs[11][28] +dbg_regs[11][29] <= registerFile:RegFile.dbg_regs[11][29] +dbg_regs[11][30] <= registerFile:RegFile.dbg_regs[11][30] +dbg_regs[11][31] <= registerFile:RegFile.dbg_regs[11][31] +dbg_regs[10][0] <= registerFile:RegFile.dbg_regs[10][0] +dbg_regs[10][1] <= registerFile:RegFile.dbg_regs[10][1] +dbg_regs[10][2] <= registerFile:RegFile.dbg_regs[10][2] +dbg_regs[10][3] <= registerFile:RegFile.dbg_regs[10][3] +dbg_regs[10][4] <= registerFile:RegFile.dbg_regs[10][4] +dbg_regs[10][5] <= registerFile:RegFile.dbg_regs[10][5] +dbg_regs[10][6] <= registerFile:RegFile.dbg_regs[10][6] +dbg_regs[10][7] <= registerFile:RegFile.dbg_regs[10][7] +dbg_regs[10][8] <= registerFile:RegFile.dbg_regs[10][8] +dbg_regs[10][9] <= registerFile:RegFile.dbg_regs[10][9] +dbg_regs[10][10] <= registerFile:RegFile.dbg_regs[10][10] +dbg_regs[10][11] <= registerFile:RegFile.dbg_regs[10][11] +dbg_regs[10][12] <= registerFile:RegFile.dbg_regs[10][12] +dbg_regs[10][13] <= registerFile:RegFile.dbg_regs[10][13] +dbg_regs[10][14] <= registerFile:RegFile.dbg_regs[10][14] +dbg_regs[10][15] <= registerFile:RegFile.dbg_regs[10][15] +dbg_regs[10][16] <= registerFile:RegFile.dbg_regs[10][16] +dbg_regs[10][17] <= registerFile:RegFile.dbg_regs[10][17] +dbg_regs[10][18] <= registerFile:RegFile.dbg_regs[10][18] +dbg_regs[10][19] <= registerFile:RegFile.dbg_regs[10][19] +dbg_regs[10][20] <= registerFile:RegFile.dbg_regs[10][20] +dbg_regs[10][21] <= registerFile:RegFile.dbg_regs[10][21] +dbg_regs[10][22] <= registerFile:RegFile.dbg_regs[10][22] +dbg_regs[10][23] <= registerFile:RegFile.dbg_regs[10][23] +dbg_regs[10][24] <= registerFile:RegFile.dbg_regs[10][24] +dbg_regs[10][25] <= registerFile:RegFile.dbg_regs[10][25] +dbg_regs[10][26] <= registerFile:RegFile.dbg_regs[10][26] +dbg_regs[10][27] <= registerFile:RegFile.dbg_regs[10][27] +dbg_regs[10][28] <= registerFile:RegFile.dbg_regs[10][28] +dbg_regs[10][29] <= registerFile:RegFile.dbg_regs[10][29] +dbg_regs[10][30] <= registerFile:RegFile.dbg_regs[10][30] +dbg_regs[10][31] <= registerFile:RegFile.dbg_regs[10][31] +dbg_regs[9][0] <= registerFile:RegFile.dbg_regs[9][0] +dbg_regs[9][1] <= registerFile:RegFile.dbg_regs[9][1] +dbg_regs[9][2] <= registerFile:RegFile.dbg_regs[9][2] +dbg_regs[9][3] <= registerFile:RegFile.dbg_regs[9][3] +dbg_regs[9][4] <= registerFile:RegFile.dbg_regs[9][4] +dbg_regs[9][5] <= registerFile:RegFile.dbg_regs[9][5] +dbg_regs[9][6] <= registerFile:RegFile.dbg_regs[9][6] +dbg_regs[9][7] <= registerFile:RegFile.dbg_regs[9][7] +dbg_regs[9][8] <= registerFile:RegFile.dbg_regs[9][8] +dbg_regs[9][9] <= registerFile:RegFile.dbg_regs[9][9] +dbg_regs[9][10] <= registerFile:RegFile.dbg_regs[9][10] +dbg_regs[9][11] <= registerFile:RegFile.dbg_regs[9][11] +dbg_regs[9][12] <= registerFile:RegFile.dbg_regs[9][12] +dbg_regs[9][13] <= registerFile:RegFile.dbg_regs[9][13] +dbg_regs[9][14] <= registerFile:RegFile.dbg_regs[9][14] +dbg_regs[9][15] <= registerFile:RegFile.dbg_regs[9][15] +dbg_regs[9][16] <= registerFile:RegFile.dbg_regs[9][16] +dbg_regs[9][17] <= registerFile:RegFile.dbg_regs[9][17] +dbg_regs[9][18] <= registerFile:RegFile.dbg_regs[9][18] +dbg_regs[9][19] <= registerFile:RegFile.dbg_regs[9][19] +dbg_regs[9][20] <= registerFile:RegFile.dbg_regs[9][20] +dbg_regs[9][21] <= registerFile:RegFile.dbg_regs[9][21] +dbg_regs[9][22] <= registerFile:RegFile.dbg_regs[9][22] +dbg_regs[9][23] <= registerFile:RegFile.dbg_regs[9][23] +dbg_regs[9][24] <= registerFile:RegFile.dbg_regs[9][24] +dbg_regs[9][25] <= registerFile:RegFile.dbg_regs[9][25] +dbg_regs[9][26] <= registerFile:RegFile.dbg_regs[9][26] +dbg_regs[9][27] <= registerFile:RegFile.dbg_regs[9][27] +dbg_regs[9][28] <= registerFile:RegFile.dbg_regs[9][28] +dbg_regs[9][29] <= registerFile:RegFile.dbg_regs[9][29] +dbg_regs[9][30] <= registerFile:RegFile.dbg_regs[9][30] +dbg_regs[9][31] <= registerFile:RegFile.dbg_regs[9][31] +dbg_regs[8][0] <= registerFile:RegFile.dbg_regs[8][0] +dbg_regs[8][1] <= registerFile:RegFile.dbg_regs[8][1] +dbg_regs[8][2] <= registerFile:RegFile.dbg_regs[8][2] +dbg_regs[8][3] <= registerFile:RegFile.dbg_regs[8][3] +dbg_regs[8][4] <= registerFile:RegFile.dbg_regs[8][4] +dbg_regs[8][5] <= registerFile:RegFile.dbg_regs[8][5] +dbg_regs[8][6] <= registerFile:RegFile.dbg_regs[8][6] +dbg_regs[8][7] <= registerFile:RegFile.dbg_regs[8][7] +dbg_regs[8][8] <= registerFile:RegFile.dbg_regs[8][8] +dbg_regs[8][9] <= registerFile:RegFile.dbg_regs[8][9] +dbg_regs[8][10] <= registerFile:RegFile.dbg_regs[8][10] +dbg_regs[8][11] <= registerFile:RegFile.dbg_regs[8][11] +dbg_regs[8][12] <= registerFile:RegFile.dbg_regs[8][12] +dbg_regs[8][13] <= registerFile:RegFile.dbg_regs[8][13] +dbg_regs[8][14] <= registerFile:RegFile.dbg_regs[8][14] +dbg_regs[8][15] <= registerFile:RegFile.dbg_regs[8][15] +dbg_regs[8][16] <= registerFile:RegFile.dbg_regs[8][16] +dbg_regs[8][17] <= registerFile:RegFile.dbg_regs[8][17] +dbg_regs[8][18] <= registerFile:RegFile.dbg_regs[8][18] +dbg_regs[8][19] <= registerFile:RegFile.dbg_regs[8][19] +dbg_regs[8][20] <= registerFile:RegFile.dbg_regs[8][20] +dbg_regs[8][21] <= registerFile:RegFile.dbg_regs[8][21] +dbg_regs[8][22] <= registerFile:RegFile.dbg_regs[8][22] +dbg_regs[8][23] <= registerFile:RegFile.dbg_regs[8][23] +dbg_regs[8][24] <= registerFile:RegFile.dbg_regs[8][24] +dbg_regs[8][25] <= registerFile:RegFile.dbg_regs[8][25] +dbg_regs[8][26] <= registerFile:RegFile.dbg_regs[8][26] +dbg_regs[8][27] <= registerFile:RegFile.dbg_regs[8][27] +dbg_regs[8][28] <= registerFile:RegFile.dbg_regs[8][28] +dbg_regs[8][29] <= registerFile:RegFile.dbg_regs[8][29] +dbg_regs[8][30] <= registerFile:RegFile.dbg_regs[8][30] +dbg_regs[8][31] <= registerFile:RegFile.dbg_regs[8][31] +dbg_regs[7][0] <= registerFile:RegFile.dbg_regs[7][0] +dbg_regs[7][1] <= registerFile:RegFile.dbg_regs[7][1] +dbg_regs[7][2] <= registerFile:RegFile.dbg_regs[7][2] +dbg_regs[7][3] <= registerFile:RegFile.dbg_regs[7][3] +dbg_regs[7][4] <= registerFile:RegFile.dbg_regs[7][4] +dbg_regs[7][5] <= registerFile:RegFile.dbg_regs[7][5] +dbg_regs[7][6] <= registerFile:RegFile.dbg_regs[7][6] +dbg_regs[7][7] <= registerFile:RegFile.dbg_regs[7][7] +dbg_regs[7][8] <= registerFile:RegFile.dbg_regs[7][8] +dbg_regs[7][9] <= registerFile:RegFile.dbg_regs[7][9] +dbg_regs[7][10] <= registerFile:RegFile.dbg_regs[7][10] +dbg_regs[7][11] <= registerFile:RegFile.dbg_regs[7][11] +dbg_regs[7][12] <= registerFile:RegFile.dbg_regs[7][12] +dbg_regs[7][13] <= registerFile:RegFile.dbg_regs[7][13] +dbg_regs[7][14] <= registerFile:RegFile.dbg_regs[7][14] +dbg_regs[7][15] <= registerFile:RegFile.dbg_regs[7][15] +dbg_regs[7][16] <= registerFile:RegFile.dbg_regs[7][16] +dbg_regs[7][17] <= registerFile:RegFile.dbg_regs[7][17] +dbg_regs[7][18] <= registerFile:RegFile.dbg_regs[7][18] +dbg_regs[7][19] <= registerFile:RegFile.dbg_regs[7][19] +dbg_regs[7][20] <= registerFile:RegFile.dbg_regs[7][20] +dbg_regs[7][21] <= registerFile:RegFile.dbg_regs[7][21] +dbg_regs[7][22] <= registerFile:RegFile.dbg_regs[7][22] +dbg_regs[7][23] <= registerFile:RegFile.dbg_regs[7][23] +dbg_regs[7][24] <= registerFile:RegFile.dbg_regs[7][24] +dbg_regs[7][25] <= registerFile:RegFile.dbg_regs[7][25] +dbg_regs[7][26] <= registerFile:RegFile.dbg_regs[7][26] +dbg_regs[7][27] <= registerFile:RegFile.dbg_regs[7][27] +dbg_regs[7][28] <= registerFile:RegFile.dbg_regs[7][28] +dbg_regs[7][29] <= registerFile:RegFile.dbg_regs[7][29] +dbg_regs[7][30] <= registerFile:RegFile.dbg_regs[7][30] +dbg_regs[7][31] <= registerFile:RegFile.dbg_regs[7][31] +dbg_regs[6][0] <= registerFile:RegFile.dbg_regs[6][0] +dbg_regs[6][1] <= registerFile:RegFile.dbg_regs[6][1] +dbg_regs[6][2] <= registerFile:RegFile.dbg_regs[6][2] +dbg_regs[6][3] <= registerFile:RegFile.dbg_regs[6][3] +dbg_regs[6][4] <= registerFile:RegFile.dbg_regs[6][4] +dbg_regs[6][5] <= registerFile:RegFile.dbg_regs[6][5] +dbg_regs[6][6] <= registerFile:RegFile.dbg_regs[6][6] +dbg_regs[6][7] <= registerFile:RegFile.dbg_regs[6][7] +dbg_regs[6][8] <= registerFile:RegFile.dbg_regs[6][8] +dbg_regs[6][9] <= registerFile:RegFile.dbg_regs[6][9] +dbg_regs[6][10] <= registerFile:RegFile.dbg_regs[6][10] +dbg_regs[6][11] <= registerFile:RegFile.dbg_regs[6][11] +dbg_regs[6][12] <= registerFile:RegFile.dbg_regs[6][12] +dbg_regs[6][13] <= registerFile:RegFile.dbg_regs[6][13] +dbg_regs[6][14] <= registerFile:RegFile.dbg_regs[6][14] +dbg_regs[6][15] <= registerFile:RegFile.dbg_regs[6][15] +dbg_regs[6][16] <= registerFile:RegFile.dbg_regs[6][16] +dbg_regs[6][17] <= registerFile:RegFile.dbg_regs[6][17] +dbg_regs[6][18] <= registerFile:RegFile.dbg_regs[6][18] +dbg_regs[6][19] <= registerFile:RegFile.dbg_regs[6][19] +dbg_regs[6][20] <= registerFile:RegFile.dbg_regs[6][20] +dbg_regs[6][21] <= registerFile:RegFile.dbg_regs[6][21] +dbg_regs[6][22] <= registerFile:RegFile.dbg_regs[6][22] +dbg_regs[6][23] <= registerFile:RegFile.dbg_regs[6][23] +dbg_regs[6][24] <= registerFile:RegFile.dbg_regs[6][24] +dbg_regs[6][25] <= registerFile:RegFile.dbg_regs[6][25] +dbg_regs[6][26] <= registerFile:RegFile.dbg_regs[6][26] +dbg_regs[6][27] <= registerFile:RegFile.dbg_regs[6][27] +dbg_regs[6][28] <= registerFile:RegFile.dbg_regs[6][28] +dbg_regs[6][29] <= registerFile:RegFile.dbg_regs[6][29] +dbg_regs[6][30] <= registerFile:RegFile.dbg_regs[6][30] +dbg_regs[6][31] <= registerFile:RegFile.dbg_regs[6][31] +dbg_regs[5][0] <= registerFile:RegFile.dbg_regs[5][0] +dbg_regs[5][1] <= registerFile:RegFile.dbg_regs[5][1] +dbg_regs[5][2] <= registerFile:RegFile.dbg_regs[5][2] +dbg_regs[5][3] <= registerFile:RegFile.dbg_regs[5][3] +dbg_regs[5][4] <= registerFile:RegFile.dbg_regs[5][4] +dbg_regs[5][5] <= registerFile:RegFile.dbg_regs[5][5] +dbg_regs[5][6] <= registerFile:RegFile.dbg_regs[5][6] +dbg_regs[5][7] <= registerFile:RegFile.dbg_regs[5][7] +dbg_regs[5][8] <= registerFile:RegFile.dbg_regs[5][8] +dbg_regs[5][9] <= registerFile:RegFile.dbg_regs[5][9] +dbg_regs[5][10] <= registerFile:RegFile.dbg_regs[5][10] +dbg_regs[5][11] <= registerFile:RegFile.dbg_regs[5][11] +dbg_regs[5][12] <= registerFile:RegFile.dbg_regs[5][12] +dbg_regs[5][13] <= registerFile:RegFile.dbg_regs[5][13] +dbg_regs[5][14] <= registerFile:RegFile.dbg_regs[5][14] +dbg_regs[5][15] <= registerFile:RegFile.dbg_regs[5][15] +dbg_regs[5][16] <= registerFile:RegFile.dbg_regs[5][16] +dbg_regs[5][17] <= registerFile:RegFile.dbg_regs[5][17] +dbg_regs[5][18] <= registerFile:RegFile.dbg_regs[5][18] +dbg_regs[5][19] <= registerFile:RegFile.dbg_regs[5][19] +dbg_regs[5][20] <= registerFile:RegFile.dbg_regs[5][20] +dbg_regs[5][21] <= registerFile:RegFile.dbg_regs[5][21] +dbg_regs[5][22] <= registerFile:RegFile.dbg_regs[5][22] +dbg_regs[5][23] <= registerFile:RegFile.dbg_regs[5][23] +dbg_regs[5][24] <= registerFile:RegFile.dbg_regs[5][24] +dbg_regs[5][25] <= registerFile:RegFile.dbg_regs[5][25] +dbg_regs[5][26] <= registerFile:RegFile.dbg_regs[5][26] +dbg_regs[5][27] <= registerFile:RegFile.dbg_regs[5][27] +dbg_regs[5][28] <= registerFile:RegFile.dbg_regs[5][28] +dbg_regs[5][29] <= registerFile:RegFile.dbg_regs[5][29] +dbg_regs[5][30] <= registerFile:RegFile.dbg_regs[5][30] +dbg_regs[5][31] <= registerFile:RegFile.dbg_regs[5][31] +dbg_regs[4][0] <= registerFile:RegFile.dbg_regs[4][0] +dbg_regs[4][1] <= registerFile:RegFile.dbg_regs[4][1] +dbg_regs[4][2] <= registerFile:RegFile.dbg_regs[4][2] +dbg_regs[4][3] <= registerFile:RegFile.dbg_regs[4][3] +dbg_regs[4][4] <= registerFile:RegFile.dbg_regs[4][4] +dbg_regs[4][5] <= registerFile:RegFile.dbg_regs[4][5] +dbg_regs[4][6] <= registerFile:RegFile.dbg_regs[4][6] +dbg_regs[4][7] <= registerFile:RegFile.dbg_regs[4][7] +dbg_regs[4][8] <= registerFile:RegFile.dbg_regs[4][8] +dbg_regs[4][9] <= registerFile:RegFile.dbg_regs[4][9] +dbg_regs[4][10] <= registerFile:RegFile.dbg_regs[4][10] +dbg_regs[4][11] <= registerFile:RegFile.dbg_regs[4][11] +dbg_regs[4][12] <= registerFile:RegFile.dbg_regs[4][12] +dbg_regs[4][13] <= registerFile:RegFile.dbg_regs[4][13] +dbg_regs[4][14] <= registerFile:RegFile.dbg_regs[4][14] +dbg_regs[4][15] <= registerFile:RegFile.dbg_regs[4][15] +dbg_regs[4][16] <= registerFile:RegFile.dbg_regs[4][16] +dbg_regs[4][17] <= registerFile:RegFile.dbg_regs[4][17] +dbg_regs[4][18] <= registerFile:RegFile.dbg_regs[4][18] +dbg_regs[4][19] <= registerFile:RegFile.dbg_regs[4][19] +dbg_regs[4][20] <= registerFile:RegFile.dbg_regs[4][20] +dbg_regs[4][21] <= registerFile:RegFile.dbg_regs[4][21] +dbg_regs[4][22] <= registerFile:RegFile.dbg_regs[4][22] +dbg_regs[4][23] <= registerFile:RegFile.dbg_regs[4][23] +dbg_regs[4][24] <= registerFile:RegFile.dbg_regs[4][24] +dbg_regs[4][25] <= registerFile:RegFile.dbg_regs[4][25] +dbg_regs[4][26] <= registerFile:RegFile.dbg_regs[4][26] +dbg_regs[4][27] <= registerFile:RegFile.dbg_regs[4][27] +dbg_regs[4][28] <= registerFile:RegFile.dbg_regs[4][28] +dbg_regs[4][29] <= registerFile:RegFile.dbg_regs[4][29] +dbg_regs[4][30] <= registerFile:RegFile.dbg_regs[4][30] +dbg_regs[4][31] <= registerFile:RegFile.dbg_regs[4][31] +dbg_regs[3][0] <= registerFile:RegFile.dbg_regs[3][0] +dbg_regs[3][1] <= registerFile:RegFile.dbg_regs[3][1] +dbg_regs[3][2] <= registerFile:RegFile.dbg_regs[3][2] +dbg_regs[3][3] <= registerFile:RegFile.dbg_regs[3][3] +dbg_regs[3][4] <= registerFile:RegFile.dbg_regs[3][4] +dbg_regs[3][5] <= registerFile:RegFile.dbg_regs[3][5] +dbg_regs[3][6] <= registerFile:RegFile.dbg_regs[3][6] +dbg_regs[3][7] <= registerFile:RegFile.dbg_regs[3][7] +dbg_regs[3][8] <= registerFile:RegFile.dbg_regs[3][8] +dbg_regs[3][9] <= registerFile:RegFile.dbg_regs[3][9] +dbg_regs[3][10] <= registerFile:RegFile.dbg_regs[3][10] +dbg_regs[3][11] <= registerFile:RegFile.dbg_regs[3][11] +dbg_regs[3][12] <= registerFile:RegFile.dbg_regs[3][12] +dbg_regs[3][13] <= registerFile:RegFile.dbg_regs[3][13] +dbg_regs[3][14] <= registerFile:RegFile.dbg_regs[3][14] +dbg_regs[3][15] <= registerFile:RegFile.dbg_regs[3][15] +dbg_regs[3][16] <= registerFile:RegFile.dbg_regs[3][16] +dbg_regs[3][17] <= registerFile:RegFile.dbg_regs[3][17] +dbg_regs[3][18] <= registerFile:RegFile.dbg_regs[3][18] +dbg_regs[3][19] <= registerFile:RegFile.dbg_regs[3][19] +dbg_regs[3][20] <= registerFile:RegFile.dbg_regs[3][20] +dbg_regs[3][21] <= registerFile:RegFile.dbg_regs[3][21] +dbg_regs[3][22] <= registerFile:RegFile.dbg_regs[3][22] +dbg_regs[3][23] <= registerFile:RegFile.dbg_regs[3][23] +dbg_regs[3][24] <= registerFile:RegFile.dbg_regs[3][24] +dbg_regs[3][25] <= registerFile:RegFile.dbg_regs[3][25] +dbg_regs[3][26] <= registerFile:RegFile.dbg_regs[3][26] +dbg_regs[3][27] <= registerFile:RegFile.dbg_regs[3][27] +dbg_regs[3][28] <= registerFile:RegFile.dbg_regs[3][28] +dbg_regs[3][29] <= registerFile:RegFile.dbg_regs[3][29] +dbg_regs[3][30] <= registerFile:RegFile.dbg_regs[3][30] +dbg_regs[3][31] <= registerFile:RegFile.dbg_regs[3][31] +dbg_regs[2][0] <= registerFile:RegFile.dbg_regs[2][0] +dbg_regs[2][1] <= registerFile:RegFile.dbg_regs[2][1] +dbg_regs[2][2] <= registerFile:RegFile.dbg_regs[2][2] +dbg_regs[2][3] <= registerFile:RegFile.dbg_regs[2][3] +dbg_regs[2][4] <= registerFile:RegFile.dbg_regs[2][4] +dbg_regs[2][5] <= registerFile:RegFile.dbg_regs[2][5] +dbg_regs[2][6] <= registerFile:RegFile.dbg_regs[2][6] +dbg_regs[2][7] <= registerFile:RegFile.dbg_regs[2][7] +dbg_regs[2][8] <= registerFile:RegFile.dbg_regs[2][8] +dbg_regs[2][9] <= registerFile:RegFile.dbg_regs[2][9] +dbg_regs[2][10] <= registerFile:RegFile.dbg_regs[2][10] +dbg_regs[2][11] <= registerFile:RegFile.dbg_regs[2][11] +dbg_regs[2][12] <= registerFile:RegFile.dbg_regs[2][12] +dbg_regs[2][13] <= registerFile:RegFile.dbg_regs[2][13] +dbg_regs[2][14] <= registerFile:RegFile.dbg_regs[2][14] +dbg_regs[2][15] <= registerFile:RegFile.dbg_regs[2][15] +dbg_regs[2][16] <= registerFile:RegFile.dbg_regs[2][16] +dbg_regs[2][17] <= registerFile:RegFile.dbg_regs[2][17] +dbg_regs[2][18] <= registerFile:RegFile.dbg_regs[2][18] +dbg_regs[2][19] <= registerFile:RegFile.dbg_regs[2][19] +dbg_regs[2][20] <= registerFile:RegFile.dbg_regs[2][20] +dbg_regs[2][21] <= registerFile:RegFile.dbg_regs[2][21] +dbg_regs[2][22] <= registerFile:RegFile.dbg_regs[2][22] +dbg_regs[2][23] <= registerFile:RegFile.dbg_regs[2][23] +dbg_regs[2][24] <= registerFile:RegFile.dbg_regs[2][24] +dbg_regs[2][25] <= registerFile:RegFile.dbg_regs[2][25] +dbg_regs[2][26] <= registerFile:RegFile.dbg_regs[2][26] +dbg_regs[2][27] <= registerFile:RegFile.dbg_regs[2][27] +dbg_regs[2][28] <= registerFile:RegFile.dbg_regs[2][28] +dbg_regs[2][29] <= registerFile:RegFile.dbg_regs[2][29] +dbg_regs[2][30] <= registerFile:RegFile.dbg_regs[2][30] +dbg_regs[2][31] <= registerFile:RegFile.dbg_regs[2][31] +dbg_regs[1][0] <= registerFile:RegFile.dbg_regs[1][0] +dbg_regs[1][1] <= registerFile:RegFile.dbg_regs[1][1] +dbg_regs[1][2] <= registerFile:RegFile.dbg_regs[1][2] +dbg_regs[1][3] <= registerFile:RegFile.dbg_regs[1][3] +dbg_regs[1][4] <= registerFile:RegFile.dbg_regs[1][4] +dbg_regs[1][5] <= registerFile:RegFile.dbg_regs[1][5] +dbg_regs[1][6] <= registerFile:RegFile.dbg_regs[1][6] +dbg_regs[1][7] <= registerFile:RegFile.dbg_regs[1][7] +dbg_regs[1][8] <= registerFile:RegFile.dbg_regs[1][8] +dbg_regs[1][9] <= registerFile:RegFile.dbg_regs[1][9] +dbg_regs[1][10] <= registerFile:RegFile.dbg_regs[1][10] +dbg_regs[1][11] <= registerFile:RegFile.dbg_regs[1][11] +dbg_regs[1][12] <= registerFile:RegFile.dbg_regs[1][12] +dbg_regs[1][13] <= registerFile:RegFile.dbg_regs[1][13] +dbg_regs[1][14] <= registerFile:RegFile.dbg_regs[1][14] +dbg_regs[1][15] <= registerFile:RegFile.dbg_regs[1][15] +dbg_regs[1][16] <= registerFile:RegFile.dbg_regs[1][16] +dbg_regs[1][17] <= registerFile:RegFile.dbg_regs[1][17] +dbg_regs[1][18] <= registerFile:RegFile.dbg_regs[1][18] +dbg_regs[1][19] <= registerFile:RegFile.dbg_regs[1][19] +dbg_regs[1][20] <= registerFile:RegFile.dbg_regs[1][20] +dbg_regs[1][21] <= registerFile:RegFile.dbg_regs[1][21] +dbg_regs[1][22] <= registerFile:RegFile.dbg_regs[1][22] +dbg_regs[1][23] <= registerFile:RegFile.dbg_regs[1][23] +dbg_regs[1][24] <= registerFile:RegFile.dbg_regs[1][24] +dbg_regs[1][25] <= registerFile:RegFile.dbg_regs[1][25] +dbg_regs[1][26] <= registerFile:RegFile.dbg_regs[1][26] +dbg_regs[1][27] <= registerFile:RegFile.dbg_regs[1][27] +dbg_regs[1][28] <= registerFile:RegFile.dbg_regs[1][28] +dbg_regs[1][29] <= registerFile:RegFile.dbg_regs[1][29] +dbg_regs[1][30] <= registerFile:RegFile.dbg_regs[1][30] +dbg_regs[1][31] <= registerFile:RegFile.dbg_regs[1][31] +dbg_regs[0][0] <= registerFile:RegFile.dbg_regs[0][0] +dbg_regs[0][1] <= registerFile:RegFile.dbg_regs[0][1] +dbg_regs[0][2] <= registerFile:RegFile.dbg_regs[0][2] +dbg_regs[0][3] <= registerFile:RegFile.dbg_regs[0][3] +dbg_regs[0][4] <= registerFile:RegFile.dbg_regs[0][4] +dbg_regs[0][5] <= registerFile:RegFile.dbg_regs[0][5] +dbg_regs[0][6] <= registerFile:RegFile.dbg_regs[0][6] +dbg_regs[0][7] <= registerFile:RegFile.dbg_regs[0][7] +dbg_regs[0][8] <= registerFile:RegFile.dbg_regs[0][8] +dbg_regs[0][9] <= registerFile:RegFile.dbg_regs[0][9] +dbg_regs[0][10] <= registerFile:RegFile.dbg_regs[0][10] +dbg_regs[0][11] <= registerFile:RegFile.dbg_regs[0][11] +dbg_regs[0][12] <= registerFile:RegFile.dbg_regs[0][12] +dbg_regs[0][13] <= registerFile:RegFile.dbg_regs[0][13] +dbg_regs[0][14] <= registerFile:RegFile.dbg_regs[0][14] +dbg_regs[0][15] <= registerFile:RegFile.dbg_regs[0][15] +dbg_regs[0][16] <= registerFile:RegFile.dbg_regs[0][16] +dbg_regs[0][17] <= registerFile:RegFile.dbg_regs[0][17] +dbg_regs[0][18] <= registerFile:RegFile.dbg_regs[0][18] +dbg_regs[0][19] <= registerFile:RegFile.dbg_regs[0][19] +dbg_regs[0][20] <= registerFile:RegFile.dbg_regs[0][20] +dbg_regs[0][21] <= registerFile:RegFile.dbg_regs[0][21] +dbg_regs[0][22] <= registerFile:RegFile.dbg_regs[0][22] +dbg_regs[0][23] <= registerFile:RegFile.dbg_regs[0][23] +dbg_regs[0][24] <= registerFile:RegFile.dbg_regs[0][24] +dbg_regs[0][25] <= registerFile:RegFile.dbg_regs[0][25] +dbg_regs[0][26] <= registerFile:RegFile.dbg_regs[0][26] +dbg_regs[0][27] <= registerFile:RegFile.dbg_regs[0][27] +dbg_regs[0][28] <= registerFile:RegFile.dbg_regs[0][28] +dbg_regs[0][29] <= registerFile:RegFile.dbg_regs[0][29] +dbg_regs[0][30] <= registerFile:RegFile.dbg_regs[0][30] +dbg_regs[0][31] <= registerFile:RegFile.dbg_regs[0][31] +dbg_pc[0] <= fetch:fetch.pc_cur[0] +dbg_pc[1] <= fetch:fetch.pc_cur[1] +dbg_pc[2] <= fetch:fetch.pc_cur[2] +dbg_pc[3] <= fetch:fetch.pc_cur[3] +dbg_pc[4] <= fetch:fetch.pc_cur[4] +dbg_pc[5] <= fetch:fetch.pc_cur[5] +dbg_pc[6] <= fetch:fetch.pc_cur[6] +dbg_pc[7] <= fetch:fetch.pc_cur[7] +dbg_pc[8] <= fetch:fetch.pc_cur[8] +dbg_pc[9] <= fetch:fetch.pc_cur[9] +dbg_pc[10] <= fetch:fetch.pc_cur[10] +dbg_pc[11] <= fetch:fetch.pc_cur[11] +dbg_pc[12] <= fetch:fetch.pc_cur[12] +dbg_pc[13] <= fetch:fetch.pc_cur[13] +dbg_pc[14] <= fetch:fetch.pc_cur[14] +dbg_pc[15] <= fetch:fetch.pc_cur[15] +dbg_pc[16] <= fetch:fetch.pc_cur[16] +dbg_pc[17] <= fetch:fetch.pc_cur[17] +dbg_pc[18] <= fetch:fetch.pc_cur[18] +dbg_pc[19] <= fetch:fetch.pc_cur[19] +dbg_pc[20] <= fetch:fetch.pc_cur[20] +dbg_pc[21] <= fetch:fetch.pc_cur[21] +dbg_pc[22] <= fetch:fetch.pc_cur[22] +dbg_pc[23] <= fetch:fetch.pc_cur[23] +dbg_pc[24] <= fetch:fetch.pc_cur[24] +dbg_pc[25] <= fetch:fetch.pc_cur[25] +dbg_pc[26] <= fetch:fetch.pc_cur[26] +dbg_pc[27] <= fetch:fetch.pc_cur[27] +dbg_pc[28] <= fetch:fetch.pc_cur[28] +dbg_pc[29] <= fetch:fetch.pc_cur[29] +dbg_pc[30] <= fetch:fetch.pc_cur[30] +dbg_pc[31] <= fetch:fetch.pc_cur[31] + + +|top|utoss_riscv:core|ControlFSM:control_fsm +opcode[0] => Equal0.IN5 +opcode[0] => Equal1.IN3 +opcode[0] => Equal2.IN2 +opcode[0] => Equal3.IN1 +opcode[0] => Equal4.IN2 +opcode[0] => Equal5.IN3 +opcode[0] => Equal6.IN3 +opcode[0] => Equal7.IN4 +opcode[0] => Equal8.IN4 +opcode[0] => Equal9.IN3 +opcode[1] => Equal0.IN4 +opcode[1] => Equal1.IN2 +opcode[1] => Equal2.IN1 +opcode[1] => Equal3.IN0 +opcode[1] => Equal4.IN1 +opcode[1] => Equal5.IN2 +opcode[1] => Equal6.IN2 +opcode[1] => Equal7.IN3 +opcode[1] => Equal8.IN3 +opcode[1] => Equal9.IN2 +opcode[2] => Equal0.IN3 +opcode[2] => Equal1.IN6 +opcode[2] => Equal2.IN6 +opcode[2] => Equal3.IN6 +opcode[2] => Equal4.IN6 +opcode[2] => Equal5.IN6 +opcode[2] => Equal6.IN1 +opcode[2] => Equal7.IN2 +opcode[2] => Equal8.IN2 +opcode[2] => Equal9.IN1 +opcode[3] => Equal0.IN2 +opcode[3] => Equal1.IN5 +opcode[3] => Equal2.IN5 +opcode[3] => Equal3.IN5 +opcode[3] => Equal4.IN5 +opcode[3] => Equal5.IN5 +opcode[3] => Equal6.IN6 +opcode[3] => Equal7.IN6 +opcode[3] => Equal8.IN6 +opcode[3] => Equal9.IN0 +opcode[4] => Equal0.IN6 +opcode[4] => Equal1.IN1 +opcode[4] => Equal2.IN0 +opcode[4] => Equal3.IN4 +opcode[4] => Equal4.IN4 +opcode[4] => Equal5.IN4 +opcode[4] => Equal6.IN0 +opcode[4] => Equal7.IN1 +opcode[4] => Equal8.IN5 +opcode[4] => Equal9.IN6 +opcode[5] => Equal0.IN1 +opcode[5] => Equal1.IN0 +opcode[5] => Equal2.IN4 +opcode[5] => Equal3.IN3 +opcode[5] => Equal4.IN0 +opcode[5] => Equal5.IN1 +opcode[5] => Equal6.IN5 +opcode[5] => Equal7.IN0 +opcode[5] => Equal8.IN1 +opcode[5] => Equal9.IN5 +opcode[6] => Equal0.IN0 +opcode[6] => Equal1.IN4 +opcode[6] => Equal2.IN3 +opcode[6] => Equal3.IN2 +opcode[6] => Equal4.IN3 +opcode[6] => Equal5.IN0 +opcode[6] => Equal6.IN4 +opcode[6] => Equal7.IN5 +opcode[6] => Equal8.IN0 +opcode[6] => Equal9.IN4 +clk => current_state~1.DATAIN +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +reset => current_state.OUTPUTSELECT +zero_flag => Selector11.IN5 +zero_flag => Selector11.IN1 +MemWriteByteAddress[0] => MemWrite.DATAB +MemWriteByteAddress[1] => MemWrite.DATAB +MemWriteByteAddress[2] => MemWrite.DATAB +MemWriteByteAddress[3] => MemWrite.DATAB +funct3[0] => Equal10.IN5 +funct3[0] => Equal11.IN5 +funct3[1] => Equal10.IN4 +funct3[1] => Equal11.IN4 +funct3[2] => Equal10.IN3 +funct3[2] => Equal11.IN3 +alu_result[0] => Equal12.IN0 +alu_result[1] => Equal12.IN31 +alu_result[2] => Equal12.IN30 +alu_result[3] => Equal12.IN29 +alu_result[4] => Equal12.IN28 +alu_result[5] => Equal12.IN27 +alu_result[6] => Equal12.IN26 +alu_result[7] => Equal12.IN25 +alu_result[8] => Equal12.IN24 +alu_result[9] => Equal12.IN23 +alu_result[10] => Equal12.IN22 +alu_result[11] => Equal12.IN21 +alu_result[12] => Equal12.IN20 +alu_result[13] => Equal12.IN19 +alu_result[14] => Equal12.IN18 +alu_result[15] => Equal12.IN17 +alu_result[16] => Equal12.IN16 +alu_result[17] => Equal12.IN15 +alu_result[18] => Equal12.IN14 +alu_result[19] => Equal12.IN13 +alu_result[20] => Equal12.IN12 +alu_result[21] => Equal12.IN11 +alu_result[22] => Equal12.IN10 +alu_result[23] => Equal12.IN9 +alu_result[24] => Equal12.IN8 +alu_result[25] => Equal12.IN7 +alu_result[26] => Equal12.IN6 +alu_result[27] => Equal12.IN5 +alu_result[28] => Equal12.IN4 +alu_result[29] => Equal12.IN3 +alu_result[30] => Equal12.IN2 +alu_result[31] => Equal12.IN1 +AdrSrc <= WideOr9.DB_MAX_OUTPUT_PORT_TYPE +IRWrite <= IRWrite.DB_MAX_OUTPUT_PORT_TYPE +RegWrite <= RegWrite.DB_MAX_OUTPUT_PORT_TYPE +PCUpdate <= Selector12.DB_MAX_OUTPUT_PORT_TYPE +pc_src[0] <= Selector13.DB_MAX_OUTPUT_PORT_TYPE +pc_src[1] <= pc_src[1].DB_MAX_OUTPUT_PORT_TYPE +MemWrite[0] <= MemWrite.DB_MAX_OUTPUT_PORT_TYPE +MemWrite[1] <= MemWrite.DB_MAX_OUTPUT_PORT_TYPE +MemWrite[2] <= MemWrite.DB_MAX_OUTPUT_PORT_TYPE +MemWrite[3] <= MemWrite.DB_MAX_OUTPUT_PORT_TYPE +Branch <= Branch.DB_MAX_OUTPUT_PORT_TYPE +ALUSrcA[0] <= ALUSrcA[0]$latch.DB_MAX_OUTPUT_PORT_TYPE +ALUSrcA[1] <= ALUSrcA[1]$latch.DB_MAX_OUTPUT_PORT_TYPE +ALUSrcB[0] <= ALUSrcB[0]$latch.DB_MAX_OUTPUT_PORT_TYPE +ALUSrcB[1] <= ALUSrcB[1]$latch.DB_MAX_OUTPUT_PORT_TYPE +ResultSrc[0] <= ResultSrc[0].DB_MAX_OUTPUT_PORT_TYPE +ResultSrc[1] <= ResultSrc[1].DB_MAX_OUTPUT_PORT_TYPE +FSMState[0] <= WideOr8.DB_MAX_OUTPUT_PORT_TYPE +FSMState[1] <= WideOr7.DB_MAX_OUTPUT_PORT_TYPE +FSMState[2] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE +FSMState[3] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE +FSMState[4] <= IRWrite.DB_MAX_OUTPUT_PORT_TYPE + + +|top|utoss_riscv:core|fetch:fetch +clk => pc_old[0]~reg0.CLK +clk => pc_old[1]~reg0.CLK +clk => pc_old[2]~reg0.CLK +clk => pc_old[3]~reg0.CLK +clk => pc_old[4]~reg0.CLK +clk => pc_old[5]~reg0.CLK +clk => pc_old[6]~reg0.CLK +clk => pc_old[7]~reg0.CLK +clk => pc_old[8]~reg0.CLK +clk => pc_old[9]~reg0.CLK +clk => pc_old[10]~reg0.CLK +clk => pc_old[11]~reg0.CLK +clk => pc_old[12]~reg0.CLK +clk => pc_old[13]~reg0.CLK +clk => pc_old[14]~reg0.CLK +clk => pc_old[15]~reg0.CLK +clk => pc_old[16]~reg0.CLK +clk => pc_old[17]~reg0.CLK +clk => pc_old[18]~reg0.CLK +clk => pc_old[19]~reg0.CLK +clk => pc_old[20]~reg0.CLK +clk => pc_old[21]~reg0.CLK +clk => pc_old[22]~reg0.CLK +clk => pc_old[23]~reg0.CLK +clk => pc_old[24]~reg0.CLK +clk => pc_old[25]~reg0.CLK +clk => pc_old[26]~reg0.CLK +clk => pc_old[27]~reg0.CLK +clk => pc_old[28]~reg0.CLK +clk => pc_old[29]~reg0.CLK +clk => pc_old[30]~reg0.CLK +clk => pc_old[31]~reg0.CLK +clk => pc_cur[0]~reg0.CLK +clk => pc_cur[1]~reg0.CLK +clk => pc_cur[2]~reg0.CLK +clk => pc_cur[3]~reg0.CLK +clk => pc_cur[4]~reg0.CLK +clk => pc_cur[5]~reg0.CLK +clk => pc_cur[6]~reg0.CLK +clk => pc_cur[7]~reg0.CLK +clk => pc_cur[8]~reg0.CLK +clk => pc_cur[9]~reg0.CLK +clk => pc_cur[10]~reg0.CLK +clk => pc_cur[11]~reg0.CLK +clk => pc_cur[12]~reg0.CLK +clk => pc_cur[13]~reg0.CLK +clk => pc_cur[14]~reg0.CLK +clk => pc_cur[15]~reg0.CLK +clk => pc_cur[16]~reg0.CLK +clk => pc_cur[17]~reg0.CLK +clk => pc_cur[18]~reg0.CLK +clk => pc_cur[19]~reg0.CLK +clk => pc_cur[20]~reg0.CLK +clk => pc_cur[21]~reg0.CLK +clk => pc_cur[22]~reg0.CLK +clk => pc_cur[23]~reg0.CLK +clk => pc_cur[24]~reg0.CLK +clk => pc_cur[25]~reg0.CLK +clk => pc_cur[26]~reg0.CLK +clk => pc_cur[27]~reg0.CLK +clk => pc_cur[28]~reg0.CLK +clk => pc_cur[29]~reg0.CLK +clk => pc_cur[30]~reg0.CLK +clk => pc_cur[31]~reg0.CLK +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +reset => pc_cur.OUTPUTSELECT +cfsm__pc_update => pc_next[31].OUTPUTSELECT +cfsm__pc_update => pc_next[30].OUTPUTSELECT +cfsm__pc_update => pc_next[29].OUTPUTSELECT +cfsm__pc_update => pc_next[28].OUTPUTSELECT +cfsm__pc_update => pc_next[27].OUTPUTSELECT +cfsm__pc_update => pc_next[26].OUTPUTSELECT +cfsm__pc_update => pc_next[25].OUTPUTSELECT +cfsm__pc_update => pc_next[24].OUTPUTSELECT +cfsm__pc_update => pc_next[23].OUTPUTSELECT +cfsm__pc_update => pc_next[22].OUTPUTSELECT +cfsm__pc_update => pc_next[21].OUTPUTSELECT +cfsm__pc_update => pc_next[20].OUTPUTSELECT +cfsm__pc_update => pc_next[19].OUTPUTSELECT +cfsm__pc_update => pc_next[18].OUTPUTSELECT +cfsm__pc_update => pc_next[17].OUTPUTSELECT +cfsm__pc_update => pc_next[16].OUTPUTSELECT +cfsm__pc_update => pc_next[15].OUTPUTSELECT +cfsm__pc_update => pc_next[14].OUTPUTSELECT +cfsm__pc_update => pc_next[13].OUTPUTSELECT +cfsm__pc_update => pc_next[12].OUTPUTSELECT +cfsm__pc_update => pc_next[11].OUTPUTSELECT +cfsm__pc_update => pc_next[10].OUTPUTSELECT +cfsm__pc_update => pc_next[9].OUTPUTSELECT +cfsm__pc_update => pc_next[8].OUTPUTSELECT +cfsm__pc_update => pc_next[7].OUTPUTSELECT +cfsm__pc_update => pc_next[6].OUTPUTSELECT +cfsm__pc_update => pc_next[5].OUTPUTSELECT +cfsm__pc_update => pc_next[4].OUTPUTSELECT +cfsm__pc_update => pc_next[3].OUTPUTSELECT +cfsm__pc_update => pc_next[2].OUTPUTSELECT +cfsm__pc_update => pc_next[1].OUTPUTSELECT +cfsm__pc_update => pc_next[0].OUTPUTSELECT +cfsm__pc_src[0] => Equal0.IN3 +cfsm__pc_src[0] => Equal1.IN3 +cfsm__pc_src[0] => Equal2.IN3 +cfsm__pc_src[1] => Equal0.IN2 +cfsm__pc_src[1] => Equal1.IN2 +cfsm__pc_src[1] => Equal2.IN2 +cfsm__ir_write => pc_old[0]~reg0.ENA +cfsm__ir_write => pc_old[1]~reg0.ENA +cfsm__ir_write => pc_old[2]~reg0.ENA +cfsm__ir_write => pc_old[3]~reg0.ENA +cfsm__ir_write => pc_old[4]~reg0.ENA +cfsm__ir_write => pc_old[5]~reg0.ENA +cfsm__ir_write => pc_old[6]~reg0.ENA +cfsm__ir_write => pc_old[7]~reg0.ENA +cfsm__ir_write => pc_old[8]~reg0.ENA +cfsm__ir_write => pc_old[9]~reg0.ENA +cfsm__ir_write => pc_old[10]~reg0.ENA +cfsm__ir_write => pc_old[11]~reg0.ENA +cfsm__ir_write => pc_old[12]~reg0.ENA +cfsm__ir_write => pc_old[13]~reg0.ENA +cfsm__ir_write => pc_old[14]~reg0.ENA +cfsm__ir_write => pc_old[15]~reg0.ENA +cfsm__ir_write => pc_old[16]~reg0.ENA +cfsm__ir_write => pc_old[17]~reg0.ENA +cfsm__ir_write => pc_old[18]~reg0.ENA +cfsm__ir_write => pc_old[19]~reg0.ENA +cfsm__ir_write => pc_old[20]~reg0.ENA +cfsm__ir_write => pc_old[21]~reg0.ENA +cfsm__ir_write => pc_old[22]~reg0.ENA +cfsm__ir_write => pc_old[23]~reg0.ENA +cfsm__ir_write => pc_old[24]~reg0.ENA +cfsm__ir_write => pc_old[25]~reg0.ENA +cfsm__ir_write => pc_old[26]~reg0.ENA +cfsm__ir_write => pc_old[27]~reg0.ENA +cfsm__ir_write => pc_old[28]~reg0.ENA +cfsm__ir_write => pc_old[29]~reg0.ENA +cfsm__ir_write => pc_old[30]~reg0.ENA +cfsm__ir_write => pc_old[31]~reg0.ENA +alu_result_for_pc[0] => ~NO_FANOUT~ +alu_result_for_pc[1] => Selector30.IN4 +alu_result_for_pc[2] => Selector29.IN5 +alu_result_for_pc[3] => Selector28.IN5 +alu_result_for_pc[4] => Selector27.IN5 +alu_result_for_pc[5] => Selector26.IN5 +alu_result_for_pc[6] => Selector25.IN5 +alu_result_for_pc[7] => Selector24.IN5 +alu_result_for_pc[8] => Selector23.IN5 +alu_result_for_pc[9] => Selector22.IN5 +alu_result_for_pc[10] => Selector21.IN5 +alu_result_for_pc[11] => Selector20.IN5 +alu_result_for_pc[12] => Selector19.IN5 +alu_result_for_pc[13] => Selector18.IN5 +alu_result_for_pc[14] => Selector17.IN5 +alu_result_for_pc[15] => Selector16.IN5 +alu_result_for_pc[16] => Selector15.IN5 +alu_result_for_pc[17] => Selector14.IN5 +alu_result_for_pc[18] => Selector13.IN5 +alu_result_for_pc[19] => Selector12.IN5 +alu_result_for_pc[20] => Selector11.IN5 +alu_result_for_pc[21] => Selector10.IN5 +alu_result_for_pc[22] => Selector9.IN5 +alu_result_for_pc[23] => Selector8.IN5 +alu_result_for_pc[24] => Selector7.IN5 +alu_result_for_pc[25] => Selector6.IN5 +alu_result_for_pc[26] => Selector5.IN5 +alu_result_for_pc[27] => Selector4.IN5 +alu_result_for_pc[28] => Selector3.IN5 +alu_result_for_pc[29] => Selector2.IN5 +alu_result_for_pc[30] => Selector1.IN5 +alu_result_for_pc[31] => Selector0.IN5 +imm_ext[0] => Add1.IN32 +imm_ext[1] => Add1.IN31 +imm_ext[2] => Add1.IN30 +imm_ext[3] => Add1.IN29 +imm_ext[4] => Add1.IN28 +imm_ext[5] => Add1.IN27 +imm_ext[6] => Add1.IN26 +imm_ext[7] => Add1.IN25 +imm_ext[8] => Add1.IN24 +imm_ext[9] => Add1.IN23 +imm_ext[10] => Add1.IN22 +imm_ext[11] => Add1.IN21 +imm_ext[12] => Add1.IN20 +imm_ext[13] => Add1.IN19 +imm_ext[14] => Add1.IN18 +imm_ext[15] => Add1.IN17 +imm_ext[16] => Add1.IN16 +imm_ext[17] => Add1.IN15 +imm_ext[18] => Add1.IN14 +imm_ext[19] => Add1.IN13 +imm_ext[20] => Add1.IN12 +imm_ext[21] => Add1.IN11 +imm_ext[22] => Add1.IN10 +imm_ext[23] => Add1.IN9 +imm_ext[24] => Add1.IN8 +imm_ext[25] => Add1.IN7 +imm_ext[26] => Add1.IN6 +imm_ext[27] => Add1.IN5 +imm_ext[28] => Add1.IN4 +imm_ext[29] => Add1.IN3 +imm_ext[30] => Add1.IN2 +imm_ext[31] => Add1.IN1 +pc_cur[0] <= pc_cur[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[1] <= pc_cur[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[2] <= pc_cur[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[3] <= pc_cur[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[4] <= pc_cur[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[5] <= pc_cur[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[6] <= pc_cur[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[7] <= pc_cur[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[8] <= pc_cur[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[9] <= pc_cur[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[10] <= pc_cur[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[11] <= pc_cur[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[12] <= pc_cur[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[13] <= pc_cur[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[14] <= pc_cur[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[15] <= pc_cur[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[16] <= pc_cur[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[17] <= pc_cur[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[18] <= pc_cur[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[19] <= pc_cur[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[20] <= pc_cur[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[21] <= pc_cur[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[22] <= pc_cur[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[23] <= pc_cur[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[24] <= pc_cur[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[25] <= pc_cur[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[26] <= pc_cur[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[27] <= pc_cur[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[28] <= pc_cur[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[29] <= pc_cur[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[30] <= pc_cur[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_cur[31] <= pc_cur[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[0] <= pc_old[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[1] <= pc_old[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[2] <= pc_old[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[3] <= pc_old[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[4] <= pc_old[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[5] <= pc_old[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[6] <= pc_old[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[7] <= pc_old[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[8] <= pc_old[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[9] <= pc_old[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[10] <= pc_old[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[11] <= pc_old[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[12] <= pc_old[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[13] <= pc_old[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[14] <= pc_old[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[15] <= pc_old[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[16] <= pc_old[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[17] <= pc_old[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[18] <= pc_old[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[19] <= pc_old[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[20] <= pc_old[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[21] <= pc_old[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[22] <= pc_old[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[23] <= pc_old[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[24] <= pc_old[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[25] <= pc_old[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[26] <= pc_old[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[27] <= pc_old[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[28] <= pc_old[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[29] <= pc_old[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[30] <= pc_old[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +pc_old[31] <= pc_old[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|top|utoss_riscv:core|MemoryLoader:MemLoad +memory_data[0] => Mux8.IN3 +memory_data[0] => Mux56.IN3 +memory_data[0] => Selector17.IN0 +memory_data[1] => Mux7.IN3 +memory_data[1] => Mux55.IN3 +memory_data[1] => Selector16.IN0 +memory_data[2] => Mux6.IN3 +memory_data[2] => Mux54.IN3 +memory_data[2] => Selector15.IN0 +memory_data[3] => Mux5.IN3 +memory_data[3] => Mux53.IN3 +memory_data[3] => Selector14.IN0 +memory_data[4] => Mux4.IN3 +memory_data[4] => Mux52.IN3 +memory_data[4] => Selector13.IN0 +memory_data[5] => Mux3.IN3 +memory_data[5] => Mux51.IN3 +memory_data[5] => Selector12.IN0 +memory_data[6] => Mux2.IN3 +memory_data[6] => Mux50.IN3 +memory_data[6] => Selector11.IN0 +memory_data[7] => Mux1.IN3 +memory_data[7] => Mux49.IN3 +memory_data[7] => Mux0.IN3 +memory_data[7] => Selector10.IN0 +memory_data[8] => Mux8.IN2 +memory_data[8] => Mux48.IN3 +memory_data[8] => Selector9.IN0 +memory_data[9] => Mux7.IN2 +memory_data[9] => Mux47.IN3 +memory_data[9] => Selector8.IN0 +memory_data[10] => Mux6.IN2 +memory_data[10] => Mux46.IN3 +memory_data[10] => Selector7.IN0 +memory_data[11] => Mux5.IN2 +memory_data[11] => Mux45.IN3 +memory_data[11] => Selector6.IN0 +memory_data[12] => Mux4.IN2 +memory_data[12] => Mux44.IN3 +memory_data[12] => Selector5.IN0 +memory_data[13] => Mux3.IN2 +memory_data[13] => Mux43.IN3 +memory_data[13] => Selector4.IN0 +memory_data[14] => Mux2.IN2 +memory_data[14] => Mux42.IN3 +memory_data[14] => Selector3.IN0 +memory_data[15] => Mux1.IN2 +memory_data[15] => mem_load_result.IN0 +memory_data[15] => Mux41.IN3 +memory_data[15] => Mux0.IN2 +memory_data[15] => Selector2.IN0 +memory_data[16] => Mux8.IN1 +memory_data[16] => Selector17.IN3 +memory_data[16] => Mux40.IN3 +memory_data[17] => Mux7.IN1 +memory_data[17] => Selector16.IN3 +memory_data[17] => Mux39.IN3 +memory_data[18] => Mux6.IN1 +memory_data[18] => Selector15.IN3 +memory_data[18] => Mux38.IN3 +memory_data[19] => Mux5.IN1 +memory_data[19] => Selector14.IN3 +memory_data[19] => Mux37.IN3 +memory_data[20] => Mux4.IN1 +memory_data[20] => Selector13.IN3 +memory_data[20] => Mux36.IN3 +memory_data[21] => Mux3.IN1 +memory_data[21] => Selector12.IN3 +memory_data[21] => Mux35.IN3 +memory_data[22] => Mux2.IN1 +memory_data[22] => Selector11.IN3 +memory_data[22] => Mux34.IN3 +memory_data[23] => Mux1.IN1 +memory_data[23] => Selector10.IN3 +memory_data[23] => Mux33.IN3 +memory_data[23] => Mux0.IN1 +memory_data[24] => Mux8.IN0 +memory_data[24] => Selector9.IN3 +memory_data[24] => Mux32.IN3 +memory_data[25] => Mux7.IN0 +memory_data[25] => Selector8.IN3 +memory_data[25] => Mux31.IN3 +memory_data[26] => Mux6.IN0 +memory_data[26] => Selector7.IN3 +memory_data[26] => Mux30.IN3 +memory_data[27] => Mux5.IN0 +memory_data[27] => Selector6.IN3 +memory_data[27] => Mux29.IN3 +memory_data[28] => Mux4.IN0 +memory_data[28] => Selector5.IN3 +memory_data[28] => Mux28.IN3 +memory_data[29] => Mux3.IN0 +memory_data[29] => Selector4.IN3 +memory_data[29] => Mux27.IN3 +memory_data[30] => Mux2.IN0 +memory_data[30] => Selector3.IN3 +memory_data[30] => Mux26.IN3 +memory_data[31] => Mux1.IN0 +memory_data[31] => mem_load_result.IN0 +memory_data[31] => Selector2.IN3 +memory_data[31] => Mux25.IN3 +memory_data[31] => Mux0.IN0 +memory_address[0] => Mux0.IN5 +memory_address[0] => Mux1.IN5 +memory_address[0] => Mux2.IN5 +memory_address[0] => Mux3.IN5 +memory_address[0] => Mux4.IN5 +memory_address[0] => Mux5.IN5 +memory_address[0] => Mux6.IN5 +memory_address[0] => Mux7.IN5 +memory_address[0] => Mux8.IN5 +memory_address[0] => Decoder0.IN1 +memory_address[0] => Equal1.IN3 +memory_address[1] => Mux0.IN4 +memory_address[1] => Mux1.IN4 +memory_address[1] => Mux2.IN4 +memory_address[1] => Mux3.IN4 +memory_address[1] => Mux4.IN4 +memory_address[1] => Mux5.IN4 +memory_address[1] => Mux6.IN4 +memory_address[1] => Mux7.IN4 +memory_address[1] => Mux8.IN4 +memory_address[1] => Decoder0.IN0 +memory_address[1] => Equal1.IN2 +memory_address[2] => ~NO_FANOUT~ +memory_address[3] => ~NO_FANOUT~ +memory_address[4] => ~NO_FANOUT~ +memory_address[5] => ~NO_FANOUT~ +memory_address[6] => ~NO_FANOUT~ +memory_address[7] => ~NO_FANOUT~ +memory_address[8] => ~NO_FANOUT~ +memory_address[9] => ~NO_FANOUT~ +memory_address[10] => ~NO_FANOUT~ +memory_address[11] => ~NO_FANOUT~ +memory_address[12] => ~NO_FANOUT~ +memory_address[13] => ~NO_FANOUT~ +memory_address[14] => ~NO_FANOUT~ +memory_address[15] => ~NO_FANOUT~ +memory_address[16] => ~NO_FANOUT~ +memory_address[17] => ~NO_FANOUT~ +memory_address[18] => ~NO_FANOUT~ +memory_address[19] => ~NO_FANOUT~ +memory_address[20] => ~NO_FANOUT~ +memory_address[21] => ~NO_FANOUT~ +memory_address[22] => ~NO_FANOUT~ +memory_address[23] => ~NO_FANOUT~ +memory_address[24] => ~NO_FANOUT~ +memory_address[25] => ~NO_FANOUT~ +memory_address[26] => ~NO_FANOUT~ +memory_address[27] => ~NO_FANOUT~ +memory_address[28] => ~NO_FANOUT~ +memory_address[29] => ~NO_FANOUT~ +memory_address[30] => ~NO_FANOUT~ +memory_address[31] => ~NO_FANOUT~ +funct3[0] => Mux9.IN2 +funct3[0] => Mux10.IN2 +funct3[0] => Mux11.IN2 +funct3[0] => Mux12.IN2 +funct3[0] => Mux13.IN2 +funct3[0] => Mux14.IN2 +funct3[0] => Mux15.IN2 +funct3[0] => Mux16.IN2 +funct3[0] => Mux17.IN2 +funct3[0] => Mux18.IN2 +funct3[0] => Mux19.IN2 +funct3[0] => Mux20.IN2 +funct3[0] => Mux21.IN2 +funct3[0] => Mux22.IN2 +funct3[0] => Mux23.IN2 +funct3[0] => Mux24.IN2 +funct3[0] => Mux25.IN5 +funct3[0] => Mux26.IN5 +funct3[0] => Mux27.IN5 +funct3[0] => Mux28.IN5 +funct3[0] => Mux29.IN5 +funct3[0] => Mux30.IN5 +funct3[0] => Mux31.IN5 +funct3[0] => Mux32.IN5 +funct3[0] => Mux33.IN5 +funct3[0] => Mux34.IN5 +funct3[0] => Mux35.IN5 +funct3[0] => Mux36.IN5 +funct3[0] => Mux37.IN5 +funct3[0] => Mux38.IN5 +funct3[0] => Mux39.IN5 +funct3[0] => Mux40.IN5 +funct3[0] => Mux41.IN5 +funct3[0] => Mux42.IN5 +funct3[0] => Mux43.IN5 +funct3[0] => Mux44.IN5 +funct3[0] => Mux45.IN5 +funct3[0] => Mux46.IN5 +funct3[0] => Mux47.IN5 +funct3[0] => Mux48.IN5 +funct3[0] => Mux49.IN5 +funct3[0] => Mux50.IN5 +funct3[0] => Mux51.IN5 +funct3[0] => Mux52.IN5 +funct3[0] => Mux53.IN5 +funct3[0] => Mux54.IN5 +funct3[0] => Mux55.IN5 +funct3[0] => Mux56.IN5 +funct3[0] => Mux57.IN5 +funct3[0] => Mux58.IN5 +funct3[0] => Mux59.IN5 +funct3[0] => Mux60.IN5 +funct3[1] => Mux9.IN1 +funct3[1] => Mux10.IN1 +funct3[1] => Mux11.IN1 +funct3[1] => Mux12.IN1 +funct3[1] => Mux13.IN1 +funct3[1] => Mux14.IN1 +funct3[1] => Mux15.IN1 +funct3[1] => Mux16.IN1 +funct3[1] => __tmp_MemData.OUTPUTSELECT +funct3[1] => __tmp_MemData.OUTPUTSELECT +funct3[1] => __tmp_MemData.OUTPUTSELECT +funct3[1] => __tmp_MemData.OUTPUTSELECT +funct3[1] => __tmp_MemData.OUTPUTSELECT +funct3[1] => __tmp_MemData.OUTPUTSELECT +funct3[1] => __tmp_MemData.OUTPUTSELECT +funct3[1] => __tmp_MemData.OUTPUTSELECT +funct3[1] => Mux17.IN1 +funct3[1] => Mux18.IN1 +funct3[1] => Mux19.IN1 +funct3[1] => Mux20.IN1 +funct3[1] => Mux21.IN1 +funct3[1] => Mux22.IN1 +funct3[1] => Mux23.IN1 +funct3[1] => Mux24.IN1 +funct3[1] => Mux25.IN4 +funct3[1] => Mux26.IN4 +funct3[1] => Mux27.IN4 +funct3[1] => Mux28.IN4 +funct3[1] => Mux29.IN4 +funct3[1] => Mux30.IN4 +funct3[1] => Mux31.IN4 +funct3[1] => Mux32.IN4 +funct3[1] => Mux33.IN4 +funct3[1] => Mux34.IN4 +funct3[1] => Mux35.IN4 +funct3[1] => Mux36.IN4 +funct3[1] => Mux37.IN4 +funct3[1] => Mux38.IN4 +funct3[1] => Mux39.IN4 +funct3[1] => Mux40.IN4 +funct3[1] => Mux41.IN4 +funct3[1] => Mux42.IN4 +funct3[1] => Mux43.IN4 +funct3[1] => Mux44.IN4 +funct3[1] => Mux45.IN4 +funct3[1] => Mux46.IN4 +funct3[1] => Mux47.IN4 +funct3[1] => Mux48.IN4 +funct3[1] => Mux49.IN4 +funct3[1] => Mux50.IN4 +funct3[1] => Mux51.IN4 +funct3[1] => Mux52.IN4 +funct3[1] => Mux53.IN4 +funct3[1] => Mux54.IN4 +funct3[1] => Mux55.IN4 +funct3[1] => Mux56.IN4 +funct3[1] => Mux57.IN4 +funct3[1] => Mux58.IN4 +funct3[1] => Mux59.IN4 +funct3[1] => Mux60.IN4 +funct3[2] => mem_load_result.IN1 +funct3[2] => mem_load_result.IN1 +funct3[2] => mem_load_result.IN1 +dataB[0] => Mux16.IN5 +dataB[0] => __tmp_MemData.DATAA +dataB[0] => Mux24.IN5 +dataB[0] => __tmp_MemData[0].DATAIN +dataB[1] => Mux15.IN5 +dataB[1] => __tmp_MemData.DATAA +dataB[1] => Mux23.IN5 +dataB[1] => __tmp_MemData[1].DATAIN +dataB[2] => Mux14.IN5 +dataB[2] => __tmp_MemData.DATAA +dataB[2] => Mux22.IN5 +dataB[2] => __tmp_MemData[2].DATAIN +dataB[3] => Mux13.IN5 +dataB[3] => __tmp_MemData.DATAA +dataB[3] => Mux21.IN5 +dataB[3] => __tmp_MemData[3].DATAIN +dataB[4] => Mux12.IN5 +dataB[4] => __tmp_MemData.DATAA +dataB[4] => Mux20.IN5 +dataB[4] => __tmp_MemData[4].DATAIN +dataB[5] => Mux11.IN5 +dataB[5] => __tmp_MemData.DATAA +dataB[5] => Mux19.IN5 +dataB[5] => __tmp_MemData[5].DATAIN +dataB[6] => Mux10.IN5 +dataB[6] => __tmp_MemData.DATAA +dataB[6] => Mux18.IN5 +dataB[6] => __tmp_MemData[6].DATAIN +dataB[7] => Mux9.IN5 +dataB[7] => __tmp_MemData.DATAA +dataB[7] => Mux17.IN5 +dataB[7] => __tmp_MemData[7].DATAIN +dataB[8] => Mux16.IN4 +dataB[8] => Mux24.IN3 +dataB[8] => Mux24.IN4 +dataB[9] => Mux15.IN4 +dataB[9] => Mux23.IN3 +dataB[9] => Mux23.IN4 +dataB[10] => Mux14.IN4 +dataB[10] => Mux22.IN3 +dataB[10] => Mux22.IN4 +dataB[11] => Mux13.IN4 +dataB[11] => Mux21.IN3 +dataB[11] => Mux21.IN4 +dataB[12] => Mux12.IN4 +dataB[12] => Mux20.IN3 +dataB[12] => Mux20.IN4 +dataB[13] => Mux11.IN4 +dataB[13] => Mux19.IN3 +dataB[13] => Mux19.IN4 +dataB[14] => Mux10.IN4 +dataB[14] => Mux18.IN3 +dataB[14] => Mux18.IN4 +dataB[15] => Mux9.IN4 +dataB[15] => Mux17.IN3 +dataB[15] => Mux17.IN4 +dataB[16] => __tmp_MemData.DATAB +dataB[17] => __tmp_MemData.DATAB +dataB[18] => __tmp_MemData.DATAB +dataB[19] => __tmp_MemData.DATAB +dataB[20] => __tmp_MemData.DATAB +dataB[21] => __tmp_MemData.DATAB +dataB[22] => __tmp_MemData.DATAB +dataB[23] => __tmp_MemData.DATAB +dataB[24] => Mux16.IN3 +dataB[25] => Mux15.IN3 +dataB[26] => Mux14.IN3 +dataB[27] => Mux13.IN3 +dataB[28] => Mux12.IN3 +dataB[29] => Mux11.IN3 +dataB[30] => Mux10.IN3 +dataB[31] => Mux9.IN3 +mem_load_result[0] <= Mux56.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[1] <= Mux55.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[2] <= Mux54.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[3] <= Mux53.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[4] <= Mux52.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[5] <= Mux51.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[6] <= Mux50.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[7] <= Mux49.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[8] <= Mux48.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[9] <= Mux47.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[10] <= Mux46.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[11] <= Mux45.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[12] <= Mux44.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[13] <= Mux43.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[14] <= Mux42.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[15] <= Mux41.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[16] <= Mux40.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[17] <= Mux39.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[18] <= Mux38.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[19] <= Mux37.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[20] <= Mux36.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[21] <= Mux35.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[22] <= Mux34.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[23] <= Mux33.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[24] <= Mux32.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[25] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[26] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[27] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[28] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[29] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[30] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE +mem_load_result[31] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE +MemWriteByteAddress[0] <= Mux60.DB_MAX_OUTPUT_PORT_TYPE +MemWriteByteAddress[1] <= Mux59.DB_MAX_OUTPUT_PORT_TYPE +MemWriteByteAddress[2] <= Mux58.DB_MAX_OUTPUT_PORT_TYPE +MemWriteByteAddress[3] <= Mux57.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[0] <= dataB[0].DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[1] <= dataB[1].DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[2] <= dataB[2].DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[3] <= dataB[3].DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[4] <= dataB[4].DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[5] <= dataB[5].DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[6] <= dataB[6].DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[7] <= dataB[7].DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[8] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[9] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[10] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[11] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[12] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[13] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[14] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[15] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[16] <= __tmp_MemData.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[17] <= __tmp_MemData.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[18] <= __tmp_MemData.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[19] <= __tmp_MemData.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[20] <= __tmp_MemData.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[21] <= __tmp_MemData.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[22] <= __tmp_MemData.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[23] <= __tmp_MemData.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[24] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[25] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[26] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[27] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[28] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[29] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[30] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE +__tmp_MemData[31] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE + + +|top|utoss_riscv:core|Instruction_Decode:instruction_decode +instr[0] => Decoder0.IN6 +instr[0] => Decoder1.IN6 +instr[0] => opcode[0].DATAIN +instr[0] => Equal0.IN3 +instr[0] => Equal1.IN2 +instr[0] => Equal2.IN1 +instr[0] => Equal3.IN2 +instr[0] => Equal4.IN3 +instr[0] => Equal5.IN5 +instr[0] => Equal6.IN3 +instr[0] => Equal7.IN4 +instr[0] => Equal8.IN4 +instr[1] => Decoder0.IN5 +instr[1] => Decoder1.IN5 +instr[1] => opcode[1].DATAIN +instr[1] => Equal0.IN2 +instr[1] => Equal1.IN1 +instr[1] => Equal2.IN0 +instr[1] => Equal3.IN1 +instr[1] => Equal4.IN2 +instr[1] => Equal5.IN4 +instr[1] => Equal6.IN2 +instr[1] => Equal7.IN3 +instr[1] => Equal8.IN3 +instr[2] => Decoder0.IN4 +instr[2] => Decoder1.IN4 +instr[2] => opcode[2].DATAIN +instr[2] => Equal0.IN6 +instr[2] => Equal1.IN6 +instr[2] => Equal2.IN6 +instr[2] => Equal3.IN6 +instr[2] => Equal4.IN6 +instr[2] => Equal5.IN3 +instr[2] => Equal6.IN1 +instr[2] => Equal7.IN2 +instr[2] => Equal8.IN2 +instr[3] => Decoder0.IN3 +instr[3] => Decoder1.IN3 +instr[3] => opcode[3].DATAIN +instr[3] => Equal0.IN5 +instr[3] => Equal1.IN5 +instr[3] => Equal2.IN5 +instr[3] => Equal3.IN5 +instr[3] => Equal4.IN5 +instr[3] => Equal5.IN2 +instr[3] => Equal6.IN6 +instr[3] => Equal7.IN6 +instr[3] => Equal8.IN6 +instr[4] => Decoder0.IN2 +instr[4] => Decoder1.IN2 +instr[4] => opcode[4].DATAIN +instr[4] => Equal0.IN1 +instr[4] => Equal1.IN0 +instr[4] => Equal2.IN4 +instr[4] => Equal3.IN4 +instr[4] => Equal4.IN4 +instr[4] => Equal5.IN6 +instr[4] => Equal6.IN0 +instr[4] => Equal7.IN1 +instr[4] => Equal8.IN5 +instr[5] => Decoder0.IN1 +instr[5] => Decoder1.IN1 +instr[5] => opcode[5].DATAIN +instr[5] => Equal0.IN0 +instr[5] => Equal1.IN4 +instr[5] => Equal2.IN3 +instr[5] => Equal3.IN0 +instr[5] => Equal4.IN1 +instr[5] => Equal5.IN1 +instr[5] => Equal6.IN5 +instr[5] => Equal7.IN0 +instr[5] => Equal8.IN1 +instr[6] => Decoder0.IN0 +instr[6] => Decoder1.IN0 +instr[6] => opcode[6].DATAIN +instr[6] => Equal0.IN4 +instr[6] => Equal1.IN3 +instr[6] => Equal2.IN2 +instr[6] => Equal3.IN3 +instr[6] => Equal4.IN0 +instr[6] => Equal5.IN0 +instr[6] => Equal6.IN4 +instr[6] => Equal7.IN5 +instr[6] => Equal8.IN0 +instr[7] => rd.DATAB +instr[7] => rd.DATAB +instr[7] => rd.DATAB +instr[7] => rd.DATAB +instr[7] => rd.DATAB +instr[7] => Selector11.IN7 +instr[7] => Selector14.IN9 +instr[8] => rd.DATAB +instr[8] => rd.DATAB +instr[8] => rd.DATAB +instr[8] => rd.DATAB +instr[8] => rd.DATAB +instr[8] => Selector9.IN7 +instr[9] => rd.DATAB +instr[9] => rd.DATAB +instr[9] => rd.DATAB +instr[9] => rd.DATAB +instr[9] => rd.DATAB +instr[9] => Selector8.IN7 +instr[10] => rd.DATAB +instr[10] => rd.DATAB +instr[10] => rd.DATAB +instr[10] => rd.DATAB +instr[10] => rd.DATAB +instr[10] => Selector7.IN7 +instr[11] => rd.DATAB +instr[11] => rd.DATAB +instr[11] => rd.DATAB +instr[11] => rd.DATAB +instr[11] => rd.DATAB +instr[11] => Selector6.IN7 +instr[12] => funct3.DATAB +instr[12] => funct3.DATAB +instr[12] => Selector16.IN3 +instr[13] => funct3.DATAB +instr[13] => funct3.DATAB +instr[13] => Selector17.IN3 +instr[14] => funct3.DATAB +instr[14] => funct3.DATAB +instr[14] => Selector18.IN3 +instr[15] => rs1.DATAB +instr[15] => rs1.DATAB +instr[15] => rs1.DATAB +instr[15] => rs1.DATAB +instr[15] => Selector19.IN3 +instr[16] => rs1.DATAB +instr[16] => rs1.DATAB +instr[16] => rs1.DATAB +instr[16] => rs1.DATAB +instr[16] => Selector20.IN3 +instr[17] => rs1.DATAB +instr[17] => rs1.DATAB +instr[17] => rs1.DATAB +instr[17] => rs1.DATAB +instr[17] => Selector21.IN3 +instr[18] => rs1.DATAB +instr[18] => rs1.DATAB +instr[18] => rs1.DATAB +instr[18] => rs1.DATAB +instr[18] => Selector22.IN3 +instr[19] => rs1.DATAB +instr[19] => rs1.DATAB +instr[19] => rs1.DATAB +instr[19] => rs1.DATAB +instr[19] => Selector23.IN3 +instr[20] => rs2.DATAB +instr[20] => rs2.DATAB +instr[20] => Selector11.IN6 +instr[20] => Selector14.IN8 +instr[20] => Selector25.IN3 +instr[21] => rs2.DATAB +instr[21] => rs2.DATAB +instr[21] => Selector9.IN6 +instr[21] => Selector26.IN3 +instr[22] => rs2.DATAB +instr[22] => rs2.DATAB +instr[22] => Selector8.IN6 +instr[22] => Selector27.IN3 +instr[23] => rs2.DATAB +instr[23] => rs2.DATAB +instr[23] => Selector7.IN6 +instr[23] => Selector28.IN3 +instr[24] => rs2.DATAB +instr[24] => rs2.DATAB +instr[24] => Selector6.IN6 +instr[24] => Selector29.IN3 +instr[25] => funct7.DATAB +instr[25] => Selector4.IN3 +instr[25] => Selector30.IN3 +instr[26] => funct7.DATAB +instr[26] => Selector3.IN3 +instr[26] => Selector31.IN3 +instr[27] => funct7.DATAB +instr[27] => Selector2.IN3 +instr[27] => Selector32.IN3 +instr[28] => funct7.DATAB +instr[28] => Selector1.IN3 +instr[28] => Selector33.IN3 +instr[29] => funct7.DATAB +instr[29] => Selector0.IN3 +instr[29] => Selector34.IN3 +instr[30] => funct7.DATAB +instr[30] => Selector12.IN3 +instr[30] => Selector35.IN3 +instr[31] => funct7.DATAB +instr[31] => Selector14.IN7 +instr[31] => Selector16.IN2 +instr[31] => Selector17.IN2 +instr[31] => Selector18.IN2 +instr[31] => Selector19.IN2 +instr[31] => Selector20.IN2 +instr[31] => Selector21.IN2 +instr[31] => Selector22.IN2 +instr[31] => Selector23.IN2 +instr[31] => Selector25.IN2 +instr[31] => Selector26.IN2 +instr[31] => Selector27.IN2 +instr[31] => Selector28.IN2 +instr[31] => Selector29.IN2 +instr[31] => Selector30.IN2 +instr[31] => Selector31.IN2 +instr[31] => Selector32.IN2 +instr[31] => Selector33.IN2 +instr[31] => Selector34.IN2 +instr[31] => Selector35.IN2 +instr[31] => imm_ext[31]$latch.DATAIN +opcode[0] <= instr[0].DB_MAX_OUTPUT_PORT_TYPE +opcode[1] <= instr[1].DB_MAX_OUTPUT_PORT_TYPE +opcode[2] <= instr[2].DB_MAX_OUTPUT_PORT_TYPE +opcode[3] <= instr[3].DB_MAX_OUTPUT_PORT_TYPE +opcode[4] <= instr[4].DB_MAX_OUTPUT_PORT_TYPE +opcode[5] <= instr[5].DB_MAX_OUTPUT_PORT_TYPE +opcode[6] <= instr[6].DB_MAX_OUTPUT_PORT_TYPE +ALUControl[0] <= ALUdecoder:instanceALUDec.alu_control[0] +ALUControl[1] <= ALUdecoder:instanceALUDec.alu_control[1] +ALUControl[2] <= ALUdecoder:instanceALUDec.alu_control[2] +ALUControl[3] <= ALUdecoder:instanceALUDec.alu_control[3] +imm_ext[0] <= imm_ext[0]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[1] <= imm_ext[1]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[2] <= imm_ext[2]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[3] <= imm_ext[3]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[4] <= imm_ext[4]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[5] <= imm_ext[5]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[6] <= imm_ext[6]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[7] <= imm_ext[7]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[8] <= imm_ext[8]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[9] <= imm_ext[9]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[10] <= imm_ext[10]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[11] <= imm_ext[11]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[12] <= imm_ext[12]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[13] <= imm_ext[13]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[14] <= imm_ext[14]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[15] <= imm_ext[15]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[16] <= imm_ext[16]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[17] <= imm_ext[17]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[18] <= imm_ext[18]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[19] <= imm_ext[19]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[20] <= imm_ext[20]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[21] <= imm_ext[21]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[22] <= imm_ext[22]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[23] <= imm_ext[23]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[24] <= imm_ext[24]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[25] <= imm_ext[25]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[26] <= imm_ext[26]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[27] <= imm_ext[27]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[28] <= imm_ext[28]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[29] <= imm_ext[29]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[30] <= imm_ext[30]$latch.DB_MAX_OUTPUT_PORT_TYPE +imm_ext[31] <= imm_ext[31]$latch.DB_MAX_OUTPUT_PORT_TYPE +funct3[0] <= funct3.DB_MAX_OUTPUT_PORT_TYPE +funct3[1] <= funct3.DB_MAX_OUTPUT_PORT_TYPE +funct3[2] <= funct3.DB_MAX_OUTPUT_PORT_TYPE +funct7[0] <= funct7.DB_MAX_OUTPUT_PORT_TYPE +funct7[1] <= funct7.DB_MAX_OUTPUT_PORT_TYPE +funct7[2] <= funct7.DB_MAX_OUTPUT_PORT_TYPE +funct7[3] <= funct7.DB_MAX_OUTPUT_PORT_TYPE +funct7[4] <= funct7.DB_MAX_OUTPUT_PORT_TYPE +funct7[5] <= funct7.DB_MAX_OUTPUT_PORT_TYPE +funct7[6] <= funct7.DB_MAX_OUTPUT_PORT_TYPE +rd[0] <= rd.DB_MAX_OUTPUT_PORT_TYPE +rd[1] <= rd.DB_MAX_OUTPUT_PORT_TYPE +rd[2] <= rd.DB_MAX_OUTPUT_PORT_TYPE +rd[3] <= rd.DB_MAX_OUTPUT_PORT_TYPE +rd[4] <= rd.DB_MAX_OUTPUT_PORT_TYPE +rs1[0] <= rs1.DB_MAX_OUTPUT_PORT_TYPE +rs1[1] <= rs1.DB_MAX_OUTPUT_PORT_TYPE +rs1[2] <= rs1.DB_MAX_OUTPUT_PORT_TYPE +rs1[3] <= rs1.DB_MAX_OUTPUT_PORT_TYPE +rs1[4] <= rs1.DB_MAX_OUTPUT_PORT_TYPE +rs2[0] <= rs2.DB_MAX_OUTPUT_PORT_TYPE +rs2[1] <= rs2.DB_MAX_OUTPUT_PORT_TYPE +rs2[2] <= rs2.DB_MAX_OUTPUT_PORT_TYPE +rs2[3] <= rs2.DB_MAX_OUTPUT_PORT_TYPE +rs2[4] <= rs2.DB_MAX_OUTPUT_PORT_TYPE + + +|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec +funct3[0] => Decoder0.IN1 +funct3[0] => Decoder1.IN2 +funct3[0] => Mux3.IN10 +funct3[0] => Mux5.IN10 +funct3[0] => Mux2.IN10 +funct3[0] => Mux1.IN10 +funct3[0] => Mux0.IN10 +funct3[0] => Mux4.IN10 +funct3[0] => Mux6.IN10 +funct3[1] => Decoder1.IN1 +funct3[1] => Mux3.IN9 +funct3[1] => Mux5.IN9 +funct3[1] => Mux2.IN9 +funct3[1] => Mux1.IN9 +funct3[1] => Mux0.IN9 +funct3[1] => Mux4.IN9 +funct3[1] => Mux6.IN9 +funct3[2] => Decoder0.IN0 +funct3[2] => Decoder1.IN0 +funct3[2] => Mux3.IN8 +funct3[2] => Mux5.IN8 +funct3[2] => Mux2.IN8 +funct3[2] => Mux1.IN8 +funct3[2] => Mux0.IN8 +funct3[2] => Mux4.IN8 +funct3[2] => Mux6.IN8 +funct7[0] => Equal0.IN6 +funct7[0] => Equal1.IN6 +funct7[1] => Equal0.IN5 +funct7[1] => Equal1.IN5 +funct7[2] => Equal0.IN4 +funct7[2] => Equal1.IN4 +funct7[3] => Equal0.IN3 +funct7[3] => Equal1.IN3 +funct7[4] => Equal0.IN2 +funct7[4] => Equal1.IN2 +funct7[5] => Equal0.IN1 +funct7[5] => Equal1.IN0 +funct7[6] => Equal0.IN0 +funct7[6] => Equal1.IN1 +alu_op[0] => Equal2.IN3 +alu_op[0] => Equal3.IN3 +alu_op[0] => Equal4.IN3 +alu_op[0] => Equal5.IN3 +alu_op[1] => Equal2.IN2 +alu_op[1] => Equal3.IN2 +alu_op[1] => Equal4.IN2 +alu_op[1] => Equal5.IN2 +alu_control[0] <= alu_control[0]$latch.DB_MAX_OUTPUT_PORT_TYPE +alu_control[1] <= alu_control[1]$latch.DB_MAX_OUTPUT_PORT_TYPE +alu_control[2] <= alu_control[2]$latch.DB_MAX_OUTPUT_PORT_TYPE +alu_control[3] <= alu_control[3]$latch.DB_MAX_OUTPUT_PORT_TYPE + + +|top|utoss_riscv:core|registerFile:RegFile +Addr1[0] => Mux0.IN4 +Addr1[0] => Mux1.IN4 +Addr1[0] => Mux2.IN4 +Addr1[0] => Mux3.IN4 +Addr1[0] => Mux4.IN4 +Addr1[0] => Mux5.IN4 +Addr1[0] => Mux6.IN4 +Addr1[0] => Mux7.IN4 +Addr1[0] => Mux8.IN4 +Addr1[0] => Mux9.IN4 +Addr1[0] => Mux10.IN4 +Addr1[0] => Mux11.IN4 +Addr1[0] => Mux12.IN4 +Addr1[0] => Mux13.IN4 +Addr1[0] => Mux14.IN4 +Addr1[0] => Mux15.IN4 +Addr1[0] => Mux16.IN4 +Addr1[0] => Mux17.IN4 +Addr1[0] => Mux18.IN4 +Addr1[0] => Mux19.IN4 +Addr1[0] => Mux20.IN4 +Addr1[0] => Mux21.IN4 +Addr1[0] => Mux22.IN4 +Addr1[0] => Mux23.IN4 +Addr1[0] => Mux24.IN4 +Addr1[0] => Mux25.IN4 +Addr1[0] => Mux26.IN4 +Addr1[0] => Mux27.IN4 +Addr1[0] => Mux28.IN4 +Addr1[0] => Mux29.IN4 +Addr1[0] => Mux30.IN4 +Addr1[0] => Mux31.IN4 +Addr1[0] => Equal0.IN4 +Addr1[1] => Mux0.IN3 +Addr1[1] => Mux1.IN3 +Addr1[1] => Mux2.IN3 +Addr1[1] => Mux3.IN3 +Addr1[1] => Mux4.IN3 +Addr1[1] => Mux5.IN3 +Addr1[1] => Mux6.IN3 +Addr1[1] => Mux7.IN3 +Addr1[1] => Mux8.IN3 +Addr1[1] => Mux9.IN3 +Addr1[1] => Mux10.IN3 +Addr1[1] => Mux11.IN3 +Addr1[1] => Mux12.IN3 +Addr1[1] => Mux13.IN3 +Addr1[1] => Mux14.IN3 +Addr1[1] => Mux15.IN3 +Addr1[1] => Mux16.IN3 +Addr1[1] => Mux17.IN3 +Addr1[1] => Mux18.IN3 +Addr1[1] => Mux19.IN3 +Addr1[1] => Mux20.IN3 +Addr1[1] => Mux21.IN3 +Addr1[1] => Mux22.IN3 +Addr1[1] => Mux23.IN3 +Addr1[1] => Mux24.IN3 +Addr1[1] => Mux25.IN3 +Addr1[1] => Mux26.IN3 +Addr1[1] => Mux27.IN3 +Addr1[1] => Mux28.IN3 +Addr1[1] => Mux29.IN3 +Addr1[1] => Mux30.IN3 +Addr1[1] => Mux31.IN3 +Addr1[1] => Equal0.IN3 +Addr1[2] => Mux0.IN2 +Addr1[2] => Mux1.IN2 +Addr1[2] => Mux2.IN2 +Addr1[2] => Mux3.IN2 +Addr1[2] => Mux4.IN2 +Addr1[2] => Mux5.IN2 +Addr1[2] => Mux6.IN2 +Addr1[2] => Mux7.IN2 +Addr1[2] => Mux8.IN2 +Addr1[2] => Mux9.IN2 +Addr1[2] => Mux10.IN2 +Addr1[2] => Mux11.IN2 +Addr1[2] => Mux12.IN2 +Addr1[2] => Mux13.IN2 +Addr1[2] => Mux14.IN2 +Addr1[2] => Mux15.IN2 +Addr1[2] => Mux16.IN2 +Addr1[2] => Mux17.IN2 +Addr1[2] => Mux18.IN2 +Addr1[2] => Mux19.IN2 +Addr1[2] => Mux20.IN2 +Addr1[2] => Mux21.IN2 +Addr1[2] => Mux22.IN2 +Addr1[2] => Mux23.IN2 +Addr1[2] => Mux24.IN2 +Addr1[2] => Mux25.IN2 +Addr1[2] => Mux26.IN2 +Addr1[2] => Mux27.IN2 +Addr1[2] => Mux28.IN2 +Addr1[2] => Mux29.IN2 +Addr1[2] => Mux30.IN2 +Addr1[2] => Mux31.IN2 +Addr1[2] => Equal0.IN2 +Addr1[3] => Mux0.IN1 +Addr1[3] => Mux1.IN1 +Addr1[3] => Mux2.IN1 +Addr1[3] => Mux3.IN1 +Addr1[3] => Mux4.IN1 +Addr1[3] => Mux5.IN1 +Addr1[3] => Mux6.IN1 +Addr1[3] => Mux7.IN1 +Addr1[3] => Mux8.IN1 +Addr1[3] => Mux9.IN1 +Addr1[3] => Mux10.IN1 +Addr1[3] => Mux11.IN1 +Addr1[3] => Mux12.IN1 +Addr1[3] => Mux13.IN1 +Addr1[3] => Mux14.IN1 +Addr1[3] => Mux15.IN1 +Addr1[3] => Mux16.IN1 +Addr1[3] => Mux17.IN1 +Addr1[3] => Mux18.IN1 +Addr1[3] => Mux19.IN1 +Addr1[3] => Mux20.IN1 +Addr1[3] => Mux21.IN1 +Addr1[3] => Mux22.IN1 +Addr1[3] => Mux23.IN1 +Addr1[3] => Mux24.IN1 +Addr1[3] => Mux25.IN1 +Addr1[3] => Mux26.IN1 +Addr1[3] => Mux27.IN1 +Addr1[3] => Mux28.IN1 +Addr1[3] => Mux29.IN1 +Addr1[3] => Mux30.IN1 +Addr1[3] => Mux31.IN1 +Addr1[3] => Equal0.IN1 +Addr1[4] => Mux0.IN0 +Addr1[4] => Mux1.IN0 +Addr1[4] => Mux2.IN0 +Addr1[4] => Mux3.IN0 +Addr1[4] => Mux4.IN0 +Addr1[4] => Mux5.IN0 +Addr1[4] => Mux6.IN0 +Addr1[4] => Mux7.IN0 +Addr1[4] => Mux8.IN0 +Addr1[4] => Mux9.IN0 +Addr1[4] => Mux10.IN0 +Addr1[4] => Mux11.IN0 +Addr1[4] => Mux12.IN0 +Addr1[4] => Mux13.IN0 +Addr1[4] => Mux14.IN0 +Addr1[4] => Mux15.IN0 +Addr1[4] => Mux16.IN0 +Addr1[4] => Mux17.IN0 +Addr1[4] => Mux18.IN0 +Addr1[4] => Mux19.IN0 +Addr1[4] => Mux20.IN0 +Addr1[4] => Mux21.IN0 +Addr1[4] => Mux22.IN0 +Addr1[4] => Mux23.IN0 +Addr1[4] => Mux24.IN0 +Addr1[4] => Mux25.IN0 +Addr1[4] => Mux26.IN0 +Addr1[4] => Mux27.IN0 +Addr1[4] => Mux28.IN0 +Addr1[4] => Mux29.IN0 +Addr1[4] => Mux30.IN0 +Addr1[4] => Mux31.IN0 +Addr1[4] => Equal0.IN0 +Addr2[0] => Mux32.IN4 +Addr2[0] => Mux33.IN4 +Addr2[0] => Mux34.IN4 +Addr2[0] => Mux35.IN4 +Addr2[0] => Mux36.IN4 +Addr2[0] => Mux37.IN4 +Addr2[0] => Mux38.IN4 +Addr2[0] => Mux39.IN4 +Addr2[0] => Mux40.IN4 +Addr2[0] => Mux41.IN4 +Addr2[0] => Mux42.IN4 +Addr2[0] => Mux43.IN4 +Addr2[0] => Mux44.IN4 +Addr2[0] => Mux45.IN4 +Addr2[0] => Mux46.IN4 +Addr2[0] => Mux47.IN4 +Addr2[0] => Mux48.IN4 +Addr2[0] => Mux49.IN4 +Addr2[0] => Mux50.IN4 +Addr2[0] => Mux51.IN4 +Addr2[0] => Mux52.IN4 +Addr2[0] => Mux53.IN4 +Addr2[0] => Mux54.IN4 +Addr2[0] => Mux55.IN4 +Addr2[0] => Mux56.IN4 +Addr2[0] => Mux57.IN4 +Addr2[0] => Mux58.IN4 +Addr2[0] => Mux59.IN4 +Addr2[0] => Mux60.IN4 +Addr2[0] => Mux61.IN4 +Addr2[0] => Mux62.IN4 +Addr2[0] => Mux63.IN4 +Addr2[0] => Equal1.IN4 +Addr2[1] => Mux32.IN3 +Addr2[1] => Mux33.IN3 +Addr2[1] => Mux34.IN3 +Addr2[1] => Mux35.IN3 +Addr2[1] => Mux36.IN3 +Addr2[1] => Mux37.IN3 +Addr2[1] => Mux38.IN3 +Addr2[1] => Mux39.IN3 +Addr2[1] => Mux40.IN3 +Addr2[1] => Mux41.IN3 +Addr2[1] => Mux42.IN3 +Addr2[1] => Mux43.IN3 +Addr2[1] => Mux44.IN3 +Addr2[1] => Mux45.IN3 +Addr2[1] => Mux46.IN3 +Addr2[1] => Mux47.IN3 +Addr2[1] => Mux48.IN3 +Addr2[1] => Mux49.IN3 +Addr2[1] => Mux50.IN3 +Addr2[1] => Mux51.IN3 +Addr2[1] => Mux52.IN3 +Addr2[1] => Mux53.IN3 +Addr2[1] => Mux54.IN3 +Addr2[1] => Mux55.IN3 +Addr2[1] => Mux56.IN3 +Addr2[1] => Mux57.IN3 +Addr2[1] => Mux58.IN3 +Addr2[1] => Mux59.IN3 +Addr2[1] => Mux60.IN3 +Addr2[1] => Mux61.IN3 +Addr2[1] => Mux62.IN3 +Addr2[1] => Mux63.IN3 +Addr2[1] => Equal1.IN3 +Addr2[2] => Mux32.IN2 +Addr2[2] => Mux33.IN2 +Addr2[2] => Mux34.IN2 +Addr2[2] => Mux35.IN2 +Addr2[2] => Mux36.IN2 +Addr2[2] => Mux37.IN2 +Addr2[2] => Mux38.IN2 +Addr2[2] => Mux39.IN2 +Addr2[2] => Mux40.IN2 +Addr2[2] => Mux41.IN2 +Addr2[2] => Mux42.IN2 +Addr2[2] => Mux43.IN2 +Addr2[2] => Mux44.IN2 +Addr2[2] => Mux45.IN2 +Addr2[2] => Mux46.IN2 +Addr2[2] => Mux47.IN2 +Addr2[2] => Mux48.IN2 +Addr2[2] => Mux49.IN2 +Addr2[2] => Mux50.IN2 +Addr2[2] => Mux51.IN2 +Addr2[2] => Mux52.IN2 +Addr2[2] => Mux53.IN2 +Addr2[2] => Mux54.IN2 +Addr2[2] => Mux55.IN2 +Addr2[2] => Mux56.IN2 +Addr2[2] => Mux57.IN2 +Addr2[2] => Mux58.IN2 +Addr2[2] => Mux59.IN2 +Addr2[2] => Mux60.IN2 +Addr2[2] => Mux61.IN2 +Addr2[2] => Mux62.IN2 +Addr2[2] => Mux63.IN2 +Addr2[2] => Equal1.IN2 +Addr2[3] => Mux32.IN1 +Addr2[3] => Mux33.IN1 +Addr2[3] => Mux34.IN1 +Addr2[3] => Mux35.IN1 +Addr2[3] => Mux36.IN1 +Addr2[3] => Mux37.IN1 +Addr2[3] => Mux38.IN1 +Addr2[3] => Mux39.IN1 +Addr2[3] => Mux40.IN1 +Addr2[3] => Mux41.IN1 +Addr2[3] => Mux42.IN1 +Addr2[3] => Mux43.IN1 +Addr2[3] => Mux44.IN1 +Addr2[3] => Mux45.IN1 +Addr2[3] => Mux46.IN1 +Addr2[3] => Mux47.IN1 +Addr2[3] => Mux48.IN1 +Addr2[3] => Mux49.IN1 +Addr2[3] => Mux50.IN1 +Addr2[3] => Mux51.IN1 +Addr2[3] => Mux52.IN1 +Addr2[3] => Mux53.IN1 +Addr2[3] => Mux54.IN1 +Addr2[3] => Mux55.IN1 +Addr2[3] => Mux56.IN1 +Addr2[3] => Mux57.IN1 +Addr2[3] => Mux58.IN1 +Addr2[3] => Mux59.IN1 +Addr2[3] => Mux60.IN1 +Addr2[3] => Mux61.IN1 +Addr2[3] => Mux62.IN1 +Addr2[3] => Mux63.IN1 +Addr2[3] => Equal1.IN1 +Addr2[4] => Mux32.IN0 +Addr2[4] => Mux33.IN0 +Addr2[4] => Mux34.IN0 +Addr2[4] => Mux35.IN0 +Addr2[4] => Mux36.IN0 +Addr2[4] => Mux37.IN0 +Addr2[4] => Mux38.IN0 +Addr2[4] => Mux39.IN0 +Addr2[4] => Mux40.IN0 +Addr2[4] => Mux41.IN0 +Addr2[4] => Mux42.IN0 +Addr2[4] => Mux43.IN0 +Addr2[4] => Mux44.IN0 +Addr2[4] => Mux45.IN0 +Addr2[4] => Mux46.IN0 +Addr2[4] => Mux47.IN0 +Addr2[4] => Mux48.IN0 +Addr2[4] => Mux49.IN0 +Addr2[4] => Mux50.IN0 +Addr2[4] => Mux51.IN0 +Addr2[4] => Mux52.IN0 +Addr2[4] => Mux53.IN0 +Addr2[4] => Mux54.IN0 +Addr2[4] => Mux55.IN0 +Addr2[4] => Mux56.IN0 +Addr2[4] => Mux57.IN0 +Addr2[4] => Mux58.IN0 +Addr2[4] => Mux59.IN0 +Addr2[4] => Mux60.IN0 +Addr2[4] => Mux61.IN0 +Addr2[4] => Mux62.IN0 +Addr2[4] => Mux63.IN0 +Addr2[4] => Equal1.IN0 +Addr3[0] => Decoder0.IN4 +Addr3[0] => Equal2.IN31 +Addr3[1] => Decoder0.IN3 +Addr3[1] => Equal2.IN30 +Addr3[2] => Decoder0.IN2 +Addr3[2] => Equal2.IN29 +Addr3[3] => Decoder0.IN1 +Addr3[3] => Equal2.IN28 +Addr3[4] => Decoder0.IN0 +Addr3[4] => Equal2.IN27 +clk => RFMem[31][0].CLK +clk => RFMem[31][1].CLK +clk => RFMem[31][2].CLK +clk => RFMem[31][3].CLK +clk => RFMem[31][4].CLK +clk => RFMem[31][5].CLK +clk => RFMem[31][6].CLK +clk => RFMem[31][7].CLK +clk => RFMem[31][8].CLK +clk => RFMem[31][9].CLK +clk => RFMem[31][10].CLK +clk => RFMem[31][11].CLK +clk => RFMem[31][12].CLK +clk => RFMem[31][13].CLK +clk => RFMem[31][14].CLK +clk => RFMem[31][15].CLK +clk => RFMem[31][16].CLK +clk => RFMem[31][17].CLK +clk => RFMem[31][18].CLK +clk => RFMem[31][19].CLK +clk => RFMem[31][20].CLK +clk => RFMem[31][21].CLK +clk => RFMem[31][22].CLK +clk => RFMem[31][23].CLK +clk => RFMem[31][24].CLK +clk => RFMem[31][25].CLK +clk => RFMem[31][26].CLK +clk => RFMem[31][27].CLK +clk => RFMem[31][28].CLK +clk => RFMem[31][29].CLK +clk => RFMem[31][30].CLK +clk => RFMem[31][31].CLK +clk => RFMem[30][0].CLK +clk => RFMem[30][1].CLK +clk => RFMem[30][2].CLK +clk => RFMem[30][3].CLK +clk => RFMem[30][4].CLK +clk => RFMem[30][5].CLK +clk => RFMem[30][6].CLK +clk => RFMem[30][7].CLK +clk => RFMem[30][8].CLK +clk => RFMem[30][9].CLK +clk => RFMem[30][10].CLK +clk => RFMem[30][11].CLK +clk => RFMem[30][12].CLK +clk => RFMem[30][13].CLK +clk => RFMem[30][14].CLK +clk => RFMem[30][15].CLK +clk => RFMem[30][16].CLK +clk => RFMem[30][17].CLK +clk => RFMem[30][18].CLK +clk => RFMem[30][19].CLK +clk => RFMem[30][20].CLK +clk => RFMem[30][21].CLK +clk => RFMem[30][22].CLK +clk => RFMem[30][23].CLK +clk => RFMem[30][24].CLK +clk => RFMem[30][25].CLK +clk => RFMem[30][26].CLK +clk => RFMem[30][27].CLK +clk => RFMem[30][28].CLK +clk => RFMem[30][29].CLK +clk => RFMem[30][30].CLK +clk => RFMem[30][31].CLK +clk => RFMem[29][0].CLK +clk => RFMem[29][1].CLK +clk => RFMem[29][2].CLK +clk => RFMem[29][3].CLK +clk => RFMem[29][4].CLK +clk => RFMem[29][5].CLK +clk => RFMem[29][6].CLK +clk => RFMem[29][7].CLK +clk => RFMem[29][8].CLK +clk => RFMem[29][9].CLK +clk => RFMem[29][10].CLK +clk => RFMem[29][11].CLK +clk => RFMem[29][12].CLK +clk => RFMem[29][13].CLK +clk => RFMem[29][14].CLK +clk => RFMem[29][15].CLK +clk => RFMem[29][16].CLK +clk => RFMem[29][17].CLK +clk => RFMem[29][18].CLK +clk => RFMem[29][19].CLK +clk => RFMem[29][20].CLK +clk => RFMem[29][21].CLK +clk => RFMem[29][22].CLK +clk => RFMem[29][23].CLK +clk => RFMem[29][24].CLK +clk => RFMem[29][25].CLK +clk => RFMem[29][26].CLK +clk => RFMem[29][27].CLK +clk => RFMem[29][28].CLK +clk => RFMem[29][29].CLK +clk => RFMem[29][30].CLK +clk => RFMem[29][31].CLK +clk => RFMem[28][0].CLK +clk => RFMem[28][1].CLK +clk => RFMem[28][2].CLK +clk => RFMem[28][3].CLK +clk => RFMem[28][4].CLK +clk => RFMem[28][5].CLK +clk => RFMem[28][6].CLK +clk => RFMem[28][7].CLK +clk => RFMem[28][8].CLK +clk => RFMem[28][9].CLK +clk => RFMem[28][10].CLK +clk => RFMem[28][11].CLK +clk => RFMem[28][12].CLK +clk => RFMem[28][13].CLK +clk => RFMem[28][14].CLK +clk => RFMem[28][15].CLK +clk => RFMem[28][16].CLK +clk => RFMem[28][17].CLK +clk => RFMem[28][18].CLK +clk => RFMem[28][19].CLK +clk => RFMem[28][20].CLK +clk => RFMem[28][21].CLK +clk => RFMem[28][22].CLK +clk => RFMem[28][23].CLK +clk => RFMem[28][24].CLK +clk => RFMem[28][25].CLK +clk => RFMem[28][26].CLK +clk => RFMem[28][27].CLK +clk => RFMem[28][28].CLK +clk => RFMem[28][29].CLK +clk => RFMem[28][30].CLK +clk => RFMem[28][31].CLK +clk => RFMem[27][0].CLK +clk => RFMem[27][1].CLK +clk => RFMem[27][2].CLK +clk => RFMem[27][3].CLK +clk => RFMem[27][4].CLK +clk => RFMem[27][5].CLK +clk => RFMem[27][6].CLK +clk => RFMem[27][7].CLK +clk => RFMem[27][8].CLK +clk => RFMem[27][9].CLK +clk => RFMem[27][10].CLK +clk => RFMem[27][11].CLK +clk => RFMem[27][12].CLK +clk => RFMem[27][13].CLK +clk => RFMem[27][14].CLK +clk => RFMem[27][15].CLK +clk => RFMem[27][16].CLK +clk => RFMem[27][17].CLK +clk => RFMem[27][18].CLK +clk => RFMem[27][19].CLK +clk => RFMem[27][20].CLK +clk => RFMem[27][21].CLK +clk => RFMem[27][22].CLK +clk => RFMem[27][23].CLK +clk => RFMem[27][24].CLK +clk => RFMem[27][25].CLK +clk => RFMem[27][26].CLK +clk => RFMem[27][27].CLK +clk => RFMem[27][28].CLK +clk => RFMem[27][29].CLK +clk => RFMem[27][30].CLK +clk => RFMem[27][31].CLK +clk => RFMem[26][0].CLK +clk => RFMem[26][1].CLK +clk => RFMem[26][2].CLK +clk => RFMem[26][3].CLK +clk => RFMem[26][4].CLK +clk => RFMem[26][5].CLK +clk => RFMem[26][6].CLK +clk => RFMem[26][7].CLK +clk => RFMem[26][8].CLK +clk => RFMem[26][9].CLK +clk => RFMem[26][10].CLK +clk => RFMem[26][11].CLK +clk => RFMem[26][12].CLK +clk => RFMem[26][13].CLK +clk => RFMem[26][14].CLK +clk => RFMem[26][15].CLK +clk => RFMem[26][16].CLK +clk => RFMem[26][17].CLK +clk => RFMem[26][18].CLK +clk => RFMem[26][19].CLK +clk => RFMem[26][20].CLK +clk => RFMem[26][21].CLK +clk => RFMem[26][22].CLK +clk => RFMem[26][23].CLK +clk => RFMem[26][24].CLK +clk => RFMem[26][25].CLK +clk => RFMem[26][26].CLK +clk => RFMem[26][27].CLK +clk => RFMem[26][28].CLK +clk => RFMem[26][29].CLK +clk => RFMem[26][30].CLK +clk => RFMem[26][31].CLK +clk => RFMem[25][0].CLK +clk => RFMem[25][1].CLK +clk => RFMem[25][2].CLK +clk => RFMem[25][3].CLK +clk => RFMem[25][4].CLK +clk => RFMem[25][5].CLK +clk => RFMem[25][6].CLK +clk => RFMem[25][7].CLK +clk => RFMem[25][8].CLK +clk => RFMem[25][9].CLK +clk => RFMem[25][10].CLK +clk => RFMem[25][11].CLK +clk => RFMem[25][12].CLK +clk => RFMem[25][13].CLK +clk => RFMem[25][14].CLK +clk => RFMem[25][15].CLK +clk => RFMem[25][16].CLK +clk => RFMem[25][17].CLK +clk => RFMem[25][18].CLK +clk => RFMem[25][19].CLK +clk => RFMem[25][20].CLK +clk => RFMem[25][21].CLK +clk => RFMem[25][22].CLK +clk => RFMem[25][23].CLK +clk => RFMem[25][24].CLK +clk => RFMem[25][25].CLK +clk => RFMem[25][26].CLK +clk => RFMem[25][27].CLK +clk => RFMem[25][28].CLK +clk => RFMem[25][29].CLK +clk => RFMem[25][30].CLK +clk => RFMem[25][31].CLK +clk => RFMem[24][0].CLK +clk => RFMem[24][1].CLK +clk => RFMem[24][2].CLK +clk => RFMem[24][3].CLK +clk => RFMem[24][4].CLK +clk => RFMem[24][5].CLK +clk => RFMem[24][6].CLK +clk => RFMem[24][7].CLK +clk => RFMem[24][8].CLK +clk => RFMem[24][9].CLK +clk => RFMem[24][10].CLK +clk => RFMem[24][11].CLK +clk => RFMem[24][12].CLK +clk => RFMem[24][13].CLK +clk => RFMem[24][14].CLK +clk => RFMem[24][15].CLK +clk => RFMem[24][16].CLK +clk => RFMem[24][17].CLK +clk => RFMem[24][18].CLK +clk => RFMem[24][19].CLK +clk => RFMem[24][20].CLK +clk => RFMem[24][21].CLK +clk => RFMem[24][22].CLK +clk => RFMem[24][23].CLK +clk => RFMem[24][24].CLK +clk => RFMem[24][25].CLK +clk => RFMem[24][26].CLK +clk => RFMem[24][27].CLK +clk => RFMem[24][28].CLK +clk => RFMem[24][29].CLK +clk => RFMem[24][30].CLK +clk => RFMem[24][31].CLK +clk => RFMem[23][0].CLK +clk => RFMem[23][1].CLK +clk => RFMem[23][2].CLK +clk => RFMem[23][3].CLK +clk => RFMem[23][4].CLK +clk => RFMem[23][5].CLK +clk => RFMem[23][6].CLK +clk => RFMem[23][7].CLK +clk => RFMem[23][8].CLK +clk => RFMem[23][9].CLK +clk => RFMem[23][10].CLK +clk => RFMem[23][11].CLK +clk => RFMem[23][12].CLK +clk => RFMem[23][13].CLK +clk => RFMem[23][14].CLK +clk => RFMem[23][15].CLK +clk => RFMem[23][16].CLK +clk => RFMem[23][17].CLK +clk => RFMem[23][18].CLK +clk => RFMem[23][19].CLK +clk => RFMem[23][20].CLK +clk => RFMem[23][21].CLK +clk => RFMem[23][22].CLK +clk => RFMem[23][23].CLK +clk => RFMem[23][24].CLK +clk => RFMem[23][25].CLK +clk => RFMem[23][26].CLK +clk => RFMem[23][27].CLK +clk => RFMem[23][28].CLK +clk => RFMem[23][29].CLK +clk => RFMem[23][30].CLK +clk => RFMem[23][31].CLK +clk => RFMem[22][0].CLK +clk => RFMem[22][1].CLK +clk => RFMem[22][2].CLK +clk => RFMem[22][3].CLK +clk => RFMem[22][4].CLK +clk => RFMem[22][5].CLK +clk => RFMem[22][6].CLK +clk => RFMem[22][7].CLK +clk => RFMem[22][8].CLK +clk => RFMem[22][9].CLK +clk => RFMem[22][10].CLK +clk => RFMem[22][11].CLK +clk => RFMem[22][12].CLK +clk => RFMem[22][13].CLK +clk => RFMem[22][14].CLK +clk => RFMem[22][15].CLK +clk => RFMem[22][16].CLK +clk => RFMem[22][17].CLK +clk => RFMem[22][18].CLK +clk => RFMem[22][19].CLK +clk => RFMem[22][20].CLK +clk => RFMem[22][21].CLK +clk => RFMem[22][22].CLK +clk => RFMem[22][23].CLK +clk => RFMem[22][24].CLK +clk => RFMem[22][25].CLK +clk => RFMem[22][26].CLK +clk => RFMem[22][27].CLK +clk => RFMem[22][28].CLK +clk => RFMem[22][29].CLK +clk => RFMem[22][30].CLK +clk => RFMem[22][31].CLK +clk => RFMem[21][0].CLK +clk => RFMem[21][1].CLK +clk => RFMem[21][2].CLK +clk => RFMem[21][3].CLK +clk => RFMem[21][4].CLK +clk => RFMem[21][5].CLK +clk => RFMem[21][6].CLK +clk => RFMem[21][7].CLK +clk => RFMem[21][8].CLK +clk => RFMem[21][9].CLK +clk => RFMem[21][10].CLK +clk => RFMem[21][11].CLK +clk => RFMem[21][12].CLK +clk => RFMem[21][13].CLK +clk => RFMem[21][14].CLK +clk => RFMem[21][15].CLK +clk => RFMem[21][16].CLK +clk => RFMem[21][17].CLK +clk => RFMem[21][18].CLK +clk => RFMem[21][19].CLK +clk => RFMem[21][20].CLK +clk => RFMem[21][21].CLK +clk => RFMem[21][22].CLK +clk => RFMem[21][23].CLK +clk => RFMem[21][24].CLK +clk => RFMem[21][25].CLK +clk => RFMem[21][26].CLK +clk => RFMem[21][27].CLK +clk => RFMem[21][28].CLK +clk => RFMem[21][29].CLK +clk => RFMem[21][30].CLK +clk => RFMem[21][31].CLK +clk => RFMem[20][0].CLK +clk => RFMem[20][1].CLK +clk => RFMem[20][2].CLK +clk => RFMem[20][3].CLK +clk => RFMem[20][4].CLK +clk => RFMem[20][5].CLK +clk => RFMem[20][6].CLK +clk => RFMem[20][7].CLK +clk => RFMem[20][8].CLK +clk => RFMem[20][9].CLK +clk => RFMem[20][10].CLK +clk => RFMem[20][11].CLK +clk => RFMem[20][12].CLK +clk => RFMem[20][13].CLK +clk => RFMem[20][14].CLK +clk => RFMem[20][15].CLK +clk => RFMem[20][16].CLK +clk => RFMem[20][17].CLK +clk => RFMem[20][18].CLK +clk => RFMem[20][19].CLK +clk => RFMem[20][20].CLK +clk => RFMem[20][21].CLK +clk => RFMem[20][22].CLK +clk => RFMem[20][23].CLK +clk => RFMem[20][24].CLK +clk => RFMem[20][25].CLK +clk => RFMem[20][26].CLK +clk => RFMem[20][27].CLK +clk => RFMem[20][28].CLK +clk => RFMem[20][29].CLK +clk => RFMem[20][30].CLK +clk => RFMem[20][31].CLK +clk => RFMem[19][0].CLK +clk => RFMem[19][1].CLK +clk => RFMem[19][2].CLK +clk => RFMem[19][3].CLK +clk => RFMem[19][4].CLK +clk => RFMem[19][5].CLK +clk => RFMem[19][6].CLK +clk => RFMem[19][7].CLK +clk => RFMem[19][8].CLK +clk => RFMem[19][9].CLK +clk => RFMem[19][10].CLK +clk => RFMem[19][11].CLK +clk => RFMem[19][12].CLK +clk => RFMem[19][13].CLK +clk => RFMem[19][14].CLK +clk => RFMem[19][15].CLK +clk => RFMem[19][16].CLK +clk => RFMem[19][17].CLK +clk => RFMem[19][18].CLK +clk => RFMem[19][19].CLK +clk => RFMem[19][20].CLK +clk => RFMem[19][21].CLK +clk => RFMem[19][22].CLK +clk => RFMem[19][23].CLK +clk => RFMem[19][24].CLK +clk => RFMem[19][25].CLK +clk => RFMem[19][26].CLK +clk => RFMem[19][27].CLK +clk => RFMem[19][28].CLK +clk => RFMem[19][29].CLK +clk => RFMem[19][30].CLK +clk => RFMem[19][31].CLK +clk => RFMem[18][0].CLK +clk => RFMem[18][1].CLK +clk => RFMem[18][2].CLK +clk => RFMem[18][3].CLK +clk => RFMem[18][4].CLK +clk => RFMem[18][5].CLK +clk => RFMem[18][6].CLK +clk => RFMem[18][7].CLK +clk => RFMem[18][8].CLK +clk => RFMem[18][9].CLK +clk => RFMem[18][10].CLK +clk => RFMem[18][11].CLK +clk => RFMem[18][12].CLK +clk => RFMem[18][13].CLK +clk => RFMem[18][14].CLK +clk => RFMem[18][15].CLK +clk => RFMem[18][16].CLK +clk => RFMem[18][17].CLK +clk => RFMem[18][18].CLK +clk => RFMem[18][19].CLK +clk => RFMem[18][20].CLK +clk => RFMem[18][21].CLK +clk => RFMem[18][22].CLK +clk => RFMem[18][23].CLK +clk => RFMem[18][24].CLK +clk => RFMem[18][25].CLK +clk => RFMem[18][26].CLK +clk => RFMem[18][27].CLK +clk => RFMem[18][28].CLK +clk => RFMem[18][29].CLK +clk => RFMem[18][30].CLK +clk => RFMem[18][31].CLK +clk => RFMem[17][0].CLK +clk => RFMem[17][1].CLK +clk => RFMem[17][2].CLK +clk => RFMem[17][3].CLK +clk => RFMem[17][4].CLK +clk => RFMem[17][5].CLK +clk => RFMem[17][6].CLK +clk => RFMem[17][7].CLK +clk => RFMem[17][8].CLK +clk => RFMem[17][9].CLK +clk => RFMem[17][10].CLK +clk => RFMem[17][11].CLK +clk => RFMem[17][12].CLK +clk => RFMem[17][13].CLK +clk => RFMem[17][14].CLK +clk => RFMem[17][15].CLK +clk => RFMem[17][16].CLK +clk => RFMem[17][17].CLK +clk => RFMem[17][18].CLK +clk => RFMem[17][19].CLK +clk => RFMem[17][20].CLK +clk => RFMem[17][21].CLK +clk => RFMem[17][22].CLK +clk => RFMem[17][23].CLK +clk => RFMem[17][24].CLK +clk => RFMem[17][25].CLK +clk => RFMem[17][26].CLK +clk => RFMem[17][27].CLK +clk => RFMem[17][28].CLK +clk => RFMem[17][29].CLK +clk => RFMem[17][30].CLK +clk => RFMem[17][31].CLK +clk => RFMem[16][0].CLK +clk => RFMem[16][1].CLK +clk => RFMem[16][2].CLK +clk => RFMem[16][3].CLK +clk => RFMem[16][4].CLK +clk => RFMem[16][5].CLK +clk => RFMem[16][6].CLK +clk => RFMem[16][7].CLK +clk => RFMem[16][8].CLK +clk => RFMem[16][9].CLK +clk => RFMem[16][10].CLK +clk => RFMem[16][11].CLK +clk => RFMem[16][12].CLK +clk => RFMem[16][13].CLK +clk => RFMem[16][14].CLK +clk => RFMem[16][15].CLK +clk => RFMem[16][16].CLK +clk => RFMem[16][17].CLK +clk => RFMem[16][18].CLK +clk => RFMem[16][19].CLK +clk => RFMem[16][20].CLK +clk => RFMem[16][21].CLK +clk => RFMem[16][22].CLK +clk => RFMem[16][23].CLK +clk => RFMem[16][24].CLK +clk => RFMem[16][25].CLK +clk => RFMem[16][26].CLK +clk => RFMem[16][27].CLK +clk => RFMem[16][28].CLK +clk => RFMem[16][29].CLK +clk => RFMem[16][30].CLK +clk => RFMem[16][31].CLK +clk => RFMem[15][0].CLK +clk => RFMem[15][1].CLK +clk => RFMem[15][2].CLK +clk => RFMem[15][3].CLK +clk => RFMem[15][4].CLK +clk => RFMem[15][5].CLK +clk => RFMem[15][6].CLK +clk => RFMem[15][7].CLK +clk => RFMem[15][8].CLK +clk => RFMem[15][9].CLK +clk => RFMem[15][10].CLK +clk => RFMem[15][11].CLK +clk => RFMem[15][12].CLK +clk => RFMem[15][13].CLK +clk => RFMem[15][14].CLK +clk => RFMem[15][15].CLK +clk => RFMem[15][16].CLK +clk => RFMem[15][17].CLK +clk => RFMem[15][18].CLK +clk => RFMem[15][19].CLK +clk => RFMem[15][20].CLK +clk => RFMem[15][21].CLK +clk => RFMem[15][22].CLK +clk => RFMem[15][23].CLK +clk => RFMem[15][24].CLK +clk => RFMem[15][25].CLK +clk => RFMem[15][26].CLK +clk => RFMem[15][27].CLK +clk => RFMem[15][28].CLK +clk => RFMem[15][29].CLK +clk => RFMem[15][30].CLK +clk => RFMem[15][31].CLK +clk => RFMem[14][0].CLK +clk => RFMem[14][1].CLK +clk => RFMem[14][2].CLK +clk => RFMem[14][3].CLK +clk => RFMem[14][4].CLK +clk => RFMem[14][5].CLK +clk => RFMem[14][6].CLK +clk => RFMem[14][7].CLK +clk => RFMem[14][8].CLK +clk => RFMem[14][9].CLK +clk => RFMem[14][10].CLK +clk => RFMem[14][11].CLK +clk => RFMem[14][12].CLK +clk => RFMem[14][13].CLK +clk => RFMem[14][14].CLK +clk => RFMem[14][15].CLK +clk => RFMem[14][16].CLK +clk => RFMem[14][17].CLK +clk => RFMem[14][18].CLK +clk => RFMem[14][19].CLK +clk => RFMem[14][20].CLK +clk => RFMem[14][21].CLK +clk => RFMem[14][22].CLK +clk => RFMem[14][23].CLK +clk => RFMem[14][24].CLK +clk => RFMem[14][25].CLK +clk => RFMem[14][26].CLK +clk => RFMem[14][27].CLK +clk => RFMem[14][28].CLK +clk => RFMem[14][29].CLK +clk => RFMem[14][30].CLK +clk => RFMem[14][31].CLK +clk => RFMem[13][0].CLK +clk => RFMem[13][1].CLK +clk => RFMem[13][2].CLK +clk => RFMem[13][3].CLK +clk => RFMem[13][4].CLK +clk => RFMem[13][5].CLK +clk => RFMem[13][6].CLK +clk => RFMem[13][7].CLK +clk => RFMem[13][8].CLK +clk => RFMem[13][9].CLK +clk => RFMem[13][10].CLK +clk => RFMem[13][11].CLK +clk => RFMem[13][12].CLK +clk => RFMem[13][13].CLK +clk => RFMem[13][14].CLK +clk => RFMem[13][15].CLK +clk => RFMem[13][16].CLK +clk => RFMem[13][17].CLK +clk => RFMem[13][18].CLK +clk => RFMem[13][19].CLK +clk => RFMem[13][20].CLK +clk => RFMem[13][21].CLK +clk => RFMem[13][22].CLK +clk => RFMem[13][23].CLK +clk => RFMem[13][24].CLK +clk => RFMem[13][25].CLK +clk => RFMem[13][26].CLK +clk => RFMem[13][27].CLK +clk => RFMem[13][28].CLK +clk => RFMem[13][29].CLK +clk => RFMem[13][30].CLK +clk => RFMem[13][31].CLK +clk => RFMem[12][0].CLK +clk => RFMem[12][1].CLK +clk => RFMem[12][2].CLK +clk => RFMem[12][3].CLK +clk => RFMem[12][4].CLK +clk => RFMem[12][5].CLK +clk => RFMem[12][6].CLK +clk => RFMem[12][7].CLK +clk => RFMem[12][8].CLK +clk => RFMem[12][9].CLK +clk => RFMem[12][10].CLK +clk => RFMem[12][11].CLK +clk => RFMem[12][12].CLK +clk => RFMem[12][13].CLK +clk => RFMem[12][14].CLK +clk => RFMem[12][15].CLK +clk => RFMem[12][16].CLK +clk => RFMem[12][17].CLK +clk => RFMem[12][18].CLK +clk => RFMem[12][19].CLK +clk => RFMem[12][20].CLK +clk => RFMem[12][21].CLK +clk => RFMem[12][22].CLK +clk => RFMem[12][23].CLK +clk => RFMem[12][24].CLK +clk => RFMem[12][25].CLK +clk => RFMem[12][26].CLK +clk => RFMem[12][27].CLK +clk => RFMem[12][28].CLK +clk => RFMem[12][29].CLK +clk => RFMem[12][30].CLK +clk => RFMem[12][31].CLK +clk => RFMem[11][0].CLK +clk => RFMem[11][1].CLK +clk => RFMem[11][2].CLK +clk => RFMem[11][3].CLK +clk => RFMem[11][4].CLK +clk => RFMem[11][5].CLK +clk => RFMem[11][6].CLK +clk => RFMem[11][7].CLK +clk => RFMem[11][8].CLK +clk => RFMem[11][9].CLK +clk => RFMem[11][10].CLK +clk => RFMem[11][11].CLK +clk => RFMem[11][12].CLK +clk => RFMem[11][13].CLK +clk => RFMem[11][14].CLK +clk => RFMem[11][15].CLK +clk => RFMem[11][16].CLK +clk => RFMem[11][17].CLK +clk => RFMem[11][18].CLK +clk => RFMem[11][19].CLK +clk => RFMem[11][20].CLK +clk => RFMem[11][21].CLK +clk => RFMem[11][22].CLK +clk => RFMem[11][23].CLK +clk => RFMem[11][24].CLK +clk => RFMem[11][25].CLK +clk => RFMem[11][26].CLK +clk => RFMem[11][27].CLK +clk => RFMem[11][28].CLK +clk => RFMem[11][29].CLK +clk => RFMem[11][30].CLK +clk => RFMem[11][31].CLK +clk => RFMem[10][0].CLK +clk => RFMem[10][1].CLK +clk => RFMem[10][2].CLK +clk => RFMem[10][3].CLK +clk => RFMem[10][4].CLK +clk => RFMem[10][5].CLK +clk => RFMem[10][6].CLK +clk => RFMem[10][7].CLK +clk => RFMem[10][8].CLK +clk => RFMem[10][9].CLK +clk => RFMem[10][10].CLK +clk => RFMem[10][11].CLK +clk => RFMem[10][12].CLK +clk => RFMem[10][13].CLK +clk => RFMem[10][14].CLK +clk => RFMem[10][15].CLK +clk => RFMem[10][16].CLK +clk => RFMem[10][17].CLK +clk => RFMem[10][18].CLK +clk => RFMem[10][19].CLK +clk => RFMem[10][20].CLK +clk => RFMem[10][21].CLK +clk => RFMem[10][22].CLK +clk => RFMem[10][23].CLK +clk => RFMem[10][24].CLK +clk => RFMem[10][25].CLK +clk => RFMem[10][26].CLK +clk => RFMem[10][27].CLK +clk => RFMem[10][28].CLK +clk => RFMem[10][29].CLK +clk => RFMem[10][30].CLK +clk => RFMem[10][31].CLK +clk => RFMem[9][0].CLK +clk => RFMem[9][1].CLK +clk => RFMem[9][2].CLK +clk => RFMem[9][3].CLK +clk => RFMem[9][4].CLK +clk => RFMem[9][5].CLK +clk => RFMem[9][6].CLK +clk => RFMem[9][7].CLK +clk => RFMem[9][8].CLK +clk => RFMem[9][9].CLK +clk => RFMem[9][10].CLK +clk => RFMem[9][11].CLK +clk => RFMem[9][12].CLK +clk => RFMem[9][13].CLK +clk => RFMem[9][14].CLK +clk => RFMem[9][15].CLK +clk => RFMem[9][16].CLK +clk => RFMem[9][17].CLK +clk => RFMem[9][18].CLK +clk => RFMem[9][19].CLK +clk => RFMem[9][20].CLK +clk => RFMem[9][21].CLK +clk => RFMem[9][22].CLK +clk => RFMem[9][23].CLK +clk => RFMem[9][24].CLK +clk => RFMem[9][25].CLK +clk => RFMem[9][26].CLK +clk => RFMem[9][27].CLK +clk => RFMem[9][28].CLK +clk => RFMem[9][29].CLK +clk => RFMem[9][30].CLK +clk => RFMem[9][31].CLK +clk => RFMem[8][0].CLK +clk => RFMem[8][1].CLK +clk => RFMem[8][2].CLK +clk => RFMem[8][3].CLK +clk => RFMem[8][4].CLK +clk => RFMem[8][5].CLK +clk => RFMem[8][6].CLK +clk => RFMem[8][7].CLK +clk => RFMem[8][8].CLK +clk => RFMem[8][9].CLK +clk => RFMem[8][10].CLK +clk => RFMem[8][11].CLK +clk => RFMem[8][12].CLK +clk => RFMem[8][13].CLK +clk => RFMem[8][14].CLK +clk => RFMem[8][15].CLK +clk => RFMem[8][16].CLK +clk => RFMem[8][17].CLK +clk => RFMem[8][18].CLK +clk => RFMem[8][19].CLK +clk => RFMem[8][20].CLK +clk => RFMem[8][21].CLK +clk => RFMem[8][22].CLK +clk => RFMem[8][23].CLK +clk => RFMem[8][24].CLK +clk => RFMem[8][25].CLK +clk => RFMem[8][26].CLK +clk => RFMem[8][27].CLK +clk => RFMem[8][28].CLK +clk => RFMem[8][29].CLK +clk => RFMem[8][30].CLK +clk => RFMem[8][31].CLK +clk => RFMem[7][0].CLK +clk => RFMem[7][1].CLK +clk => RFMem[7][2].CLK +clk => RFMem[7][3].CLK +clk => RFMem[7][4].CLK +clk => RFMem[7][5].CLK +clk => RFMem[7][6].CLK +clk => RFMem[7][7].CLK +clk => RFMem[7][8].CLK +clk => RFMem[7][9].CLK +clk => RFMem[7][10].CLK +clk => RFMem[7][11].CLK +clk => RFMem[7][12].CLK +clk => RFMem[7][13].CLK +clk => RFMem[7][14].CLK +clk => RFMem[7][15].CLK +clk => RFMem[7][16].CLK +clk => RFMem[7][17].CLK +clk => RFMem[7][18].CLK +clk => RFMem[7][19].CLK +clk => RFMem[7][20].CLK +clk => RFMem[7][21].CLK +clk => RFMem[7][22].CLK +clk => RFMem[7][23].CLK +clk => RFMem[7][24].CLK +clk => RFMem[7][25].CLK +clk => RFMem[7][26].CLK +clk => RFMem[7][27].CLK +clk => RFMem[7][28].CLK +clk => RFMem[7][29].CLK +clk => RFMem[7][30].CLK +clk => RFMem[7][31].CLK +clk => RFMem[6][0].CLK +clk => RFMem[6][1].CLK +clk => RFMem[6][2].CLK +clk => RFMem[6][3].CLK +clk => RFMem[6][4].CLK +clk => RFMem[6][5].CLK +clk => RFMem[6][6].CLK +clk => RFMem[6][7].CLK +clk => RFMem[6][8].CLK +clk => RFMem[6][9].CLK +clk => RFMem[6][10].CLK +clk => RFMem[6][11].CLK +clk => RFMem[6][12].CLK +clk => RFMem[6][13].CLK +clk => RFMem[6][14].CLK +clk => RFMem[6][15].CLK +clk => RFMem[6][16].CLK +clk => RFMem[6][17].CLK +clk => RFMem[6][18].CLK +clk => RFMem[6][19].CLK +clk => RFMem[6][20].CLK +clk => RFMem[6][21].CLK +clk => RFMem[6][22].CLK +clk => RFMem[6][23].CLK +clk => RFMem[6][24].CLK +clk => RFMem[6][25].CLK +clk => RFMem[6][26].CLK +clk => RFMem[6][27].CLK +clk => RFMem[6][28].CLK +clk => RFMem[6][29].CLK +clk => RFMem[6][30].CLK +clk => RFMem[6][31].CLK +clk => RFMem[5][0].CLK +clk => RFMem[5][1].CLK +clk => RFMem[5][2].CLK +clk => RFMem[5][3].CLK +clk => RFMem[5][4].CLK +clk => RFMem[5][5].CLK +clk => RFMem[5][6].CLK +clk => RFMem[5][7].CLK +clk => RFMem[5][8].CLK +clk => RFMem[5][9].CLK +clk => RFMem[5][10].CLK +clk => RFMem[5][11].CLK +clk => RFMem[5][12].CLK +clk => RFMem[5][13].CLK +clk => RFMem[5][14].CLK +clk => RFMem[5][15].CLK +clk => RFMem[5][16].CLK +clk => RFMem[5][17].CLK +clk => RFMem[5][18].CLK +clk => RFMem[5][19].CLK +clk => RFMem[5][20].CLK +clk => RFMem[5][21].CLK +clk => RFMem[5][22].CLK +clk => RFMem[5][23].CLK +clk => RFMem[5][24].CLK +clk => RFMem[5][25].CLK +clk => RFMem[5][26].CLK +clk => RFMem[5][27].CLK +clk => RFMem[5][28].CLK +clk => RFMem[5][29].CLK +clk => RFMem[5][30].CLK +clk => RFMem[5][31].CLK +clk => RFMem[4][0].CLK +clk => RFMem[4][1].CLK +clk => RFMem[4][2].CLK +clk => RFMem[4][3].CLK +clk => RFMem[4][4].CLK +clk => RFMem[4][5].CLK +clk => RFMem[4][6].CLK +clk => RFMem[4][7].CLK +clk => RFMem[4][8].CLK +clk => RFMem[4][9].CLK +clk => RFMem[4][10].CLK +clk => RFMem[4][11].CLK +clk => RFMem[4][12].CLK +clk => RFMem[4][13].CLK +clk => RFMem[4][14].CLK +clk => RFMem[4][15].CLK +clk => RFMem[4][16].CLK +clk => RFMem[4][17].CLK +clk => RFMem[4][18].CLK +clk => RFMem[4][19].CLK +clk => RFMem[4][20].CLK +clk => RFMem[4][21].CLK +clk => RFMem[4][22].CLK +clk => RFMem[4][23].CLK +clk => RFMem[4][24].CLK +clk => RFMem[4][25].CLK +clk => RFMem[4][26].CLK +clk => RFMem[4][27].CLK +clk => RFMem[4][28].CLK +clk => RFMem[4][29].CLK +clk => RFMem[4][30].CLK +clk => RFMem[4][31].CLK +clk => RFMem[3][0].CLK +clk => RFMem[3][1].CLK +clk => RFMem[3][2].CLK +clk => RFMem[3][3].CLK +clk => RFMem[3][4].CLK +clk => RFMem[3][5].CLK +clk => RFMem[3][6].CLK +clk => RFMem[3][7].CLK +clk => RFMem[3][8].CLK +clk => RFMem[3][9].CLK +clk => RFMem[3][10].CLK +clk => RFMem[3][11].CLK +clk => RFMem[3][12].CLK +clk => RFMem[3][13].CLK +clk => RFMem[3][14].CLK +clk => RFMem[3][15].CLK +clk => RFMem[3][16].CLK +clk => RFMem[3][17].CLK +clk => RFMem[3][18].CLK +clk => RFMem[3][19].CLK +clk => RFMem[3][20].CLK +clk => RFMem[3][21].CLK +clk => RFMem[3][22].CLK +clk => RFMem[3][23].CLK +clk => RFMem[3][24].CLK +clk => RFMem[3][25].CLK +clk => RFMem[3][26].CLK +clk => RFMem[3][27].CLK +clk => RFMem[3][28].CLK +clk => RFMem[3][29].CLK +clk => RFMem[3][30].CLK +clk => RFMem[3][31].CLK +clk => RFMem[2][0].CLK +clk => RFMem[2][1].CLK +clk => RFMem[2][2].CLK +clk => RFMem[2][3].CLK +clk => RFMem[2][4].CLK +clk => RFMem[2][5].CLK +clk => RFMem[2][6].CLK +clk => RFMem[2][7].CLK +clk => RFMem[2][8].CLK +clk => RFMem[2][9].CLK +clk => RFMem[2][10].CLK +clk => RFMem[2][11].CLK +clk => RFMem[2][12].CLK +clk => RFMem[2][13].CLK +clk => RFMem[2][14].CLK +clk => RFMem[2][15].CLK +clk => RFMem[2][16].CLK +clk => RFMem[2][17].CLK +clk => RFMem[2][18].CLK +clk => RFMem[2][19].CLK +clk => RFMem[2][20].CLK +clk => RFMem[2][21].CLK +clk => RFMem[2][22].CLK +clk => RFMem[2][23].CLK +clk => RFMem[2][24].CLK +clk => RFMem[2][25].CLK +clk => RFMem[2][26].CLK +clk => RFMem[2][27].CLK +clk => RFMem[2][28].CLK +clk => RFMem[2][29].CLK +clk => RFMem[2][30].CLK +clk => RFMem[2][31].CLK +clk => RFMem[1][0].CLK +clk => RFMem[1][1].CLK +clk => RFMem[1][2].CLK +clk => RFMem[1][3].CLK +clk => RFMem[1][4].CLK +clk => RFMem[1][5].CLK +clk => RFMem[1][6].CLK +clk => RFMem[1][7].CLK +clk => RFMem[1][8].CLK +clk => RFMem[1][9].CLK +clk => RFMem[1][10].CLK +clk => RFMem[1][11].CLK +clk => RFMem[1][12].CLK +clk => RFMem[1][13].CLK +clk => RFMem[1][14].CLK +clk => RFMem[1][15].CLK +clk => RFMem[1][16].CLK +clk => RFMem[1][17].CLK +clk => RFMem[1][18].CLK +clk => RFMem[1][19].CLK +clk => RFMem[1][20].CLK +clk => RFMem[1][21].CLK +clk => RFMem[1][22].CLK +clk => RFMem[1][23].CLK +clk => RFMem[1][24].CLK +clk => RFMem[1][25].CLK +clk => RFMem[1][26].CLK +clk => RFMem[1][27].CLK +clk => RFMem[1][28].CLK +clk => RFMem[1][29].CLK +clk => RFMem[1][30].CLK +clk => RFMem[1][31].CLK +clk => RFMem[0][0].CLK +clk => RFMem[0][1].CLK +clk => RFMem[0][2].CLK +clk => RFMem[0][3].CLK +clk => RFMem[0][4].CLK +clk => RFMem[0][5].CLK +clk => RFMem[0][6].CLK +clk => RFMem[0][7].CLK +clk => RFMem[0][8].CLK +clk => RFMem[0][9].CLK +clk => RFMem[0][10].CLK +clk => RFMem[0][11].CLK +clk => RFMem[0][12].CLK +clk => RFMem[0][13].CLK +clk => RFMem[0][14].CLK +clk => RFMem[0][15].CLK +clk => RFMem[0][16].CLK +clk => RFMem[0][17].CLK +clk => RFMem[0][18].CLK +clk => RFMem[0][19].CLK +clk => RFMem[0][20].CLK +clk => RFMem[0][21].CLK +clk => RFMem[0][22].CLK +clk => RFMem[0][23].CLK +clk => RFMem[0][24].CLK +clk => RFMem[0][25].CLK +clk => RFMem[0][26].CLK +clk => RFMem[0][27].CLK +clk => RFMem[0][28].CLK +clk => RFMem[0][29].CLK +clk => RFMem[0][30].CLK +clk => RFMem[0][31].CLK +regWrite => always32.IN1 +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[0] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[1] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[2] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[3] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[4] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[5] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[6] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[7] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[8] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[9] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[10] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[11] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[12] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => RFMem.DATAB +dataIn[13] => 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RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[18] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[19] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => RFMem.DATAB +dataIn[20] => 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RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[21] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[22] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[23] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[24] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[25] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[26] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[27] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[28] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[29] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[30] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +dataIn[31] => RFMem.DATAB +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +reset => RFMem.OUTPUTSELECT +baseAddr[0] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[1] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[2] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[3] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[4] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[5] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[6] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[7] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[8] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[9] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[10] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[11] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[12] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[13] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[14] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[15] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[16] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[17] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[18] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[19] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[20] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[21] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[22] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[23] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[24] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[25] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[26] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[27] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[28] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[29] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[30] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +baseAddr[31] <= baseAddr.DB_MAX_OUTPUT_PORT_TYPE +writeData[0] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[1] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[2] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[3] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[4] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[5] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[6] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[7] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[8] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[9] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[10] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[11] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[12] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[13] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[14] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[15] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[16] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[17] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[18] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[19] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[20] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[21] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[22] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[23] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[24] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[25] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[26] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[27] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[28] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[29] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[30] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +writeData[31] <= writeData.DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][0] <= dbg_regs[31][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][1] <= dbg_regs[31][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][2] <= dbg_regs[31][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][3] <= dbg_regs[31][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][4] <= dbg_regs[31][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][5] <= dbg_regs[31][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][6] <= dbg_regs[31][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][7] <= dbg_regs[31][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][8] <= dbg_regs[31][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][9] <= dbg_regs[31][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][10] <= dbg_regs[31][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][11] <= dbg_regs[31][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][12] <= dbg_regs[31][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][13] <= dbg_regs[31][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][14] <= dbg_regs[31][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][15] <= dbg_regs[31][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][16] <= dbg_regs[31][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][17] <= dbg_regs[31][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][18] <= dbg_regs[31][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][19] <= dbg_regs[31][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][20] <= dbg_regs[31][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][21] <= dbg_regs[31][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][22] <= dbg_regs[31][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][23] <= dbg_regs[31][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][24] <= dbg_regs[31][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][25] <= dbg_regs[31][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][26] <= dbg_regs[31][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][27] <= dbg_regs[31][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][28] <= dbg_regs[31][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][29] <= dbg_regs[31][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][30] <= dbg_regs[31][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[31][31] <= dbg_regs[31][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][0] <= dbg_regs[30][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][1] <= dbg_regs[30][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][2] <= dbg_regs[30][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][3] <= dbg_regs[30][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][4] <= dbg_regs[30][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][5] <= dbg_regs[30][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][6] <= dbg_regs[30][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][7] <= dbg_regs[30][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][8] <= dbg_regs[30][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][9] <= dbg_regs[30][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][10] <= dbg_regs[30][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][11] <= dbg_regs[30][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][12] <= dbg_regs[30][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][13] <= dbg_regs[30][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][14] <= dbg_regs[30][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][15] <= dbg_regs[30][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][16] <= dbg_regs[30][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][17] <= dbg_regs[30][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][18] <= dbg_regs[30][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][19] <= dbg_regs[30][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][20] <= dbg_regs[30][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][21] <= dbg_regs[30][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][22] <= dbg_regs[30][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][23] <= dbg_regs[30][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][24] <= dbg_regs[30][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][25] <= dbg_regs[30][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][26] <= dbg_regs[30][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][27] <= dbg_regs[30][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][28] <= dbg_regs[30][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][29] <= dbg_regs[30][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][30] <= dbg_regs[30][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[30][31] <= dbg_regs[30][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][0] <= dbg_regs[29][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][1] <= dbg_regs[29][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][2] <= dbg_regs[29][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][3] <= dbg_regs[29][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][4] <= dbg_regs[29][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][5] <= dbg_regs[29][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][6] <= dbg_regs[29][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][7] <= dbg_regs[29][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][8] <= dbg_regs[29][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][9] <= dbg_regs[29][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][10] <= dbg_regs[29][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][11] <= dbg_regs[29][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][12] <= dbg_regs[29][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][13] <= dbg_regs[29][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][14] <= dbg_regs[29][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][15] <= dbg_regs[29][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][16] <= dbg_regs[29][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][17] <= dbg_regs[29][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][18] <= dbg_regs[29][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][19] <= dbg_regs[29][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][20] <= dbg_regs[29][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][21] <= dbg_regs[29][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][22] <= dbg_regs[29][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][23] <= dbg_regs[29][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][24] <= dbg_regs[29][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][25] <= dbg_regs[29][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][26] <= dbg_regs[29][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][27] <= dbg_regs[29][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][28] <= dbg_regs[29][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][29] <= dbg_regs[29][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][30] <= dbg_regs[29][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[29][31] <= dbg_regs[29][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][0] <= dbg_regs[28][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][1] <= dbg_regs[28][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][2] <= dbg_regs[28][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][3] <= dbg_regs[28][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][4] <= dbg_regs[28][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][5] <= dbg_regs[28][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][6] <= dbg_regs[28][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][7] <= dbg_regs[28][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][8] <= dbg_regs[28][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][9] <= dbg_regs[28][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][10] <= dbg_regs[28][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][11] <= dbg_regs[28][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][12] <= dbg_regs[28][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][13] <= dbg_regs[28][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][14] <= dbg_regs[28][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][15] <= dbg_regs[28][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][16] <= dbg_regs[28][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][17] <= dbg_regs[28][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][18] <= dbg_regs[28][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][19] <= dbg_regs[28][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][20] <= dbg_regs[28][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][21] <= dbg_regs[28][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][22] <= dbg_regs[28][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][23] <= dbg_regs[28][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][24] <= dbg_regs[28][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][25] <= dbg_regs[28][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][26] <= dbg_regs[28][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][27] <= dbg_regs[28][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][28] <= dbg_regs[28][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][29] <= dbg_regs[28][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][30] <= dbg_regs[28][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[28][31] <= dbg_regs[28][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][0] <= dbg_regs[27][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][1] <= dbg_regs[27][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][2] <= dbg_regs[27][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][3] <= dbg_regs[27][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][4] <= dbg_regs[27][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][5] <= dbg_regs[27][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][6] <= dbg_regs[27][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][7] <= dbg_regs[27][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][8] <= dbg_regs[27][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][9] <= dbg_regs[27][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][10] <= dbg_regs[27][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][11] <= dbg_regs[27][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][12] <= dbg_regs[27][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][13] <= dbg_regs[27][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][14] <= dbg_regs[27][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][15] <= dbg_regs[27][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][16] <= dbg_regs[27][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][17] <= dbg_regs[27][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][18] <= dbg_regs[27][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][19] <= dbg_regs[27][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][20] <= dbg_regs[27][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][21] <= dbg_regs[27][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][22] <= dbg_regs[27][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][23] <= dbg_regs[27][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][24] <= dbg_regs[27][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][25] <= dbg_regs[27][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][26] <= dbg_regs[27][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][27] <= dbg_regs[27][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][28] <= dbg_regs[27][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][29] <= dbg_regs[27][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][30] <= dbg_regs[27][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[27][31] <= dbg_regs[27][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][0] <= dbg_regs[26][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][1] <= dbg_regs[26][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][2] <= dbg_regs[26][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][3] <= dbg_regs[26][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][4] <= dbg_regs[26][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][5] <= dbg_regs[26][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][6] <= dbg_regs[26][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][7] <= dbg_regs[26][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][8] <= dbg_regs[26][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][9] <= dbg_regs[26][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][10] <= dbg_regs[26][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][11] <= dbg_regs[26][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][12] <= dbg_regs[26][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][13] <= dbg_regs[26][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][14] <= dbg_regs[26][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][15] <= dbg_regs[26][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][16] <= dbg_regs[26][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][17] <= dbg_regs[26][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][18] <= dbg_regs[26][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][19] <= dbg_regs[26][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][20] <= dbg_regs[26][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][21] <= dbg_regs[26][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][22] <= dbg_regs[26][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][23] <= dbg_regs[26][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][24] <= dbg_regs[26][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][25] <= dbg_regs[26][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][26] <= dbg_regs[26][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][27] <= dbg_regs[26][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][28] <= dbg_regs[26][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][29] <= dbg_regs[26][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][30] <= dbg_regs[26][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[26][31] <= dbg_regs[26][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][0] <= dbg_regs[25][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][1] <= dbg_regs[25][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][2] <= dbg_regs[25][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][3] <= dbg_regs[25][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][4] <= dbg_regs[25][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][5] <= dbg_regs[25][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][6] <= dbg_regs[25][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][7] <= dbg_regs[25][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][8] <= dbg_regs[25][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][9] <= dbg_regs[25][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][10] <= dbg_regs[25][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][11] <= dbg_regs[25][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][12] <= dbg_regs[25][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][13] <= dbg_regs[25][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][14] <= dbg_regs[25][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][15] <= dbg_regs[25][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][16] <= dbg_regs[25][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][17] <= dbg_regs[25][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][18] <= dbg_regs[25][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][19] <= dbg_regs[25][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][20] <= dbg_regs[25][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][21] <= dbg_regs[25][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][22] <= dbg_regs[25][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][23] <= dbg_regs[25][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][24] <= dbg_regs[25][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][25] <= dbg_regs[25][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][26] <= dbg_regs[25][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][27] <= dbg_regs[25][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][28] <= dbg_regs[25][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][29] <= dbg_regs[25][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][30] <= dbg_regs[25][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[25][31] <= dbg_regs[25][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][0] <= dbg_regs[24][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][1] <= dbg_regs[24][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][2] <= dbg_regs[24][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][3] <= dbg_regs[24][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][4] <= dbg_regs[24][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][5] <= dbg_regs[24][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][6] <= dbg_regs[24][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][7] <= dbg_regs[24][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][8] <= dbg_regs[24][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][9] <= dbg_regs[24][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][10] <= dbg_regs[24][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][11] <= dbg_regs[24][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][12] <= dbg_regs[24][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][13] <= dbg_regs[24][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][14] <= dbg_regs[24][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][15] <= dbg_regs[24][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][16] <= dbg_regs[24][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][17] <= dbg_regs[24][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][18] <= dbg_regs[24][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][19] <= dbg_regs[24][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][20] <= dbg_regs[24][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][21] <= dbg_regs[24][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][22] <= dbg_regs[24][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][23] <= dbg_regs[24][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][24] <= dbg_regs[24][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][25] <= dbg_regs[24][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][26] <= dbg_regs[24][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][27] <= dbg_regs[24][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][28] <= dbg_regs[24][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][29] <= dbg_regs[24][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][30] <= dbg_regs[24][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[24][31] <= dbg_regs[24][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][0] <= dbg_regs[23][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][1] <= dbg_regs[23][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][2] <= dbg_regs[23][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][3] <= dbg_regs[23][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][4] <= dbg_regs[23][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][5] <= dbg_regs[23][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][6] <= dbg_regs[23][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][7] <= dbg_regs[23][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][8] <= dbg_regs[23][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][9] <= dbg_regs[23][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][10] <= dbg_regs[23][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][11] <= dbg_regs[23][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][12] <= dbg_regs[23][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][13] <= dbg_regs[23][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][14] <= dbg_regs[23][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][15] <= dbg_regs[23][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][16] <= dbg_regs[23][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][17] <= dbg_regs[23][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][18] <= dbg_regs[23][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][19] <= dbg_regs[23][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][20] <= dbg_regs[23][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][21] <= dbg_regs[23][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][22] <= dbg_regs[23][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][23] <= dbg_regs[23][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][24] <= dbg_regs[23][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][25] <= dbg_regs[23][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][26] <= dbg_regs[23][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][27] <= dbg_regs[23][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][28] <= dbg_regs[23][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][29] <= dbg_regs[23][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][30] <= dbg_regs[23][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[23][31] <= dbg_regs[23][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][0] <= dbg_regs[22][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][1] <= dbg_regs[22][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][2] <= dbg_regs[22][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][3] <= dbg_regs[22][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][4] <= dbg_regs[22][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][5] <= dbg_regs[22][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][6] <= dbg_regs[22][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][7] <= dbg_regs[22][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][8] <= dbg_regs[22][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][9] <= dbg_regs[22][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][10] <= dbg_regs[22][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][11] <= dbg_regs[22][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][12] <= dbg_regs[22][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][13] <= dbg_regs[22][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][14] <= dbg_regs[22][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][15] <= dbg_regs[22][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][16] <= dbg_regs[22][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][17] <= dbg_regs[22][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][18] <= dbg_regs[22][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][19] <= dbg_regs[22][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][20] <= dbg_regs[22][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][21] <= dbg_regs[22][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][22] <= dbg_regs[22][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][23] <= dbg_regs[22][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][24] <= dbg_regs[22][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][25] <= dbg_regs[22][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][26] <= dbg_regs[22][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][27] <= dbg_regs[22][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][28] <= dbg_regs[22][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][29] <= dbg_regs[22][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][30] <= dbg_regs[22][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[22][31] <= dbg_regs[22][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][0] <= dbg_regs[21][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][1] <= dbg_regs[21][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][2] <= dbg_regs[21][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][3] <= dbg_regs[21][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][4] <= dbg_regs[21][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][5] <= dbg_regs[21][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][6] <= dbg_regs[21][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][7] <= dbg_regs[21][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][8] <= dbg_regs[21][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][9] <= dbg_regs[21][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][10] <= dbg_regs[21][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][11] <= dbg_regs[21][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][12] <= dbg_regs[21][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][13] <= dbg_regs[21][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][14] <= dbg_regs[21][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][15] <= dbg_regs[21][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][16] <= dbg_regs[21][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][17] <= dbg_regs[21][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][18] <= dbg_regs[21][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][19] <= dbg_regs[21][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][20] <= dbg_regs[21][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][21] <= dbg_regs[21][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][22] <= dbg_regs[21][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][23] <= dbg_regs[21][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][24] <= dbg_regs[21][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][25] <= dbg_regs[21][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][26] <= dbg_regs[21][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][27] <= dbg_regs[21][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][28] <= dbg_regs[21][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][29] <= dbg_regs[21][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][30] <= dbg_regs[21][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[21][31] <= dbg_regs[21][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][0] <= dbg_regs[20][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][1] <= dbg_regs[20][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][2] <= dbg_regs[20][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][3] <= dbg_regs[20][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][4] <= dbg_regs[20][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][5] <= dbg_regs[20][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][6] <= dbg_regs[20][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][7] <= dbg_regs[20][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][8] <= dbg_regs[20][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][9] <= dbg_regs[20][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][10] <= dbg_regs[20][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][11] <= dbg_regs[20][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][12] <= dbg_regs[20][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][13] <= dbg_regs[20][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][14] <= dbg_regs[20][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][15] <= dbg_regs[20][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][16] <= dbg_regs[20][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][17] <= dbg_regs[20][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][18] <= dbg_regs[20][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][19] <= dbg_regs[20][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][20] <= dbg_regs[20][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][21] <= dbg_regs[20][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][22] <= dbg_regs[20][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][23] <= dbg_regs[20][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][24] <= dbg_regs[20][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][25] <= dbg_regs[20][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][26] <= dbg_regs[20][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][27] <= dbg_regs[20][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][28] <= dbg_regs[20][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][29] <= dbg_regs[20][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][30] <= dbg_regs[20][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[20][31] <= dbg_regs[20][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][0] <= dbg_regs[19][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][1] <= dbg_regs[19][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][2] <= dbg_regs[19][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][3] <= dbg_regs[19][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][4] <= dbg_regs[19][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][5] <= dbg_regs[19][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][6] <= dbg_regs[19][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][7] <= dbg_regs[19][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][8] <= dbg_regs[19][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][9] <= dbg_regs[19][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][10] <= dbg_regs[19][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][11] <= dbg_regs[19][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][12] <= dbg_regs[19][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][13] <= dbg_regs[19][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][14] <= dbg_regs[19][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][15] <= dbg_regs[19][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][16] <= dbg_regs[19][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][17] <= dbg_regs[19][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][18] <= dbg_regs[19][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][19] <= dbg_regs[19][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][20] <= dbg_regs[19][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][21] <= dbg_regs[19][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][22] <= dbg_regs[19][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][23] <= dbg_regs[19][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][24] <= dbg_regs[19][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][25] <= dbg_regs[19][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][26] <= dbg_regs[19][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][27] <= dbg_regs[19][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][28] <= dbg_regs[19][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][29] <= dbg_regs[19][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][30] <= dbg_regs[19][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[19][31] <= dbg_regs[19][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][0] <= dbg_regs[18][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][1] <= dbg_regs[18][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][2] <= dbg_regs[18][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][3] <= dbg_regs[18][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][4] <= dbg_regs[18][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][5] <= dbg_regs[18][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][6] <= dbg_regs[18][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][7] <= dbg_regs[18][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][8] <= dbg_regs[18][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][9] <= dbg_regs[18][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][10] <= dbg_regs[18][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][11] <= dbg_regs[18][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][12] <= dbg_regs[18][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][13] <= dbg_regs[18][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][14] <= dbg_regs[18][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][15] <= dbg_regs[18][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][16] <= dbg_regs[18][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][17] <= dbg_regs[18][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][18] <= dbg_regs[18][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][19] <= dbg_regs[18][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][20] <= dbg_regs[18][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][21] <= dbg_regs[18][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][22] <= dbg_regs[18][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][23] <= dbg_regs[18][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][24] <= dbg_regs[18][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][25] <= dbg_regs[18][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][26] <= dbg_regs[18][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][27] <= dbg_regs[18][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][28] <= dbg_regs[18][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][29] <= dbg_regs[18][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][30] <= dbg_regs[18][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[18][31] <= dbg_regs[18][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][0] <= dbg_regs[17][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][1] <= dbg_regs[17][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][2] <= dbg_regs[17][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][3] <= dbg_regs[17][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][4] <= dbg_regs[17][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][5] <= dbg_regs[17][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][6] <= dbg_regs[17][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][7] <= dbg_regs[17][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][8] <= dbg_regs[17][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][9] <= dbg_regs[17][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][10] <= dbg_regs[17][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][11] <= dbg_regs[17][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][12] <= dbg_regs[17][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][13] <= dbg_regs[17][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][14] <= dbg_regs[17][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][15] <= dbg_regs[17][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][16] <= dbg_regs[17][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][17] <= dbg_regs[17][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][18] <= dbg_regs[17][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][19] <= dbg_regs[17][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][20] <= dbg_regs[17][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][21] <= dbg_regs[17][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][22] <= dbg_regs[17][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][23] <= dbg_regs[17][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][24] <= dbg_regs[17][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][25] <= dbg_regs[17][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][26] <= dbg_regs[17][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][27] <= dbg_regs[17][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][28] <= dbg_regs[17][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][29] <= dbg_regs[17][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][30] <= dbg_regs[17][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[17][31] <= dbg_regs[17][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][0] <= dbg_regs[16][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][1] <= dbg_regs[16][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][2] <= dbg_regs[16][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][3] <= dbg_regs[16][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][4] <= dbg_regs[16][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][5] <= dbg_regs[16][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][6] <= dbg_regs[16][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][7] <= dbg_regs[16][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][8] <= dbg_regs[16][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][9] <= dbg_regs[16][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][10] <= dbg_regs[16][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][11] <= dbg_regs[16][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][12] <= dbg_regs[16][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][13] <= dbg_regs[16][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][14] <= dbg_regs[16][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][15] <= dbg_regs[16][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][16] <= dbg_regs[16][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][17] <= dbg_regs[16][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][18] <= dbg_regs[16][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][19] <= dbg_regs[16][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][20] <= dbg_regs[16][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][21] <= dbg_regs[16][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][22] <= dbg_regs[16][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][23] <= dbg_regs[16][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][24] <= dbg_regs[16][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][25] <= dbg_regs[16][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][26] <= dbg_regs[16][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][27] <= dbg_regs[16][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][28] <= dbg_regs[16][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][29] <= dbg_regs[16][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][30] <= dbg_regs[16][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[16][31] <= dbg_regs[16][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][0] <= dbg_regs[15][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][1] <= dbg_regs[15][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][2] <= dbg_regs[15][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][3] <= dbg_regs[15][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][4] <= dbg_regs[15][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][5] <= dbg_regs[15][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][6] <= dbg_regs[15][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][7] <= dbg_regs[15][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][8] <= dbg_regs[15][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][9] <= dbg_regs[15][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][10] <= dbg_regs[15][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][11] <= dbg_regs[15][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][12] <= dbg_regs[15][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][13] <= dbg_regs[15][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][14] <= dbg_regs[15][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][15] <= dbg_regs[15][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][16] <= dbg_regs[15][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][17] <= dbg_regs[15][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][18] <= dbg_regs[15][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][19] <= dbg_regs[15][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][20] <= dbg_regs[15][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][21] <= dbg_regs[15][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][22] <= dbg_regs[15][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][23] <= dbg_regs[15][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][24] <= dbg_regs[15][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][25] <= dbg_regs[15][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][26] <= dbg_regs[15][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][27] <= dbg_regs[15][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][28] <= dbg_regs[15][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][29] <= dbg_regs[15][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][30] <= dbg_regs[15][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[15][31] <= dbg_regs[15][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][0] <= dbg_regs[14][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][1] <= dbg_regs[14][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][2] <= dbg_regs[14][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][3] <= dbg_regs[14][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][4] <= dbg_regs[14][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][5] <= dbg_regs[14][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][6] <= dbg_regs[14][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][7] <= dbg_regs[14][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][8] <= dbg_regs[14][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][9] <= dbg_regs[14][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][10] <= dbg_regs[14][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][11] <= dbg_regs[14][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][12] <= dbg_regs[14][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][13] <= dbg_regs[14][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][14] <= dbg_regs[14][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][15] <= dbg_regs[14][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][16] <= dbg_regs[14][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][17] <= dbg_regs[14][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][18] <= dbg_regs[14][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][19] <= dbg_regs[14][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][20] <= dbg_regs[14][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][21] <= dbg_regs[14][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][22] <= dbg_regs[14][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][23] <= dbg_regs[14][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][24] <= dbg_regs[14][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][25] <= dbg_regs[14][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][26] <= dbg_regs[14][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][27] <= dbg_regs[14][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][28] <= dbg_regs[14][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][29] <= dbg_regs[14][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][30] <= dbg_regs[14][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[14][31] <= dbg_regs[14][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][0] <= dbg_regs[13][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][1] <= dbg_regs[13][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][2] <= dbg_regs[13][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][3] <= dbg_regs[13][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][4] <= dbg_regs[13][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][5] <= dbg_regs[13][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][6] <= dbg_regs[13][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][7] <= dbg_regs[13][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][8] <= dbg_regs[13][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][9] <= dbg_regs[13][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][10] <= dbg_regs[13][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][11] <= dbg_regs[13][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][12] <= dbg_regs[13][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][13] <= dbg_regs[13][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][14] <= dbg_regs[13][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][15] <= dbg_regs[13][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][16] <= dbg_regs[13][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][17] <= dbg_regs[13][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][18] <= dbg_regs[13][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][19] <= dbg_regs[13][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][20] <= dbg_regs[13][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][21] <= dbg_regs[13][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][22] <= dbg_regs[13][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][23] <= dbg_regs[13][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][24] <= dbg_regs[13][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][25] <= dbg_regs[13][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][26] <= dbg_regs[13][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][27] <= dbg_regs[13][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][28] <= dbg_regs[13][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][29] <= dbg_regs[13][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][30] <= dbg_regs[13][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[13][31] <= dbg_regs[13][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][0] <= dbg_regs[12][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][1] <= dbg_regs[12][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][2] <= dbg_regs[12][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][3] <= dbg_regs[12][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][4] <= dbg_regs[12][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][5] <= dbg_regs[12][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][6] <= dbg_regs[12][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][7] <= dbg_regs[12][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][8] <= dbg_regs[12][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][9] <= dbg_regs[12][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][10] <= dbg_regs[12][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][11] <= dbg_regs[12][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][12] <= dbg_regs[12][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][13] <= dbg_regs[12][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][14] <= dbg_regs[12][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][15] <= dbg_regs[12][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][16] <= dbg_regs[12][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][17] <= dbg_regs[12][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][18] <= dbg_regs[12][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][19] <= dbg_regs[12][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][20] <= dbg_regs[12][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][21] <= dbg_regs[12][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][22] <= dbg_regs[12][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][23] <= dbg_regs[12][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][24] <= dbg_regs[12][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][25] <= dbg_regs[12][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][26] <= dbg_regs[12][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][27] <= dbg_regs[12][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][28] <= dbg_regs[12][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][29] <= dbg_regs[12][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][30] <= dbg_regs[12][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[12][31] <= dbg_regs[12][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][0] <= dbg_regs[11][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][1] <= dbg_regs[11][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][2] <= dbg_regs[11][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][3] <= dbg_regs[11][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][4] <= dbg_regs[11][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][5] <= dbg_regs[11][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][6] <= dbg_regs[11][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][7] <= dbg_regs[11][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][8] <= dbg_regs[11][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][9] <= dbg_regs[11][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][10] <= dbg_regs[11][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][11] <= dbg_regs[11][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][12] <= dbg_regs[11][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][13] <= dbg_regs[11][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][14] <= dbg_regs[11][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][15] <= dbg_regs[11][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][16] <= dbg_regs[11][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][17] <= dbg_regs[11][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][18] <= dbg_regs[11][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][19] <= dbg_regs[11][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][20] <= dbg_regs[11][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][21] <= dbg_regs[11][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][22] <= dbg_regs[11][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][23] <= dbg_regs[11][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][24] <= dbg_regs[11][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][25] <= dbg_regs[11][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][26] <= dbg_regs[11][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][27] <= dbg_regs[11][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][28] <= dbg_regs[11][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][29] <= dbg_regs[11][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][30] <= dbg_regs[11][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[11][31] <= dbg_regs[11][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][0] <= dbg_regs[10][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][1] <= dbg_regs[10][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][2] <= dbg_regs[10][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][3] <= dbg_regs[10][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][4] <= dbg_regs[10][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][5] <= dbg_regs[10][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][6] <= dbg_regs[10][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][7] <= dbg_regs[10][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][8] <= dbg_regs[10][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][9] <= dbg_regs[10][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][10] <= dbg_regs[10][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][11] <= dbg_regs[10][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][12] <= dbg_regs[10][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][13] <= dbg_regs[10][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][14] <= dbg_regs[10][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][15] <= dbg_regs[10][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][16] <= dbg_regs[10][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][17] <= dbg_regs[10][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][18] <= dbg_regs[10][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][19] <= dbg_regs[10][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][20] <= dbg_regs[10][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][21] <= dbg_regs[10][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][22] <= dbg_regs[10][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][23] <= dbg_regs[10][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][24] <= dbg_regs[10][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][25] <= dbg_regs[10][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][26] <= dbg_regs[10][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][27] <= dbg_regs[10][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][28] <= dbg_regs[10][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][29] <= dbg_regs[10][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][30] <= dbg_regs[10][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[10][31] <= dbg_regs[10][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][0] <= dbg_regs[9][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][1] <= dbg_regs[9][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][2] <= dbg_regs[9][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][3] <= dbg_regs[9][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][4] <= dbg_regs[9][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][5] <= dbg_regs[9][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][6] <= dbg_regs[9][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][7] <= dbg_regs[9][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][8] <= dbg_regs[9][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][9] <= dbg_regs[9][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][10] <= dbg_regs[9][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][11] <= dbg_regs[9][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][12] <= dbg_regs[9][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][13] <= dbg_regs[9][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][14] <= dbg_regs[9][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][15] <= dbg_regs[9][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][16] <= dbg_regs[9][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][17] <= dbg_regs[9][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][18] <= dbg_regs[9][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][19] <= dbg_regs[9][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][20] <= dbg_regs[9][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][21] <= dbg_regs[9][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][22] <= dbg_regs[9][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][23] <= dbg_regs[9][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][24] <= dbg_regs[9][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][25] <= dbg_regs[9][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][26] <= dbg_regs[9][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][27] <= dbg_regs[9][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][28] <= dbg_regs[9][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][29] <= dbg_regs[9][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][30] <= dbg_regs[9][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[9][31] <= dbg_regs[9][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][0] <= dbg_regs[8][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][1] <= dbg_regs[8][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][2] <= dbg_regs[8][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][3] <= dbg_regs[8][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][4] <= dbg_regs[8][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][5] <= dbg_regs[8][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][6] <= dbg_regs[8][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][7] <= dbg_regs[8][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][8] <= dbg_regs[8][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][9] <= dbg_regs[8][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][10] <= dbg_regs[8][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][11] <= dbg_regs[8][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][12] <= dbg_regs[8][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][13] <= dbg_regs[8][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][14] <= dbg_regs[8][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][15] <= dbg_regs[8][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][16] <= dbg_regs[8][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][17] <= dbg_regs[8][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][18] <= dbg_regs[8][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][19] <= dbg_regs[8][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][20] <= dbg_regs[8][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][21] <= dbg_regs[8][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][22] <= dbg_regs[8][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][23] <= dbg_regs[8][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][24] <= dbg_regs[8][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][25] <= dbg_regs[8][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][26] <= dbg_regs[8][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][27] <= dbg_regs[8][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][28] <= dbg_regs[8][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][29] <= dbg_regs[8][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][30] <= dbg_regs[8][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[8][31] <= dbg_regs[8][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][0] <= dbg_regs[7][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][1] <= dbg_regs[7][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][2] <= dbg_regs[7][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][3] <= dbg_regs[7][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][4] <= dbg_regs[7][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][5] <= dbg_regs[7][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][6] <= dbg_regs[7][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][7] <= dbg_regs[7][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][8] <= dbg_regs[7][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][9] <= dbg_regs[7][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][10] <= dbg_regs[7][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][11] <= dbg_regs[7][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][12] <= dbg_regs[7][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][13] <= dbg_regs[7][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][14] <= dbg_regs[7][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][15] <= dbg_regs[7][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][16] <= dbg_regs[7][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][17] <= dbg_regs[7][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][18] <= dbg_regs[7][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][19] <= dbg_regs[7][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][20] <= dbg_regs[7][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][21] <= dbg_regs[7][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][22] <= dbg_regs[7][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][23] <= dbg_regs[7][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][24] <= dbg_regs[7][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][25] <= dbg_regs[7][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][26] <= dbg_regs[7][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][27] <= dbg_regs[7][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][28] <= dbg_regs[7][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][29] <= dbg_regs[7][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][30] <= dbg_regs[7][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[7][31] <= dbg_regs[7][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][0] <= dbg_regs[6][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][1] <= dbg_regs[6][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][2] <= dbg_regs[6][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][3] <= dbg_regs[6][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][4] <= dbg_regs[6][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][5] <= dbg_regs[6][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][6] <= dbg_regs[6][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][7] <= dbg_regs[6][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][8] <= dbg_regs[6][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][9] <= dbg_regs[6][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][10] <= dbg_regs[6][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][11] <= dbg_regs[6][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][12] <= dbg_regs[6][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][13] <= dbg_regs[6][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][14] <= dbg_regs[6][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][15] <= dbg_regs[6][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][16] <= dbg_regs[6][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][17] <= dbg_regs[6][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][18] <= dbg_regs[6][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][19] <= dbg_regs[6][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][20] <= dbg_regs[6][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][21] <= dbg_regs[6][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][22] <= dbg_regs[6][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][23] <= dbg_regs[6][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][24] <= dbg_regs[6][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][25] <= dbg_regs[6][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][26] <= dbg_regs[6][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][27] <= dbg_regs[6][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][28] <= dbg_regs[6][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][29] <= dbg_regs[6][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][30] <= dbg_regs[6][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[6][31] <= dbg_regs[6][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][0] <= dbg_regs[5][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][1] <= dbg_regs[5][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][2] <= dbg_regs[5][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][3] <= dbg_regs[5][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][4] <= dbg_regs[5][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][5] <= dbg_regs[5][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][6] <= dbg_regs[5][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][7] <= dbg_regs[5][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][8] <= dbg_regs[5][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][9] <= dbg_regs[5][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][10] <= dbg_regs[5][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][11] <= dbg_regs[5][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][12] <= dbg_regs[5][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][13] <= dbg_regs[5][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][14] <= dbg_regs[5][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][15] <= dbg_regs[5][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][16] <= dbg_regs[5][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][17] <= dbg_regs[5][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][18] <= dbg_regs[5][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][19] <= dbg_regs[5][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][20] <= dbg_regs[5][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][21] <= dbg_regs[5][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][22] <= dbg_regs[5][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][23] <= dbg_regs[5][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][24] <= dbg_regs[5][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][25] <= dbg_regs[5][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][26] <= dbg_regs[5][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][27] <= dbg_regs[5][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][28] <= dbg_regs[5][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][29] <= dbg_regs[5][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][30] <= dbg_regs[5][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[5][31] <= dbg_regs[5][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][0] <= dbg_regs[4][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][1] <= dbg_regs[4][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][2] <= dbg_regs[4][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][3] <= dbg_regs[4][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][4] <= dbg_regs[4][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][5] <= dbg_regs[4][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][6] <= dbg_regs[4][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][7] <= dbg_regs[4][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][8] <= dbg_regs[4][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][9] <= dbg_regs[4][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][10] <= dbg_regs[4][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][11] <= dbg_regs[4][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][12] <= dbg_regs[4][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][13] <= dbg_regs[4][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][14] <= dbg_regs[4][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][15] <= dbg_regs[4][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][16] <= dbg_regs[4][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][17] <= dbg_regs[4][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][18] <= dbg_regs[4][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][19] <= dbg_regs[4][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][20] <= dbg_regs[4][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][21] <= dbg_regs[4][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][22] <= dbg_regs[4][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][23] <= dbg_regs[4][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][24] <= dbg_regs[4][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][25] <= dbg_regs[4][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][26] <= dbg_regs[4][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][27] <= dbg_regs[4][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][28] <= dbg_regs[4][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][29] <= dbg_regs[4][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][30] <= dbg_regs[4][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[4][31] <= dbg_regs[4][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][0] <= dbg_regs[3][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][1] <= dbg_regs[3][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][2] <= dbg_regs[3][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][3] <= dbg_regs[3][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][4] <= dbg_regs[3][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][5] <= dbg_regs[3][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][6] <= dbg_regs[3][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][7] <= dbg_regs[3][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][8] <= dbg_regs[3][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][9] <= dbg_regs[3][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][10] <= dbg_regs[3][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][11] <= dbg_regs[3][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][12] <= dbg_regs[3][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][13] <= dbg_regs[3][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][14] <= dbg_regs[3][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][15] <= dbg_regs[3][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][16] <= dbg_regs[3][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][17] <= dbg_regs[3][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][18] <= dbg_regs[3][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][19] <= dbg_regs[3][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][20] <= dbg_regs[3][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][21] <= dbg_regs[3][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][22] <= dbg_regs[3][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][23] <= dbg_regs[3][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][24] <= dbg_regs[3][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][25] <= dbg_regs[3][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][26] <= dbg_regs[3][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][27] <= dbg_regs[3][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][28] <= dbg_regs[3][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][29] <= dbg_regs[3][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][30] <= dbg_regs[3][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[3][31] <= dbg_regs[3][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][0] <= dbg_regs[2][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][1] <= dbg_regs[2][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][2] <= dbg_regs[2][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][3] <= dbg_regs[2][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][4] <= dbg_regs[2][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][5] <= dbg_regs[2][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][6] <= dbg_regs[2][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][7] <= dbg_regs[2][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][8] <= dbg_regs[2][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][9] <= dbg_regs[2][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][10] <= dbg_regs[2][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][11] <= dbg_regs[2][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][12] <= dbg_regs[2][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][13] <= dbg_regs[2][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][14] <= dbg_regs[2][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][15] <= dbg_regs[2][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][16] <= dbg_regs[2][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][17] <= dbg_regs[2][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][18] <= dbg_regs[2][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][19] <= dbg_regs[2][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][20] <= dbg_regs[2][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][21] <= dbg_regs[2][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][22] <= dbg_regs[2][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][23] <= dbg_regs[2][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][24] <= dbg_regs[2][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][25] <= dbg_regs[2][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][26] <= dbg_regs[2][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][27] <= dbg_regs[2][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][28] <= dbg_regs[2][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][29] <= dbg_regs[2][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][30] <= dbg_regs[2][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[2][31] <= dbg_regs[2][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][0] <= dbg_regs[1][0].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][1] <= dbg_regs[1][1].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][2] <= dbg_regs[1][2].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][3] <= dbg_regs[1][3].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][4] <= dbg_regs[1][4].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][5] <= dbg_regs[1][5].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][6] <= dbg_regs[1][6].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][7] <= dbg_regs[1][7].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][8] <= dbg_regs[1][8].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][9] <= dbg_regs[1][9].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][10] <= dbg_regs[1][10].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][11] <= dbg_regs[1][11].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][12] <= dbg_regs[1][12].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][13] <= dbg_regs[1][13].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][14] <= dbg_regs[1][14].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][15] <= dbg_regs[1][15].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][16] <= dbg_regs[1][16].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][17] <= dbg_regs[1][17].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][18] <= dbg_regs[1][18].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][19] <= dbg_regs[1][19].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][20] <= dbg_regs[1][20].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][21] <= dbg_regs[1][21].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][22] <= dbg_regs[1][22].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][23] <= dbg_regs[1][23].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][24] <= dbg_regs[1][24].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][25] <= dbg_regs[1][25].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][26] <= dbg_regs[1][26].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][27] <= dbg_regs[1][27].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][28] <= dbg_regs[1][28].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][29] <= dbg_regs[1][29].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][30] <= dbg_regs[1][30].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[1][31] <= dbg_regs[1][31].DB_MAX_OUTPUT_PORT_TYPE +dbg_regs[0][0] <= +dbg_regs[0][1] <= +dbg_regs[0][2] <= +dbg_regs[0][3] <= +dbg_regs[0][4] <= +dbg_regs[0][5] <= +dbg_regs[0][6] <= +dbg_regs[0][7] <= +dbg_regs[0][8] <= +dbg_regs[0][9] <= +dbg_regs[0][10] <= +dbg_regs[0][11] <= +dbg_regs[0][12] <= +dbg_regs[0][13] <= +dbg_regs[0][14] <= +dbg_regs[0][15] <= +dbg_regs[0][16] <= +dbg_regs[0][17] <= +dbg_regs[0][18] <= +dbg_regs[0][19] <= +dbg_regs[0][20] <= +dbg_regs[0][21] <= +dbg_regs[0][22] <= +dbg_regs[0][23] <= +dbg_regs[0][24] <= +dbg_regs[0][25] <= +dbg_regs[0][26] <= +dbg_regs[0][27] <= +dbg_regs[0][28] <= +dbg_regs[0][29] <= +dbg_regs[0][30] <= +dbg_regs[0][31] <= + + +|top|utoss_riscv:core|ALU:alu +a[0] => Add0.IN32 +a[0] => Add1.IN64 +a[0] => ShiftLeft0.IN32 +a[0] => LessThan0.IN32 +a[0] => LessThan1.IN32 +a[0] => out.IN0 +a[0] => ShiftRight0.IN32 +a[0] => ShiftRight1.IN32 +a[0] => out.IN0 +a[0] => out.IN0 +a[0] => LessThan2.IN32 +a[0] => LessThan3.IN32 +a[1] => Add0.IN31 +a[1] => Add1.IN63 +a[1] => ShiftLeft0.IN31 +a[1] => LessThan0.IN31 +a[1] => LessThan1.IN31 +a[1] => out.IN0 +a[1] => ShiftRight0.IN31 +a[1] => ShiftRight1.IN31 +a[1] => out.IN0 +a[1] => out.IN0 +a[1] => LessThan2.IN31 +a[1] => LessThan3.IN31 +a[2] => Add0.IN30 +a[2] => Add1.IN62 +a[2] => ShiftLeft0.IN30 +a[2] => LessThan0.IN30 +a[2] => LessThan1.IN30 +a[2] => out.IN0 +a[2] => ShiftRight0.IN30 +a[2] => ShiftRight1.IN30 +a[2] => out.IN0 +a[2] => out.IN0 +a[2] => LessThan2.IN30 +a[2] => LessThan3.IN30 +a[3] => Add0.IN29 +a[3] => Add1.IN61 +a[3] => ShiftLeft0.IN29 +a[3] => LessThan0.IN29 +a[3] => LessThan1.IN29 +a[3] => out.IN0 +a[3] => ShiftRight0.IN29 +a[3] => ShiftRight1.IN29 +a[3] => out.IN0 +a[3] => out.IN0 +a[3] => LessThan2.IN29 +a[3] => LessThan3.IN29 +a[4] => Add0.IN28 +a[4] => Add1.IN60 +a[4] => ShiftLeft0.IN28 +a[4] => LessThan0.IN28 +a[4] => LessThan1.IN28 +a[4] => out.IN0 +a[4] => ShiftRight0.IN28 +a[4] => ShiftRight1.IN28 +a[4] => out.IN0 +a[4] => out.IN0 +a[4] => LessThan2.IN28 +a[4] => LessThan3.IN28 +a[5] => Add0.IN27 +a[5] => Add1.IN59 +a[5] => ShiftLeft0.IN27 +a[5] => LessThan0.IN27 +a[5] => LessThan1.IN27 +a[5] => out.IN0 +a[5] => ShiftRight0.IN27 +a[5] => ShiftRight1.IN27 +a[5] => out.IN0 +a[5] => out.IN0 +a[5] => LessThan2.IN27 +a[5] => LessThan3.IN27 +a[6] => Add0.IN26 +a[6] => Add1.IN58 +a[6] => ShiftLeft0.IN26 +a[6] => LessThan0.IN26 +a[6] => LessThan1.IN26 +a[6] => out.IN0 +a[6] => ShiftRight0.IN26 +a[6] => ShiftRight1.IN26 +a[6] => out.IN0 +a[6] => out.IN0 +a[6] => LessThan2.IN26 +a[6] => LessThan3.IN26 +a[7] => Add0.IN25 +a[7] => Add1.IN57 +a[7] => ShiftLeft0.IN25 +a[7] => LessThan0.IN25 +a[7] => LessThan1.IN25 +a[7] => out.IN0 +a[7] => ShiftRight0.IN25 +a[7] => ShiftRight1.IN25 +a[7] => out.IN0 +a[7] => out.IN0 +a[7] => LessThan2.IN25 +a[7] => LessThan3.IN25 +a[8] => Add0.IN24 +a[8] => Add1.IN56 +a[8] => ShiftLeft0.IN24 +a[8] => LessThan0.IN24 +a[8] => LessThan1.IN24 +a[8] => out.IN0 +a[8] => ShiftRight0.IN24 +a[8] => ShiftRight1.IN24 +a[8] => out.IN0 +a[8] => out.IN0 +a[8] => LessThan2.IN24 +a[8] => LessThan3.IN24 +a[9] => Add0.IN23 +a[9] => Add1.IN55 +a[9] => ShiftLeft0.IN23 +a[9] => LessThan0.IN23 +a[9] => LessThan1.IN23 +a[9] => out.IN0 +a[9] => ShiftRight0.IN23 +a[9] => ShiftRight1.IN23 +a[9] => out.IN0 +a[9] => out.IN0 +a[9] => LessThan2.IN23 +a[9] => LessThan3.IN23 +a[10] => Add0.IN22 +a[10] => Add1.IN54 +a[10] => ShiftLeft0.IN22 +a[10] => LessThan0.IN22 +a[10] => LessThan1.IN22 +a[10] => out.IN0 +a[10] => ShiftRight0.IN22 +a[10] => ShiftRight1.IN22 +a[10] => out.IN0 +a[10] => out.IN0 +a[10] => LessThan2.IN22 +a[10] => LessThan3.IN22 +a[11] => Add0.IN21 +a[11] => Add1.IN53 +a[11] => ShiftLeft0.IN21 +a[11] => LessThan0.IN21 +a[11] => LessThan1.IN21 +a[11] => out.IN0 +a[11] => ShiftRight0.IN21 +a[11] => ShiftRight1.IN21 +a[11] => out.IN0 +a[11] => out.IN0 +a[11] => LessThan2.IN21 +a[11] => LessThan3.IN21 +a[12] => Add0.IN20 +a[12] => Add1.IN52 +a[12] => ShiftLeft0.IN20 +a[12] => LessThan0.IN20 +a[12] => LessThan1.IN20 +a[12] => out.IN0 +a[12] => ShiftRight0.IN20 +a[12] => ShiftRight1.IN20 +a[12] => out.IN0 +a[12] => out.IN0 +a[12] => LessThan2.IN20 +a[12] => LessThan3.IN20 +a[13] => Add0.IN19 +a[13] => Add1.IN51 +a[13] => ShiftLeft0.IN19 +a[13] => LessThan0.IN19 +a[13] => LessThan1.IN19 +a[13] => out.IN0 +a[13] => ShiftRight0.IN19 +a[13] => ShiftRight1.IN19 +a[13] => out.IN0 +a[13] => out.IN0 +a[13] => LessThan2.IN19 +a[13] => LessThan3.IN19 +a[14] => Add0.IN18 +a[14] => Add1.IN50 +a[14] => ShiftLeft0.IN18 +a[14] => LessThan0.IN18 +a[14] => LessThan1.IN18 +a[14] => out.IN0 +a[14] => ShiftRight0.IN18 +a[14] => ShiftRight1.IN18 +a[14] => out.IN0 +a[14] => out.IN0 +a[14] => LessThan2.IN18 +a[14] => LessThan3.IN18 +a[15] => Add0.IN17 +a[15] => Add1.IN49 +a[15] => ShiftLeft0.IN17 +a[15] => LessThan0.IN17 +a[15] => LessThan1.IN17 +a[15] => out.IN0 +a[15] => ShiftRight0.IN17 +a[15] => ShiftRight1.IN17 +a[15] => out.IN0 +a[15] => out.IN0 +a[15] => LessThan2.IN17 +a[15] => LessThan3.IN17 +a[16] => Add0.IN16 +a[16] => Add1.IN48 +a[16] => ShiftLeft0.IN16 +a[16] => LessThan0.IN16 +a[16] => LessThan1.IN16 +a[16] => out.IN0 +a[16] => ShiftRight0.IN16 +a[16] => ShiftRight1.IN16 +a[16] => out.IN0 +a[16] => out.IN0 +a[16] => LessThan2.IN16 +a[16] => LessThan3.IN16 +a[17] => Add0.IN15 +a[17] => Add1.IN47 +a[17] => ShiftLeft0.IN15 +a[17] => LessThan0.IN15 +a[17] => LessThan1.IN15 +a[17] => out.IN0 +a[17] => ShiftRight0.IN15 +a[17] => ShiftRight1.IN15 +a[17] => out.IN0 +a[17] => out.IN0 +a[17] => LessThan2.IN15 +a[17] => LessThan3.IN15 +a[18] => Add0.IN14 +a[18] => Add1.IN46 +a[18] => ShiftLeft0.IN14 +a[18] => LessThan0.IN14 +a[18] => LessThan1.IN14 +a[18] => out.IN0 +a[18] => ShiftRight0.IN14 +a[18] => ShiftRight1.IN14 +a[18] => out.IN0 +a[18] => out.IN0 +a[18] => LessThan2.IN14 +a[18] => LessThan3.IN14 +a[19] => Add0.IN13 +a[19] => Add1.IN45 +a[19] => ShiftLeft0.IN13 +a[19] => LessThan0.IN13 +a[19] => LessThan1.IN13 +a[19] => out.IN0 +a[19] => ShiftRight0.IN13 +a[19] => ShiftRight1.IN13 +a[19] => out.IN0 +a[19] => out.IN0 +a[19] => LessThan2.IN13 +a[19] => LessThan3.IN13 +a[20] => Add0.IN12 +a[20] => Add1.IN44 +a[20] => ShiftLeft0.IN12 +a[20] => LessThan0.IN12 +a[20] => LessThan1.IN12 +a[20] => out.IN0 +a[20] => ShiftRight0.IN12 +a[20] => ShiftRight1.IN12 +a[20] => out.IN0 +a[20] => out.IN0 +a[20] => LessThan2.IN12 +a[20] => LessThan3.IN12 +a[21] => Add0.IN11 +a[21] => Add1.IN43 +a[21] => ShiftLeft0.IN11 +a[21] => LessThan0.IN11 +a[21] => LessThan1.IN11 +a[21] => out.IN0 +a[21] => ShiftRight0.IN11 +a[21] => ShiftRight1.IN11 +a[21] => out.IN0 +a[21] => out.IN0 +a[21] => LessThan2.IN11 +a[21] => LessThan3.IN11 +a[22] => Add0.IN10 +a[22] => Add1.IN42 +a[22] => ShiftLeft0.IN10 +a[22] => LessThan0.IN10 +a[22] => LessThan1.IN10 +a[22] => out.IN0 +a[22] => ShiftRight0.IN10 +a[22] => ShiftRight1.IN10 +a[22] => out.IN0 +a[22] => out.IN0 +a[22] => LessThan2.IN10 +a[22] => LessThan3.IN10 +a[23] => Add0.IN9 +a[23] => Add1.IN41 +a[23] => ShiftLeft0.IN9 +a[23] => LessThan0.IN9 +a[23] => LessThan1.IN9 +a[23] => out.IN0 +a[23] => ShiftRight0.IN9 +a[23] => ShiftRight1.IN9 +a[23] => out.IN0 +a[23] => out.IN0 +a[23] => LessThan2.IN9 +a[23] => LessThan3.IN9 +a[24] => Add0.IN8 +a[24] => Add1.IN40 +a[24] => ShiftLeft0.IN8 +a[24] => LessThan0.IN8 +a[24] => LessThan1.IN8 +a[24] => out.IN0 +a[24] => ShiftRight0.IN8 +a[24] => ShiftRight1.IN8 +a[24] => out.IN0 +a[24] => out.IN0 +a[24] => LessThan2.IN8 +a[24] => LessThan3.IN8 +a[25] => Add0.IN7 +a[25] => Add1.IN39 +a[25] => ShiftLeft0.IN7 +a[25] => LessThan0.IN7 +a[25] => LessThan1.IN7 +a[25] => out.IN0 +a[25] => ShiftRight0.IN7 +a[25] => ShiftRight1.IN7 +a[25] => out.IN0 +a[25] => out.IN0 +a[25] => LessThan2.IN7 +a[25] => LessThan3.IN7 +a[26] => Add0.IN6 +a[26] => Add1.IN38 +a[26] => ShiftLeft0.IN6 +a[26] => LessThan0.IN6 +a[26] => LessThan1.IN6 +a[26] => out.IN0 +a[26] => ShiftRight0.IN6 +a[26] => ShiftRight1.IN6 +a[26] => out.IN0 +a[26] => out.IN0 +a[26] => LessThan2.IN6 +a[26] => LessThan3.IN6 +a[27] => Add0.IN5 +a[27] => Add1.IN37 +a[27] => ShiftLeft0.IN5 +a[27] => LessThan0.IN5 +a[27] => LessThan1.IN5 +a[27] => out.IN0 +a[27] => ShiftRight0.IN5 +a[27] => ShiftRight1.IN5 +a[27] => out.IN0 +a[27] => out.IN0 +a[27] => LessThan2.IN5 +a[27] => LessThan3.IN5 +a[28] => Add0.IN4 +a[28] => Add1.IN36 +a[28] => ShiftLeft0.IN4 +a[28] => LessThan0.IN4 +a[28] => LessThan1.IN4 +a[28] => out.IN0 +a[28] => ShiftRight0.IN4 +a[28] => ShiftRight1.IN4 +a[28] => out.IN0 +a[28] => out.IN0 +a[28] => LessThan2.IN4 +a[28] => LessThan3.IN4 +a[29] => Add0.IN3 +a[29] => Add1.IN35 +a[29] => ShiftLeft0.IN3 +a[29] => LessThan0.IN3 +a[29] => LessThan1.IN3 +a[29] => out.IN0 +a[29] => ShiftRight0.IN3 +a[29] => ShiftRight1.IN3 +a[29] => out.IN0 +a[29] => out.IN0 +a[29] => LessThan2.IN3 +a[29] => LessThan3.IN3 +a[30] => Add0.IN2 +a[30] => Add1.IN34 +a[30] => ShiftLeft0.IN2 +a[30] => LessThan0.IN2 +a[30] => LessThan1.IN2 +a[30] => out.IN0 +a[30] => ShiftRight0.IN2 +a[30] => ShiftRight1.IN2 +a[30] => out.IN0 +a[30] => out.IN0 +a[30] => LessThan2.IN2 +a[30] => LessThan3.IN2 +a[31] => Add0.IN1 +a[31] => Add1.IN33 +a[31] => ShiftLeft0.IN1 +a[31] => LessThan0.IN1 +a[31] => LessThan1.IN1 +a[31] => out.IN0 +a[31] => ShiftRight0.IN1 +a[31] => ShiftRight1.IN0 +a[31] => ShiftRight1.IN1 +a[31] => out.IN0 +a[31] => out.IN0 +a[31] => LessThan2.IN1 +a[31] => LessThan3.IN1 +b[0] => Add0.IN64 +b[0] => ShiftLeft0.IN37 +b[0] => LessThan0.IN64 +b[0] => LessThan1.IN64 +b[0] => out.IN1 +b[0] => ShiftRight0.IN37 +b[0] => ShiftRight1.IN37 +b[0] => out.IN1 +b[0] => out.IN1 +b[0] => LessThan2.IN64 +b[0] => LessThan3.IN64 +b[0] => Add1.IN32 +b[1] => Add0.IN63 +b[1] => ShiftLeft0.IN36 +b[1] => LessThan0.IN63 +b[1] => LessThan1.IN63 +b[1] => out.IN1 +b[1] => ShiftRight0.IN36 +b[1] => ShiftRight1.IN36 +b[1] => out.IN1 +b[1] => out.IN1 +b[1] => LessThan2.IN63 +b[1] => LessThan3.IN63 +b[1] => Add1.IN31 +b[2] => Add0.IN62 +b[2] => ShiftLeft0.IN35 +b[2] => LessThan0.IN62 +b[2] => LessThan1.IN62 +b[2] => out.IN1 +b[2] => ShiftRight0.IN35 +b[2] => ShiftRight1.IN35 +b[2] => out.IN1 +b[2] => out.IN1 +b[2] => LessThan2.IN62 +b[2] => LessThan3.IN62 +b[2] => Add1.IN30 +b[3] => Add0.IN61 +b[3] => ShiftLeft0.IN34 +b[3] => LessThan0.IN61 +b[3] => LessThan1.IN61 +b[3] => out.IN1 +b[3] => ShiftRight0.IN34 +b[3] => ShiftRight1.IN34 +b[3] => out.IN1 +b[3] => out.IN1 +b[3] => LessThan2.IN61 +b[3] => LessThan3.IN61 +b[3] => Add1.IN29 +b[4] => Add0.IN60 +b[4] => ShiftLeft0.IN33 +b[4] => LessThan0.IN60 +b[4] => LessThan1.IN60 +b[4] => out.IN1 +b[4] => ShiftRight0.IN33 +b[4] => ShiftRight1.IN33 +b[4] => out.IN1 +b[4] => out.IN1 +b[4] => LessThan2.IN60 +b[4] => LessThan3.IN60 +b[4] => Add1.IN28 +b[5] => Add0.IN59 +b[5] => LessThan0.IN59 +b[5] => LessThan1.IN59 +b[5] => out.IN1 +b[5] => out.IN1 +b[5] => out.IN1 +b[5] => LessThan2.IN59 +b[5] => LessThan3.IN59 +b[5] => Add1.IN27 +b[6] => Add0.IN58 +b[6] => LessThan0.IN58 +b[6] => LessThan1.IN58 +b[6] => out.IN1 +b[6] => out.IN1 +b[6] => out.IN1 +b[6] => LessThan2.IN58 +b[6] => LessThan3.IN58 +b[6] => Add1.IN26 +b[7] => Add0.IN57 +b[7] => LessThan0.IN57 +b[7] => LessThan1.IN57 +b[7] => out.IN1 +b[7] => out.IN1 +b[7] => out.IN1 +b[7] => LessThan2.IN57 +b[7] => LessThan3.IN57 +b[7] => Add1.IN25 +b[8] => Add0.IN56 +b[8] => LessThan0.IN56 +b[8] => LessThan1.IN56 +b[8] => out.IN1 +b[8] => out.IN1 +b[8] => out.IN1 +b[8] => LessThan2.IN56 +b[8] => LessThan3.IN56 +b[8] => Add1.IN24 +b[9] => Add0.IN55 +b[9] => LessThan0.IN55 +b[9] => LessThan1.IN55 +b[9] => out.IN1 +b[9] => out.IN1 +b[9] => out.IN1 +b[9] => LessThan2.IN55 +b[9] => LessThan3.IN55 +b[9] => Add1.IN23 +b[10] => Add0.IN54 +b[10] => LessThan0.IN54 +b[10] => LessThan1.IN54 +b[10] => out.IN1 +b[10] => out.IN1 +b[10] => out.IN1 +b[10] => LessThan2.IN54 +b[10] => LessThan3.IN54 +b[10] => Add1.IN22 +b[11] => Add0.IN53 +b[11] => LessThan0.IN53 +b[11] => LessThan1.IN53 +b[11] => out.IN1 +b[11] => out.IN1 +b[11] => out.IN1 +b[11] => LessThan2.IN53 +b[11] => LessThan3.IN53 +b[11] => Add1.IN21 +b[12] => Add0.IN52 +b[12] => LessThan0.IN52 +b[12] => LessThan1.IN52 +b[12] => out.IN1 +b[12] => out.IN1 +b[12] => out.IN1 +b[12] => LessThan2.IN52 +b[12] => LessThan3.IN52 +b[12] => Add1.IN20 +b[13] => Add0.IN51 +b[13] => LessThan0.IN51 +b[13] => LessThan1.IN51 +b[13] => out.IN1 +b[13] => out.IN1 +b[13] => out.IN1 +b[13] => LessThan2.IN51 +b[13] => LessThan3.IN51 +b[13] => Add1.IN19 +b[14] => Add0.IN50 +b[14] => LessThan0.IN50 +b[14] => LessThan1.IN50 +b[14] => out.IN1 +b[14] => out.IN1 +b[14] => out.IN1 +b[14] => LessThan2.IN50 +b[14] => LessThan3.IN50 +b[14] => Add1.IN18 +b[15] => Add0.IN49 +b[15] => LessThan0.IN49 +b[15] => LessThan1.IN49 +b[15] => out.IN1 +b[15] => out.IN1 +b[15] => out.IN1 +b[15] => LessThan2.IN49 +b[15] => LessThan3.IN49 +b[15] => Add1.IN17 +b[16] => Add0.IN48 +b[16] => LessThan0.IN48 +b[16] => LessThan1.IN48 +b[16] => out.IN1 +b[16] => out.IN1 +b[16] => out.IN1 +b[16] => LessThan2.IN48 +b[16] => LessThan3.IN48 +b[16] => Add1.IN16 +b[17] => Add0.IN47 +b[17] => LessThan0.IN47 +b[17] => LessThan1.IN47 +b[17] => out.IN1 +b[17] => out.IN1 +b[17] => out.IN1 +b[17] => LessThan2.IN47 +b[17] => LessThan3.IN47 +b[17] => Add1.IN15 +b[18] => Add0.IN46 +b[18] => LessThan0.IN46 +b[18] => LessThan1.IN46 +b[18] => out.IN1 +b[18] => out.IN1 +b[18] => out.IN1 +b[18] => LessThan2.IN46 +b[18] => LessThan3.IN46 +b[18] => Add1.IN14 +b[19] => Add0.IN45 +b[19] => LessThan0.IN45 +b[19] => LessThan1.IN45 +b[19] => out.IN1 +b[19] => out.IN1 +b[19] => out.IN1 +b[19] => LessThan2.IN45 +b[19] => LessThan3.IN45 +b[19] => Add1.IN13 +b[20] => Add0.IN44 +b[20] => LessThan0.IN44 +b[20] => LessThan1.IN44 +b[20] => out.IN1 +b[20] => out.IN1 +b[20] => out.IN1 +b[20] => LessThan2.IN44 +b[20] => LessThan3.IN44 +b[20] => Add1.IN12 +b[21] => Add0.IN43 +b[21] => LessThan0.IN43 +b[21] => LessThan1.IN43 +b[21] => out.IN1 +b[21] => out.IN1 +b[21] => out.IN1 +b[21] => LessThan2.IN43 +b[21] => LessThan3.IN43 +b[21] => Add1.IN11 +b[22] => Add0.IN42 +b[22] => LessThan0.IN42 +b[22] => LessThan1.IN42 +b[22] => out.IN1 +b[22] => out.IN1 +b[22] => out.IN1 +b[22] => LessThan2.IN42 +b[22] => LessThan3.IN42 +b[22] => Add1.IN10 +b[23] => Add0.IN41 +b[23] => LessThan0.IN41 +b[23] => LessThan1.IN41 +b[23] => out.IN1 +b[23] => out.IN1 +b[23] => out.IN1 +b[23] => LessThan2.IN41 +b[23] => LessThan3.IN41 +b[23] => Add1.IN9 +b[24] => Add0.IN40 +b[24] => LessThan0.IN40 +b[24] => LessThan1.IN40 +b[24] => out.IN1 +b[24] => out.IN1 +b[24] => out.IN1 +b[24] => LessThan2.IN40 +b[24] => LessThan3.IN40 +b[24] => Add1.IN8 +b[25] => Add0.IN39 +b[25] => LessThan0.IN39 +b[25] => LessThan1.IN39 +b[25] => out.IN1 +b[25] => out.IN1 +b[25] => out.IN1 +b[25] => LessThan2.IN39 +b[25] => LessThan3.IN39 +b[25] => Add1.IN7 +b[26] => Add0.IN38 +b[26] => LessThan0.IN38 +b[26] => LessThan1.IN38 +b[26] => out.IN1 +b[26] => out.IN1 +b[26] => out.IN1 +b[26] => LessThan2.IN38 +b[26] => LessThan3.IN38 +b[26] => Add1.IN6 +b[27] => Add0.IN37 +b[27] => LessThan0.IN37 +b[27] => LessThan1.IN37 +b[27] => out.IN1 +b[27] => out.IN1 +b[27] => out.IN1 +b[27] => LessThan2.IN37 +b[27] => LessThan3.IN37 +b[27] => Add1.IN5 +b[28] => Add0.IN36 +b[28] => LessThan0.IN36 +b[28] => LessThan1.IN36 +b[28] => out.IN1 +b[28] => out.IN1 +b[28] => out.IN1 +b[28] => LessThan2.IN36 +b[28] => LessThan3.IN36 +b[28] => Add1.IN4 +b[29] => Add0.IN35 +b[29] => LessThan0.IN35 +b[29] => LessThan1.IN35 +b[29] => out.IN1 +b[29] => out.IN1 +b[29] => out.IN1 +b[29] => LessThan2.IN35 +b[29] => LessThan3.IN35 +b[29] => Add1.IN3 +b[30] => Add0.IN34 +b[30] => LessThan0.IN34 +b[30] => LessThan1.IN34 +b[30] => out.IN1 +b[30] => out.IN1 +b[30] => out.IN1 +b[30] => LessThan2.IN34 +b[30] => LessThan3.IN34 +b[30] => Add1.IN2 +b[31] => Add0.IN33 +b[31] => LessThan0.IN33 +b[31] => LessThan1.IN33 +b[31] => out.IN1 +b[31] => out.IN1 +b[31] => out.IN1 +b[31] => LessThan2.IN33 +b[31] => LessThan3.IN33 +b[31] => Add1.IN1 +alu_control[0] => Mux0.IN19 +alu_control[0] => Mux1.IN19 +alu_control[0] => Mux2.IN19 +alu_control[0] => Mux3.IN19 +alu_control[0] => Mux4.IN19 +alu_control[0] => Mux5.IN19 +alu_control[0] => Mux6.IN19 +alu_control[0] => Mux7.IN19 +alu_control[0] => Mux8.IN19 +alu_control[0] => Mux9.IN19 +alu_control[0] => Mux10.IN19 +alu_control[0] => Mux11.IN19 +alu_control[0] => Mux12.IN19 +alu_control[0] => Mux13.IN19 +alu_control[0] => Mux14.IN19 +alu_control[0] => Mux15.IN19 +alu_control[0] => Mux16.IN19 +alu_control[0] => Mux17.IN19 +alu_control[0] => Mux18.IN19 +alu_control[0] => Mux19.IN19 +alu_control[0] => Mux20.IN19 +alu_control[0] => Mux21.IN19 +alu_control[0] => Mux22.IN19 +alu_control[0] => Mux23.IN19 +alu_control[0] => Mux24.IN19 +alu_control[0] => Mux25.IN19 +alu_control[0] => Mux26.IN19 +alu_control[0] => Mux27.IN19 +alu_control[0] => Mux28.IN19 +alu_control[0] => Mux29.IN19 +alu_control[0] => Mux30.IN19 +alu_control[0] => Mux31.IN19 +alu_control[1] => Mux0.IN18 +alu_control[1] => Mux1.IN18 +alu_control[1] => Mux2.IN18 +alu_control[1] => Mux3.IN18 +alu_control[1] => Mux4.IN18 +alu_control[1] => Mux5.IN18 +alu_control[1] => Mux6.IN18 +alu_control[1] => Mux7.IN18 +alu_control[1] => Mux8.IN18 +alu_control[1] => Mux9.IN18 +alu_control[1] => Mux10.IN18 +alu_control[1] => Mux11.IN18 +alu_control[1] => Mux12.IN18 +alu_control[1] => Mux13.IN18 +alu_control[1] => Mux14.IN18 +alu_control[1] => Mux15.IN18 +alu_control[1] => Mux16.IN18 +alu_control[1] => Mux17.IN18 +alu_control[1] => Mux18.IN18 +alu_control[1] => Mux19.IN18 +alu_control[1] => Mux20.IN18 +alu_control[1] => Mux21.IN18 +alu_control[1] => Mux22.IN18 +alu_control[1] => Mux23.IN18 +alu_control[1] => Mux24.IN18 +alu_control[1] => Mux25.IN18 +alu_control[1] => Mux26.IN18 +alu_control[1] => Mux27.IN18 +alu_control[1] => Mux28.IN18 +alu_control[1] => Mux29.IN18 +alu_control[1] => Mux30.IN18 +alu_control[1] => Mux31.IN18 +alu_control[2] => Mux0.IN17 +alu_control[2] => Mux1.IN17 +alu_control[2] => Mux2.IN17 +alu_control[2] => Mux3.IN17 +alu_control[2] => Mux4.IN17 +alu_control[2] => Mux5.IN17 +alu_control[2] => Mux6.IN17 +alu_control[2] => Mux7.IN17 +alu_control[2] => Mux8.IN17 +alu_control[2] => Mux9.IN17 +alu_control[2] => Mux10.IN17 +alu_control[2] => Mux11.IN17 +alu_control[2] => Mux12.IN17 +alu_control[2] => Mux13.IN17 +alu_control[2] => Mux14.IN17 +alu_control[2] => Mux15.IN17 +alu_control[2] => Mux16.IN17 +alu_control[2] => Mux17.IN17 +alu_control[2] => Mux18.IN17 +alu_control[2] => Mux19.IN17 +alu_control[2] => Mux20.IN17 +alu_control[2] => Mux21.IN17 +alu_control[2] => Mux22.IN17 +alu_control[2] => Mux23.IN17 +alu_control[2] => Mux24.IN17 +alu_control[2] => Mux25.IN17 +alu_control[2] => Mux26.IN17 +alu_control[2] => Mux27.IN17 +alu_control[2] => Mux28.IN17 +alu_control[2] => Mux29.IN17 +alu_control[2] => Mux30.IN17 +alu_control[2] => Mux31.IN17 +alu_control[3] => Mux0.IN16 +alu_control[3] => Mux1.IN16 +alu_control[3] => Mux2.IN16 +alu_control[3] => Mux3.IN16 +alu_control[3] => Mux4.IN16 +alu_control[3] => Mux5.IN16 +alu_control[3] => Mux6.IN16 +alu_control[3] => Mux7.IN16 +alu_control[3] => Mux8.IN16 +alu_control[3] => Mux9.IN16 +alu_control[3] => Mux10.IN16 +alu_control[3] => Mux11.IN16 +alu_control[3] => Mux12.IN16 +alu_control[3] => Mux13.IN16 +alu_control[3] => Mux14.IN16 +alu_control[3] => Mux15.IN16 +alu_control[3] => Mux16.IN16 +alu_control[3] => Mux17.IN16 +alu_control[3] => Mux18.IN16 +alu_control[3] => Mux19.IN16 +alu_control[3] => Mux20.IN16 +alu_control[3] => Mux21.IN16 +alu_control[3] => Mux22.IN16 +alu_control[3] => Mux23.IN16 +alu_control[3] => Mux24.IN16 +alu_control[3] => Mux25.IN16 +alu_control[3] => Mux26.IN16 +alu_control[3] => Mux27.IN16 +alu_control[3] => Mux28.IN16 +alu_control[3] => Mux29.IN16 +alu_control[3] => Mux30.IN16 +alu_control[3] => Mux31.IN16 +out[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE +out[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE +out[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE +out[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE +out[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE +out[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE +out[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE +out[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE +out[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE +out[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE +out[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE +out[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE +out[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE +out[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE +out[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE +out[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE +out[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE +out[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE +out[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE +out[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE +out[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE +out[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE +out[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE +out[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE +out[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE +out[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE +out[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +out[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +out[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +out[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +out[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +out[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +zeroE <= Equal0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/quartus workspace/db/top.hif b/quartus workspace/db/top.hif new file mode 100644 index 0000000..2ccb7e6 Binary files /dev/null and b/quartus workspace/db/top.hif differ diff --git a/quartus workspace/db/top.lpc.html b/quartus workspace/db/top.lpc.html new file mode 100644 index 0000000..6b184b8 --- /dev/null +++ b/quartus workspace/db/top.lpc.html @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
core|alu680003300000000
core|RegFile5032032108832323200000
core|instruction_decode|instanceALUDec12000400000000
core|instruction_decode320006800000000
core|MemLoad9903006800000000
core|fetch700106400000000
core|control_fsm496062266600000
core34000112400000000
u_mem11250004200000000
u_master110003207900000000
u_uart|uart_rx_inst40001200000000
u_uart|uart_tx_inst11000300000000
u_uart130001500000000
diff --git a/quartus workspace/db/top.lpc.rdb b/quartus workspace/db/top.lpc.rdb new file mode 100644 index 0000000..d56786b Binary files /dev/null and b/quartus workspace/db/top.lpc.rdb differ diff --git a/quartus workspace/db/top.lpc.txt b/quartus workspace/db/top.lpc.txt new file mode 100644 index 0000000..ae5de71 --- /dev/null +++ b/quartus workspace/db/top.lpc.txt @@ -0,0 +1,19 @@ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; core|alu ; 68 ; 0 ; 0 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; core|RegFile ; 50 ; 32 ; 0 ; 32 ; 1088 ; 32 ; 32 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; core|instruction_decode|instanceALUDec ; 12 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; core|instruction_decode ; 32 ; 0 ; 0 ; 0 ; 68 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; core|MemLoad ; 99 ; 0 ; 30 ; 0 ; 68 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; core|fetch ; 70 ; 0 ; 1 ; 0 ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; core|control_fsm ; 49 ; 6 ; 0 ; 6 ; 22 ; 6 ; 6 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; core ; 34 ; 0 ; 0 ; 0 ; 1124 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; u_mem ; 1125 ; 0 ; 0 ; 0 ; 42 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; u_master ; 1100 ; 0 ; 32 ; 0 ; 79 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; u_uart|uart_rx_inst ; 4 ; 0 ; 0 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; u_uart|uart_tx_inst ; 11 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; u_uart ; 13 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/quartus workspace/db/top.map.ammdb b/quartus workspace/db/top.map.ammdb new file mode 100644 index 0000000..7a55cff Binary files /dev/null and b/quartus workspace/db/top.map.ammdb differ diff --git a/quartus workspace/db/top.map.bpm b/quartus workspace/db/top.map.bpm new file mode 100644 index 0000000..d3fbf12 Binary files /dev/null and b/quartus workspace/db/top.map.bpm differ diff --git a/quartus workspace/db/top.map.cdb b/quartus workspace/db/top.map.cdb new file mode 100644 index 0000000..64cb13f Binary files /dev/null and b/quartus workspace/db/top.map.cdb differ diff --git a/quartus workspace/db/top.map.hdb b/quartus workspace/db/top.map.hdb new file mode 100644 index 0000000..6d7430e Binary files /dev/null and b/quartus workspace/db/top.map.hdb differ diff --git a/quartus workspace/db/top.map.kpt b/quartus workspace/db/top.map.kpt new file mode 100644 index 0000000..2774171 Binary files /dev/null and b/quartus workspace/db/top.map.kpt differ diff --git a/quartus workspace/db/top.map.logdb b/quartus workspace/db/top.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/quartus workspace/db/top.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/quartus workspace/db/top.map.qmsg b/quartus workspace/db/top.map.qmsg new file mode 100644 index 0000000..480426b --- /dev/null +++ b/quartus workspace/db/top.map.qmsg @@ -0,0 +1,152 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1768272780366 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition " "Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1768272780366 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 12 21:52:59 2026 " "Processing started: Mon Jan 12 21:52:59 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1768272780366 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272780366 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272780367 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1768272780622 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1768272780622 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "src/logger.sv 1 1 " "Found 1 design units, including 1 entities, in source file src/logger.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Logger " "Found entity 1: Logger" { } { { "src/Logger.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/src/Logger.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785847 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785847 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" { } { { "../envs/de1-soc/top.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785848 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785848 ""} +{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "5 memory_map.sv(114) " "Verilog HDL Expression warning at memory_map.sv(114): truncated literal to match 5 bits" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 114 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1768272785849 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" { { "Info" "ISGN_ENTITY_NAME" "1 memory_map " "Found entity 1: memory_map" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 71 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785849 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785849 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/alu_aludecoder/aludecoder.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/alu_aludecoder/aludecoder.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ALUdecoder " "Found entity 1: ALUdecoder" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785851 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785851 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/alu_aludecoder/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/alu_aludecoder/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Found entity 1: ALU" { } { { "../src/ALU_ALUdecoder/ALU.v" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALU.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785852 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785852 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/registerfile.v 0 0 " "Found 0 design units, including 0 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/registerfile.v" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785853 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/memoryloader.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/memoryloader.sv" { { "Info" "ISGN_ENTITY_NAME" "1 MemoryLoader " "Found entity 1: MemoryLoader" { } { { "../src/Instruction_Decode/MemoryLoader.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/MemoryLoader.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785854 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785854 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/instruction_decode.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/instruction_decode.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Instruction_Decode " "Found entity 1: Instruction_Decode" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785855 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785855 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" { { "Info" "ISGN_ENTITY_NAME" "1 utoss_riscv " "Found entity 1: utoss_riscv" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785856 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785856 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/fetch.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/fetch.sv" { { "Info" "ISGN_ENTITY_NAME" "1 fetch " "Found entity 1: fetch" { } { { "../src/fetch.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/fetch.sv" 10 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785858 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785858 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "MemWrite MEMWRITE ControlFSM.sv(21) " "Verilog HDL Declaration information at ControlFSM.sv(21): object \"MemWrite\" differs only in case from object \"MEMWRITE\" in the same scope" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1768272785859 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/controlfsm.sv 1 1 " "Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/controlfsm.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ControlFSM " "Found entity 1: ControlFSM" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 7 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785860 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785860 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_rx.sv 1 1 " "Found 1 design units, including 1 entities, in source file uart_rx.sv" { { "Info" "ISGN_ENTITY_NAME" "1 uart_rx " "Found entity 1: uart_rx" { } { { "uart_rx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785861 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785861 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_tx.sv 1 1 " "Found 1 design units, including 1 entities, in source file uart_tx.sv" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "uart_tx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_tx.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785862 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785862 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.sv 1 1 " "Found 1 design units, including 1 entities, in source file uart.sv" { { "Info" "ISGN_ENTITY_NAME" "1 uart " "Found entity 1: uart" { } { { "uart.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785863 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785863 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "inst_mem.v 1 1 " "Found 1 design units, including 1 entities, in source file inst_mem.v" { { "Info" "ISGN_ENTITY_NAME" "1 inst_mem " "Found entity 1: inst_mem" { } { { "inst_mem.v" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/inst_mem.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785864 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785864 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_bus_master.sv 1 1 " "Found 1 design units, including 1 entities, in source file uart_bus_master.sv" { { "Info" "ISGN_ENTITY_NAME" "1 uart_bus_master " "Found entity 1: uart_bus_master" { } { { "uart_bus_master.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_bus_master.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785865 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785865 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "registerfile.sv 1 1 " "Found 1 design units, including 1 entities, in source file registerfile.sv" { { "Info" "ISGN_ENTITY_NAME" "1 registerFile " "Found entity 1: registerFile" { } { { "RegisterFile.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/RegisterFile.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272785866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785866 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1768272785908 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart uart:u_uart " "Elaborating entity \"uart\" for hierarchy \"uart:u_uart\"" { } { { "../envs/de1-soc/top.sv" "u_uart" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785911 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart:u_uart\|uart_tx:uart_tx_inst " "Elaborating entity \"uart_tx\" for hierarchy \"uart:u_uart\|uart_tx:uart_tx_inst\"" { } { { "uart.sv" "uart_tx_inst" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart.sv" 48 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785912 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_tx.sv(48) " "Verilog HDL assignment warning at uart_tx.sv(48): truncated value with size 32 to match size of target (19)" { } { { "uart_tx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_tx.sv" 48 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272785912 "|top|uart:u_uart|uart_tx:uart_tx_inst"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_tx.sv(64) " "Verilog HDL assignment warning at uart_tx.sv(64): truncated value with size 32 to match size of target (19)" { } { { "uart_tx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_tx.sv" 64 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272785913 "|top|uart:u_uart|uart_tx:uart_tx_inst"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_rx uart:u_uart\|uart_rx:uart_rx_inst " "Elaborating entity \"uart_rx\" for hierarchy \"uart:u_uart\|uart_rx:uart_rx_inst\"" { } { { "uart.sv" "uart_rx_inst" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart.sv" 64 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785913 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_rx.sv(78) " "Verilog HDL assignment warning at uart_rx.sv(78): truncated value with size 32 to match size of target (19)" { } { { "uart_rx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv" 78 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272785914 "|top|uart:u_uart|uart_rx:uart_rx_inst"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_rx.sv(91) " "Verilog HDL assignment warning at uart_rx.sv(91): truncated value with size 32 to match size of target (19)" { } { { "uart_rx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv" 91 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272785914 "|top|uart:u_uart|uart_rx:uart_rx_inst"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_rx.sv(109) " "Verilog HDL assignment warning at uart_rx.sv(109): truncated value with size 32 to match size of target (19)" { } { { "uart_rx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272785914 "|top|uart:u_uart|uart_rx:uart_rx_inst"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 uart_rx.sv(112) " "Verilog HDL assignment warning at uart_rx.sv(112): truncated value with size 32 to match size of target (19)" { } { { "uart_rx.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv" 112 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1768272785914 "|top|uart:u_uart|uart_rx:uart_rx_inst"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_bus_master uart_bus_master:u_master " "Elaborating entity \"uart_bus_master\" for hierarchy \"uart_bus_master:u_master\"" { } { { "../envs/de1-soc/top.sv" "u_master" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 74 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785915 ""} +{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "uart_bus_master.sv(164) " "Verilog HDL Case Statement information at uart_bus_master.sv(164): all case item expressions in this case statement are onehot" { } { { "uart_bus_master.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_bus_master.sv" 164 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1768272785919 "|top|uart_bus_master:u_master"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_map memory_map:u_mem " "Elaborating entity \"memory_map\" for hierarchy \"memory_map:u_mem\"" { } { { "../envs/de1-soc/top.sv" "u_mem" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785921 ""} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "20 0 511 memory_map.sv(92) " "Verilog HDL warning at memory_map.sv(92): number of words (20) in memory file does not match the number of elements in the address range \[0:511\]" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 92 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1768272785926 "|top|memory_map:u_mem"} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "20 0 511 memory_map.sv(93) " "Verilog HDL warning at memory_map.sv(93): number of words (20) in memory file does not match the number of elements in the address range \[0:511\]" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 93 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1768272785926 "|top|memory_map:u_mem"} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "20 0 511 memory_map.sv(94) " "Verilog HDL warning at memory_map.sv(94): number of words (20) in memory file does not match the number of elements in the address range \[0:511\]" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 94 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1768272785927 "|top|memory_map:u_mem"} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "20 0 511 memory_map.sv(95) " "Verilog HDL warning at memory_map.sv(95): number of words (20) in memory file does not match the number of elements in the address range \[0:511\]" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 95 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1768272785927 "|top|memory_map:u_mem"} +{ "Warning" "WVRFX_VERI_CANT_ANALYZE_CASE_STATEMENT" "memory_map.sv(110) " "Verilog HDL Case Statement warning at memory_map.sv(110): can't check case statement for completeness because the case expression has too many possible states" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 110 0 0 } } } 0 10762 "Verilog HDL Case Statement warning at %1!s!: can't check case statement for completeness because the case expression has too many possible states" 0 0 "Analysis & Synthesis" 0 -1 1768272785932 "|top|memory_map:u_mem"} +{ "Warning" "WVRFX_VERI_CANT_ANALYZE_CASE_STATEMENT" "memory_map.sv(123) " "Verilog HDL Case Statement warning at memory_map.sv(123): can't check case statement for completeness because the case expression has too many possible states" { } { { "../envs/de1-soc/memory_map.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv" 123 0 0 } } } 0 10762 "Verilog HDL Case Statement warning at %1!s!: can't check case statement for completeness because the case expression has too many possible states" 0 0 "Analysis & Synthesis" 0 -1 1768272785933 "|top|memory_map:u_mem"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "utoss_riscv utoss_riscv:core " "Elaborating entity \"utoss_riscv\" for hierarchy \"utoss_riscv:core\"" { } { { "../envs/de1-soc/top.sv" "core" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 118 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785961 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ControlFSM utoss_riscv:core\|ControlFSM:control_fsm " "Elaborating entity \"ControlFSM\" for hierarchy \"utoss_riscv:core\|ControlFSM:control_fsm\"" { } { { "../src/utoss_riscv.sv" "control_fsm" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785985 ""} +{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "ControlFSM.sv(244) " "Verilog HDL Case Statement warning at ControlFSM.sv(244): incomplete case statement has no default case item" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 244 0 0 } } } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "Analysis & Synthesis" 0 -1 1768272785986 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ALUSrcA ControlFSM.sv(146) " "Verilog HDL Always Construct warning at ControlFSM.sv(146): inferring latch(es) for variable \"ALUSrcA\", which holds its previous value in one or more paths through the always construct" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1768272785986 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "ALUSrcB ControlFSM.sv(146) " "Verilog HDL Always Construct warning at ControlFSM.sv(146): inferring latch(es) for variable \"ALUSrcB\", which holds its previous value in one or more paths through the always construct" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1768272785986 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALUSrcB\[0\] ControlFSM.sv(146) " "Inferred latch for \"ALUSrcB\[0\]\" at ControlFSM.sv(146)" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785986 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALUSrcB\[1\] ControlFSM.sv(146) " "Inferred latch for \"ALUSrcB\[1\]\" at ControlFSM.sv(146)" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785986 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALUSrcA\[0\] ControlFSM.sv(146) " "Inferred latch for \"ALUSrcA\[0\]\" at ControlFSM.sv(146)" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785986 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ALUSrcA\[1\] ControlFSM.sv(146) " "Inferred latch for \"ALUSrcA\[1\]\" at ControlFSM.sv(146)" { } { { "../src/ControlFSM.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv" 146 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785986 "|top|utoss_riscv:core|ControlFSM:control_fsm"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fetch utoss_riscv:core\|fetch:fetch " "Elaborating entity \"fetch\" for hierarchy \"utoss_riscv:core\|fetch:fetch\"" { } { { "../src/utoss_riscv.sv" "fetch" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 92 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785987 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MemoryLoader utoss_riscv:core\|MemoryLoader:MemLoad " "Elaborating entity \"MemoryLoader\" for hierarchy \"utoss_riscv:core\|MemoryLoader:MemLoad\"" { } { { "../src/utoss_riscv.sv" "MemLoad" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 115 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785989 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Instruction_Decode utoss_riscv:core\|Instruction_Decode:instruction_decode " "Elaborating entity \"Instruction_Decode\" for hierarchy \"utoss_riscv:core\|Instruction_Decode:instruction_decode\"" { } { { "../src/utoss_riscv.sv" "instruction_decode" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 131 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785990 ""} +{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "Instruction_Decode.sv(127) " "Verilog HDL Case Statement warning at Instruction_Decode.sv(127): incomplete case statement has no default case item" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "imm_ext Instruction_Decode.sv(127) " "Verilog HDL Always Construct warning at Instruction_Decode.sv(127): inferring latch(es) for variable \"imm_ext\", which holds its previous value in one or more paths through the always construct" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[0\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[0\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[1\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[1\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[2\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[2\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[3\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[3\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[4\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[4\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[5\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[5\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[6\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[6\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[7\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[7\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[8\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[8\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[9\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[9\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[10\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[10\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[11\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[11\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[12\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[12\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[13\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[13\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[14\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[14\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[15\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[15\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[16\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[16\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785991 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[17\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[17\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[18\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[18\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[19\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[19\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[20\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[20\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[21\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[21\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[22\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[22\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[23\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[23\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[24\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[24\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[25\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[25\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[26\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[26\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[27\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[27\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[28\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[28\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[29\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[29\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[30\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[30\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "imm_ext\[31\] Instruction_Decode.sv(127) " "Inferred latch for \"imm_ext\[31\]\" at Instruction_Decode.sv(127)" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALUdecoder utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec " "Elaborating entity \"ALUdecoder\" for hierarchy \"utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec\"" { } { { "../src/Instruction_Decode/Instruction_Decode.sv" "instanceALUDec" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 147 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785992 ""} +{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "alu_control ALUdecoder.sv(10) " "Verilog HDL Always Construct warning at ALUdecoder.sv(10): inferring latch(es) for variable \"alu_control\", which holds its previous value in one or more paths through the always construct" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1768272785993 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "alu_control\[0\] ALUdecoder.sv(10) " "Inferred latch for \"alu_control\[0\]\" at ALUdecoder.sv(10)" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785993 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "alu_control\[1\] ALUdecoder.sv(10) " "Inferred latch for \"alu_control\[1\]\" at ALUdecoder.sv(10)" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785993 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "alu_control\[2\] ALUdecoder.sv(10) " "Inferred latch for \"alu_control\[2\]\" at ALUdecoder.sv(10)" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785993 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "alu_control\[3\] ALUdecoder.sv(10) " "Inferred latch for \"alu_control\[3\]\" at ALUdecoder.sv(10)" { } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272785993 "|top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "registerFile utoss_riscv:core\|registerFile:RegFile " "Elaborating entity \"registerFile\" for hierarchy \"utoss_riscv:core\|registerFile:RegFile\"" { } { { "../src/utoss_riscv.sv" "RegFile" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272785994 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALU utoss_riscv:core\|ALU:alu " "Elaborating entity \"ALU\" for hierarchy \"utoss_riscv:core\|ALU:alu\"" { } { { "../src/utoss_riscv.sv" "alu" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 152 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272786003 ""} +{ "Info" "IOPT_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "memory_map:u_mem\|M0_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"memory_map:u_mem\|M0_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 9 " "Parameter WIDTHAD_A set to 9" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 512 " "Parameter NUMWORDS_A set to 512" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 9 " "Parameter WIDTHAD_B set to 9" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 512 " "Parameter NUMWORDS_B set to 512" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/top.ram0_memory_map_ee718c45.hdl.mif " "Parameter INIT_FILE set to db/top.ram0_memory_map_ee718c45.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "memory_map:u_mem\|M1_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"memory_map:u_mem\|M1_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 9 " "Parameter WIDTHAD_A set to 9" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 512 " "Parameter NUMWORDS_A set to 512" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 9 " "Parameter WIDTHAD_B set to 9" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 512 " "Parameter NUMWORDS_B set to 512" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/top.ram1_memory_map_ee718c45.hdl.mif " "Parameter INIT_FILE set to db/top.ram1_memory_map_ee718c45.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "memory_map:u_mem\|M2_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"memory_map:u_mem\|M2_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 9 " "Parameter WIDTHAD_A set to 9" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 512 " "Parameter NUMWORDS_A set to 512" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 9 " "Parameter WIDTHAD_B set to 9" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 512 " "Parameter NUMWORDS_B set to 512" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/top.ram2_memory_map_ee718c45.hdl.mif " "Parameter INIT_FILE set to db/top.ram2_memory_map_ee718c45.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "memory_map:u_mem\|M3_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"memory_map:u_mem\|M3_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 9 " "Parameter WIDTHAD_A set to 9" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 512 " "Parameter NUMWORDS_A set to 512" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 9 " "Parameter WIDTHAD_B set to 9" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 512 " "Parameter NUMWORDS_B set to 512" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/top.ram3_memory_map_ee718c45.hdl.mif " "Parameter INIT_FILE set to db/top.ram3_memory_map_ee718c45.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1768272787432 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1768272787432 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1768272787432 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "memory_map:u_mem\|altsyncram:M0_rtl_0 " "Elaborated megafunction instantiation \"memory_map:u_mem\|altsyncram:M0_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272787467 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "memory_map:u_mem\|altsyncram:M0_rtl_0 " "Instantiated megafunction \"memory_map:u_mem\|altsyncram:M0_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 9 " "Parameter \"WIDTHAD_A\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 512 " "Parameter \"NUMWORDS_A\" = \"512\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 9 " "Parameter \"WIDTHAD_B\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 512 " "Parameter \"NUMWORDS_B\" = \"512\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/top.ram0_memory_map_ee718c45.hdl.mif " "Parameter \"INIT_FILE\" = \"db/top.ram0_memory_map_ee718c45.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787468 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1768272787468 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6lr1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_6lr1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6lr1 " "Found entity 1: altsyncram_6lr1" { } { { "db/altsyncram_6lr1.tdf" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_6lr1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272787502 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272787502 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "memory_map:u_mem\|altsyncram:M1_rtl_0 " "Elaborated megafunction instantiation \"memory_map:u_mem\|altsyncram:M1_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272787512 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "memory_map:u_mem\|altsyncram:M1_rtl_0 " "Instantiated megafunction \"memory_map:u_mem\|altsyncram:M1_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 9 " "Parameter \"WIDTHAD_A\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 512 " "Parameter \"NUMWORDS_A\" = \"512\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 9 " "Parameter \"WIDTHAD_B\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 512 " "Parameter \"NUMWORDS_B\" = \"512\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/top.ram1_memory_map_ee718c45.hdl.mif " "Parameter \"INIT_FILE\" = \"db/top.ram1_memory_map_ee718c45.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787512 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1768272787512 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7lr1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7lr1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7lr1 " "Found entity 1: altsyncram_7lr1" { } { { "db/altsyncram_7lr1.tdf" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_7lr1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272787545 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272787545 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "memory_map:u_mem\|altsyncram:M2_rtl_0 " "Elaborated megafunction instantiation \"memory_map:u_mem\|altsyncram:M2_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272787555 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "memory_map:u_mem\|altsyncram:M2_rtl_0 " "Instantiated megafunction \"memory_map:u_mem\|altsyncram:M2_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 9 " "Parameter \"WIDTHAD_A\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 512 " "Parameter \"NUMWORDS_A\" = \"512\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 9 " "Parameter \"WIDTHAD_B\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 512 " "Parameter \"NUMWORDS_B\" = \"512\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/top.ram2_memory_map_ee718c45.hdl.mif " "Parameter \"INIT_FILE\" = \"db/top.ram2_memory_map_ee718c45.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787555 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1768272787555 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_8lr1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_8lr1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_8lr1 " "Found entity 1: altsyncram_8lr1" { } { { "db/altsyncram_8lr1.tdf" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_8lr1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272787589 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272787589 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "memory_map:u_mem\|altsyncram:M3_rtl_0 " "Elaborated megafunction instantiation \"memory_map:u_mem\|altsyncram:M3_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272787598 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "memory_map:u_mem\|altsyncram:M3_rtl_0 " "Instantiated megafunction \"memory_map:u_mem\|altsyncram:M3_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 9 " "Parameter \"WIDTHAD_A\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 512 " "Parameter \"NUMWORDS_A\" = \"512\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 9 " "Parameter \"WIDTHAD_B\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 512 " "Parameter \"NUMWORDS_B\" = \"512\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/top.ram3_memory_map_ee718c45.hdl.mif " "Parameter \"INIT_FILE\" = \"db/top.ram3_memory_map_ee718c45.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1768272787598 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1768272787598 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_9lr1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_9lr1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_9lr1 " "Found entity 1: altsyncram_9lr1" { } { { "db/altsyncram_9lr1.tdf" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_9lr1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1768272787630 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272787630 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec\|alu_control\[2\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec\|alu_control\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec\|alu_control\[3\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec\|alu_control\[3\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[12\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[12\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[4\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[4\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[2\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[2\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[2\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[2\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[2\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[3\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[3\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[2\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[2\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[0\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[1\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[2\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[2\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[30\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[30\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[29\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[29\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[28\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[28\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[27\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[27\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[26\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[26\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[25\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[25\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787888 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787888 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[24\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[24\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[23\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[23\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[22\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[22\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[21\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[21\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[20\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[20\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[19\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[19\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[18\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[18\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[17\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[17\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[16\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[16\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[15\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[15\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[14\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[14\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[13\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[13\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[12\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[12\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[11\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[11\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[10\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[10\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[9\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[9\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[8\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[8\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[7\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[7\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[6\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[6\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[5\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[5\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/Instruction_Decode/Instruction_Decode.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv" 127 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec\|alu_control\[0\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec\|alu_control\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec\|alu_control\[1\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|ALUdecoder:instanceALUDec\|alu_control\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA utoss_riscv:core\|instruction\[0\] " "Ports D and ENA on the latch are fed by the same signal utoss_riscv:core\|instruction\[0\]" { } { { "../src/utoss_riscv.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv" 101 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1768272787889 ""} } { { "../src/ALU_ALUdecoder/ALUdecoder.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv" 10 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1768272787889 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1768272789371 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "11 " "11 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1768272792765 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.map.smsg " "Generated suppressed messages file E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272792861 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1768272793031 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1768272793031 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "../envs/de1-soc/top.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1768272793184 "|top|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" { } { { "../envs/de1-soc/top.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1768272793184 "|top|KEY[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[3\] " "No output dependent on input pin \"KEY\[3\]\"" { } { { "../envs/de1-soc/top.sv" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1768272793184 "|top|KEY[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1768272793184 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "3736 " "Implemented 3736 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1768272793193 ""} { "Info" "ICUT_CUT_TM_OPINS" "11 " "Implemented 11 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1768272793193 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3687 " "Implemented 3687 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1768272793193 ""} { "Info" "ICUT_CUT_TM_RAMS" "32 " "Implemented 32 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1768272793193 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1768272793193 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 94 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 94 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4949 " "Peak virtual memory: 4949 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1768272793220 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 12 21:53:13 2026 " "Processing ended: Mon Jan 12 21:53:13 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1768272793220 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1768272793220 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1768272793220 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1768272793220 ""} diff --git a/quartus workspace/db/top.map.rdb b/quartus workspace/db/top.map.rdb new file mode 100644 index 0000000..b6de4bf Binary files /dev/null and b/quartus workspace/db/top.map.rdb differ diff --git a/quartus workspace/db/top.map_bb.cdb b/quartus workspace/db/top.map_bb.cdb new file mode 100644 index 0000000..03e530d Binary files /dev/null and b/quartus workspace/db/top.map_bb.cdb differ diff --git a/quartus workspace/db/top.map_bb.hdb b/quartus workspace/db/top.map_bb.hdb new file mode 100644 index 0000000..f9dc33c Binary files /dev/null and b/quartus workspace/db/top.map_bb.hdb differ diff --git a/quartus workspace/db/top.map_bb.logdb b/quartus workspace/db/top.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/quartus workspace/db/top.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/quartus workspace/db/top.pplq.rdb b/quartus workspace/db/top.pplq.rdb new file mode 100644 index 0000000..7bc367e Binary files /dev/null and b/quartus workspace/db/top.pplq.rdb differ diff --git a/quartus workspace/db/top.pre_map.cdb b/quartus workspace/db/top.pre_map.cdb new file mode 100644 index 0000000..87ad548 Binary files /dev/null and b/quartus workspace/db/top.pre_map.cdb differ diff --git a/quartus workspace/db/top.pre_map.hdb b/quartus workspace/db/top.pre_map.hdb new file mode 100644 index 0000000..7681afa Binary files /dev/null and b/quartus workspace/db/top.pre_map.hdb differ diff --git a/quartus workspace/db/top.ram0_memory_map_ee718c45.hdl.mif b/quartus workspace/db/top.ram0_memory_map_ee718c45.hdl.mif new file mode 100644 index 0000000..8cf16aa --- /dev/null +++ b/quartus workspace/db/top.ram0_memory_map_ee718c45.hdl.mif @@ -0,0 +1,524 @@ +-- begin_signature +-- memory_map(SIZE +-- 512) +-- end_signature +WIDTH=8; +DEPTH=512; + +ADDRESS_RADIX=UNS; +DATA_RADIX=BIN; + +CONTENT BEGIN + 511 : XXXXXXXX; + 510 : XXXXXXXX; + 509 : XXXXXXXX; + 508 : XXXXXXXX; + 507 : XXXXXXXX; + 506 : XXXXXXXX; + 505 : XXXXXXXX; + 504 : XXXXXXXX; + 503 : XXXXXXXX; + 502 : XXXXXXXX; + 501 : XXXXXXXX; + 500 : XXXXXXXX; + 499 : XXXXXXXX; + 498 : XXXXXXXX; + 497 : XXXXXXXX; + 496 : XXXXXXXX; + 495 : XXXXXXXX; + 494 : XXXXXXXX; + 493 : XXXXXXXX; + 492 : XXXXXXXX; + 491 : XXXXXXXX; + 490 : XXXXXXXX; + 489 : XXXXXXXX; + 488 : XXXXXXXX; + 487 : XXXXXXXX; + 486 : XXXXXXXX; + 485 : XXXXXXXX; + 484 : XXXXXXXX; + 483 : XXXXXXXX; + 482 : XXXXXXXX; + 481 : XXXXXXXX; + 480 : XXXXXXXX; + 479 : XXXXXXXX; + 478 : XXXXXXXX; + 477 : XXXXXXXX; + 476 : XXXXXXXX; + 475 : XXXXXXXX; + 474 : XXXXXXXX; + 473 : XXXXXXXX; + 472 : XXXXXXXX; + 471 : XXXXXXXX; + 470 : XXXXXXXX; + 469 : XXXXXXXX; + 468 : XXXXXXXX; + 467 : XXXXXXXX; + 466 : XXXXXXXX; + 465 : XXXXXXXX; + 464 : XXXXXXXX; + 463 : XXXXXXXX; + 462 : XXXXXXXX; + 461 : XXXXXXXX; + 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files /dev/null and b/quartus workspace/db/top.root_partition.map.reg_db.cdb differ diff --git a/quartus workspace/db/top.routing.rdb b/quartus workspace/db/top.routing.rdb new file mode 100644 index 0000000..9264a76 Binary files /dev/null and b/quartus workspace/db/top.routing.rdb differ diff --git a/quartus workspace/db/top.rtlv.hdb b/quartus workspace/db/top.rtlv.hdb new file mode 100644 index 0000000..a3d95d8 Binary files /dev/null and b/quartus workspace/db/top.rtlv.hdb differ diff --git a/quartus workspace/db/top.rtlv_sg.cdb b/quartus workspace/db/top.rtlv_sg.cdb new file mode 100644 index 0000000..02c457a Binary files /dev/null and b/quartus workspace/db/top.rtlv_sg.cdb differ diff --git a/quartus workspace/db/top.rtlv_sg_swap.cdb b/quartus workspace/db/top.rtlv_sg_swap.cdb new file mode 100644 index 0000000..e2ef558 Binary files /dev/null and b/quartus workspace/db/top.rtlv_sg_swap.cdb differ diff --git a/quartus workspace/db/top.sld_design_entry.sci b/quartus workspace/db/top.sld_design_entry.sci new file mode 100644 index 0000000..e7008aa Binary files /dev/null and b/quartus workspace/db/top.sld_design_entry.sci differ diff --git a/quartus workspace/db/top.sld_design_entry_dsc.sci b/quartus workspace/db/top.sld_design_entry_dsc.sci new file mode 100644 index 0000000..e7008aa Binary files /dev/null and b/quartus workspace/db/top.sld_design_entry_dsc.sci differ diff --git a/quartus workspace/db/top.smart_action.txt b/quartus workspace/db/top.smart_action.txt new file mode 100644 index 0000000..e04bbcf --- /dev/null +++ b/quartus workspace/db/top.smart_action.txt @@ -0,0 +1 @@ +FIT diff --git a/quartus workspace/db/top.smp_dump.txt b/quartus workspace/db/top.smp_dump.txt new file mode 100644 index 0000000..1e4b222 --- /dev/null +++ b/quartus workspace/db/top.smp_dump.txt @@ -0,0 +1,46 @@ + +State Machine - |top|utoss_riscv:core|ControlFSM:control_fsm|current_state +Name current_state.BRANCHCOMP current_state.JALR_STEP2 current_state.JALR_CALC current_state.AUIPC current_state.LUI current_state.BRANCHIFEQ current_state.MEMWB current_state.MEMREAD current_state.MEMWRITE current_state.ALUWB current_state.MEMADR current_state.EXECUTEI current_state.UNCONDJUMP current_state.EXECUTER current_state.DECODE current_state.FETCH current_state.FETCH_WAIT +current_state.FETCH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +current_state.DECODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 +current_state.EXECUTER 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 +current_state.UNCONDJUMP 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 +current_state.EXECUTEI 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 +current_state.MEMADR 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 +current_state.ALUWB 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 +current_state.MEMWRITE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 +current_state.MEMREAD 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 +current_state.MEMWB 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 +current_state.BRANCHIFEQ 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 +current_state.LUI 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 +current_state.AUIPC 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 +current_state.JALR_CALC 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 +current_state.JALR_STEP2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 +current_state.BRANCHCOMP 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 +current_state.FETCH_WAIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 + +State Machine - |top|uart_bus_master:u_master|state +Name state.STATE_REG state.STATE_SEND state.STATE_DO_RD1 state.STATE_DO_RD0 state.STATE_DO_WR state.STATE_CHK state.STATE_D3 state.STATE_D2 state.STATE_D1 state.STATE_D0 state.STATE_A3 state.STATE_A2 state.STATE_A1 state.STATE_A0 state.STATE_CMD state.STATE_WAIT_SOF +state.STATE_WAIT_SOF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +state.STATE_CMD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 +state.STATE_A0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 +state.STATE_A1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 +state.STATE_A2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 +state.STATE_A3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 +state.STATE_D0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 +state.STATE_D1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 +state.STATE_D2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 +state.STATE_D3 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 +state.STATE_CHK 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 +state.STATE_DO_WR 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 +state.STATE_DO_RD0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 +state.STATE_DO_RD1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 +state.STATE_SEND 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +state.STATE_REG 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 + +State Machine - |top|uart:u_uart|uart_rx:uart_rx_inst|state +Name state.STATE_STOP state.STATE_DATA state.STATE_START state.STATE_IDLE +state.STATE_IDLE 0 0 0 0 +state.STATE_START 0 0 1 1 +state.STATE_DATA 0 1 0 1 +state.STATE_STOP 1 0 0 1 diff --git a/quartus workspace/db/top.sta.qmsg b/quartus workspace/db/top.sta.qmsg new file mode 100644 index 0000000..19a687a --- /dev/null +++ b/quartus workspace/db/top.sta.qmsg @@ -0,0 +1,58 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1768270596033 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition " "Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1768270596033 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 12 21:16:35 2026 " "Processing started: Mon Jan 12 21:16:35 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1768270596033 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1768270596033 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta top -c top " "Command: quartus_sta top -c top" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1768270596033 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1768270596112 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1768270596667 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1768270596667 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270596706 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270596706 ""} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "40 " "The Timing Analyzer is analyzing 40 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Timing Analyzer" 0 -1 1768270597152 ""} +{ "Info" "ISTA_SDC_FOUND" "../envs/de1-soc/quartus/top.sdc " "Reading SDC File: '../envs/de1-soc/quartus/top.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1768270597230 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "top.sdc 9 LEDR port " "Ignored filter at top.sdc(9): LEDR could not be matched with a port" { } { { "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc" 9 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1768270597236 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_false_path top.sdc 9 Argument is an empty collection " "Ignored set_false_path at top.sdc(9): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_false_path -from \[get_ports LEDR\] " "set_false_path -from \[get_ports LEDR\]" { } { { "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc" 9 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1768270597237 ""} } { { "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc" 9 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1768270597237 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_false_path top.sdc 10 Argument is an empty collection " "Ignored set_false_path at top.sdc(10): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_false_path -to \[get_ports LEDR\] " "set_false_path -to \[get_ports LEDR\]" { } { { "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc" 10 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1768270597237 ""} } { { "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc" "" { Text "E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc" 10 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1768270597237 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB " "Node: utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch utoss_riscv:core\|ControlFSM:control_fsm\|ALUSrcB\[1\] utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB " "Latch utoss_riscv:core\|ControlFSM:control_fsm\|ALUSrcB\[1\] is being clocked by utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1768270597251 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1768270597251 "|top|utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "utoss_riscv:core\|instruction\[0\] " "Node: utoss_riscv:core\|instruction\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[5\] utoss_riscv:core\|instruction\[0\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[5\] is being clocked by utoss_riscv:core\|instruction\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1768270597252 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1768270597252 "|top|utoss_riscv:core|instruction[0]"} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1768270597272 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1768270597272 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1768270597273 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1768270597281 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 5.578 " "Worst-case setup slack is 5.578" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270597379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270597379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.578 0.000 CLOCK_50 " " 5.578 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270597379 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270597379 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.307 " "Worst-case hold slack is 0.307" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270597400 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270597400 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.307 0.000 CLOCK_50 " " 0.307 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270597400 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270597400 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1768270597403 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1768270597405 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.877 " "Worst-case minimum pulse width slack is 8.877" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270597407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270597407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.877 0.000 CLOCK_50 " " 8.877 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270597407 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270597407 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1768270597441 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1768270597489 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1768270598819 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB " "Node: utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch utoss_riscv:core\|ControlFSM:control_fsm\|ALUSrcB\[1\] utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB " "Latch utoss_riscv:core\|ControlFSM:control_fsm\|ALUSrcB\[1\] is being clocked by utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1768270599039 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1768270599039 "|top|utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "utoss_riscv:core\|instruction\[0\] " "Node: utoss_riscv:core\|instruction\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[5\] utoss_riscv:core\|instruction\[0\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[5\] is being clocked by utoss_riscv:core\|instruction\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1768270599039 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1768270599039 "|top|utoss_riscv:core|instruction[0]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1768270599044 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 5.784 " "Worst-case setup slack is 5.784" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270599127 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270599127 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.784 0.000 CLOCK_50 " " 5.784 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270599127 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270599127 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.295 " "Worst-case hold slack is 0.295" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270599153 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270599153 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.295 0.000 CLOCK_50 " " 0.295 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270599153 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270599153 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1768270599155 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1768270599159 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.823 " "Worst-case minimum pulse width slack is 8.823" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270599163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270599163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.823 0.000 CLOCK_50 " " 8.823 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270599163 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270599163 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1768270599209 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1768270599445 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1768270600769 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB " "Node: utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch utoss_riscv:core\|ControlFSM:control_fsm\|ALUSrcB\[1\] utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB " "Latch utoss_riscv:core\|ControlFSM:control_fsm\|ALUSrcB\[1\] is being clocked by utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1768270600964 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1768270600964 "|top|utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "utoss_riscv:core\|instruction\[0\] " "Node: utoss_riscv:core\|instruction\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[5\] utoss_riscv:core\|instruction\[0\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[5\] is being clocked by utoss_riscv:core\|instruction\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1768270600964 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1768270600964 "|top|utoss_riscv:core|instruction[0]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1768270600967 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 10.798 " "Worst-case setup slack is 10.798" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270600990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270600990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 10.798 0.000 CLOCK_50 " " 10.798 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270600990 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270600990 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.177 " "Worst-case hold slack is 0.177" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 CLOCK_50 " " 0.177 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601016 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270601016 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1768270601018 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1768270601021 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.784 " "Worst-case minimum pulse width slack is 8.784" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.784 0.000 CLOCK_50 " " 8.784 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601025 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270601025 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1768270601066 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB " "Node: utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch utoss_riscv:core\|ControlFSM:control_fsm\|ALUSrcB\[1\] utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB " "Latch utoss_riscv:core\|ControlFSM:control_fsm\|ALUSrcB\[1\] is being clocked by utoss_riscv:core\|ControlFSM:control_fsm\|current_state.ALUWB" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1768270601336 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1768270601336 "|top|utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "utoss_riscv:core\|instruction\[0\] " "Node: utoss_riscv:core\|instruction\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[5\] utoss_riscv:core\|instruction\[0\] " "Latch utoss_riscv:core\|Instruction_Decode:instruction_decode\|imm_ext\[5\] is being clocked by utoss_riscv:core\|instruction\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1768270601336 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1768270601336 "|top|utoss_riscv:core|instruction[0]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1768270601340 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 11.789 " "Worst-case setup slack is 11.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601366 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601366 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 11.789 0.000 CLOCK_50 " " 11.789 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601366 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270601366 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.165 " "Worst-case hold slack is 0.165" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601394 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601394 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.165 0.000 CLOCK_50 " " 0.165 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601394 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270601394 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1768270601397 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1768270601400 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.776 " "Worst-case minimum pulse width slack is 8.776" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.776 0.000 CLOCK_50 " " 8.776 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1768270601404 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1768270601404 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1768270602665 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1768270602669 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 13 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5485 " "Peak virtual memory: 5485 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1768270602775 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 12 21:16:42 2026 " "Processing ended: Mon Jan 12 21:16:42 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1768270602775 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1768270602775 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Total CPU time (on all processors): 00:00:18" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1768270602775 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1768270602775 ""} diff --git a/quartus workspace/db/top.sta.rdb b/quartus workspace/db/top.sta.rdb new file mode 100644 index 0000000..3961b08 Binary files /dev/null and b/quartus workspace/db/top.sta.rdb differ diff --git a/quartus workspace/db/top.taw.rdb b/quartus workspace/db/top.taw.rdb new file mode 100644 index 0000000..2a1bcec Binary files /dev/null and b/quartus workspace/db/top.taw.rdb differ diff --git a/quartus workspace/db/top.tis_db_list.ddb b/quartus workspace/db/top.tis_db_list.ddb new file mode 100644 index 0000000..4c33f8f Binary files /dev/null and b/quartus workspace/db/top.tis_db_list.ddb differ diff --git a/quartus workspace/db/top.tiscmp.fast_1100mv_0c.ddb b/quartus workspace/db/top.tiscmp.fast_1100mv_0c.ddb new file mode 100644 index 0000000..b2b91f1 Binary files /dev/null and b/quartus workspace/db/top.tiscmp.fast_1100mv_0c.ddb differ diff --git a/quartus workspace/db/top.tiscmp.fast_1100mv_85c.ddb b/quartus workspace/db/top.tiscmp.fast_1100mv_85c.ddb new file mode 100644 index 0000000..83628e0 Binary files /dev/null and b/quartus workspace/db/top.tiscmp.fast_1100mv_85c.ddb differ diff --git a/quartus workspace/db/top.tiscmp.slow_1100mv_0c.ddb b/quartus workspace/db/top.tiscmp.slow_1100mv_0c.ddb new file mode 100644 index 0000000..3d1d9bd Binary files /dev/null and b/quartus workspace/db/top.tiscmp.slow_1100mv_0c.ddb differ diff --git a/quartus workspace/db/top.tiscmp.slow_1100mv_85c.ddb b/quartus workspace/db/top.tiscmp.slow_1100mv_85c.ddb new file mode 100644 index 0000000..5f1c8a2 Binary files /dev/null and b/quartus workspace/db/top.tiscmp.slow_1100mv_85c.ddb differ diff --git a/quartus workspace/db/top.tmw_info b/quartus workspace/db/top.tmw_info new file mode 100644 index 0000000..9683770 --- /dev/null +++ b/quartus workspace/db/top.tmw_info @@ -0,0 +1,2 @@ +start_analysis_synthesis:s:00:00:17-start_full_compilation +start_analysis_elaboration:s-start_full_compilation diff --git a/quartus workspace/db/top.vpr.ammdb b/quartus workspace/db/top.vpr.ammdb new file mode 100644 index 0000000..459511c Binary files /dev/null and b/quartus workspace/db/top.vpr.ammdb differ diff --git a/quartus workspace/db/top_partition_pins.json b/quartus workspace/db/top_partition_pins.json new file mode 100644 index 0000000..92229ba --- /dev/null +++ b/quartus workspace/db/top_partition_pins.json @@ -0,0 +1,65 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "LEDR[0]", + "strict" : false + }, + { + "name" : "LEDR[1]", + "strict" : false + }, + { + "name" : "LEDR[2]", + "strict" : false + }, + { + "name" : "LEDR[3]", + "strict" : false + }, + { + "name" : "LEDR[4]", + "strict" : false + }, + { + "name" : "LEDR[5]", + "strict" : false + }, + { + "name" : "LEDR[6]", + "strict" : false + }, + { + "name" : "LEDR[7]", + "strict" : false + }, + { + "name" : "LEDR[8]", + "strict" : false + }, + { + "name" : "LEDR[9]", + "strict" : false + }, + { + "name" : "UART_RX", + "strict" : false + }, + { + "name" : "CLOCK_50", + "strict" : false + }, + { + "name" : "KEY[0]", + "strict" : false + }, + { + "name" : "UART_TX", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/quartus workspace/greybox_tmp/cbx_args.txt b/quartus workspace/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..de4acdd --- /dev/null +++ b/quartus workspace/greybox_tmp/cbx_args.txt @@ -0,0 +1,17 @@ +CLOCK_ENABLE_INPUT_A=BYPASS +CLOCK_ENABLE_OUTPUT_A=BYPASS +INTENDED_DEVICE_FAMILY="Cyclone V" +NUMWORDS_A=1024 +OPERATION_MODE=SINGLE_PORT +OUTDATA_ACLR_A=NONE +OUTDATA_REG_A=CLOCK0 +POWER_UP_UNINITIALIZED=FALSE +RAM_BLOCK_TYPE=M10K +READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ +WIDTHAD_A=10 +WIDTH_A=32 +WIDTH_BYTEENA_A=1 +DEVICE_FAMILY="Cyclone V" +address_a +clock0 +q_a diff --git a/quartus workspace/incremental_db/README b/quartus workspace/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/quartus workspace/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/quartus workspace/incremental_db/compiled_partitions/top.db_info b/quartus workspace/incremental_db/compiled_partitions/top.db_info new file mode 100644 index 0000000..6a066b7 --- /dev/null +++ b/quartus workspace/incremental_db/compiled_partitions/top.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition +Version_Index = 553884160 +Creation_Time = Tue Nov 25 19:59:49 2025 diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.ammdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.ammdb new file mode 100644 index 0000000..f2dcb0e Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.ammdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.cdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.cdb new file mode 100644 index 0000000..232ffaf Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.cdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.dfp b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.dfp differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.cdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.cdb new file mode 100644 index 0000000..041b89c Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.cdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.hdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.hdb new file mode 100644 index 0000000..d42437c Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.hdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.sig b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3 \ No newline at end of file diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hdb new file mode 100644 index 0000000..5a0f458 Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.hdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.logdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.rcfdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.rcfdb new file mode 100644 index 0000000..ee664fc Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.cmp.rcfdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.cdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.cdb new file mode 100644 index 0000000..7fd6008 Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.cdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.dpi b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.dpi new file mode 100644 index 0000000..100004f Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.dpi differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.cdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..a83253a Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.cdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hb_info b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hb_info differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..8c8608f Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.sig b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3 \ No newline at end of file diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hdb b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hdb new file mode 100644 index 0000000..b23d47f Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.hdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.kpt b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.kpt new file mode 100644 index 0000000..716c57f Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.root_partition.map.kpt differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.rrp.hdb b/quartus workspace/incremental_db/compiled_partitions/top.rrp.hdb new file mode 100644 index 0000000..a9b0663 Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.rrp.hdb differ diff --git a/quartus workspace/incremental_db/compiled_partitions/top.rrs.cdb b/quartus workspace/incremental_db/compiled_partitions/top.rrs.cdb new file mode 100644 index 0000000..7d85355 Binary files /dev/null and b/quartus workspace/incremental_db/compiled_partitions/top.rrs.cdb differ diff --git a/quartus workspace/output_files/top.asm.rpt b/quartus workspace/output_files/top.asm.rpt new file mode 100644 index 0000000..7d6d52d --- /dev/null +++ b/quartus workspace/output_files/top.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for top +Mon Jan 12 21:16:34 2026 +Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2023 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Jan 12 21:16:34 2026 ; +; Revision Name ; top ; +; Top-level Entity Name ; top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------------------------------------------------------------------+ +; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.sof ; ++-----------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.sof ; ++----------------+--------------------------------------------------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------------------------------------------------------------------------------------+ +; JTAG usercode ; 0x01096104 ; +; Checksum ; 0x01096104 ; ++----------------+--------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition + Info: Processing started: Mon Jan 12 21:16:27 2026 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off top -c top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 5270 megabytes + Info: Processing ended: Mon Jan 12 21:16:34 2026 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:07 + + diff --git a/quartus workspace/output_files/top.cdf b/quartus workspace/output_files/top.cdf new file mode 100644 index 0000000..b1ec52a --- /dev/null +++ b/quartus workspace/output_files/top.cdf @@ -0,0 +1,15 @@ +/* Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Ign) + Device PartName(SOCVHPS) MfrSpec(OpMask(0)); + P ActionCode(Cfg) + Device PartName(5CSEMA5F31) Path("E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/") File("top.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/quartus workspace/output_files/top.done b/quartus workspace/output_files/top.done new file mode 100644 index 0000000..d333f72 --- /dev/null +++ b/quartus workspace/output_files/top.done @@ -0,0 +1 @@ +Mon Jan 12 21:16:43 2026 diff --git a/quartus workspace/output_files/top.fit.rpt b/quartus workspace/output_files/top.fit.rpt new file mode 100644 index 0000000..6894b4c --- /dev/null +++ b/quartus workspace/output_files/top.fit.rpt @@ -0,0 +1,2762 @@ +Fitter report for top +Mon Jan 12 21:16:25 2026 +Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Fitter Netlist Optimizations + 6. Ignored Assignments + 7. Incremental Compilation Preservation Summary + 8. Incremental Compilation Partition Settings + 9. Incremental Compilation Placement Preservation + 10. Pin-Out File + 11. Fitter Resource Usage Summary + 12. Fitter Partition Statistics + 13. Input Pins + 14. Output Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Control Signals + 22. Global & Other Fast Signals + 23. Non-Global High Fan-Out Signals + 24. Fitter RAM Summary + 25. Routing Usage Summary + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Estimated Delay Added for Hold Timing Summary + 32. Estimated Delay Added for Hold Timing Details + 33. Fitter Messages + 34. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2023 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++---------------------------------+------------------------------------------------+ +; Fitter Status ; Successful - Mon Jan 12 21:16:25 2026 ; +; Quartus Prime Version ; 22.1std.2 Build 922 07/20/2023 SC Lite Edition ; +; Revision Name ; top ; +; Top-level Entity Name ; top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 1,909 / 32,070 ( 6 % ) ; +; Total registers ; 1563 ; +; Total pins ; 17 / 457 ( 4 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 16,384 / 4,065,280 ( < 1 % ) ; +; Total RAM Blocks ; 4 / 397 ( 1 % ) ; +; Total DSP Blocks ; 0 / 87 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 5CSEMA5F31C6 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Auto RAM to MLAB Conversion ; On ; On ; +; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; +; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Clamping Diode ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; +; Advanced Physical Optimization ; On ; On ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 16 ; +; Maximum allowed ; 16 ; +; ; ; +; Average used ; 1.06 ; +; Maximum used ; 16 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.5% ; +; Processor 3 ; 0.5% ; +; Processor 4 ; 0.5% ; +; Processor 5 ; 0.4% ; +; Processor 6 ; 0.4% ; +; Processor 7 ; 0.4% ; +; Processor 8 ; 0.4% ; +; Processor 9 ; 0.4% ; +; Processor 10 ; 0.4% ; +; Processor 11 ; 0.4% ; +; Processor 12 ; 0.4% ; +; Processor 13 ; 0.4% ; +; Processor 14 ; 0.4% ; +; Processor 15 ; 0.4% ; +; Processor 16 ; 0.4% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++-----------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+---------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++-----------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+---------------------------------------------------+------------------+-----------------------+ +; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; +; utoss_riscv:core|alu_out[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|alu_out[3]~DUPLICATE ; ; ; +; utoss_riscv:core|alu_out[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|alu_out[4]~DUPLICATE ; ; ; +; utoss_riscv:core|alu_out[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|alu_out[13]~DUPLICATE ; ; ; +; utoss_riscv:core|alu_out[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|alu_out[14]~DUPLICATE ; ; ; +; utoss_riscv:core|alu_out[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|alu_out[15]~DUPLICATE ; ; ; +; utoss_riscv:core|alu_out[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|alu_out[16]~DUPLICATE ; ; ; +; utoss_riscv:core|dataB[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|dataB[4]~DUPLICATE ; ; ; +; utoss_riscv:core|dataB[28] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|dataB[28]~DUPLICATE ; ; ; +; utoss_riscv:core|fetch:fetch|pc_old[23] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|fetch:fetch|pc_old[23]~DUPLICATE ; ; ; +; utoss_riscv:core|fetch:fetch|pc_old[24] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|fetch:fetch|pc_old[24]~DUPLICATE ; ; ; +; utoss_riscv:core|fetch:fetch|pc_old[26] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|fetch:fetch|pc_old[26]~DUPLICATE ; ; ; +; utoss_riscv:core|instruction[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; utoss_riscv:core|instruction[16]~DUPLICATE ; ; ; ++-----------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+---------------------------------------------------+------------------+-----------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++----------+----------------+--------------+----------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++----------+----------------+--------------+----------------+---------------+----------------+ +; Location ; ; ; ADC_CS_N ; PIN_AJ4 ; QSF Assignment ; +; Location ; ; ; ADC_DIN ; PIN_AK4 ; QSF Assignment ; +; Location ; ; ; ADC_DOUT ; PIN_AK3 ; QSF Assignment ; +; Location ; ; ; ADC_SCLK ; PIN_AK2 ; QSF Assignment ; +; Location ; ; ; AUD_ADCDAT ; PIN_K7 ; QSF Assignment ; +; Location ; ; ; AUD_ADCLRCK ; PIN_K8 ; QSF Assignment ; +; Location ; ; ; AUD_BCLK ; PIN_H7 ; QSF Assignment ; +; Location ; ; ; AUD_DACDAT ; PIN_J7 ; QSF Assignment ; +; Location ; ; ; AUD_DACLRCK ; PIN_H8 ; QSF Assignment ; +; Location ; ; ; AUD_XCK ; PIN_G7 ; QSF Assignment ; +; Location ; ; ; CLOCK2_50 ; PIN_AA16 ; QSF Assignment ; +; Location ; ; ; CLOCK3_50 ; PIN_Y26 ; QSF Assignment ; +; Location ; ; ; CLOCK4_50 ; PIN_K14 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[0] ; PIN_AK14 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[10] ; PIN_AG12 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[11] ; PIN_AH13 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[12] ; PIN_AJ14 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[1] ; PIN_AH14 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[2] ; PIN_AG15 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[3] ; PIN_AE14 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[4] ; PIN_AB15 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[5] ; PIN_AC14 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[6] ; PIN_AD14 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[7] ; PIN_AF15 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[8] ; PIN_AH15 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[9] ; PIN_AG13 ; QSF Assignment ; +; Location ; ; ; DRAM_BA[0] ; PIN_AF13 ; QSF Assignment ; +; Location ; ; ; DRAM_BA[1] ; PIN_AJ12 ; QSF Assignment ; +; Location ; ; ; DRAM_CAS_N ; PIN_AF11 ; QSF Assignment ; +; Location ; ; ; DRAM_CKE ; PIN_AK13 ; QSF Assignment ; +; Location ; ; ; DRAM_CLK ; PIN_AH12 ; QSF Assignment ; +; Location ; ; ; DRAM_CS_N ; PIN_AG11 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[0] ; PIN_AK6 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[10] ; PIN_AJ9 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[11] ; PIN_AH9 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[12] ; PIN_AH8 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[13] ; PIN_AH7 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[14] ; PIN_AJ6 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[15] ; PIN_AJ5 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[1] ; PIN_AJ7 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[2] ; PIN_AK7 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[3] ; PIN_AK8 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[4] ; PIN_AK9 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[5] ; PIN_AG10 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[6] ; PIN_AK11 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[7] ; PIN_AJ11 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[8] ; PIN_AH10 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[9] ; PIN_AJ10 ; QSF Assignment ; +; Location ; ; ; DRAM_LDQM ; PIN_AB13 ; QSF Assignment ; +; Location ; ; ; DRAM_RAS_N ; PIN_AE13 ; QSF Assignment ; +; Location ; ; ; DRAM_UDQM ; PIN_AK12 ; QSF Assignment ; +; Location ; ; ; DRAM_WE_N ; PIN_AA13 ; QSF Assignment ; +; Location ; ; ; FAN_CTRL ; PIN_AA12 ; QSF Assignment ; +; Location ; ; ; FPGA_I2C_SCLK ; PIN_J12 ; QSF Assignment ; +; Location ; ; ; FPGA_I2C_SDAT ; PIN_K12 ; QSF Assignment ; +; Location ; ; ; GPIO_0[0] ; PIN_AC18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[10] ; PIN_AH18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[11] ; PIN_AH17 ; QSF Assignment ; +; Location ; ; ; GPIO_0[12] ; PIN_AG16 ; QSF Assignment ; +; Location ; ; ; GPIO_0[13] ; PIN_AE16 ; QSF Assignment ; +; Location ; ; ; GPIO_0[14] ; PIN_AF16 ; QSF Assignment ; +; Location ; ; ; GPIO_0[15] ; PIN_AG17 ; QSF Assignment ; +; Location ; ; ; GPIO_0[16] ; PIN_AA18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[17] ; PIN_AA19 ; QSF Assignment ; +; Location ; ; ; GPIO_0[18] ; PIN_AE17 ; QSF Assignment ; +; Location ; ; ; GPIO_0[19] ; PIN_AC20 ; QSF Assignment ; +; Location ; ; ; GPIO_0[1] ; PIN_Y17 ; QSF Assignment ; +; Location ; ; ; GPIO_0[20] ; PIN_AH19 ; QSF Assignment ; +; Location ; ; ; GPIO_0[21] ; PIN_AJ20 ; QSF Assignment ; +; Location ; ; ; GPIO_0[22] ; PIN_AH20 ; QSF Assignment ; +; Location ; ; ; GPIO_0[23] ; PIN_AK21 ; QSF Assignment ; +; Location ; ; ; GPIO_0[24] ; PIN_AD19 ; QSF Assignment ; +; Location ; ; ; GPIO_0[25] ; PIN_AD20 ; QSF Assignment ; +; Location ; ; ; GPIO_0[26] ; PIN_AE18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[27] ; PIN_AE19 ; QSF Assignment ; +; Location ; ; ; GPIO_0[28] ; PIN_AF20 ; QSF Assignment ; +; Location ; ; ; GPIO_0[29] ; PIN_AF21 ; QSF Assignment ; +; Location ; ; ; GPIO_0[2] ; PIN_AD17 ; QSF Assignment ; +; Location ; ; ; GPIO_0[30] ; PIN_AF19 ; QSF Assignment ; +; Location ; ; ; GPIO_0[31] ; PIN_AG21 ; QSF Assignment ; +; Location ; ; ; GPIO_0[32] ; PIN_AF18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[33] ; PIN_AG20 ; QSF Assignment ; +; Location ; ; ; GPIO_0[34] ; PIN_AG18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[35] ; PIN_AJ21 ; QSF Assignment ; +; Location ; ; ; GPIO_0[3] ; PIN_Y18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[4] ; PIN_AK16 ; QSF Assignment ; +; Location ; ; ; GPIO_0[5] ; PIN_AK18 ; QSF Assignment ; +; Location ; ; ; GPIO_0[6] ; PIN_AK19 ; QSF Assignment ; +; Location ; ; ; GPIO_0[7] ; PIN_AJ19 ; QSF Assignment ; +; Location ; ; ; GPIO_0[8] ; PIN_AJ17 ; QSF Assignment ; +; Location ; ; ; GPIO_0[9] ; PIN_AJ16 ; QSF Assignment ; +; Location ; ; ; GPIO_1[0] ; PIN_AB17 ; QSF Assignment ; +; Location ; ; ; GPIO_1[10] ; PIN_AG26 ; QSF Assignment ; +; Location ; ; ; GPIO_1[11] ; PIN_AH24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[12] ; PIN_AH27 ; QSF Assignment ; +; Location ; ; ; GPIO_1[13] ; PIN_AJ27 ; QSF Assignment ; +; Location ; ; ; GPIO_1[14] ; PIN_AK29 ; QSF Assignment ; +; Location ; ; ; GPIO_1[15] ; PIN_AK28 ; QSF Assignment ; +; Location ; ; ; GPIO_1[16] ; PIN_AK27 ; QSF Assignment ; +; Location ; ; ; GPIO_1[17] ; PIN_AJ26 ; QSF Assignment ; +; Location ; ; ; GPIO_1[18] ; PIN_AK26 ; QSF Assignment ; +; Location ; ; ; GPIO_1[19] ; PIN_AH25 ; QSF Assignment ; +; Location ; ; ; GPIO_1[1] ; PIN_AA21 ; QSF Assignment ; +; Location ; ; ; GPIO_1[20] ; PIN_AJ25 ; QSF Assignment ; +; Location ; ; ; GPIO_1[21] ; PIN_AJ24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[22] ; PIN_AK24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[23] ; PIN_AG23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[24] ; PIN_AK23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[25] ; PIN_AH23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[26] ; PIN_AK22 ; QSF Assignment ; +; Location ; ; ; GPIO_1[27] ; PIN_AJ22 ; QSF Assignment ; +; Location ; ; ; GPIO_1[28] ; PIN_AH22 ; QSF Assignment ; +; Location ; ; ; GPIO_1[29] ; PIN_AG22 ; QSF Assignment ; +; Location ; ; ; GPIO_1[2] ; PIN_AB21 ; QSF Assignment ; +; Location ; ; ; GPIO_1[30] ; PIN_AF24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[31] ; PIN_AF23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[32] ; PIN_AE22 ; QSF Assignment ; +; Location ; ; ; GPIO_1[33] ; PIN_AD21 ; QSF Assignment ; +; Location ; ; ; GPIO_1[34] ; PIN_AA20 ; QSF Assignment ; +; Location ; ; ; GPIO_1[35] ; PIN_AC22 ; QSF Assignment ; +; Location ; ; ; GPIO_1[3] ; PIN_AC23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[4] ; PIN_AD24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[5] ; PIN_AE23 ; QSF Assignment ; +; Location ; ; ; GPIO_1[6] ; PIN_AE24 ; QSF Assignment ; +; Location ; ; ; GPIO_1[7] ; PIN_AF25 ; QSF Assignment ; +; Location ; ; ; GPIO_1[8] ; PIN_AF26 ; QSF Assignment ; +; Location ; ; ; GPIO_1[9] ; PIN_AG25 ; QSF Assignment ; +; Location ; ; ; HEX0[0] ; PIN_AE26 ; QSF Assignment ; +; Location ; ; ; HEX0[1] ; PIN_AE27 ; QSF Assignment ; +; Location ; ; ; HEX0[2] ; PIN_AE28 ; QSF Assignment ; +; Location ; ; ; HEX0[3] ; PIN_AG27 ; QSF Assignment ; +; Location ; ; ; HEX0[4] ; PIN_AF28 ; QSF Assignment ; +; Location ; ; ; HEX0[5] ; PIN_AG28 ; QSF Assignment ; +; Location ; ; ; HEX0[6] ; PIN_AH28 ; QSF Assignment ; +; Location ; ; ; HEX1[0] ; PIN_AJ29 ; QSF Assignment ; +; Location ; ; ; HEX1[1] ; PIN_AH29 ; QSF Assignment ; +; Location ; ; ; HEX1[2] ; PIN_AH30 ; QSF Assignment ; +; Location ; ; ; HEX1[3] ; PIN_AG30 ; QSF Assignment ; +; Location ; ; ; HEX1[4] ; PIN_AF29 ; QSF Assignment ; +; Location ; ; ; HEX1[5] ; PIN_AF30 ; QSF Assignment ; +; Location ; ; ; HEX1[6] ; PIN_AD27 ; QSF Assignment ; +; Location ; ; ; HEX2[0] ; PIN_AB23 ; QSF Assignment ; +; Location ; ; ; HEX2[1] ; PIN_AE29 ; QSF Assignment ; +; Location ; ; ; HEX2[2] ; PIN_AD29 ; QSF Assignment ; +; Location ; ; ; HEX2[3] ; PIN_AC28 ; QSF Assignment ; +; Location ; ; ; HEX2[4] ; PIN_AD30 ; QSF Assignment ; +; Location ; ; ; HEX2[5] ; PIN_AC29 ; QSF Assignment ; +; Location ; ; ; HEX2[6] ; PIN_AC30 ; QSF Assignment ; +; Location ; ; ; HEX3[0] ; PIN_AD26 ; QSF Assignment ; +; Location ; ; ; HEX3[1] ; PIN_AC27 ; QSF Assignment ; +; Location ; ; ; HEX3[2] ; PIN_AD25 ; QSF Assignment ; +; Location ; ; ; HEX3[3] ; PIN_AC25 ; QSF Assignment ; +; Location ; ; ; HEX3[4] ; PIN_AB28 ; QSF Assignment ; +; Location ; ; ; HEX3[5] ; PIN_AB25 ; QSF Assignment ; +; Location ; ; ; HEX3[6] ; PIN_AB22 ; QSF Assignment ; +; Location ; ; ; HEX4[0] ; PIN_AA24 ; QSF Assignment ; +; Location ; ; ; HEX4[1] ; PIN_Y23 ; QSF Assignment ; +; Location ; ; ; HEX4[2] ; PIN_Y24 ; QSF Assignment ; +; Location ; ; ; HEX4[3] ; PIN_W22 ; QSF Assignment ; +; Location ; ; ; HEX4[4] ; PIN_W24 ; QSF Assignment ; +; Location ; ; ; HEX4[5] ; PIN_V23 ; QSF Assignment ; +; Location ; ; ; HEX4[6] ; PIN_W25 ; QSF Assignment ; +; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ; +; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ; +; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ; +; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ; +; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ; +; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ; +; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ; +; Location ; ; ; IRDA_RXD ; PIN_AA30 ; QSF Assignment ; +; Location ; ; ; IRDA_TXD ; PIN_AB30 ; QSF Assignment ; +; Location ; ; ; PS2_CLK ; PIN_AD7 ; QSF Assignment ; +; Location ; ; ; PS2_CLK2 ; PIN_AD9 ; QSF Assignment ; +; Location ; ; ; PS2_DAT ; PIN_AE7 ; QSF Assignment ; +; Location ; ; ; PS2_DAT2 ; PIN_AE9 ; QSF Assignment ; +; Location ; ; ; SW[0] ; PIN_AB12 ; QSF Assignment ; +; Location ; ; ; SW[1] ; PIN_AC12 ; QSF Assignment ; +; Location ; ; ; SW[2] ; PIN_AF9 ; QSF Assignment ; +; Location ; ; ; SW[3] ; PIN_AF10 ; QSF Assignment ; +; Location ; ; ; SW[4] ; PIN_AD11 ; QSF Assignment ; +; Location ; ; ; SW[5] ; PIN_AD12 ; QSF Assignment ; +; Location ; ; ; SW[6] ; PIN_AE11 ; QSF Assignment ; +; Location ; ; ; SW[7] ; PIN_AC9 ; QSF Assignment ; +; Location ; ; ; SW[8] ; PIN_AD10 ; QSF Assignment ; +; Location ; ; ; SW[9] ; PIN_AE12 ; QSF Assignment ; +; Location ; ; ; TD_CLK27 ; PIN_H15 ; QSF Assignment ; +; Location ; ; ; TD_DATA[0] ; PIN_D2 ; QSF Assignment ; +; Location ; ; ; TD_DATA[1] ; PIN_B1 ; QSF Assignment ; +; Location ; ; ; TD_DATA[2] ; PIN_E2 ; QSF Assignment ; +; Location ; ; ; TD_DATA[3] ; PIN_B2 ; QSF Assignment ; +; Location ; ; ; TD_DATA[4] ; PIN_D1 ; QSF Assignment ; +; Location ; ; ; TD_DATA[5] ; PIN_E1 ; QSF Assignment ; +; Location ; ; ; TD_DATA[6] ; PIN_C2 ; QSF Assignment ; +; Location ; ; ; TD_DATA[7] ; PIN_B3 ; QSF Assignment ; +; Location ; ; ; TD_HS ; PIN_A5 ; QSF Assignment ; +; Location ; ; ; TD_RESET_N ; PIN_F6 ; QSF Assignment ; +; Location ; ; ; TD_VS ; PIN_A3 ; QSF Assignment ; +; Location ; ; ; USB_B2_CLK ; PIN_AF4 ; QSF Assignment ; +; Location ; ; ; USB_B2_DATA[0] ; PIN_AH4 ; QSF Assignment ; +; Location ; ; ; USB_B2_DATA[1] ; PIN_AH3 ; QSF Assignment ; +; Location ; ; ; USB_B2_DATA[2] ; PIN_AJ2 ; QSF Assignment ; +; Location ; ; ; USB_B2_DATA[3] ; PIN_AJ1 ; QSF Assignment ; +; Location ; ; ; USB_B2_DATA[4] ; PIN_AH2 ; QSF Assignment ; +; Location ; ; ; USB_B2_DATA[5] ; PIN_AG3 ; QSF Assignment ; +; Location ; ; ; USB_B2_DATA[6] ; PIN_AG2 ; QSF Assignment ; +; Location ; ; ; USB_B2_DATA[7] ; PIN_AG1 ; QSF Assignment ; +; Location ; ; ; USB_EMPTY ; PIN_AF5 ; QSF Assignment ; +; Location ; ; ; USB_FULL ; PIN_AG5 ; QSF Assignment ; +; Location ; ; ; USB_OE_N ; PIN_AF6 ; QSF Assignment ; +; Location ; ; ; USB_RD_N ; PIN_AG6 ; QSF Assignment ; +; Location ; ; ; USB_RESET_N ; PIN_AG7 ; QSF Assignment ; +; Location ; ; ; USB_SCL ; PIN_AG8 ; QSF Assignment ; +; Location ; ; ; USB_SDA ; PIN_AF8 ; QSF Assignment ; +; Location ; ; ; USB_WR_N ; PIN_AH5 ; QSF Assignment ; +; Location ; ; ; VGA_BLANK_N ; PIN_F10 ; QSF Assignment ; +; Location ; ; ; VGA_B[0] ; PIN_B13 ; QSF Assignment ; +; Location ; ; ; VGA_B[1] ; PIN_G13 ; QSF Assignment ; +; Location ; ; ; VGA_B[2] ; PIN_H13 ; QSF Assignment ; +; Location ; ; ; VGA_B[3] ; PIN_F14 ; QSF Assignment ; +; Location ; ; ; VGA_B[4] ; PIN_H14 ; QSF Assignment ; +; Location ; ; ; VGA_B[5] ; PIN_F15 ; QSF Assignment ; +; Location ; ; ; VGA_B[6] ; PIN_G15 ; QSF Assignment ; +; Location ; ; ; VGA_B[7] ; PIN_J14 ; QSF Assignment ; +; Location ; ; ; VGA_CLK ; PIN_A11 ; QSF Assignment ; +; Location ; ; ; VGA_G[0] ; PIN_J9 ; QSF Assignment ; +; Location ; ; ; VGA_G[1] ; PIN_J10 ; QSF Assignment ; +; Location ; ; ; VGA_G[2] ; PIN_H12 ; QSF Assignment ; +; Location ; ; ; VGA_G[3] ; PIN_G10 ; QSF Assignment ; +; Location ; ; ; VGA_G[4] ; PIN_G11 ; QSF Assignment ; +; Location ; ; ; VGA_G[5] ; PIN_G12 ; QSF Assignment ; +; Location ; ; ; VGA_G[6] ; PIN_F11 ; QSF Assignment ; +; Location ; ; ; VGA_G[7] ; PIN_E11 ; QSF Assignment ; +; Location ; ; ; VGA_HS ; PIN_B11 ; QSF Assignment ; +; Location ; ; ; VGA_R[0] ; PIN_A13 ; QSF Assignment ; +; Location ; ; ; VGA_R[1] ; PIN_C13 ; QSF Assignment ; +; Location ; ; ; VGA_R[2] ; PIN_E13 ; QSF Assignment ; +; Location ; ; ; VGA_R[3] ; PIN_B12 ; QSF Assignment ; +; Location ; ; ; VGA_R[4] ; PIN_C12 ; QSF Assignment ; +; Location ; ; ; VGA_R[5] ; PIN_D12 ; QSF Assignment ; +; Location ; ; ; VGA_R[6] ; PIN_E12 ; QSF Assignment ; +; Location ; ; ; VGA_R[7] ; PIN_F13 ; QSF Assignment ; +; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ; +; Location ; ; ; VGA_VS ; PIN_D11 ; QSF Assignment ; ++----------+----------------+--------------+----------------+---------------+----------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+---------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+---------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 4062 ) ; 0.00 % ( 0 / 4062 ) ; 0.00 % ( 0 / 4062 ) ; +; -- Achieved ; 0.00 % ( 0 / 4062 ) ; 0.00 % ( 0 / 4062 ) ; 0.00 % ( 0 / 4062 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+---------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 4062 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.pin. + + ++---------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-------------------------------------------------------------+-----------------------+-------+ +; Resource ; Usage ; % ; ++-------------------------------------------------------------+-----------------------+-------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 1,909 / 32,070 ; 6 % ; +; ALMs needed [=A-B+C] ; 1,909 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 2,125 / 32,070 ; 7 % ; +; [a] ALMs used for LUT logic and registers ; 230 ; ; +; [b] ALMs used for LUT logic ; 1,353 ; ; +; [c] ALMs used for registers ; 542 ; ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; +; [B] Estimate of ALMs recoverable by dense packing ; 227 / 32,070 ; < 1 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 11 / 32,070 ; < 1 % ; +; [a] Due to location constrained logic ; 0 ; ; +; [b] Due to LAB-wide signal conflicts ; 2 ; ; +; [c] Due to LAB input limits ; 9 ; ; +; [d] Due to virtual I/Os ; 0 ; ; +; ; ; ; +; Difficulty packing design ; Low ; ; +; ; ; ; +; Total LABs: partially or completely used ; 287 / 3,207 ; 9 % ; +; -- Logic LABs ; 287 ; ; +; -- Memory LABs (up to half of total LABs) ; 0 ; ; +; ; ; ; +; Combinational ALUT usage for logic ; 2,444 ; ; +; -- 7 input functions ; 16 ; ; +; -- 6 input functions ; 1,457 ; ; +; -- 5 input functions ; 255 ; ; +; -- 4 input functions ; 240 ; ; +; -- <=3 input functions ; 476 ; ; +; Combinational ALUT usage for route-throughs ; 228 ; ; +; ; ; ; +; Dedicated logic registers ; 1,563 ; ; +; -- By type: ; ; ; +; -- Primary logic registers ; 1,544 / 64,140 ; 2 % ; +; -- Secondary logic registers ; 19 / 64,140 ; < 1 % ; +; -- By function: ; ; ; +; -- Design implementation registers ; 1,551 ; ; +; -- Routing optimization registers ; 12 ; ; +; ; ; ; +; Virtual pins ; 0 ; ; +; I/O pins ; 17 / 457 ; 4 % ; +; -- Clock pins ; 2 / 8 ; 25 % ; +; -- Dedicated input pins ; 0 / 21 ; 0 % ; +; ; ; ; +; Hard processor system peripheral utilization ; ; ; +; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ; +; -- Clock resets ; 0 / 1 ( 0 % ) ; ; +; -- Cross trigger ; 0 / 1 ( 0 % ) ; ; +; -- S2F AXI ; 0 / 1 ( 0 % ) ; ; +; -- F2S AXI ; 0 / 1 ( 0 % ) ; ; +; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ; +; -- SDRAM ; 0 / 1 ( 0 % ) ; ; +; -- Interrupts ; 0 / 1 ( 0 % ) ; ; +; -- JTAG ; 0 / 1 ( 0 % ) ; ; +; -- Loan I/O ; 0 / 1 ( 0 % ) ; ; +; -- MPU event standby ; 0 / 1 ( 0 % ) ; ; +; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ; +; -- STM event ; 0 / 1 ( 0 % ) ; ; +; -- TPIU trace ; 0 / 1 ( 0 % ) ; ; +; -- DMA ; 0 / 1 ( 0 % ) ; ; +; -- CAN ; 0 / 2 ( 0 % ) ; ; +; -- EMAC ; 0 / 2 ( 0 % ) ; ; +; -- I2C ; 0 / 4 ( 0 % ) ; ; +; -- NAND Flash ; 0 / 1 ( 0 % ) ; ; +; -- QSPI ; 0 / 1 ( 0 % ) ; ; +; -- SDMMC ; 0 / 1 ( 0 % ) ; ; +; -- SPI Master ; 0 / 2 ( 0 % ) ; ; +; -- SPI Slave ; 0 / 2 ( 0 % ) ; ; +; -- UART ; 0 / 2 ( 0 % ) ; ; +; -- USB ; 0 / 2 ( 0 % ) ; ; +; ; ; ; +; M10K blocks ; 4 / 397 ; 1 % ; +; Total MLAB memory bits ; 0 ; ; +; Total block memory bits ; 16,384 / 4,065,280 ; < 1 % ; +; Total block memory implementation bits ; 40,960 / 4,065,280 ; 1 % ; +; ; ; ; +; Total DSP Blocks ; 0 / 87 ; 0 % ; +; ; ; ; +; Fractional PLLs ; 0 / 6 ; 0 % ; +; Global signals ; 1 ; ; +; -- Global clocks ; 1 / 16 ; 6 % ; +; -- Quadrant clocks ; 0 / 66 ; 0 % ; +; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ; +; SERDES Transmitters ; 0 / 100 ; 0 % ; +; SERDES Receivers ; 0 / 100 ; 0 % ; +; JTAGs ; 0 / 1 ; 0 % ; +; ASMI blocks ; 0 / 1 ; 0 % ; +; CRC blocks ; 0 / 1 ; 0 % ; +; Remote update blocks ; 0 / 1 ; 0 % ; +; Oscillator blocks ; 0 / 1 ; 0 % ; +; Impedance control blocks ; 0 / 4 ; 0 % ; +; Hard Memory Controllers ; 0 / 2 ; 0 % ; +; Average interconnect usage (total/H/V) ; 2.0% / 2.2% / 1.6% ; ; +; Peak interconnect usage (total/H/V) ; 23.3% / 24.5% / 19.5% ; ; +; Maximum fan-out ; 1567 ; ; +; Highest non-global fan-out ; 1027 ; ; +; Total fan-out ; 18478 ; ; +; Average fan-out ; 4.32 ; ; ++-------------------------------------------------------------+-----------------------+-------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 1909 / 32070 ( 6 % ) ; 0 / 32070 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 1909 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 2125 / 32070 ( 7 % ) ; 0 / 32070 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 230 ; 0 ; +; [b] ALMs used for LUT logic ; 1353 ; 0 ; +; [c] ALMs used for registers ; 542 ; 0 ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; +; [B] Estimate of ALMs recoverable by dense packing ; 227 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 11 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [a] Due to location constrained logic ; 0 ; 0 ; +; [b] Due to LAB-wide signal conflicts ; 2 ; 0 ; +; [c] Due to LAB input limits ; 9 ; 0 ; +; [d] Due to virtual I/Os ; 0 ; 0 ; +; ; ; ; +; Difficulty packing design ; Low ; Low ; +; ; ; ; +; Total LABs: partially or completely used ; 287 / 3207 ( 9 % ) ; 0 / 3207 ( 0 % ) ; +; -- Logic LABs ; 287 ; 0 ; +; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; +; ; ; ; +; Combinational ALUT usage for logic ; 2444 ; 0 ; +; -- 7 input functions ; 16 ; 0 ; +; -- 6 input functions ; 1457 ; 0 ; +; -- 5 input functions ; 255 ; 0 ; +; -- 4 input functions ; 240 ; 0 ; +; -- <=3 input functions ; 476 ; 0 ; +; Combinational ALUT usage for route-throughs ; 228 ; 0 ; +; Memory ALUT usage ; 0 ; 0 ; +; -- 64-address deep ; 0 ; 0 ; +; -- 32-address deep ; 0 ; 0 ; +; ; ; ; +; Dedicated logic registers ; 0 ; 0 ; +; -- By type: ; ; ; +; -- Primary logic registers ; 1544 / 64140 ( 2 % ) ; 0 / 64140 ( 0 % ) ; +; -- Secondary logic registers ; 19 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- By function: ; ; ; +; -- Design implementation registers ; 1551 ; 0 ; +; -- Routing optimization registers ; 12 ; 0 ; +; ; ; ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 17 ; 0 ; +; I/O registers ; 0 ; 0 ; +; Total block memory bits ; 16384 ; 0 ; +; Total block memory implementation bits ; 40960 ; 0 ; +; M10K block ; 4 / 397 ( 1 % ) ; 0 / 397 ( 0 % ) ; +; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 18514 ; 0 ; +; -- Registered Connections ; 5686 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 6 ; 0 ; +; -- Output Ports ; 11 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++-------------------------------------------------------------+-----------------------+--------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; CLOCK_50 ; AF14 ; 3B ; 32 ; 0 ; 0 ; 1567 ; 0 ; yes ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; +; KEY[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 262 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; +; KEY[1] ; AA15 ; 3B ; 36 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; +; KEY[2] ; W15 ; 3B ; 40 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; +; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; +; UART_TX ; E9 ; 8A ; 30 ; 81 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; LEDR[0] ; V16 ; 4A ; 52 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; LEDR[1] ; W16 ; 4A ; 52 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; LEDR[2] ; V17 ; 4A ; 60 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; LEDR[3] ; V18 ; 4A ; 80 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; LEDR[4] ; W17 ; 4A ; 60 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; LEDR[5] ; W19 ; 4A ; 80 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; LEDR[6] ; Y19 ; 4A ; 84 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; LEDR[7] ; W20 ; 5A ; 89 ; 6 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; LEDR[8] ; W21 ; 5A ; 89 ; 8 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; LEDR[9] ; Y21 ; 5A ; 89 ; 6 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; UART_RX ; D9 ; 8A ; 30 ; 81 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++---------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+-----------------+---------------+--------------+---------------+ +; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; 3A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 5 / 48 ( 10 % ) ; 2.5V ; -- ; 2.5V ; +; 4A ; 7 / 80 ( 9 % ) ; 2.5V ; -- ; 2.5V ; +; 5A ; 3 / 32 ( 9 % ) ; 2.5V ; -- ; 2.5V ; +; 5B ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 2 / 80 ( 3 % ) ; 2.5V ; -- ; 2.5V ; ++----------+-----------------+---------------+--------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ; +; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 122 ; 3B ; KEY[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA15 ; 120 ; 3B ; KEY[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA27 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB12 ; 72 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB23 ; 227 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB24 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB25 ; 230 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC11 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC12 ; 82 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC21 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC25 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC27 ; 242 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC28 ; 245 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC29 ; 247 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC30 ; 259 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD8 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD12 ; 80 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD27 ; 222 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD28 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD29 ; 255 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD30 ; 257 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE15 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE26 ; 220 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE27 ; 229 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE28 ; 231 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE29 ; 253 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE30 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF9 ; 67 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF10 ; 57 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF14 ; 114 ; 3B ; CLOCK_50 ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF28 ; 235 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AF29 ; 237 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AF30 ; 239 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG4 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG27 ; 212 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AG28 ; 233 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AG29 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AG30 ; 243 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH26 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH28 ; 214 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AH29 ; 218 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AH30 ; 241 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AJ29 ; 216 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ; +; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ; +; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ; +; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ; +; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D9 ; 480 ; 8A ; UART_RX ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ; +; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ; +; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 478 ; 8A ; UART_TX ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ; +; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ; +; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ; +; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ; +; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ; +; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ; +; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ; +; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ; +; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U23 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; V16 ; 138 ; 4A ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V17 ; 154 ; 4A ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V18 ; 194 ; 4A ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V22 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V24 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; W15 ; 130 ; 3B ; KEY[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W16 ; 136 ; 4A ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W17 ; 152 ; 4A ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W19 ; 192 ; 4A ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W20 ; 217 ; 5A ; LEDR[7] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W21 ; 221 ; 5A ; LEDR[8] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W23 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 128 ; 3B ; KEY[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 202 ; 4A ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 219 ; 5A ; LEDR[9] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; KEY[1] ; Incomplete set of assignments ; +; KEY[2] ; Incomplete set of assignments ; +; KEY[3] ; Incomplete set of assignments ; +; LEDR[0] ; Incomplete set of assignments ; +; LEDR[1] ; Incomplete set of assignments ; +; LEDR[2] ; Incomplete set of assignments ; +; LEDR[3] ; Incomplete set of assignments ; +; LEDR[4] ; Incomplete set of assignments ; +; LEDR[5] ; Incomplete set of assignments ; +; LEDR[6] ; Incomplete set of assignments ; +; LEDR[7] ; Incomplete set of assignments ; +; LEDR[8] ; Incomplete set of assignments ; +; LEDR[9] ; Incomplete set of assignments ; +; UART_RX ; Incomplete set of assignments ; +; CLOCK_50 ; Incomplete set of assignments ; +; KEY[0] ; Incomplete set of assignments ; +; UART_TX ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++-----------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------+--------------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++-----------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------+--------------------+--------------+ +; |top ; 1909.0 (35.1) ; 2125.0 (36.4) ; 226.5 (2.6) ; 10.5 (1.3) ; 0.0 (0.0) ; 2444 (70) ; 1563 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 17 ; 0 ; |top ; top ; work ; +; |memory_map:u_mem| ; 59.0 (59.0) ; 61.2 (61.2) ; 2.3 (2.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 98 (98) ; 10 (10) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem ; memory_map ; work ; +; |altsyncram:M0_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 4096 ; 1 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M0_rtl_0 ; altsyncram ; work ; +; |altsyncram_6lr1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 4096 ; 1 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M0_rtl_0|altsyncram_6lr1:auto_generated ; altsyncram_6lr1 ; work ; +; |altsyncram:M1_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 4096 ; 1 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M1_rtl_0 ; altsyncram ; work ; +; |altsyncram_7lr1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 4096 ; 1 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M1_rtl_0|altsyncram_7lr1:auto_generated ; altsyncram_7lr1 ; work ; +; |altsyncram:M2_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 4096 ; 1 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M2_rtl_0 ; altsyncram ; work ; +; |altsyncram_8lr1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 4096 ; 1 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M2_rtl_0|altsyncram_8lr1:auto_generated ; altsyncram_8lr1 ; work ; +; |altsyncram:M3_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 4096 ; 1 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M3_rtl_0 ; altsyncram ; work ; +; |altsyncram_9lr1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 4096 ; 1 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated ; altsyncram_9lr1 ; work ; +; |uart:u_uart| ; 82.5 (0.0) ; 84.0 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 151 (0) ; 81 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|uart:u_uart ; uart ; work ; +; |uart_rx:uart_rx_inst| ; 49.0 (49.0) ; 50.5 (50.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 89 (89) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|uart:u_uart|uart_rx:uart_rx_inst ; uart_rx ; work ; +; |uart_tx:uart_tx_inst| ; 33.5 (33.5) ; 33.5 (33.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 62 (62) ; 34 (34) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|uart:u_uart|uart_tx:uart_tx_inst ; uart_tx ; work ; +; |uart_bus_master:u_master| ; 370.8 (370.8) ; 420.5 (420.5) ; 51.5 (51.5) ; 1.8 (1.8) ; 0.0 (0.0) ; 521 (521) ; 227 (227) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|uart_bus_master:u_master ; uart_bus_master ; work ; +; |utoss_riscv:core| ; 1361.6 (121.4) ; 1522.9 (135.0) ; 168.6 (15.8) ; 7.3 (2.1) ; 0.0 (0.0) ; 1604 (168) ; 1245 (169) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core ; utoss_riscv ; work ; +; |ALU:alu| ; 331.4 (331.4) ; 347.4 (347.4) ; 16.6 (16.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 468 (468) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|ALU:alu ; ALU ; work ; +; |ControlFSM:control_fsm| ; 28.5 (28.5) ; 28.5 (28.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (52) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|ControlFSM:control_fsm ; ControlFSM ; work ; +; |Instruction_Decode:instruction_decode| ; 54.0 (45.6) ; 54.0 (45.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 107 (89) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|Instruction_Decode:instruction_decode ; Instruction_Decode ; work ; +; |ALUdecoder:instanceALUDec| ; 8.4 (8.4) ; 8.4 (8.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 18 (18) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec ; ALUdecoder ; work ; +; |MemoryLoader:MemLoad| ; 13.8 (13.8) ; 14.2 (14.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (34) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|MemoryLoader:MemLoad ; MemoryLoader ; work ; +; |fetch:fetch| ; 61.2 (61.2) ; 65.8 (65.8) ; 4.8 (4.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 95 (95) ; 67 (67) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|fetch:fetch ; fetch ; work ; +; |registerFile:RegFile| ; 750.1 (750.1) ; 878.0 (878.0) ; 132.3 (132.3) ; 4.3 (4.3) ; 0.0 (0.0) ; 680 (680) ; 992 (992) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|registerFile:RegFile ; registerFile ; work ; ++-----------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------+--------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; KEY[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; KEY[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; KEY[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; UART_RX ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; KEY[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; UART_TX ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------------------------------+-------------------+---------+ +; KEY[1] ; ; ; +; KEY[2] ; ; ; +; KEY[3] ; ; ; +; CLOCK_50 ; ; ; +; KEY[0] ; ; ; +; - uart:u_uart|uart_rx:uart_rx_inst|o_data[0] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|o_data[2] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|o_data[1] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|o_data[6] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|o_data[7] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|o_data[3] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|o_data[5] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|o_data[4] ; 0 ; 0 ; +; - uart_bus_master:u_master|cmd[5] ; 0 ; 0 ; +; - uart_bus_master:u_master|cmd[0] ; 0 ; 0 ; +; - uart_bus_master:u_master|cmd[3] ; 0 ; 0 ; +; - uart_bus_master:u_master|cmd[6] ; 0 ; 0 ; +; - uart_bus_master:u_master|cmd[2] ; 0 ; 0 ; +; - uart_bus_master:u_master|cmd[7] ; 0 ; 0 ; +; - uart_bus_master:u_master|cmd[1] ; 0 ; 0 ; +; - uart_bus_master:u_master|cmd[4] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[13] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[14] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[15] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[16] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[25] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[24] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[26] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[27] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[28] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[29] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[30] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[31] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[23] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[10] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[11] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[22] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[21] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[20] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[9] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[19] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[18] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[17] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[8] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[0] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[1] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[2] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[3] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[4] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[5] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[12] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[6] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[7] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[26] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[27] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[28] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[29] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[30] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[31] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[10] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[12] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[13] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[14] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[15] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[16] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[9] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[8] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[7] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[6] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[5] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[4] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[3] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[2] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[17] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[1] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[0] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[11] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[18] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[19] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[20] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[21] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[22] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[23] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[24] ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[25] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[18] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[7] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[8] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[6] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[3] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[2] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[1] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[9] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[10] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[11] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[5] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[12] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[13] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[4] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[14] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[0] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[15] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[16] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[17] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[12] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[15] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[14] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[2] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[13] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[0] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[1] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[5] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[18] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[11] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[17] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[10] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[9] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[8] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[16] ; 0 ; 0 ; +; - uart_bus_master:u_master|chk_calc[1] ; 0 ; 0 ; +; - uart_bus_master:u_master|chk_calc[2] ; 0 ; 0 ; +; - uart_bus_master:u_master|chk_calc[3] ; 0 ; 0 ; +; - uart_bus_master:u_master|chk_calc[4] ; 0 ; 0 ; +; - uart_bus_master:u_master|chk_calc[0] ; 0 ; 0 ; +; - uart_bus_master:u_master|chk_calc[5] ; 0 ; 0 ; +; - uart_bus_master:u_master|chk_calc[6] ; 0 ; 0 ; +; - uart_bus_master:u_master|chk_calc[7] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|o_txd ; 0 ; 0 ; +; - uart_bus_master:u_master|hold_core ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|o_valid ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|o_ready ; 0 ; 0 ; +; - uart_bus_master:u_master|tx_valid ; 0 ; 0 ; +; - uart_bus_master:u_master|resp_len[0] ; 0 ; 0 ; +; - uart_bus_master:u_master|resp_len[1] ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|state ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|data_reg[0] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|data_reg[2] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|data_reg[1] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|data_reg[6] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|data_reg[7] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|data_reg[3] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|data_reg[5] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|data_reg[4] ; 0 ; 0 ; +; - uart_bus_master:u_master|state.STATE_CHK ; 0 ; 0 ; +; - uart_bus_master:u_master|state.STATE_CMD ; 0 ; 0 ; +; - uart_bus_master:u_master|resp_len[2] ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|state.STATE_STOP ; 0 ; 0 ; +; - uart_bus_master:u_master|state.STATE_D0 ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_data[26]~0 ; 0 ; 0 ; +; - core_reset ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~24 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~25 ; 0 ; 0 ; +; - utoss_riscv:core|fetch:fetch|pc_cur[18]~1 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~27 ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_write_enable~0 ; 0 ; 0 ; +; - uart_bus_master:u_master|bus_addr[13]~0 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|data_reg~0 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|data_reg[2]~1 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|timer[18]~2 ; 0 ; 0 ; +; - uart_bus_master:u_master|wdata[0]~0 ; 0 ; 0 ; +; - uart_bus_master:u_master|wdata[0]~1 ; 0 ; 0 ; +; - uart_bus_master:u_master|state~38 ; 0 ; 0 ; +; - uart_bus_master:u_master|cmd[5]~0 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|o_data[0]~0 ; 0 ; 0 ; +; - uart_bus_master:u_master|chk_calc[1]~0 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[8][18]~0 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[9][4]~1 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[10][5]~2 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[11][27]~3 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[12][24]~4 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[13][26]~5 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[14][16]~6 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[15][4]~7 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[16][15]~8 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[20][26]~9 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[24][4]~10 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[28][8]~11 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[17][1]~12 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[21][28]~13 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[25][4]~14 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[29][3]~15 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[18][1]~16 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[22][16]~17 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[26][8]~18 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[30][22]~19 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[19][20]~20 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[23][9]~21 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[27][1]~22 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[31][7]~23 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[2][2]~24 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[3][31]~25 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[4][14]~26 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[5][9]~27 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[6][1]~28 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[7][2]~29 ; 0 ; 0 ; +; - utoss_riscv:core|registerFile:RegFile|RFMem[1][17]~30 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~28 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~29 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~30 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~31 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~32 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~33 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~34 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~35 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~36 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~37 ; 0 ; 0 ; +; - uart_bus_master:u_master|addr[1]~0 ; 0 ; 0 ; +; - uart_bus_master:u_master|addr[1]~1 ; 0 ; 0 ; +; - uart_bus_master:u_master|state~41 ; 0 ; 0 ; +; - uart_bus_master:u_master|state~42 ; 0 ; 0 ; +; - uart_bus_master:u_master|addr[11]~2 ; 0 ; 0 ; +; - uart_bus_master:u_master|addr[11]~3 ; 0 ; 0 ; +; - uart_bus_master:u_master|addr[20]~4 ; 0 ; 0 ; +; - uart_bus_master:u_master|addr[20]~5 ; 0 ; 0 ; +; - uart_bus_master:u_master|addr[24]~6 ; 0 ; 0 ; +; - uart_bus_master:u_master|addr[24]~7 ; 0 ; 0 ; +; - uart_bus_master:u_master|wdata[8]~2 ; 0 ; 0 ; +; - uart_bus_master:u_master|wdata[8]~3 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|bit_idx~0 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|bit_idx~1 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|bit_idx~2 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|bit_idx~3 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|data_reg~2 ; 0 ; 0 ; +; - uart_bus_master:u_master|tx_data[7]~4 ; 0 ; 0 ; +; - uart_bus_master:u_master|tx_data[7]~5 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|rxd_q1~0 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[3]~3 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[3]~15 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[4]~17 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[6]~19 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|timer[7]~21 ; 0 ; 0 ; +; - uart_bus_master:u_master|state~43 ; 0 ; 0 ; +; - uart_bus_master:u_master|state~45 ; 0 ; 0 ; +; - uart_bus_master:u_master|state~46 ; 0 ; 0 ; +; - uart_bus_master:u_master|state~47 ; 0 ; 0 ; +; - uart_bus_master:u_master|state~51 ; 0 ; 0 ; +; - utoss_riscv:core|ControlFSM:control_fsm|current_state~38 ; 0 ; 0 ; +; - uart_bus_master:u_master|state~52 ; 0 ; 0 ; +; - uart_bus_master:u_master|resp_idx~0 ; 0 ; 0 ; +; - uart_bus_master:u_master|resp_idx[0]~1 ; 0 ; 0 ; +; - uart_bus_master:u_master|resp_len[1]~3 ; 0 ; 0 ; +; - uart_bus_master:u_master|resp_idx~3 ; 0 ; 0 ; +; - uart_bus_master:u_master|resp_idx~4 ; 0 ; 0 ; +; - uart_bus_master:u_master|resp_idx[0]~5 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|data_reg~3 ; 0 ; 0 ; +; - uart_bus_master:u_master|resp[6][0]~3 ; 0 ; 0 ; +; - uart_bus_master:u_master|resp[2][0]~4 ; 0 ; 0 ; +; - uart_bus_master:u_master|resp[5][4]~5 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|state~20 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|state~22 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|bit_idx~0 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|bit_idx[3]~3 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|bit_idx~4 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|bit_idx~5 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|bit_idx~6 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|rxd_q0~0 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|state~23 ; 0 ; 0 ; +; - uart:u_uart|uart_rx:uart_rx_inst|rxd_q1_d~0 ; 0 ; 0 ; +; - uart_bus_master:u_master|wdata[21]~4 ; 0 ; 0 ; +; - uart_bus_master:u_master|wdata[28]~5 ; 0 ; 0 ; +; - uart_bus_master:u_master|wdata[28]~6 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|data_reg~4 ; 0 ; 0 ; +; - uart_bus_master:u_master|reg_idx[4]~0 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|data_reg~5 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|data_reg~6 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|data_reg~7 ; 0 ; 0 ; +; - uart:u_uart|uart_tx:uart_tx_inst|data_reg~8 ; 0 ; 0 ; +; UART_TX ; ; ; +; - uart:u_uart|uart_rx:uart_rx_inst|rxd_q0~0 ; 1 ; 0 ; ++-----------------------------------------------------------------+-------------------+---------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++----------------------------------------------------------------------------------------------+---------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------------------------------------------------------------------------------------------+---------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_AF14 ; 1567 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; +; KEY[0] ; PIN_AA14 ; 262 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; core_reset ; LABCELL_X37_Y10_N6 ; 1027 ; Sync. clear ; no ; -- ; -- ; -- ; +; memory_map:u_mem|LEDR[0]~0 ; LABCELL_X33_Y8_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; memory_map:u_mem|M0~0 ; LABCELL_X33_Y8_N36 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; memory_map:u_mem|M1~0 ; LABCELL_X33_Y8_N57 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; memory_map:u_mem|M2~0 ; LABCELL_X33_Y8_N18 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; memory_map:u_mem|M3~0 ; LABCELL_X35_Y9_N3 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; uart:u_uart|uart_rx:uart_rx_inst|bit_idx[3]~3 ; MLABCELL_X28_Y3_N21 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; uart:u_uart|uart_rx:uart_rx_inst|o_data[0]~0 ; LABCELL_X30_Y3_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart:u_uart|uart_rx:uart_rx_inst|timer[3]~3 ; LABCELL_X30_Y3_N51 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[2]~1 ; LABCELL_X30_Y4_N0 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; uart:u_uart|uart_tx:uart_tx_inst|timer[18]~2 ; LABCELL_X29_Y7_N6 ; 19 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|addr[11]~2 ; LABCELL_X33_Y4_N45 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|addr[11]~3 ; LABCELL_X31_Y6_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|addr[1]~0 ; LABCELL_X33_Y4_N33 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|addr[1]~1 ; LABCELL_X31_Y5_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|addr[20]~4 ; LABCELL_X31_Y6_N3 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|addr[20]~5 ; LABCELL_X31_Y6_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|addr[24]~6 ; LABCELL_X30_Y6_N54 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|addr[24]~7 ; LABCELL_X30_Y6_N3 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|bus_addr[13]~0 ; LABCELL_X31_Y8_N12 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|bus_write_data[26]~0 ; LABCELL_X31_Y8_N33 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|chk_calc[1]~0 ; LABCELL_X30_Y5_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|cmd[5]~0 ; LABCELL_X30_Y6_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|reg_idx[4]~0 ; LABCELL_X30_Y6_N48 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|resp[2][0]~4 ; LABCELL_X31_Y8_N15 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|resp[5][4]~5 ; LABCELL_X30_Y7_N39 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|resp[6][0]~3 ; LABCELL_X30_Y7_N12 ; 24 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|resp_idx[0]~1 ; LABCELL_X30_Y7_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|resp_idx[0]~5 ; LABCELL_X35_Y11_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|resp_len[1]~3 ; LABCELL_X30_Y7_N45 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|state.STATE_CMD ; FF_X27_Y7_N32 ; 22 ; Sync. load ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|state.STATE_DO_RD1 ; FF_X31_Y8_N38 ; 51 ; Sync. load ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|state~46 ; LABCELL_X30_Y6_N30 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|state~47 ; LABCELL_X30_Y6_N51 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|tx_data[7]~4 ; MLABCELL_X28_Y9_N51 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|tx_data[7]~5 ; LABCELL_X30_Y7_N9 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|wdata[0]~0 ; LABCELL_X27_Y8_N6 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|wdata[0]~1 ; LABCELL_X27_Y8_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|wdata[21]~4 ; LABCELL_X30_Y6_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|wdata[28]~5 ; LABCELL_X30_Y6_N24 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|wdata[28]~6 ; LABCELL_X30_Y6_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|wdata[8]~2 ; LABCELL_X27_Y7_N15 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_bus_master:u_master|wdata[8]~3 ; LABCELL_X27_Y7_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|ControlFSM:control_fsm|WideOr13 ; LABCELL_X29_Y8_N18 ; 4 ; Latch enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state.FETCH_WAIT ; FF_X29_Y8_N56 ; 71 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|Selector4~3 ; MLABCELL_X34_Y9_N33 ; 4 ; Latch enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3~0 ; LABCELL_X36_Y10_N48 ; 32 ; Latch enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|dataA[18]~4 ; LABCELL_X57_Y8_N54 ; 32 ; Sync. clear ; no ; -- ; -- ; -- ; +; utoss_riscv:core|dataB[6]~4 ; LABCELL_X37_Y10_N0 ; 34 ; Sync. clear ; no ; -- ; -- ; -- ; +; utoss_riscv:core|fetch:fetch|pc_cur[18]~1 ; LABCELL_X37_Y8_N54 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[10][5]~2 ; LABCELL_X53_Y11_N42 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[11][27]~3 ; LABCELL_X62_Y11_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[12][24]~4 ; LABCELL_X53_Y11_N45 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[13][26]~5 ; LABCELL_X62_Y11_N33 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[14][16]~6 ; LABCELL_X53_Y11_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[15][4]~7 ; LABCELL_X53_Y11_N21 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[16][15]~8 ; LABCELL_X61_Y11_N54 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[17][1]~12 ; LABCELL_X61_Y11_N9 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[18][1]~16 ; LABCELL_X61_Y11_N6 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[19][20]~20 ; LABCELL_X61_Y11_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[1][17]~30 ; LABCELL_X62_Y11_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[20][26]~9 ; LABCELL_X61_Y11_N3 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[21][28]~13 ; LABCELL_X62_Y11_N21 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[22][16]~17 ; LABCELL_X61_Y11_N45 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[23][9]~21 ; LABCELL_X61_Y11_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[24][4]~10 ; LABCELL_X61_Y11_N57 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[25][4]~14 ; LABCELL_X62_Y11_N9 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[26][8]~18 ; LABCELL_X61_Y11_N42 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[27][1]~22 ; LABCELL_X61_Y11_N21 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[28][8]~11 ; LABCELL_X62_Y11_N6 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[29][3]~15 ; LABCELL_X62_Y11_N42 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[2][2]~24 ; LABCELL_X53_Y11_N3 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[30][22]~19 ; LABCELL_X61_Y11_N0 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[31][7]~23 ; LABCELL_X61_Y11_N27 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[3][31]~25 ; LABCELL_X53_Y11_N39 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[4][14]~26 ; LABCELL_X53_Y11_N51 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[5][9]~27 ; LABCELL_X62_Y11_N48 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[6][1]~28 ; LABCELL_X53_Y11_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[7][2]~29 ; LABCELL_X53_Y11_N27 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[8][18]~0 ; LABCELL_X53_Y11_N0 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; utoss_riscv:core|registerFile:RegFile|RFMem[9][4]~1 ; LABCELL_X53_Y11_N36 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; ++----------------------------------------------------------------------------------------------+---------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_AF14 ; 1567 ; Global Clock ; GCLK6 ; -- ; ++----------+----------+---------+----------------------+------------------+---------------------------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++------------+--------------------+ +; Name ; Fan-Out ; ++------------+--------------------+ +; core_reset ; 1027 ; ++------------+--------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++--------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+-----------------------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLABs ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ; ++--------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+-----------------------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +; memory_map:u_mem|altsyncram:M0_rtl_0|altsyncram_6lr1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 512 ; 8 ; 512 ; 8 ; yes ; no ; yes ; no ; 4096 ; 512 ; 8 ; 512 ; 8 ; 4096 ; 1 ; 0 ; db/top.ram0_memory_map_ee718c45.hdl.mif ; M10K_X38_Y8_N0 ; Old data ; New data ; New data ; Off ; No ; No - Address Too Wide ; +; memory_map:u_mem|altsyncram:M1_rtl_0|altsyncram_7lr1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 512 ; 8 ; 512 ; 8 ; yes ; no ; yes ; no ; 4096 ; 512 ; 8 ; 512 ; 8 ; 4096 ; 1 ; 0 ; db/top.ram1_memory_map_ee718c45.hdl.mif ; M10K_X26_Y8_N0 ; Old data ; New data ; New data ; Off ; No ; No - Address Too Wide ; +; memory_map:u_mem|altsyncram:M2_rtl_0|altsyncram_8lr1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 512 ; 8 ; 512 ; 8 ; yes ; no ; yes ; no ; 4096 ; 512 ; 8 ; 512 ; 8 ; 4096 ; 1 ; 0 ; db/top.ram2_memory_map_ee718c45.hdl.mif ; M10K_X26_Y9_N0 ; Old data ; New data ; New data ; Off ; No ; No - Address Too Wide ; +; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 512 ; 8 ; 512 ; 8 ; yes ; no ; yes ; no ; 4096 ; 512 ; 8 ; 512 ; 8 ; 4096 ; 1 ; 0 ; db/top.ram3_memory_map_ee718c45.hdl.mif ; M10K_X38_Y9_N0 ; Old data ; New data ; New data ; Off ; No ; No - Address Too Wide ; ++--------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+-----------------------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++-----------------------------------------------------------------------+ +; Routing Usage Summary ; ++---------------------------------------------+-------------------------+ +; Routing Resource Type ; Usage ; ++---------------------------------------------+-------------------------+ +; Block interconnects ; 6,879 / 289,320 ( 2 % ) ; +; C12 interconnects ; 26 / 13,420 ( < 1 % ) ; +; C2 interconnects ; 2,256 / 119,108 ( 2 % ) ; +; C4 interconnects ; 1,147 / 56,300 ( 2 % ) ; +; DQS bus muxes ; 0 / 25 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ; +; Direct links ; 264 / 289,320 ( < 1 % ) ; +; Global clocks ; 1 / 16 ( 6 % ) ; +; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; +; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ; +; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ; +; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ; +; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ; +; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ; +; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ; +; Local interconnects ; 1,529 / 84,580 ( 2 % ) ; +; Quadrant clocks ; 0 / 66 ( 0 % ) ; +; R14 interconnects ; 242 / 12,676 ( 2 % ) ; +; R14/C12 interconnect drivers ; 252 / 20,720 ( 1 % ) ; +; R3 interconnects ; 3,055 / 130,992 ( 2 % ) ; +; R6 interconnects ; 5,046 / 266,960 ( 2 % ) ; +; Spine clocks ; 4 / 360 ( 1 % ) ; +; Wire stub REs ; 0 / 15,858 ( 0 % ) ; ++---------------------------------------------+-------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 28 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 19 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +; Total Pass ; 17 ; 0 ; 17 ; 0 ; 0 ; 17 ; 17 ; 0 ; 17 ; 17 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 17 ; 0 ; 17 ; 17 ; 0 ; 0 ; 17 ; 0 ; 0 ; 17 ; 6 ; 17 ; 17 ; 17 ; 17 ; 6 ; 17 ; 17 ; 17 ; 17 ; 6 ; 17 ; 17 ; 17 ; 17 ; 17 ; 17 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; KEY[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; KEY[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; KEY[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; LEDR[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; LEDR[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; LEDR[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; LEDR[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; LEDR[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; LEDR[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; LEDR[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; LEDR[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; LEDR[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; LEDR[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; UART_RX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; KEY[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; UART_TX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ + + ++------------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+-----------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+-----------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable CvP_CONFDONE pin ; Off ; +; Enable open drain on CRC_ERROR pin ; On ; +; Enable open drain on CvP_CONFDONE pin ; On ; +; Enable open drain on INIT_DONE pin ; On ; +; Enable open drain on Partial Reconfiguration pins ; Off ; +; Enable open drain on nCEO pin ; On ; +; Enable Partial Reconfiguration pins ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Enable internal scrubbing ; Off ; +; Active Serial clock source ; 100 MHz Internal Oscillator ; +; Device initialization clock source ; Internal Oscillator ; +; Configuration via Protocol ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Enable nCEO output ; Off ; +; Data[15..8] ; Unreserved ; +; Data[7..5] ; Unreserved ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+-----------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.10 V ; +; Low Junction Temperature ; 0 C ; +; High Junction Temperature ; 85 C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ +; CLOCK_50 ; CLOCK_50 ; 31.5 ; ++-----------------+----------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer. + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++-------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++-------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------+-------------------+ +; uart_bus_master:u_master|chk_calc[4] ; uart_bus_master:u_master|resp[1][1] ; 0.861 ; +; uart_bus_master:u_master|chk_calc[7] ; uart_bus_master:u_master|resp[1][1] ; 0.861 ; +; uart_bus_master:u_master|chk_calc[1] ; uart_bus_master:u_master|resp[1][1] ; 0.857 ; +; uart_bus_master:u_master|chk_calc[2] ; uart_bus_master:u_master|resp[1][1] ; 0.857 ; +; uart_bus_master:u_master|chk_calc[5] ; uart_bus_master:u_master|resp[1][1] ; 0.843 ; +; uart_bus_master:u_master|chk_calc[6] ; uart_bus_master:u_master|resp[1][1] ; 0.843 ; +; uart_bus_master:u_master|chk_calc[3] ; uart_bus_master:u_master|resp[1][1] ; 0.831 ; +; uart_bus_master:u_master|cmd[5] ; uart_bus_master:u_master|resp[1][1] ; 0.830 ; +; uart_bus_master:u_master|cmd[7] ; uart_bus_master:u_master|resp[1][1] ; 0.825 ; +; uart_bus_master:u_master|cmd[6] ; uart_bus_master:u_master|resp[1][1] ; 0.814 ; +; uart_bus_master:u_master|chk_calc[0] ; uart_bus_master:u_master|resp[1][1] ; 0.674 ; +; uart_bus_master:u_master|cmd[3] ; uart_bus_master:u_master|resp[1][1] ; 0.619 ; +; uart_bus_master:u_master|cmd[4] ; uart_bus_master:u_master|resp[1][1] ; 0.619 ; +; uart:u_uart|uart_rx:uart_rx_inst|o_data[1] ; uart_bus_master:u_master|state.STATE_REG ; 0.449 ; +; uart:u_uart|uart_rx:uart_rx_inst|o_data[3] ; uart_bus_master:u_master|state.STATE_REG ; 0.432 ; +; uart:u_uart|uart_rx:uart_rx_inst|o_data[6] ; uart_bus_master:u_master|state.STATE_REG ; 0.412 ; +; uart:u_uart|uart_rx:uart_rx_inst|o_data[2] ; uart_bus_master:u_master|state.STATE_REG ; 0.399 ; +; uart:u_uart|uart_tx:uart_tx_inst|bit_idx[1] ; uart:u_uart|uart_tx:uart_tx_inst|bit_idx[2] ; 0.362 ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state.LUI ; utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB ; 0.359 ; +; uart:u_uart|uart_rx:uart_rx_inst|bit_idx[1] ; uart:u_uart|uart_rx:uart_rx_inst|bit_idx[3] ; 0.358 ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state.DECODE ; utoss_riscv:core|ControlFSM:control_fsm|current_state.UNCONDJUMP ; 0.356 ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state.EXECUTER ; utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB ; 0.356 ; +; uart:u_uart|uart_rx:uart_rx_inst|bit_idx[2] ; uart:u_uart|uart_rx:uart_rx_inst|bit_idx[3] ; 0.355 ; +; uart:u_uart|uart_tx:uart_tx_inst|bit_idx[0] ; uart:u_uart|uart_tx:uart_tx_inst|bit_idx[2] ; 0.350 ; +; uart_bus_master:u_master|resp_idx[0] ; uart_bus_master:u_master|resp_idx[1] ; 0.348 ; +; uart_bus_master:u_master|bus_write_data[8] ; memory_map:u_mem|LEDR[8] ; 0.346 ; +; uart:u_uart|uart_rx:uart_rx_inst|rxd_q1 ; uart:u_uart|uart_rx:uart_rx_inst|data_reg[6] ; 0.330 ; +; utoss_riscv:core|alu_out[30] ; utoss_riscv:core|fetch:fetch|pc_cur[30] ; 0.329 ; +; uart_bus_master:u_master|resp[4][4] ; uart_bus_master:u_master|tx_data[4] ; 0.328 ; +; uart:u_uart|uart_rx:uart_rx_inst|bit_idx[0] ; uart:u_uart|uart_rx:uart_rx_inst|state.STATE_START ; 0.328 ; +; uart_bus_master:u_master|resp[4][7] ; uart_bus_master:u_master|tx_data[7] ; 0.327 ; +; uart_bus_master:u_master|resp[4][3] ; uart_bus_master:u_master|tx_data[3] ; 0.327 ; +; uart:u_uart|uart_rx:uart_rx_inst|o_data[0] ; uart_bus_master:u_master|state.STATE_WAIT_SOF ; 0.327 ; +; uart:u_uart|uart_rx:uart_rx_inst|o_data[4] ; uart_bus_master:u_master|state.STATE_WAIT_SOF ; 0.327 ; +; uart:u_uart|uart_rx:uart_rx_inst|o_data[5] ; uart_bus_master:u_master|state.STATE_WAIT_SOF ; 0.327 ; +; uart:u_uart|uart_rx:uart_rx_inst|o_data[7] ; uart_bus_master:u_master|state.STATE_WAIT_SOF ; 0.327 ; +; uart:u_uart|uart_rx:uart_rx_inst|o_valid ; uart_bus_master:u_master|state.STATE_WAIT_SOF ; 0.327 ; +; uart_bus_master:u_master|state.STATE_SEND ; uart_bus_master:u_master|state.STATE_WAIT_SOF ; 0.327 ; +; uart_bus_master:u_master|resp[4][5] ; uart_bus_master:u_master|tx_data[5] ; 0.323 ; +; uart_bus_master:u_master|resp[4][1] ; uart_bus_master:u_master|tx_data[1] ; 0.323 ; +; uart_bus_master:u_master|resp[4][2] ; uart_bus_master:u_master|tx_data[2] ; 0.322 ; +; uart_bus_master:u_master|resp[4][0] ; uart_bus_master:u_master|tx_data[0] ; 0.322 ; +; uart_bus_master:u_master|tx_valid ; uart:u_uart|uart_tx:uart_tx_inst|state ; 0.322 ; +; utoss_riscv:core|dataA[7] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.316 ; +; utoss_riscv:core|fetch:fetch|pc_old[7] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.316 ; +; utoss_riscv:core|ControlFSM:control_fsm|ALUSrcA[1] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.316 ; +; utoss_riscv:core|ControlFSM:control_fsm|ALUSrcA[0] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.316 ; +; utoss_riscv:core|fetch:fetch|pc_cur[7] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.316 ; +; uart_bus_master:u_master|resp_len[1] ; uart_bus_master:u_master|resp_idx[0] ; 0.313 ; +; uart_bus_master:u_master|cmd[0] ; uart_bus_master:u_master|state.STATE_DO_WR ; 0.309 ; +; uart_bus_master:u_master|resp_idx[1] ; uart_bus_master:u_master|resp_idx[0] ; 0.308 ; +; uart_bus_master:u_master|resp[5][5] ; uart_bus_master:u_master|tx_data[5] ; 0.300 ; +; uart_bus_master:u_master|resp[5][0] ; uart_bus_master:u_master|tx_data[0] ; 0.299 ; +; uart_bus_master:u_master|resp[5][4] ; uart_bus_master:u_master|tx_data[4] ; 0.298 ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state.EXECUTEI ; utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB ; 0.298 ; +; uart_bus_master:u_master|resp[5][2] ; uart_bus_master:u_master|tx_data[2] ; 0.297 ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state.MEMWB ; utoss_riscv:core|ControlFSM:control_fsm|current_state.FETCH ; 0.295 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[6] ; uart:u_uart|uart_tx:uart_tx_inst|data_reg[5] ; 0.293 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[4] ; uart:u_uart|uart_tx:uart_tx_inst|data_reg[3] ; 0.293 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[2] ; uart:u_uart|uart_tx:uart_tx_inst|data_reg[1] ; 0.293 ; +; uart_bus_master:u_master|resp[5][7] ; uart_bus_master:u_master|tx_data[7] ; 0.292 ; +; uart_bus_master:u_master|resp[5][3] ; uart_bus_master:u_master|tx_data[3] ; 0.292 ; +; uart:u_uart|uart_rx:uart_rx_inst|rxd_q0 ; uart:u_uart|uart_rx:uart_rx_inst|rxd_q1 ; 0.292 ; +; uart:u_uart|uart_rx:uart_rx_inst|state.STATE_DATA ; uart:u_uart|uart_rx:uart_rx_inst|data_reg[0] ; 0.288 ; +; uart_bus_master:u_master|bus_write_data[4] ; memory_map:u_mem|LEDR[4] ; 0.285 ; +; uart_bus_master:u_master|bus_write_data[1] ; memory_map:u_mem|LEDR[1] ; 0.285 ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB ; utoss_riscv:core|ControlFSM:control_fsm|current_state.FETCH ; 0.281 ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state.MEMWRITE ; utoss_riscv:core|ControlFSM:control_fsm|current_state.FETCH ; 0.281 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[7] ; uart:u_uart|uart_tx:uart_tx_inst|data_reg[6] ; 0.278 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[3] ; uart:u_uart|uart_tx:uart_tx_inst|data_reg[2] ; 0.277 ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state.JALR_CALC ; utoss_riscv:core|ControlFSM:control_fsm|current_state.JALR_STEP2 ; 0.276 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[1] ; uart:u_uart|uart_tx:uart_tx_inst|o_txd ; 0.275 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[5] ; uart:u_uart|uart_tx:uart_tx_inst|data_reg[4] ; 0.272 ; +; uart:u_uart|uart_tx:uart_tx_inst|bit_idx[2] ; uart:u_uart|uart_tx:uart_tx_inst|bit_idx[3] ; 0.272 ; +; uart:u_uart|uart_tx:uart_tx_inst|state ; uart:u_uart|uart_tx:uart_tx_inst|timer[4] ; 0.267 ; +; uart_bus_master:u_master|cmd[1] ; uart_bus_master:u_master|state.STATE_DO_WR ; 0.264 ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|alu_control[2] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[30] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[19] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[18] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[22] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[21] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[13] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[10] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[25] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[31] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[24] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|data[7] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[26] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[28] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[27] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|fetch:fetch|pc_cur[27] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|fetch:fetch|pc_old[27] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|fetch:fetch|pc_cur[28] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|fetch:fetch|pc_old[28] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[8] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[12] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|fetch:fetch|pc_cur[12] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|fetch:fetch|pc_old[12] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; +; utoss_riscv:core|dataA[11] ; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ram_block1a2~porta_address_reg0 ; 0.257 ; ++-------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------+-------------------+ +Note: This table only shows the top 100 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 16 of the 16 processors detected +Info (119006): Selected device 5CSEMA5F31C6 for design "top" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Info (184020): Starting Fitter periphery placement operations +Info (11191): Automatically promoted 1 clock (1 global) + Info (11162): CLOCK_50~inputCLKENA0 with 1583 fanout uses global clock CLKCTRL_G6 +Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 +Info (176233): Starting register packing +Warning (335093): The Timing Analyzer is analyzing 40 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report. +Info (332104): Reading SDC File: '../envs/de1-soc/quartus/top.sdc' +Warning (332174): Ignored filter at top.sdc(9): LEDR could not be matched with a port File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc Line: 9 +Warning (332049): Ignored set_false_path at top.sdc(9): Argument is an empty collection File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc Line: 9 + Info (332050): set_false_path -from [get_ports LEDR] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc Line: 9 +Warning (332049): Ignored set_false_path at top.sdc(10): Argument is an empty collection File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc Line: 10 + Info (332050): set_false_path -to [get_ports LEDR] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc Line: 10 +Warning (332060): Node: utoss_riscv:core|instruction[0] was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|alu_control[0] is being clocked by utoss_riscv:core|instruction[0] +Warning (332060): Node: utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch utoss_riscv:core|ControlFSM:control_fsm|ALUSrcA[0] is being clocked by utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 1 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 20.000 CLOCK_50 +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "ADC_CS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "ADC_DIN" is assigned to location or region, but does not exist in design + Warning (15706): Node "ADC_DOUT" is assigned to location or region, but does not exist in design + Warning (15706): Node "ADC_SCLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design + Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design + Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design + Warning (15706): Node "CLOCK4_50" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_LDQM" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_UDQM" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "FAN_CTRL" is assigned to location or region, but does not exist in design + Warning (15706): Node "FPGA_I2C_SCLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "FPGA_I2C_SDAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[16]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[17]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[18]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[19]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[20]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[21]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[22]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[23]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[24]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[25]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[26]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[27]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[28]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[29]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[30]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[31]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[32]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[33]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[34]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[35]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[16]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[17]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[18]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[19]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[20]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[21]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[22]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[23]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[24]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[25]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[26]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[27]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[28]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[29]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[30]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[31]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[32]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[33]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[34]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[35]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design + Warning (15706): Node "IRDA_TXD" is assigned to location or region, but does not exist in design + Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design + Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_B2_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_B2_DATA[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_B2_DATA[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_B2_DATA[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_B2_DATA[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_B2_DATA[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_B2_DATA[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_B2_DATA[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_B2_DATA[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_EMPTY" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_FULL" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_OE_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_RD_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_RESET_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_SCL" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_SDA" is assigned to location or region, but does not exist in design + Warning (15706): Node "USB_WR_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10 +Info (170189): Fitter placement preparation operations beginning +Info (14951): The Fitter is using Advanced Physical Optimization. +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:03:04 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 1% of the available device resources + Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X33_Y0 to location X44_Y10 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:04 +Info (11888): Total time spent on timing analysis during the Fitter is 3.52 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:09 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 254 warnings + Info: Peak virtual memory: 8049 megabytes + Info: Processing ended: Mon Jan 12 21:16:26 2026 + Info: Elapsed time: 00:06:43 + Info: Total CPU time (on all processors): 00:40:37 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.fit.smsg. + + diff --git a/quartus workspace/output_files/top.fit.smsg b/quartus workspace/output_files/top.fit.smsg new file mode 100644 index 0000000..9302919 --- /dev/null +++ b/quartus workspace/output_files/top.fit.smsg @@ -0,0 +1,6 @@ +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density +Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks diff --git a/quartus workspace/output_files/top.fit.summary b/quartus workspace/output_files/top.fit.summary new file mode 100644 index 0000000..a4e9cef --- /dev/null +++ b/quartus workspace/output_files/top.fit.summary @@ -0,0 +1,20 @@ +Fitter Status : Successful - Mon Jan 12 21:16:25 2026 +Quartus Prime Version : 22.1std.2 Build 922 07/20/2023 SC Lite Edition +Revision Name : top +Top-level Entity Name : top +Family : Cyclone V +Device : 5CSEMA5F31C6 +Timing Models : Final +Logic utilization (in ALMs) : 1,909 / 32,070 ( 6 % ) +Total registers : 1563 +Total pins : 17 / 457 ( 4 % ) +Total virtual pins : 0 +Total block memory bits : 16,384 / 4,065,280 ( < 1 % ) +Total RAM Blocks : 4 / 397 ( 1 % ) +Total DSP Blocks : 0 / 87 ( 0 % ) +Total HSSI RX PCSs : 0 +Total HSSI PMA RX Deserializers : 0 +Total HSSI TX PCSs : 0 +Total HSSI PMA TX Serializers : 0 +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) diff --git a/quartus workspace/output_files/top.flow.rpt b/quartus workspace/output_files/top.flow.rpt new file mode 100644 index 0000000..7b008cc --- /dev/null +++ b/quartus workspace/output_files/top.flow.rpt @@ -0,0 +1,119 @@ +Flow report for top +Mon Jan 12 21:53:13 2026 +Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2023 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++---------------------------------+------------------------------------------------+ +; Flow Status ; Successful - Mon Jan 12 21:53:13 2026 ; +; Quartus Prime Version ; 22.1std.2 Build 922 07/20/2023 SC Lite Edition ; +; Revision Name ; top ; +; Top-level Entity Name ; top ; +; Family ; Cyclone V ; +; Device ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 1551 ; +; Total pins ; 17 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 16,384 ; +; Total DSP Blocks ; 0 ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++---------------------------------+------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 01/12/2026 21:53:00 ; +; Main task ; Compilation ; +; Revision Name ; top ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 10995770589192.176827278003772 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:13 ; 1.0 ; 4949 MB ; 00:00:23 ; +; Total ; 00:00:13 ; -- ; -- ; 00:00:23 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; LAPTOP-NE01NI69 ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off top -c top + + + diff --git a/quartus workspace/output_files/top.jdi b/quartus workspace/output_files/top.jdi new file mode 100644 index 0000000..6013160 --- /dev/null +++ b/quartus workspace/output_files/top.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/quartus workspace/output_files/top.map.rpt b/quartus workspace/output_files/top.map.rpt new file mode 100644 index 0000000..01717b5 --- /dev/null +++ b/quartus workspace/output_files/top.map.rpt @@ -0,0 +1,1492 @@ +Analysis & Synthesis report for top +Mon Jan 12 21:53:13 2026 +Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis RAM Summary + 9. State Machine - |top|utoss_riscv:core|ControlFSM:control_fsm|current_state + 10. State Machine - |top|uart_bus_master:u_master|state + 11. State Machine - |top|uart:u_uart|uart_rx:uart_rx_inst|state + 12. User-Specified and Inferred Latches + 13. Registers Removed During Synthesis + 14. General Register Statistics + 15. Inverted Register Statistics + 16. Registers Packed Into Inferred Megafunctions + 17. Multiplexer Restructuring Statistics (Restructuring Performed) + 18. Source assignments for memory_map:u_mem|altsyncram:M0_rtl_0|altsyncram_6lr1:auto_generated + 19. Source assignments for memory_map:u_mem|altsyncram:M1_rtl_0|altsyncram_7lr1:auto_generated + 20. Source assignments for memory_map:u_mem|altsyncram:M2_rtl_0|altsyncram_8lr1:auto_generated + 21. Source assignments for memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated + 22. Parameter Settings for User Entity Instance: uart:u_uart + 23. Parameter Settings for User Entity Instance: uart:u_uart|uart_tx:uart_tx_inst + 24. Parameter Settings for User Entity Instance: uart:u_uart|uart_rx:uart_rx_inst + 25. Parameter Settings for User Entity Instance: memory_map:u_mem + 26. Parameter Settings for User Entity Instance: utoss_riscv:core|ControlFSM:control_fsm + 27. Parameter Settings for Inferred Entity Instance: memory_map:u_mem|altsyncram:M0_rtl_0 + 28. Parameter Settings for Inferred Entity Instance: memory_map:u_mem|altsyncram:M1_rtl_0 + 29. Parameter Settings for Inferred Entity Instance: memory_map:u_mem|altsyncram:M2_rtl_0 + 30. Parameter Settings for Inferred Entity Instance: memory_map:u_mem|altsyncram:M3_rtl_0 + 31. altsyncram Parameter Settings by Entity Instance + 32. Port Connectivity Checks: "utoss_riscv:core|Instruction_Decode:instruction_decode" + 33. Port Connectivity Checks: "utoss_riscv:core|ControlFSM:control_fsm" + 34. Port Connectivity Checks: "uart:u_uart" + 35. Post-Synthesis Netlist Statistics for Top Partition + 36. Elapsed Time Per Partition + 37. Analysis & Synthesis Messages + 38. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2023 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++---------------------------------+------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Jan 12 21:53:13 2026 ; +; Quartus Prime Version ; 22.1std.2 Build 922 07/20/2023 SC Lite Edition ; +; Revision Name ; top ; +; Top-level Entity Name ; top ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 1551 ; +; Total pins ; 17 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 16,384 ; +; Total DSP Blocks ; 0 ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++---------------------------------+------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 5CSEMA5F31C6 ; ; +; Top-level entity name ; top ; top ; +; Family name ; Cyclone V ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 3 ; 3 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Automatic Parallel Synthesis ; On ; On ; +; Partial Reconfiguration Bitstream ID ; Off ; Off ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 16 ; +; Maximum allowed ; 16 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 16 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.0% ; +; Processor 3 ; 0.0% ; +; Processor 4 ; 0.0% ; +; Processor 5 ; 0.0% ; +; Processor 6 ; 0.0% ; +; Processor 7 ; 0.0% ; +; Processor 8 ; 0.0% ; +; Processors 9-16 ; 0.0% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++-------------------------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++-------------------------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; ../envs/de1-soc/poc/poc3.mem ; yes ; User Unspecified File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/poc/poc3.mem ; ; +; ../envs/de1-soc/poc/poc2.mem ; yes ; User Unspecified File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/poc/poc2.mem ; ; +; ../envs/de1-soc/poc/poc1.mem ; yes ; User Unspecified File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/poc/poc1.mem ; ; +; ../envs/de1-soc/top.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv ; ; +; ../envs/de1-soc/memory_map.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv ; ; +; ../src/ALU_ALUdecoder/ALUdecoder.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv ; ; +; ../src/ALU_ALUdecoder/ALU.v ; yes ; User Verilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALU.v ; ; +; ../src/Instruction_Decode/MemoryLoader.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/MemoryLoader.sv ; ; +; ../src/Instruction_Decode/Instruction_Decode.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv ; ; +; ../src/utoss_riscv.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv ; ; +; ../src/fetch.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/fetch.sv ; ; +; ../src/ControlFSM.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv ; ; +; ../envs/de1-soc/poc/poc0.mem ; yes ; User Unspecified File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/poc/poc0.mem ; ; +; uart_rx.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv ; ; +; uart_tx.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_tx.sv ; ; +; uart.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart.sv ; ; +; uart_bus_master.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_bus_master.sv ; ; +; RegisterFile.sv ; yes ; User SystemVerilog HDL File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/RegisterFile.sv ; ; +; src/types.svh ; yes ; Auto-Found Unspecified File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/src/types.svh ; ; +; src/params.svh ; yes ; Auto-Found Unspecified File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/src/params.svh ; ; +; src/utils.svh ; yes ; Auto-Found Unspecified File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/src/utils.svh ; ; +; altsyncram.tdf ; yes ; Megafunction ; d:/intelfpga_lite/22.1std/quartus/libraries/megafunctions/altsyncram.tdf ; ; +; stratix_ram_block.inc ; yes ; Megafunction ; d:/intelfpga_lite/22.1std/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; +; lpm_mux.inc ; yes ; Megafunction ; d:/intelfpga_lite/22.1std/quartus/libraries/megafunctions/lpm_mux.inc ; ; +; lpm_decode.inc ; yes ; Megafunction ; d:/intelfpga_lite/22.1std/quartus/libraries/megafunctions/lpm_decode.inc ; ; +; aglobal221.inc ; yes ; Megafunction ; d:/intelfpga_lite/22.1std/quartus/libraries/megafunctions/aglobal221.inc ; ; +; a_rdenreg.inc ; yes ; Megafunction ; d:/intelfpga_lite/22.1std/quartus/libraries/megafunctions/a_rdenreg.inc ; ; +; altrom.inc ; yes ; Megafunction ; d:/intelfpga_lite/22.1std/quartus/libraries/megafunctions/altrom.inc ; ; +; altram.inc ; yes ; Megafunction ; d:/intelfpga_lite/22.1std/quartus/libraries/megafunctions/altram.inc ; ; +; altdpram.inc ; yes ; Megafunction ; d:/intelfpga_lite/22.1std/quartus/libraries/megafunctions/altdpram.inc ; ; +; db/altsyncram_6lr1.tdf ; yes ; Auto-Generated Megafunction ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_6lr1.tdf ; ; +; db/top.ram0_memory_map_ee718c45.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/top.ram0_memory_map_ee718c45.hdl.mif ; ; +; db/altsyncram_7lr1.tdf ; yes ; Auto-Generated Megafunction ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_7lr1.tdf ; ; +; db/top.ram1_memory_map_ee718c45.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/top.ram1_memory_map_ee718c45.hdl.mif ; ; +; db/altsyncram_8lr1.tdf ; yes ; Auto-Generated Megafunction ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_8lr1.tdf ; ; +; db/top.ram2_memory_map_ee718c45.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/top.ram2_memory_map_ee718c45.hdl.mif ; ; +; db/altsyncram_9lr1.tdf ; yes ; Auto-Generated Megafunction ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_9lr1.tdf ; ; +; db/top.ram3_memory_map_ee718c45.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/top.ram3_memory_map_ee718c45.hdl.mif ; ; ++-------------------------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimate of Logic utilization (ALMs needed) ; 2023 ; +; ; ; +; Combinational ALUT usage for logic ; 2443 ; +; -- 7 input functions ; 16 ; +; -- 6 input functions ; 1457 ; +; -- 5 input functions ; 255 ; +; -- 4 input functions ; 240 ; +; -- <=3 input functions ; 475 ; +; ; ; +; Dedicated logic registers ; 1551 ; +; ; ; +; I/O pins ; 17 ; +; Total MLAB memory bits ; 0 ; +; Total block memory bits ; 16384 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; CLOCK_50~input ; +; Maximum fan-out ; 1583 ; +; Total fan-out ; 18527 ; +; Average fan-out ; 4.56 ; ++---------------------------------------------+----------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------+--------------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++-----------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------+--------------------+--------------+ +; |top ; 2443 (69) ; 1551 (0) ; 16384 ; 0 ; 17 ; 0 ; |top ; top ; work ; +; |memory_map:u_mem| ; 98 (98) ; 10 (10) ; 16384 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem ; memory_map ; work ; +; |altsyncram:M0_rtl_0| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M0_rtl_0 ; altsyncram ; work ; +; |altsyncram_6lr1:auto_generated| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M0_rtl_0|altsyncram_6lr1:auto_generated ; altsyncram_6lr1 ; work ; +; |altsyncram:M1_rtl_0| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M1_rtl_0 ; altsyncram ; work ; +; |altsyncram_7lr1:auto_generated| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M1_rtl_0|altsyncram_7lr1:auto_generated ; altsyncram_7lr1 ; work ; +; |altsyncram:M2_rtl_0| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M2_rtl_0 ; altsyncram ; work ; +; |altsyncram_8lr1:auto_generated| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M2_rtl_0|altsyncram_8lr1:auto_generated ; altsyncram_8lr1 ; work ; +; |altsyncram:M3_rtl_0| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M3_rtl_0 ; altsyncram ; work ; +; |altsyncram_9lr1:auto_generated| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |top|memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated ; altsyncram_9lr1 ; work ; +; |uart:u_uart| ; 151 (0) ; 81 (0) ; 0 ; 0 ; 0 ; 0 ; |top|uart:u_uart ; uart ; work ; +; |uart_rx:uart_rx_inst| ; 89 (89) ; 47 (47) ; 0 ; 0 ; 0 ; 0 ; |top|uart:u_uart|uart_rx:uart_rx_inst ; uart_rx ; work ; +; |uart_tx:uart_tx_inst| ; 62 (62) ; 34 (34) ; 0 ; 0 ; 0 ; 0 ; |top|uart:u_uart|uart_tx:uart_tx_inst ; uart_tx ; work ; +; |uart_bus_master:u_master| ; 521 (521) ; 227 (227) ; 0 ; 0 ; 0 ; 0 ; |top|uart_bus_master:u_master ; uart_bus_master ; work ; +; |utoss_riscv:core| ; 1604 (168) ; 1233 (160) ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core ; utoss_riscv ; work ; +; |ALU:alu| ; 468 (468) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|ALU:alu ; ALU ; work ; +; |ControlFSM:control_fsm| ; 52 (52) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|ControlFSM:control_fsm ; ControlFSM ; work ; +; |Instruction_Decode:instruction_decode| ; 107 (89) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|Instruction_Decode:instruction_decode ; Instruction_Decode ; work ; +; |ALUdecoder:instanceALUDec| ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec ; ALUdecoder ; work ; +; |MemoryLoader:MemLoad| ; 34 (34) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|MemoryLoader:MemLoad ; MemoryLoader ; work ; +; |fetch:fetch| ; 95 (95) ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|fetch:fetch ; fetch ; work ; +; |registerFile:RegFile| ; 680 (680) ; 992 (992) ; 0 ; 0 ; 0 ; 0 ; |top|utoss_riscv:core|registerFile:RegFile ; registerFile ; work ; ++-----------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------+--------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++--------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+-----------------------------------------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++--------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+-----------------------------------------+ +; memory_map:u_mem|altsyncram:M0_rtl_0|altsyncram_6lr1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 8 ; 512 ; 8 ; 4096 ; db/top.ram0_memory_map_ee718c45.hdl.mif ; +; memory_map:u_mem|altsyncram:M1_rtl_0|altsyncram_7lr1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 8 ; 512 ; 8 ; 4096 ; db/top.ram1_memory_map_ee718c45.hdl.mif ; +; memory_map:u_mem|altsyncram:M2_rtl_0|altsyncram_8lr1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 8 ; 512 ; 8 ; 4096 ; db/top.ram2_memory_map_ee718c45.hdl.mif ; +; memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 8 ; 512 ; 8 ; 4096 ; db/top.ram3_memory_map_ee718c45.hdl.mif ; ++--------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+-----------------------------------------+ + + +Encoding Type: One-Hot ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |top|utoss_riscv:core|ControlFSM:control_fsm|current_state ; ++--------------------------+--------------------------+--------------------------+-------------------------+---------------------+-------------------+--------------------------+---------------------+-----------------------+------------------------+---------------------+----------------------+------------------------+--------------------------+------------------------+----------------------+---------------------+--------------------------+ +; Name ; current_state.BRANCHCOMP ; current_state.JALR_STEP2 ; current_state.JALR_CALC ; current_state.AUIPC ; current_state.LUI ; current_state.BRANCHIFEQ ; current_state.MEMWB ; current_state.MEMREAD ; current_state.MEMWRITE ; current_state.ALUWB ; current_state.MEMADR ; current_state.EXECUTEI ; current_state.UNCONDJUMP ; current_state.EXECUTER ; current_state.DECODE ; current_state.FETCH ; current_state.FETCH_WAIT ; ++--------------------------+--------------------------+--------------------------+-------------------------+---------------------+-------------------+--------------------------+---------------------+-----------------------+------------------------+---------------------+----------------------+------------------------+--------------------------+------------------------+----------------------+---------------------+--------------------------+ +; current_state.FETCH ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; current_state.DECODE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; 0 ; +; current_state.EXECUTER ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; 0 ; +; current_state.UNCONDJUMP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; 0 ; +; current_state.EXECUTEI ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.MEMADR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.ALUWB ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.MEMWRITE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.MEMREAD ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.MEMWB ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.BRANCHIFEQ ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.LUI ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.AUIPC ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.JALR_CALC ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.JALR_STEP2 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.BRANCHCOMP ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; +; current_state.FETCH_WAIT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; ++--------------------------+--------------------------+--------------------------+-------------------------+---------------------+-------------------+--------------------------+---------------------+-----------------------+------------------------+---------------------+----------------------+------------------------+--------------------------+------------------------+----------------------+---------------------+--------------------------+ + + +Encoding Type: One-Hot ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |top|uart_bus_master:u_master|state ; ++----------------------+-----------------+------------------+--------------------+--------------------+-------------------+-----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+-----------------+----------------------+ +; Name ; state.STATE_REG ; state.STATE_SEND ; state.STATE_DO_RD1 ; state.STATE_DO_RD0 ; state.STATE_DO_WR ; state.STATE_CHK ; state.STATE_D3 ; state.STATE_D2 ; state.STATE_D1 ; state.STATE_D0 ; state.STATE_A3 ; state.STATE_A2 ; state.STATE_A1 ; state.STATE_A0 ; state.STATE_CMD ; state.STATE_WAIT_SOF ; ++----------------------+-----------------+------------------+--------------------+--------------------+-------------------+-----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+-----------------+----------------------+ +; state.STATE_WAIT_SOF ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; state.STATE_CMD ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; state.STATE_A0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; state.STATE_A1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; state.STATE_A2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_A3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_D0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_D1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_D2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_D3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_CHK ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_DO_WR ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_DO_RD0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_DO_RD1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_SEND ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; state.STATE_REG ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+-----------------+------------------+--------------------+--------------------+-------------------+-----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+-----------------+----------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------------+ +; State Machine - |top|uart:u_uart|uart_rx:uart_rx_inst|state ; ++-------------------+------------------+------------------+-------------------+------------------+ +; Name ; state.STATE_STOP ; state.STATE_DATA ; state.STATE_START ; state.STATE_IDLE ; ++-------------------+------------------+------------------+-------------------+------------------+ +; state.STATE_IDLE ; 0 ; 0 ; 0 ; 0 ; +; state.STATE_START ; 0 ; 0 ; 1 ; 1 ; +; state.STATE_DATA ; 0 ; 1 ; 0 ; 1 ; +; state.STATE_STOP ; 1 ; 0 ; 0 ; 1 ; ++-------------------+------------------+------------------+-------------------+------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; User-Specified and Inferred Latches ; ++-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------------+ +; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ; ++-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------------+ +; utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|alu_control[2] ; utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|Selector4 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|alu_control[3] ; utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|Selector4 ; yes ; +; utoss_riscv:core|ControlFSM:control_fsm|ALUSrcB[1] ; utoss_riscv:core|ControlFSM:control_fsm|WideOr13 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[4] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|ControlFSM:control_fsm|ALUSrcB[0] ; utoss_riscv:core|ControlFSM:control_fsm|WideOr13 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[2] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[3] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[0] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[1] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|ControlFSM:control_fsm|ALUSrcA[0] ; utoss_riscv:core|ControlFSM:control_fsm|WideOr13 ; yes ; +; utoss_riscv:core|ControlFSM:control_fsm|ALUSrcA[1] ; utoss_riscv:core|ControlFSM:control_fsm|WideOr13 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[31] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[30] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[29] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[28] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[27] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[26] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[25] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[24] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[23] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[22] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[21] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[20] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[19] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[18] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[17] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[16] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[15] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[14] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[13] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[12] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[11] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[10] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[9] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[8] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[7] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[6] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[5] ; utoss_riscv:core|Instruction_Decode:instruction_decode|WideOr3 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|alu_control[0] ; utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|Selector4 ; yes ; +; utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|alu_control[1] ; utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|Selector4 ; yes ; +; Number of user-specified and inferred latches = 40 ; ; ; ++-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------------+ +Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations. + + ++--------------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------------------------+----------------------------------------+ +; utoss_riscv:core|registerFile:RegFile|RFMem[0][0] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][1] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][2] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][3] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][4] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][5] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][6] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][7] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][8] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][9] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][10] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][11] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][12] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][13] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][14] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][15] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][16] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][17] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][18] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][19] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][20] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][21] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][22] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][23] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][24] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][25] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][26] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][27] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][28] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][29] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][30] ; Stuck at GND due to stuck port data_in ; +; utoss_riscv:core|registerFile:RegFile|RFMem[0][31] ; Stuck at GND due to stuck port data_in ; +; uart_bus_master:u_master|resp[0][0] ; Stuck at GND due to stuck port data_in ; +; uart_bus_master:u_master|resp[0][1] ; Stuck at VCC due to stuck port data_in ; +; uart_bus_master:u_master|resp[0][2] ; Stuck at GND due to stuck port data_in ; +; uart_bus_master:u_master|resp[1][2] ; Stuck at GND due to stuck port data_in ; +; uart_bus_master:u_master|resp[0][3] ; Stuck at VCC due to stuck port data_in ; +; uart_bus_master:u_master|resp[1][3] ; Stuck at GND due to stuck port data_in ; +; uart_bus_master:u_master|resp[0][4] ; Stuck at VCC due to stuck port data_in ; +; uart_bus_master:u_master|resp[1][4] ; Stuck at VCC due to stuck port data_in ; +; uart_bus_master:u_master|resp[0][5] ; Stuck at GND due to stuck port data_in ; +; uart_bus_master:u_master|resp[1][5] ; Stuck at GND due to stuck port data_in ; +; uart_bus_master:u_master|resp[0][6] ; Stuck at VCC due to stuck port data_in ; +; uart_bus_master:u_master|resp[1][6] ; Stuck at GND due to stuck port data_in ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[9] ; Stuck at VCC due to stuck port data_in ; +; uart_bus_master:u_master|resp[0][7] ; Stuck at GND due to stuck port data_in ; +; uart_bus_master:u_master|resp[1][7] ; Stuck at VCC due to stuck port data_in ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state~2 ; Lost fanout ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state~3 ; Lost fanout ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state~4 ; Lost fanout ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state~5 ; Lost fanout ; +; uart_bus_master:u_master|state~17 ; Lost fanout ; +; uart_bus_master:u_master|state~18 ; Lost fanout ; +; uart_bus_master:u_master|state~19 ; Lost fanout ; +; uart_bus_master:u_master|state~20 ; Lost fanout ; +; uart_bus_master:u_master|state~21 ; Lost fanout ; +; uart:u_uart|uart_rx:uart_rx_inst|state~9 ; Lost fanout ; +; uart:u_uart|uart_rx:uart_rx_inst|state~10 ; Lost fanout ; +; Total Number of Removed Registers = 58 ; ; ++---------------------------------------------------------+----------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 1551 ; +; Number of registers using Synchronous Clear ; 1303 ; +; Number of registers using Synchronous Load ; 13 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 1365 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------------+---------+ +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[1] ; 1 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[2] ; 1 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[3] ; 1 ; +; uart:u_uart|uart_rx:uart_rx_inst|rxd_q1_d ; 7 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[4] ; 1 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[5] ; 1 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[6] ; 1 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[7] ; 1 ; +; uart:u_uart|uart_tx:uart_tx_inst|data_reg[8] ; 1 ; +; Total number of inverted registers = 9 ; ; ++----------------------------------------------+---------+ + + ++-----------------------------------------------------------------------+ +; Registers Packed Into Inferred Megafunctions ; ++------------------------------------+---------------------------+------+ +; Register Name ; Megafunction ; Type ; ++------------------------------------+---------------------------+------+ +; memory_map:u_mem|mem_rdata[0..7] ; memory_map:u_mem|M0_rtl_0 ; RAM ; +; memory_map:u_mem|mem_rdata[8..15] ; memory_map:u_mem|M1_rtl_0 ; RAM ; +; memory_map:u_mem|mem_rdata[16..23] ; memory_map:u_mem|M2_rtl_0 ; RAM ; +; memory_map:u_mem|mem_rdata[24..31] ; memory_map:u_mem|M3_rtl_0 ; RAM ; ++------------------------------------+---------------------------+------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------+ +; 3:1 ; 17 bits ; 34 LEs ; 34 LEs ; 0 LEs ; Yes ; |top|utoss_riscv:core|data[27] ; +; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |top|uart:u_uart|uart_rx:uart_rx_inst|o_data[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |top|uart_bus_master:u_master|cmd[5] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|uart_bus_master:u_master|bus_addr[13] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|uart_bus_master:u_master|bus_write_data[26] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[16][15] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[8][18] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[24][4] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[4][14] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[20][26] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[12][24] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[28][8] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[2][2] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[18][1] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[10][5] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[26][8] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[6][1] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[22][16] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[14][16] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[30][22] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[1][17] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[17][1] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[9][4] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[25][4] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[5][9] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[21][28] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[13][26] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[29][3] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[3][31] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[19][20] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[11][27] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[27][1] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[7][2] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[23][9] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[15][4] ; +; 3:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|registerFile:RegFile|RFMem[31][7] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |top|utoss_riscv:core|data[8] ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |top|uart:u_uart|uart_tx:uart_tx_inst|bit_idx[3] ; +; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |top|uart_bus_master:u_master|resp_idx[0] ; +; 4:1 ; 24 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |top|uart_bus_master:u_master|resp[5][5] ; +; 5:1 ; 19 bits ; 57 LEs ; 38 LEs ; 19 LEs ; Yes ; |top|uart:u_uart|uart_tx:uart_tx_inst|timer[18] ; +; 10:1 ; 8 bits ; 48 LEs ; 32 LEs ; 16 LEs ; Yes ; |top|uart_bus_master:u_master|tx_data[7] ; +; 7:1 ; 7 bits ; 28 LEs ; 14 LEs ; 14 LEs ; Yes ; |top|utoss_riscv:core|data[2] ; +; 5:1 ; 30 bits ; 90 LEs ; 60 LEs ; 30 LEs ; Yes ; |top|utoss_riscv:core|fetch:fetch|pc_cur[18] ; +; 5:1 ; 6 bits ; 18 LEs ; 12 LEs ; 6 LEs ; Yes ; |top|uart_bus_master:u_master|resp[1][7] ; +; 33:1 ; 32 bits ; 704 LEs ; 640 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|dataA[18] ; +; 33:1 ; 32 bits ; 704 LEs ; 640 LEs ; 64 LEs ; Yes ; |top|utoss_riscv:core|dataB[6] ; +; 7:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |top|uart_bus_master:u_master|addr[1] ; +; 7:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |top|uart_bus_master:u_master|addr[11] ; +; 7:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |top|uart_bus_master:u_master|addr[20] ; +; 7:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |top|uart_bus_master:u_master|addr[24] ; +; 7:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |top|uart_bus_master:u_master|wdata[0] ; +; 7:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |top|uart_bus_master:u_master|wdata[8] ; +; 7:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |top|uart_bus_master:u_master|wdata[21] ; +; 7:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |top|uart_bus_master:u_master|wdata[28] ; +; 7:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |top|uart:u_uart|uart_rx:uart_rx_inst|bit_idx[3] ; +; 9:1 ; 15 bits ; 90 LEs ; 30 LEs ; 60 LEs ; Yes ; |top|uart:u_uart|uart_rx:uart_rx_inst|timer[12] ; +; 9:1 ; 4 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |top|uart:u_uart|uart_rx:uart_rx_inst|timer[3] ; +; 7:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |top|uart_bus_master:u_master|chk_calc[1] ; +; 261:1 ; 16 bits ; 2784 LEs ; 144 LEs ; 2640 LEs ; Yes ; |top|uart_bus_master:u_master|resp[3][0] ; +; 263:1 ; 2 bits ; 350 LEs ; 18 LEs ; 332 LEs ; Yes ; |top|uart_bus_master:u_master|resp_len[1] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |top|uart:u_uart|uart_tx:uart_tx_inst|data_reg[2] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |top|bus_write_data[17] ; +; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|Mux6 ; +; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|Mux39 ; +; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|ALU:alu|ShiftLeft0 ; +; 4:1 ; 49 bits ; 98 LEs ; 98 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|ALU:alu|ShiftRight1 ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|ALU:alu|ShiftRight0 ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|ALU:alu|ShiftRight1 ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|ALU:alu|ShiftLeft0 ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|ALU:alu|ShiftLeft0 ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|ALU:alu|ShiftLeft0 ; +; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; No ; |top|uart_bus_master:u_master|resp ; +; 3:1 ; 30 bits ; 60 LEs ; 60 LEs ; 0 LEs ; No ; |top|bus_addr[30] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |top|bus_write_data[8] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |top|bus_write_data[31] ; +; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|Selector11 ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|Instruction_Decode:instruction_decode|rs2[4] ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|Instruction_Decode:instruction_decode|rd[1] ; +; 3:1 ; 10 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |top|memory_map:u_mem|Selector22 ; +; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; No ; |top|utoss_riscv:core|Instruction_Decode:instruction_decode|rs1[4] ; +; 5:1 ; 4 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |top|bus_write_enable[0] ; +; 32:1 ; 32 bits ; 672 LEs ; 672 LEs ; 0 LEs ; No ; |top|uart_bus_master:u_master|Mux19 ; +; 8:1 ; 4 bits ; 20 LEs ; 8 LEs ; 12 LEs ; No ; |top|utoss_riscv:core|Instruction_Decode:instruction_decode|Selector9 ; +; 8:1 ; 2 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|ControlFSM:control_fsm|current_state ; +; 9:1 ; 2 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |top|utoss_riscv:core|ControlFSM:control_fsm|next_state ; +; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |top|uart:u_uart|uart_rx:uart_rx_inst|state ; +; 22:1 ; 8 bits ; 112 LEs ; 88 LEs ; 24 LEs ; No ; |top|utoss_riscv:core|ALU:alu|Mux8 ; +; 21:1 ; 5 bits ; 70 LEs ; 50 LEs ; 20 LEs ; No ; |top|utoss_riscv:core|ALU:alu|Mux24 ; +; 9:1 ; 2 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |top|uart:u_uart|uart_rx:uart_rx_inst|state ; +; 21:1 ; 3 bits ; 42 LEs ; 30 LEs ; 12 LEs ; No ; |top|utoss_riscv:core|ALU:alu|Mux18 ; +; 23:1 ; 2 bits ; 30 LEs ; 22 LEs ; 8 LEs ; No ; |top|utoss_riscv:core|ALU:alu|Mux21 ; +; 25:1 ; 3 bits ; 48 LEs ; 39 LEs ; 9 LEs ; No ; |top|utoss_riscv:core|ALU:alu|Mux2 ; +; 24:1 ; 2 bits ; 32 LEs ; 24 LEs ; 8 LEs ; No ; |top|utoss_riscv:core|ALU:alu|Mux6 ; +; 24:1 ; 3 bits ; 48 LEs ; 36 LEs ; 12 LEs ; No ; |top|utoss_riscv:core|ALU:alu|Mux29 ; +; 11:1 ; 2 bits ; 14 LEs ; 8 LEs ; 6 LEs ; No ; |top|uart_bus_master:u_master|state ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Source assignments for memory_map:u_mem|altsyncram:M0_rtl_0|altsyncram_6lr1:auto_generated ; ++---------------------------------+--------------------+------+------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Source assignments for memory_map:u_mem|altsyncram:M1_rtl_0|altsyncram_7lr1:auto_generated ; ++---------------------------------+--------------------+------+------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Source assignments for memory_map:u_mem|altsyncram:M2_rtl_0|altsyncram_8lr1:auto_generated ; ++---------------------------------+--------------------+------+------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Source assignments for memory_map:u_mem|altsyncram:M3_rtl_0|altsyncram_9lr1:auto_generated ; ++---------------------------------+--------------------+------+------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------+ + + ++----------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart:u_uart ; ++----------------+----------+------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+----------+------------------------------+ +; DATA_WIDTH ; 8 ; Signed Integer ; +; CLK_HZ ; 50000000 ; Signed Integer ; +; BAUD ; 115200 ; Signed Integer ; ++----------------+----------+------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart:u_uart|uart_tx:uart_tx_inst ; ++----------------+-------+------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------+ +; DATA_WIDTH ; 8 ; Signed Integer ; +; DIV ; 434 ; Signed Integer ; ++----------------+-------+------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart:u_uart|uart_rx:uart_rx_inst ; ++----------------+-------+------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------+ +; DATA_WIDTH ; 8 ; Signed Integer ; +; DIV ; 434 ; Signed Integer ; ++----------------+-------+------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: memory_map:u_mem ; ++----------------+-------+--------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------+ +; SIZE ; 512 ; Signed Integer ; ++----------------+-------+--------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: utoss_riscv:core|ControlFSM:control_fsm ; ++----------------+-------+-------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------+ +; FETCH ; 00000 ; Unsigned Binary ; +; DECODE ; 00001 ; Unsigned Binary ; +; EXECUTER ; 00010 ; Unsigned Binary ; +; UNCONDJUMP ; 00011 ; Unsigned Binary ; +; EXECUTEI ; 00100 ; Unsigned Binary ; +; MEMADR ; 00101 ; Unsigned Binary ; +; ALUWB ; 00110 ; Unsigned Binary ; +; MEMWRITE ; 00111 ; Unsigned Binary ; +; MEMREAD ; 01000 ; Unsigned Binary ; +; MEMWB ; 01001 ; Unsigned Binary ; +; BRANCHIFEQ ; 01010 ; Unsigned Binary ; +; LUI ; 01011 ; Unsigned Binary ; +; AUIPC ; 01100 ; Unsigned Binary ; +; JALR_CALC ; 01101 ; Unsigned Binary ; +; JALR_STEP2 ; 01110 ; Unsigned Binary ; +; BRANCHCOMP ; 01111 ; Unsigned Binary ; +; FETCH_WAIT ; 10000 ; Unsigned Binary ; ++----------------+-------+-------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: memory_map:u_mem|altsyncram:M0_rtl_0 ; ++------------------------------------+-----------------------------------------+----------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------------------------------+----------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Untyped ; +; WIDTHAD_A ; 9 ; Untyped ; +; NUMWORDS_A ; 512 ; Untyped ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Untyped ; +; WIDTHAD_B ; 9 ; Untyped ; +; NUMWORDS_B ; 512 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK0 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; db/top.ram0_memory_map_ee718c45.hdl.mif ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone V ; Untyped ; +; CBXI_PARAMETER ; altsyncram_6lr1 ; Untyped ; ++------------------------------------+-----------------------------------------+----------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: memory_map:u_mem|altsyncram:M1_rtl_0 ; ++------------------------------------+-----------------------------------------+----------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------------------------------+----------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Untyped ; +; WIDTHAD_A ; 9 ; Untyped ; +; NUMWORDS_A ; 512 ; Untyped ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Untyped ; +; WIDTHAD_B ; 9 ; Untyped ; +; NUMWORDS_B ; 512 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK0 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; db/top.ram1_memory_map_ee718c45.hdl.mif ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone V ; Untyped ; +; CBXI_PARAMETER ; altsyncram_7lr1 ; Untyped ; ++------------------------------------+-----------------------------------------+----------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: memory_map:u_mem|altsyncram:M2_rtl_0 ; ++------------------------------------+-----------------------------------------+----------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------------------------------+----------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Untyped ; +; WIDTHAD_A ; 9 ; Untyped ; +; NUMWORDS_A ; 512 ; Untyped ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Untyped ; +; WIDTHAD_B ; 9 ; Untyped ; +; NUMWORDS_B ; 512 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK0 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; db/top.ram2_memory_map_ee718c45.hdl.mif ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone V ; Untyped ; +; CBXI_PARAMETER ; altsyncram_8lr1 ; Untyped ; ++------------------------------------+-----------------------------------------+----------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: memory_map:u_mem|altsyncram:M3_rtl_0 ; ++------------------------------------+-----------------------------------------+----------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------------------------------+----------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Untyped ; +; WIDTHAD_A ; 9 ; Untyped ; +; NUMWORDS_A ; 512 ; Untyped ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Untyped ; +; WIDTHAD_B ; 9 ; Untyped ; +; NUMWORDS_B ; 512 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK0 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; db/top.ram3_memory_map_ee718c45.hdl.mif ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone V ; Untyped ; +; CBXI_PARAMETER ; altsyncram_9lr1 ; Untyped ; ++------------------------------------+-----------------------------------------+----------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------+ +; altsyncram Parameter Settings by Entity Instance ; ++-------------------------------------------+--------------------------------------+ +; Name ; Value ; ++-------------------------------------------+--------------------------------------+ +; Number of entity instances ; 4 ; +; Entity Instance ; memory_map:u_mem|altsyncram:M0_rtl_0 ; +; -- OPERATION_MODE ; DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 512 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 512 ; +; -- ADDRESS_REG_B ; CLOCK0 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; +; Entity Instance ; memory_map:u_mem|altsyncram:M1_rtl_0 ; +; -- OPERATION_MODE ; DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 512 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 512 ; +; -- ADDRESS_REG_B ; CLOCK0 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; +; Entity Instance ; memory_map:u_mem|altsyncram:M2_rtl_0 ; +; -- OPERATION_MODE ; DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 512 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 512 ; +; -- ADDRESS_REG_B ; CLOCK0 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; +; Entity Instance ; memory_map:u_mem|altsyncram:M3_rtl_0 ; +; -- OPERATION_MODE ; DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 512 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 512 ; +; -- ADDRESS_REG_B ; CLOCK0 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; ++-------------------------------------------+--------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "utoss_riscv:core|Instruction_Decode:instruction_decode" ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ +; funct7 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "utoss_riscv:core|ControlFSM:control_fsm" ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ +; Branch ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; FSMState ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "uart:u_uart" ; ++--------------------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------+--------+----------+-------------------------------------------------------------------------------------+ +; o_tx_busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; o_rx_busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; o_rx_overrun_error ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; o_rx_frame_error ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------------------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; arriav_ff ; 1551 ; +; ENA ; 146 ; +; ENA SCLR ; 1209 ; +; ENA SCLR SLD ; 10 ; +; SCLR ; 84 ; +; SLD ; 3 ; +; plain ; 99 ; +; arriav_lcell_comb ; 2443 ; +; arith ; 133 ; +; 1 data inputs ; 69 ; +; 2 data inputs ; 32 ; +; 4 data inputs ; 31 ; +; 5 data inputs ; 1 ; +; extend ; 16 ; +; 7 data inputs ; 16 ; +; normal ; 2294 ; +; 1 data inputs ; 5 ; +; 2 data inputs ; 138 ; +; 3 data inputs ; 231 ; +; 4 data inputs ; 209 ; +; 5 data inputs ; 254 ; +; 6 data inputs ; 1457 ; +; boundary_port ; 17 ; +; stratixv_ram_block ; 32 ; +; ; ; +; Max LUT depth ; 12.00 ; +; Average LUT depth ; 6.22 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:06 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition + Info: Processing started: Mon Jan 12 21:52:59 2026 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 16 of the 16 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file src/logger.sv + Info (12023): Found entity 1: Logger File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/src/Logger.sv Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv + Info (12023): Found entity 1: top File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv Line: 1 +Warning (10229): Verilog HDL Expression warning at memory_map.sv(114): truncated literal to match 5 bits File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv Line: 114 +Info (12021): Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv + Info (12023): Found entity 1: memory_map File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv Line: 71 +Info (12021): Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/alu_aludecoder/aludecoder.sv + Info (12023): Found entity 1: ALUdecoder File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/alu_aludecoder/alu.v + Info (12023): Found entity 1: ALU File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALU.v Line: 1 +Info (12021): Found 0 design units, including 0 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/registerfile.v +Info (12021): Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/memoryloader.sv + Info (12023): Found entity 1: MemoryLoader File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/MemoryLoader.sv Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/instruction_decode/instruction_decode.sv + Info (12023): Found entity 1: Instruction_Decode File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 4 +Info (12021): Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv + Info (12023): Found entity 1: utoss_riscv File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/fetch.sv + Info (12023): Found entity 1: fetch File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/fetch.sv Line: 10 +Info (12021): Found 1 design units, including 1 entities, in source file /risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/controlfsm.sv + Info (12023): Found entity 1: ControlFSM File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv Line: 7 +Info (12021): Found 1 design units, including 1 entities, in source file uart_rx.sv + Info (12023): Found entity 1: uart_rx File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file uart_tx.sv + Info (12023): Found entity 1: uart_tx File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_tx.sv Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file uart.sv + Info (12023): Found entity 1: uart File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart.sv Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file inst_mem.v + Info (12023): Found entity 1: inst_mem File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/inst_mem.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file uart_bus_master.sv + Info (12023): Found entity 1: uart_bus_master File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_bus_master.sv Line: 9 +Info (12021): Found 1 design units, including 1 entities, in source file registerfile.sv + Info (12023): Found entity 1: registerFile File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/RegisterFile.sv Line: 1 +Info (12127): Elaborating entity "top" for the top level hierarchy +Info (12128): Elaborating entity "uart" for hierarchy "uart:u_uart" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv Line: 46 +Info (12128): Elaborating entity "uart_tx" for hierarchy "uart:u_uart|uart_tx:uart_tx_inst" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart.sv Line: 48 +Warning (10230): Verilog HDL assignment warning at uart_tx.sv(48): truncated value with size 32 to match size of target (19) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_tx.sv Line: 48 +Warning (10230): Verilog HDL assignment warning at uart_tx.sv(64): truncated value with size 32 to match size of target (19) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_tx.sv Line: 64 +Info (12128): Elaborating entity "uart_rx" for hierarchy "uart:u_uart|uart_rx:uart_rx_inst" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart.sv Line: 64 +Warning (10230): Verilog HDL assignment warning at uart_rx.sv(78): truncated value with size 32 to match size of target (19) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv Line: 78 +Warning (10230): Verilog HDL assignment warning at uart_rx.sv(91): truncated value with size 32 to match size of target (19) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv Line: 91 +Warning (10230): Verilog HDL assignment warning at uart_rx.sv(109): truncated value with size 32 to match size of target (19) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv Line: 109 +Warning (10230): Verilog HDL assignment warning at uart_rx.sv(112): truncated value with size 32 to match size of target (19) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_rx.sv Line: 112 +Info (12128): Elaborating entity "uart_bus_master" for hierarchy "uart_bus_master:u_master" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv Line: 74 +Info (10264): Verilog HDL Case Statement information at uart_bus_master.sv(164): all case item expressions in this case statement are onehot File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/uart_bus_master.sv Line: 164 +Info (12128): Elaborating entity "memory_map" for hierarchy "memory_map:u_mem" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv Line: 105 +Warning (10850): Verilog HDL warning at memory_map.sv(92): number of words (20) in memory file does not match the number of elements in the address range [0:511] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv Line: 92 +Warning (10850): Verilog HDL warning at memory_map.sv(93): number of words (20) in memory file does not match the number of elements in the address range [0:511] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv Line: 93 +Warning (10850): Verilog HDL warning at memory_map.sv(94): number of words (20) in memory file does not match the number of elements in the address range [0:511] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv Line: 94 +Warning (10850): Verilog HDL warning at memory_map.sv(95): number of words (20) in memory file does not match the number of elements in the address range [0:511] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv Line: 95 +Warning (10762): Verilog HDL Case Statement warning at memory_map.sv(110): can't check case statement for completeness because the case expression has too many possible states File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv Line: 110 +Warning (10762): Verilog HDL Case Statement warning at memory_map.sv(123): can't check case statement for completeness because the case expression has too many possible states File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/memory_map.sv Line: 123 +Info (12128): Elaborating entity "utoss_riscv" for hierarchy "utoss_riscv:core" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv Line: 118 +Info (12128): Elaborating entity "ControlFSM" for hierarchy "utoss_riscv:core|ControlFSM:control_fsm" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 78 +Warning (10270): Verilog HDL Case Statement warning at ControlFSM.sv(244): incomplete case statement has no default case item File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv Line: 244 +Warning (10240): Verilog HDL Always Construct warning at ControlFSM.sv(146): inferring latch(es) for variable "ALUSrcA", which holds its previous value in one or more paths through the always construct File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv Line: 146 +Warning (10240): Verilog HDL Always Construct warning at ControlFSM.sv(146): inferring latch(es) for variable "ALUSrcB", which holds its previous value in one or more paths through the always construct File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv Line: 146 +Info (10041): Inferred latch for "ALUSrcB[0]" at ControlFSM.sv(146) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv Line: 146 +Info (10041): Inferred latch for "ALUSrcB[1]" at ControlFSM.sv(146) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv Line: 146 +Info (10041): Inferred latch for "ALUSrcA[0]" at ControlFSM.sv(146) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv Line: 146 +Info (10041): Inferred latch for "ALUSrcA[1]" at ControlFSM.sv(146) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv Line: 146 +Info (12128): Elaborating entity "fetch" for hierarchy "utoss_riscv:core|fetch:fetch" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 92 +Info (12128): Elaborating entity "MemoryLoader" for hierarchy "utoss_riscv:core|MemoryLoader:MemLoad" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 115 +Info (12128): Elaborating entity "Instruction_Decode" for hierarchy "utoss_riscv:core|Instruction_Decode:instruction_decode" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 131 +Warning (10270): Verilog HDL Case Statement warning at Instruction_Decode.sv(127): incomplete case statement has no default case item File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Warning (10240): Verilog HDL Always Construct warning at Instruction_Decode.sv(127): inferring latch(es) for variable "imm_ext", which holds its previous value in one or more paths through the always construct File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[0]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[1]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[2]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[3]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[4]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[5]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[6]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[7]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[8]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[9]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[10]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[11]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[12]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[13]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[14]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[15]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[16]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[17]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[18]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[19]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[20]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[21]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[22]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[23]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[24]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[25]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[26]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[27]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[28]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[29]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[30]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (10041): Inferred latch for "imm_ext[31]" at Instruction_Decode.sv(127) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 +Info (12128): Elaborating entity "ALUdecoder" for hierarchy "utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 147 +Warning (10240): Verilog HDL Always Construct warning at ALUdecoder.sv(10): inferring latch(es) for variable "alu_control", which holds its previous value in one or more paths through the always construct File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv Line: 10 +Info (10041): Inferred latch for "alu_control[0]" at ALUdecoder.sv(10) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv Line: 10 +Info (10041): Inferred latch for "alu_control[1]" at ALUdecoder.sv(10) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv Line: 10 +Info (10041): Inferred latch for "alu_control[2]" at ALUdecoder.sv(10) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv Line: 10 +Info (10041): Inferred latch for "alu_control[3]" at ALUdecoder.sv(10) File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv Line: 10 +Info (12128): Elaborating entity "registerFile" for hierarchy "utoss_riscv:core|registerFile:RegFile" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 144 +Info (12128): Elaborating entity "ALU" for hierarchy "utoss_riscv:core|ALU:alu" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 152 +Info (19000): Inferred 4 megafunctions from design logic + Info (276029): Inferred altsyncram megafunction from the following design logic: "memory_map:u_mem|M0_rtl_0" + Info (286033): Parameter OPERATION_MODE set to DUAL_PORT + Info (286033): Parameter WIDTH_A set to 8 + Info (286033): Parameter WIDTHAD_A set to 9 + Info (286033): Parameter NUMWORDS_A set to 512 + Info (286033): Parameter WIDTH_B set to 8 + Info (286033): Parameter WIDTHAD_B set to 9 + Info (286033): Parameter NUMWORDS_B set to 512 + Info (286033): Parameter ADDRESS_ACLR_A set to NONE + Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED + Info (286033): Parameter ADDRESS_ACLR_B set to NONE + Info (286033): Parameter OUTDATA_ACLR_B set to NONE + Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 + Info (286033): Parameter INDATA_ACLR_A set to NONE + Info (286033): Parameter WRCONTROL_ACLR_A set to NONE + Info (286033): Parameter INIT_FILE set to db/top.ram0_memory_map_ee718c45.hdl.mif + Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA + Info (276029): Inferred altsyncram megafunction from the following design logic: "memory_map:u_mem|M1_rtl_0" + Info (286033): Parameter OPERATION_MODE set to DUAL_PORT + Info (286033): Parameter WIDTH_A set to 8 + Info (286033): Parameter WIDTHAD_A set to 9 + Info (286033): Parameter NUMWORDS_A set to 512 + Info (286033): Parameter WIDTH_B set to 8 + Info (286033): Parameter WIDTHAD_B set to 9 + Info (286033): Parameter NUMWORDS_B set to 512 + Info (286033): Parameter ADDRESS_ACLR_A set to NONE + Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED + Info (286033): Parameter ADDRESS_ACLR_B set to NONE + Info (286033): Parameter OUTDATA_ACLR_B set to NONE + Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 + Info (286033): Parameter INDATA_ACLR_A set to NONE + Info (286033): Parameter WRCONTROL_ACLR_A set to NONE + Info (286033): Parameter INIT_FILE set to db/top.ram1_memory_map_ee718c45.hdl.mif + Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA + Info (276029): Inferred altsyncram megafunction from the following design logic: "memory_map:u_mem|M2_rtl_0" + Info (286033): Parameter OPERATION_MODE set to DUAL_PORT + Info (286033): Parameter WIDTH_A set to 8 + Info (286033): Parameter WIDTHAD_A set to 9 + Info (286033): Parameter NUMWORDS_A set to 512 + Info (286033): Parameter WIDTH_B set to 8 + Info (286033): Parameter WIDTHAD_B set to 9 + Info (286033): Parameter NUMWORDS_B set to 512 + Info (286033): Parameter ADDRESS_ACLR_A set to NONE + Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED + Info (286033): Parameter ADDRESS_ACLR_B set to NONE + Info (286033): Parameter OUTDATA_ACLR_B set to NONE + Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 + Info (286033): Parameter INDATA_ACLR_A set to NONE + Info (286033): Parameter WRCONTROL_ACLR_A set to NONE + Info (286033): Parameter INIT_FILE set to db/top.ram2_memory_map_ee718c45.hdl.mif + Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA + Info (276029): Inferred altsyncram megafunction from the following design logic: "memory_map:u_mem|M3_rtl_0" + Info (286033): Parameter OPERATION_MODE set to DUAL_PORT + Info (286033): Parameter WIDTH_A set to 8 + Info (286033): Parameter WIDTHAD_A set to 9 + Info (286033): Parameter NUMWORDS_A set to 512 + Info (286033): Parameter WIDTH_B set to 8 + Info (286033): Parameter WIDTHAD_B set to 9 + Info (286033): Parameter NUMWORDS_B set to 512 + Info (286033): Parameter ADDRESS_ACLR_A set to NONE + Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED + Info (286033): Parameter ADDRESS_ACLR_B set to NONE + Info (286033): Parameter OUTDATA_ACLR_B set to NONE + Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 + Info (286033): Parameter INDATA_ACLR_A set to NONE + Info (286033): Parameter WRCONTROL_ACLR_A set to NONE + Info (286033): Parameter INIT_FILE set to db/top.ram3_memory_map_ee718c45.hdl.mif + Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA +Info (12130): Elaborated megafunction instantiation "memory_map:u_mem|altsyncram:M0_rtl_0" +Info (12133): Instantiated megafunction "memory_map:u_mem|altsyncram:M0_rtl_0" with the following parameter: + Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" + Info (12134): Parameter "WIDTH_A" = "8" + Info (12134): Parameter "WIDTHAD_A" = "9" + Info (12134): Parameter "NUMWORDS_A" = "512" + Info (12134): Parameter "WIDTH_B" = "8" + Info (12134): Parameter "WIDTHAD_B" = "9" + Info (12134): Parameter "NUMWORDS_B" = "512" + Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" + Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" + Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" + Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" + Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" + Info (12134): Parameter "INDATA_ACLR_A" = "NONE" + Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" + Info (12134): Parameter "INIT_FILE" = "db/top.ram0_memory_map_ee718c45.hdl.mif" + Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_6lr1.tdf + Info (12023): Found entity 1: altsyncram_6lr1 File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_6lr1.tdf Line: 28 +Info (12130): Elaborated megafunction instantiation "memory_map:u_mem|altsyncram:M1_rtl_0" +Info (12133): Instantiated megafunction "memory_map:u_mem|altsyncram:M1_rtl_0" with the following parameter: + Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" + Info (12134): Parameter "WIDTH_A" = "8" + Info (12134): Parameter "WIDTHAD_A" = "9" + Info (12134): Parameter "NUMWORDS_A" = "512" + Info (12134): Parameter "WIDTH_B" = "8" + Info (12134): Parameter "WIDTHAD_B" = "9" + Info (12134): Parameter "NUMWORDS_B" = "512" + Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" + Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" + Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" + Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" + Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" + Info (12134): Parameter "INDATA_ACLR_A" = "NONE" + Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" + Info (12134): Parameter "INIT_FILE" = "db/top.ram1_memory_map_ee718c45.hdl.mif" + Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_7lr1.tdf + Info (12023): Found entity 1: altsyncram_7lr1 File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_7lr1.tdf Line: 28 +Info (12130): Elaborated megafunction instantiation "memory_map:u_mem|altsyncram:M2_rtl_0" +Info (12133): Instantiated megafunction "memory_map:u_mem|altsyncram:M2_rtl_0" with the following parameter: + Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" + Info (12134): Parameter "WIDTH_A" = "8" + Info (12134): Parameter "WIDTHAD_A" = "9" + Info (12134): Parameter "NUMWORDS_A" = "512" + Info (12134): Parameter "WIDTH_B" = "8" + Info (12134): Parameter "WIDTHAD_B" = "9" + Info (12134): Parameter "NUMWORDS_B" = "512" + Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" + Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" + Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" + Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" + Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" + Info (12134): Parameter "INDATA_ACLR_A" = "NONE" + Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" + Info (12134): Parameter "INIT_FILE" = "db/top.ram2_memory_map_ee718c45.hdl.mif" + Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8lr1.tdf + Info (12023): Found entity 1: altsyncram_8lr1 File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_8lr1.tdf Line: 28 +Info (12130): Elaborated megafunction instantiation "memory_map:u_mem|altsyncram:M3_rtl_0" +Info (12133): Instantiated megafunction "memory_map:u_mem|altsyncram:M3_rtl_0" with the following parameter: + Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" + Info (12134): Parameter "WIDTH_A" = "8" + Info (12134): Parameter "WIDTHAD_A" = "9" + Info (12134): Parameter "NUMWORDS_A" = "512" + Info (12134): Parameter "WIDTH_B" = "8" + Info (12134): Parameter "WIDTHAD_B" = "9" + Info (12134): Parameter "NUMWORDS_B" = "512" + Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" + Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" + Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" + Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" + Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" + Info (12134): Parameter "INDATA_ACLR_A" = "NONE" + Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" + Info (12134): Parameter "INIT_FILE" = "db/top.ram3_memory_map_ee718c45.hdl.mif" + Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_9lr1.tdf + Info (12023): Found entity 1: altsyncram_9lr1 File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/db/altsyncram_9lr1.tdf Line: 28 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|alu_control[2] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv Line: 10 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|alu_control[3] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv Line: 10 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[12] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[4] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[2] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[2] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[2] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[3] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[2] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[0] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[1] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[2] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[30] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[29] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[28] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[27] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[26] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[25] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[24] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[23] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[22] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[21] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[20] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[19] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[18] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[17] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[16] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[15] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[14] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[13] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[12] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[11] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[10] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[9] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[8] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[7] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[6] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[5] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/Instruction_Decode/Instruction_Decode.sv Line: 127 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|alu_control[0] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv Line: 10 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Warning (13012): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec|alu_control[1] has unsafe behavior File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ALU_ALUdecoder/ALUdecoder.sv Line: 10 + Warning (13013): Ports D and ENA on the latch are fed by the same signal utoss_riscv:core|instruction[0] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/utoss_riscv.sv Line: 101 +Info (286030): Timing-Driven Synthesis is running +Info (17049): 11 registers lost all their fanouts during netlist optimizations. +Info (144001): Generated suppressed messages file E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.map.smsg +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 3 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "KEY[1]" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv Line: 3 + Warning (15610): No output dependent on input pin "KEY[2]" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv Line: 3 + Warning (15610): No output dependent on input pin "KEY[3]" File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/top.sv Line: 3 +Info (21057): Implemented 3736 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 6 input pins + Info (21059): Implemented 11 output pins + Info (21061): Implemented 3687 logic cells + Info (21064): Implemented 32 RAM segments +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 94 warnings + Info: Peak virtual memory: 4949 megabytes + Info: Processing ended: Mon Jan 12 21:53:13 2026 + Info: Elapsed time: 00:00:14 + Info: Total CPU time (on all processors): 00:00:23 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/quartus workspace/output_files/top.map.smsg. + + diff --git a/quartus workspace/output_files/top.map.smsg b/quartus workspace/output_files/top.map.smsg new file mode 100644 index 0000000..9692fa6 --- /dev/null +++ b/quartus workspace/output_files/top.map.smsg @@ -0,0 +1 @@ +Info (10281): Verilog HDL Declaration information at ControlFSM.sv(21): object "MemWrite" differs only in case from object "MEMWRITE" in the same scope File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/src/ControlFSM.sv Line: 21 diff --git a/quartus workspace/output_files/top.map.summary b/quartus workspace/output_files/top.map.summary new file mode 100644 index 0000000..ac821cd --- /dev/null +++ b/quartus workspace/output_files/top.map.summary @@ -0,0 +1,17 @@ +Analysis & Synthesis Status : Successful - Mon Jan 12 21:53:13 2026 +Quartus Prime Version : 22.1std.2 Build 922 07/20/2023 SC Lite Edition +Revision Name : top +Top-level Entity Name : top +Family : Cyclone V +Logic utilization (in ALMs) : N/A +Total registers : 1551 +Total pins : 17 +Total virtual pins : 0 +Total block memory bits : 16,384 +Total DSP Blocks : 0 +Total HSSI RX PCSs : 0 +Total HSSI PMA RX Deserializers : 0 +Total HSSI TX PCSs : 0 +Total HSSI PMA TX Serializers : 0 +Total PLLs : 0 +Total DLLs : 0 diff --git a/quartus workspace/output_files/top.pin b/quartus workspace/output_files/top.pin new file mode 100644 index 0000000..3ec2be6 --- /dev/null +++ b/quartus workspace/output_files/top.pin @@ -0,0 +1,977 @@ + -- Copyright (C) 2023 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 3A: 2.5V + -- Bank 3B: 2.5V + -- Bank 4A: 2.5V + -- Bank 5A: 2.5V + -- Bank 5B: 2.5V + -- Bank 6B: 2.5V + -- Bank 6A: 2.5V + -- Bank 7A: 2.5V + -- Bank 7B: 2.5V + -- Bank 7C: 2.5V + -- Bank 7D: 2.5V + -- Bank 8A: 2.5V + -- Bank 9A: Dedicated configuration pins only, no VCCIO required. + -- RREF : External reference resistor for the quad, MUST be connected to + -- GND via a 2k Ohm resistor. + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin + -- must not be connected. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition +CHIP "top" ASSIGNED TO AN: 5CSEMA5F31C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A : +VCCIO8A : A7 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A : +GND : A12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C : +GND : A17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A : +GND : A26 : : : : 7A : +GND : A27 : gnd : : : : +HPS_TRST : A28 : : : : 7A : +HPS_TMS : A29 : : : : 7A : +GND : AA1 : gnd : : : : +GND : AA2 : gnd : : : : +GND : AA3 : gnd : : : : +GND : AA4 : gnd : : : : +VCC : AA5 : power : : 1.1V : : +GND : AA6 : gnd : : : : +DNU : AA7 : : : : : +VCCA_FPLL : AA8 : power : : 2.5V : : +GND : AA9 : gnd : : : : +VCCPD3A : AA10 : power : : 2.5V : 3A : +GND : AA11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B : +KEY[0] : AA14 : input : 2.5 V : : 3B : Y +KEY[1] : AA15 : input : 2.5 V : : 3B : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A : +VCCIO4A : AA17 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A : +GND : AA22 : gnd : : : : +VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B : +VCCIO5B : AA27 : power : : 2.5V : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 5B : +VREFB5BN0 : AA29 : power : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B : +GND : AB1 : gnd : : : : +GND : AB2 : gnd : : : : +DNU : AB3 : : : : : +DNU : AB4 : : : : : +GND : AB5 : gnd : : : : +VCCA_FPLL : AB6 : power : : 2.5V : : +GND : AB7 : gnd : : : : +nCSO, DATA4 : AB8 : : : : 3A : +TDO : AB9 : output : : : 3A : +VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : : +VCC_AUX : AB11 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B : +VCCIO3B : AB14 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B : +VCC_AUX : AB16 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A : +VCCPD3B4A : AB18 : power : : 2.5V : 3B, 4A : +GND : AB19 : gnd : : : : +VCCPD3B4A : AB20 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5A : +VCCIO5A : AB24 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 5B : +GND : AB29 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B : +GND : AC1 : gnd : : : : +GND : AC2 : gnd : : : : +GND : AC3 : gnd : : : : +GND : AC4 : gnd : : : : +TCK : AC5 : input : : : 3A : +GND : AC6 : gnd : : : : +AS_DATA3, DATA3 : AC7 : : : : 3A : +GND : AC8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3A : +VCCPD3A : AC10 : power : : 2.5V : 3A : +VCCIO3A : AC11 : power : : 2.5V : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3A : +VCCPD3B4A : AC13 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B : +VCCPD3B4A : AC15 : power : : 2.5V : 3B, 4A : +GND : AC16 : gnd : : : : +VCCPD3B4A : AC17 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A : +VCCPD3B4A : AC19 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A : +VCCIO4A : AC21 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A : +VREFB5AN0 : AC24 : power : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5A : +GND : AC26 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC28 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC29 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC30 : : : : 5B : +GND : AD1 : gnd : : : : +GND : AD2 : gnd : : : : +DNU : AD3 : : : : : +DNU : AD4 : : : : : +GND : AD5 : gnd : : : : +VREFB3AN0 : AD6 : power : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A : +VCCIO3A : AD8 : power : : 2.5V : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3A : +VCCIO3B : AD13 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B : +DNU : AD15 : : : : : +VCCPD3B4A : AD16 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A : +VCCIO4A : AD18 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A : +VCC_AUX : AD22 : power : : 2.5V : : +GND : AD23 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5A : +VCCIO5A : AD28 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD29 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD30 : : : : 5B : +GND : AE1 : gnd : : : : +GND : AE2 : gnd : : : : +GND : AE3 : gnd : : : : +GND : AE4 : gnd : : : : +AS_DATA1, DATA1 : AE5 : : : : 3A : +AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A : +AS_DATA2, DATA2 : AE8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A : +GND : AE10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B : +VCCIO3B : AE15 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A : +GND : AE20 : gnd : : : : +VCCPD3B4A : AE21 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A : +VCCIO4A : AE25 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE29 : : : : 5B : +VCCIO5B : AE30 : power : : 2.5V : 5B : +GND : AF1 : gnd : : : : +GND : AF2 : gnd : : : : +GND : AF3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A : +VCCIO3A : AF7 : power : : 2.5V : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B : +GND : AF12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B : +CLOCK_50 : AF14 : input : 2.5 V : : 3B : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A : +GND : AF17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A : +VCCIO4A : AF22 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A : +GND : AF27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF28 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF29 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF30 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A : +VCCIO3A : AG4 : power : : 2.5V : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A : +GND : AG9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B : +GND : AG14 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A : +VCCIO4A : AG19 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A : +GND : AG24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG27 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG28 : : : : 5A : +VCCIO5A : AG29 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG30 : : : : 5A : +GND : AH1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A : +GND : AH6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B : +GND : AH11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B : +VCCIO4A : AH16 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A : +GND : AH21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A : +VCCIO4A : AH26 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH28 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH29 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH30 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A : +GND : AJ3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B : +VCCIO3B : AJ8 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B : +VCCIO3B : AJ13 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B : +VREFB3BN0 : AJ15 : power : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A : +GND : AJ18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A : +VCCIO4A : AJ23 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A : +GND : AJ28 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AJ29 : : : : 5A : +GND : AJ30 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B : +GND : AK5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B : +VCCIO3B : AK10 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B : +GND : AK15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A : +VREFB4AN0 : AK17 : power : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A : +VCCIO4A : AK20 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A : +GND : AK25 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A : +VCCIO8A : B4 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A : +GND : B9 : gnd : : : : +VREFB8AN0 : B10 : power : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A : +GND : B14 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B : +GND : B19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A : +GND : B24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A : +HPS_TDI : B27 : : : : 7A : +HPS_TDO : B28 : : : : 7A : +GND : B29 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A : +GND : C1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A : +GND : C6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A : +VCCIO8A : C11 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D : +GND : C16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B : +GND : C21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A : +GND : C26 : gnd : : : : +HPS_nRST : C27 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A : +GND : D3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A : +VCCIO8A : D8 : power : : 2.5V : 8A : +UART_RX : D9 : output : 2.5 V : : 8A : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A : +GND : D13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C : +VCCIO7C_HPS : D18 : power : : 2.5V : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A : +GND : D23 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A : +HPS_CLK1 : D25 : : : : 7A : +GND : D26 : : : : 7A : +HPS_RZQ_0 : D27 : : : : 6A : +VCCIO6A_HPS : D28 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A : +VCCIO8A : E5 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A : +UART_TX : E9 : input : 2.5 V : : 8A : Y +GND : E10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D : +VCCIO7D_HPS : E15 : power : : 2.5V : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B : +VCCIO7B_HPS : E20 : power : : 2.5V : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B : +VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A : +GND : E25 : gnd : : : : +DNU : E26 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A : +GND : E30 : gnd : : : : +DNU : F1 : : : : : +GND : F2 : gnd : : : : +CONF_DONE : F3 : : : : 9A : +nSTATUS : F4 : : : : 9A : +GND : F5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A : +GND : F7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A : +VCCIO8A : F12 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D : +GND : F17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B : +VCCIO7A_HPS : F22 : power : : 2.5V : 7A : +HPS_nPOR : F23 : : : : 7A : +HPS_PORSEL : F24 : : : : 7A : +HPS_CLK2 : F25 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A : +GND : F27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A : +GND : G1 : : : : : +DNU : G2 : : : : : +GND : G3 : gnd : : : : +GND : G4 : gnd : : : : +nCE : G5 : : : : 9A : +MSEL2 : G6 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A : +VCCIO8A : G9 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A : +VCCIO8A : G14 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C : +VCCIO7B_HPS : G19 : power : : 2.5V : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A : +VCCRSTCLK_HPS : G23 : : : : 7A : +GND : G24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A : +VCCIO6A_HPS : G29 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A : +GND : H1 : gnd : : : : +GND : H2 : gnd : : : : +DNU : H3 : : : : : +DNU : H4 : : : : : +GND : H5 : gnd : : : : +VCCIO8A : H6 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A : +VCCBAT : H9 : power : : 1.2V : : +VCC_AUX : H10 : power : : 2.5V : : +GND : H11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A : +VCCIO7D_HPS : H16 : power : : 2.5V : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A : +VCCIO7A_HPS : H21 : power : : 2.5V : 7A : +HPS_TCK : H22 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A : +VCCIO6A_HPS : H26 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A : +GND : J1 : gnd : : : : +GND : J2 : gnd : : : : +GND : J3 : gnd : : : : +GND : J4 : gnd : : : : +nCONFIG : J5 : : : : 9A : +GND : J6 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A : +GND : J8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A : +VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A : +VCCIO8A : J13 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A : +DNU : J15 : : : : : +VCC_AUX : J16 : power : : 2.5V : : +VCCPD7C_HPS : J17 : power : : 2.5V : 7C : +GND : J18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B : +VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : : +VCC_AUX_SHARED : J21 : power : : 2.5V : : +GND : J22 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A : +GND : J28 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A : +GND : K1 : gnd : : : : +GND : K2 : gnd : : : : +DNU : K3 : : : : : +DNU : K4 : : : : : +GND : K5 : gnd : : : : +MSEL1 : K6 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A : +VCCA_FPLL : K9 : power : : 2.5V : : +GND : K10 : gnd : : : : +VCCPD8A : K11 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A : +VCCPD8A : K13 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A : +GND : K15 : gnd : : : : +VCCPD7D_HPS : K16 : power : : 2.5V : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B : +VCCPD7B_HPS : K18 : power : : 2.5V : 7B : +VCCPD7A_HPS : K19 : power : : 2.5V : 7A : +GND : K20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A : +VCCIO6A_HPS : K24 : power : : 2.5V : 6A : +GND : K25 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A : +VCCIO6A_HPS : K30 : power : : 2.5V : 6A : +GND : L1 : gnd : : : : +GND : L2 : gnd : : : : +GND : L3 : gnd : : : : +GND : L4 : gnd : : : : +VCC : L5 : power : : 1.1V : : +GND : L6 : gnd : : : : +MSEL3 : L7 : : : : 9A : +MSEL0 : L8 : : : : 9A : +MSEL4 : L9 : : : : 9A : +VCCPD8A : L10 : power : : 2.5V : 8A : +GND : L11 : gnd : : : : +VCCPD8A : L12 : power : : 2.5V : 8A : +GND : L13 : gnd : : : : +VCCPD8A : L14 : power : : 2.5V : 8A : +GND : L15 : gnd : : : : +VCC_HPS : L16 : power : : 1.1V : : +GND : L17 : gnd : : : : +VCC_HPS : L18 : power : : 1.1V : : +GND : L19 : gnd : : : : +VCC_HPS : L20 : power : : 1.1V : : +VCCPLL_HPS : L21 : power : : 2.5V : : +GND : L22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A : +VCCIO6A_HPS : L27 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A : +GND : M1 : gnd : : : : +GND : M2 : gnd : : : : +DNU : M3 : : : : : +DNU : M4 : : : : : +GND : M5 : gnd : : : : +VCC : M6 : power : : 1.1V : : +GND : M7 : gnd : : : : +GND : M8 : gnd : : : : +VCC : M9 : power : : 1.1V : : +GND : M10 : gnd : : : : +VCC : M11 : power : : 1.1V : : +GND : M12 : gnd : : : : +VCC : M13 : power : : 1.1V : : +GND : M14 : gnd : : : : +VCC_HPS : M15 : power : : 1.1V : : +GND : M16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D : +GND : M18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A : +GND : M20 : gnd : : : : +VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A : +VCCIO6A_HPS : M24 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A : +GND : M29 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A : +GND : N1 : gnd : : : : +GND : N2 : gnd : : : : +GND : N3 : gnd : : : : +GND : N4 : gnd : : : : +VCC : N5 : power : : 1.1V : : +GND : N6 : gnd : : : : +VCCA_FPLL : N7 : power : : 2.5V : : +GND : N8 : gnd : : : : +GND : N9 : gnd : : : : +VCC : N10 : power : : 1.1V : : +GND : N11 : gnd : : : : +VCC : N12 : power : : 1.1V : : +GND : N13 : gnd : : : : +VCC : N14 : power : : 1.1V : : +GND : N15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D : +GND : N17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A : +GND : N19 : gnd : : : : +VCC_HPS : N20 : power : : 1.1V : : +VCCIO6A_HPS : N21 : power : : 2.5V : 6A : +VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A : +GND : N26 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B : +GND : P1 : gnd : : : : +GND : P2 : gnd : : : : +DNU : P3 : : : : : +DNU : P4 : : : : : +GND : P5 : gnd : : : : +VCCA_FPLL : P6 : power : : 2.5V : : +GND : P7 : gnd : : : : +GND : P8 : gnd : : : : +GND : P9 : gnd : : : : +GND : P10 : gnd : : : : +VCC : P11 : power : : 1.1V : : +GND : P12 : gnd : : : : +VCC : P13 : power : : 1.1V : : +GND : P14 : gnd : : : : +VCC_HPS : P15 : power : : 1.1V : : +GND : P16 : gnd : : : : +VCC_HPS : P17 : power : : 1.1V : : +GND : P18 : gnd : : : : +VCC_HPS : P19 : power : : 1.1V : : +GND : P20 : gnd : : : : +VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B : +VCCIO6B_HPS : P23 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B : +VCCIO6B_HPS : P28 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B : +GND : R1 : gnd : : : : +GND : R2 : gnd : : : : +GND : R3 : gnd : : : : +GND : R4 : gnd : : : : +VCC : R5 : power : : 1.1V : : +GND : R6 : gnd : : : : +VCCA_FPLL : R7 : power : : 2.5V : : +GND : R8 : gnd : : : : +GND : R9 : gnd : : : : +VCC : R10 : power : : 1.1V : : +GND : R11 : gnd : : : : +VCC : R12 : power : : 1.1V : : +GND : R13 : gnd : : : : +VCC : R14 : power : : 1.1V : : +GND : R15 : gnd : : : : +VCC_HPS : R16 : power : : 1.1V : : +GND : R17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B : +VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B : +VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B : +VCCIO6B_HPS : R25 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B : +GND : R30 : gnd : : : : +GND : T1 : gnd : : : : +GND : T2 : gnd : : : : +DNU : T3 : : : : : +DNU : T4 : : : : : +GND : T5 : gnd : : : : +VCC : T6 : power : : 1.1V : : +GND : T7 : gnd : : : : +GND : T8 : gnd : : : : +GND : T9 : gnd : : : : +GND : T10 : gnd : : : : +VCC : T11 : power : : 1.1V : : +GND : T12 : gnd : : : : +VCC : T13 : power : : 1.1V : : +GND : T14 : gnd : : : : +GND : T15 : gnd : : : : +GND : T16 : gnd : : : : +VCC_HPS : T17 : power : : 1.1V : : +GND : T18 : gnd : : : : +VCC_HPS : T19 : power : : 1.1V : : +GND : T20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B : +VCCIO6B_HPS : T22 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B : +GND : T27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B : +GND : U1 : gnd : : : : +GND : U2 : gnd : : : : +GND : U3 : gnd : : : : +GND : U4 : gnd : : : : +VCC : U5 : power : : 1.1V : : +GND : U6 : gnd : : : : +DCLK : U7 : : : : 3A : +TDI : U8 : input : : : 3A : +GND : U9 : gnd : : : : +VCC : U10 : power : : 1.1V : : +GND : U11 : gnd : : : : +VCC : U12 : power : : 1.1V : : +GND : U13 : gnd : : : : +VCC : U14 : power : : 1.1V : : +GND : U15 : gnd : : : : +VCC_HPS : U16 : power : : 1.1V : : +GND : U17 : gnd : : : : +VCC_HPS : U18 : power : : 1.1V : : +VCCIO6B_HPS : U19 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B : +VCC : U21 : power : : 1.1V : : +GND : U22 : gnd : : : : +VCCPD5B : U23 : power : : 2.5V : 5B : +GND : U24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B : +GND : U29 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B : +GND : V1 : gnd : : : : +GND : V2 : gnd : : : : +DNU : V3 : : : : : +DNU : V4 : : : : : +GND : V5 : gnd : : : : +VCCA_FPLL : V6 : power : : 2.5V : : +GND : V7 : gnd : : : : +VCCA_FPLL : V8 : power : : 2.5V : : +TMS : V9 : input : : : 3A : +GND : V10 : gnd : : : : +VCC : V11 : power : : 1.1V : : +GND : V12 : gnd : : : : +VCC : V13 : power : : 1.1V : : +GND : V14 : gnd : : : : +VCC : V15 : power : : 1.1V : : +LEDR[0] : V16 : output : 2.5 V : : 4A : Y +LEDR[2] : V17 : output : 2.5 V : : 4A : Y +LEDR[3] : V18 : output : 2.5 V : : 4A : Y +GND : V19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B : +GND : V21 : gnd : : : : +VCCPD5A : V22 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5A : +VCCPD5A : V24 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B : +VCCIO6B_HPS : V26 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B : +GND : W1 : gnd : : : : +GND : W2 : gnd : : : : +GND : W3 : gnd : : : : +GND : W4 : gnd : : : : +VCC : W5 : power : : 1.1V : : +GND : W6 : gnd : : : : +GND : W7 : gnd : : : : +GND : W8 : gnd : : : : +GND : W9 : gnd : : : : +VCC : W10 : power : : 1.1V : : +GND : W11 : gnd : : : : +VCC : W12 : power : : 1.1V : : +GND : W13 : gnd : : : : +VCC : W14 : power : : 1.1V : : +KEY[2] : W15 : input : 2.5 V : : 3B : Y +LEDR[1] : W16 : output : 2.5 V : : 4A : Y +LEDR[4] : W17 : output : 2.5 V : : 4A : Y +GND : W18 : gnd : : : : +LEDR[5] : W19 : output : 2.5 V : : 4A : Y +LEDR[7] : W20 : output : 2.5 V : : 5A : Y +LEDR[8] : W21 : output : 2.5 V : : 5A : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5A : +VCCIO5A : W23 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B : +GND : W28 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B : +GND : Y1 : gnd : : : : +GND : Y2 : gnd : : : : +DNU : Y3 : : : : : +DNU : Y4 : : : : : +GND : Y5 : gnd : : : : +VCC : Y6 : power : : 1.1V : : +GND : Y7 : gnd : : : : +GND : Y8 : gnd : : : : +VCC : Y9 : power : : 1.1V : : +GND : Y10 : gnd : : : : +VCC : Y11 : power : : 1.1V : : +GND : Y12 : gnd : : : : +VCC : Y13 : power : : 1.1V : : +GND : Y14 : gnd : : : : +GND : Y15 : gnd : : : : +KEY[3] : Y16 : input : 2.5 V : : 3B : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A : +LEDR[6] : Y19 : output : 2.5 V : : 4A : Y +GND : Y20 : gnd : : : : +LEDR[9] : Y21 : output : 2.5 V : : 5A : Y +VCCA_FPLL : Y22 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A : +GND : Y25 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B : +GND : Y30 : gnd : : : : diff --git a/quartus workspace/output_files/top.sld b/quartus workspace/output_files/top.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/quartus workspace/output_files/top.sld @@ -0,0 +1 @@ + diff --git a/quartus workspace/output_files/top.sof b/quartus workspace/output_files/top.sof new file mode 100644 index 0000000..4993b55 Binary files /dev/null and b/quartus workspace/output_files/top.sof differ diff --git a/quartus workspace/output_files/top.sta.rpt b/quartus workspace/output_files/top.sta.rpt new file mode 100644 index 0000000..ca365fa --- /dev/null +++ b/quartus workspace/output_files/top.sta.rpt @@ -0,0 +1,699 @@ +Timing Analyzer report for top +Mon Jan 12 21:16:42 2026 +Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1100mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1100mV 85C Model Setup Summary + 9. Slow 1100mV 85C Model Hold Summary + 10. Slow 1100mV 85C Model Recovery Summary + 11. Slow 1100mV 85C Model Removal Summary + 12. Slow 1100mV 85C Model Minimum Pulse Width Summary + 13. Slow 1100mV 85C Model Metastability Summary + 14. Slow 1100mV 0C Model Fmax Summary + 15. Slow 1100mV 0C Model Setup Summary + 16. Slow 1100mV 0C Model Hold Summary + 17. Slow 1100mV 0C Model Recovery Summary + 18. Slow 1100mV 0C Model Removal Summary + 19. Slow 1100mV 0C Model Minimum Pulse Width Summary + 20. Slow 1100mV 0C Model Metastability Summary + 21. Fast 1100mV 85C Model Setup Summary + 22. Fast 1100mV 85C Model Hold Summary + 23. Fast 1100mV 85C Model Recovery Summary + 24. Fast 1100mV 85C Model Removal Summary + 25. Fast 1100mV 85C Model Minimum Pulse Width Summary + 26. Fast 1100mV 85C Model Metastability Summary + 27. Fast 1100mV 0C Model Setup Summary + 28. Fast 1100mV 0C Model Hold Summary + 29. Fast 1100mV 0C Model Recovery Summary + 30. Fast 1100mV 0C Model Removal Summary + 31. Fast 1100mV 0C Model Minimum Pulse Width Summary + 32. Fast 1100mV 0C Model Metastability Summary + 33. Multicorner Timing Analysis Summary + 34. Board Trace Model Assignments + 35. Input Transition Times + 36. Signal Integrity Metrics (Slow 1100mv 0c Model) + 37. Signal Integrity Metrics (Slow 1100mv 85c Model) + 38. Signal Integrity Metrics (Fast 1100mv 0c Model) + 39. Signal Integrity Metrics (Fast 1100mv 85c Model) + 40. Setup Transfers + 41. Hold Transfers + 42. Report TCCS + 43. Report RSKM + 44. Unconstrained Paths Summary + 45. Clock Status Summary + 46. Unconstrained Input Ports + 47. Unconstrained Output Ports + 48. Unconstrained Input Ports + 49. Unconstrained Output Ports + 50. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2023 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++--------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+--------------------------------------------------------+ +; Quartus Prime Version ; Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; top ; +; Device Family ; Cyclone V ; +; Device Name ; 5CSEMA5F31C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+--------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 16 ; +; Maximum allowed ; 16 ; +; ; ; +; Average used ; 3.47 ; +; Maximum used ; 16 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 20.0% ; +; Processor 3 ; 19.8% ; +; Processor 4 ; 19.7% ; +; Processor 5 ; 15.7% ; +; Processor 6 ; 15.7% ; +; Processor 7 ; 15.7% ; +; Processor 8 ; 15.7% ; +; Processor 9 ; 15.7% ; +; Processor 10 ; 15.6% ; +; Processor 11 ; 15.6% ; +; Processor 12 ; 15.6% ; +; Processor 13 ; 15.6% ; +; Processor 14 ; 15.6% ; +; Processor 15 ; 15.6% ; +; Processor 16 ; 15.6% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------+ +; SDC File List ; ++---------------------------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++---------------------------------+--------+--------------------------+ +; ../envs/de1-soc/quartus/top.sdc ; OK ; Mon Jan 12 21:16:37 2026 ; ++---------------------------------+--------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ + + ++-------------------------------------------------+ +; Slow 1100mV 85C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 69.34 MHz ; 69.34 MHz ; CLOCK_50 ; ; ++-----------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++-------------------------------------+ +; Slow 1100mV 85C Model Setup Summary ; ++----------+-------+------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+------------------+ +; CLOCK_50 ; 5.578 ; 0.000 ; ++----------+-------+------------------+ + + ++------------------------------------+ +; Slow 1100mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 0.307 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Slow 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Slow 1100mV 85C Model Minimum Pulse Width Summary ; ++----------+-------+--------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+--------------------------------+ +; CLOCK_50 ; 8.877 ; 0.000 ; ++----------+-------+--------------------------------+ + + +----------------------------------------------- +; Slow 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++-------------------------------------------------+ +; Slow 1100mV 0C Model Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 70.34 MHz ; 70.34 MHz ; CLOCK_50 ; ; ++-----------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------+ +; Slow 1100mV 0C Model Setup Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 5.784 ; 0.000 ; ++----------+-------+-----------------+ + + ++-----------------------------------+ +; Slow 1100mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; CLOCK_50 ; 0.295 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Slow 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Slow 1100mV 0C Model Minimum Pulse Width Summary ; ++----------+-------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-------------------------------+ +; CLOCK_50 ; 8.823 ; 0.000 ; ++----------+-------+-------------------------------+ + + +---------------------------------------------- +; Slow 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-------------------------------------+ +; Fast 1100mV 85C Model Setup Summary ; ++----------+--------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+-----------------+ +; CLOCK_50 ; 10.798 ; 0.000 ; ++----------+--------+-----------------+ + + ++------------------------------------+ +; Fast 1100mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; CLOCK_50 ; 0.177 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Fast 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Fast 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Fast 1100mV 85C Model Minimum Pulse Width Summary ; ++----------+-------+--------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+--------------------------------+ +; CLOCK_50 ; 8.784 ; 0.000 ; ++----------+-------+--------------------------------+ + + +----------------------------------------------- +; Fast 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------+ +; Fast 1100mV 0C Model Setup Summary ; ++----------+--------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+----------------+ +; CLOCK_50 ; 11.789 ; 0.000 ; ++----------+--------+----------------+ + + ++-----------------------------------+ +; Fast 1100mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; CLOCK_50 ; 0.165 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Fast 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Fast 1100mV 0C Model Minimum Pulse Width Summary ; ++----------+-------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-------------------------------+ +; CLOCK_50 ; 8.776 ; 0.000 ; ++----------+-------+-------------------------------+ + + +---------------------------------------------- +; Fast 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 5.578 ; 0.165 ; N/A ; N/A ; 8.776 ; +; CLOCK_50 ; 5.578 ; 0.165 ; N/A ; N/A ; 8.776 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; CLOCK_50 ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ++------------------+-------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; UART_RX ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++-------------------------------------------------------------+ +; Input Transition Times ; ++----------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++----------+--------------+-----------------+-----------------+ +; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; KEY[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; KEY[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; CLOCK_50 ; 2.5 V ; 2000 ps ; 2000 ps ; +; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; UART_TX ; 2.5 V ; 2000 ps ; 2000 ps ; ++----------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; +; UART_RX ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; +; UART_RX ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; UART_RX ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; UART_RX ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; ++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 5843881 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 5843881 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 2 ; 2 ; +; Unconstrained Input Ports ; 1 ; 1 ; +; Unconstrained Input Port Paths ; 1 ; 1 ; +; Unconstrained Output Ports ; 11 ; 11 ; +; Unconstrained Output Port Paths ; 11 ; 11 ; ++---------------------------------+-------+------+ + + ++-----------------------------------------------------------------------------------------------+ +; Clock Status Summary ; ++-------------------------------------------------------------+----------+------+---------------+ +; Target ; Clock ; Type ; Status ; ++-------------------------------------------------------------+----------+------+---------------+ +; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ; +; utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB ; ; Base ; Unconstrained ; +; utoss_riscv:core|instruction[0] ; ; Base ; Unconstrained ; ++-------------------------------------------------------------+----------+------+---------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; UART_TX ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; UART_RX ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; UART_TX ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; UART_RX ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition + Info: Processing started: Mon Jan 12 21:16:35 2026 +Info: Command: quartus_sta top -c top +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 16 of the 16 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Warning (335093): The Timing Analyzer is analyzing 40 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report. +Info (332104): Reading SDC File: '../envs/de1-soc/quartus/top.sdc' +Warning (332174): Ignored filter at top.sdc(9): LEDR could not be matched with a port File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc Line: 9 +Warning (332049): Ignored set_false_path at top.sdc(9): Argument is an empty collection File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc Line: 9 + Info (332050): set_false_path -from [get_ports LEDR] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc Line: 9 +Warning (332049): Ignored set_false_path at top.sdc(10): Argument is an empty collection File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc Line: 10 + Info (332050): set_false_path -to [get_ports LEDR] File: E:/risc-v-boris-basic-execution-environment/risc-v-boris-basic-execution-environment/envs/de1-soc/quartus/top.sdc Line: 10 +Warning (332060): Node: utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch utoss_riscv:core|ControlFSM:control_fsm|ALUSrcB[1] is being clocked by utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB +Warning (332060): Node: utoss_riscv:core|instruction[0] was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[5] is being clocked by utoss_riscv:core|instruction[0] +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1100mV 85C Model +Info (332146): Worst-case setup slack is 5.578 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 5.578 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.307 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.307 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.877 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.877 0.000 CLOCK_50 +Info: Analyzing Slow 1100mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch utoss_riscv:core|ControlFSM:control_fsm|ALUSrcB[1] is being clocked by utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB +Warning (332060): Node: utoss_riscv:core|instruction[0] was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[5] is being clocked by utoss_riscv:core|instruction[0] +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332146): Worst-case setup slack is 5.784 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 5.784 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.295 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.295 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.823 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.823 0.000 CLOCK_50 +Info: Analyzing Fast 1100mV 85C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch utoss_riscv:core|ControlFSM:control_fsm|ALUSrcB[1] is being clocked by utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB +Warning (332060): Node: utoss_riscv:core|instruction[0] was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[5] is being clocked by utoss_riscv:core|instruction[0] +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332146): Worst-case setup slack is 10.798 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 10.798 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.177 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.177 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.784 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.784 0.000 CLOCK_50 +Info: Analyzing Fast 1100mV 0C Model +Warning (332060): Node: utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch utoss_riscv:core|ControlFSM:control_fsm|ALUSrcB[1] is being clocked by utoss_riscv:core|ControlFSM:control_fsm|current_state.ALUWB +Warning (332060): Node: utoss_riscv:core|instruction[0] was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch utoss_riscv:core|Instruction_Decode:instruction_decode|imm_ext[5] is being clocked by utoss_riscv:core|instruction[0] +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332146): Worst-case setup slack is 11.789 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 11.789 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.165 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.165 0.000 CLOCK_50 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 8.776 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 8.776 0.000 CLOCK_50 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 13 warnings + Info: Peak virtual memory: 5485 megabytes + Info: Processing ended: Mon Jan 12 21:16:42 2026 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:18 + + diff --git a/quartus workspace/output_files/top.sta.summary b/quartus workspace/output_files/top.sta.summary new file mode 100644 index 0000000..acfb755 --- /dev/null +++ b/quartus workspace/output_files/top.sta.summary @@ -0,0 +1,53 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1100mV 85C Model Setup 'CLOCK_50' +Slack : 5.578 +TNS : 0.000 + +Type : Slow 1100mV 85C Model Hold 'CLOCK_50' +Slack : 0.307 +TNS : 0.000 + +Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50' +Slack : 8.877 +TNS : 0.000 + +Type : Slow 1100mV 0C Model Setup 'CLOCK_50' +Slack : 5.784 +TNS : 0.000 + +Type : Slow 1100mV 0C Model Hold 'CLOCK_50' +Slack : 0.295 +TNS : 0.000 + +Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50' +Slack : 8.823 +TNS : 0.000 + +Type : Fast 1100mV 85C Model Setup 'CLOCK_50' +Slack : 10.798 +TNS : 0.000 + +Type : Fast 1100mV 85C Model Hold 'CLOCK_50' +Slack : 0.177 +TNS : 0.000 + +Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50' +Slack : 8.784 +TNS : 0.000 + +Type : Fast 1100mV 0C Model Setup 'CLOCK_50' +Slack : 11.789 +TNS : 0.000 + +Type : Fast 1100mV 0C Model Hold 'CLOCK_50' +Slack : 0.165 +TNS : 0.000 + +Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50' +Slack : 8.776 +TNS : 0.000 + +------------------------------------------------------------ diff --git a/quartus workspace/src/ALU_ALUdecoder/ALU.v b/quartus workspace/src/ALU_ALUdecoder/ALU.v new file mode 100644 index 0000000..a41baa5 --- /dev/null +++ b/quartus workspace/src/ALU_ALUdecoder/ALU.v @@ -0,0 +1,28 @@ +module ALU + ( input [31:0] a + , input [31:0] b + , input [3:0] alu_control + , output reg [31:0] out + , output zeroE + ); + always @(*) + begin + case (alu_control) + 4'b0000: out = a + b; // ADD + 4'b0001: out = a - b; // SUB + 4'b0010: out = a << b[4:0]; // SLL + 4'b0011: out = ($signed(a) < $signed(b)) ? 32'b1 : 32'b0; // SLT + 4'b0100: out = (a < b) ? 32'b1 : 32'b0; // SLTU + 4'b0101: out = a ^ b; // XOR + 4'b0110: out = a >> b[4:0]; // SRL + 4'b0111: out = $signed(a) >>> b[4:0]; // SRA + 4'b1000: out = a | b; // OR + 4'b1001: out = a & b; // AND + 4'b1010: out = ($signed(a) >= $signed(b)) ? 32'b1 : 32'b0; // SGE + 4'b1011: out = (a >= b) ? 32'b1 : 32'b0; // SGEU + default: out = 32'b0; + endcase + end + assign zeroE = (out == 0); +endmodule + diff --git a/quartus workspace/src/ALU_ALUdecoder/ALUdecoder.sv b/quartus workspace/src/ALU_ALUdecoder/ALUdecoder.sv new file mode 100644 index 0000000..7ef8894 --- /dev/null +++ b/quartus workspace/src/ALU_ALUdecoder/ALUdecoder.sv @@ -0,0 +1,58 @@ +`include "src/types.svh" + +module ALUdecoder ( input [2:0] funct3 + , input [6:0] funct7 + , input alu_op_t alu_op + , output reg [3:0] alu_control + ); + always @(*) + begin + case (alu_op) + ALU_OP__ADD: alu_control = 4'b0000; //lw, sw (ADD) + ALU_OP__BRANCH: + begin + case (funct3) + 3'b000: alu_control = 4'b0001; //beq (SUB) + 3'b001: alu_control = 4'b0001; // bne (SUB) + 3'b100: alu_control = 4'b0011; // blt (SLT) + 3'b110: alu_control = 4'b0100; // bltu (SLTU) + 3'b101: alu_control = 4'b1010; // bge (SGE) + 3'b111: alu_control = 4'b1011; // bgeu (SGEU) + default: alu_control = 4'b0001; // SUB + endcase + end + ALU_OP__REGISTER_OPERATION: //R type + begin + case (funct3) + 3'b000: if (funct7 == 7'h00) alu_control = 4'b0000; //ADD + else if (funct7 == 7'h20) alu_control = 4'b0001; //SUB + 3'b001: alu_control = 4'b0010; //SLL + 3'b010: alu_control = 4'b0011; //SLT + 3'b011: alu_control = 4'b0100; //SLTU + 3'b100: alu_control = 4'b0101; //XOR + 3'b101: if (funct7 == 7'h00) alu_control = 4'b0110; //SRL + else if (funct7 == 7'h20) alu_control = 4'b0111; //SRA + 3'b110: alu_control = 4'b1000; //OR + 3'b111: alu_control = 4'b1001; //AND + default: alu_control = 4'b0; + endcase + end + ALU_OP__UNSET: //I type + begin + case (funct3) + 3'b000: alu_control = 4'b0000; //ADDI + 3'b001: alu_control = 4'b0010; //SLLI + 3'b010: alu_control = 4'b0011; //SLTI + 3'b011: alu_control = 4'b0100; //SLTIU + 3'b100: alu_control = 4'b0101; //XORI + 3'b101: if (funct7 == 7'h00) alu_control = 4'b0110; //SRLI + else if (funct7 == 7'h20) alu_control = 4'b0111; //SRAI +// I type doesn't have funct7; the funct7 here is the upper 7 bits of the immediate + 3'b110: alu_control = 4'b1000; //ORI + 3'b111: alu_control = 4'b1001; //ANDI + default: alu_control = 4'b0; + endcase + end + endcase + end +endmodule diff --git a/quartus workspace/src/ControlFSM.sv b/quartus workspace/src/ControlFSM.sv new file mode 100644 index 0000000..b7a120a --- /dev/null +++ b/quartus workspace/src/ControlFSM.sv @@ -0,0 +1,317 @@ +//created by Joonseo Park, for University of Toronto Open Source Society +//A Moore Type Finite State Machine for the RV32I Microprocessor Control Unit + +`include "src/types.svh" +`include "src/params.svh" + +module ControlFSM + ( input opcode_t opcode + , input wire clk + , input wire reset + , input wire zero_flag + , input wire [3:0] MemWriteByteAddress + , input wire [2:0] funct3 + , input data_t alu_result + , output adr_src_t AdrSrc + , output reg IRWrite + , output reg RegWrite + , output reg PCUpdate + , output pc_src_t pc_src + , output reg [3:0] MemWrite + , output reg Branch + , output alu_src_a_t ALUSrcA + , output alu_src_b_t ALUSrcB + , output result_src_t ResultSrc + , output reg [4:0] FSMState + ); + + //parameterize states (binary encoding) + //in later systemverilog implementation, change to enum + parameter FETCH = 5'b00000; + parameter DECODE = 5'b00001; + parameter EXECUTER = 5'b00010; + parameter UNCONDJUMP = 5'b00011; + parameter EXECUTEI = 5'b00100; + parameter MEMADR = 5'b00101; + parameter ALUWB = 5'b00110; + parameter MEMWRITE = 5'b00111; + parameter MEMREAD = 5'b01000; + parameter MEMWB = 5'b01001; + parameter BRANCHIFEQ = 5'b01010; + + //new states for lui and auipc + parameter LUI = 5'b01011; + parameter AUIPC = 5'b01100; + + parameter JALR_CALC = 5'b01101; // calculate rs1 + imm, store in alu_out + parameter JALR_STEP2 = 5'b01110; // link and use alu_out to update PC + + // new state for remaining branch instructions + parameter BRANCHCOMP = 5'b01111; + + //declare state registers + reg [4:0] current_state, next_state; + + //Next state logic + always @(*)begin + + case (current_state) + + FETCH: next_state = DECODE; + + DECODE: begin + + if (opcode == JType) next_state = UNCONDJUMP; + + else if (opcode == RType) next_state = EXECUTER; + + else if (opcode == IType_logic) next_state = EXECUTEI; + + else if (opcode == IType_load || opcode == SType) next_state = MEMADR; + + else if (opcode == BType) begin + + case (funct3) + + 3'b000: next_state = BRANCHIFEQ; + + 3'b001: next_state = BRANCHIFEQ; + + default: next_state = BRANCHCOMP; + + endcase + + end + + else if (opcode == UType_auipc) next_state = AUIPC; + + else if (opcode == UType_lui) next_state = LUI; + + else if (opcode == IType_jalr) next_state = JALR_CALC; + + else if (opcode == FENCE) next_state = FETCH; + + else next_state = DECODE; + + end + + AUIPC: next_state = ALUWB; + + LUI: next_state = ALUWB; + + UNCONDJUMP: next_state = ALUWB; + + EXECUTER: next_state = ALUWB; + + EXECUTEI: next_state = ALUWB; + + MEMADR: begin + + if (opcode == IType_load) next_state = MEMREAD; + + else if (opcode == SType) next_state = MEMWRITE; + + else next_state = MEMADR; + + end + + BRANCHIFEQ: next_state = FETCH; + + BRANCHCOMP: next_state = FETCH; + + ALUWB: next_state = FETCH; + + MEMREAD: next_state = MEMWB; + + MEMWRITE: next_state = FETCH; + + MEMWB: next_state = FETCH; + + JALR_CALC: next_state = JALR_STEP2; + + JALR_STEP2: next_state = ALUWB; + + default: next_state = FETCH; + + endcase + + end + + //output logic + always @(*) begin + Branch <= 1'b0; + pc_src <= PC_SRC__INCREMENT; + PCUpdate <= 1'b0; + IRWrite <= 1'b0; + MemWrite <= 4'b0; + RegWrite <= 1'b0; + + FSMState <= current_state; + + case (current_state) + + FETCH: begin + + AdrSrc <= ADR_SRC__PC; + IRWrite <= 1'b1; + PCUpdate <= 1'b1; + + end + + DECODE: begin + + ALUSrcA <= ALU_SRC_A__OLD_PC; + ALUSrcB <= ALU_SRC_B__IMM_EXT; + + end + + AUIPC: begin + + ALUSrcA <= ALU_SRC_A__OLD_PC; + ALUSrcB <= ALU_SRC_B__IMM_EXT; + + end + + LUI: begin + + ALUSrcA <= ALU_SRC_A__ZERO; + ALUSrcB <= ALU_SRC_B__IMM_EXT; + + end + + EXECUTER: begin + + ALUSrcA <= ALU_SRC_A__RD1; + ALUSrcB <= ALU_SRC_B__RD2; + + end + + EXECUTEI: begin + + ALUSrcA <= ALU_SRC_A__RD1; + ALUSrcB <= ALU_SRC_B__IMM_EXT; + + end + + UNCONDJUMP: begin + + ALUSrcA <= ALU_SRC_A__OLD_PC; + ALUSrcB <= ALU_SRC_B__4; + ResultSrc <= RESULT_SRC__ALU_OUT; + PCUpdate <= 1'b1; + pc_src <= PC_SRC__JUMP; // new added + + end + + JALR_CALC: begin + ALUSrcA <= ALU_SRC_A__RD1; // rs1 + ALUSrcB <= ALU_SRC_B__IMM_EXT; // + imm + end + + JALR_STEP2: begin + ALUSrcA <= ALU_SRC_A__OLD_PC; // Calculate link = pc_old + 4, write back in ALUWB + ALUSrcB <= ALU_SRC_B__4; + ResultSrc <= RESULT_SRC__ALU_OUT; + pc_src <= PC_SRC__ALU_RESULT; // fetch (alu_out & ~1) for new PC + PCUpdate <= 1'b1; + end + + + MEMADR: begin + + ALUSrcA <= ALU_SRC_A__RD1; + ALUSrcB <= ALU_SRC_B__IMM_EXT; + + end + + BRANCHIFEQ: begin + + ALUSrcA <= ALU_SRC_A__RD1; + ALUSrcB <= ALU_SRC_B__RD2; + ResultSrc <= RESULT_SRC__ALU_OUT; + Branch <= 1'b1; + case (funct3) + 3'b000: begin + if (zero_flag) begin + pc_src <= PC_SRC__JUMP; + PCUpdate <= 1'b1; + end + else pc_src <= PC_SRC__INCREMENT; + end + + 3'b001: begin + if (!zero_flag) begin + pc_src <= PC_SRC__JUMP; + PCUpdate <= 1'b1; + end + else pc_src <= PC_SRC__INCREMENT; + end + endcase + end + + BRANCHCOMP: begin + + ALUSrcA <= ALU_SRC_A__RD1; + ALUSrcB <= ALU_SRC_B__RD2; + ResultSrc <= RESULT_SRC__ALU_OUT; + Branch <= 1'b1; + if (alu_result == 32'b1) begin + pc_src <= PC_SRC__JUMP; + PCUpdate <= 1'b1; + end + else pc_src <= PC_SRC__INCREMENT; + + end + + ALUWB: begin + + ResultSrc <= RESULT_SRC__ALU_OUT; + RegWrite <= 1'b1; + + end + + MEMWRITE: begin + + ResultSrc <= RESULT_SRC__ALU_OUT; + AdrSrc <= ADR_SRC__RESULT; + MemWrite <= MemWriteByteAddress; + + end + + MEMREAD: begin + + ResultSrc <= RESULT_SRC__ALU_OUT; + AdrSrc <= ADR_SRC__RESULT; + + end + + MEMWB: begin + + ResultSrc <= RESULT_SRC__DATA; + RegWrite <= 1'b1; + + end + + default: begin //by default, we return to FETCH state + + AdrSrc <= ADR_SRC__PC; + IRWrite <= 1'b1; + + end + + + endcase + + end + + //State transition logic (sequential) + always @ (posedge clk) begin + + if (reset) current_state <= FETCH; + + else begin + current_state <= next_state; + end + + end +endmodule diff --git a/quartus workspace/src/Instruction_Decode/ControlFSMTB.py b/quartus workspace/src/Instruction_Decode/ControlFSMTB.py new file mode 100644 index 0000000..6945d70 --- /dev/null +++ b/quartus workspace/src/Instruction_Decode/ControlFSMTB.py @@ -0,0 +1,60 @@ +#Created by Joonseo Park +import cocotb #cocoTB library +from cocotb.triggers import Timer +from cocotb.triggers import ClockCycles +from cocotb.triggers import RisingEdge +from cocotb.clock import Clock + +#Implement function for checking each state +#check if each state that the FSM goes to corresponds to the states that we should see (as described in dictionaries) +#for state inthisdict +async def checkStates(statesList: list, dut) -> bool: + for state in statesList: + if (dut.FSMState.value != statesList[state]): + return [False, statesList[state]] + await RisingEdge(dut.clk) +return True + +#Testbench function +@cocotb.test() +async def ControlFSMTB(dut): + + correctStates = True + + #start() is a cocoTB trigger for starting a concurrent execution + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + #reset the DUT for 2 clock cycles + dut.reset.value = 1 + await ClockCycles(dut.clk, 2, rising=True) + assert dut.FSMState.value == 0b0000, "Error: upon reset, the FSM state is not set to FETCH" + + #Opcode = 7'b0110011 (R-Type) + dut.opcode.value = 0b0110011 + RTypeStates = [0b0000, 0b0001, 0b0010, 0b0110, 0b0000] + correctStates = await checkStates(RTypeStates, dut) + assert correctStates[0] == True, f"Incorrect states generated for opcode = {dut.opcode.value}, (R-Type). The first incorrect state is {correctStates[1]}" + + #Opcode = 7'b0010011 (I-Type) + dut.opcode.value = 0b0010011 + ITypeStates = [0b0000, 0b0001, 0b0100, 0b0110, 0b0000] + correctStates = await checkStates(ITypeStates, dut) + assert correctStates[0] == True, f"Incorrect states generated for opcode = {dut.opcode.value}, (I-Type). The first incorrect state is {correctStates[1]}" + + #Opcode = 7'b0000011 (lw) + dut.opcode.value = 0b0000011 + LWTypeStates = [0b0000, 0b0001, 0b0101, 0b1000, 0b1001, 0b0000] + correctStates = await checkStates(LWTypeStates, dut) + assert correctStates[0] == True, f"Incorrect states generated for opcode = {dut.opcode.value}, (lw). The first incorrect state is {correctStates[1]}" + + #Opcode = 7'b0100011 (sw) + dut.opcode.value = 0b0100011 + SWTypeStates = [0b0000, 0b0001, 0b0101, 0b0111] + correctStates = await checkStates(LWTypeStates, dut) + assert correctStates[0] == True, f"Incorrect states generated for opcode = {dut.opcode.value}, (sw). The first incorrect state is {correctStates[1]}" + +#Opcode = 7'b1101111 (J-Type) +dut.opcode.value = 0b1101111 +JTypeStates = [0b0000, 0b0001, 0b0011, 0b0110, 0b0000] +correctStates = await checkStates(LWTypeStates, dut) +assert correctStates[0] == True, f"Incorrect states generated for opcode = {dut.opcode.value}, (J-Type). The first incorrect state is {correctStates[1]}" diff --git a/quartus workspace/src/Instruction_Decode/Instruction_Decode.sv b/quartus workspace/src/Instruction_Decode/Instruction_Decode.sv new file mode 100644 index 0000000..d2d4d78 --- /dev/null +++ b/quartus workspace/src/Instruction_Decode/Instruction_Decode.sv @@ -0,0 +1,149 @@ +`include "src/params.svh" +`include "src/types.svh" + +module Instruction_Decode + ( input wire [31:0] instr + , output opcode_t opcode + , output wire [3:0] ALUControl + , output imm_t imm_ext + , output reg [2:0] funct3 + , output reg [6:0] funct7 + , output reg [4:0] rd + , output reg [4:0] rs1 + , output reg [4:0] rs2 + ); + + alu_op_t alu_op; + // reg [2:0] funct3; + // reg [6:0] funct7; + wire [3:0] state; + + assign opcode = instr[6:0]; + + //combinational logic for extracting funct3 and funct7[5] for ALU Decoder input + always @(*) begin + + if (opcode == RType || opcode == IType_logic) begin //R-Type + + funct3 = instr[14:12]; + funct7 = instr[31:25]; + + end + + else if (opcode == IType_load || opcode == SType || opcode == BType) begin + + funct3 = instr[14:12]; + funct7 = 7'b0; + + end + + else begin // U-Type and J-Type + + funct3 = 3'b000; + funct7 = 7'b0; + + end + + end + + // determine ALU op based on the opcode; see Table 7.2 of the digital design and computer + // architecture book + always @(*) begin + case (opcode) + RType: alu_op = ALU_OP__REGISTER_OPERATION; + IType_load: alu_op = ALU_OP__ADD; + IType_jalr: alu_op = ALU_OP__ADD; // rs1 + imm + SType: alu_op = ALU_OP__ADD; + BType: alu_op = ALU_OP__BRANCH; + UType_auipc: alu_op = ALU_OP__ADD; // used to add 0 to imm ext + UType_lui: alu_op = ALU_OP__ADD; // used to add 0 to imm ext + FENCE: alu_op = ALU_OP__UNSET; + default: alu_op = ALU_OP__UNSET; + + endcase + end + + //logic for extracting rs1, rs2, and rd registers from 32-bit instruction field + //The logic depends on the instruction type + always @(*) begin + + if (opcode == RType) begin //R-Type + + rd = instr[11:7]; + rs1 = instr[19:15]; + rs2 = instr[24:20]; + + end + + else if (opcode == IType_logic || opcode == IType_load) begin //I-Type (where lw is I type) + + rd = instr[11:7]; + rs1 = instr[19:15]; + rs2 = 5'b00000; + + end + + else if (opcode == SType || opcode == BType) begin //S-type and B-Type + + rd = 5'b00000; + rs1 = instr[19:15]; + rs2 = instr[24:20]; + + end + + else if (opcode == JType) begin //J-Type + + rd = instr[11:7]; + rs1 = 5'b00000; + rs2 = 5'b00000; + + end + + else if (opcode == UType_auipc || opcode == UType_lui) begin + rd = instr[11:7]; + rs1 = 5'b00000; + rs2 = 5'b00000; + end + + else if (opcode == IType_jalr) begin + rd = instr[11:7]; + rs1 = instr[19:15]; + rs2 = 5'b00000; + end + + else begin + + rd = 5'b00000; + rs1 = 5'b00000; + rs2 = 5'b00000; + + end + + end + + // case statement for choosing 32-bit immediate format; based on opcode + // this is essentially the extend module of the processor + always @(*) begin + case (opcode) + IType_logic : imm_ext = {{20{instr[31]}}, instr[31:20]}; + IType_load : imm_ext = {{20{instr[31]}}, instr[31:20]}; + IType_jalr : imm_ext = {{20{instr[31]}}, instr[31:20]}; + SType : imm_ext = {{20{instr[31]}}, instr[31:25], instr[11:7]}; + BType : imm_ext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0}; + JType : imm_ext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; + UType_auipc : imm_ext = {instr[31:12], 12'b0}; + UType_lui : imm_ext = {instr[31:12], 12'b0}; + + endcase + end + + //Instantiate ALU Decoder module + + ALUdecoder instanceALUDec + ( .funct3(funct3) + , .funct7(funct7) + , .alu_op(alu_op) + , .alu_control(ALUControl) + ); + +endmodule diff --git a/quartus workspace/src/Instruction_Decode/Makefile b/quartus workspace/src/Instruction_Decode/Makefile new file mode 100644 index 0000000..784b308 --- /dev/null +++ b/quartus workspace/src/Instruction_Decode/Makefile @@ -0,0 +1,20 @@ +SRC_DIR := src +OUTPUT := out/top.vvp +IVERILOG := iverilog +VVP := vvp + +SRCS := $(SRC_DIR)/Instruction_Decode/RegisterFile.v + +all: $(OUTPUT) + +$(OUTPUT): $(SRCS) + $(IVERILOG) -g2012 -o $(OUTPUT) + +run: $(OUTPUT) + $(VVP) $(OUTPUT) + +# tmp +RegFile_TB: + $(IVERILOG) -g2012 -o $(OUTPUT) $(SRCS) src/Instruction_Decode/RegisterFile.v test/RegFile_TB.sv + +.PHONY: all run \ No newline at end of file diff --git a/quartus workspace/src/Instruction_Decode/MemoryLoader.sv b/quartus workspace/src/Instruction_Decode/MemoryLoader.sv new file mode 100644 index 0000000..170e5f9 --- /dev/null +++ b/quartus workspace/src/Instruction_Decode/MemoryLoader.sv @@ -0,0 +1,107 @@ +`include "src/types.svh" + +module MemoryLoader +( input data_t memory_data +, input addr_t memory_address +, input logic [2:0] funct3 +, input logic [31:0] dataB +, output data_t mem_load_result +, output logic [3:0] MemWriteByteAddress +, output logic [31:0] __tmp_MemData +); + + integer byteindex; + assign byteindex = memory_address[1:0]; + + always @(*) begin + case (funct3) + 3'b000: begin // lb & sb + case (byteindex) + 2'd0: begin + mem_load_result = {{24{memory_data[7]}}, memory_data[7:0]}; + MemWriteByteAddress = 4'b0001; + __tmp_MemData = {24'b0, dataB[7:0]}; + end + 2'd1: begin + mem_load_result = {{24{memory_data[15]}}, memory_data[15:8]}; + MemWriteByteAddress = 4'b0010; + __tmp_MemData = {16'b0, dataB[7:0], 8'b0}; + end + 2'd2: begin + mem_load_result = {{24{memory_data[23]}}, memory_data[23:16]}; + MemWriteByteAddress = 4'b0100; + __tmp_MemData = {8'b0, dataB[7:0], 16'b0}; + end + 2'd3: begin + mem_load_result = {{24{memory_data[31]}}, memory_data[31:24]}; + MemWriteByteAddress = 4'b1000; + __tmp_MemData = {dataB[7:0], 24'b0}; + end + default: begin + mem_load_result = 32'hX; + MemWriteByteAddress = 4'bx; + __tmp_MemData = 32'bx; + end + endcase + end + + 3'b001: begin // lh & sh + case (byteindex) + 2'd0: begin + mem_load_result = {{16{memory_data[15]}}, memory_data[15:0]}; + MemWriteByteAddress = 4'b0011; + __tmp_MemData = {16'b0, dataB[15:0]}; + end +/* 2'd1: begin + mem_load_result = {{16{memory_data[23]}}, memory_data[23:8]}; + MemWriteByteAddress = 4'b0110; + __tmp_MemData = {8'b0, dataB[15:0], 8'b0}; + end*/ + // skip unaligned halfword access + 2'd2: begin + mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]}; + MemWriteByteAddress = 4'b1100; + __tmp_MemData = {dataB[15:0], 16'b0}; + end + default: begin + mem_load_result = 32'hX; + MemWriteByteAddress = 4'bX; + __tmp_MemData = 32'bX; + end + endcase + end + + 3'b010: begin + mem_load_result = memory_data; // lw + MemWriteByteAddress = 4'b1111; //sw + __tmp_MemData = dataB; + end + 3'b100: begin // lbu + case (byteindex) + 2'd0: mem_load_result = {24'b0, memory_data[7:0]}; + 2'd1: mem_load_result = {24'b0, memory_data[15:8]}; + 2'd2: mem_load_result = {24'b0, memory_data[23:16]}; + 2'd3: mem_load_result = {24'b0, memory_data[31:24]}; + default: mem_load_result = 32'hX; + endcase + end + + 3'b101: begin // lhu + case (byteindex) + 2'd0: mem_load_result = {16'b0, memory_data[15:0]}; + 2'd1: mem_load_result = {16'b0, memory_data[23:8]}; + 2'd2: mem_load_result = {16'b0, memory_data[31:16]}; + default: mem_load_result = 32'hX; + endcase + end + + default: begin + mem_load_result = 32'hX; + MemWriteByteAddress = 4'b0000; + __tmp_MemData = 31'bx; + end + endcase + end + + +endmodule diff --git a/quartus workspace/src/Instruction_Decode/RegisterFile.v b/quartus workspace/src/Instruction_Decode/RegisterFile.v new file mode 100644 index 0000000..f3a905c --- /dev/null +++ b/quartus workspace/src/Instruction_Decode/RegisterFile.v @@ -0,0 +1,46 @@ +//Created by Joonseo Park +//The register file holds the source and destination registers specified by instruction fields + +//REGISTERS: +//baseAddr --> holds data read line #1; the output of rs1 +//writeData --> holds data read line #2; the output of rs2 +//rs1 --> a register inside RF memory, holding base address +//rs2 --> a register inside RF memory, holding data to be written into destination register +//rd --> a register inside RF memory, holding address of register to be written into + +module registerFile + ( input [4:0] Addr1 //rs1 field (holds addr of one of 32 registers) - first source register + , input [4:0] Addr2 //rs2 field - second source register (holds data to be stored) + , input [4:0] Addr3 //rd field - desination register + , input clk + , input regWrite + , input [31:0] dataIn + , input reset + , output wire [31:0] baseAddr //data read line #1 - from first source register + , output wire [31:0] writeData //data read line #2 - from second source register + ); + + //declare 32 registers in Register File, with 32 bits each 32 bits deep (32 addresses) and 32 bits + //wide (32 bits at each register) note that RFMem[0:31] means there are 32 elements (with addr for + //each element), each of which are 32-bit regs + reg [31:0] RFMem [0:31] /* synthesis ramstyle = M10K*/; + + // x0 always 0, read out 32-bit contents of rs1 register + assign baseAddr = (Addr1 == 5'd0) ? 32'd0 : RFMem[Addr1]; + + // x0 always 0 on read, read out 32-bit contents of rs2 register + assign writeData = (Addr2 == 5'd0) ? 32'd0 : RFMem[Addr2]; + + always @(posedge clk) begin + + if (reset) RFMem[0] <= 0; + + if (regWrite && Addr3 != 0) begin + + RFMem[Addr3] <= dataIn; //write into destination register if RegWrite = 1 + + end + + end + +endmodule diff --git a/quartus workspace/src/Instruction_Decode/testInstructDecode.tcl b/quartus workspace/src/Instruction_Decode/testInstructDecode.tcl new file mode 100644 index 0000000..0685ce8 --- /dev/null +++ b/quartus workspace/src/Instruction_Decode/testInstructDecode.tcl @@ -0,0 +1,43 @@ +# create default "work" directory, where compiled Verilog goes +vlib work + +#compile all Verilog modules in project to working directory +vlog Instruction_Decode.v ControlFSM.v ALU_Decoder.v RegisterFile.v + +#load simulation with Instruction Decode as top level module +vsim Instruction_Decode + +#log all signals and add some signals to waveform window +log {/*} + +# add wave {/*} would add all items in top level simulation module +add wave {/*} + +# create clock +force {clk} 0 0ns, 1 {5 ns} -r 10ns +#10ns period clock + +force {reset} 1; + +run 20ns + +force {reset} 0; + +force {instr} 32'b11111111110001001010001100000011; #lw x6, -4(x6) + +#run 70 nanoseconds +run 70ns + +force {instr} 32'b00000000011001001010010000100011; #sw x6, 8(x9) + +run 70ns + +force {instr} 32'b00000000011000101110001000110011; #or x4, x5, x6 + +run 70ns + +force {instr} 32'b11111110010000100000101011100011; #beq x4, x4, L7 + +run 70ns + + diff --git a/quartus workspace/src/Logger.sv b/quartus workspace/src/Logger.sv new file mode 100644 index 0000000..5d2ef88 --- /dev/null +++ b/quartus workspace/src/Logger.sv @@ -0,0 +1,284 @@ +`include "src/types.svh" +`include "src/params.svh" +module Logger +( input wire clk +, input addr_t pc_cur +, input instr_t instruction +, input wire [4:0] FSM_State +, input wire [6:0] opcode +, input logic [2:0] funct3 +, input logic [6:0] funct7 +, input logic [4:0] rs1, rs2, rd +, input imm_t imm_ext +, input addr_t memory_address +, input data_t memory_data +, input wire write_enable +, input data_t rd1, rd2, result +, input wire regWrite +); + + integer cycle = 32'h0; + string operation = "unknown"; + string source_register1 = "unkown"; + string source_register2 = "unknown"; + string destination_register = "unknown"; + string complete_instruction = "unknown"; + data_t new_pc; + + assign new_pc = pc_cur + imm_ext + 'h4; + + always @(posedge clk) begin + // Display the high-level PC and instruction information + $display("Cycle %d: \nPC: %08h \nInstruction (Hex): %08h", cycle, pc_cur, instruction); + + // Determine which FSM State we are in + case (FSM_State) + 5'b00000: $display("FSM State: FETCH"); + 5'b00001: $display("FSM State: DECODE"); + 5'b00010: $display("FSM State: EXECUTER"); + 5'b00011: $display("FSM State: UNCONDJUMP"); + 5'b00100: $display("FSM State: EXECUTEI"); + 5'b00101: $display("FSM State: MEMADR"); + 5'b00110: $display("FSM State: ALUWB"); + 5'b00111: $display("FSM State: MEMWRITE"); + 5'b01000: $display("FSM State: MEMREAD"); + 5'b01001: $display("FSM State: MEMWB"); + 5'b01010: $display("FSM State: BRANCHIFEQ"); + 5'b01011: $display("FSM State: LUI"); + 5'b01100: $display("FSM State: AUIPC"); + 5'b01101: $display("FSM State: JALR_CALC"); + 5'b01110: $display("FSM State: JALR_STEP2"); + 5'b01111: $display("FSM State: BRANCHCOMP"); + endcase + + // Parse the instruction we are executing + case (opcode) + RType: begin + case (funct3) + 3'b000: begin + case (funct7) + 7'h00: operation = "add"; + 7'h20: operation = "sub"; + endcase + end + 3'b001: operation = "sll"; + 3'b010: operation = "slt"; + 3'b011: operation = "sltu"; + 3'b100: operation = "xor"; + 3'b101: begin + case (funct7) + 7'h00: operation = "srl"; + 7'h20: operation = "sra"; + endcase + end + 3'b110: operation = "or"; + 3'b111: operation = "and"; + endcase + end + + IType_logic: begin + case (funct3) + 3'b000: operation = "addi"; + 3'b001: operation = "slli"; + 3'b010: operation = "slti"; + 3'b011: operation = "sltiu"; + 3'b100: operation = "xori"; + 3'b101: begin + case (funct7) + 7'h00: operation = "srli"; + 7'h20: operation = "srai"; + endcase + end + 3'b110: operation = "ori"; + 3'b111: operation = "andi"; + endcase + end + + IType_load: begin + case (funct3) + 3'b000: operation = "lb"; + 3'b001: operation = "lh"; + 3'b010: operation = "lw"; + 3'b100: operation = "lbu"; + 3'b101: operation = "lhu"; + endcase + end + + SType: begin + case (funct3) + 3'b000: operation = "sb"; + 3'b001: operation = "sh"; + 3'b010: operation = "sw"; + endcase + end + + BType: begin + case (funct3) + 3'b000: operation = "beq"; + 3'b001: operation = "bne"; + 3'b100: operation = "blt"; + 3'b101: operation = "bge"; + 3'b110: operation = "bltu"; + 3'b111: operation = "bgeu"; + endcase + end + + JType: operation = "jal"; + UType_auipc: operation = "auipc"; + UType_lui: operation = "lui"; + IType_jalr: operation = "jalr"; + default: operation = "unknown"; + endcase + + // Parse register names + case (rs1) + 5'b00000: source_register1 = "zero"; + 5'b00001: source_register1 = "ra"; + 5'b00010: source_register1 = "sp"; + 5'b00011: source_register1 = "gp"; + 5'b00100: source_register1 = "tp"; + 5'b00101: source_register1 = "t0"; + 5'b00110: source_register1 = "t1"; + 5'b00111: source_register1 = "t2"; + 5'b01000: source_register1 = "s0"; + 5'b01001: source_register1 = "s1"; + 5'b01010: source_register1 = "a0"; + 5'b01011: source_register1 = "a1"; + 5'b01100: source_register1 = "a2"; + 5'b01101: source_register1 = "a3"; + 5'b01110: source_register1 = "a4"; + 5'b01111: source_register1 = "a5"; + 5'b10000: source_register1 = "a6"; + 5'b10001: source_register1 = "a7"; + 5'b10010: source_register1 = "s2"; + 5'b10011: source_register1 = "s3"; + 5'b10100: source_register1 = "s4"; + 5'b10101: source_register1 = "s5"; + 5'b10110: source_register1 = "s6"; + 5'b10111: source_register1 = "s7"; + 5'b11000: source_register1 = "s8"; + 5'b11001: source_register1 = "s9"; + 5'b11010: source_register1 = "s10"; + 5'b11011: source_register1 = "s11"; + 5'b11100: source_register1 = "t3"; + 5'b11101: source_register1 = "t4"; + 5'b11110: source_register1 = "t5"; + 5'b11111: source_register1 = "t6"; + endcase + + case (rs2) + 5'b00000: source_register2 = "zero"; + 5'b00001: source_register2 = "ra"; + 5'b00010: source_register2 = "sp"; + 5'b00011: source_register2 = "gp"; + 5'b00100: source_register2 = "tp"; + 5'b00101: source_register2 = "t0"; + 5'b00110: source_register2 = "t1"; + 5'b00111: source_register2 = "t2"; + 5'b01000: source_register2 = "s0"; + 5'b01001: source_register2 = "s1"; + 5'b01010: source_register2 = "a0"; + 5'b01011: source_register2 = "a1"; + 5'b01100: source_register2 = "a2"; + 5'b01101: source_register2 = "a3"; + 5'b01110: source_register2 = "a4"; + 5'b01111: source_register2 = "a5"; + 5'b10000: source_register2 = "a6"; + 5'b10001: source_register2 = "a7"; + 5'b10010: source_register2 = "s2"; + 5'b10011: source_register2 = "s3"; + 5'b10100: source_register2 = "s4"; + 5'b10101: source_register2 = "s5"; + 5'b10110: source_register2 = "s6"; + 5'b10111: source_register2 = "s7"; + 5'b11000: source_register2 = "s8"; + 5'b11001: source_register2 = "s9"; + 5'b11010: source_register2 = "s10"; + 5'b11011: source_register2 = "s11"; + 5'b11100: source_register2 = "t3"; + 5'b11101: source_register2 = "t4"; + 5'b11110: source_register2 = "t5"; + 5'b11111: source_register2 = "t6"; + endcase + + case (rd) + 5'b00000: destination_register = "zero"; + 5'b00001: destination_register = "ra"; + 5'b00010: destination_register = "sp"; + 5'b00011: destination_register = "gp"; + 5'b00100: destination_register = "tp"; + 5'b00101: destination_register = "t0"; + 5'b00110: destination_register = "t1"; + 5'b00111: destination_register = "t2"; + 5'b01000: destination_register = "s0"; + 5'b01001: destination_register = "s1"; + 5'b01010: destination_register = "a0"; + 5'b01011: destination_register = "a1"; + 5'b01100: destination_register = "a2"; + 5'b01101: destination_register = "a3"; + 5'b01110: destination_register = "a4"; + 5'b01111: destination_register = "a5"; + 5'b10000: destination_register = "a6"; + 5'b10001: destination_register = "a7"; + 5'b10010: destination_register = "s2"; + 5'b10011: destination_register = "s3"; + 5'b10100: destination_register = "s4"; + 5'b10101: destination_register = "s5"; + 5'b10110: destination_register = "s6"; + 5'b10111: destination_register = "s7"; + 5'b11000: destination_register = "s8"; + 5'b11001: destination_register = "s9"; + 5'b11010: destination_register = "s10"; + 5'b11011: destination_register = "s11"; + 5'b11100: destination_register = "t3"; + 5'b11101: destination_register = "t4"; + 5'b11110: destination_register = "t5"; + 5'b11111: destination_register = "t6"; + endcase + + // Construct the instruction to display + case (opcode) + RType: complete_instruction = {operation, " ", destination_register, ", ", source_register1, ", ", source_register2}; + IType_logic: complete_instruction = {operation, " ", destination_register, ", ", source_register1, ", 0x", $sformatf("%08h", imm_ext)}; + IType_load: complete_instruction = {operation, " ", destination_register, ", ", $sformatf("%0d", imm_ext), "(", source_register1, ")"}; + SType: complete_instruction = {operation, " ", source_register2, ", ", $sformatf("%0d", imm_ext), "(", source_register1, ")"}; + BType: complete_instruction = {operation, " ", source_register1, ", ", source_register2, ", 0x", $sformatf("%08h", new_pc)}; + JType: complete_instruction = {operation, " ", destination_register, ", 0x", $sformatf("%08h", new_pc)}; + UType_auipc: complete_instruction = {operation, " ", destination_register, ", 0x", $sformatf("%08h", imm_ext)}; + UType_lui: complete_instruction = {operation, " ", destination_register, ", 0x", $sformatf("%08h", imm_ext)}; + IType_jalr: complete_instruction = {operation, " ", destination_register, ", ", source_register1, ", 0x", $sformatf("%08h", new_pc)}; + default: complete_instruction = "unknown"; + endcase + + // Display the parsed instruction + $display("Parsed Instruction: %s", complete_instruction); + + // Display the value read from memory + $display("Read Memory Address: 0x%08h", memory_address, " Value: 0x%08h", memory_data); + + // If data is being written, display what and where + if (write_enable) begin + $display("Write Memory Address: 0x%08h", memory_address, " Value: 0x%08h", memory_data); + end + + // Display values read from register file + if (rs1 != 5'b00000) begin + $display("Read Register: %s", source_register1, " Value: 0x%08h", rd1); + end + + if (rs2 != 5'b00000) begin + $display("Read Register: %s", source_register2, " Value: 0x%08h", rd2); + end + + // If data is being written to register, display what and where + if (regWrite && rd != 5'b00000) begin + $display("Write Register: %s", destination_register, " Value: 0x%08h", result); + end + + // Include new line to separate log into packets + $display("\n"); + + cycle = cycle + 1'b1; + end + +endmodule diff --git a/quartus workspace/src/fetch.sv b/quartus workspace/src/fetch.sv new file mode 100644 index 0000000..a83c304 --- /dev/null +++ b/quartus workspace/src/fetch.sv @@ -0,0 +1,45 @@ +// module for fetching instructions +// +// concerns itself with reading instruction from the instruction memory, as well as managing the +// program counter (PC); implemented as a Moore FSM +// + +`include "src/utils.svh" +`include "src/types.svh" + +module fetch + ( input wire clk + , input wire reset + , input wire cfsm__pc_update + , input pc_src_t cfsm__pc_src + , input wire cfsm__ir_write + , input addr_t alu_result_for_pc + , input imm_t imm_ext + , output addr_t pc_cur + , output addr_t pc_old + ); + + addr_t pc_next; + + always @ (*) begin + if (cfsm__pc_update) begin + case (cfsm__pc_src) + PC_SRC__INCREMENT: pc_next <= pc_cur + 32'h4; + PC_SRC__JUMP: pc_next <= pc_old + imm_ext; + PC_SRC__ALU_RESULT: pc_next <= {alu_result_for_pc[31:1], 1'b0}; + endcase + end else begin + pc_next <= pc_cur; + end + end + + always @ (posedge clk) begin + if (reset) pc_cur <= 32'h00000000; + else pc_cur <= pc_next; + + if (cfsm__ir_write) begin + pc_old <= pc_cur; + end + end + +endmodule diff --git a/quartus workspace/src/params.svh b/quartus workspace/src/params.svh new file mode 100644 index 0000000..da127cc --- /dev/null +++ b/quartus workspace/src/params.svh @@ -0,0 +1,28 @@ +`ifndef PARAMS_VH +`define PARAMS_VH + +// Opcodes +parameter RType = 7'b0110011; +parameter IType_logic = 7'b0010011; +parameter IType_load = 7'b0000011; +parameter SType = 7'b0100011; +parameter BType = 7'b1100011; +parameter JType = 7'b1101111; +parameter UType_auipc = 7'b0010111; +parameter UType_lui = 7'b0110111; +parameter IType_jalr = 7'b1100111; +parameter FENCE = 7'b0001111; + +//ALU Operation Control Codes +parameter ALUAdd = 4'b0000; +parameter ALUSub = 4'b0001; +parameter ALUSLL = 4'b0010; +parameter ALUSLT = 4'b0011; +parameter ALUSLTU = 4'b0100; +parameter ALUXOR = 4'b0101; +parameter ALUSRL = 4'b0110; +parameter ALUSRA = 4'b0111; +parameter ALUOR = 4'b1000; +parameter ALUAND = 4'b1001; + +`endif // PARAMS_VH diff --git a/quartus workspace/src/types.svh b/quartus workspace/src/types.svh new file mode 100644 index 0000000..963274a --- /dev/null +++ b/quartus workspace/src/types.svh @@ -0,0 +1,66 @@ +`ifndef TYPES_VH +`define TYPES_VH + +/* defines the bitness of the processor */ +`define PROCESSOR_BITNESS 32 + +typedef logic [`PROCESSOR_BITNESS -1:0] instr_t; +typedef logic [`PROCESSOR_BITNESS -1:0] addr_t; +typedef logic [`PROCESSOR_BITNESS -1:0] imm_t; +typedef logic [`PROCESSOR_BITNESS -1:0] data_t; + +typedef logic [6:0] opcode_t; + +// based on table 7.2 of digital design and computer architecture book +typedef enum logic [1:0] + { ALU_OP__ADD = 2'b00 + , ALU_OP__BRANCH = 2'b01 + , ALU_OP__REGISTER_OPERATION = 2'b10 + + // default value to use when alu op is not to be relied on + , ALU_OP__UNSET = 2'b11 + } alu_op_t; + +// represents the possible input sources for the first operand of the ALU as selected by the Control +// FSM; See Figure 7.46 of digital design and computer architecture book +typedef enum logic [1:0] + { ALU_SRC_A__PC = 2'b00 + , ALU_SRC_A__OLD_PC = 2'b01 + , ALU_SRC_A__RD1 = 2'b10 + , ALU_SRC_A__ZERO = 2'b11 + + , ALU_SRC_A__UNSET = 2'bxx + } alu_src_a_t; + +// represents the possible input sources for the second operand of the ALU as selected by the +// Control FSM; See Figure 7.46 of digital design and computer architecture book +typedef enum logic [1:0] + { ALU_SRC_B__RD2 = 2'b00 + , ALU_SRC_B__IMM_EXT = 2'b01 + , ALU_SRC_B__4 = 2'b10 + + , ALU_SRC_B__UNSET = 2'b11 + } alu_src_b_t; + +// represents the possible input sources of the address for memory access as selected by the Control +// FSM; See Figure 7.22 of the digital disgn and computer architecture book +typedef enum logic + { ADR_SRC__PC = 1'b0 + , ADR_SRC__RESULT = 1'b1 + } adr_src_t; + +// represents the possible sources of the result fed into PC, RF, or memory as selected by the +// Control FSM; See Figure 7.46 of the digital design and computer architecture book +typedef enum logic [1:0] + { RESULT_SRC__ALU_OUT = 2'b00 + , RESULT_SRC__DATA = 2'b01 + , RESULT_SRC__ALU_RESULT = 2'b10 + } result_src_t; + +typedef enum logic [1:0] + { PC_SRC__INCREMENT = 2'b00 + , PC_SRC__JUMP = 2'b01 + , PC_SRC__ALU_RESULT = 2'b10 + } pc_src_t; + +`endif diff --git a/quartus workspace/src/utils.svh b/quartus workspace/src/utils.svh new file mode 100644 index 0000000..b3f65d4 --- /dev/null +++ b/quartus workspace/src/utils.svh @@ -0,0 +1,7 @@ +`ifndef UTILS_VH +`define UTILS_VH + +`define TRUE 1'b1 +`define FALSE 1'b0 + +`endif diff --git a/quartus workspace/src/utils/register.sv b/quartus workspace/src/utils/register.sv new file mode 100644 index 0000000..b7c7b0f --- /dev/null +++ b/quartus workspace/src/utils/register.sv @@ -0,0 +1,20 @@ +/* Generic register module */ + +module register #( type DATA_TYPE ) + ( input wire clk + , input wire reset + , input wire en + , input wire [31:0] data_in + , output reg [31:0] data_out + ); + + always @(posedge clk) begin + if (reset) begin + data_out <= 32'b0; + end + else + if (en) begin + data_out <= data_in; + end + end +endmodule diff --git a/quartus workspace/src/utoss_riscv.sv b/quartus workspace/src/utoss_riscv.sv new file mode 100644 index 0000000..deeeba0 --- /dev/null +++ b/quartus workspace/src/utoss_riscv.sv @@ -0,0 +1,213 @@ +`include "src/types.svh" + +module utoss_riscv + ( input wire clk + , input wire reset + + // memory interface begin + , output addr_t memory__address + , output data_t memory__write_data + , output logic [3:0] memory__write_enable + , input data_t memory__read_data + // memory interface end + ); + + wire cfsm__pc_update; + wire cfsm__reg_write; + wire cfsm__ir_write; + pc_src_t cfsm__pc_src; + result_src_t cfsm__result_src; + + addr_t pc_cur; + data_t data; + instr_t instruction; + opcode_t opcode; + imm_t imm_ext; + reg [2:0] funct3; + reg [6:0] funct7; + + integer byteindex; + + data_t result; + data_t mem_load_result; + + data_t rd1; + data_t rd2; + + data_t alu_input_a; + data_t alu_input_b; + data_t alu_result; + data_t alu_out; + + addr_t pc_old; + + wire alu__zero_flag; + + adr_src_t cfsm__adr_src; + wire __tmp_Branch; + wire [1:0] __tmp_ALUSrcA, __tmp_ALUSrcB; + wire [3:0] __tmp_ALUControl; + wire [1:0] __tmp_ResultSrc; + wire [4:0] __tmp_FSMState; + data_t dataA, dataB; + reg [4:0] rd, rs1, rs2; + + logic [3:0] MemWriteByteAddress; + + ControlFSM control_fsm + ( .opcode ( opcode ) + , .clk ( clk ) + , .reset ( reset ) + , .zero_flag ( alu__zero_flag ) + , .MemWriteByteAddress ( MemWriteByteAddress ) + , .funct3 ( funct3 ) + , .alu_result ( alu_result ) + , .AdrSrc ( cfsm__adr_src ) + , .IRWrite ( cfsm__ir_write ) + , .RegWrite ( cfsm__reg_write ) + , .PCUpdate ( cfsm__pc_update ) + , .pc_src ( cfsm__pc_src ) + , .MemWrite ( memory__write_enable ) + , .Branch ( __tmp_Branch ) + , .ALUSrcA ( __tmp_ALUSrcA ) + , .ALUSrcB ( __tmp_ALUSrcB ) + , .ResultSrc ( cfsm__result_src ) + , .FSMState ( __tmp_FSMState ) + ); + + fetch fetch + ( .clk ( clk ) + , .reset ( reset ) + , .cfsm__pc_update ( cfsm__pc_update ) + , .alu_result_for_pc ( alu_out ) + , .cfsm__pc_src ( cfsm__pc_src ) + , .cfsm__ir_write ( cfsm__ir_write ) + , .imm_ext ( imm_ext ) + + // outputs + , .pc_cur ( pc_cur ) + , .pc_old ( pc_old ) + ); + + always @(*) begin + case (cfsm__adr_src) + ADR_SRC__PC: memory__address = pc_cur; + ADR_SRC__RESULT: memory__address = result; + endcase + end + + always @(posedge clk) begin + if (cfsm__ir_write) begin + instruction <= memory__read_data; + end + end + + MemoryLoader MemLoad + ( .memory_data ( memory__read_data ) + , .memory_address ( memory__address ) + , .mem_load_result ( mem_load_result ) + , .funct3 ( funct3 ) + , .dataB ( dataB ) + , .MemWriteByteAddress ( MemWriteByteAddress ) + , .__tmp_MemData ( memory__write_data ) + ); + + always @(posedge clk) begin + data <= mem_load_result; + end + + Instruction_Decode instruction_decode + ( .instr ( instruction ) + , .opcode ( opcode ) + , .funct3 ( funct3 ) + , .funct7 ( funct7 ) + , .ALUControl ( __tmp_ALUControl ) + , .imm_ext ( imm_ext ) + , .rd ( rd ) + , .rs1 ( rs1 ) + , .rs2 ( rs2 ) + ); + + registerFile RegFile + ( .Addr1 ( rs1 ) + , .Addr2 ( rs2 ) + , .Addr3 ( rd ) + , .clk ( clk ) + , .reset ( reset ) + , .regWrite ( cfsm__reg_write ) + , .dataIn ( result ) + , .baseAddr ( rd1 ) + , .writeData ( rd2 ) + ); + + ALU alu + ( .a ( alu_input_a ) + , .b ( alu_input_b ) + , .alu_control ( __tmp_ALUControl ) + , .out ( alu_result ) + , .zeroE ( alu__zero_flag ) + ); + + always @(posedge clk) begin + alu_out <= alu_result; + end + + always @(*) begin + case (__tmp_ALUSrcA) + ALU_SRC_A__PC: alu_input_a = pc_cur; + ALU_SRC_A__OLD_PC: alu_input_a = pc_old; + ALU_SRC_A__RD1: alu_input_a = dataA; + ALU_SRC_A__ZERO: alu_input_a = 32'b0; + + default: alu_input_a = 32'hxxxxxxxx; + endcase + end + + always @(*) begin + case (__tmp_ALUSrcB) + ALU_SRC_B__RD2: alu_input_b = dataB; + ALU_SRC_B__IMM_EXT: alu_input_b = imm_ext; + ALU_SRC_B__4: alu_input_b = 32'd4; + default: alu_input_b = 32'hxxxxxxxx; + endcase + end + + always @(*) begin + case (cfsm__result_src) + RESULT_SRC__ALU_OUT: result = alu_out; + RESULT_SRC__DATA: result = data; + RESULT_SRC__ALU_RESULT: result = alu_result; + default: result = 32'hxxxxxxxx; + endcase + end + + always @(posedge clk) begin + dataA <= rd1; + dataB <= rd2; + end + +`ifndef UTOSS_RISCV_SYNTHESIS + Logger CoreLog + ( + .clk ( clk ) + , .pc_cur ( pc_cur ) + , .instruction ( instruction ) + , .FSM_State ( __tmp_FSMState ) + , .opcode ( opcode ) + , .funct3 ( funct3 ) + , .funct7 ( funct7 ) + , .rs1 ( rs1 ) + , .rs2 ( rs2 ) + , .rd ( rd ) + , .imm_ext ( imm_ext ) + , .memory_address ( memory__address ) + , .memory_data ( mem_load_result ) + , .write_enable ( memory__write_enable ) + , .rd1 ( rd1 ) + , .rd2 ( rd2 ) + , .result ( result ) + , .regWrite ( cfsm__reg_write ) + ); +`endif + +endmodule diff --git a/quartus workspace/top.qpf b/quartus workspace/top.qpf new file mode 100644 index 0000000..2e344c1 --- /dev/null +++ b/quartus workspace/top.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2023 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition +# Date created = 19:54:22 November 25, 2025 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "22.1" +DATE = "19:54:22 November 25, 2025" + +# Revisions + +PROJECT_REVISION = "top" diff --git a/quartus workspace/top.qsf b/quartus workspace/top.qsf new file mode 100644 index 0000000..9414f44 --- /dev/null +++ b/quartus workspace/top.qsf @@ -0,0 +1,341 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2023 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition +# Date created = 19:54:22 November 25, 2025 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA5F31C6 +set_global_assignment -name TOP_LEVEL_ENTITY top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:54:22 NOVEMBER 25, 2025" +set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "DE1-SoC Board" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_AJ4 -to ADC_CS_N +set_location_assignment PIN_AK4 -to ADC_DIN +set_location_assignment PIN_AK3 -to ADC_DOUT +set_location_assignment PIN_AK2 -to ADC_SCLK +set_location_assignment PIN_K7 -to AUD_ADCDAT +set_location_assignment PIN_K8 -to AUD_ADCLRCK +set_location_assignment PIN_H7 -to AUD_BCLK +set_location_assignment PIN_J7 -to AUD_DACDAT +set_location_assignment PIN_H8 -to AUD_DACLRCK +set_location_assignment PIN_G7 -to AUD_XCK +set_location_assignment PIN_AF14 -to CLOCK_50 +set_location_assignment PIN_AA16 -to CLOCK2_50 +set_location_assignment PIN_Y26 -to CLOCK3_50 +set_location_assignment PIN_K14 -to CLOCK4_50 +set_location_assignment PIN_AK14 -to DRAM_ADDR[0] +set_location_assignment PIN_AH14 -to DRAM_ADDR[1] +set_location_assignment PIN_AG15 -to DRAM_ADDR[2] +set_location_assignment PIN_AE14 -to DRAM_ADDR[3] +set_location_assignment PIN_AB15 -to DRAM_ADDR[4] +set_location_assignment PIN_AC14 -to DRAM_ADDR[5] +set_location_assignment PIN_AD14 -to DRAM_ADDR[6] +set_location_assignment PIN_AF15 -to DRAM_ADDR[7] +set_location_assignment PIN_AH15 -to DRAM_ADDR[8] +set_location_assignment PIN_AG13 -to DRAM_ADDR[9] +set_location_assignment PIN_AG12 -to DRAM_ADDR[10] +set_location_assignment PIN_AH13 -to DRAM_ADDR[11] +set_location_assignment PIN_AJ14 -to DRAM_ADDR[12] +set_location_assignment PIN_AF13 -to DRAM_BA[0] +set_location_assignment PIN_AJ12 -to DRAM_BA[1] +set_location_assignment PIN_AF11 -to DRAM_CAS_N +set_location_assignment PIN_AK13 -to DRAM_CKE +set_location_assignment PIN_AH12 -to DRAM_CLK +set_location_assignment PIN_AG11 -to DRAM_CS_N +set_location_assignment PIN_AK6 -to DRAM_DQ[0] +set_location_assignment PIN_AJ7 -to DRAM_DQ[1] +set_location_assignment PIN_AK7 -to DRAM_DQ[2] +set_location_assignment PIN_AK8 -to DRAM_DQ[3] +set_location_assignment PIN_AK9 -to DRAM_DQ[4] +set_location_assignment PIN_AG10 -to DRAM_DQ[5] +set_location_assignment PIN_AK11 -to DRAM_DQ[6] +set_location_assignment PIN_AJ11 -to DRAM_DQ[7] +set_location_assignment PIN_AH10 -to DRAM_DQ[8] +set_location_assignment PIN_AJ10 -to DRAM_DQ[9] +set_location_assignment PIN_AJ9 -to DRAM_DQ[10] +set_location_assignment PIN_AH9 -to DRAM_DQ[11] +set_location_assignment PIN_AH8 -to DRAM_DQ[12] +set_location_assignment PIN_AH7 -to DRAM_DQ[13] +set_location_assignment PIN_AJ6 -to DRAM_DQ[14] +set_location_assignment PIN_AJ5 -to DRAM_DQ[15] +set_location_assignment PIN_AB13 -to DRAM_LDQM +set_location_assignment PIN_AE13 -to DRAM_RAS_N +set_location_assignment PIN_AK12 -to DRAM_UDQM +set_location_assignment PIN_AA13 -to DRAM_WE_N +set_location_assignment PIN_AA12 -to FAN_CTRL +set_location_assignment PIN_J12 -to FPGA_I2C_SCLK +set_location_assignment PIN_K12 -to FPGA_I2C_SDAT +set_location_assignment PIN_AC18 -to GPIO_0[0] +set_location_assignment PIN_AH18 -to GPIO_0[10] +set_location_assignment PIN_AH17 -to GPIO_0[11] +set_location_assignment PIN_AG16 -to GPIO_0[12] +set_location_assignment PIN_AE16 -to GPIO_0[13] +set_location_assignment PIN_AF16 -to GPIO_0[14] +set_location_assignment PIN_AG17 -to GPIO_0[15] +set_location_assignment PIN_AA18 -to GPIO_0[16] +set_location_assignment PIN_AA19 -to GPIO_0[17] +set_location_assignment PIN_AE17 -to GPIO_0[18] +set_location_assignment PIN_AC20 -to GPIO_0[19] +set_location_assignment PIN_Y17 -to GPIO_0[1] +set_location_assignment PIN_AH19 -to GPIO_0[20] +set_location_assignment PIN_AJ20 -to GPIO_0[21] +set_location_assignment PIN_AH20 -to GPIO_0[22] +set_location_assignment PIN_AK21 -to GPIO_0[23] +set_location_assignment PIN_AD19 -to GPIO_0[24] +set_location_assignment PIN_AD20 -to GPIO_0[25] +set_location_assignment PIN_AE18 -to GPIO_0[26] +set_location_assignment PIN_AE19 -to GPIO_0[27] +set_location_assignment PIN_AF20 -to GPIO_0[28] +set_location_assignment PIN_AF21 -to GPIO_0[29] +set_location_assignment PIN_AD17 -to GPIO_0[2] +set_location_assignment PIN_AF19 -to GPIO_0[30] +set_location_assignment PIN_AG21 -to GPIO_0[31] +set_location_assignment PIN_AF18 -to GPIO_0[32] +set_location_assignment PIN_AG20 -to GPIO_0[33] +set_location_assignment PIN_AG18 -to GPIO_0[34] +set_location_assignment PIN_AJ21 -to GPIO_0[35] +set_location_assignment PIN_Y18 -to GPIO_0[3] +set_location_assignment PIN_AK16 -to GPIO_0[4] +set_location_assignment PIN_AK18 -to GPIO_0[5] +set_location_assignment PIN_AK19 -to GPIO_0[6] +set_location_assignment PIN_AJ19 -to GPIO_0[7] +set_location_assignment PIN_AJ17 -to GPIO_0[8] +set_location_assignment PIN_AJ16 -to GPIO_0[9] +set_location_assignment PIN_AB17 -to GPIO_1[0] +set_location_assignment PIN_AG26 -to GPIO_1[10] +set_location_assignment PIN_AH24 -to GPIO_1[11] +set_location_assignment PIN_AH27 -to GPIO_1[12] +set_location_assignment PIN_AJ27 -to GPIO_1[13] +set_location_assignment PIN_AK29 -to GPIO_1[14] +set_location_assignment PIN_AK28 -to GPIO_1[15] +set_location_assignment PIN_AK27 -to GPIO_1[16] +set_location_assignment PIN_AJ26 -to GPIO_1[17] +set_location_assignment PIN_AK26 -to GPIO_1[18] +set_location_assignment PIN_AH25 -to GPIO_1[19] +set_location_assignment PIN_AA21 -to GPIO_1[1] +set_location_assignment PIN_AJ25 -to GPIO_1[20] +set_location_assignment PIN_AJ24 -to GPIO_1[21] +set_location_assignment PIN_AK24 -to GPIO_1[22] +set_location_assignment PIN_AG23 -to GPIO_1[23] +set_location_assignment PIN_AK23 -to GPIO_1[24] +set_location_assignment PIN_AH23 -to GPIO_1[25] +set_location_assignment PIN_AK22 -to GPIO_1[26] +set_location_assignment PIN_AJ22 -to GPIO_1[27] +set_location_assignment PIN_AH22 -to GPIO_1[28] +set_location_assignment PIN_AG22 -to GPIO_1[29] +set_location_assignment PIN_AB21 -to GPIO_1[2] +set_location_assignment PIN_AF24 -to GPIO_1[30] +set_location_assignment PIN_AF23 -to GPIO_1[31] +set_location_assignment PIN_AE22 -to GPIO_1[32] +set_location_assignment PIN_AD21 -to GPIO_1[33] +set_location_assignment PIN_AA20 -to GPIO_1[34] +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AC23 -to GPIO_1[3] +set_location_assignment PIN_AD24 -to GPIO_1[4] +set_location_assignment PIN_AE23 -to GPIO_1[5] +set_location_assignment PIN_AE24 -to GPIO_1[6] +set_location_assignment PIN_AF25 -to GPIO_1[7] +set_location_assignment PIN_AF26 -to GPIO_1[8] +set_location_assignment PIN_AG25 -to GPIO_1[9] +set_location_assignment PIN_AE26 -to HEX0[0] +set_location_assignment PIN_AE27 -to HEX0[1] +set_location_assignment PIN_AE28 -to HEX0[2] +set_location_assignment PIN_AG27 -to HEX0[3] +set_location_assignment PIN_AF28 -to HEX0[4] +set_location_assignment PIN_AG28 -to HEX0[5] +set_location_assignment PIN_AH28 -to HEX0[6] +set_location_assignment PIN_AJ29 -to HEX1[0] +set_location_assignment PIN_AH29 -to HEX1[1] +set_location_assignment PIN_AH30 -to HEX1[2] +set_location_assignment PIN_AG30 -to HEX1[3] +set_location_assignment PIN_AF29 -to HEX1[4] +set_location_assignment PIN_AF30 -to HEX1[5] +set_location_assignment PIN_AD27 -to HEX1[6] +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_AE29 -to HEX2[1] +set_location_assignment PIN_AD29 -to HEX2[2] +set_location_assignment PIN_AC28 -to HEX2[3] +set_location_assignment PIN_AD30 -to HEX2[4] +set_location_assignment PIN_AC29 -to HEX2[5] +set_location_assignment PIN_AC30 -to HEX2[6] +set_location_assignment PIN_AD26 -to HEX3[0] +set_location_assignment PIN_AC27 -to HEX3[1] +set_location_assignment PIN_AD25 -to HEX3[2] +set_location_assignment PIN_AC25 -to HEX3[3] +set_location_assignment PIN_AB28 -to HEX3[4] +set_location_assignment PIN_AB25 -to HEX3[5] +set_location_assignment PIN_AB22 -to HEX3[6] +set_location_assignment PIN_AA24 -to HEX4[0] +set_location_assignment PIN_Y23 -to HEX4[1] +set_location_assignment PIN_Y24 -to HEX4[2] +set_location_assignment PIN_W22 -to HEX4[3] +set_location_assignment PIN_W24 -to HEX4[4] +set_location_assignment PIN_V23 -to HEX4[5] +set_location_assignment PIN_W25 -to HEX4[6] +set_location_assignment PIN_V25 -to HEX5[0] +set_location_assignment PIN_AA28 -to HEX5[1] +set_location_assignment PIN_Y27 -to HEX5[2] +set_location_assignment PIN_AB27 -to HEX5[3] +set_location_assignment PIN_AB26 -to HEX5[4] +set_location_assignment PIN_AA26 -to HEX5[5] +set_location_assignment PIN_AA25 -to HEX5[6] +set_location_assignment PIN_AA30 -to IRDA_RXD +set_location_assignment PIN_AB30 -to IRDA_TXD +set_location_assignment PIN_AA14 -to KEY[0] +set_location_assignment PIN_AA15 -to KEY[1] +set_location_assignment PIN_W15 -to KEY[2] +set_location_assignment PIN_Y16 -to KEY[3] +set_location_assignment PIN_V16 -to LEDR[0] +set_location_assignment PIN_W16 -to LEDR[1] +set_location_assignment PIN_V17 -to LEDR[2] +set_location_assignment PIN_V18 -to LEDR[3] +set_location_assignment PIN_W17 -to LEDR[4] +set_location_assignment PIN_W19 -to LEDR[5] +set_location_assignment PIN_Y19 -to LEDR[6] +set_location_assignment PIN_W20 -to LEDR[7] +set_location_assignment PIN_W21 -to LEDR[8] +set_location_assignment PIN_Y21 -to LEDR[9] +set_location_assignment PIN_AD7 -to PS2_CLK +set_location_assignment PIN_AE7 -to PS2_DAT +set_location_assignment PIN_AD9 -to PS2_CLK2 +set_location_assignment PIN_AE9 -to PS2_DAT2 +set_location_assignment PIN_AB12 -to SW[0] +set_location_assignment PIN_AC12 -to SW[1] +set_location_assignment PIN_AF9 -to SW[2] +set_location_assignment PIN_AF10 -to SW[3] +set_location_assignment PIN_AD11 -to SW[4] +set_location_assignment PIN_AD12 -to SW[5] +set_location_assignment PIN_AE11 -to SW[6] +set_location_assignment PIN_AC9 -to SW[7] +set_location_assignment PIN_AD10 -to SW[8] +set_location_assignment PIN_AE12 -to SW[9] +set_location_assignment PIN_H15 -to TD_CLK27 +set_location_assignment PIN_D2 -to TD_DATA[0] +set_location_assignment PIN_B1 -to TD_DATA[1] +set_location_assignment PIN_E2 -to TD_DATA[2] +set_location_assignment PIN_B2 -to TD_DATA[3] +set_location_assignment PIN_D1 -to TD_DATA[4] +set_location_assignment PIN_E1 -to TD_DATA[5] +set_location_assignment PIN_C2 -to TD_DATA[6] +set_location_assignment PIN_B3 -to TD_DATA[7] +set_location_assignment PIN_A5 -to TD_HS +set_location_assignment PIN_F6 -to TD_RESET_N +set_location_assignment PIN_A3 -to TD_VS +set_location_assignment PIN_AF4 -to USB_B2_CLK +set_location_assignment PIN_AH4 -to USB_B2_DATA[0] +set_location_assignment PIN_AH3 -to USB_B2_DATA[1] +set_location_assignment PIN_AJ2 -to USB_B2_DATA[2] +set_location_assignment PIN_AJ1 -to USB_B2_DATA[3] +set_location_assignment PIN_AH2 -to USB_B2_DATA[4] +set_location_assignment PIN_AG3 -to USB_B2_DATA[5] +set_location_assignment PIN_AG2 -to USB_B2_DATA[6] +set_location_assignment PIN_AG1 -to USB_B2_DATA[7] +set_location_assignment PIN_AF5 -to USB_EMPTY +set_location_assignment PIN_AG5 -to USB_FULL +set_location_assignment PIN_AF6 -to USB_OE_N +set_location_assignment PIN_AG6 -to USB_RD_N +set_location_assignment PIN_AG7 -to USB_RESET_N +set_location_assignment PIN_AG8 -to USB_SCL +set_location_assignment PIN_AF8 -to USB_SDA +set_location_assignment PIN_AH5 -to USB_WR_N +set_location_assignment PIN_B13 -to VGA_B[0] +set_location_assignment PIN_G13 -to VGA_B[1] +set_location_assignment PIN_H13 -to VGA_B[2] +set_location_assignment PIN_F14 -to VGA_B[3] +set_location_assignment PIN_H14 -to VGA_B[4] +set_location_assignment PIN_F15 -to VGA_B[5] +set_location_assignment PIN_G15 -to VGA_B[6] +set_location_assignment PIN_J14 -to VGA_B[7] +set_location_assignment PIN_F10 -to VGA_BLANK_N +set_location_assignment PIN_A11 -to VGA_CLK +set_location_assignment PIN_J9 -to VGA_G[0] +set_location_assignment PIN_J10 -to VGA_G[1] +set_location_assignment PIN_H12 -to VGA_G[2] +set_location_assignment PIN_G10 -to VGA_G[3] +set_location_assignment PIN_G11 -to VGA_G[4] +set_location_assignment PIN_G12 -to VGA_G[5] +set_location_assignment PIN_F11 -to VGA_G[6] +set_location_assignment PIN_E11 -to VGA_G[7] +set_location_assignment PIN_B11 -to VGA_HS +set_location_assignment PIN_A13 -to VGA_R[0] +set_location_assignment PIN_C13 -to VGA_R[1] +set_location_assignment PIN_E13 -to VGA_R[2] +set_location_assignment PIN_B12 -to VGA_R[3] +set_location_assignment PIN_C12 -to VGA_R[4] +set_location_assignment PIN_D12 -to VGA_R[5] +set_location_assignment PIN_E12 -to VGA_R[6] +set_location_assignment PIN_F13 -to VGA_R[7] +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_D11 -to VGA_VS +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_location_assignment PIN_D9 -to UART_RX +set_location_assignment PIN_E9 -to UART_TX +set_global_assignment -name SYSTEMVERILOG_FILE src/Logger.sv +set_global_assignment -name SOURCE_FILE "../envs/de1-soc/poc/poc3.mem" +set_global_assignment -name SOURCE_FILE "../envs/de1-soc/poc/poc2.mem" +set_global_assignment -name SOURCE_FILE "../envs/de1-soc/poc/poc1.mem" +set_global_assignment -name SDC_FILE "../envs/de1-soc/quartus/top.sdc" +set_global_assignment -name SOURCE_FILE ../src/utils.svh +set_global_assignment -name SOURCE_FILE ../src/types.svh +set_global_assignment -name SOURCE_FILE ../src/params.svh +set_global_assignment -name SOURCE_FILE "../envs/de1-soc/poc/poc.mem" +set_global_assignment -name SYSTEMVERILOG_FILE "../envs/de1-soc/top.sv" +set_global_assignment -name SYSTEMVERILOG_FILE "../envs/de1-soc/memory_map.sv" +set_global_assignment -name SYSTEMVERILOG_FILE ../src/ALU_ALUdecoder/ALUdecoder.sv +set_global_assignment -name VERILOG_FILE ../src/ALU_ALUdecoder/ALU.v +set_global_assignment -name VERILOG_FILE ../src/Instruction_Decode/RegisterFile.v +set_global_assignment -name SYSTEMVERILOG_FILE ../src/Instruction_Decode/MemoryLoader.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../src/Instruction_Decode/Instruction_Decode.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../src/utoss_riscv.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../src/fetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../src/ControlFSM.sv +set_global_assignment -name SOURCE_FILE "../envs/de1-soc/poc/poc0.mem" +set_global_assignment -name SYSTEMVERILOG_FILE uart_rx.sv +set_global_assignment -name SYSTEMVERILOG_FILE uart_tx.sv +set_global_assignment -name SYSTEMVERILOG_FILE uart.sv +set_global_assignment -name VERILOG_FILE inst_mem.v +set_global_assignment -name SYSTEMVERILOG_FILE uart_bus_master.sv +set_global_assignment -name SYSTEMVERILOG_FILE RegisterFile.sv +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/quartus workspace/top.qsf.bak b/quartus workspace/top.qsf.bak new file mode 100644 index 0000000..4d0cae5 --- /dev/null +++ b/quartus workspace/top.qsf.bak @@ -0,0 +1,59 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2023 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition +# Date created = 19:54:22 November 25, 2025 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA5F31C6 +set_global_assignment -name TOP_LEVEL_ENTITY top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:54:22 NOVEMBER 25, 2025" +set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../src/utils/register.sv +set_global_assignment -name SYSTEMVERILOG_FILE "../envs/de1-soc/top.sv" +set_global_assignment -name SYSTEMVERILOG_FILE "../envs/de1-soc/memory_map.sv" +set_global_assignment -name SYSTEMVERILOG_FILE ../src/ALU_ALUdecoder/ALUdecoder.sv +set_global_assignment -name VERILOG_FILE ../src/ALU_ALUdecoder/ALU.v +set_global_assignment -name VERILOG_FILE ../src/Instruction_Decode/RegisterFile.v +set_global_assignment -name SYSTEMVERILOG_FILE ../src/Instruction_Decode/MemoryLoader.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../src/Instruction_Decode/Instruction_Decode.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../src/utoss_riscv.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../src/Logger.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../src/fetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../src/ControlFSM.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name BOARD "DE1-SoC Board" \ No newline at end of file diff --git a/quartus workspace/top.qws b/quartus workspace/top.qws new file mode 100644 index 0000000..89f80ec Binary files /dev/null and b/quartus workspace/top.qws differ diff --git a/quartus workspace/uart.sv b/quartus workspace/uart.sv new file mode 100644 index 0000000..0c7c952 --- /dev/null +++ b/quartus workspace/uart.sv @@ -0,0 +1,67 @@ +`timescale 1ns / 1ps + +module uart # +( + parameter DATA_WIDTH = 8, + parameter CLK_HZ = 50000000, + parameter BAUD = 115200 +) +( + input wire clk, + input wire rst, + + input wire [DATA_WIDTH-1:0] i_data_s, //slave receive this data + input wire i_valid_s, + output wire o_ready_s, + + output wire [DATA_WIDTH-1:0] o_data_m, //master receive this data + output wire o_valid_m, + input wire i_ready_m, + + input wire i_rxd, + output wire o_txd, + + output wire o_tx_busy, + output wire o_rx_busy, + output wire o_rx_overrun_error, + output wire o_rx_frame_error +); + + +// clocks per bit +//localparam integer CLK_HZ = 50000000; +//localparam integer BAUD = 115200; +localparam integer DIV = (CLK_HZ / BAUD); // 50e6/115200 ≈ 434 + +uart_tx #( + .DATA_WIDTH(DATA_WIDTH), + .DIV(DIV) +) +uart_tx_inst ( + .clk(clk), + .rst(rst), + .i_data(i_data_s), + .i_valid(i_valid_s), + .o_ready(o_ready_s), + .o_txd(o_txd), + .o_busy(o_tx_busy) +); + +uart_rx #( + .DATA_WIDTH(DATA_WIDTH), + .DIV(DIV) +) +uart_rx_inst ( + .clk(clk), + .rst(rst), + .o_data(o_data_m), + .o_valid(o_valid_m), + .i_ready(i_ready_m), + .i_rxd(i_rxd), + .o_busy(o_rx_busy), + .o_overrun_error(o_rx_overrun_error), + .o_frame_error(o_rx_frame_error) +); + + +endmodule \ No newline at end of file diff --git a/quartus workspace/uart.sv.bak b/quartus workspace/uart.sv.bak new file mode 100644 index 0000000..35c355c --- /dev/null +++ b/quartus workspace/uart.sv.bak @@ -0,0 +1,65 @@ +`timescale 1ns / 1ps + +module uart # +( + parameter DATA_WIDTH = 8 +) +( + input wire clk, + input wire rst, + + input wire [DATA_WIDTH-1:0] i_data_s, //slave receive this data + input wire i_valid_s, + output wire o_ready_s, + + output wire [DATA_WIDTH-1:0] o_data_m, //master receive this data + output wire o_valid_m, + input wire i_ready_m, + + input wire i_rxd, + output wire o_txd, + + output wire o_tx_busy, + output wire o_rx_busy, + output wire o_rx_overrun_error, + output wire o_rx_frame_error +); + + +// clocks per bit +localparam integer CLK_HZ = 50000000; +localparam integer BAUD = 115200; +localparam integer DIV = (CLK_HZ / BAUD); // 50e6/115200 ≈ 434 + +uart_tx #( + .DATA_WIDTH(DATA_WIDTH), + .DIV(DIV) +) +uart_tx_inst ( + .clk(clk), + .rst(rst), + .i_data(i_data_s), + .i_valid(i_valid_s), + .o_ready(o_ready_s), + .o_txd(o_txd), + .o_busy(o_tx_busy) +); + +uart_rx #( + .DATA_WIDTH(DATA_WIDTH), + .DIV(DIV) +) +uart_rx_inst ( + .clk(clk), + .rst(rst), + .o_data(o_data_m), + .o_valid(o_valid_m), + .i_ready(i_ready_m), + .i_rxd(i_rxd), + .o_busy(o_rx_busy), + .o_overrun_error(o_rx_overrun_error), + .o_frame_error(o_rx_frame_error) +); + + +endmodule \ No newline at end of file diff --git a/quartus workspace/uart_bus_master.sv b/quartus workspace/uart_bus_master.sv new file mode 100644 index 0000000..7fbc566 --- /dev/null +++ b/quartus workspace/uart_bus_master.sv @@ -0,0 +1,289 @@ +//protocol: A: address D: data +//SOF: A5 +//command number(10-13) +//WRITE32: A5 10 A0 A1 A2 A3 D0 D1 D2 D3 CHK +//READ32: A5 11 A0 A1 A2 A3 CHK +//RUN: A5 12 CHK (CHK=0x12) +//HALT: A5 13 CHK (CHK=0x12) +//R_ACK:90 R_RD:91 +module uart_bus_master ( + input wire clk, + input wire rst, + + input wire [7:0] rx_data, + input wire rx_valid, + output wire rx_ready, + + output logic [7:0] tx_data, + output logic tx_valid, + input wire tx_ready, + + output logic [31:0] bus_addr, + output logic [31:0] bus_write_data, + output logic [3:0] bus_write_enable, + input wire [31:0] bus_read_data, + + output logic hold_core, + input logic [31:0] dbg_regs [0:31], + input logic [31:0] dbg_pc +); + + assign rx_ready = (state != STATE_SEND); + + localparam byte SOF = 8'hA5; + localparam byte RSOF = 8'h5A; + + localparam byte CMD_WR32 = 8'h10; + localparam byte CMD_RD32 = 8'h11; + localparam byte CMD_RUN = 8'h12; + localparam byte CMD_HALT = 8'h13; + localparam byte CMD_RDREG = 8'h14; + + + localparam byte R_ACK = 8'h90; + localparam byte R_RD = 8'h91; + localparam byte R_RDREG = 8'h92; + + localparam byte STATUS_OK = 8'h00; + localparam byte STATUS_CHK = 8'h01; + localparam byte STATUS_BUSY = 8'h02; + localparam byte STATUS_CMD = 8'h03; + + typedef enum logic [4:0] { + STATE_WAIT_SOF = 5'd0, + STATE_CMD = 5'd1, + STATE_A0 = 5'd2, + STATE_A1 = 5'd3, + STATE_A2 = 5'd4, + STATE_A3 = 5'd5, + STATE_D0 = 5'd6, + STATE_D1 = 5'd7, + STATE_D2 = 5'd8, + STATE_D3 = 5'd9, + STATE_CHK = 5'd10, + STATE_DO_WR = 5'd11, + STATE_DO_RD0 = 5'd12, + STATE_DO_RD1 = 5'd13, + STATE_SEND = 5'd14, + STATE_REG = 5'd15 + } state_t; + + state_t state; + logic [4:0] reg_idx; + logic [7:0] cmd; + logic [31:0] addr; + logic [31:0] wdata; + logic [7:0] chk_calc; + + logic [7:0] resp [0:6]; + logic [2:0] resp_len; + logic [2:0] resp_idx; + + task automatic prepare_ack(input byte status); + begin + // 5A 90 STATUS CHK + resp[0] = RSOF; + resp[1] = R_ACK; + resp[2] = status; + resp[3] = (R_ACK ^ status); + resp_len = 3'd4; + resp_idx = 3'd0; + state = STATE_SEND; + end + endtask + + task automatic prepare_rd(input logic [31:0] d); + begin + // 5A 91 d0 d1 d2 d3 chk + resp[0] = RSOF; + resp[1] = R_RD; + resp[2] = d[7:0]; + resp[3] = d[15:8]; + resp[4] = d[23:16]; + resp[5] = d[31:24]; + resp[6] = (R_RD ^ d[7:0] ^ d[15:8] ^ d[23:16] ^ d[31:24]); + resp_len = 3'd7; + resp_idx = 3'd0; + state = STATE_SEND; + end + endtask + + task automatic prepare_rdreg(input logic [31:0] d); + begin + // 5A 92 d0 d1 d2 d3 chk + resp[0] = RSOF; + resp[1] = R_RDREG; + resp[2] = d[7:0]; + resp[3] = d[15:8]; + resp[4] = d[23:16]; + resp[5] = d[31:24]; + resp[6] = (R_RDREG ^ d[7:0] ^ d[15:8] ^ d[23:16] ^ d[31:24]); + resp_len = 3'd7; + resp_idx = 3'd0; + state = STATE_SEND; + end + endtask + + always_ff @(posedge clk) begin + if (rst) begin + bus_addr <= 32'd0; + bus_write_data <= 32'd0; + bus_write_enable <= 4'b0000; + + tx_data <= 8'd0; + tx_valid <= 1'b0; + + state <= STATE_WAIT_SOF; + cmd <= 8'd0; + addr <= 32'd0; + wdata <= 32'd0; + chk_calc <= 8'd0; + + resp_len <= 3'd0; + resp_idx <= 3'd0; + + hold_core <= 1'b1; + end else begin + bus_write_enable <= 4'b0000; + + if (tx_valid && tx_ready) tx_valid <= 1'b0; + + if (state == STATE_SEND) begin + if (!tx_valid && tx_ready) begin + tx_data <= resp[resp_idx]; + tx_valid <= 1'b1; + if (resp_idx == resp_len-1) begin + state <= STATE_WAIT_SOF; + resp_idx <= 3'd0; + end else begin + resp_idx <= resp_idx + 3'd1; + end + end + + end else begin + case (state) + STATE_WAIT_SOF: begin + if (rx_valid & rx_ready && rx_data == SOF) state <= STATE_CMD; + end + + STATE_CMD: if (rx_valid & rx_ready) begin + cmd <= rx_data; + chk_calc <= rx_data; + addr <= 32'd0; + wdata <= 32'd0; + + if (rx_data == CMD_RUN || rx_data == CMD_HALT) state <= STATE_CHK; + else if (rx_data == CMD_RDREG) state <= STATE_REG; + else state <= STATE_A0; + end + + STATE_A0: if (rx_valid & rx_ready) begin + addr[7:0] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_A1; + end + + STATE_A1: if (rx_valid & rx_ready) begin + addr[15:8] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_A2; + end + + STATE_A2: if (rx_valid & rx_ready) begin + addr[23:16] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_A3; + end + + STATE_A3: if (rx_valid & rx_ready) begin + addr[31:24] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + if (cmd == CMD_WR32) state <= STATE_D0; + else state <= STATE_CHK; // RD32 no data packet + end + + STATE_D0: if (rx_valid & rx_ready) begin + wdata[7:0] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_D1; + end + + STATE_D1: if (rx_valid & rx_ready) begin + wdata[15:8] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_D2; + end + + STATE_D2: if (rx_valid & rx_ready) begin + wdata[23:16] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_D3; + end + + STATE_D3: if (rx_valid & rx_ready) begin + wdata[31:24] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_CHK; + end + + STATE_REG: if (rx_valid & rx_ready) begin + reg_idx <= rx_data[4:0]; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_CHK; + end + + STATE_CHK: if (rx_valid & rx_ready) begin + if (rx_data != chk_calc) begin + prepare_ack(STATUS_CHK); + end else begin + unique case (cmd) + CMD_HALT: begin + hold_core <= 1'b1; + prepare_ack(STATUS_OK); + end + CMD_RUN: begin + hold_core <= 1'b0; + prepare_ack(STATUS_OK); + end + CMD_WR32: begin + if (!hold_core) prepare_ack(STATUS_BUSY); + else state <= STATE_DO_WR; + end + CMD_RD32: begin + if (!hold_core) prepare_ack(STATUS_BUSY); + else state <= STATE_DO_RD0; + end + CMD_RDREG: begin + prepare_rdreg(dbg_regs[reg_idx]); + end + default: begin + prepare_ack(STATUS_CMD); + end + endcase + end + end + + STATE_DO_WR: begin + bus_addr <= addr; + bus_write_data <= wdata; + bus_write_enable <= 4'b1111; + prepare_ack(STATUS_OK); + end + + STATE_DO_RD0: begin + bus_addr <= addr; + state <= STATE_DO_RD1; + end + + STATE_DO_RD1: begin + prepare_rd(bus_read_data); + end + + default: state <= STATE_WAIT_SOF; + endcase + end + end + end + +endmodule + diff --git a/quartus workspace/uart_bus_master.sv.bak b/quartus workspace/uart_bus_master.sv.bak new file mode 100644 index 0000000..7b23f02 --- /dev/null +++ b/quartus workspace/uart_bus_master.sv.bak @@ -0,0 +1,139 @@ +module uart_bus_master #( + parameter int CLK_HZ = 50_000_000, + parameter int BAUD = 115200 +)( + input wire clk, + input wire rst, + + // UART RX stream + input wire [7:0] rx_data, + input wire rx_valid, + output wire rx_ready, + + // UART TX stream + output logic [7:0] tx_data, + output logic tx_valid, + input wire tx_ready, + + // memory bus (single-cycle write strobe, 1-cycle read latency from your memory_map) + output logic [31:0] bus_addr, + output logic [31:0] bus_wdata, + output logic [3:0] bus_wstrb, + input wire [31:0] bus_rdata, + + // control + output logic hold_core // 1=hold core in reset and allow UART bus access +); + + assign rx_ready = 1'b1; + + localparam byte SOF = 8'hA5; + localparam byte RSOF = 8'h5A; + + localparam byte CMD_WR32 = 8'h10; + localparam byte CMD_RD32 = 8'h11; + localparam byte CMD_RUN = 8'h12; + localparam byte CMD_HALT = 8'h13; + + localparam byte R_ACK = 8'h90; + localparam byte R_RD = 8'h91; + + // default: after reset, hold core (方便你先用UART装程序) + always_ff @(posedge clk) begin + if (rst) hold_core <= 1'b1; + end + + // parser + typedef enum logic [3:0] { + S_WAIT_SOF = 4'd0, + S_CMD = 4'd1, + S_A0 = 4'd2, + S_A1 = 4'd3, + S_A2 = 4'd4, + S_A3 = 4'd5, + S_D0 = 4'd6, + S_D1 = 4'd7, + S_D2 = 4'd8, + S_D3 = 4'd9, + S_CHK = 4'd10, + S_DO_WR = 4'd11, + S_DO_RD_0 = 4'd12, + S_DO_RD_1 = 4'd13, + S_SEND = 4'd14 + } st_t; + + st_t st; + + logic [7:0] cmd; + logic [31:0] addr; + logic [31:0] wdata; + logic [7:0] chk_calc; + logic [7:0] chk_recv; + + logic [31:0] rdata_latched; + logic [7:0] status; + + // response sequencer + logic [3:0] send_idx; + logic [7:0] resp_chk; + + wire rx_fire = rx_valid & rx_ready; + + // bus defaults + always_ff @(posedge clk) begin + if (rst) begin + bus_addr <= 32'd0; + bus_wdata <= 32'd0; + bus_wstrb <= 4'b0000; + + tx_data <= 8'd0; + tx_valid <= 1'b0; + + st <= S_WAIT_SOF; + cmd <= 8'd0; + addr <= 32'd0; + wdata <= 32'd0; + chk_calc <= 8'd0; + chk_recv <= 8'd0; + rdata_latched <= 32'd0; + status <= 8'd0; + send_idx <= 4'd0; + resp_chk <= 8'd0; + end else begin + // default: no bus write unless pulsed + bus_wstrb <= 4'b0000; + + // default: drop tx_valid after handshake + if (tx_valid && tx_ready) tx_valid <= 1'b0; + + case (st) + S_WAIT_SOF: begin + if (rx_fire && rx_data == SOF) begin + st <= S_CMD; + end + end + + S_CMD: if (rx_fire) begin + cmd <= rx_data; + chk_calc <= rx_data; // start XOR from CMD + addr <= 32'd0; + wdata <= 32'd0; + + if (rx_data == CMD_RUN || rx_data == CMD_HALT) begin + st <= S_CHK; + end else begin + st <= S_A0; + end + end + + S_A0: if (rx_fire) begin addr[7:0] <= rx_data; chk_calc <= chk_calc ^ rx_data; st <= S_A1; end + S_A1: if (rx_fire) begin addr[15:8] <= rx_data; chk_calc <= chk_calc ^ rx_data; st <= S_A2; end + S_A2: if (rx_fire) begin addr[23:16] <= rx_data; chk_calc <= chk_calc ^ rx_data; st <= S_A3; end + S_A3: if (rx_fire) begin + addr[31:24] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + if (cmd == CMD_WR32) st <= S_D0; + else st <= S_CHK; // RD32 -> checksum next + end + + S_D0: if (rx_fir diff --git a/quartus workspace/uart_rx.sv b/quartus workspace/uart_rx.sv new file mode 100644 index 0000000..f61528a --- /dev/null +++ b/quartus workspace/uart_rx.sv @@ -0,0 +1,139 @@ +`timescale 1ns / 1ps + +module uart_rx # +( + parameter DATA_WIDTH = 8, + parameter DIV = 434 // 50e6/115200 ≈ 434 +) +( + input wire clk, + input wire rst, + + + output logic [DATA_WIDTH-1:0] o_data, + output logic o_valid, + input wire i_ready, + + input wire i_rxd, + + output logic o_busy, + output logic o_overrun_error, + output logic o_frame_error +); + + reg rxd_q0; + reg rxd_q1; + + // detect falling edge + reg rxd_q1_d = 1'b1; + wire start_fall = (rxd_q1_d == 1'b1) && (rxd_q1 == 1'b0); + + typedef enum logic [1:0] { + STATE_IDLE = 2'd0, + STATE_START = 2'd1, + STATE_DATA = 2'd2, + STATE_STOP = 2'd3 + } uart_state_t; + uart_state_t state = STATE_IDLE; + + reg [18:0] timer; + reg [3:0] bit_idx; + reg [DATA_WIDTH-1:0] data_reg; + + always_ff @(posedge clk) begin + if (rst) begin + o_data <= 0; + o_valid <= 0; + o_busy <= 0; + o_overrun_error <= 0; + o_frame_error <= 0; + rxd_q0 <= 1'b1; + rxd_q1 <= 1'b1; + rxd_q1_d <= 1'b1; + state <= STATE_IDLE; + timer <= 0; + bit_idx <= 0; + data_reg <= 0; + end else begin + // 2FF synchronizer because aynchronous input + rxd_q0 <= i_rxd; + rxd_q1 <= rxd_q0; + rxd_q1_d <= rxd_q1; + o_overrun_error <= 1'b0; + o_frame_error <= 1'b0; + + if (o_valid && i_ready) begin + o_valid <= 1'b0; + end + + case (state) + STATE_IDLE: begin + o_busy <= 1'b0; + bit_idx <= 0; + timer <= 0; + + if (start_fall) begin + o_busy <= 1'b1; + state <= STATE_START; + timer <= (DIV/2) - 1; // center + end + end + + STATE_START: begin + o_busy <= 1'b1; + if (timer != 0) begin + timer <= timer - 1'b1; + end else begin + if (rxd_q1 == 1'b0) begin + state <= STATE_DATA; + bit_idx <= 0; + data_reg <= 0; + timer <= DIV - 1; + end else begin + ///starting bit not 0, error + state <= STATE_IDLE; + o_frame_error <= 1'b1; + end + end + end + + STATE_DATA: begin + o_busy <= 1'b1; + if (timer != 0) begin + timer <= timer - 1'b1; + end else begin + data_reg[bit_idx] <= rxd_q1; // LSB first + + if (bit_idx == DATA_WIDTH-1) begin + state <= STATE_STOP; + timer <= DIV - 1; + end else begin + bit_idx <= bit_idx + 1'b1; + timer <= DIV - 1; + end + end + end + + STATE_STOP: begin + o_busy <= 1'b1; + if (timer != 0) begin + timer <= timer - 1'b1; + end else begin + // stop bit should be 1 + if (rxd_q1 == 1'b1) begin + o_data <= data_reg; + o_overrun_error <= o_valid; // previous data is still there + o_valid <= 1'b1; + end else begin + o_frame_error <= 1'b1; + end + state <= STATE_IDLE; + end + end + + default: state <= STATE_IDLE; + endcase + end + end + +endmodule diff --git a/quartus workspace/uart_tx.sv b/quartus workspace/uart_tx.sv new file mode 100644 index 0000000..fb3640d --- /dev/null +++ b/quartus workspace/uart_tx.sv @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps + +module uart_tx # +( + parameter DATA_WIDTH = 8, + parameter DIV = 434 // 50e6/115200 ≈ 434 +) +( + input wire clk, + input wire rst, + input wire [DATA_WIDTH-1:0] i_data, + input wire i_valid, + output logic o_ready, + output logic o_txd, + output logic o_busy +); + + // 1 start + DATA_WIDTH data + 1 stop + localparam integer FRAME_BITS = DATA_WIDTH + 2; + + reg [FRAME_BITS-1:0] data_reg = {FRAME_BITS{1'b1}}; + reg [3:0] bit_idx; + reg [18:0] timer; + + typedef enum logic {STATE_IDLE, STATE_SEND} uart_tx_state_t; + uart_tx_state_t state; + + always_ff @(posedge clk) begin + if (rst) begin + o_ready <= 1'b1; + o_txd <= 1'b1; + o_busy <= 1'b0; + data_reg <= {FRAME_BITS{1'b1}}; + bit_idx <= 4'd0; + timer <= 19'd0; + state <= STATE_IDLE; + end else begin + case (state) + STATE_IDLE: begin + o_txd <= 1'b1; + o_busy <= 1'b0; + o_ready <= 1'b1; + + if (i_valid) begin + data_reg <= {1'b1, i_data, 1'b0}; + bit_idx <= 4'd0; + o_txd <= 1'b0; + timer <= DIV - 1; + o_busy <= 1'b1; + o_ready <= 1'b0; + state <= STATE_SEND; + end + end + + STATE_SEND: begin + o_busy <= 1'b1; + o_ready <= 1'b0; + if (timer != 0) begin + timer <= timer - 1'b1; + end else begin + bit_idx <= bit_idx + 1'b1; + data_reg <= {1'b1, data_reg[FRAME_BITS-1:1]}; //shift 1 bit so that LSB is the data out + o_txd <= data_reg[1]; + timer <= DIV - 1; + if (bit_idx == FRAME_BITS-1) begin + state <= STATE_IDLE; + end + end + end + + default: state <= STATE_IDLE; + endcase + end + end + +endmodule diff --git a/quartus workspace/uart_tx.sv.bak b/quartus workspace/uart_tx.sv.bak new file mode 100644 index 0000000..276e7f8 --- /dev/null +++ b/quartus workspace/uart_tx.sv.bak @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps + +module uart_tx # +( + parameter DATA_WIDTH = 8, + parameter DIV = 434 // 50e6/115200 ≈ 434 +) +( + input wire clk, + input wire rst, + input wire [DATA_WIDTH-1:0] i_data, + input wire i_valid, + output logic o_ready, + output logic o_txd, + output logic o_busy +); + + // 1 start + DATA_WIDTH data + 1 stop + localparam integer FRAME_BITS = DATA_WIDTH + 2; + + reg [FRAME_BITS-1:0] data_reg = {FRAME_BITS{1'b1}}; + reg [3:0] bit_idx; + reg [18:0] timer; + + typedef enum logic {STATE_IDLE, STATE_SEND} uart_tx_state_t; + uart_tx_state_t state; + + always @(posedge clk) begin + if (rst) begin + o_ready <= 1'b1; + o_txd <= 1'b1; + o_busy <= 1'b0; + data_reg <= {FRAME_BITS{1'b1}}; + bit_idx <= 4'd0; + timer <= 19'd0; + state <= STATE_IDLE; + end else begin + case (state) + STATE_IDLE: begin + o_txd <= 1'b1; + o_busy <= 1'b0; + o_ready <= 1'b1; + + if (i_valid) begin + data_reg <= {1'b1, i_data, 1'b0}; + bit_idx <= 4'd0; + o_txd <= 1'b0; + timer <= DIV - 1; + o_busy <= 1'b1; + o_ready <= 1'b0; + state <= STATE_SEND; + end + end + + STATE_SEND: begin + o_busy <= 1'b1; + o_ready <= 1'b0; + if (timer != 0) begin + timer <= timer - 1'b1; + end else begin + bit_idx <= bit_idx + 1'b1; + data_reg <= {1'b1, data_reg[FRAME_BITS-1:1]}; //shift 1 bit so that LSB is the data out + o_txd <= data_reg[1]; + timer <= DIV - 1; + if (bit_idx == FRAME_BITS-1) begin + state <= STATE_IDLE; + end + end + end + + default: state <= STATE_IDLE; + endcase + end + end + +endmodule diff --git a/riscof/sail_cSim/env/model_test.h b/riscof/sail_cSim/env/model_test.h index 386ffdf..3c86dd5 100644 --- a/riscof/sail_cSim/env/model_test.h +++ b/riscof/sail_cSim/env/model_test.h @@ -1,55 +1,55 @@ -#ifndef _COMPLIANCE_MODEL_H -#define _COMPLIANCE_MODEL_H - -#define RVMODEL_DATA_SECTION \ - .pushsection .tohost,"aw",@progbits; \ - .align 8; .global tohost; tohost: .dword 0; \ - .align 8; .global fromhost; fromhost: .dword 0; \ - .popsection; \ - .align 8; .global begin_regstate; begin_regstate: \ - .word 128; \ - .align 8; .global end_regstate; end_regstate: \ - .word 4; - -//RV_COMPLIANCE_HALT -#define RVMODEL_HALT \ - li x1, 1; \ - write_tohost: \ - sw x1, tohost, t5; \ - j write_tohost; - -#define RVMODEL_BOOT - -//RV_COMPLIANCE_DATA_BEGIN -#define RVMODEL_DATA_BEGIN \ - RVMODEL_DATA_SECTION \ - .align 4;\ - .global begin_signature; begin_signature: - -//RV_COMPLIANCE_DATA_END -#define RVMODEL_DATA_END \ - .align 4; .global end_signature; end_signature: - -//RVTEST_IO_INIT -#define RVMODEL_IO_INIT -//RVTEST_IO_WRITE_STR -#define RVMODEL_IO_WRITE_STR(_R, _STR) -//RVTEST_IO_CHECK -#define RVMODEL_IO_CHECK() -//RVTEST_IO_ASSERT_GPR_EQ -#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) -//RVTEST_IO_ASSERT_SFPR_EQ -#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) -//RVTEST_IO_ASSERT_DFPR_EQ -#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) - -#define RVMODEL_SET_MSW_INT - -#define RVMODEL_CLEAR_MSW_INT - -#define RVMODEL_CLEAR_MTIMER_INT - -#define RVMODEL_CLEAR_MEXT_INT - - -#endif // _COMPLIANCE_MODEL_H +#ifndef _COMPLIANCE_MODEL_H +#define _COMPLIANCE_MODEL_H + +#define RVMODEL_DATA_SECTION \ + .pushsection .tohost,"aw",@progbits; \ + .align 8; .global tohost; tohost: .dword 0; \ + .align 8; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 8; .global begin_regstate; begin_regstate: \ + .word 128; \ + .align 8; .global end_regstate; end_regstate: \ + .word 4; + +//RV_COMPLIANCE_HALT +#define RVMODEL_HALT \ + li x1, 1; \ + write_tohost: \ + sw x1, tohost, t5; \ + j write_tohost; + +#define RVMODEL_BOOT + +//RV_COMPLIANCE_DATA_BEGIN +#define RVMODEL_DATA_BEGIN \ + RVMODEL_DATA_SECTION \ + .align 4;\ + .global begin_signature; begin_signature: + +//RV_COMPLIANCE_DATA_END +#define RVMODEL_DATA_END \ + .align 4; .global end_signature; end_signature: + +//RVTEST_IO_INIT +#define RVMODEL_IO_INIT +//RVTEST_IO_WRITE_STR +#define RVMODEL_IO_WRITE_STR(_R, _STR) +//RVTEST_IO_CHECK +#define RVMODEL_IO_CHECK() +//RVTEST_IO_ASSERT_GPR_EQ +#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) +//RVTEST_IO_ASSERT_SFPR_EQ +#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) +//RVTEST_IO_ASSERT_DFPR_EQ +#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) + +#define RVMODEL_SET_MSW_INT + +#define RVMODEL_CLEAR_MSW_INT + +#define RVMODEL_CLEAR_MTIMER_INT + +#define RVMODEL_CLEAR_MEXT_INT + + +#endif // _COMPLIANCE_MODEL_H diff --git a/riscof/utoss_riscv/env/model_test.h b/riscof/utoss_riscv/env/model_test.h index 80101da..a55076e 100644 --- a/riscof/utoss_riscv/env/model_test.h +++ b/riscof/utoss_riscv/env/model_test.h @@ -1,60 +1,60 @@ -#ifndef _COMPLIANCE_MODEL_H -#define _COMPLIANCE_MODEL_H -#define RVMODEL_DATA_SECTION \ - .pushsection .tohost,"aw",@progbits; \ - .align 8; .global tohost; tohost: .dword 0; \ - .align 8; .global fromhost; fromhost: .dword 0; \ - .popsection; \ - .align 8; .global begin_regstate; begin_regstate: \ - .word 128; \ - .align 8; .global end_regstate; end_regstate: \ - .word 4; - -//RV_COMPLIANCE_HALT -#define RVMODEL_HALT \ - li x1, 1; \ - write_tohost: \ - sw x1, tohost, t5; \ - j write_tohost; - -#define RVMODEL_BOOT - -//RV_COMPLIANCE_DATA_BEGIN -#define RVMODEL_DATA_BEGIN \ - RVMODEL_DATA_SECTION \ - .align 4;\ - .global begin_signature; begin_signature: - -//RV_COMPLIANCE_DATA_END -#define RVMODEL_DATA_END \ - .align 4;\ - .global end_signature; end_signature: - -//RVTEST_IO_INIT -#define RVMODEL_IO_INIT -//RVTEST_IO_WRITE_STR -#define RVMODEL_IO_WRITE_STR(_R, _STR) -//RVTEST_IO_CHECK -#define RVMODEL_IO_CHECK() -//RVTEST_IO_ASSERT_GPR_EQ -#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) -//RVTEST_IO_ASSERT_SFPR_EQ -#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) -//RVTEST_IO_ASSERT_DFPR_EQ -#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) - -#define RVMODEL_SET_MSW_INT \ - li t1, 1; \ - li t2, 0x2000000; \ - sw t1, 0(t2); - -#define RVMODEL_CLEAR_MSW_INT \ - li t2, 0x2000000; \ - sw x0, 0(t2); - -#define RVMODEL_CLEAR_MTIMER_INT - -#define RVMODEL_CLEAR_MEXT_INT - - -#endif // _COMPLIANCE_MODEL_H +#ifndef _COMPLIANCE_MODEL_H +#define _COMPLIANCE_MODEL_H +#define RVMODEL_DATA_SECTION \ + .pushsection .tohost,"aw",@progbits; \ + .align 8; .global tohost; tohost: .dword 0; \ + .align 8; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 8; .global begin_regstate; begin_regstate: \ + .word 128; \ + .align 8; .global end_regstate; end_regstate: \ + .word 4; + +//RV_COMPLIANCE_HALT +#define RVMODEL_HALT \ + li x1, 1; \ + write_tohost: \ + sw x1, tohost, t5; \ + j write_tohost; + +#define RVMODEL_BOOT + +//RV_COMPLIANCE_DATA_BEGIN +#define RVMODEL_DATA_BEGIN \ + RVMODEL_DATA_SECTION \ + .align 4;\ + .global begin_signature; begin_signature: + +//RV_COMPLIANCE_DATA_END +#define RVMODEL_DATA_END \ + .align 4;\ + .global end_signature; end_signature: + +//RVTEST_IO_INIT +#define RVMODEL_IO_INIT +//RVTEST_IO_WRITE_STR +#define RVMODEL_IO_WRITE_STR(_R, _STR) +//RVTEST_IO_CHECK +#define RVMODEL_IO_CHECK() +//RVTEST_IO_ASSERT_GPR_EQ +#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) +//RVTEST_IO_ASSERT_SFPR_EQ +#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) +//RVTEST_IO_ASSERT_DFPR_EQ +#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) + +#define RVMODEL_SET_MSW_INT \ + li t1, 1; \ + li t2, 0x2000000; \ + sw t1, 0(t2); + +#define RVMODEL_CLEAR_MSW_INT \ + li t2, 0x2000000; \ + sw x0, 0(t2); + +#define RVMODEL_CLEAR_MTIMER_INT + +#define RVMODEL_CLEAR_MEXT_INT + + +#endif // _COMPLIANCE_MODEL_H diff --git a/src/ControlFSM.sv b/src/ControlFSM.sv index 71502c8..20cdd1e 100644 --- a/src/ControlFSM.sv +++ b/src/ControlFSM.sv @@ -48,10 +48,8 @@ module ControlFSM // new state for remaining branch instructions parameter BRANCHCOMP = 5'b01111; - parameter FETCH_WAIT = 5'b10000; - //declare state registers reg [4:0] current_state, next_state; @@ -60,8 +58,8 @@ module ControlFSM case (current_state) - FETCH: next_state = FETCH_WAIT; - FETCH_WAIT: next_state = DECODE; + FETCH: next_state = FETCH_WAIT; + FETCH_WAIT: next_state = DECODE; DECODE: begin @@ -155,20 +153,19 @@ module ControlFSM case (current_state) - FETCH: begin - AdrSrc = ADR_SRC__PC; - end + FETCH: begin + AdrSrc = ADR_SRC__PC; + end - FETCH_WAIT: begin - AdrSrc = ADR_SRC__PC; - IRWrite = 1'b1; - PCUpdate = 1'b1; - pc_src = PC_SRC__INCREMENT; - end + FETCH_WAIT: begin + AdrSrc = ADR_SRC__PC; + IRWrite = 1'b1; + PCUpdate = 1'b1; + pc_src = PC_SRC__INCREMENT; + end DECODE: begin - ALUSrcA = ALU_SRC_A__OLD_PC; ALUSrcB = ALU_SRC_B__IMM_EXT; diff --git a/src/ControlFSM.sv.bak b/src/ControlFSM.sv.bak new file mode 100644 index 0000000..b7a120a --- /dev/null +++ b/src/ControlFSM.sv.bak @@ -0,0 +1,317 @@ +//created by Joonseo Park, for University of Toronto Open Source Society +//A Moore Type Finite State Machine for the RV32I Microprocessor Control Unit + +`include "src/types.svh" +`include "src/params.svh" + +module ControlFSM + ( input opcode_t opcode + , input wire clk + , input wire reset + , input wire zero_flag + , input wire [3:0] MemWriteByteAddress + , input wire [2:0] funct3 + , input data_t alu_result + , output adr_src_t AdrSrc + , output reg IRWrite + , output reg RegWrite + , output reg PCUpdate + , output pc_src_t pc_src + , output reg [3:0] MemWrite + , output reg Branch + , output alu_src_a_t ALUSrcA + , output alu_src_b_t ALUSrcB + , output result_src_t ResultSrc + , output reg [4:0] FSMState + ); + + //parameterize states (binary encoding) + //in later systemverilog implementation, change to enum + parameter FETCH = 5'b00000; + parameter DECODE = 5'b00001; + parameter EXECUTER = 5'b00010; + parameter UNCONDJUMP = 5'b00011; + parameter EXECUTEI = 5'b00100; + parameter MEMADR = 5'b00101; + parameter ALUWB = 5'b00110; + parameter MEMWRITE = 5'b00111; + parameter MEMREAD = 5'b01000; + parameter MEMWB = 5'b01001; + parameter BRANCHIFEQ = 5'b01010; + + //new states for lui and auipc + parameter LUI = 5'b01011; + parameter AUIPC = 5'b01100; + + parameter JALR_CALC = 5'b01101; // calculate rs1 + imm, store in alu_out + parameter JALR_STEP2 = 5'b01110; // link and use alu_out to update PC + + // new state for remaining branch instructions + parameter BRANCHCOMP = 5'b01111; + + //declare state registers + reg [4:0] current_state, next_state; + + //Next state logic + always @(*)begin + + case (current_state) + + FETCH: next_state = DECODE; + + DECODE: begin + + if (opcode == JType) next_state = UNCONDJUMP; + + else if (opcode == RType) next_state = EXECUTER; + + else if (opcode == IType_logic) next_state = EXECUTEI; + + else if (opcode == IType_load || opcode == SType) next_state = MEMADR; + + else if (opcode == BType) begin + + case (funct3) + + 3'b000: next_state = BRANCHIFEQ; + + 3'b001: next_state = BRANCHIFEQ; + + default: next_state = BRANCHCOMP; + + endcase + + end + + else if (opcode == UType_auipc) next_state = AUIPC; + + else if (opcode == UType_lui) next_state = LUI; + + else if (opcode == IType_jalr) next_state = JALR_CALC; + + else if (opcode == FENCE) next_state = FETCH; + + else next_state = DECODE; + + end + + AUIPC: next_state = ALUWB; + + LUI: next_state = ALUWB; + + UNCONDJUMP: next_state = ALUWB; + + EXECUTER: next_state = ALUWB; + + EXECUTEI: next_state = ALUWB; + + MEMADR: begin + + if (opcode == IType_load) next_state = MEMREAD; + + else if (opcode == SType) next_state = MEMWRITE; + + else next_state = MEMADR; + + end + + BRANCHIFEQ: next_state = FETCH; + + BRANCHCOMP: next_state = FETCH; + + ALUWB: next_state = FETCH; + + MEMREAD: next_state = MEMWB; + + MEMWRITE: next_state = FETCH; + + MEMWB: next_state = FETCH; + + JALR_CALC: next_state = JALR_STEP2; + + JALR_STEP2: next_state = ALUWB; + + default: next_state = FETCH; + + endcase + + end + + //output logic + always @(*) begin + Branch <= 1'b0; + pc_src <= PC_SRC__INCREMENT; + PCUpdate <= 1'b0; + IRWrite <= 1'b0; + MemWrite <= 4'b0; + RegWrite <= 1'b0; + + FSMState <= current_state; + + case (current_state) + + FETCH: begin + + AdrSrc <= ADR_SRC__PC; + IRWrite <= 1'b1; + PCUpdate <= 1'b1; + + end + + DECODE: begin + + ALUSrcA <= ALU_SRC_A__OLD_PC; + ALUSrcB <= ALU_SRC_B__IMM_EXT; + + end + + AUIPC: begin + + ALUSrcA <= ALU_SRC_A__OLD_PC; + ALUSrcB <= ALU_SRC_B__IMM_EXT; + + end + + LUI: begin + + ALUSrcA <= ALU_SRC_A__ZERO; + ALUSrcB <= ALU_SRC_B__IMM_EXT; + + end + + EXECUTER: begin + + ALUSrcA <= ALU_SRC_A__RD1; + ALUSrcB <= ALU_SRC_B__RD2; + + end + + EXECUTEI: begin + + ALUSrcA <= ALU_SRC_A__RD1; + ALUSrcB <= ALU_SRC_B__IMM_EXT; + + end + + UNCONDJUMP: begin + + ALUSrcA <= ALU_SRC_A__OLD_PC; + ALUSrcB <= ALU_SRC_B__4; + ResultSrc <= RESULT_SRC__ALU_OUT; + PCUpdate <= 1'b1; + pc_src <= PC_SRC__JUMP; // new added + + end + + JALR_CALC: begin + ALUSrcA <= ALU_SRC_A__RD1; // rs1 + ALUSrcB <= ALU_SRC_B__IMM_EXT; // + imm + end + + JALR_STEP2: begin + ALUSrcA <= ALU_SRC_A__OLD_PC; // Calculate link = pc_old + 4, write back in ALUWB + ALUSrcB <= ALU_SRC_B__4; + ResultSrc <= RESULT_SRC__ALU_OUT; + pc_src <= PC_SRC__ALU_RESULT; // fetch (alu_out & ~1) for new PC + PCUpdate <= 1'b1; + end + + + MEMADR: begin + + ALUSrcA <= ALU_SRC_A__RD1; + ALUSrcB <= ALU_SRC_B__IMM_EXT; + + end + + BRANCHIFEQ: begin + + ALUSrcA <= ALU_SRC_A__RD1; + ALUSrcB <= ALU_SRC_B__RD2; + ResultSrc <= RESULT_SRC__ALU_OUT; + Branch <= 1'b1; + case (funct3) + 3'b000: begin + if (zero_flag) begin + pc_src <= PC_SRC__JUMP; + PCUpdate <= 1'b1; + end + else pc_src <= PC_SRC__INCREMENT; + end + + 3'b001: begin + if (!zero_flag) begin + pc_src <= PC_SRC__JUMP; + PCUpdate <= 1'b1; + end + else pc_src <= PC_SRC__INCREMENT; + end + endcase + end + + BRANCHCOMP: begin + + ALUSrcA <= ALU_SRC_A__RD1; + ALUSrcB <= ALU_SRC_B__RD2; + ResultSrc <= RESULT_SRC__ALU_OUT; + Branch <= 1'b1; + if (alu_result == 32'b1) begin + pc_src <= PC_SRC__JUMP; + PCUpdate <= 1'b1; + end + else pc_src <= PC_SRC__INCREMENT; + + end + + ALUWB: begin + + ResultSrc <= RESULT_SRC__ALU_OUT; + RegWrite <= 1'b1; + + end + + MEMWRITE: begin + + ResultSrc <= RESULT_SRC__ALU_OUT; + AdrSrc <= ADR_SRC__RESULT; + MemWrite <= MemWriteByteAddress; + + end + + MEMREAD: begin + + ResultSrc <= RESULT_SRC__ALU_OUT; + AdrSrc <= ADR_SRC__RESULT; + + end + + MEMWB: begin + + ResultSrc <= RESULT_SRC__DATA; + RegWrite <= 1'b1; + + end + + default: begin //by default, we return to FETCH state + + AdrSrc <= ADR_SRC__PC; + IRWrite <= 1'b1; + + end + + + endcase + + end + + //State transition logic (sequential) + always @ (posedge clk) begin + + if (reset) current_state <= FETCH; + + else begin + current_state <= next_state; + end + + end +endmodule diff --git a/src/Instruction_Decode/Instruction_Decode.sv b/src/Instruction_Decode/Instruction_Decode.sv index 67827b5..c14b326 100644 --- a/src/Instruction_Decode/Instruction_Decode.sv +++ b/src/Instruction_Decode/Instruction_Decode.sv @@ -45,6 +45,11 @@ module Instruction_Decode end + default: begin + funct3 = 3'b000; + funct7 = 7'b0; + end + endcase end diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv index 5fc6433..3173dba 100644 --- a/src/Instruction_Decode/MemoryLoader.sv +++ b/src/Instruction_Decode/MemoryLoader.sv @@ -85,4 +85,4 @@ module MemoryLoader MemWriteByteAddress = 4'bxxxx; end endcase -endmodule \ No newline at end of file +endmodule diff --git a/src/Instruction_Decode/MemoryLoader.sv.bak b/src/Instruction_Decode/MemoryLoader.sv.bak new file mode 100644 index 0000000..170e5f9 --- /dev/null +++ b/src/Instruction_Decode/MemoryLoader.sv.bak @@ -0,0 +1,107 @@ +`include "src/types.svh" + +module MemoryLoader +( input data_t memory_data +, input addr_t memory_address +, input logic [2:0] funct3 +, input logic [31:0] dataB +, output data_t mem_load_result +, output logic [3:0] MemWriteByteAddress +, output logic [31:0] __tmp_MemData +); + + integer byteindex; + assign byteindex = memory_address[1:0]; + + always @(*) begin + case (funct3) + 3'b000: begin // lb & sb + case (byteindex) + 2'd0: begin + mem_load_result = {{24{memory_data[7]}}, memory_data[7:0]}; + MemWriteByteAddress = 4'b0001; + __tmp_MemData = {24'b0, dataB[7:0]}; + end + 2'd1: begin + mem_load_result = {{24{memory_data[15]}}, memory_data[15:8]}; + MemWriteByteAddress = 4'b0010; + __tmp_MemData = {16'b0, dataB[7:0], 8'b0}; + end + 2'd2: begin + mem_load_result = {{24{memory_data[23]}}, memory_data[23:16]}; + MemWriteByteAddress = 4'b0100; + __tmp_MemData = {8'b0, dataB[7:0], 16'b0}; + end + 2'd3: begin + mem_load_result = {{24{memory_data[31]}}, memory_data[31:24]}; + MemWriteByteAddress = 4'b1000; + __tmp_MemData = {dataB[7:0], 24'b0}; + end + default: begin + mem_load_result = 32'hX; + MemWriteByteAddress = 4'bx; + __tmp_MemData = 32'bx; + end + endcase + end + + 3'b001: begin // lh & sh + case (byteindex) + 2'd0: begin + mem_load_result = {{16{memory_data[15]}}, memory_data[15:0]}; + MemWriteByteAddress = 4'b0011; + __tmp_MemData = {16'b0, dataB[15:0]}; + end +/* 2'd1: begin + mem_load_result = {{16{memory_data[23]}}, memory_data[23:8]}; + MemWriteByteAddress = 4'b0110; + __tmp_MemData = {8'b0, dataB[15:0], 8'b0}; + end*/ + // skip unaligned halfword access + 2'd2: begin + mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]}; + MemWriteByteAddress = 4'b1100; + __tmp_MemData = {dataB[15:0], 16'b0}; + end + default: begin + mem_load_result = 32'hX; + MemWriteByteAddress = 4'bX; + __tmp_MemData = 32'bX; + end + endcase + end + + 3'b010: begin + mem_load_result = memory_data; // lw + MemWriteByteAddress = 4'b1111; //sw + __tmp_MemData = dataB; + end + 3'b100: begin // lbu + case (byteindex) + 2'd0: mem_load_result = {24'b0, memory_data[7:0]}; + 2'd1: mem_load_result = {24'b0, memory_data[15:8]}; + 2'd2: mem_load_result = {24'b0, memory_data[23:16]}; + 2'd3: mem_load_result = {24'b0, memory_data[31:24]}; + default: mem_load_result = 32'hX; + endcase + end + + 3'b101: begin // lhu + case (byteindex) + 2'd0: mem_load_result = {16'b0, memory_data[15:0]}; + 2'd1: mem_load_result = {16'b0, memory_data[23:8]}; + 2'd2: mem_load_result = {16'b0, memory_data[31:16]}; + default: mem_load_result = 32'hX; + endcase + end + + default: begin + mem_load_result = 32'hX; + MemWriteByteAddress = 4'b0000; + __tmp_MemData = 31'bx; + end + endcase + end + + +endmodule diff --git a/src/Instruction_Decode/RegisterFile.v b/src/Instruction_Decode/RegisterFile.v index cbd41cc..13d2f30 100644 --- a/src/Instruction_Decode/RegisterFile.v +++ b/src/Instruction_Decode/RegisterFile.v @@ -9,44 +9,44 @@ //rd --> a register inside RF memory, holding address of register to be written into module registerFile - ( input [4:0] Addr1 //rs1 field (holds addr of one of 32 registers) - first source register - , input [4:0] Addr2 //rs2 field - second source register (holds data to be stored) - , input [4:0] Addr3 //rd field - desination register - , input clk - , input regWrite - , input [31:0] dataIn - , input reset - , output wire [31:0] baseAddr //data read line #1 - from first source register - , output wire [31:0] writeData //data read line #2 - from second source register + ( input [4:0] Addr1 + , input [4:0] Addr2 + , input [4:0] Addr3 + , input clk + , input regWrite + , input [31:0] dataIn + , input reset + , output wire [31:0] baseAddr + , output wire [31:0] writeData + , output logic [31:0] dbg_regs [0:31] // NEW, added for UART debugging ); - //declare 32 registers in Register File, with 32 bits each 32 bits deep (32 addresses) and 32 bits - //wide (32 bits at each register) note that RFMem[0:31] means there are 32 elements (with addr for - //each element), each of which are 32-bit regs reg [31:0] RFMem [0:31] /* synthesis ramstyle = M10K*/; - // x0 always 0, read out 32-bit contents of rs1 register assign baseAddr = (Addr1 == 5'd0) ? 32'd0 : RFMem[Addr1]; - - // x0 always 0 on read, read out 32-bit contents of rs2 register assign writeData = (Addr2 == 5'd0) ? 32'd0 : RFMem[Addr2]; - always @(posedge clk) begin +always @(*) begin + dbg_regs[0] = 32'd0; + for (int i = 1; i < 32; i++) begin + dbg_regs[i] = RFMem[i]; + end +end + + always @(posedge clk) begin if (reset) begin `ifndef TESTBENCH - integer i; - for (i = 0; i < 32; i = i + 1) begin - RFMem[i] <= 32'b0; - end + integer k; + for (k = 0; k < 32; k = k + 1) begin + RFMem[k] <= 32'b0; + end `else RFMem[0] <= 32'b0; `endif end else if (regWrite && Addr3 != 0) begin - RFMem[Addr3] <= dataIn; //write into destination register if RegWrite = 1 - + RFMem[Addr3] <= dataIn; end - end endmodule diff --git a/src/Instruction_Decode/RegisterFile.v.bak b/src/Instruction_Decode/RegisterFile.v.bak new file mode 100644 index 0000000..f3a905c --- /dev/null +++ b/src/Instruction_Decode/RegisterFile.v.bak @@ -0,0 +1,46 @@ +//Created by Joonseo Park +//The register file holds the source and destination registers specified by instruction fields + +//REGISTERS: +//baseAddr --> holds data read line #1; the output of rs1 +//writeData --> holds data read line #2; the output of rs2 +//rs1 --> a register inside RF memory, holding base address +//rs2 --> a register inside RF memory, holding data to be written into destination register +//rd --> a register inside RF memory, holding address of register to be written into + +module registerFile + ( input [4:0] Addr1 //rs1 field (holds addr of one of 32 registers) - first source register + , input [4:0] Addr2 //rs2 field - second source register (holds data to be stored) + , input [4:0] Addr3 //rd field - desination register + , input clk + , input regWrite + , input [31:0] dataIn + , input reset + , output wire [31:0] baseAddr //data read line #1 - from first source register + , output wire [31:0] writeData //data read line #2 - from second source register + ); + + //declare 32 registers in Register File, with 32 bits each 32 bits deep (32 addresses) and 32 bits + //wide (32 bits at each register) note that RFMem[0:31] means there are 32 elements (with addr for + //each element), each of which are 32-bit regs + reg [31:0] RFMem [0:31] /* synthesis ramstyle = M10K*/; + + // x0 always 0, read out 32-bit contents of rs1 register + assign baseAddr = (Addr1 == 5'd0) ? 32'd0 : RFMem[Addr1]; + + // x0 always 0 on read, read out 32-bit contents of rs2 register + assign writeData = (Addr2 == 5'd0) ? 32'd0 : RFMem[Addr2]; + + always @(posedge clk) begin + + if (reset) RFMem[0] <= 0; + + if (regWrite && Addr3 != 0) begin + + RFMem[Addr3] <= dataIn; //write into destination register if RegWrite = 1 + + end + + end + +endmodule diff --git a/src/uart.sv b/src/uart.sv new file mode 100644 index 0000000..cf39ed1 --- /dev/null +++ b/src/uart.sv @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps + +module uart # +( + parameter DATA_WIDTH = 8 + , parameter CLK_HZ = 50000000 + , parameter BAUD = 115200 +) +( + input wire clk + , input wire rst + , input wire [DATA_WIDTH - 1:0] i_data_s + , input wire i_valid_s + , output wire o_ready_s + , output wire [DATA_WIDTH - 1:0] o_data_m + , output wire o_valid_m + , input wire i_ready_m + , input wire i_rxd + , output wire o_txd + , output wire o_tx_busy + , output wire o_rx_busy + , output wire o_rx_overrun_error + , output wire o_rx_frame_error +); + + +// clocks per bit +//localparam integer CLK_HZ = 50000000; +//localparam integer BAUD = 115200; +localparam int DIV = (CLK_HZ / BAUD); // 50e6/115200 ≈ 434 + +uart_tx #( + .DATA_WIDTH(DATA_WIDTH) + , .DIV(DIV) +) +uart_tx_inst ( + .clk(clk) + , .rst(rst) + , .i_data(i_data_s) + , .i_valid(i_valid_s) + , .o_ready(o_ready_s) + , .o_txd(o_txd) + , .o_busy(o_tx_busy) +); + +uart_rx #( + .DATA_WIDTH(DATA_WIDTH) + , .DIV(DIV) +) +uart_rx_inst ( + .clk(clk) + , .rst(rst) + , .o_data(o_data_m) + , .o_valid(o_valid_m) + , .i_ready(i_ready_m) + , .i_rxd(i_rxd) + , .o_busy(o_rx_busy) + , .o_overrun_error(o_rx_overrun_error) + , .o_frame_error(o_rx_frame_error) +); + + +endmodule \ No newline at end of file diff --git a/src/uart_bus_master.sv b/src/uart_bus_master.sv new file mode 100644 index 0000000..dad6fff --- /dev/null +++ b/src/uart_bus_master.sv @@ -0,0 +1,282 @@ +//protocol: A: address D: data +//SOF: A5 +//command number(10-13) +//WRITE32: A5 10 A0 A1 A2 A3 D0 D1 D2 D3 CHK +//READ32: A5 11 A0 A1 A2 A3 CHK +//RUN: A5 12 CHK (CHK=0x12) +//HALT: A5 13 CHK (CHK=0x12) +//R_ACK:90 R_RD:91 +module uart_bus_master ( + input wire clk + , input wire rst + , input wire [7:0] rx_data + , input wire rx_valid + , output wire rx_ready + , output logic [7:0] tx_data + , output logic tx_valid + , input wire tx_ready + , output logic [31:0] bus_addr + , output logic [31:0] bus_write_data + , output logic [3:0] bus_write_enable + , input wire [31:0] bus_read_data + , output logic hold_core + , input logic [31:0] dbg_regs [0:31] + , input logic [31:0] dbg_pc +); + + assign rx_ready = (state != STATE_SEND); + + localparam byte SOF = 8'hA5; + localparam byte RSOF = 8'h5A; + + localparam byte CMD_WR32 = 8'h10; + localparam byte CMD_RD32 = 8'h11; + localparam byte CMD_RUN = 8'h12; + localparam byte CMD_HALT = 8'h13; + localparam byte CMD_RDREG = 8'h14; + localparam byte R_ACK = 8'h90; + localparam byte R_RD = 8'h91; + localparam byte R_RDREG = 8'h92; + + localparam byte STATUS_OK = 8'h00; + localparam byte STATUS_CHK = 8'h01; + localparam byte STATUS_BUSY = 8'h02; + localparam byte STATUS_CMD = 8'h03; + + typedef enum logic [4:0] { + STATE_WAIT_SOF = 5'd0 + , STATE_CMD = 5'd1 + , STATE_A0 = 5'd2 + , STATE_A1 = 5'd3 + , STATE_A2 = 5'd4 + , STATE_A3 = 5'd5 + , STATE_D0 = 5'd6 + , STATE_D1 = 5'd7 + , STATE_D2 = 5'd8 + , STATE_D3 = 5'd9 + , STATE_CHK = 5'd10 + , STATE_DO_WR = 5'd11 + , STATE_DO_RD0 = 5'd12 + , STATE_DO_RD1 = 5'd13 + , STATE_SEND = 5'd14 + , STATE_REG = 5'd15 + } state_t; + + state_t state; + logic [4:0] reg_idx; + logic [7:0] cmd; + logic [31:0] addr; + logic [31:0] wdata; + logic [7:0] chk_calc; + + logic [7:0] resp [0:6]; + logic [2:0] resp_len; + logic [2:0] resp_idx; + + task automatic prepare_ack(input byte status); + begin + // 5A 90 STATUS CHK + resp[0] = RSOF; + resp[1] = R_ACK; + resp[2] = status; + resp[3] = (R_ACK ^ status); + resp_len = 3'd4; + resp_idx = 3'd0; + state = STATE_SEND; + end + endtask + + task automatic prepare_rd(input logic [31:0] d); + begin + // 5A 91 d0 d1 d2 d3 chk + resp[0] = RSOF; + resp[1] = R_RD; + resp[2] = d[7:0]; + resp[3] = d[15:8]; + resp[4] = d[23:16]; + resp[5] = d[31:24]; + resp[6] = (R_RD ^ d[7:0] ^ d[15:8] ^ d[23:16] ^ d[31:24]); + resp_len = 3'd7; + resp_idx = 3'd0; + state = STATE_SEND; + end + endtask + + task automatic prepare_rdreg(input logic [31:0] d); + begin + // 5A 92 d0 d1 d2 d3 chk + resp[0] = RSOF; + resp[1] = R_RDREG; + resp[2] = d[7:0]; + resp[3] = d[15:8]; + resp[4] = d[23:16]; + resp[5] = d[31:24]; + resp[6] = (R_RDREG ^ d[7:0] ^ d[15:8] ^ d[23:16] ^ d[31:24]); + resp_len = 3'd7; + resp_idx = 3'd0; + state = STATE_SEND; + end + endtask + + always @(posedge clk) begin + if (rst) begin + bus_addr <= 32'd0; + bus_write_data <= 32'd0; + bus_write_enable <= 4'b0000; + + tx_data <= 8'd0; + tx_valid <= 1'b0; + + state <= STATE_WAIT_SOF; + cmd <= 8'd0; + addr <= 32'd0; + wdata <= 32'd0; + chk_calc <= 8'd0; + + resp_len <= 3'd0; + resp_idx <= 3'd0; + + hold_core <= 1'b1; + end else begin + bus_write_enable <= 4'b0000; + if (tx_valid && tx_ready) tx_valid <= 1'b0; + + if (state == STATE_SEND) begin + if (!tx_valid && tx_ready) begin + tx_data <= resp[resp_idx]; + tx_valid <= 1'b1; + if (resp_idx == resp_len - 1) begin + state <= STATE_WAIT_SOF; + resp_idx <= 3'd0; + end else begin + resp_idx <= resp_idx + 3'd1; + end + end + + end else begin + case (state) + STATE_WAIT_SOF: begin + if (rx_valid & rx_ready && rx_data == SOF) state <= STATE_CMD; + end + + STATE_CMD: if (rx_valid & rx_ready) begin + cmd <= rx_data; + chk_calc <= rx_data; + addr <= 32'd0; + wdata <= 32'd0; + + if (rx_data == CMD_RUN || rx_data == CMD_HALT) state <= STATE_CHK; + else if (rx_data == CMD_RDREG) state <= STATE_REG; + else state <= STATE_A0; + end + + STATE_A0: if (rx_valid & rx_ready) begin + addr[7:0] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_A1; + end + + STATE_A1: if (rx_valid & rx_ready) begin + addr[15:8] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_A2; + end + + STATE_A2: if (rx_valid & rx_ready) begin + addr[23:16] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_A3; + end + + STATE_A3: if (rx_valid & rx_ready) begin + addr[31:24] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + if (cmd == CMD_WR32) state <= STATE_D0; + else state <= STATE_CHK; // RD32 no data packet + end + + STATE_D0: if (rx_valid & rx_ready) begin + wdata[7:0] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_D1; + end + + STATE_D1: if (rx_valid & rx_ready) begin + wdata[15:8] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_D2; + end + + STATE_D2: if (rx_valid & rx_ready) begin + wdata[23:16] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_D3; + end + + STATE_D3: if (rx_valid & rx_ready) begin + wdata[31:24] <= rx_data; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_CHK; + end + + STATE_REG: if (rx_valid & rx_ready) begin + reg_idx <= rx_data[4:0]; + chk_calc <= chk_calc ^ rx_data; + state <= STATE_CHK; + end + + STATE_CHK: if (rx_valid & rx_ready) begin + if (rx_data != chk_calc) begin + prepare_ack(STATUS_CHK); + end else begin + case (cmd) + CMD_HALT: begin + hold_core <= 1'b1; + prepare_ack(STATUS_OK); + end + CMD_RUN: begin + hold_core <= 1'b0; + prepare_ack(STATUS_OK); + end + CMD_WR32: begin + if (!hold_core) prepare_ack(STATUS_BUSY); + else state <= STATE_DO_WR; + end + CMD_RD32: begin + if (!hold_core) prepare_ack(STATUS_BUSY); + else state <= STATE_DO_RD0; + end + CMD_RDREG: begin + prepare_rdreg(dbg_regs[reg_idx]); + end + default: begin + prepare_ack(STATUS_CMD); + end + endcase + end + end + + STATE_DO_WR: begin + bus_addr <= addr; + bus_write_data <= wdata; + bus_write_enable <= 4'b1111; + prepare_ack(STATUS_OK); + end + + STATE_DO_RD0: begin + bus_addr <= addr; + state <= STATE_DO_RD1; + end + + STATE_DO_RD1: begin + prepare_rd(bus_read_data); + end + + default: state <= STATE_WAIT_SOF; + endcase + end + end + end + +endmodule + diff --git a/src/uart_rx.sv b/src/uart_rx.sv new file mode 100644 index 0000000..5bed3bb --- /dev/null +++ b/src/uart_rx.sv @@ -0,0 +1,135 @@ +`timescale 1ns / 1ps + +module uart_rx # +( + parameter DATA_WIDTH = 8 + , parameter DIV = 434 // 50e6/115200 ≈ 434 +) +( + input wire clk + , input wire rst + , output logic [DATA_WIDTH - 1:0] o_data + , output logic o_valid + , input wire i_ready + , input wire i_rxd + , output logic o_busy + , output logic o_overrun_error + , output logic o_frame_error +); + + reg rxd_q0; + reg rxd_q1; + + // detect falling edge + reg rxd_q1_d = 1'b1; + wire start_fall = (rxd_q1_d == 1'b1) && (rxd_q1 == 1'b0); + + typedef enum logic [1:0] { + STATE_IDLE = 2'd0 + , STATE_START = 2'd1 + , STATE_DATA = 2'd2 + , STATE_STOP = 2'd3 + } uart_state_t; + uart_state_t state = STATE_IDLE; + + reg [18:0] timer; + reg [3:0] bit_idx; + reg [DATA_WIDTH - 1:0] data_reg; + + always @(posedge clk) begin + if (rst) begin + o_data <= 0; + o_valid <= 0; + o_busy <= 0; + o_overrun_error <= 0; + o_frame_error <= 0; + rxd_q0 <= 1'b1; + rxd_q1 <= 1'b1; + rxd_q1_d <= 1'b1; + state <= STATE_IDLE; + timer <= 0; + bit_idx <= 0; + data_reg <= 0; + end else begin + // 2FF synchronizer because aynchronous input + rxd_q0 <= i_rxd; + rxd_q1 <= rxd_q0; + rxd_q1_d <= rxd_q1; + o_overrun_error <= 1'b0; + o_frame_error <= 1'b0; + + if (o_valid && i_ready) begin + o_valid <= 1'b0; + end + + case (state) + STATE_IDLE: begin + o_busy <= 1'b0; + bit_idx <= 0; + timer <= 0; + + if (start_fall) begin + o_busy <= 1'b1; + state <= STATE_START; + timer <= (DIV / 2) - 1; // center + end + end + + STATE_START: begin + o_busy <= 1'b1; + if (timer != 0) begin + timer <= timer - 1'b1; + end else begin + if (rxd_q1 == 1'b0) begin + state <= STATE_DATA; + bit_idx <= 0; + data_reg <= 0; + timer <= DIV - 1; + end else begin + ///starting bit not 0, error + state <= STATE_IDLE; + o_frame_error <= 1'b1; + end + end + end + + STATE_DATA: begin + o_busy <= 1'b1; + if (timer != 0) begin + timer <= timer - 1'b1; + end else begin + data_reg[bit_idx] <= rxd_q1; // LSB first + + if (bit_idx == DATA_WIDTH - 1) begin + state <= STATE_STOP; + timer <= DIV - 1; + end else begin + bit_idx <= bit_idx + 1'b1; + timer <= DIV - 1; + end + end + end + + STATE_STOP: begin + o_busy <= 1'b1; + if (timer != 0) begin + timer <= timer - 1'b1; + end else begin + // stop bit should be 1 + if (rxd_q1 == 1'b1) begin + o_data <= data_reg; + o_overrun_error <= o_valid; // previous data is still there + o_valid <= 1'b1; + end else begin + o_frame_error <= 1'b1; + end + state <= STATE_IDLE; + end + end + + default: state <= STATE_IDLE; + endcase + end + end + +endmodule diff --git a/src/uart_tx.sv b/src/uart_tx.sv new file mode 100644 index 0000000..7fb4a80 --- /dev/null +++ b/src/uart_tx.sv @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps + +module uart_tx # +( + parameter DATA_WIDTH = 8 + , parameter DIV = 434 // 50e6/115200 ≈ 434 +) +( + input wire clk + , input wire rst + , input wire [DATA_WIDTH - 1:0] i_data + , input wire i_valid + , output logic o_ready + , output logic o_txd + , output logic o_busy +); + + // 1 start + DATA_WIDTH data + 1 stop + localparam int FRAME_BITS = DATA_WIDTH + 2; + + reg [FRAME_BITS - 1:0] data_reg = {FRAME_BITS{1'b1}}; + reg [3:0] bit_idx; + reg [18:0] timer; + + typedef enum logic {STATE_IDLE, STATE_SEND} uart_tx_state_t; + uart_tx_state_t state; + + always @(posedge clk) begin + if (rst) begin + o_ready <= 1'b1; + o_txd <= 1'b1; + o_busy <= 1'b0; + data_reg <= {FRAME_BITS{1'b1}}; + bit_idx <= 4'd0; + timer <= 19'd0; + state <= STATE_IDLE; + end else begin + case (state) + STATE_IDLE: begin + o_txd <= 1'b1; + o_busy <= 1'b0; + o_ready <= 1'b1; + + if (i_valid) begin + data_reg <= {1'b1, i_data, 1'b0}; + bit_idx <= 4'd0; + o_txd <= 1'b0; + timer <= DIV - 1; + o_busy <= 1'b1; + o_ready <= 1'b0; + state <= STATE_SEND; + end + end + + STATE_SEND: begin + o_busy <= 1'b1; + o_ready <= 1'b0; + if (timer != 0) begin + timer <= timer - 1'b1; + end else begin + bit_idx <= bit_idx + 1'b1; + data_reg <= {1'b1, data_reg[FRAME_BITS - 1:1]}; //shift 1 bit so that LSB is the data out + o_txd <= data_reg[1]; + timer <= DIV - 1; + if (bit_idx == FRAME_BITS - 1) begin + state <= STATE_IDLE; + end + end + end + + default: state <= STATE_IDLE; + endcase + end + end + +endmodule diff --git a/src/utoss_riscv.sv b/src/utoss_riscv.sv index d3cb17a..19a322f 100644 --- a/src/utoss_riscv.sv +++ b/src/utoss_riscv.sv @@ -4,12 +4,13 @@ module utoss_riscv ( input wire clk , input wire reset - // memory interface begin - , output addr_t memory__address - , output data_t memory__write_data + , output addr_t memory__address + , output data_t memory__write_data , output logic [3:0] memory__write_enable - , input data_t memory__read_data - // memory interface end + , input data_t memory__read_data + + , output logic [31:0] dbg_regs [0:31] + , output addr_t dbg_pc ); wire cfsm__pc_update; @@ -54,6 +55,7 @@ module utoss_riscv logic [3:0] MemWriteByteAddress; + assign dbg_pc = pc_cur; ControlFSM control_fsm ( .opcode ( opcode ) , .clk ( clk ) @@ -138,6 +140,7 @@ module utoss_riscv , .dataIn ( result ) , .baseAddr ( rd1 ) , .writeData ( rd2 ) + , .dbg_regs ( dbg_regs ) ); ALU alu @@ -210,4 +213,4 @@ module utoss_riscv ); `endif -endmodule \ No newline at end of file +endmodule diff --git a/src/utoss_riscv.sv.bak b/src/utoss_riscv.sv.bak new file mode 100644 index 0000000..deeeba0 --- /dev/null +++ b/src/utoss_riscv.sv.bak @@ -0,0 +1,213 @@ +`include "src/types.svh" + +module utoss_riscv + ( input wire clk + , input wire reset + + // memory interface begin + , output addr_t memory__address + , output data_t memory__write_data + , output logic [3:0] memory__write_enable + , input data_t memory__read_data + // memory interface end + ); + + wire cfsm__pc_update; + wire cfsm__reg_write; + wire cfsm__ir_write; + pc_src_t cfsm__pc_src; + result_src_t cfsm__result_src; + + addr_t pc_cur; + data_t data; + instr_t instruction; + opcode_t opcode; + imm_t imm_ext; + reg [2:0] funct3; + reg [6:0] funct7; + + integer byteindex; + + data_t result; + data_t mem_load_result; + + data_t rd1; + data_t rd2; + + data_t alu_input_a; + data_t alu_input_b; + data_t alu_result; + data_t alu_out; + + addr_t pc_old; + + wire alu__zero_flag; + + adr_src_t cfsm__adr_src; + wire __tmp_Branch; + wire [1:0] __tmp_ALUSrcA, __tmp_ALUSrcB; + wire [3:0] __tmp_ALUControl; + wire [1:0] __tmp_ResultSrc; + wire [4:0] __tmp_FSMState; + data_t dataA, dataB; + reg [4:0] rd, rs1, rs2; + + logic [3:0] MemWriteByteAddress; + + ControlFSM control_fsm + ( .opcode ( opcode ) + , .clk ( clk ) + , .reset ( reset ) + , .zero_flag ( alu__zero_flag ) + , .MemWriteByteAddress ( MemWriteByteAddress ) + , .funct3 ( funct3 ) + , .alu_result ( alu_result ) + , .AdrSrc ( cfsm__adr_src ) + , .IRWrite ( cfsm__ir_write ) + , .RegWrite ( cfsm__reg_write ) + , .PCUpdate ( cfsm__pc_update ) + , .pc_src ( cfsm__pc_src ) + , .MemWrite ( memory__write_enable ) + , .Branch ( __tmp_Branch ) + , .ALUSrcA ( __tmp_ALUSrcA ) + , .ALUSrcB ( __tmp_ALUSrcB ) + , .ResultSrc ( cfsm__result_src ) + , .FSMState ( __tmp_FSMState ) + ); + + fetch fetch + ( .clk ( clk ) + , .reset ( reset ) + , .cfsm__pc_update ( cfsm__pc_update ) + , .alu_result_for_pc ( alu_out ) + , .cfsm__pc_src ( cfsm__pc_src ) + , .cfsm__ir_write ( cfsm__ir_write ) + , .imm_ext ( imm_ext ) + + // outputs + , .pc_cur ( pc_cur ) + , .pc_old ( pc_old ) + ); + + always @(*) begin + case (cfsm__adr_src) + ADR_SRC__PC: memory__address = pc_cur; + ADR_SRC__RESULT: memory__address = result; + endcase + end + + always @(posedge clk) begin + if (cfsm__ir_write) begin + instruction <= memory__read_data; + end + end + + MemoryLoader MemLoad + ( .memory_data ( memory__read_data ) + , .memory_address ( memory__address ) + , .mem_load_result ( mem_load_result ) + , .funct3 ( funct3 ) + , .dataB ( dataB ) + , .MemWriteByteAddress ( MemWriteByteAddress ) + , .__tmp_MemData ( memory__write_data ) + ); + + always @(posedge clk) begin + data <= mem_load_result; + end + + Instruction_Decode instruction_decode + ( .instr ( instruction ) + , .opcode ( opcode ) + , .funct3 ( funct3 ) + , .funct7 ( funct7 ) + , .ALUControl ( __tmp_ALUControl ) + , .imm_ext ( imm_ext ) + , .rd ( rd ) + , .rs1 ( rs1 ) + , .rs2 ( rs2 ) + ); + + registerFile RegFile + ( .Addr1 ( rs1 ) + , .Addr2 ( rs2 ) + , .Addr3 ( rd ) + , .clk ( clk ) + , .reset ( reset ) + , .regWrite ( cfsm__reg_write ) + , .dataIn ( result ) + , .baseAddr ( rd1 ) + , .writeData ( rd2 ) + ); + + ALU alu + ( .a ( alu_input_a ) + , .b ( alu_input_b ) + , .alu_control ( __tmp_ALUControl ) + , .out ( alu_result ) + , .zeroE ( alu__zero_flag ) + ); + + always @(posedge clk) begin + alu_out <= alu_result; + end + + always @(*) begin + case (__tmp_ALUSrcA) + ALU_SRC_A__PC: alu_input_a = pc_cur; + ALU_SRC_A__OLD_PC: alu_input_a = pc_old; + ALU_SRC_A__RD1: alu_input_a = dataA; + ALU_SRC_A__ZERO: alu_input_a = 32'b0; + + default: alu_input_a = 32'hxxxxxxxx; + endcase + end + + always @(*) begin + case (__tmp_ALUSrcB) + ALU_SRC_B__RD2: alu_input_b = dataB; + ALU_SRC_B__IMM_EXT: alu_input_b = imm_ext; + ALU_SRC_B__4: alu_input_b = 32'd4; + default: alu_input_b = 32'hxxxxxxxx; + endcase + end + + always @(*) begin + case (cfsm__result_src) + RESULT_SRC__ALU_OUT: result = alu_out; + RESULT_SRC__DATA: result = data; + RESULT_SRC__ALU_RESULT: result = alu_result; + default: result = 32'hxxxxxxxx; + endcase + end + + always @(posedge clk) begin + dataA <= rd1; + dataB <= rd2; + end + +`ifndef UTOSS_RISCV_SYNTHESIS + Logger CoreLog + ( + .clk ( clk ) + , .pc_cur ( pc_cur ) + , .instruction ( instruction ) + , .FSM_State ( __tmp_FSMState ) + , .opcode ( opcode ) + , .funct3 ( funct3 ) + , .funct7 ( funct7 ) + , .rs1 ( rs1 ) + , .rs2 ( rs2 ) + , .rd ( rd ) + , .imm_ext ( imm_ext ) + , .memory_address ( memory__address ) + , .memory_data ( mem_load_result ) + , .write_enable ( memory__write_enable ) + , .rd1 ( rd1 ) + , .rd2 ( rd2 ) + , .result ( result ) + , .regWrite ( cfsm__reg_write ) + ); +`endif + +endmodule diff --git a/test/utils.svh b/test/utils.svh index 7a53fc8..025da9d 100644 --- a/test/utils.svh +++ b/test/utils.svh @@ -24,4 +24,6 @@ `include "src/utils.svh" +`include "src/utils.svh" + `endif diff --git a/test_uart.py b/test_uart.py new file mode 100644 index 0000000..c0f1ab8 --- /dev/null +++ b/test_uart.py @@ -0,0 +1,129 @@ +import serial +import time + +COM = "COM4" +BAUD = 115200 +TIMEOUT = 1.0 + +WORDS = [ + 0xFE010113, 0x00112E23, 0x00812C23, 0x00912A23, + 0x02010413, 0x00000493, 0x00148793, 0x3FF7F493, + 0x100007B7, 0x0097A023, 0xFE042623, 0x0100006F, + 0xFEC42783, 0x00178793, 0xFEF42623, 0xFEC42703, + 0x000F47B7, 0x23F78793, 0xFEE7D4E3, 0xFCDFF06F, +] + +def hx(b: bytes) -> str: + return " ".join(f"{x:02x}" for x in b) + +def xor_chk(bs: bytes) -> int: + c = 0 + for b in bs: + c ^= b + return c & 0xFF + +def read_exact(ser, n) -> bytes: + d = ser.read(n) + if len(d) != n: + raise RuntimeError(f"need {n}, got {len(d)}: {hx(d)}") + return d + +def expect_ack(resp: bytes, label: str) -> int: + + if len(resp) != 4 or resp[0] != 0x5A or resp[1] != 0x90: + raise RuntimeError(f"{label}: not ACK: {hx(resp)}") + status = resp[2] + chk = resp[3] + exp = (0x90 ^ status) & 0xFF + if chk != exp: + raise RuntimeError(f"{label}: bad ACK chk got {chk:02x} expect {exp:02x} frame={hx(resp)}") + return status + +def cmd_halt(ser): + ser.write(bytes([0xA5, 0x13, 0x13])) # CHK=0x13 + resp = read_exact(ser, 4) + st = expect_ack(resp, "HALT") + print("HALT resp:", hx(resp), "status=", hex(st)) + return st + +def cmd_run(ser): + ser.write(bytes([0xA5, 0x12, 0x12])) # CHK=0x12 + resp = read_exact(ser, 4) + st = expect_ack(resp, "RUN") + print("RUN resp:", hx(resp), "status=", hex(st)) + return st + +def cmd_wr32(ser, addr: int, data: int): + pkt = bytearray([0xA5, 0x10]) + pkt += addr.to_bytes(4, "little") + pkt += data.to_bytes(4, "little") + pkt += bytes([xor_chk(pkt[1:])]) + ser.write(pkt) + resp = read_exact(ser, 4) + st = expect_ack(resp, "WR32") + if st != 0: + raise RuntimeError(f"WR32 status={st:02x} addr=0x{addr:08x} resp={hx(resp)}") + return st + +def cmd_rdreg(ser, reg_idx: int) -> int: + reg_idx &= 0x1F + cmd = 0x14 + chk = cmd ^ reg_idx + ser.write(bytes([0xA5, cmd, reg_idx, chk])) + + hdr = read_exact(ser, 2) + + if hdr == bytes([0x5A, 0x90]): + tail = read_exact(ser, 2) + st = expect_ack(hdr + tail, "RDREG(ACK)") + raise RuntimeError(f"RDREG returned ACK status=0x{st:02x} frame={hx(hdr+tail)}") + + if hdr != bytes([0x5A, 0x92]): + rest = ser.read(16) + raise RuntimeError(f"RDREG bad header: {hx(hdr)} rest={hx(rest)}") + + rest = read_exact(ser, 5) # d0 d1 d2 d3 chk + d0, d1, d2, d3, rcv_chk = rest + exp_chk = (0x92 ^ d0 ^ d1 ^ d2 ^ d3) & 0xFF + if rcv_chk != exp_chk: + raise RuntimeError(f"RDREG bad chk got {rcv_chk:02x} expect {exp_chk:02x} frame={hx(hdr+rest)}") + + return int.from_bytes(bytes([d0, d1, d2, d3]), "little") + +def main(): + ser = serial.Serial(COM, BAUD, timeout=TIMEOUT) + time.sleep(0.2) + ser.reset_input_buffer() + ser.reset_output_buffer() + + cmd_halt(ser) + + print("Loading program...") + base = 0x00000000 + for i, w in enumerate(WORDS): + addr = base + 4*i + cmd_wr32(ser, addr, w) + if (i % 4) == 3: + print(f" wrote up to 0x{addr:08x}") + + cmd_run(ser) + print("Core running. LEDR should be counting now.") + + print("Reading cnt from x9 (s1).") + last = None + try: + while True: + v = cmd_rdreg(ser, 9) # x9 = cnt + if last is None: + print(f"cnt = {v:4d} (0x{v:08x})") + else: + print(f"cnt = {v:4d} (0x{v:08x}) ") + last = v + time.sleep(0.5) + except KeyboardInterrupt: + print("\nStopped.") + finally: + ser.close() + +if __name__ == "__main__": + main()