From f7055b0a230c60a1f294a7edb34affc642e29c1c Mon Sep 17 00:00:00 2001 From: Tim Date: Wed, 9 Sep 2026 16:40:56 -0700 Subject: [PATCH] test(bare-metal): rusty_zstd round-trips on an ESP32-S3 CI proves the crate COMPILES for Cortex-M4F and RV32. Running on a part is a different claim, so this one was run. census64::CENSUS_LIVE = false (expected: Xtensa LX7 has no 64-bit atomics) source 8260 bytes L1 8260 -> 468 bytes (17.65x) round trip OK L3 8260 -> 426 bytes (19.39x) round trip OK L5 8260 -> 263 bytes (31.41x) round trip OK RESULT: PASS -- compressed and decompressed on the board Three levels because they are three different match finders: Fast, DFast and Greedy. Each output was decompressed and compared byte for byte against the source, on the part. The S3 is the right board for this even though it is neither CI target: it is 32-bit, so `core::sync::atomic::AtomicU64` does not exist there either and every census counter is the `census64` stub. That makes it the exact configuration the previous commit created, and the PASS is the evidence that stubbing the instrument left the codec alone. `bare-metal/esp32s3` is excluded from the workspace and hand-run: it needs Espressif's Rust fork, which CI does not have. A plain `cargo build` at the root never sees it. Its README carries the commands, the captured output, and what the test does NOT claim -- no timing, no heap floor (192 KiB was enough for 8 KiB of source at levels 1 to 5), and one part rather than three. Co-Authored-By: Claude Opus 5 (1M context) --- .gitignore | 4 + CHANGELOG.md | 27 + Cargo.toml | 5 + README.md | 1 + bare-metal/esp32s3/.cargo/config.toml | 15 + bare-metal/esp32s3/Cargo.lock | 1572 ++++++++++++++++++++++++ bare-metal/esp32s3/Cargo.toml | 23 + bare-metal/esp32s3/README.md | 58 + bare-metal/esp32s3/rust-toolchain.toml | 2 + bare-metal/esp32s3/src/main.rs | 101 ++ 10 files changed, 1808 insertions(+) create mode 100644 bare-metal/esp32s3/.cargo/config.toml create mode 100644 bare-metal/esp32s3/Cargo.lock create mode 100644 bare-metal/esp32s3/Cargo.toml create mode 100644 bare-metal/esp32s3/README.md create mode 100644 bare-metal/esp32s3/rust-toolchain.toml create mode 100644 bare-metal/esp32s3/src/main.rs diff --git a/.gitignore b/.gitignore index 54352a0..fadac67 100644 --- a/.gitignore +++ b/.gitignore @@ -22,3 +22,7 @@ # `rustc scripts/cpuprobe.rs` drops its binary wherever it is run from. /cpuprobe.exe /cpuprobe.pdb + +# The bare-metal firmware builds into its own target dir (it is not a +# workspace member, so the root /target rule does not cover it). +bare-metal/*/target/ diff --git a/CHANGELOG.md b/CHANGELOG.md index faba3b2..4c06978 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,33 @@ based on [Keep a Changelog](https://keepachangelog.com/); this project uses ## [Unreleased] +### Added -- the bare-metal claim, run on silicon (ESP32-S3) + +CI proves rusty_zstd COMPILES for Cortex-M4F and RV32. That is a different +claim from running, so this one was run: `bare-metal/esp32s3` is a `no_std + +alloc` firmware that compresses and decompresses on the part and compares the +result byte for byte against the source. + +``` +census64::CENSUS_LIVE = false (false is expected here: no 64-bit atomics) +source 8260 bytes +L1 8260 -> 468 bytes (17.65x) round trip OK +L3 8260 -> 426 bytes (19.39x) round trip OK +L5 8260 -> 263 bytes (31.41x) round trip OK +RESULT: PASS -- compressed and decompressed on the board +``` + +Three levels because they are three different match finders: Fast, DFast and +Greedy. Xtensa LX7 is 32-bit, so every census counter on that part is the +`census64` stub -- which makes the board the exact configuration the fix +created, and the `PASS` the evidence that stubbing the instrument left the +codec alone. + +It is excluded from the workspace and hand-run: it needs Espressif's Rust fork, +which CI does not have. It claims no timing and no heap floor; 192 KiB was +enough for 8 KiB of source at levels 1 to 5, and the crate sizes its tables +from the source length. See `bare-metal/esp32s3/README.md`. + ### Fixed -- the census counters cost the crate BARE METAL; they no longer do `cargo check -p rusty_zstd --no-default-features --features alloc` failed with diff --git a/Cargo.toml b/Cargo.toml index 91f1616..d5c06ec 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -7,6 +7,11 @@ members = [ "crates/rzstd-alloc", ] +# The on-board proof (bare-metal/esp32s3) is a firmware crate for Xtensa: it +# needs Espressif's Rust fork and its own linker script, so it must not be a +# workspace member. Excluded, a plain `cargo build` at the root never sees it. +exclude = ["bare-metal/esp32s3"] + [workspace.package] version = "0.2.5" edition = "2021" diff --git a/README.md b/README.md index d094e87..e9244db 100644 --- a/README.md +++ b/README.md @@ -370,6 +370,7 @@ Fetch the oracle with `pwsh scripts/fetch-oracle.ps1`, or point | `no_std + alloc` | ✅ builds | | `thumbv7em-none-eabihf` (Cortex-M4F) | ✅ builds (`no_std + alloc`) | | `riscv32imac-unknown-none-elf` | ✅ builds (`no_std + alloc`) | +| ESP32-S3 (Xtensa LX7) | ✅ **round-trips on the board** ([proof](bare-metal/esp32s3/README.md)) | AVX2 and NEON kernels are selected at **runtime**. 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+esp-println = { version = "0.18.0", default-features = false, features = ["esp32s3", "jtag-serial"] } +esp-backtrace = { version = "0.20.0", features = ["esp32s3", "println", "panic-handler"] } +rusty_zstd = { path = "../../crates/rusty_zstd", default-features = false, features = ["alloc"] } + +[profile.release] +opt-level = "s" +lto = true +codegen-units = 1 +debug = 2 diff --git a/bare-metal/esp32s3/README.md b/bare-metal/esp32s3/README.md new file mode 100644 index 0000000..321052e --- /dev/null +++ b/bare-metal/esp32s3/README.md @@ -0,0 +1,58 @@ +# rusty_zstd on an ESP32-S3 — the on-board proof + +"Builds for a bare-metal target" and "runs on the part" are different claims. +CI makes the first one every push (`cargo check --target thumbv7em-none-eabihf` +and `--target riscv32imac-unknown-none-elf`). This directory is the second one, +and it is hand-run: it needs Espressif's Rust fork, which CI does not have. + +**Result, 2026-09-09, ESP32-S3 revision v0.2, 8 MB flash, 192 KiB heap:** + +``` +=== rusty_zstd on ESP32-S3 (xtensa, no_std + alloc) === +census64::CENSUS_LIVE = false (false is expected here: no 64-bit atomics) +source 8260 bytes +L1 8260 -> 468 bytes (17.65x) round trip OK +L3 8260 -> 426 bytes (19.39x) round trip OK +L5 8260 -> 263 bytes (31.41x) round trip OK + +RESULT: PASS -- compressed and decompressed on the board +``` + +Three levels because they are three different match finders: L1 is Fast, L3 is +DFast, L5 is Greedy. Each compressed and then decompressed back to a buffer +compared byte for byte against the source. + +## Why this part is the right test + +Xtensa LX7 is 32-bit, so `core::sync::atomic::AtomicU64` does not exist on it — +the same reason Cortex-M4F and RV32 could not build the crate at all until +`census64` landed. Every census counter here is the zero-sized stub, which is +why `CENSUS_LIVE` prints `false`. **A zero from a counter on this part means +"not measurable on this target", never "measured zero".** + +The board therefore exercises the exact configuration the fix created, and the +`PASS` line is the evidence that stubbing the instrument did not disturb the +codec. + +## Running it + +```sh +espup install # once: the `esp` Rust fork for Xtensa +cargo install espflash # once +cd bare-metal/esp32s3 +cargo run --release -- --port COM4 # your port; omit on Linux/macOS to autodetect +``` + +Passes when the last line reads `RESULT: PASS`. It is not in the workspace +(`exclude` in the root manifest), so a normal `cargo build` at the repo root +never sees it and never needs the Xtensa toolchain. + +## What it does not claim + +- **No timing.** There is no cycle count here, so nothing in this directory is a + performance claim. It answers "does it work", not "how fast". +- **Heap, not measured to a floor.** 192 KiB was enough for an 8 KiB source at + levels 1 to 5. The crate sizes its tables from the SOURCE length, so a bigger + input needs more; finding the minimum heap per level is a separate exercise. +- **One part.** The S3 is Xtensa. The two targets CI compiles are ARM and + RISC-V, and neither has been run on silicon here. diff --git a/bare-metal/esp32s3/rust-toolchain.toml b/bare-metal/esp32s3/rust-toolchain.toml new file mode 100644 index 0000000..a2f5ab5 --- /dev/null +++ b/bare-metal/esp32s3/rust-toolchain.toml @@ -0,0 +1,2 @@ +[toolchain] +channel = "esp" diff --git a/bare-metal/esp32s3/src/main.rs b/bare-metal/esp32s3/src/main.rs new file mode 100644 index 0000000..5756e63 --- /dev/null +++ b/bare-metal/esp32s3/src/main.rs @@ -0,0 +1,101 @@ +//! rusty_zstd on an ESP32-S3, `no_std + alloc`. +//! +//! The point of this firmware is one line of output: a round trip that +//! happened on a part with no 64-bit atomics. Until this ran, "bare metal" +//! meant "the compiler accepted it". +//! +//! Xtensa LX7 is 32-bit, so `core::sync::atomic::AtomicU64` does not exist and +//! every census counter in the codec is the `census64` stub. `CENSUS_LIVE` is +//! printed so the log says which build this was. + +#![no_std] +#![no_main] + +extern crate alloc; + +use alloc::vec::Vec; +use esp_backtrace as _; + +// The image header espflash refuses to flash without. +esp_bootloader_esp_idf::esp_app_desc!(); +use esp_println::println; + +/// Compressible but not trivial: repeated phrases with varying joins, so the +/// match finder actually walks chains instead of emitting one long RLE. +fn corpus() -> Vec { + let words: [&str; 8] = [ + "the ", "quick ", "brown ", "fox ", "jumps ", "over ", "lazy ", "dog ", + ]; + let mut v: Vec = Vec::with_capacity(8 * 1024); + let mut x: u64 = 0x9E37_79B9_7F4A_7C15; + while v.len() < 8 * 1024 { + x = x + .wrapping_mul(6364136223846793005) + .wrapping_add(1442695040888963407); + v.extend_from_slice(words[((x >> 33) as usize) % words.len()].as_bytes()); + // Periodic long repeats, so matches run past the short-match path. + if (x >> 60) & 7 == 0 { + let take = core::cmp::min(v.len(), 512); + let tail: Vec = v[v.len() - take..].to_vec(); + v.extend_from_slice(&tail); + } + } + v +} + +#[esp_hal::main] +fn main() -> ! { + let _p = esp_hal::init(esp_hal::Config::default()); + esp_alloc::heap_allocator!(size: 192 * 1024); + + println!(); + println!("=== rusty_zstd on ESP32-S3 (xtensa, no_std + alloc) ==="); + println!( + "census64::CENSUS_LIVE = {} (false is expected here: no 64-bit atomics)", + rusty_zstd::census64::CENSUS_LIVE + ); + + let src = corpus(); + println!("source {} bytes", src.len()); + + let mut all_ok = true; + for level in [1i32, 3, 5] { + match rusty_zstd::compress(&src, level) { + Ok(z) => { + let ratio = src.len() as f32 / z.len() as f32; + match rusty_zstd::decompress(&z) { + Ok(back) => { + let ok = back.len() == src.len() && back == src; + all_ok &= ok; + println!( + "L{level} {} -> {} bytes ({:.2}x) round trip {}", + src.len(), + z.len(), + ratio, + if ok { "OK" } else { "MISMATCH" } + ); + } + Err(e) => { + all_ok = false; + println!("L{level} decompress FAILED: {e:?}"); + } + } + } + Err(e) => { + all_ok = false; + println!("L{level} compress FAILED: {e:?}"); + } + } + } + + println!(); + if all_ok { + println!("RESULT: PASS -- compressed and decompressed on the board"); + } else { + println!("RESULT: FAIL"); + } + + loop { + core::hint::spin_loop(); + } +}