diff --git a/src/Core.hs b/src/Core.hs
index 5401a98..34d0b6a 100644
--- a/src/Core.hs
+++ b/src/Core.hs
@@ -281,8 +281,7 @@ fetch = do
 decode :: (Access f) => CPUM f ()
 decode = do
   input <- ask
-  ctrl <- gets stateCtrl
-  status <- gets stateHalt
+  ctrl <- gets stateCtrl  
 
   ir <-
     if (inputIsInstr input)
@@ -294,6 +293,7 @@ decode = do
   let load_hazard_first_cycle = maybe False isNopLoadHazardFirstCycle (ctrlExInstr ctrl)
   let call_current_cycle = maybe False isCall (ctrlExInstr ctrl)
   let break_current_cycle = maybe False isBreak (ctrlExInstr ctrl)
+  let halted = maybe False isNopHalted (ctrlExInstr ctrl)
 
   let ir'
         -- If a branch was taken in this cycle, we stall.
@@ -309,7 +309,7 @@ decode = do
         -- If a break is executed in this cycle, we halt.
         | break_current_cycle = Nop Halted
         -- If the core is not running anymore, we halt.
-        | status /= Running = Nop Halted
+        | halted = Nop Halted
         -- Otherwise we process the decoded instruction.
         | otherwise = ir
 
@@ -395,10 +395,8 @@ execute = do
             PC -> gets $ pack . stateExPc
           let imm' = imm ++# (0 :: BitVector 12)
           pure (ADD, pure base', pure imm')
-        Instruction.IType (Env Call) _ _ _ ->
-          lift halt >> empty
-        Instruction.IType (Env Break) _ _ _ ->
-          lift halt >> empty
+        Instruction.IType (Env Call) _ _ _ -> empty
+        Instruction.IType (Env Break) _ _ _ -> empty
         Instruction.Nop _ -> empty
 
     rs1 :: MaybeT (CPUM f) (f Word)
@@ -492,12 +490,10 @@ memory = do
       setLines $ \c -> c {ctrlMeRegFwd = Just (rd, res)}
     Instruction.UType _ rd _ ->
       setLines $ \c -> c {ctrlMeRegFwd = Just (rd, res)}
-    Instruction.IType (Env Call) _ _ _ -> do
+    Instruction.IType (Env Call) _ _ _ ->
       setSyscall
-    Instruction.IType (Env Break) _ _ _ -> do
+    Instruction.IType (Env Break) _ _ _ ->
       halt
-    Instruction.Nop Halted -> do
-      halt    
     _ -> pure ()
 
 -- | Commit computations to the register file.
@@ -506,7 +502,6 @@ writeback = do
   input <- asks inputMem
   ir <- gets stateWbInstr
   res <- gets stateWbAluRes
-  status <- gets stateHalt
 
   case ir of
     Instruction.RType _ rd _ _ -> do
diff --git a/src/Instruction.hs b/src/Instruction.hs
index ad833fc..5cddcdf 100644
--- a/src/Instruction.hs
+++ b/src/Instruction.hs
@@ -22,6 +22,7 @@ module Instruction
     isCall,
     isNopBranchFirstCycle,
     isNopLoadHazardFirstCycle,
+    isNopHalted,
     break,
     loadHazard,
     isLoad,
@@ -450,6 +451,10 @@ isNopLoadHazardFirstCycle :: Instruction -> Bool
 isNopLoadHazardFirstCycle (Nop LoadHazardFirstCycle) = True
 isNopLoadHazardFirstCycle _ = False
 
+isNopHalted :: Instruction -> Bool
+isNopHalted (Nop Halted) = True
+isNopHalted _ = False
+
 break :: Instruction
 break = IType (Env Break) 0 0 0