diff --git a/CLAUDE.md b/CLAUDE.md index 299efebcf632..bc0694e59863 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -4,18 +4,26 @@ This file provides guidance to Claude Code (claude.ai/code) when working with co ## What this branch is -`openipc-novatek` is OpenIPC's U-Boot for Novatek's NA51089 camera SoCs: -the NT98562 (64 MiB of DDR in the package) and the NT98566 (128 MiB), one -Cortex-A9 each. The tree is **mainline U-Boot v2022.10**, the same release -as `openipc-hisilicon`, `openipc-xm`, `openipc-gk710x` and -`openipc-anyka`, plus: +`openipc-novatek` is OpenIPC's U-Boot for Novatek's camera SoCs: + +- NA51089, one Cortex-A9: the NT98560 (external DDR), NT98561 and NT98562 + (64 MiB of DDR in the package) and NT98566 (128 MiB); +- the NT9852x SDK's two dies, two Cortex-A9s each, NA51089's blocks at + NA51089's addresses: NA51055 (NT98520, NT98522, NT98523, NT98525) and + NA51084 (NT98528, NT98529); see "The NT9852x dies" below; + +and for two NVR dies, NA51103 and NA51090 (see "The NVR dies"). The tree +is **mainline U-Boot v2022.10**, the same release as `openipc-hisilicon`, +`openipc-xm`, `openipc-gk710x` and `openipc-anyka`, plus: - the OpenIPC boot layer, as on `openipc-anyka`; - the NA51089 support, written from the vendor sources: the NT9856x Linux SDK v1.01.007 (U-Boot 2019.04, kernel 4.19.91), and the device tree of a - Xiongmai NT98562 camera; -- the SDK's loader, which runs before U-Boot, as Novatek ships it - (`board/novatek/na51089/loader`), built from its sources. + Xiongmai NT98562 camera; the NT9852x support from that SDK's U-Boot + 2019.04 and board trees; +- the SDKs' loaders, which run before U-Boot, as Novatek ships them + (`board/novatek/na51089/loader`, `board/novatek/na51055/loader`), built + from their sources. CI and user docs live on the `openipc` branch: @@ -31,8 +39,12 @@ Adding or dropping a SoC needs both branches: `openipc/.dts`, and `TARGET_*` in `arch/arm/mach-novatek/Kconfig`; - there: `build-novatek.yml`'s matrices and the README. -The other dies of the SDKs (NA51055, NA51068, NA51090, NA51102, NA51103, -the NS02xxx parts) are not supported. +The NVR dies NA51103 (NT98332) and NA51090 (NT98633) are supported as +AArch64 targets behind the board's own loader and BL31 (see "The NVR +dies"), the NA51068 DVR/NVR die (NT98321, NT98323) on SPI NOR (see +"NA51068"), and NS02501 (NT98532, NT98533) with NA51089's layout and its +own loader (see "NS02501"). The other dies of the SDKs (NA51102, the +other NS02xxx parts) are not supported. ## Relationship to mainline @@ -88,6 +100,17 @@ DDR. Then, from `LibExt/LIBExt_src/Ctrl_Flow/bl_func.c`: `/nvt_memory_cfg/uboot`, and the 16-bit words plus their indices must sum to 0 over BinLength; then it calls CodeEntry. +**It calls CodeEntry with its MMU and caches on**: SCTLR 0x00c5187d, its +translation table at 0x1018000 (in its DRAM area, `/nvt_memory_cfg/loader`) +mapping the DDR write-back write-allocate and the registers as device +memory. This U-Boot runs with the data cache off and no cache maintenance +(`SYS_DCACHE_OFF`), so `cpu_init_cp15` has to run: `openipc_config` has +`SKIP_LOWLEVEL_INIT_ONLY` (no `lowlevel_init`, the loader has the clocks +and DDR up), not `SKIP_LOWLEVEL_INIT`, which skipped it too. Without it the +cache stayed live under the MAC's and the flash controller's DMA, and +anything loaded to 0x1000000 (`${baseaddr}`) overwrote the table. At the +prompt SCTLR reads 0x00c5187a. + `openipc/nvt-image.py` builds the 256 KiB image the programmer writes at offset 0: @@ -170,7 +193,7 @@ offset 0: ## Build ```sh -bash build.sh # both; continues past failures, exits non-zero if any failed +bash build.sh # every SoC; continues past failures, exits non-zero if any failed bash build.sh nt98566 # one or more SoCs (CROSS_COMPILE defaults to arm-linux-gnueabi-) ``` @@ -179,19 +202,25 @@ bash build.sh nt98566 # one or more SoCs (CROSS_COMPILE defaults to arm-li - `.config` is `openipc/openipc_config`, then `openipc/_config`, then `olddefconfig`. There are no `configs/*_defconfig` for these targets. - The loader uses `LOADER_CROSS_COMPILE`: `arm-none-eabi-` if there is one, - else `CROSS_COMPILE`. -- U-Boot is ~233 KiB, ~94 KiB packed, in the 128 KiB slot; + else `CROSS_COMPILE` (refused for the NT98528/529). +- U-Boot is ~233 KiB, ~94 KiB packed (NA51068: 242 KiB, 98 KiB), in the 128 KiB slot; `nvt-image.py` fails the build if a part does not fit. Check the packed size after enabling anything. +- nt98332 and nt98633 are AArch64: `CROSS_COMPILE_A64`, default + `aarch64-linux-gnu-` (Debian/Ubuntu `gcc-aarch64-linux-gnu`; CI must + install it). Their outputs are `output/u-boot-nt98332-nor.bin` / + `u-boot-nt98633-nand.bin` (U-Boot's slot alone) and + `u-boot--qemu.bin` (the stand-in's boot area, for CI). ## Verification -The emulator is OpenIPC/qemu-hisilicon, machines `nt98562`, `nt98566` -(`docs/novatek.md` there). `-M ,flash-file=` does the loader's -job (not the DDR training, so it does not run the loader): it reads the -device tree at 0x10000, unpacks U-Boot from its BCL1 container (LZMA -support is newer than the first NT9856x machines), fills SHMINFO and starts -it. +The emulator is OpenIPC/qemu-hisilicon (`docs/novatek.md` there), a +machine per SoC but the NT98520 and NT98522, which run on the NT98525's +and NT98523's (the same dies). Since OpenIPC/qemu-hisilicon#222, +`-M ,flash-file=` runs the image's own loader through a mask +ROM model: the DDR training, the device tree at 0x10000, U-Boot's BCL1 +container, SHMINFO, the jump. (Before, a stand-in did the loader's job +without running it.) - **CI smoke:** two boots of an 8 MiB image holding only the image. The second must load the environment the first saved. @@ -214,13 +243,232 @@ it. - SD (`-drive if=sd,index=0,format=raw,file=`): `mmc info`, `fatls`, `fatload` and `mmc read/write` against the host's CRCs; recovery of a changed kernel, and nothing rewritten with the same one. -- **What qemu does not check:** the loader at all (the DDR parameters, its - flash and BCL1 handling: the build is the vendor's, the toolchain is - not), the pin, clock, reset and pad set-up of every block, the flash - controller's timing, the PHY's power-on order and MDIO clock, the SD - host's command and FIFO timing. +- **What qemu does not check:** the DDR parameters against real DDR (the + model's training succeeds), caches, the pin, clock, reset and pad set-up + of every block, the flash controller's timing, the PHY's power-on order + and MDIO clock, the SD host's command and FIFO timing. - **On silicon:** nothing yet. +## NS02501: NT98532, NT98533 + +Two Cortex-A32s run in AArch32 (a GIC-400, the generic timer), chip ID +`0x5521`, NA51089's blocks at NA51089's addresses. `NVT_NS02501` +(`TARGET_NT98532`, `TARGET_NT98533`) builds the NA51089 board code with +the die's differences compiled in; the vendor sources are the NS02501 +SDK's U-Boot 2021.10 (`nvt_ns02501_a32`, `nvt-ns02501`, +`eth_ns02501.c`, `nvt_ivot_mmc_a64.c` + `_ns02501.h`, `nvt_flash_spi`). + +- **Loader** (`board/novatek/ns02501/loader`, `ns02501_loader_v3.07.101`): + 45056 bytes, its main part deflated (the SoC's gzip engine unpacks + it). `CHIP` is the package, `532BD` / `533QD` here (the SDK boards': + 2 Gbit, 1066 MHz; `Configram533` has every package's DDR parameters, + there is no ConfigRam directory). Built with `ROM_PUBLIC_API` off, it + has no ROM LZMA: it carries LzmaDec (`bl_lzma.c`), as NA51055's. Any + of arm-none-eabi, arm-linux-gnueabi 13 or 15 builds a working one. +- **The tree is packed.** The SDK trees are ~95 KiB (the vendor kernels + take their clocks from `nvt-clk` in them): `nvt-image.py --fdt-lzma` + puts the tree at 0x10000 in an LZMA BCL1 container (~8.5 KiB), which + the loader unpacks (`bl_load_fdt_from_flash()`). Same layout otherwise. +- **Memory:** 256 MiB; SHMINFO at the SDK's `0xA00000` (`NVT_SHMINFO`); + `osmem` 36M (the SDK boards'); `/hdal-memory` has two address cells + (`[DDR id][address]`), which `ft_board_setup()` follows. +- **Console** UART0 at 48 MHz (the vendor's `ns02501_a32.h`); timer 0 as + on NA51089; reset by the watchdog with CG+0x80 bit 8, CG+0x74 bit 19, + CTRL `0x102` (`ns02501_hw_init.c`). +- **Flash:** TOP+0x04 [13:12] = 1, pads off GPIO 0x140F, a 240 MHz + source, the tree's 12 MHz, fixed pad drive, output delay 3 from 48 MHz. +- **Ethernet:** its own pinmux bits (RMII_1 0x1, RMII_2 0x2, EXTPHYCLK + 0x100; the SDK boards' 0 is the embedded PHY), node `/eth0@f02b0000`, + PHY MDIO address 1, the vendor's default trims (its eFuse reader is + closed; Linux keeps what U-Boot set), AALE. +- **SD:** CGPIO13-18, clock source code 1 for 192 MHz (0 is 480 MHz), + 4-bit pad drive fields from PAD+0x50 (2 as the tree), the AXI channel + enabled. +- **Not done:** the CPU clock (left as the loader sets it; the vendor + caps it at 800 MHz without an eFuse code), the OTP 800 ms power-down + wait, an external PHY's EVB reset GPIO, pad power from the tree. +- **Other packages** (532QB..533BE): the same U-Boot with a loader + built for its `CHIP` and `NVT_DDR_SIZE` to match; no target each. + +Verified under qemu-hisilicon (`nt98532`, `nt98533`, images from CI's +toolchains, the real loader): two boots with the env kept; dhcp, ping, +3 MB tftp + crc32, unaligned `sf`, `mmc info`/`fatls`/write+read; +`reset` makes the watchdog reset the machine (`-no-reboot` exits), but +the model does not run its loader again after any reset, its own +`system_reset` too (its core reset register at `0xFFE40000` keeps its +value, so core 1, which trains the DDR, is not started again), so the +reboot itself is not seen; SCTLR `0x00c5187d` at U-Boot's entry, `0x00c5187a` at the prompt; +the SDK's 5.10.168 kernel boots to its shell with `/memory` +`<0 0x2400000>` and media `<0 0x2400000 0xdc00000>`. **On silicon:** +nothing yet. + +## The NT9852x dies: NA51055, NA51084 + +The NT9852x Linux SDK's dies: NA51055 (chip ID 0x4821; NT98520, NT98522, +NT98523, NT98525) and NA51084 (0x5021; NT98528, NT98529). Two Cortex-A9s +each, NA51089's blocks at NA51089's addresses; one U-Boot code base with +NA51089 (`NVT_NA51055`, board `na51089`), told apart at run time by the +chip ID (`nvt_chip_id()`), as the vendor's U-Boot 2019.04 does. + +- **The loader** (`board/novatek/na51055/loader`) is + `nt9852x_loader_release_v2.05.013`, the SDK's `na51055_ldr`: the + NA51089 loader's toolchain changes, plus + - an LZMA decoder (`bl_lzma.c`, U-Boot's `lib/lzma` LzmaDec): its mask + ROM has none and its own LZ leaves U-Boot ~176 KiB, past its 128 KiB + slot. The image is then the same as NA51089's. + - `LOADER_TYPE` follows `CHIP` (the 528/529 flow), through + `LibExt/LIBExt_src/Ctrl_Flow/Makefile`, which builds `bl_func.c`. + - The image is limited to 32 KiB (64 KiB for the 528 model): the 52x + loaders end at ~32.73 KiB; the 528 one is built without its own SD + card update (`STORAGEEXT=NONE`). + - The 528 model needs a bare-metal toolchain: built with + arm-linux-gnueabi it stops after the DDR training (why is open); + arm-none-eabi and the SDK's Linaro arm-eabi work. `build.sh` refuses + a Linux toolchain for it. +- **DDR** (`build.sh`): the NT98522/523's in the package (512 Mbit, + 1 Gbit) with no DDR2; the others' on the board, the SDK boards' 4 Gbit + DDR3 dies (NT98520: one; NT98525/528/529: two, the second at + 0x40000000, the media pool's alone, which `ft_board_setup()` keeps). + A board with other DDR needs its own loader build. +- **Device trees:** `openipc/na51055.dtsi` and `na51084.dtsi` are the + SDK's NT98525 and NT98528 NOR boards, flattened, with the OpenIPC chain + in `/nor`, U-Boot at 0x03900000 and the loader's scratch below it; the + parts' trees change what their SDK boards change. The SDK's NA51055 + boards describe one CPU, its NA51084 ones two (`cpu-release-addr` + 0xF07F8000). `osmem`: 64M on the NT98523 (its CMA is at 48 MiB), 256M + on the 512 MiB parts. +- **What differs from NA51089** (vendor `nvt_na51055_a32/clock.c`, + `eth_na51055.c`, `nvt_ivot_mmc.c`): + - PLL8's ratio at CG+0x1188 (NA51055) / CG+0x47E0 (NA51084); NA51084 + runs 1000 MHz unless the tree asks for 1200/1350, which only the + NT98529 gets. + - Ethernet: own pin and LED bits, the external PHY selected by bit 8 of + 0x3004, NA51084's RMII_2 and RGMII, no PHY PLL reset; the DMA's + descriptor skip counts in 4-byte units on NA51055, so the NT9852x + targets pack the descriptors (16 bytes; the data cache is off, a + build-time check says so); AALE. + - SD: NA51055 samples on the internal clock (SRC_CLK_SEL). + +## The NVR dies: NT98332 (NA51103), NT98633 (NA51090) + +Two (NA51103) or four (NA51090) Cortex-A53s, 1 / 2 GiB, the blocks at +`0x2_F000_0000` (`arch/arm/mach-novatek/include/mach/na511xx.h`), board +code in `board/novatek/na511xx/`, `NVT_NA511XX` selects `ARM64` +(`ARCH_NOVATEK` selects `CPU_V7A` only without it). + +**Boot chain, and why only U-Boot is replaced.** Mask ROM (AArch32) -> +the board's loader (Xiongmai's FW98332A, the NVR's FW98633A; no source +for these dies in any SDK) -> DDR training -> RMR warm reset of the A53s +into AArch64 -> the board's BL31 (TF-A v2.2, TZASC over its own +megabyte at `0x1F00000`) -> U-Boot -> Linux, which brings the other cores +up through BL31's PSCI. BL31 enters BL33 at the address in its own +header (written from `/nvt_memory_cfg/uboot`: `0x1E000000` / +`0x3E000000`) with a fixed SPSR `0x3C9`, AArch64 EL2h: U-Boot is AArch64 +and runs at EL2. The vendor's `_a32` configs are template copies and +cannot be entered from it. So the OpenIPC image is U-Boot's slot alone; +the loader, its tree and BL31 stay as the board has them. + +| | NT98332 (Xiongmai NBD80N36RA, 16 MiB NOR) | NT98633 (N2032-8HDD, 128 MiB SPI NAND) | +| --- | --- | --- | +| loader / tree / BL31 | `0x0` / `0x10000` (`XMFDT32G` + LZMA) / in the loader | `0x0` / `0x40000` / `0x80000` | +| U-Boot slot | `0x20000`, 128 KiB, bare LZMA (`5D`, 16 MiB dict, end marker) | `0xC0000`, 896 KiB, BCL1 alg 11 (size field = length twice) | +| environment | `0x40000` (OpenIPC NOR layout from here: kernel `0x50000`, rootfs `0x250000`) | `0x1A0000`, the board's uenv, 2 blocks | +| then | | UBI `0x1E0000`..end (rootfs UBIFS with `/boot/uImage`) | +| mtdparts | `spi_nor.0:` OpenIPC NOR list | `spi_nand.0:1664k(boot),256k(env),-(ubi)` | + +`openipc/nvt-nvr-image.py` builds the slot (HEADINFO length and +checksum as for NA51089, `BinFlag` 2); given a dump of the board's +flash it also writes a copy with the slot in. `${ubwrite}` writes only +the slot. Installing from the vendor U-Boot: tftp the slot, then +`sf erase 0x20000 0x20000; sf write 0x20000 0x20000` (NOR) or +`nand erase 0xc0000 0xe0000; nand write 0xc0000 0xe0000` (NAND). + +**Peripherals.** +- Console UART0 `0x2_F028_0000`, 16550, 48 MHz; the architected timer; + reset by the watchdog (NA51103 `0x60000`, NA51090 `0x110000`). +- MMU on (`mem_map` in `soc.c`): with it off every access is a device one + and U-Boot's unaligned accesses fault. Caches on, so the drivers' cache + maintenance matters. +- Flash: the NA51089 controller at `0x2_F018_0000`. NOR through + `nvt_sflash.c` (per-die clock/pins/PHY; 128-byte FIFO); SPI NAND + through `drivers/mtd/nand/raw/nvt_spinand.c`, the controller run as a + plain SPI master (not its NAND mode), the chip's on-die ECC on. +- Ethernet: `nvt_eqos.c` (MDC divider fixed for the 150 MHz APB). NA51103 + uses the MAC at `0x440000`, NA51090 the one at `0x210000` (the tree's + and Linux's eth0). Pins, clocks and the external PHY's reset GPIO come + from the loader's tree (`/top/eth` pinmux), as eth_na51103.c / + eth_na51090.c. phylib binds the PHY as MII, as the vendor does (its + strapped RGMII delays stay). +- Memory: U-Boot stays in its 32 MiB region; staging at `0x2000000` + (past BL31); the boot counter at `0x1E20000` (`0x1F20000` is BL31's); + `mem=` and `/hdal-memory/media` (4-cell addresses) split at `${osmem}` + (the boards' firmware: `0x15e00000`, `0x57600000`). The tree's + `/reserved-memory` keeps BL31 out of the kernel's and bootm's way. +- Not supported: SD (no slot on the NVRs), USB/SATA/HDMI in U-Boot, the + second MAC, the CPU clock raise the vendor U-Boot does from the tree. + +**Verified under qemu-hisilicon** (`nt98332`, `nt98633`, the boards' +dumps with the slot and env replaced, the real loader and BL31): prompt +twice with the env kept; `sf`/`nand` erase/write/read + `crc32` +(unaligned on NOR); `saveenv` + `reset`; `ping`, `dhcp`, `tftpboot` 3 MB +with the host's crc32; UBI create/write/read across a reset; TFTP +recovery onto an empty flash then boot from it (NOR: squashfs layout; +NAND: UBIFS `/boot/uImage`); the boot limit's failsafe; the dumps' own +4.19 kernels boot (their uImages say "uncompressed" over LZMA data: +repack them with `-C lzma`). CI smoke: `u-boot--qemu.bin` on the +stand-in loader (`-smp 2` / `-smp 4`). Not checked: the boards' DDR +contents across a watchdog reset (the boot counter), the controller's +timing and the NAND's ECC error paths, the PHYs. **On silicon:** +nothing yet. +## NA51068 + +The NT9832x SDK v1.02.024's die: NT98321 (DDR3) and NT98323 (DDR4), two +Cortex-A9s (MPCore at `0xF9C00000`), Faraday-heritage peripherals, +external DDR (512 MiB or more on every SDK board). `TARGET_NT98321`, +`TARGET_NT98323`, `NVT_NA51068`; `board/novatek/na51068`, +`arch/arm/mach-novatek/na51068.c`, `include/mach/na51068.h`, +`openipc/na51068.dtsi` (the SDK's `cfg_98323_DDR4_4GX1_NOR_EVB` tree with +the OpenIPC `/nor` chain; `nt98321.dts` changes what the 321 EVB does). + +- **Boot:** as NA51089, same image (`nvt-image.py`): loader 0 (64 KiB), + tree 0x10000, BCL1 LZMA U-Boot 0x20000. The loader + (`board/novatek/na51068/loader`, `na51068_loader_v1.08.014`) runs from + SRAM `0xFE080000` and then from DDR `0x100000`; its mask ROM has no + routines, its LZMA decoder is `lzma_inflate()` of its own `Compress.a` + (OpenIPC hooks algorithm 11 to it). Models `323_DDR4_4GX1_NOR_EVB` and + `321_DDR3_4GX1_NOR_EVB` (SpiFlash, `STORAGEEXT NONE`: with the SD + update code the image is over 64 KiB). The tree goes to `0x80000`, + SHMINFO `0xA00000`, U-Boot `0x1E000000` (the SDK's), the second core's + pen `0x1FF80000` (HEADINFO BinCtrl SMP). +- **The loader jumps with its MMU on**, page tables in its DDR region: + `SKIP_LOWLEVEL_INIT_ONLY` (not `SKIP_LOWLEVEL_INIT`) so that + `cpu_init_cp15` turns it off; else writes to `0x100000+` hang. +- **Timer:** the A9 global timer at PLL16's rate (CG `0x107C0`+0x20..28, + 12 MHz x ratio / 2^17; an eighth of the CPU). The CPU clock is the + loader's: the vendor U-Boot's raise to 1400 MHz needs the core voltage + set by PWM from eFuse trim, not ported. +- **Console** UART0 `0xFE200000`, 48 MHz. **Reset** the watchdog + `0xFE8A0000`, as the vendor kernel. +- **SPI NOR:** FTSPI020 `0xFA900000`, `drivers/mtd/spi/nvt_spi020.c` + (`NVT_SPI020`), PIO, single lane, 4-byte opcodes past 16 MiB. +- **Ethernet:** two `nvt_eqos` MACs (`0xFCC00000` eth0, `0xFCD00000` + eth1), each RGMII, RMII or the embedded PHY per `/top@fe030000/eth` + pinmux (`0x1201`: MAC0 RGMII, embedded PHY on MAC1). Both registered; + `eth_init` moves on to the next without link. +- **SD:** a standard SDHCI at `0xFA600000`, mainline `sdhci.c` non-DM + (`add_sdhci`). +- **Kernel:** `osmem` 192M (323) / 160M (321) as the SDK boards; + `CONFIG_SYS_BOOTMAPSZ` 128 MiB: the SDK's kernel 4.9 hangs silently + with the tree and initrd just below 192 MiB. +- **NAND:** the qemu machine picks NAND for a 128/256 MiB image; NT98321 + boards usually boot from SPI NAND, which needs a SPI020 NAND driver and + a UBI layout: not done. +- **Verified under qemu** (`-M nt98323` / `nt98321`, real loader): two-boot + smoke; `sf` read/erase/write at odd offsets (16 and 32 MiB); `saveenv` + + `reset`; dhcp, ping, 3 MB tftp on both MACs; SD `mmc read/write`, + `fatls`, recovery of `uImage..img`; the SDK's kernel 4.9.118 + + NT9852x ramdisk to a shell with `${fdtaddr}`. **On silicon:** nothing. + ## Things to keep - `mem=` stays the first kernel argument, as on the other OpenIPC targets. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2eb661b2b4ee..412f077e976a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -824,13 +824,16 @@ config ARCH_K3 select FIT config ARCH_NOVATEK - bool "Novatek NA51089 IP camera SoCs" - select CPU_V7A + bool "Novatek IP camera and NVR SoCs" + select CPU_V7A if !ARM64 select CREATE_ARCH_SYMLINK help - Novatek's NT98562 and NT98566: one Cortex-A9 with DDR in the - package. The mask ROM starts the vendor loader, which trains the - DDR, loads U-Boot as its device tree describes and starts it. + Novatek's NA51089 cameras (one Cortex-A9) and NA51103 / NA51090 + NVRs (Cortex-A53s, AArch64; the SoC selects ARM64). The mask ROM + starts the vendor loader, which trains the DDR, loads U-Boot as + its device tree describes and starts it, on the NVRs through the + board's BL31. + Also the NA51068 DVR/NVR die (NT98321, NT98323), two Cortex-A9s. config ARCH_OMAP2PLUS bool "TI OMAP2+" diff --git a/arch/arm/mach-novatek/Kconfig b/arch/arm/mach-novatek/Kconfig index 61d82d704751..146c500d47c7 100644 --- a/arch/arm/mach-novatek/Kconfig +++ b/arch/arm/mach-novatek/Kconfig @@ -4,6 +4,18 @@ choice prompt "Novatek SoC" default TARGET_NT98562 +config TARGET_NT98560 + bool "NT98560" + select NVT_NA51089 + help + NA51089 with external DDR3, 512 MiB on the SDK's board. + +config TARGET_NT98561 + bool "NT98561" + select NVT_NA51089 + help + NA51089 with 64 MiB of DDR2 in the package, as the NT98562. + config TARGET_NT98562 bool "NT98562" select NVT_NA51089 @@ -16,11 +28,163 @@ config TARGET_NT98566 help NA51089 with 128 MiB of DDR3 in the package. +config TARGET_NT98520 + bool "NT98520" + select NVT_NA51055 + help + NA51055 (two Cortex-A9s) with external DDR3, one die, 512 MiB + as the loader is built. + +config TARGET_NT98522 + bool "NT98522" + select NVT_NA51055 + help + NA51055 with 64 MiB of DDR in the package. + +config TARGET_NT98523 + bool "NT98523" + select NVT_NA51055 + help + NA51055 with 128 MiB of DDR in the package. + +config TARGET_NT98525 + bool "NT98525" + select NVT_NA51055 + help + NA51055 with two external DDR3 dies, 512 MiB each on the SDK's + board; U-Boot uses the first. + +config TARGET_NT98528 + bool "NT98528" + select NVT_NA51055 + help + NA51084 (two Cortex-A9s, the NT9852x SDK's other die) with two + external DDR3 dies, 512 MiB each on the SDK's board. + +config TARGET_NT98529 + bool "NT98529" + select NVT_NA51055 + help + NA51084 as the NT98528, its CPU cleared for 1.2 GHz. + +config TARGET_NT98532 + bool "NT98532" + select NVT_NS02501 + help + NS02501 (two Cortex-A32s, AArch32 only) with 256 MiB of DDR, as + the SDK's 532BD NOR board. + +config TARGET_NT98533 + bool "NT98533" + select NVT_NS02501 + help + NS02501 with 256 MiB of DDR in the package (533QD), as the SDK's + 533QD boards. + +config TARGET_NT98332 + bool "NT98332 (NA51103)" + select NVT_NA51103 + help + NA51103, the NVR die with two Cortex-A53s, 1 GiB of DDR on the + boards. U-Boot runs in AArch64 at EL2, started by the board's + BL31. + +config TARGET_NT98633 + bool "NT98633 (NA51090)" + select NVT_NA51090 + help + NA51090, the NVR die with four Cortex-A53s, 2 GiB of DDR on the + boards. U-Boot runs in AArch64 at EL2, started by the board's + BL31. + +config TARGET_NT98321 + bool "NT98321" + select NVT_NA51068 + help + NA51068 (DVR/NVR, two Cortex-A9s) with external DDR3, 512 MiB on + the SDK's board, booting from SPI NOR. + +config TARGET_NT98323 + bool "NT98323" + select NVT_NA51068 + help + NA51068 (DVR/NVR, two Cortex-A9s) with external DDR4, 512 MiB on + the SDK's NOR board. + endchoice config NVT_NA51089 bool +config NVT_NA51055 + bool + help + The NT9852x SDK's dies, NA51055 and NA51084: NA51089's blocks at + NA51089's addresses, two Cortex-A9s, their own loader + (board/novatek/na51055/loader). The chip ID tells them apart. + +config NVT_NS02501 + bool + help + The NT98532/NT98533 die: NA51089's blocks at NA51089's addresses, + two Cortex-A32s run in AArch32 with a GIC-400 and the generic + timer, its own loader (board/novatek/ns02501/loader). + +# The NVR dies: the board's loader warm-resets the A53s into AArch64 and +# its BL31 (TF-A v2.2) enters U-Boot at EL2 with a fixed SPSR (0x3C9), so +# U-Boot is an AArch64 one. +config NVT_NA511XX + bool + select ARM64 + +config NVT_NA51103 + bool + select NVT_NA511XX + +config NVT_NA51090 + bool + select NVT_NA511XX + +config NVT_NA51068 + bool + +config NVT_DDR_SIZE + hex + default 0x80000000 if TARGET_NT98633 + default 0x40000000 if TARGET_NT98332 + default 0x20000000 if TARGET_NT98560 || NVT_NA51068 + default 0x08000000 if TARGET_NT98566 + default 0x20000000 if TARGET_NT98520 || TARGET_NT98525 + default 0x20000000 if TARGET_NT98528 || TARGET_NT98529 + default 0x08000000 if TARGET_NT98523 + default 0x10000000 if NVT_NS02501 + default 0x04000000 + help + The DDR at 0: the package's, or the board's for a part with + external DDR, as its loader is built. A second DDR die (at + 0x40000000 on NA51055 / NA51084) is the media pool's alone. On NA51068 + the loader's device tree (/nvt_memory_cfg/dram) says it; this is + the fallback. + +config NVT_OSMEM + string + default "0x57600000" if NVT_NA51090 + default "0x15e00000" if NVT_NA51103 + default "160M" if TARGET_NT98321 + default "192M" if TARGET_NT98323 + default "256M" if NVT_DDR_SIZE >= 0x20000000 + default "64M" if TARGET_NT98523 + default "36M" if NVT_NS02501 + default "32M" + help + What Linux gets of the DDR by default (osmem, mem=); the vendor + media modules get the rest. 32M is what OpenIPC's install guide + sets on the NT98562/566's vendor U-Boot; larger parts give Linux + what their SDK board does (the NT98523's tree keeps its CMA at + 48 MiB; the NS02501 boards give Linux 36 MiB), the NVRs what + their firmware sets (Xiongmai's NT98332 NVR 0x15e00000, the + NT98633 NVR's tree 0x57600000). + config SYS_SOC default "novatek" @@ -28,6 +192,8 @@ config SYS_VENDOR default "novatek" config SYS_BOARD + default "na511xx" if NVT_NA511XX + default "na51068" if NVT_NA51068 default "na51089" config SYS_CONFIG_NAME diff --git a/arch/arm/mach-novatek/Makefile b/arch/arm/mach-novatek/Makefile index aa1026bf7d81..164aa07e2f1f 100644 --- a/arch/arm/mach-novatek/Makefile +++ b/arch/arm/mach-novatek/Makefile @@ -1,3 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ +# NA51068 (its own map and timer) has na51068.c; every other die soc.c +ifdef CONFIG_NVT_NA51068 +obj-y += na51068.o +else obj-y += soc.o +endif diff --git a/arch/arm/mach-novatek/include/mach/hardware.h b/arch/arm/mach-novatek/include/mach/hardware.h new file mode 100644 index 000000000000..5359097c586a --- /dev/null +++ b/arch/arm/mach-novatek/include/mach/hardware.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * The memory map of the Novatek die U-Boot is built for: the drivers and + * the board code include this rather than a die's own header. + */ + +#ifndef __NVT_HARDWARE_H +#define __NVT_HARDWARE_H + +#if defined(CONFIG_NVT_NA511XX) +#include +#elif defined(CONFIG_NVT_NA51068) +#include +#else +#include +#endif + +#ifndef __ASSEMBLY__ +/* The device tree the loader left (SHMINFO), or NULL */ +const void *nvt_loader_fdt(void); +#endif + +#endif diff --git a/arch/arm/mach-novatek/include/mach/na51068.h b/arch/arm/mach-novatek/include/mach/na51068.h new file mode 100644 index 000000000000..c8db5604b797 --- /dev/null +++ b/arch/arm/mach-novatek/include/mach/na51068.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Novatek NA51068 (NT98321, NT98323): memory map, after the NT9832x SDK's + * U-Boot 2016.07 (arch-nvt-na51068/IOAddress.h), kernel 4.9.118 + * (plat-na51068) and board device trees. + */ + +#ifndef __NA51068_H +#define __NA51068_H + +#include + +#define NVT_DDR_BASE 0x00000000 + +#define NVT_SCU_BASE 0xF9C00000 /* A9 MPCore: SCU, GIC, timers */ +#define NVT_GTIMER_BASE (NVT_SCU_BASE + 0x200) +#define NVT_PL310_BASE 0xF9C20000 +#define NVT_SDHCI_BASE 0xFA600000 +#define NVT_FLASH_BASE 0xFA900000 /* Faraday FTSPI020 */ +#define NVT_ETH0_BASE 0xFCC00000 +#define NVT_ETH1_BASE 0xFCD00000 +#define NVT_CG_BASE 0xFE000000 /* clocks, PLLs, resets */ +#define NVT_TOP_BASE 0xFE030000 /* pinmux, chip ID */ +#define NVT_PAD_BASE 0xFE040000 +#define NVT_UART0_BASE 0xFE200000 +#define NVT_GPIO1_BASE 0xFE420000 +#define NVT_GPIO2_BASE 0xFE440000 +#define NVT_WDT_BASE 0xFE8A0000 + +/* TOP */ +#define NVT_TOP_CHIP_ID (NVT_TOP_BASE + 0xF0) /* [31:16] */ + +/* CG: the CPU's clock, from PLL16, eight times its rate */ +#define NVT_CG_CPU_CKCTRL (NVT_CG_BASE + 0x100) +#define NVT_CPU_CK_APLL BIT(31) /* else 80 MHz */ +#define NVT_CG_PLL16 (NVT_CG_BASE + 0x107C0) /* ratio at +0x20/24/28 */ + +/* + * The A9 global timer counts at PLL16's rate, an eighth of the CPU's: + * the loader leaves it as it is, the vendor U-Boot enables it. + */ +#define NVT_GTIMER_LO (NVT_GTIMER_BASE + 0x00) +#define NVT_GTIMER_HI (NVT_GTIMER_BASE + 0x04) +#define NVT_GTIMER_CTRL (NVT_GTIMER_BASE + 0x08) + +/* Watchdog: every CTRL write carries the key in [31:16] */ +#define NVT_CG_APB_RSTN (NVT_CG_BASE + 0x5C) +#define NVT_CG_WDT_RSTN BIT(28) +#define NVT_CG_APB_GATE (NVT_CG_BASE + 0x78) +#define NVT_CG_WDT_GATE BIT(15) +#define NVT_WDT_CTRL (NVT_WDT_BASE + 0x00) +#define NVT_WDT_MANUAL (NVT_WDT_BASE + 0x0C) +#define NVT_WDT_KEY 0x5A960000 +#define NVT_WDT_EN BIT(0) + +/* + * What the loader leaves in DDR (the /nvt_memory_cfg node of its device + * tree, openipc/na51068.dtsi): the device tree at 0x80000, SHMINFO at + * 0xA00000, its own code from 0x100000. U-Boot runs where + * /nvt_memory_cfg/uboot says: at 0x1E000000, as on every board of the + * SDK (all have 512 MiB or more), above Linux's memory and its CMA pools + * (0x02000000-0x04800000), below the second core's pen at 0x1FF80000. + */ +#define NVT_SHMINFO (NVT_DDR_BASE + 0x00A00000) +#define NVT_SHM_LD_NVT 0x00 /* "LD_NVT" */ +#define NVT_SHM_FDT_ADDR 0x2C +#define NVT_UBOOT_BASE (NVT_DDR_BASE + 0x1E000000) +#define NVT_UBOOT_SIZE 0x01F80000 + +#ifndef __ASSEMBLY__ +/* The loader's device tree, from SHMINFO, or NULL (mach-novatek/na51068.c) */ +const void *nvt_loader_fdt(void); +#endif + +#endif diff --git a/arch/arm/mach-novatek/include/mach/na51089.h b/arch/arm/mach-novatek/include/mach/na51089.h index da529981161d..d1c87b31ad88 100644 --- a/arch/arm/mach-novatek/include/mach/na51089.h +++ b/arch/arm/mach-novatek/include/mach/na51089.h @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Novatek NA51089 (NT98562, NT98566): memory map, after the vendor - * U-Boot 2019.04 (arch-nvt-na51089_a32/IOAddress.h) and the SDK's - * device trees. + * Novatek NA51089 (NT98560/561/562/566), and NA51055 / NA51084 + * (NT98520/522/523/525/528/529) and NS02501 (NT98532/533), which share + * its map: after the vendor U-Boots 2019.04 and 2021.10 + * (arch-nvt-na51089_a32/IOAddress.h, arch-nvt-na51055_a32/IOAddress.h, + * arch-nvt-ns02501_a32/IOAddress.h) and the SDKs' device trees. */ #ifndef __NA51089_H @@ -25,15 +27,37 @@ #define NVT_SDIO1_BASE 0xF0420000 #define NVT_PL310_BASE 0xFFE00000 -/* TOP */ +/* + * TOP. NA51055 (NT98520/522/523/525) and NA51084 (NT98528/529), the + * NT9852x SDK's two dies, have NA51089's blocks at NA51089's addresses; + * the vendor's code tells them apart at run time by this ID. + */ #define NVT_TOP_CHIP_ID (NVT_TOP_BASE + 0xF0) /* [31:16] */ #define NVT_CHIP_NA51089 0x7021 +#define NVT_CHIP_NA51055 0x4821 +#define NVT_CHIP_NA51084 0x5021 +/* NS02501, two Cortex-A32s (AArch32 only): its own targets (NVT_NS02501) */ +#define NVT_CHIP_NS02501 0x5521 + +#ifndef __ASSEMBLY__ +static inline unsigned int nvt_chip_id(void) +{ + return *(volatile unsigned int *)NVT_TOP_CHIP_ID >> 16; +} +#endif /* CG: per-module clock enables and resets (active low) */ #define NVT_CG_CLKEN0 (NVT_CG_BASE + 0x74) #define NVT_CG_RSTN0 (NVT_CG_BASE + 0x84) #define NVT_CG_FLASH BIT(0) +#ifdef CONFIG_NVT_NS02501 +/* NS02501: the watchdog's clock in CLKEN0, its reset in the word before */ +#define NVT_CG_WDT BIT(19) +#define NVT_CG_WDT_RSTN (NVT_CG_BASE + 0x80) +#define NVT_CG_WDT_RST BIT(8) +#else #define NVT_CG_WDT BIT(17) +#endif /* * Timer 0 of the twenty in the timer block: the loader leaves it running @@ -46,15 +70,21 @@ /* Watchdog: every CTRL write carries the key in [31:16] */ #define NVT_WDT_CTRL (NVT_WDT_BASE + 0x00) #define NVT_WDT_MANUAL (NVT_WDT_BASE + 0x0C) +#define NVT_WDT_DATA (NVT_WDT_BASE + 0x84) #define NVT_WDT_KEY 0x5A960000 #define NVT_WDT_EN BIT(0) /* * What the loader leaves in DDR (the /nvt_memory_cfg node of its device - * tree): the device tree at 0x100000 and the SHMINFO block at 0x200000. - * U-Boot runs where /nvt_memory_cfg/uboot says. + * tree): the device tree at 0x100000 and the SHMINFO block at 0x200000 + * (0xA00000 in the NS02501 SDK's trees, which openipc/ns02501.dtsi + * keeps). U-Boot runs where /nvt_memory_cfg/uboot says. */ +#ifdef CONFIG_NVT_NS02501 +#define NVT_SHMINFO (NVT_DDR_BASE + 0x00A00000) +#else #define NVT_SHMINFO (NVT_DDR_BASE + 0x00200000) +#endif #define NVT_SHM_LD_NVT 0x00 /* "LD_NVT" */ #define NVT_SHM_FDT_ADDR 0x2C /* /nvt_memory_cfg/uboot: where U-Boot is loaded, and where it stays */ diff --git a/arch/arm/mach-novatek/include/mach/na511xx.h b/arch/arm/mach-novatek/include/mach/na511xx.h new file mode 100644 index 000000000000..b434c972f1ac --- /dev/null +++ b/arch/arm/mach-novatek/include/mach/na511xx.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Novatek NA51103 (NT98332) and NA51090 (NT98633), the NVR dies: memory + * map, after the vendor U-Boot 2019.04 (arch-nvt-na51103_a64/IOAddress.h, + * arch-nvt-na51090_a64/IOAddress.h) and the boards' device trees. The + * blocks sit above 4 GiB, at 0x2_F000_0000; most keep the NA51089 + * register layout at new offsets. + */ + +#ifndef __NA511XX_H +#define __NA511XX_H + +#include + +#define NVT_DDR_BASE 0x00000000 +#define NVT_IO(off) (0x2F0000000UL + (off)) + +#define NVT_TOP_BASE NVT_IO(0x010000) /* pinmux, chip ID */ +#define NVT_CG_BASE NVT_IO(0x020000) /* clocks, resets */ +#define NVT_PAD_BASE NVT_IO(0x030000) +#define NVT_GPIO_BASE NVT_IO(0x040000) +#define NVT_FLASH_BASE NVT_IO(0x180000) +#define NVT_UART0_BASE NVT_IO(0x280000) +#ifdef CONFIG_NVT_NA51090 +#define NVT_WDT_BASE NVT_IO(0x110000) +/* The boards' tree's eth0, Linux's (the vendor U-Boot's MAC1) */ +#define NVT_ETH_BASE NVT_IO(0x210000) +#else +#define NVT_WDT_BASE NVT_IO(0x060000) +#define NVT_ETH_BASE NVT_IO(0x440000) +#endif +#define NVT_IO_SIZE 0x10000000 /* to 0x2_FFFF_FFFF */ + +/* TOP */ +#define NVT_TOP_CHIP_ID (NVT_TOP_BASE + 0xF0) /* [31:16] */ +#define NVT_CHIP_NA51103 0x8B20 +#define NVT_CHIP_NA51090 0xBC21 + +/* CG: per-module clock enables and resets (active low) */ +#define NVT_CG_WDT_CLKEN (NVT_CG_BASE + 0x7C) +#define NVT_CG_WDT_RSTN (NVT_CG_BASE + 0x9C) +#define NVT_CG_WDT_EN BIT(4) +#define NVT_CG_WDT_RST BIT(12) + +/* Watchdog: every CTRL write carries the key in [31:16] */ +#define NVT_WDT_CTRL (NVT_WDT_BASE + 0x00) +#define NVT_WDT_MANUAL (NVT_WDT_BASE + 0x0C) +#define NVT_WDT_KEY 0x5A960000 +#define NVT_WDT_EN BIT(0) + +/* The MAC's CSR clock is the 150 MHz APB: MDC divider CR 1 (/62) */ +#define NVT_ETH_MDIO_CR 1 + +/* UART0, a 16550 with 32-bit registers */ +#define NVT_UART_HZ 48000000 + +/* + * What the loader leaves in DDR (/nvt_memory_cfg of its device tree): + * the device tree at 0x100000, SHMINFO at 0xA00000, BL31 at 0x1F00000 + * (secure, kept out of reach: no-map in the kernel's tree too), and + * U-Boot where /nvt_memory_cfg/uboot says, 32 MiB below the end of the + * first 512 MiB / 1 GiB. + */ +#define NVT_SHMINFO (NVT_DDR_BASE + 0x00A00000) +#define NVT_SHM_LD_NVT 0x00 /* "LD_NVT" */ +#define NVT_SHM_FDT_ADDR 0x2C +#define NVT_BL31_BASE (NVT_DDR_BASE + 0x01F00000) +#define NVT_BL31_SIZE 0x00100000 +#ifdef CONFIG_NVT_NA51090 +#define NVT_UBOOT_BASE (NVT_DDR_BASE + 0x3E000000) +#else +#define NVT_UBOOT_BASE (NVT_DDR_BASE + 0x1E000000) +#endif +#define NVT_UBOOT_SIZE 0x02000000 + +#endif diff --git a/arch/arm/mach-novatek/na51068.c b/arch/arm/mach-novatek/na51068.c new file mode 100644 index 000000000000..19d405571f82 --- /dev/null +++ b/arch/arm/mach-novatek/na51068.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Novatek NA51068: the loader's HEADINFO, the timer, reset and the DRAM + * size. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * HEADINFO, at 0x300 into the image (board/novatek/na51068/u-boot.lds), + * as on NA51089. The loader starts U-Boot at CodeEntry, and refuses an + * image whose CodeEntry is not where its device tree's + * /nvt_memory_cfg/uboot puts it. openipc/nvt-image.py fills in the length + * and the checksum. BinCtrl bit 1 (SMP), as the vendor U-Boot sets it for + * its SMP kernels: the loader then parks the second core at + * /nvt_memory_cfg/core2entry2, where Linux releases it (cpu-release-addr). + */ +struct nvt_headinfo { + u32 code_entry; + u32 resv1[19]; /* written by the loader */ + char chip_name[8]; + char version[8]; + char date[8]; + u32 bin_length; + u32 checksum; + u32 crc_len_check; + u32 modelext_addr; /* the loader writes its FDT address here */ + u32 bin_ctrl; + u32 crc_tag; +}; + +#define NVT_BIN_CTRL_SMP BIT(1) + +static const struct nvt_headinfo headinfo + __used __section(".nvt_headinfo") = { + .code_entry = CONFIG_SYS_TEXT_BASE, + .chip_name = "ub51068 ", + .version = "OpenIPC ", + .date = " ", + .bin_length = 0xffffffff, + .checksum = 0xffffffff, + .bin_ctrl = NVT_BIN_CTRL_SMP, +}; + +/* PLL16, in Hz: 12 MHz times its 24-bit ratio over 2^17 */ +static ulong nvt_pll16_hz(void) +{ + u32 ratio = (readl(NVT_CG_PLL16 + 0x20) & 0xff) | + (readl(NVT_CG_PLL16 + 0x24) & 0xff) << 8 | + (readl(NVT_CG_PLL16 + 0x28) & 0xff) << 16; + + return ((u64)ratio * 12000000) >> 17; +} + +/* The CPU's clock: eight times PLL16, or 80 MHz off the APLL */ +static ulong nvt_cpu_hz(void) +{ + if (!(readl(NVT_CG_CPU_CKCTRL) & NVT_CPU_CK_APLL)) + return 80000000; + return nvt_pll16_hz() * 8; +} + +/* + * The A9 global timer, 64 bits at an eighth of the CPU's clock. The CPU + * clock is the loader's: the vendor U-Boot raises it to the device tree's + * after setting the core voltage from the eFuse trim, which is not done + * here. + */ +int timer_init(void) +{ + gd->arch.timer_rate_hz = nvt_cpu_hz() / 8; + setbits_le32(NVT_GTIMER_CTRL, BIT(0)); + return 0; +} + +ulong get_tbclk(void) +{ + return gd->arch.timer_rate_hz; +} + +uint64_t notrace get_ticks(void) +{ + u32 hi, lo; + + do { + hi = readl(NVT_GTIMER_HI); + lo = readl(NVT_GTIMER_LO); + } while (hi != readl(NVT_GTIMER_HI)); + return (u64)hi << 32 | lo; +} + +/* + * As the vendor kernel resets (plat-na51068/reset.c): the watchdog's + * clock and reset, then its manual trigger + */ +void reset_cpu(void) +{ + clrbits_le32(NVT_CG_APB_RSTN, NVT_CG_WDT_RSTN); + udelay(50); + setbits_le32(NVT_CG_APB_RSTN, NVT_CG_WDT_RSTN); + clrbits_le32(NVT_CG_APB_GATE, NVT_CG_WDT_GATE); + writel(NVT_WDT_KEY | 0x112, NVT_WDT_CTRL); + udelay(80); + writel(NVT_WDT_KEY | 0x112 | NVT_WDT_EN, NVT_WDT_CTRL); + writel(1, NVT_WDT_MANUAL); + while (1) + ; +} + +/* The loader's device tree, from SHMINFO, or NULL */ +const void *nvt_loader_fdt(void) +{ + const void *shm = (const void *)NVT_SHMINFO; + const void *fdt; + + if (memcmp(shm + NVT_SHM_LD_NVT, "LD_NVT", 6)) + return NULL; + fdt = (const void *)readl(shm + NVT_SHM_FDT_ADDR); + return fdt_check_header(fdt) ? NULL : fdt; +} + +/* + * The DDR is on the board: its size is what the loader's device tree + * says (/nvt_memory_cfg/dram), which its DDR set-up was built for + */ +int dram_init(void) +{ + const void *fdt = nvt_loader_fdt(); + const fdt32_t *reg = NULL; + int node, len; + + gd->ram_size = PHYS_SDRAM_1_SIZE; + if (fdt) { + node = fdt_path_offset(fdt, "/nvt_memory_cfg/dram"); + if (node >= 0) + reg = fdt_getprop(fdt, node, "reg", &len); + if (reg && len == 8 && fdt32_to_cpu(reg[1])) + gd->ram_size = fdt32_to_cpu(reg[1]); + } + return 0; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + printf("CPU: Novatek %s @ %lu MHz\n", CONFIG_PRODUCT_SOC, + (nvt_cpu_hz() + 500000) / 1000000); + return 0; +} +#endif diff --git a/arch/arm/mach-novatek/soc.c b/arch/arm/mach-novatek/soc.c index 9cc80ef42561..d72fabba00c3 100644 --- a/arch/arm/mach-novatek/soc.c +++ b/arch/arm/mach-novatek/soc.c @@ -1,16 +1,23 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Novatek NA51089: the loader's HEADINFO, reset and DRAM size. The - * timer is timer 0 of the timer block, which the loader leaves running - * (CONFIG_SYS_TIMER_COUNTER in include/configs/novatek.h). + * Novatek: the loader's HEADINFO, reset and DRAM size. On NA51089, + * NA51055, NA51084 and NS02501 the timer is timer 0 of the timer block, + * which the loader leaves running (CONFIG_SYS_TIMER_COUNTER in + * include/configs/novatek.h); on the AArch64 NVR dies (NA51103, NA51090) + * it is the architected timer, and the MMU maps the DDR and the blocks + * above 4 GiB. */ #include #include #include #include -#include +#include +#ifdef CONFIG_ARM64 +#include +#endif #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -37,27 +44,99 @@ struct nvt_headinfo { static const struct nvt_headinfo headinfo __used __section(".nvt_headinfo") = { .code_entry = CONFIG_SYS_TEXT_BASE, + /* The vendor U-Boot's tag; no loader checks it */ +#if defined(CONFIG_NVT_NA51103) + .chip_name = "ub51103 ", +#elif defined(CONFIG_NVT_NA51090) + .chip_name = "ub51090 ", +#elif defined(CONFIG_NVT_NA51055) + .chip_name = "ub51055 ", +#elif defined(CONFIG_NVT_NS02501) + .chip_name = "ub02501 ", +#else .chip_name = "ub51089 ", +#endif .version = "OpenIPC ", .date = " ", .bin_length = 0xffffffff, .checksum = 0xffffffff, +#ifdef CONFIG_NVT_NA511XX + /* As the vendor's SMP builds: Linux brings up the other cores */ + .bin_ctrl = 2, +#endif }; -/* As the vendor U-Boot resets: the watchdog, then its manual trigger */ +const void *nvt_loader_fdt(void) +{ + const void *shm = (const void *)NVT_SHMINFO; + const void *fdt; + + if (memcmp(shm + NVT_SHM_LD_NVT, "LD_NVT", 6)) + return NULL; + fdt = (const void *)(ulong)readl(shm + NVT_SHM_FDT_ADDR); + return fdt_check_header(fdt) ? NULL : fdt; +} + +/* + * As the vendor U-Boot resets: the watchdog, then its manual trigger. + * CTRL is written as each vendor U-Boot writes it: 0x112 under the key, + * 0x102 on NS02501 (ns02501_hw_init.c). + */ +#ifdef CONFIG_NVT_NS02501 +#define NVT_WDT_CFG 0x102 +#else +#define NVT_WDT_CFG 0x112 +#endif + void reset_cpu(void) { +#if defined(CONFIG_NVT_NA511XX) + setbits_le32(NVT_CG_WDT_RSTN, NVT_CG_WDT_RST); + setbits_le32(NVT_CG_WDT_CLKEN, NVT_CG_WDT_EN); +#elif defined(CONFIG_NVT_NS02501) + /* ns02501_hw_init.c: its reset and clock bits, a zero count */ + setbits_le32(NVT_CG_WDT_RSTN, NVT_CG_WDT_RST); + setbits_le32(NVT_CG_CLKEN0, NVT_CG_WDT); + writel(0, NVT_WDT_DATA); +#else setbits_le32(NVT_CG_CLKEN0, NVT_CG_WDT); setbits_le32(NVT_CG_RSTN0, NVT_CG_WDT); - writel(NVT_WDT_KEY | 0x112, NVT_WDT_CTRL); +#endif + writel(NVT_WDT_KEY | NVT_WDT_CFG, NVT_WDT_CTRL); udelay(80); - writel(NVT_WDT_KEY | 0x112 | NVT_WDT_EN, NVT_WDT_CTRL); + writel(NVT_WDT_KEY | NVT_WDT_CFG | NVT_WDT_EN, NVT_WDT_CTRL); writel(1, NVT_WDT_MANUAL); while (1) ; } -/* The DDR is in the package: its size is the part's */ +#ifdef CONFIG_ARM64 +/* + * The DDR, cached, and the blocks at 0x2_F000_0000 as device memory. With + * the MMU off every access would be a device one, and the unaligned ones + * U-Boot makes would fault. + */ +static struct mm_region nvt_mem_map[] = { + { + .virt = NVT_DDR_BASE, + .phys = NVT_DDR_BASE, + .size = CONFIG_NVT_DDR_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE, + }, { + .virt = NVT_IO(0), + .phys = NVT_IO(0), + .size = NVT_IO_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + 0, + } +}; + +struct mm_region *mem_map = nvt_mem_map; +#endif + +/* The DDR is in the package, or on the board: its size is the part's */ int dram_init(void) { gd->ram_size = PHYS_SDRAM_1_SIZE; diff --git a/board/novatek/na51055/loader/.gitattributes b/board/novatek/na51055/loader/.gitattributes new file mode 100644 index 000000000000..1c5b20e00b05 --- /dev/null +++ b/board/novatek/na51055/loader/.gitattributes @@ -0,0 +1,2 @@ +# The vendor loader, as the SDK ships it: no line-ending conversion +* -text diff --git a/board/novatek/na51055/loader/.gitignore b/board/novatek/na51055/loader/.gitignore new file mode 100644 index 000000000000..f84d41d3cbe0 --- /dev/null +++ b/board/novatek/na51055/loader/.gitignore @@ -0,0 +1,2 @@ +# The vendor libraries the loader links against +!*.a diff --git a/board/novatek/na51055/loader/ARC/Lib/Release/CA9.a b/board/novatek/na51055/loader/ARC/Lib/Release/CA9.a new file mode 100644 index 000000000000..3c7ec4a4eb13 Binary files /dev/null and b/board/novatek/na51055/loader/ARC/Lib/Release/CA9.a differ diff --git a/board/novatek/na51055/loader/ARC/Lib/Release/Common_exFAT.a b/board/novatek/na51055/loader/ARC/Lib/Release/Common_exFAT.a new file mode 100644 index 000000000000..6c5ed25241f5 Binary files /dev/null and b/board/novatek/na51055/loader/ARC/Lib/Release/Common_exFAT.a differ diff --git a/board/novatek/na51055/loader/ARC/Lib/Release/Common_normal.a b/board/novatek/na51055/loader/ARC/Lib/Release/Common_normal.a new file mode 100644 index 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--git a/board/novatek/na51055/loader/ARC/Lib/Release/nvtpack.a b/board/novatek/na51055/loader/ARC/Lib/Release/nvtpack.a new file mode 100644 index 000000000000..6a58af82fdc7 Binary files /dev/null and b/board/novatek/na51055/loader/ARC/Lib/Release/nvtpack.a differ diff --git a/board/novatek/na51055/loader/Include/CMacro.h b/board/novatek/na51055/loader/Include/CMacro.h new file mode 100755 index 000000000000..956cd8ec9cce --- /dev/null +++ b/board/novatek/na51055/loader/Include/CMacro.h @@ -0,0 +1,35 @@ +/*++ + +Copyright (c) 2005 Novatek Microelectronics Corporation + +Module Name: + StdCMac.h + +Abstract: + Standard C Macros for shared header file of ARM ASM and C + You should include this file first and then include the shared header file + For more information, please refer to http://www.arm.com/support/faqdev/1208.html + +Environment: + For nt96610 + +Notes: + Copyright (c) 2005 Novatek Microelectronics Corporation. All Rights Reserved. + +Revision History: + ??/??/??: Created by ARM + 03/17/05: Modify by Chris Hsu for NT96610 uITRON project +--*/ + +#ifndef __C_MACRO_H +#define __C_MACRO_H + + +/* Comment */ +#define COMMENT + +/* end */ +#define END + +#endif // __C_MACRO_H + diff --git a/board/novatek/na51055/loader/Include/Driver/CC.h b/board/novatek/na51055/loader/Include/Driver/CC.h new file mode 100755 index 000000000000..ca71331870ff --- /dev/null +++ b/board/novatek/na51055/loader/Include/Driver/CC.h @@ -0,0 +1,41 @@ +/** + Header file for CC (Core Communicator) module. + + This file is the header file that define the API and data type + for CC module. + + @file CC.h + @ingroup mIDrvSys_CC + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ + +#ifndef _CC_H +#define _CC_H + +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + +#define CC_CORE_CA53_CORE1 0 +#define CC_CORE_CA53_CORE2 1 +#define CC_CORE_DSP 2 +#define CC_CORE_DSP2 3 + +typedef enum +{ + DMA_ID_1, ///< DMA Controller + DMA_ID_2, ///< DMA Controller 2 + + DMA_ID_COUNT, //< DMA controller count + + ENUM_DUMMY4WORD(DMA_ID) +} DMA_ID; + +extern void cc_setCore2Base(UINT32 uiBaseAddr); +extern ER cc_startCore(UINT32 uiCoreID); +extern void cc_stopCore(UINT32 uiCoreID); +extern UINT32 dma_get_dram_capacity(DMA_ID id); + + + +#endif diff --git a/board/novatek/na51055/loader/Include/Driver/Cache.h b/board/novatek/na51055/loader/Include/Driver/Cache.h new file mode 100755 index 000000000000..e840ce007b2a --- /dev/null +++ b/board/novatek/na51055/loader/Include/Driver/Cache.h @@ -0,0 +1,511 @@ +/** + CPU module driver. + + This file is the driver of CPU module. + + @file Cache.h + @ingroup mIHALCore + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2005. All rights reserved. +*/ + +#ifndef _CACHE_H +#define _CACHE_H +#include "constant.h" + + +/* + csselrcache level & type selection + + Detailed reference to [trm p4-177 CSSELR] +*/ +typedef enum _CACHE_LV_TYPE_ +{ + LEVEL_1_DCACHE = 0x0, //< Level 1 data cache + LEVEL_1_ICACHE, //< Level 1 instruction cache + LEVEL_2_DCACHE, //< Level 2 data cache +} CACHE_LV_TYPE; + + +/* + Values for Ctype fields in CLIDR +*/ + +typedef enum _CLIDR_CTYPE_ +{ + CLIDR_CTYPE_NO_CACHE = 0x0, + CLIDR_CTYPE_INSTRUCTION_ONLY= 0x1, + CLIDR_CTYPE_DATA_ONLY = 0x2, + CLIDR_CTYPE_INSTRUCTION_DATA= 0x3, + CLIDR_CTYPE_UNIFIED = 0x4, +}CLIDR_CTYPE; + + +//Instruction Synchronization Barrier. +#define _ISB() \ + __asm__ __volatile__("isb\n\t") + +//Data Synchronization Barrier +#define _DSB() \ + __asm__ __volatile__("dsb\n\t") + +//Data Memory Barrier +#define _DMB() \ + __asm__ __volatile__("dmb\n\t") + + +/* + ************************************************************************ + * Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |W|W|R|W|NumSets |Associativity |L | + * |T|B|A|A| | |S | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_DC_SETS 8 +#define S_DC_W 2 +#define S_DC_LS 5 + +#define _DC_SETS (1 << S_DC_SETS) /* 256 sets */ +#define _DC_W (1 << S_DC_W) /* 4 way */ +#define _DC_LS (1 << S_DC_LS) /* 32 byte line size */ + +#define S_IC_SETS 8 +#define S_IC_W 2 +#define S_IC_LS 5 + +#define _IC_SETS (1 << S_IC_SETS) /* 256 sets */ +#define _IC_W (1 << S_IC_W) /* 4 way */ +#define _IC_LS (1 << S_IC_LS) /* 32 byte line size */ + +#define S_DC_W_L2 4 /* L2 way shift*/ + +#define S_SC_SETS 9 +#define S_SC_W 3 +#define S_SC_LS 5 + +#define _SC_SETS (1 << S_SC_SETS) /* 512 sets */ +#define _SC_W (1 << S_SC_W) /* 8 way */ +#define _SC_LS (1 << S_SC_LS) /* 32 byte line size */ + + +#define S_CCSIDR_WT 31 +#define M_CCSIDR_WT (0x1 << S_CCSIDR_WT) /* Support write-through */ +#define S_CCSIDR_WB 30 +#define M_CCSIDR_WB (0x1 << S_CCSIDR_WB) /* Support write-back */ +#define S_CCSIDR_RA 29 +#define M_CCSIDR_RA (0x1 << S_CCSIDR_RA) /* Support read-allocation */ +#define S_CCSIDR_WA 28 +#define M_CCSIDR_WA (0x1 << S_CCSIDR_WA) /* Support write-allocation */ +#define S_CCSIDR_SETS 13 +#define M_CCSIDR_SETS (0x7fff << S_CCSIDR_SETS) /* Number of sets */ +#define S_CCSIDR_A 3 +#define M_CCSIDR_A (0x3ff << S_CCSIDR_A) /* Number of associatiovity */ +#define S_CCSIDR_LS 0 +#define M_CCSIDR_LS (0x7 << S_CCSIDR_LS) /* Cache line size */ + + +/* + * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_WXN (1 << 19) /* Write Permision Imply XN */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ + +#define SCTLR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + : "=r" (val)); \ + val; \ + }) + +#define LEVEL_1 (1 - 1) +#define LEVEL_2 (2 - 1) + +#define CCSIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__( \ + "mrc p15, 1, %0, c0, c0, 0\n\t" \ + : "=r" (val)); \ + val; \ + }) + + +#define sel_CSSELR(InD) \ + __asm__ __volatile__( \ + "mcr p15, 2, %0, c0, c0, 0\n\t" \ + : \ + : "r"(InD)); + +#define _ICACHE_INV_ALL() _ICIALLU() \ + _BPIALL() + +/* + ICIALLU, Instruction Cache Invalidate All to PoU + The ICIALLU characteristics are: + + Invalidate all instruction caches to PoU. If branch predictors are + architecturally visible, also flush branch predictors. + + This register is part of the Cache maintenance instructions functional group. + + Usage constraints + If EL3 is implemented and is using AArch32, this operation can be performed at the following + exception levels: +*/ +#define _ICIALLU() \ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); + +/* + Branch Predictor Invalidate All + The BPIALL characteristics are: + + Invalidate all entries from branch predictors. + This register is part of the Cache maintenance instructions functional group. + Usage constraints + If EL3 is implemented and is using AArch32, this operation can be performed at the following + exception levels: +*/ +#define _BPIALL() \ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); + + +/* + ICIMVAU : Instruction Cache line Invalidate by VA to PoU +*/ +#define _ICACHE_INV_MVAU(addr) _ICIMVAU(addr) +#define _ICIMVAU(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c5, 1\n\t" \ + : \ + : "r"(addr)); + +#define _DCACHE_INV_MVAC(addr) _DCIMVAC(addr) +#define _DCIMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c6, 1\n\t" \ + : \ + : "r"(addr)); + +//DCCMVAC Clean data cache line by VA to PoC +#define _DCACHE_WBACK_MVAC(addr) _DCCMVAC(addr) +#define _DCCMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c10, 1\n\t" \ + : \ + : "r"(addr)); + +//_DCCIMVAC Clean and invalidate data cache line by VA to PoC +#define _DCACHE_WBACK_INV_MVAC(addr) _DCCIMVAC(addr) +#define _DCCIMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c14, 1\n\t" \ + : \ + : "r"(addr)); + +//DCCISW Clean and invalidate data cache line by set/way +#define _DCCISW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c14, 2\n\t" \ + : \ + : "r"(way_set)); + +//DCISW Invalidate data cache line by set/way +/* + The DCISW input value bit assignments are: + + |31......................4 | 3...1 | 0 | + Setway level rsv + bit[3..1] = 0x0 = Level 1 + bit[3..1] = 0x1 = Level 2 + ... +*/ +#define _DCISW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c6, 2\n\t" \ + : \ + : "r"(way_set)); + + +//DCCSW Clean data cache line by set/way +/* + The DCCSW input value bit assignments are: + + |31......................4 | 3...1 | 0 | + Setway level rsv + bit[3..1] = 0x0 = Level 1 + bit[3..1] = 0x1 = Level 2 + ... +*/ +#define _DCCSW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c10, 2\n\t" \ + : \ + : "r"(way_set)) + + + + +/* Cache dirty register () */ +#define read_CDSR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c7, c10, 6\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +/* Get CPU ID */ +#define read_MPIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c0, c0, 5\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +/* ead current CP15 Cache Level ID Register */ +#define read_CLIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 1, %0, c0, c0, 1\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +#define change_property() \ + ({ \ + __asm__ __volatile__( \ + ".arch_extension sec\n\t" \ + "smc #123\n\t" \ + : \ + : \ + ); \ + }) + +#define CLEAR_MMU() \ + __asm__ __volatile__("mcr p15, 0, r0, c8, c7, 0\n\t"); + + +#define DISABLE_MMU() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x1\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define DISABLE_DCACHE() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x4\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define DISABLE_ICACHE() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x1000\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define SETUP_TTBR0(val) \ + ({ \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c2, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) +/* Cache dirty register () */ +#define read_CDSR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c7, c10, 6\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) +/** + @addtogroup mIHALCore +*/ +//@{ + +/** + @name CPU clean invalidate all DCache + + Clean and invalidate all data cache + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCacheAll() cpu_cleanInvalidateDCacheAll() ///< clean invalidate all DCache +//@} + +/** + @name CPU clean invalidate DCache + + Clean and invalidate data cache + Cache line associated with input address will be clean and invalidated + + @param[in] addr data address to be clean and invalidated + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCache(addr) cpu_cleanInvalidateDCache(addr) ///< clean invalidate DCache +//@} + +/** + @name CPU clean invalidate DCache block + + Clean and invalidate data cache block + Cache line associated with input region will be clean and invalidated + + @param[in] m starting data address to be clean and invalidated + @param[in] n end data address to be clean and invalidated + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCacheBlock(m,n) cpu_cleanInvalidateDCacheBlock(m, n) ///< clean invalidate DCache block +//@} + +/** + @name CPU invalidate DCache + + Invalidate data cache + Cache line associated with input address will be invalidated + + @param[in] addr data address to be invalidated + + @return void +*/ +//@{ +#define CPUInvalidateDCache(m) cpu_invalidateDCache(m) ///< invalidate DCache +//@} + +/** + @name CPU invalidate DCache block + + Invalidate data cache block + Cache line associated with input region will be invalidated + + @param[in] m starting data address to be invalidated + @param[in] n end data address to be invalidated + + @return void +*/ +//@{ +#define CPUInvalidateDCacheBlock(m,n) cpu_invalidateDCacheBlock(m,n) ///< invalidate DCache block +//@} + +/** + @name CPU clean DCache + + Clean data cache + Cache line associated with input address will be clean + + @param[in] addr data address to be clean + + @return void +*/ +//@{ +#define CPUCleanDCache(m) cpu_cleanDCache(m) ///< clean DCache +//@} + +/** + @name CPU clean DCache block + + Clean data cache block + Cache line associated with input region will be clean + + @param[in] m starting data address to be clean + @param[in] n end data address to be clean + + @return void +*/ +//@{ +#define CPUCleanDCacheBlock(m, n) cpu_cleanDCacheBlock(m, n) ///< clean DCache block +//@} + +/** + @name CPU invalidate all DCache + + Invalidate all data cache + + @return void +*/ +//@{ +#define CPUInvalidateDCacheAll() cpu_invalidateDCacheAll() ///< invalidate all DCache +//@} + + +extern BOOL CPUChkDCacheEnabled(UINT32 addr); +extern void CPUInvalidateICacheAll(void) __attribute__ ((section (".part1"))); +//extern void CPUInvalidateICacheAll(void) __attribute__ ((section (".part1"), far)); +//extern void CPUInvalidateICache(UINT32 addr); +extern void CPUInvalidateICacheBlock(UINT32 start, UINT32 end); + +#if 0 +extern void CPUInvalidateDCacheAll(void); +extern void CPUInvalidateDCache(UINT32 addr); +extern void CPUInvalidateDCacheBlock(UINT32 start, UINT32 end); +#endif +extern void cpu_invalidateDCacheBlock(UINT32 start, UINT32 end); +extern void cpu_invalidateDCache(UINT32 addr); +extern void cpu_invalidateDCacheAll(void)__attribute__ ((section (".part1"))); +extern void cpu_cleanDCache(UINT32 addr); +extern void cpu_cleanDCacheBlock(UINT32 start, UINT32 end); +extern void _cache_clean_d_cache_all(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); +extern void _cache_invalidate_data_cache_all(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); +extern void _cache_clean_invalidate_d_cache_All(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); + + + +extern void cpu_cleanInvalidateDCacheAll(void)__attribute__ ((section (".part1"))); +//extern void cpu_cleanInvalidateDCacheAll(void)__attribute__ ((section (".part1"), far)); +extern void cpu_cleanInvalidateDCache(UINT32 addr); +extern void cpu_cleanInvalidateDCacheBlock(UINT32 start, UINT32 end); + +extern void CPUflushReadCache(UINT32 uiStartAddr, UINT32 uiLength); +extern void CPUflushWriteCache(UINT32 uiStartAddr, UINT32 uiLength); + + + +#endif + +//@} diff --git a/board/novatek/na51055/loader/Include/Driver/Clock.h b/board/novatek/na51055/loader/Include/Driver/Clock.h new file mode 100755 index 000000000000..92be645d86d4 --- /dev/null +++ b/board/novatek/na51055/loader/Include/Driver/Clock.h @@ -0,0 +1,26 @@ +/** + System Clock APIs header file + + System Clock APIs header. + + @file clock.h + @ingroup mIHALSysCG + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __CLOCK_H +#define __CLOCK_H + +#include "IOReg.h" + +/** \addtogroup mIHALSysCG */ +//@{ + + + + +//@} + +#endif // __CLOCK_H diff --git a/board/novatek/na51055/loader/Include/Driver/GPIO.h b/board/novatek/na51055/loader/Include/Driver/GPIO.h new file mode 100755 index 000000000000..bb6719e983e6 --- /dev/null +++ b/board/novatek/na51055/loader/Include/Driver/GPIO.h @@ -0,0 +1,314 @@ +/** + General Purpose I/O controller header file + + General Purpose I/O controller header file + + @file GPIO.h + @ingroup mIIOGPIO + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _GPIO_H +#define _GPIO_H + +#include "IOReg.h" + +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + +/** + @addtogroup mIDrvIO_GPIO +*/ +//@{ + +/** + GPIO direction + + GPIO direction definition for gpio_setDir() and gpio_getDir() +*/ +typedef enum { + GPIO_DIR_INPUT = 0, ///< GPIO is input direction + GPIO_DIR_OUTPUT = 1, ///< GPIO is output direction + + ENUM_DUMMY4WORD(GPIO_DIR) +} GPIO_DIR; + +/** + GPIO interrupt type + + GPIO interrupt type definition for type argument of gpio_setIntTypePol() +*/ +typedef enum { + GPIO_INTTYPE_EDGE = 0, ///< GPIO interrupt is edge trigger + GPIO_INTTYPE_LEVEL = 1, ///< GPIO interrupt is level trigger + + ENUM_DUMMY4WORD(GPIO_INTTYPE) +} GPIO_INTTYPE; + +/** + GPIO interrupt polarity + + GPIO interrupt polarity definition for pol argument of gpio_setIntTypePol() +*/ +typedef enum { + GPIO_INTPOL_POSHIGH = 0, ///< GPIO interrupt polarity is \n + ///< - @b positvie edge for edge trigger + ///< - @b high level for level trigger + GPIO_INTPOL_NEGLOW = 1, ///< GPIO interrupt polarity is \n + ///< - @b negative edge for edge trigger + ///< - @b low level for level trigger + GPIO_INTPOL_BOTHEDGE = 2, ///< GPIO interrupt polarity is \n + ///< - @b both edge for edge trigger + ENUM_DUMMY4WORD(GPIO_INTPOL) +} GPIO_INTPOL; + + + +/** + @name GPIO pins ID + + GPIO pins ID definition + + For detail GPIO pin out, please refer to NT96520 data sheet. +*/ +//@{ +/*Storage GPIO - CGPIO*/ +#define C_GPIO_0 0 ///< C_GPIO[0] +#define C_GPIO_1 1 ///< C_GPIO[1] +#define C_GPIO_2 2 ///< C_GPIO[2] +#define C_GPIO_3 3 ///< C_GPIO[3] +#define C_GPIO_4 4 ///< C_GPIO[4] +#define C_GPIO_5 5 ///< C_GPIO[5] +#define C_GPIO_6 6 ///< C_GPIO[6] +#define C_GPIO_7 7 ///< C_GPIO[7] +#define C_GPIO_8 8 ///< C_GPIO[8] +#define C_GPIO_9 9 ///< C_GPIO[9] +#define C_GPIO_10 10 ///< C_GPIO[10] +#define C_GPIO_11 11 ///< C_GPIO[11] +#define C_GPIO_12 12 ///< C_GPIO[12] +#define C_GPIO_13 13 ///< C_GPIO[13] +#define C_GPIO_14 14 ///< C_GPIO[14] +#define C_GPIO_15 15 ///< C_GPIO[15] +#define C_GPIO_16 16 ///< C_GPIO[16] +#define C_GPIO_17 17 ///< C_GPIO[17] +#define C_GPIO_18 18 ///< C_GPIO[18] +#define C_GPIO_19 19 ///< C_GPIO[19] +#define C_GPIO_20 20 ///< C_GPIO[20] +#define C_GPIO_21 21 ///< C_GPIO[21] +#define C_GPIO_22 22 ///< C_GPIO[22] + +/*Peripheral GPIO - PGPIO*/ +#define P_GPIO_SHIFT_BASE 32 +#define P_GPIO_0 (0 +P_GPIO_SHIFT_BASE) ///< P_GPIO[0] +#define P_GPIO_1 (1 +P_GPIO_SHIFT_BASE) ///< P_GPIO[1] +#define P_GPIO_2 (2 +P_GPIO_SHIFT_BASE) ///< P_GPIO[2] +#define P_GPIO_3 (3 +P_GPIO_SHIFT_BASE) ///< P_GPIO[3] +#define P_GPIO_4 (4 +P_GPIO_SHIFT_BASE) ///< P_GPIO[4] +#define P_GPIO_5 (5 +P_GPIO_SHIFT_BASE) ///< P_GPIO[5] +#define P_GPIO_6 (6 +P_GPIO_SHIFT_BASE) ///< P_GPIO[6] +#define P_GPIO_7 (7 +P_GPIO_SHIFT_BASE) ///< P_GPIO[7] +#define P_GPIO_8 (8 +P_GPIO_SHIFT_BASE) ///< P_GPIO[8] +#define P_GPIO_9 (9 +P_GPIO_SHIFT_BASE) ///< P_GPIO[9] +#define P_GPIO_10 (10+P_GPIO_SHIFT_BASE) ///< P_GPIO[10] +#define P_GPIO_11 (11+P_GPIO_SHIFT_BASE) ///< P_GPIO[11] +#define P_GPIO_12 (12+P_GPIO_SHIFT_BASE) ///< P_GPIO[12] +#define P_GPIO_13 (13+P_GPIO_SHIFT_BASE) ///< P_GPIO[13] +#define P_GPIO_14 (14+P_GPIO_SHIFT_BASE) ///< P_GPIO[14] +#define P_GPIO_15 (15+P_GPIO_SHIFT_BASE) ///< P_GPIO[15] +#define P_GPIO_16 (16+P_GPIO_SHIFT_BASE) ///< P_GPIO[16] +#define P_GPIO_17 (17+P_GPIO_SHIFT_BASE) ///< P_GPIO[17] +#define P_GPIO_18 (18+P_GPIO_SHIFT_BASE) ///< P_GPIO[18] +#define P_GPIO_19 (19+P_GPIO_SHIFT_BASE) ///< P_GPIO[19] +#define P_GPIO_20 (20+P_GPIO_SHIFT_BASE) ///< P_GPIO[20] +#define P_GPIO_21 (21+P_GPIO_SHIFT_BASE) ///< P_GPIO[21] +#define P_GPIO_22 (22+P_GPIO_SHIFT_BASE) ///< P_GPIO[22] +#define P_GPIO_23 (23+P_GPIO_SHIFT_BASE) ///< P_GPIO[23] +#define P_GPIO_24 (24+P_GPIO_SHIFT_BASE) ///< P_GPIO[24] +#define P_GPIO_25 (25+P_GPIO_SHIFT_BASE) ///< P_GPIO[25] + +/*Sensor GPIO - SGPIO*/ +#define S_GPIO_SHIFT_BASE 64 +#define S_GPIO_0 (0 +S_GPIO_SHIFT_BASE) ///< S_GPIO[0] +#define S_GPIO_1 (1 +S_GPIO_SHIFT_BASE) ///< S_GPIO[1] +#define S_GPIO_2 (2 +S_GPIO_SHIFT_BASE) ///< S_GPIO[2] +#define S_GPIO_3 (3 +S_GPIO_SHIFT_BASE) ///< S_GPIO[3] +#define S_GPIO_4 (4 +S_GPIO_SHIFT_BASE) ///< S_GPIO[4] +#define S_GPIO_5 (5 +S_GPIO_SHIFT_BASE) ///< S_GPIO[5] +#define S_GPIO_6 (6 +S_GPIO_SHIFT_BASE) ///< S_GPIO[6] +#define S_GPIO_7 (7 +S_GPIO_SHIFT_BASE) ///< S_GPIO[7] +#define S_GPIO_8 (8 +S_GPIO_SHIFT_BASE) ///< S_GPIO[8] +#define S_GPIO_9 (9 +S_GPIO_SHIFT_BASE) ///< S_GPIO[9] +#define S_GPIO_10 (10+S_GPIO_SHIFT_BASE) ///< S_GPIO[10] +#define S_GPIO_11 (11+S_GPIO_SHIFT_BASE) ///< S_GPIO[11] +#define S_GPIO_12 (12+S_GPIO_SHIFT_BASE) ///< S_GPIO[11] + + +/*LCD GPIO - LGPIO*/ +#define L_GPIO_SHIFT_BASE 96 +#define L_GPIO_0 (0 +L_GPIO_SHIFT_BASE) ///< L_GPIO[0] +#define L_GPIO_1 (1 +L_GPIO_SHIFT_BASE) ///< L_GPIO[1] +#define L_GPIO_2 (2 +L_GPIO_SHIFT_BASE) ///< L_GPIO[2] +#define L_GPIO_3 (3 +L_GPIO_SHIFT_BASE) ///< L_GPIO[3] +#define L_GPIO_4 (4 +L_GPIO_SHIFT_BASE) ///< L_GPIO[4] +#define L_GPIO_5 (5 +L_GPIO_SHIFT_BASE) ///< L_GPIO[5] +#define L_GPIO_6 (6 +L_GPIO_SHIFT_BASE) ///< L_GPIO[6] +#define L_GPIO_7 (7 +L_GPIO_SHIFT_BASE) ///< L_GPIO[7] +#define L_GPIO_8 (8 +L_GPIO_SHIFT_BASE) ///< L_GPIO[8] +#define L_GPIO_9 (9 +L_GPIO_SHIFT_BASE) ///< L_GPIO[9] +#define L_GPIO_10 (10+L_GPIO_SHIFT_BASE) ///< L_GPIO[10] +#define L_GPIO_11 (11+L_GPIO_SHIFT_BASE) ///< L_GPIO[11] +#define L_GPIO_12 (12+L_GPIO_SHIFT_BASE) ///< L_GPIO[12] +#define L_GPIO_13 (13+L_GPIO_SHIFT_BASE) ///< L_GPIO[13] +#define L_GPIO_14 (14+L_GPIO_SHIFT_BASE) ///< L_GPIO[14] +#define L_GPIO_15 (15+L_GPIO_SHIFT_BASE) ///< L_GPIO[15] +#define L_GPIO_16 (16+L_GPIO_SHIFT_BASE) ///< L_GPIO[16] +#define L_GPIO_17 (17+L_GPIO_SHIFT_BASE) ///< L_GPIO[17] +#define L_GPIO_18 (18+L_GPIO_SHIFT_BASE) ///< L_GPIO[18] +#define L_GPIO_19 (19+L_GPIO_SHIFT_BASE) ///< L_GPIO[19] +#define L_GPIO_20 (20+L_GPIO_SHIFT_BASE) ///< L_GPIO[20] +#define L_GPIO_21 (21+L_GPIO_SHIFT_BASE) ///< L_GPIO[21] +#define L_GPIO_22 (22+L_GPIO_SHIFT_BASE) ///< L_GPIO[22] +#define L_GPIO_23 (23+L_GPIO_SHIFT_BASE) ///< L_GPIO[23] +#define L_GPIO_24 (24+L_GPIO_SHIFT_BASE) ///< L_GPIO[24] + +/*Dedicated GPIO - DGPIO*/ +// In order to backward comaptible, DGPIO is used as " GPIO_IS_DGPIO | D_GPIO_* " +#define D_GPIO_SHIFT_BASE 128 +#define D_GPIO_0 (0 +D_GPIO_SHIFT_BASE) ///< DGPIO[0] +#define D_GPIO_1 (1 +D_GPIO_SHIFT_BASE) ///< DGPIO[1] +#define D_GPIO_2 (2 +D_GPIO_SHIFT_BASE) ///< DGPIO[2] +#define D_GPIO_3 (3 +D_GPIO_SHIFT_BASE) ///< DGPIO[3] +#define D_GPIO_4 (4 +D_GPIO_SHIFT_BASE) ///< DGPIO[4] +#define D_GPIO_5 (5 +D_GPIO_SHIFT_BASE) ///< DGPIO[5] +#define D_GPIO_6 (6 +D_GPIO_SHIFT_BASE) ///< DGPIO[6] +#define D_GPIO_7 (7 +D_GPIO_SHIFT_BASE) ///< DGPIO[7] +#define D_GPIO_8 (8 +D_GPIO_SHIFT_BASE) ///< DGPIO[8] +#define D_GPIO_9 (9 +D_GPIO_SHIFT_BASE) ///< DGPIO[9] +#define D_GPIO_10 (10+D_GPIO_SHIFT_BASE) ///< DGPIO[10] + +#define D_GPIO_16 (16 +D_GPIO_SHIFT_BASE) ///< D_GPIO[16] (USB Wakeup) (No pad instance) + +/*GPIO HSI Data register(High speed interface)*/ +#define H_GPIO_SHIFT_BASE 160 +#define H_GPIO_0 (0 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[0] +#define H_GPIO_1 (1 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[1] +#define H_GPIO_2 (2 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[2] +#define H_GPIO_3 (3 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[3] +#define H_GPIO_4 (4 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[4] +#define H_GPIO_5 (5 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[5] +#define H_GPIO_6 (6 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[6] +#define H_GPIO_7 (7 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[7] +#define H_GPIO_8 (8 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[8] +#define H_GPIO_9 (9 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[9] +#define H_GPIO_10 (10+H_GPIO_SHIFT_BASE) ///< HSI_GPIO[10] +#define H_GPIO_11 (11+H_GPIO_SHIFT_BASE) ///< HSI_GPIO[11] + +/*GPIO ADC Data register*/ +#define A_GPI_SHIFT_BASE 192 +#define A_GPIO_0 (0 + A_GPI_SHIFT_BASE) ///< A_GPIO[0] +#define A_GPIO_1 (1 + A_GPI_SHIFT_BASE) ///< A_GPIO[1] +#define A_GPIO_2 (2 + A_GPI_SHIFT_BASE) ///< A_GPIO[2] + +//@} + +/*For temporary usage as passing build codes*/ +#define C_GPIO_23 23 +#define C_GPIO_24 24 +#define C_GPIO_25 25 +#define C_GPIO_26 26 +#define C_GPIO_27 27 +#define C_GPIO_28 28 +#define C_GPIO_29 29 +#define C_GPIO_30 30 +#define C_GPIO_31 31 +#define C_GPIO_32 32 +#define C_GPIO_33 33 +#define L_GPIO_30 (30+L_GPIO_SHIFT_BASE) +#define L_GPIO_31 (31+L_GPIO_SHIFT_BASE) +#define L_GPIO_32 (32+L_GPIO_SHIFT_BASE) +#define GPIO_INT_USBPLUGIN (GPIO_INT_39) + + + + +/** + @name GPIO Interrupt ID + + GPIO interrupt ID definition + + GPIO interrupt ID for interrupt related APIs. +*/ +//@{ +#define GPIO_INT_00 0 ///< GPIO INT[0]: C_GPIO[3] +#define GPIO_INT_01 1 ///< GPIO INT[1]: C_GPIO[5] +#define GPIO_INT_02 2 ///< GPIO INT[2]: C_GPIO[7] +#define GPIO_INT_03 3 ///< GPIO INT[3]: C_GPIO[9] +#define GPIO_INT_04 4 ///< GPIO INT[4]: C_GPIO[12] +#define GPIO_INT_05 5 ///< GPIO INT[5]: C_GPIO[14] +#define GPIO_INT_06 6 ///< GPIO INT[6]: C_GPIO[16] +#define GPIO_INT_07 7 ///< GPIO INT[7]: C_GPIO[18] +#define GPIO_INT_08 8 ///< GPIO INT[8]: C_GPIO[20] +#define GPIO_INT_09 9 ///< GPIO INT[9]: C_GPIO[22] +#define GPIO_INT_10 10 ///< GPIO INT[10]: H_GPIO[0] +#define GPIO_INT_11 11 ///< GPIO INT[11]: H_GPIO[11] +#define GPIO_INT_12 12 ///< GPIO INT[12]: S_GPIO[1] +#define GPIO_INT_13 13 ///< GPIO INT[13]: S_GPIO[4] +#define GPIO_INT_14 14 ///< GPIO INT[14]: S_GPIO[6] +#define GPIO_INT_15 15 ///< GPIO INT[15]: S_GPIO[10] +#define GPIO_INT_16 16 ///< GPIO INT[16]: S_GPIO[12] +#define GPIO_INT_17 17 ///< GPIO INT[17]: P_GPIO[3] +#define GPIO_INT_18 18 ///< GPIO INT[18]: P_GPIO[7] +#define GPIO_INT_19 19 ///< GPIO INT[19]: P_GPIO[8] +#define GPIO_INT_20 20 ///< GPIO INT[20]: P_GPIO[9] +#define GPIO_INT_21 21 ///< GPIO INT[21]: P_GPIO[11] +#define GPIO_INT_22 22 ///< GPIO INT[22]: P_GPIO[15] +#define GPIO_INT_23 23 ///< GPIO INT[23]: P_GPIO[17] +#define GPIO_INT_24 24 ///< GPIO INT[24]: P_GPIO[18] +#define GPIO_INT_25 25 ///< GPIO INT[25]: P_GPIO[24] +#define GPIO_INT_26 26 ///< GPIO INT[26]: L_GPIO[1] +#define GPIO_INT_27 27 ///< GPIO INT[27]: L_GPIO[6] +#define GPIO_INT_28 28 ///< GPIO INT[28]: L_GPIO[11] +#define GPIO_INT_29 29 ///< GPIO INT[29]: L_GPIO[14] +#define GPIO_INT_30 30 ///< GPIO INT[30]: P_GPIO[18] +#define GPIO_INT_31 31 ///< GPIO INT[31]: L_GPIO[22] +#define GPIO_INT_32 32 ///< DGPIO INT[0]: D_GPIO[0] +#define GPIO_INT_33 33 ///< DGPIO INT[1]: D_GPIO[1] +#define GPIO_INT_34 34 ///< DGPIO INT[2]: D_GPIO[2] +#define GPIO_INT_35 35 ///< DGPIO INT[3]: D_GPIO[3] +#define GPIO_INT_36 36 ///< DGPIO INT[4]: D_GPIO[4] +#define GPIO_INT_37 37 ///< DGPIO INT[5]: D_GPIO[5] +#define GPIO_INT_38 38 ///< DGPIO INT[6]: D_GPIO[6] +#define GPIO_INT_39 39 ///< DGPIO INT[7]: D_GPIO[7] + +#define GPIO_INT_48 48 ///< DGPIO INT[16]: USB wakeup + +#define GPIO_INT_USBWAKEUP (GPIO_INT_48) ///< DGPIO INT[16]: USB wakeup +//@} + +// In order to backward comaptible, DGPIO is used as " GPIO_IS_DGPIO | D_GPIO_* " or "D_GPIO_*" +#define GPIO_IS_DGPIO (128) + + +// +// The general api for the GPIO device driver +// +extern void gpio_setDir(UINT32 pin, UINT32 dir); +extern UINT32 gpio_getDir(UINT32 pin); +extern void gpio_setPin(UINT32 pin); +extern void gpio_clearPin(UINT32 pin); +extern UINT32 gpio_getPin(UINT32 pin); +extern void gpio_pullSet(UINT32 pin); +extern void gpio_pullClear(UINT32 pin); +extern UINT32 gpio_readData(UINT32 dataidx); +extern void gpio_writeData(UINT32 dataidx, UINT32 value); +//extern UINT32 gpio_readDir(UINT32 dataidx); +//extern void gpio_writeDir(UINT32 dataidx, UINT32 value); +extern UINT32 dgpio_readData(void); +extern void dgpio_writeData(UINT32 value); +extern UINT32 top_get_bs(void); +//extern UINT32 dgpio_readDir(void); +//extern void dgpio_writeDir(UINT32 value); +//@} +#endif + diff --git a/board/novatek/na51055/loader/Include/Driver/Memory.h b/board/novatek/na51055/loader/Include/Driver/Memory.h new file mode 100755 index 000000000000..60c472e0f31c --- /dev/null +++ b/board/novatek/na51055/loader/Include/Driver/Memory.h @@ -0,0 +1,436 @@ +# ifndef _MEMORY_520_H +# define _MEMORY_520_H + +#ifndef __ASSEMBLY__ + COMMENT /* Memory Map */ /* # define BOOT_ROM_RAM_BASE_ADDR 0x20000000*/ +#endif +# define DRAM_BASE_ADDR (0x00000000) +# define DRAM_EXP_BASE_ADDR (DRAM_BASE_ADDR + 0x180) +# define DRAM_INT_BASE_ADDR (DRAM_BASE_ADDR + 0x200) + +# define StackSize_KNL 0x1000 /* 4KB */ +# define StackSize_INT 0x400 /* 1KB */ + +# define FAT_HEAP_BUFFER_SIZE 0xA0000//0x1E0000 //0x1E8000 +# define EXFAT_BITMAP_BUFFER_SIZE 0x20000 //0x18000 +# define LOADER_TMP_BUFFER_SIZE 0x80000 + +# define BOOT_ROM_SP_LIMIT_ADDR 0xF07F8FFC +# define BOOT_ROM_RAM_TEMP_ADDR 0xF0800200 +# define BOOT_ROM_CFG_TEMP_ADDR 0xF0800248 +# define BOOT_ROM_RAM_BASE_ADDR 0x00000000 +# define DMA2_CTRL_REG_BASE_ADDR 0xF0100000 +# define DMA2_PHY_REG_BASE_ADDR 0xF0101000 +# define USB_OTG_REG_BASE_ADDR 0//0xF0600000 +# define DDR_CTRL_REG_BASE_ADDR 0xF0000000 /* DDR phy base address */ +# define DDR_PHY_REG_BASE_ADDR 0xF0001000 +# define DDR_ARB_REG_BASE_ADDR 0xF0008000 +# define DMA2_ARB_REG_BASE_ADDR 0xF0108000 + +# define CLOCK_GEN_REG_BASE_ADDR 0xF0020000 +# define PMU_REG_BASE_ADDR 0xF0024000 +# define TOP_CTRL_REG_BASE_ADDR 0xF0010000 +# define PAD_CTRL_REG_BASE_ADDR 0xF0030000 +# define GPIO_CTRL_REG_BASE_ADDR 0xF0070000 +# define PMC_REG_BASE 0xF00A0000 + +# define TRNG_REG_BASE_ADDR 0xF0680000 + +# define CPU_REG_BASE_ADDR 0xF0FF0000 + +# define UART0_REG_BASE_ADDR 0xF0290000 +# define UART2_REG_BASE_ADDR 0xF0300000 +# define SM_HOST_REG_BASE_ADDR 0xF0400000 +# define MS_HOST_REG_BASE_ADDR 0xF0410000 +# define SD_HOST1_REG_BASE_ADDR 0xF0420000 +# define SD_HOST2_REG_BASE_ADDR 0xF0500000 +# define SD_HOST3_REG_BASE_ADDR 0xF0510000 +# define SPI_CTRL_REG_BASE_ADDR 0xF0230000 +# define ETH_CTRL_REG_BASE_ADDR 0xF02B0000 +# define EFUSE_CTRL_REG_BASE_ADDR 0xF0660000 +# define IDE_SRAM_BASE_ADDR 0xF07C0000 +# define IDE_CTRL_REG_BASE_ADDR 0xF0800000 +# define TIMER_REG_BASE_ADDR 0xF0040000 +# define WDT_REG_BASE_ADDR 0xF0050000 + +# define BOOT_LOADER_TMP_BUFFER 0x00001000 +# define CHIP_REMAP_REG_OFFSET 0x00000088 +# define CPE_RTC_BASE 0xF0060000 /* RTC controller */ +# define CPE_GPIO_BASE 0xF0070000 /* GPIO controller */ +# define INTERRUPT_BASE_ADDR 0xF0080000 /* Interrupt controller */ +# define CC_BASE_ADDR 0xF0090000 /* CC controller */ +# define IOADDR_GIC_REG_BASE 0xFFD00000 /* GIC Interrupt */ +# define configARM_TIMER_BASEADDR 0xFFD00200 +# define ARM_TIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ + + +# define BOOT_ROM_RAM_TEMP_ADDR2 0xF07E8000 //Eth +# define PAD_REG_BASE 0xF0030000 +# define L2_MEM_BASE 0xFFE00000 +# define IOADDR_HVYLOAD_REG_BASE 0xF0008000 + +# define CC_CPU2_CPU1_CMDBUF_REG1 0xF07F8000 //CC_CPU2_CPU1_CMDBUF_REG1 to store uboot starting address +# define CC_CPU2_CPU1_CMDBUF_REG2 0xF07F8004 //CC_CPU2_CPU1_CMDBUF_REG1 has used in core2_entry.s +# define NVT_CORE2_START CC_CPU2_CPU1_CMDBUF_REG2 //core2_entry.S 's entry point + +# define ARM_TIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ +# define ARM_TIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ +# define ARM_TIMER_COUNTER_OFFSET 0x04 /**< Timer Counter Register */ +# define ARM_TIMER_CONTROL_OFFSET 0x08 /**< Timer Control Register */ +# define ARM_TIMER_ISR_OFFSET 0x0C /**< Timer Interrupt Status Register */ +# define ARM_TIMER_COUNTER_OFFSET_L 0x00 /**< Timer Counter Register */ +# define ARM_TIMER_COUNTER_OFFSET_H 0x04 /**< Timer Counter Register */ +# define ARM_TIMER_COUNTER_CMP_OFFSET_L 0x10 /**< Timer Counter Register */ +# define ARM_TIMER_COUNTER_CMP_OFFSET_H 0x14 /**< Timer Counter Register */ +# define CYGHWR_HAL_RTC_PRESCALER 1 +# define ARM_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */ +# define ARM_TIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */ +# define ARM_TIMER_CONTROL_PRESCALER_SHIFT 8 +# define ARM_TIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004 /**< Intr enable */ +# define ARM_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */ +# define ARM_TIMER_CONTROL_ENABLE_MASK 0x00000001 /**< Timer enable */ + +#define ARM_TIMER_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */ +#define CRYPTO_REG_BASE_ADDR 0xF0620000 +#define HASH_REG_BASE_ADDR 0xF0700000 +#define RSA_REG_BASE_ADDR 0xF06A0000 + +#define CRYPTO_CONFIG_REG (CRYPTO_REG_BASE_ADDR + 0x00) +#define CRYPTO_CONTROL_REG (CRYPTO_REG_BASE_ADDR + 0x04) +#define CRYPTO_OUT_DATA_REG (CRYPTO_REG_BASE_ADDR + 0x08) +#define CRYPTO_STATUS_REG (CRYPTO_REG_BASE_ADDR + 0x0C) + +#define CRYPTO_PIO_INPUT0_REG (CRYPTO_REG_BASE_ADDR + 0x30) +#define CRYPTO_PIO_INPUT1_REG (CRYPTO_REG_BASE_ADDR + 0x34) +#define CRYPTO_PIO_INPUT2_REG (CRYPTO_REG_BASE_ADDR + 0x38) +#define CRYPTO_PIO_INPUT3_REG (CRYPTO_REG_BASE_ADDR + 0x3C) +#define CRYPTO_PIO_OUTPUT0_REG (CRYPTO_REG_BASE_ADDR + 0x40) +#define CRYPTO_PIO_OUTPUT1_REG (CRYPTO_REG_BASE_ADDR + 0x44) +#define CRYPTO_PIO_OUTPUT2_REG (CRYPTO_REG_BASE_ADDR + 0x48) +#define CRYPTO_PIO_OUTPUT3_REG (CRYPTO_REG_BASE_ADDR + 0x4C) + +// Hash +#define HASH_CONFIG_REG (HASH_REG_BASE_ADDR + 0x00) +#define HASH_STATUS_REG (HASH_REG_BASE_ADDR + 0x0C) +#define HASH_OUTPUT_DATA1_REG (HASH_REG_BASE_ADDR + 0x70) +#define HASH_INPUT_DATA_REG (HASH_REG_BASE_ADDR + 0x90) + +//RSA +#define RSA_CONFIG_REG (RSA_REG_BASE_ADDR + 0x00) +#define RSA_CONTROL_REG (RSA_REG_BASE_ADDR + 0x04) +#define RSA_STATUS_REG (RSA_REG_BASE_ADDR + 0x0C) +#define RSA_KEY_N_REG (RSA_REG_BASE_ADDR + 0x10) +#define RSA_KEY_N_ADDR_REG (RSA_REG_BASE_ADDR + 0x14) +#define RSA_KEY_ED_REG (RSA_REG_BASE_ADDR + 0x18) +#define RSA_KEY_ED_ADDR_REG (RSA_REG_BASE_ADDR + 0x1C) +#define RSA_DATA_REG (RSA_REG_BASE_ADDR + 0x20) +#define RSA_DATA_ADDR_REG (RSA_REG_BASE_ADDR + 0x24) +#define RSA_CRC32_DEFAULT_REG_OFS (RSA_REG_BASE_ADDR + 0x30) +#define RSA_CRC32_POLY_REG_OFS (RSA_REG_BASE_ADDR + 0x34) +#define RSA_CRC32_OUTPUT_REG_OFS (RSA_REG_BASE_ADDR + 0x38) + +// Crypto +#define CRYPTO_CONFREG_SWRST (1<<0) +#define CRYPTO_CONFREG_CRYPTO_EN (1<<1) +#define CRYPTO_CONFREG_AES128 (2<<4) +#define CRYPTO_CONFREG_DECRYPT (1<<8) + +#define CRYPTO_PIO_DONE (1<<0) + +// Hash +#define HASH_CONFREG_INITSTATE (1<<20) +#define HASH_CONFREG_SHA256 (1<<4) +#define HASH_CONFREG_ENABLE (1<<1) + +//RSA +#define RSA_ENABLE (1<<0) + +#define RSA_KEYWIDTH_256 (0x0<<1) +#define RSA_KEYWIDTH_512 (0x1<<1) +#define RSA_KEYWIDTH_1024 (0x2<<1) +#define RSA_KEYWIDTH_2048 (0x3<<1) +#define RSA_KEYWIDTH_4096 (0x4<<1) + +#define RSA_NORMAL_MODE (0x0<<4) +#define RSA_MODE_CRC_KEY_N (0x1<<4) +#define RSA_MODE_CRC_KEY_ED (0x2<<4) + + +#define RSA_TRANSFER_END (0x1<<0) +#define RSA_BUSY (0x1<<1) + +#define HASH_TRANSFER_END (0x1<<0) + + + +#define TOP_CTRL_SRAM_RESET_REG0 (TOP_CTRL_REG_BASE_ADDR + 0x1000) + +//Shut down SRAM SDIO1 mask +#define TOP_SRAM_SD_SDIO1 0x20000000 +//Shut down SRAM RSA mask +#define TOP_SRAM_SD_RSA 0x02000000 + + +#define reg0_cache_type_ofs 0x004 //reg0_cache_type +#define CACHE_CTRL_REG_OFS 0x100 +#define CACHE_AUX_CTRL_REG_OFS 0x104 + +#define CACHE_TAG_RAM_CTRL_OFS 0x108 +#define CACHE_DATA_RAM_CTRL_OFS 0x10C + + +#define reg2_int_clear_ofs 0x220 //reg2_int_clear +#define reg7_cache_sync 0x730 //reg7_cache_sync +#define reg7_inv_way 0x77C //reg7_inv_way + +#define CACHE_PREFETCH_REG_OFS 0xF60 + +#define L2_REG0_BASE (L2_MEM_BASE + 0x000) /* Cache ID and Cache Type */ +#define L2_REG1_BASE (L2_MEM_BASE + 0x100) /* Control */ +#define L2_REG2_BASE (L2_MEM_BASE + 0X200) /* Interrupt and Counter Control Registers */ +#define L2_REG7_BASE (L2_MEM_BASE + 0x700) /* Cache Maintenance Operations */ +#define L2_REG9_BASE (L2_MEM_BASE + 0x900) /* Cache Lockdown */ +#define L2_REG12_BASE (L2_MEM_BASE + 0xC00) /* Address Filtering */ +#define L2_REG15_BASE (L2_MEM_BASE + 0xF00) /* Debug, Prefetch and Power */ + +/** + * Cache ID and Cache Type + */ +#define L2_REG0_CACHE_ID (*((volatile unsigned long *)(L2_REG0_BASE + 0x00))) +#define L2_REG0_CACHE_TYPE (*((volatile unsigned long *)(L2_REG0_BASE + 0x04))) + +#define S_L2_REG0_CACHE_TYPE_DB (31) +#define M_L2_REG0_CACHE_TYPE_DB (0xf << S_L2_REG0_CACHE_TYPE_DB) +#define S_L2_REG0_CACHE_TYPE_CTYPE (25) +#define M_L2_REG0_CACHE_TYPE_CTYPE (0xf << S_L2_REG0_CACHE_TYPE_CTYPE) +#define S_L2_REG0_CACHE_TYPE_H (24) +#define M_L2_REG0_CACHE_TYPE_H (0x1 << S_L2_REG0_CACHE_TYPE_H) +#define S_L2_REG0_CACHE_TYPE_DWS (20) +#define M_L2_REG0_CACHE_TYPE_DWS (0x7 << S_L2_REG0_CACHE_TYPE_DWS) +#define S_L2_REG0_CACHE_TYPE_DA (18) +#define M_L2_REG0_CACHE_TYPE_DA (0x1 << S_L2_REG0_CACHE_TYPE_DA) +#define S_L2_REG0_CACHE_TYPE_DLS (12) +#define M_L2_REG0_CACHE_TYPE_DLS (0x3 << S_L2_REG0_CACHE_TYPE_DLS) +#define S_L2_REG0_CACHE_TYPE_IWS (8) +#define M_L2_REG0_CACHE_TYPE_IWS (0x7 << S_L2_REG0_CACHE_TYPE_IWS) +#define S_L2_REG0_CACHE_TYPE_IA (6) +#define M_L2_REG0_CACHE_TYPE_IA (0x1 << S_L2_REG0_CACHE_TYPE_IA) +#define S_L2_REG0_CACHE_TYPE_ILS (0) +#define M_L2_REG0_CACHE_TYPE_ILS (0x3 << S_L2_REG0_CACHE_TYPE_ILS) + +#define K_L2_REG0_CACHE_TYPE_DA_16WAY (1) +#define K_L2_REG0_CACHE_TYPE_DA_8WAY (0) + +/** + * Control + */ +#define L2_REG1_CONTROL (*((volatile unsigned long *)(L2_REG1_BASE + 0x00))) +#define L2_REG1_AUX_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x04))) +#define L2_REG1_TAG_RAM_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x08))) +#define L2_REG1_DATA_RAM_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x0C))) + +#define S_L2_REG1_CONTROL_EN (0) +#define M_L2_REG1_CONTROL_EN (0x1 << S_L2_REG1_CONTROL_EN) + +#define K_L2_REG1_CONTROL_EN_ON 1 +#define K_L2_REG1_CONTROL_EN_OFF 0 + +#define S_L2_REG1_AUX_CTRL_BRESP (30) +#define M_L2_REG1_AUX_CTRL_BRESP (0x1 << S_L2_REG1_AUX_CTRL_BRESP) +#define S_L2_REG1_AUX_CTRL_INSTR_PREF (29) +#define M_L2_REG1_AUX_CTRL_INSTR_PREF (0x1 << S_L2_REG1_AUX_CTRL_INSTR_PREF) +#define S_L2_REG1_AUX_CTRL_DATA_PERF (28) +#define M_L2_REG1_AUX_CTRL_DATA_PERF (0x1 << S_L2_REG1_AUX_CTRL_DATA_PERF) +#define S_L2_REG1_AUX_CTRL_NS_INT_CTRL (27) +#define M_L2_REG1_AUX_CTRL_NS_INT_CTRL (0x1 << S_L2_REG1_AUX_CTRL_NS_INT_CTRL) +#define S_L2_REG1_AUX_CTRL_NS_LOCK_EN (26) +#define M_L2_REG1_AUX_CTRL_NS_LOCK_EN (0x1 << S_L2_REG1_AUX_CTRL_NS_LOCK_EN) +#define S_L2_REG1_AUX_CTRL_CACHE_POLICY (25) +#define M_L2_REG1_AUX_CTRL_CACHE_POLICY (0x1 << S_L2_REG1_AUX_CTRL_CACHE_POLICY) +#define S_L2_REG1_AUX_CTRL_FORCE_WA (23) +#define M_L2_REG1_AUX_CTRL_FORCE_WA (0x3 << S_L2_REG1_AUX_CTRL_FORCE_WA) +#define S_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN (22) +#define M_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN (0x1 << S_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN) +#define S_L2_REG1_AUX_CTRL_PARITY_EN (21) +#define M_L2_REG1_AUX_CTRL_PARITY_EN (0x1 << S_L2_REG1_AUX_CTRL_PARITY_EN) +#define S_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN (20) +#define M_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN (0x1 << S_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN) +#define S_L2_REG1_AUX_CTRL_WAT_SIZE (17) +#define M_L2_REG1_AUX_CTRL_WAT_SIZE (0x7 << S_L2_REG1_AUX_CTRL_WAT_SIZE) +#define S_L2_REG1_AUX_CTRL_ASSOCIATIVITY (16) +#define M_L2_REG1_AUX_CTRL_ASSOCIATIVITY (0x1 << S_L2_REG1_AUX_CTRL_ASSOCIATIVITY) +#define S_L2_REG1_AUX_CTRL_SHARED_INV_EN (13) +#define M_L2_REG1_AUX_CTRL_SHARED_INV_EN (0x1 << S_L2_REG1_AUX_CTRL_SHARED_INV_EN) +#define S_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF (12) +#define M_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF (0x1 << S_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF) +#define S_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN (11) +#define M_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN (0x1 << S_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN) +#define S_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN (10) +#define M_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN (0x1 << S_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN) +#define S_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN (0) +#define M_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN (0x1 << S_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN) + +/** + * Interrupt and Counter Control Registers + */ +#define L2_REG2_EV_CNT_CTRL (*((volatile unsigned long *)(L2_REG2_BASE + 0x00))) +#define L2_REG2_EV_CNT1_CFG (*((volatile unsigned long *)(L2_REG2_BASE + 0x04))) +#define L2_REG2_EV_CNT0_CFG (*((volatile unsigned long *)(L2_REG2_BASE + 0x08))) +#define L2_REG2_EV_CNT1 (*((volatile unsigned long *)(L2_REG2_BASE + 0x0C))) +#define L2_REG2_EV_CNT0 (*((volatile unsigned long *)(L2_REG2_BASE + 0x10))) +#define L2_REG2_INT_MASK (*((volatile unsigned long *)(L2_REG2_BASE + 0x14))) +#define L2_REG2_INT_MASK_STATUS (*((volatile unsigned long *)(L2_REG2_BASE + 0x18))) +#define L2_REG2_INT_RAW_STATUS (*((volatile unsigned long *)(L2_REG2_BASE + 0x1C))) +#define L2_REG2_INT_CLEAR (*((volatile unsigned long *)(L2_REG2_BASE + 0x20))) + +#define S_L2_REG2_INT_DECERR (8) +#define M_L2_REG2_INT_DECERR (0x1 << S_L2_REG2_INT_DECERR) /* Decode error */ +#define S_L2_REG2_INT_SLVERR (7) +#define M_L2_REG2_INT_SLVERR (0x1 << S_L2_REG2_INT_SLVERR) /* Slave error */ +#define S_L2_REG2_INT_ERRRD (6) +#define M_L2_REG2_INT_ERRRD (0x1 << S_L2_REG2_INT_ERRRD) /* Data RAM read error */ +#define S_L2_REG2_INT_ERRRT (5) +#define M_L2_REG2_INT_ERRRT (0x1 << S_L2_REG2_INT_ERRRT) /* Tag RAM read error */ +#define S_L2_REG2_INT_ERRWD (4) +#define M_L2_REG2_INT_ERRWD (0x1 << S_L2_REG2_INT_ERRWD) /* Data RAM write error */ +#define S_L2_REG2_INT_ERRWT (3) +#define M_L2_REG2_INT_ERRWT (0x1 << S_L2_REG2_INT_ERRWT) /* Tag RAM write error */ +#define S_L2_REG2_INT_PARRD (2) +#define M_L2_REG2_INT_PARRD (0x1 << S_L2_REG2_INT_PARRD) /* Parity error on data RAM read */ +#define S_L2_REG2_INT_PARRT (1) +#define M_L2_REG2_INT_PARRT (0x1 << S_L2_REG2_INT_PARRT) /* Pariry error on tag RAM read */ +#define S_L2_REG2_INT_ECNTR (0) +#define M_L2_REG2_INT_ECNTR (0x1 << S_L2_REG2_INT_ECNTR) /* Event counter1/0 overflow increment */ + +/** + * Cache Maintenance Operations + */ +#define L2_REG7_CACHE_SYNC (*((volatile unsigned long *)(L2_REG7_BASE + 0x30))) +#define L2_REG7_INV_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0x70))) +#define L2_REG7_INV_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0x7C))) +#define L2_REG7_CLEAN_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0xB0))) +#define L2_REG7_CLEAN_INDEX (*((volatile unsigned long *)(L2_REG7_BASE + 0xB8))) +#define L2_REG7_CLEAN_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0xBC))) +#define L2_REG7_CLEAN_INV_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0xF0))) +#define L2_REG7_CLEAN_INV_INDEX (*((volatile unsigned long *)(L2_REG7_BASE + 0xF8))) +#define L2_REG7_CLEAN_INV_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0xFC))) + + +#define K_L2_REG7_CACHE_SYNC_C (0x1) + +#define K_L2_REG7_INV_WAY_8WAY (0x00ff) +#define K_L2_REG7_INV_WAY_16WAY (0xffff) +#define K_L2_REG7_CLEAN_WAY_8WAY (0x00ff) +#define K_L2_REG7_CLEAN_WAY_16WAY (0xffff) + + +/** + * Cache Lockdown + */ +#define L2_REG9_D_LOCKDOWN0 (*((volatile unsigned long *)(L2_REG9_BASE + 0x00))) +#define L2_REG9_I_LOCKDOWN0 (*((volatile unsigned long *)(L2_REG9_BASE + 0x04))) +#define L2_REG9_D_LOCKDOWN1 (*((volatile unsigned long *)(L2_REG9_BASE + 0x08))) +#define L2_REG9_I_LOCKDOWN1 (*((volatile unsigned long *)(L2_REG9_BASE + 0x0C))) +#define L2_REG9_D_LOCKDOWN2 (*((volatile unsigned long *)(L2_REG9_BASE + 0x10))) +#define L2_REG9_I_LOCKDOWN2 (*((volatile unsigned long *)(L2_REG9_BASE + 0x14))) +#define L2_REG9_D_LOCKDOWN3 (*((volatile unsigned long *)(L2_REG9_BASE + 0x18))) +#define L2_REG9_I_LOCKDOWN3 (*((volatile unsigned long *)(L2_REG9_BASE + 0x1C))) +#define L2_REG9_D_LOCKDOWN4 (*((volatile unsigned long *)(L2_REG9_BASE + 0x20))) +#define L2_REG9_I_LOCKDOWN4 (*((volatile unsigned long *)(L2_REG9_BASE + 0x24))) +#define L2_REG9_D_LOCKDOWN5 (*((volatile unsigned long *)(L2_REG9_BASE + 0x28))) +#define L2_REG9_I_LOCKDOWN5 (*((volatile unsigned long *)(L2_REG9_BASE + 0x2C))) +#define L2_REG9_D_LOCKDOWN6 (*((volatile unsigned long *)(L2_REG9_BASE + 0x30))) +#define L2_REG9_I_LOCKDOWN6 (*((volatile unsigned long *)(L2_REG9_BASE + 0x34))) +#define L2_REG9_D_LOCKDOWN7 (*((volatile unsigned long *)(L2_REG9_BASE + 0x38))) +#define L2_REG9_I_LOCKDOWN7 (*((volatile unsigned long *)(L2_REG9_BASE + 0x3C))) +#define L2_REG9_LOCK_LINE_EN (*((volatile unsigned long *)(L2_REG9_BASE + 0x50))) +#define L2_REG9_UNLOCK_WAY (*((volatile unsigned long *)(L2_REG9_BASE + 0x54))) + +/** + * Address Filtering + */ +#define L2_REG12_ADDR_FILTERING_START (*((volatile unsigned long *)(L2_REG12_BASE + 0x00))) +#define L2_REG12_ADDR_FILTERING_END (*((volatile unsigned long *)(L2_REG12_BASE + 0x04))) + +/** + * Debug, Prefetch and Power + */ +#define L2_REG15_DEBUG_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x40))) +#define L2_REG15_PREF_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x60))) +#define L2_REG15_POWER_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x80))) + +#define S_L2_REG15_DEBUG_CTRL_SPNIDEN (2) +#define M_L2_REG15_DEBUG_CTRL_SPNIDEN (0x1 << S_L2_REG15_DEBUG_CTRL_SPNIDEN) +#define S_L2_REG15_DEBUG_CTRL_DWB (1) +#define M_L2_REG15_DEBUG_CTRL_DWB (0x1 << S_L2_REG15_DEBUG_CTRL_DWB) +#define S_L2_REG15_DEBUG_CTRL_DCL (0) +#define M_L2_REG15_DEBUG_CTRL_DCL (0x1 << S_L2_REG15_DEBUG_CTRL_DCL) + +#define S_L2_REG15_PREF_CTRL_DL_FILL_EN (30) +#define M_L2_REG15_PREF_CTRL_DL_FILL_EN (0x1 << S_L2_REG15_PREF_CTRL_DL_FILL_EN) +#define S_L2_REG15_PREF_CTRL_INST_PREF_EN (29) +#define M_L2_REG15_PREF_CTRL_INST_PREF_EN (0x1 << S_L2_REG15_PREF_CTRL_INST_PREF_EN) +#define S_L2_REG15_PREF_CTRL_DATA_PREF_EN (28) +#define M_L2_REG15_PREF_CTRL_DATA_PREF_EN (0x1 << S_L2_REG15_PREF_CTRL_DATA_PREF_EN) +#define S_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS (27) +#define M_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS (0x1 << S_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS) +#define S_L2_REG15_PREF_CTRL_PREF_DROP_EN (24) +#define M_L2_REG15_PREF_CTRL_PREF_DROP_EN (0x1 << S_L2_REG15_PREF_CTRL_PREF_DROP_EN) +#define S_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN (23) +#define M_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN (0x1 << S_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN) +#define S_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN (21) +#define M_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN (0x1 << S_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN) +#define S_L2_REG15_PREF_CTRL_PREF_OFF (0) +#define M_L2_REG15_PREF_CTRL_PREF_OFF (0xf << S_L2_REG15_PREF_CTRL_PREF_OFF) + +// DDR phy duty configuration register bit +#define DDR_PHY_INCREASE_DUTY 0x40 // P < N +#define DDR_PHY_DECREASE_DUTY 0x00 // P > N +#define DDR_PHY_DUTY_TYPE_MSK 0x40 // bit mask for increase/decrease duty +#define DDR_PHY_CLK_ADJ_EN 0x80 + +// DDR phy duty calibration control register bit +#define DDR_PHY_CLK_OP_ONGOING 0x10 +#define DDR_PHY_CLK_OP_DONE 0x00 +#define DDR_PHY_DQS_OP_ONGOING 0x20 +#define DDR_PHY_DQS_OP_DONE 0x00 + + +# define DDR_PHY_CAL_CLK_ADJ_OFS 0x000 /* 0x00 */ +# define DDR_PHY_CAL_CMD_ADJ_OFS 0x01C /* 0x1C */ +# define DDR_PHY_CAL_CTRL_OFS 0x150 /* 0x54 */ +# define DDR_PHY_CAL_CLK_CFG_OFS 0x154 /* 0x55 */ +# define DDR_PHY_CAL_DQS_CFG_OFS 0x158 /* 0x56 */ +# define DDR_PHY_CAL_DTY_CNT_LB_OFS 0x15C /* 0x57 duty cnt low byte */ +# define DDR_PHY_CAL_DTY_CNT_HB_OFS 0x160 /* 0x58 duty cnt high byte */ +# define DDR_PHY_CAL_DQS0_ADJ_OFS 0x1D0 /* 0x1D0 */ +# define DDR_PHY_CAL_DQ_ADJ_OFS 0x1D4 /* 0x1D0 */ + + +#define BOOT_SOURCE_SPI 0x00 +#define BOOT_SOURCE_CARD 0x01 +#define BOOT_SOURCE_SPI_NAND_2K 0x02 +#define BOOT_SOURCE_SPI_NAND_RS_2K 0x03 +#define BOOT_SOURCE_ETHERNET 0x04 +#define BOOT_SOURCE_USB 0x05 +#define BOOT_SOURCE_SPI_NAND_4K 0x06 +#define BOOT_SOURCE_BMC 0x07 +#define BOOT_SOURCE_EMMC_4BIT 0x08 +#define BOOT_SOURCE_EMMC_8BIT 0x09 +#define BOOT_SOURCE_SPI_NAND_RS_4K 0x0A +#define BOOT_SOURCE_USB_FULL 0x0B + +#define BOOT_SOURCE_MSK 0x0F + + +# define IDENTIFY_ERR 2 +# define MBR_ERR 3 +# define PBR_ERR 4 +# define READ512_ERR 5 +# define READ_ERR 7 +# define HPA_ERR 8 +# define CHECKSUM_ERR 9 +#ifndef __ASSEMBLY__ + END +#endif +# endif diff --git a/board/novatek/na51055/loader/Include/Driver/crypto.h b/board/novatek/na51055/loader/Include/Driver/crypto.h new file mode 100755 index 000000000000..4ac5318aaa53 --- /dev/null +++ b/board/novatek/na51055/loader/Include/Driver/crypto.h @@ -0,0 +1,98 @@ +/** + Header file for CC (Core Communicator) module. + + This file is the header file that define the API and data type + for CC module. + + @file CC.h + @ingroup mIDrvSys_CC + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ + +#include "constant.h" + +#ifndef _CRYPTO_H +#define _CRYPTO_H + +#define ROM_AES_SIZE (16) +#define ROM_SHA_SIZE (32) // unit: byte +#define ROM_RSA_SIZE (256) // RSA-2048 +#define ROM_RSA_EKEY_SIZE (32) +#define ROM_RSA_CRC32_SIZE (4) +/** + Crypto engine crypto mode +*/ +typedef enum { + CRYPTO_RSV0, + CRYPTO_RSV1, + CRYPTO_AES, ///< Select Crypto mode AES + CRYPTO_MODE_NUM, +} CRYPTO_MODE; + +/** + Crypto engine crypto Operating mode +*/ +typedef enum { + CRYPTO_EBC = 0x00, ///< Select Crypto opmode EBC + CRYPTO_CBC, ///< Select Crypto opmode CBC + CRYPTO_OPMODE_NUM, +} CRYPTO_OPMODE; + +/** + Crypto engine encrypt or decrypt +*/ +typedef enum { + CRYPTO_ENCRYPT = 0x00, ///< Select Crypto engine encrypt + CRYPTO_DECRYPT, ///< Select Crypto engine decrypt + CRYPTO_TYPE_NUM, + +} CRYPTO_TYPE; + +typedef enum { + EFUSE_OTP_1ST_KEY_SET_FIELD = 0x0, // This if for secure boot + EFUSE_OTP_2ND_KEY_SET_FIELD, + EFUSE_OTP_3RD_KEY_SET_FIELD, + EFUSE_OTP_4TH_KEY_SET_FIELD, + + EFUSE_OTP_TOTAL_KEY_SET_FIELD, +} EFUSE_OTP_KEY_SET_FIELD; + +typedef struct _CRYPT_OP { + CRYPTO_OPMODE op_mode; ///< Operation Mode (now support ECB only) + CRYPTO_TYPE en_de_crypt; ///< Encrypt or decrypt (CRYPTO_ENCRYPT or CRYPTO_DECRYPT) + UINT32 src_addr; ///< Source address + UINT32 dst_addr; ///< Destination address + UINT32 length; ///< length +} CRYPT_OP; + +/** + Crypto engine check +*/ +typedef enum { + SECUREBOOT_SECURE_EN = 0x00, ///< Quary if secure enable or not + SECUREBOOT_DATA_AREA_ENCRYPT, ///< Quary if data area encrypt to cypher text or not + SECUREBOOT_SIGN_RSA, ///< Quary if Signature methed is RSA or not(AES) + SECUREBOOT_SIGN_RSA_CHK, ///< Quary if Signature hash checksum RSA key correct or not + SECUREBOOT_STATUS_NUM, + +} SECUREBOOT_STATUS; + +#define is_secure_enable() quary_secure_boot(SECUREBOOT_SECURE_EN) //For backward compatitable +#define is_data_area_encrypted() quary_secure_boot(SECUREBOOT_DATA_AREA_ENCRYPT) //For backward compatitable +#define is_signature_rsa() quary_secure_boot(SECUREBOOT_SIGN_RSA) //For backward compatitable +#define is_signature_aes() !quary_secure_boot(SECUREBOOT_SIGN_RSA) //For backward compatitable +BOOL quary_secure_boot(SECUREBOOT_STATUS scu_status); +UINT32 crypto_data_operation(EFUSE_OTP_KEY_SET_FIELD key_set, CRYPT_OP crypt_op_param); +void rsa_setConfig(UINT32 mode); +void rsa_setkey_n(UINT8* key, UINT32 len, UINT32 sram_size); +void rsa_setkey_ed(UINT8* key, UINT32 len, UINT32 sram_size); +INT32 rsa_pio_enable(UINT8* data, UINT32 len, UINT32 sram_size); +void rsa_getOutput(UINT8 * Output, UINT32 len, UINT32 sram_size); + +void shahw( const unsigned char *input, int ilen, UINT32 output[8]); +void rsa_decrypt(UINT32 *input ,UINT32 input_len, UINT32 *pRSAN, UINT32 RSAN_len, UINT32 *pRSAED, UINT32 RSAED_len , UINT32 *pShaOut); +BOOL rsa_keycheck(UINT32 *input , BOOL efuseCheck); + +#endif diff --git a/board/novatek/na51055/loader/Include/Driver/nand.h b/board/novatek/na51055/loader/Include/Driver/nand.h new file mode 100755 index 000000000000..824fe21bce71 --- /dev/null +++ b/board/novatek/na51055/loader/Include/Driver/nand.h @@ -0,0 +1,123 @@ +/** + nand module driver. + + This file is the driver of storage module. + + @file nand.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _NAND_DEF_ +#define _NAND_DEF_ + +#include "IOReg.h" + +#define _SNAND_WINBOND_ID (0xEF) +#define _SNAND_ESMT_ID (0xC8) +#define _SNAND_GD_ID (0xC8) +#define _SNAND_MICRON_ID (0x2C) +#define _SNAND_ATO_ID (0x9B) +#define _SNAND_ETRON_ID (0xD5) +#define _SNAND_MXIC_ID (0xC2) +#define _SNAND_TOSHIBA_ID (0x98) +#define _SNAND_DOSILICON_ID (0xE5) +#define _SNAND_FMS_ID (0xA1) +#define _SNAND_XTX_ID (0x2C) + + +#define _GD_SPI_NAND_1Gb (0xF1) +#define _MXIC_SPI_NAND_1Gb (0x12) +#define _DOSILICON_NAND_1Gb (0x71) +/** + SPI NAND flash QE(quid enable) identify type + +*/ + +//@{ +typedef enum { + SPINAND_QE_NONE = 0x0, ///< SPI NAND flash not with QE bit(only by quad command) + SPINAND_QE_FEATURE2_B0H_BIT0_TYPE1, ///< SPI NAND flash QE bit locate at feature field(0xB0H) bit[0] +} SPINAND_QE_TYPE; + + +/** + SPI NAND flash twp plane identify type + +*/ +//@{ +typedef enum { + SPINAND_2_PLANE_NONE = 0x0, ///< SPI NAND flash not 2 plane type + SPINAND_2_PLANE_COLUMN_ADDR_BIT_12_AS_PLANE_SEL,///< SPI NAND flash use column addr bit[12] as plane select +} SPINAND_PLANE_TYPE; + + + +/** + SPI flash identification structure + + @note For SPIFLASH_IDENTIFY_CB +*/ +typedef struct { + UINT32 pagesize; + UINT32 erasesize; + UINT32 qe_opt; + UINT32 plane_opt; +} SPINAND_IDENTIFY, *PSPINAND_IDENTIFY; + +/** + SPIFLASH identify callback + + Callback routine to be invoked after JEDEC ID is read from spi flash. + Callback routine should check if read ID is supported. + + @note STRG_EXT_CMD_SPI_IDENTIFY_CB + + @param[in] first parameter (JEDEC) manufacturer ID read from spi flash + @param[in] second parameter (JEDEC) type ID read from spi flash + @param[in] third parameter (JEDEC) capacity ID read from spi flash + @param[out] forth parameter flash identification returned to spi flash driver + + @return + - @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information + - @b FALSE: input ID is NOT supported/identified by call back +*/ +typedef BOOL (*SPINAND_IDENTIFY_CB)(UINT32, UINT32, UINT32, PSPINAND_IDENTIFY); + + + + +/** + * struct nand_flash_dev - NAND Flash Device ID Structure + * @mfr_id: manufecturer ID part of the full chip ID array (refers the same + * memory address as @id[0]) + * @dev_id: the device ID (the second byte of the full chip ID array) + * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as + * well as the eraseblock size) is determined from the extended NAND + * chip ID array) + * @erasesize: NAND block size + * @qe_opt: Quad enable type(please reference document to select this option) + * @plane_opt: 2 plane nand option(please reference document to select this option) + * @options: stores various chip bit options + * + */ +typedef struct _nand_flash_dev { + UINT32 mfr_id; + UINT32 dev_id; + UINT32 third_id; + UINT32 pagesize; + UINT32 erasesize; + UINT32 qe_opt; + UINT32 plane_opt; +} NAND_FLASH_DEV, *PNAND_FLASH_DEV; + +#define SPI_ID_NAND(mfrid, devid, third, pagesz, erasesz, opts, plane_opt_type)\ + { .mfr_id =(mfrid), .dev_id = (devid), .third_id = (third), .pagesize = (pagesz), \ + .erasesize = (erasesz), .qe_opt = (opts), .plane_opt=(plane_opt_type) } + +extern BOOL nand_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiThirdID, PSPINAND_IDENTIFY pIdentify); + +#endif + diff --git a/board/novatek/na51055/loader/Include/Driver/nor.h b/board/novatek/na51055/loader/Include/Driver/nor.h new file mode 100755 index 000000000000..5c1128410b98 --- /dev/null +++ b/board/novatek/na51055/loader/Include/Driver/nor.h @@ -0,0 +1,51 @@ +/** + nand module driver. + + This file is the driver of storage module. + + @file nand.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _NOR_DEF_ +#define _NOR_DEF_ + +#include "IOReg.h" +#include "StorageDef.h" + + +/** + * struct nand_flash_dev - NAND Flash Device ID Structure + * @name: a human-readable name of the NAND chip + * @dev_id: the device ID (the second byte of the full chip ID array) + * @mfr_id: manufecturer ID part of the full chip ID array (refers the same + * memory address as @id[0]) + * @dev_id: device ID part of the full chip ID array (refers the same memory + * address as @id[1]) + * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as + * well as the eraseblock size) is determined from the extended NAND + * chip ID array) + * @chipsize: total chip size in MiB + * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) + * @options: stores various chip bit options + * + */ +typedef struct _nor_flash_dev { + UINT32 mfr_id; + UINT32 dev_id; + UINT32 capacity_id; + UINT32 bDualRead; + UINT32 uiQuadReadType; + UINT32 uiFlashSize; +} NOR_FLASH_DEV, *PNOR_FLASH_DEV; + +#define SPI_ID_NOR(mfrid, devid, capacityid, dual_read, quad_read_type, flash_size)\ + { .mfr_id =(mfrid), .dev_id = (devid), .capacity_id =(capacityid), .bDualRead=(dual_read), \ + .uiQuadReadType=(quad_read_type), .uiFlashSize=(flash_size) } + + +extern BOOL nor_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify); +#endif diff --git a/board/novatek/na51055/loader/Include/Driver/pad.h b/board/novatek/na51055/loader/Include/Driver/pad.h new file mode 100755 index 000000000000..7476029602eb --- /dev/null +++ b/board/novatek/na51055/loader/Include/Driver/pad.h @@ -0,0 +1,874 @@ +/** + PAD controller header + + PAD controller header + + @file pad.h + @ingroup mIHALSysPAD + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _PAD_H +#define _PAD_H + +//#include "Type.h" +#include "constant.h" + + + +/** \addtogroup mIHALSysPAD */ +//@{ + +// Macro to generate dummy element for enum type to expand enum size to word (4 bytes) +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + +#if 0 +/** + Pad type select + + Pad type select + + Pad type value for pad_setPullUpDown(). +*/ +typedef enum +{ + PAD_NONE = 0x00, ///< none of pull up/down + PAD_PULLDOWN = 0x01, ///< pull down + PAD_PULLUP = 0x02, ///< pull up + PAD_KEEPER = 0x03, ///< keeper + + ENUM_DUMMY4WORD(PAD_PULL) +} PAD_PULL; + +/** + Pad driving select + + Pad driving select + + Pad driving value for pad_setDrivingSink(). +*/ +typedef enum { + PAD_DRIVINGSINK_2P5MA = 0x01, ///< for backward compatible + PAD_DRIVINGSINK_5MA = 0x02, ///< Pad driver/sink 5mA + PAD_DRIVINGSINK_7P5MA = 0x04, ///< for backward compatible + PAD_DRIVINGSINK_10MA = 0x08, ///< Pad driver/sink 10mA + + PAD_DRIVINGSINK_12P5MA = 0x10, ///< for backward compatible + PAD_DRIVINGSINK_15MA = 0x20, ///< Pad driver/sink 15mA + PAD_DRIVINGSINK_17P5MA = 0x40, ///< for backward compatible + PAD_DRIVINGSINK_20MA = 0x80, ///< Pad driver/sink 20mA + PAD_DRIVINGSINK_25MA = 0x100, ///< Pad driver/sink 25mA + PAD_DRIVINGSINK_30MA = 0x200, ///< Pad driver/sink 30mA + PAD_DRIVINGSINK_35MA = 0x400, ///< Pad driver/sink 35mA + PAD_DRIVINGSINK_40MA = 0x800, ///< Pad driver/sink 40mA + PAD_DRIVINGSINK_4MA = 0x1000, ///< PAD driver/sink 4mA + PAD_DRIVINGSINK_6MA = 0x2000, ///< PAD driver/sink 6mA + PAD_DRIVINGSINK_8MA = 0x4000, ///< PAD driver/sink 8mA + PAD_DRIVINGSINK_16MA = 0x8000, ///< PAD driver/sink 16mA + + ENUM_DUMMY4WORD(PAD_DRIVINGSINK) +} PAD_DRIVINGSINK; + +/** + @name Pad type pin ID. + + Pad type pin ID. + + Pad ID of pad_setPullUpDown(). +*/ +#define PAD_PIN_NOT_EXIST (15) // For backward compatible +//@{ +//CGPIOx group begin +#define PAD_PIN_CGPIO_BASE 0 +#define PAD_PIN_CGPIO0 (PAD_PIN_CGPIO_BASE + 0) ///< CGPIO0 +#define PAD_PIN_CGPIO1 (PAD_PIN_CGPIO_BASE + 1) ///< CGPIO1 +#define PAD_PIN_CGPIO2 (PAD_PIN_CGPIO_BASE + 2) ///< CGPIO2 +#define PAD_PIN_CGPIO3 (PAD_PIN_CGPIO_BASE + 3) ///< CGPIO3 +#define PAD_PIN_CGPIO4 (PAD_PIN_CGPIO_BASE + 4) ///< CGPIO4 +#define PAD_PIN_CGPIO5 (PAD_PIN_CGPIO_BASE + 5) ///< CGPIO5 +#define PAD_PIN_CGPIO6 (PAD_PIN_CGPIO_BASE + 6) ///< CGPIO6 +#define PAD_PIN_CGPIO7 (PAD_PIN_CGPIO_BASE + 7) ///< CGPIO7 +#define PAD_PIN_CGPIO8 (PAD_PIN_CGPIO_BASE + 8) ///< CGPIO8 +#define PAD_PIN_CGPIO9 (PAD_PIN_CGPIO_BASE + 9) ///< CGPIO9 +#define PAD_PIN_CGPIO10 (PAD_PIN_CGPIO_BASE + 10) ///< CGPIO10 +#define PAD_PIN_CGPIO11 (PAD_PIN_CGPIO_BASE + 11) ///< CGPIO11 +#define PAD_PIN_CGPIO12 (PAD_PIN_CGPIO_BASE + 12) ///< CGPIO12 +#define PAD_PIN_CGPIO13 (PAD_PIN_CGPIO_BASE + 13) ///< CGPIO13 +#define PAD_PIN_CGPIO14 (PAD_PIN_CGPIO_BASE + 14) ///< CGPIO14 +#define PAD_PIN_CGPIO15 (PAD_PIN_CGPIO_BASE + 15) ///< CGPIO15 + +#define PAD_PIN_CGPIO16 (PAD_PIN_CGPIO_BASE + 16) ///< CGPIO16 +#define PAD_PIN_CGPIO17 (PAD_PIN_CGPIO_BASE + 17) ///< CGPIO17 +#define PAD_PIN_CGPIO18 (PAD_PIN_CGPIO_BASE + 18) ///< CGPIO18 +#define PAD_PIN_CGPIO19 (PAD_PIN_CGPIO_BASE + 19) ///< CGPIO19 +#define PAD_PIN_CGPIO20 (PAD_PIN_CGPIO_BASE + 20) ///< CGPIO20 +#define PAD_PIN_CGPIO21 (PAD_PIN_CGPIO_BASE + 21) ///< CGPIO21 +#define PAD_PIN_CGPIO22 (PAD_PIN_CGPIO_BASE + 22) ///< CGPIO22 +#define PAD_PIN_CGPIO23 (PAD_PIN_CGPIO_BASE + 23) ///< CGPIO23 +#define PAD_PIN_CGPIO24 (PAD_PIN_CGPIO_BASE + 24) ///< CGPIO24 +#define PAD_PIN_CGPIO25 (PAD_PIN_CGPIO_BASE + 25) ///< CGPIO25 +#define PAD_PIN_CGPIO26 (PAD_PIN_CGPIO_BASE + 26) ///< CGPIO26 +#define PAD_PIN_CGPIO27 (PAD_PIN_CGPIO_BASE + 27) ///< CGPIO27 +#define PAD_PIN_CGPIO28 (PAD_PIN_CGPIO_BASE + 28) ///< CGPIO28 +#define PAD_PIN_CGPIO29 (PAD_PIN_CGPIO_BASE + 29) ///< CGPIO29 +#define PAD_PIN_CGPIO30 (PAD_PIN_CGPIO_BASE + 30) ///< CGPIO30 +#define PAD_PIN_CGPIO31 (PAD_PIN_CGPIO_BASE + 31) ///< CGPIO31 + +#define PAD_PIN_CGPIO32 (PAD_PIN_CGPIO_BASE + 32) ///< CGPIO32 +#define PAD_PIN_CGPIO33 (PAD_PIN_CGPIO_BASE + 33) ///< CGPIO33 +//CGPIOx group end + +//SGPIOx group begin +#define PAD_PIN_SGPIO_BASE 100 +#define PAD_PIN_SGPIO0 (PAD_PIN_SGPIO_BASE + 0) ///< SGPIO0 +#define PAD_PIN_SGPIO1 (PAD_PIN_SGPIO_BASE + 1) ///< SGPIO1 +#define PAD_PIN_SGPIO2 (PAD_PIN_SGPIO_BASE + 2) ///< SGPIO2 +#define PAD_PIN_SGPIO3 (PAD_PIN_SGPIO_BASE + 3) ///< SGPIO3 +#define PAD_PIN_SGPIO4 (PAD_PIN_SGPIO_BASE + 4) ///< SGPIO4 +#define PAD_PIN_SGPIO5 (PAD_PIN_SGPIO_BASE + 5) ///< SGPIO5 +#define PAD_PIN_SGPIO6 (PAD_PIN_SGPIO_BASE + 6) ///< SGPIO6 +#define PAD_PIN_SGPIO7 (PAD_PIN_SGPIO_BASE + 7) ///< SGPIO7 +#define PAD_PIN_SGPIO8 (PAD_PIN_SGPIO_BASE + 8) ///< SGPIO8 +#define PAD_PIN_SGPIO9 (PAD_PIN_SGPIO_BASE + 9) ///< SGPIO9 +#define PAD_PIN_SGPIO10 (PAD_PIN_SGPIO_BASE + 10) ///< SGPIO10 +#define PAD_PIN_SGPIO11 (PAD_PIN_SGPIO_BASE + 11) ///< SGPIO11 +//SGPIOx group end + +//PGPIOx group begin +#define PAD_PIN_PGPIO_BASE 150 +#define PAD_PIN_PGPIO0 (PAD_PIN_PGPIO_BASE + 0) ///< PGPIO0 +#define PAD_PIN_PGPIO1 (PAD_PIN_PGPIO_BASE + 1) ///< PGPIO1 +#define PAD_PIN_PGPIO2 (PAD_PIN_PGPIO_BASE + 2) ///< PGPIO2 +#define PAD_PIN_PGPIO3 (PAD_PIN_PGPIO_BASE + 3) ///< PGPIO3 +#define PAD_PIN_PGPIO4 (PAD_PIN_PGPIO_BASE + 4) ///< PGPIO4 +#define PAD_PIN_PGPIO5 (PAD_PIN_PGPIO_BASE + 5) ///< PGPIO5 +#define PAD_PIN_PGPIO6 (PAD_PIN_PGPIO_BASE + 6) ///< PGPIO6 +#define PAD_PIN_PGPIO7 (PAD_PIN_PGPIO_BASE + 7) ///< PGPIO7 +#define PAD_PIN_PGPIO8 (PAD_PIN_PGPIO_BASE + 8) ///< PGPIO8 +#define PAD_PIN_PGPIO9 (PAD_PIN_PGPIO_BASE + 9) ///< PGPIO9 +#define PAD_PIN_PGPIO10 (PAD_PIN_PGPIO_BASE + 10) ///< PGPIO10 +#define PAD_PIN_PGPIO11 (PAD_PIN_PGPIO_BASE + 11) ///< PGPIO11 +#define PAD_PIN_PGPIO12 (PAD_PIN_PGPIO_BASE + 12) ///< PGPIO12 +#define PAD_PIN_PGPIO13 (PAD_PIN_PGPIO_BASE + 13) ///< PGPIO13 +#define PAD_PIN_PGPIO14 (PAD_PIN_PGPIO_BASE + 14) ///< PGPIO14 +#define PAD_PIN_PGPIO15 (PAD_PIN_PGPIO_BASE + 15) ///< PGPIO15 + +#define PAD_PIN_PGPIO16 (PAD_PIN_PGPIO_BASE + 16) ///< PGPIO16 +#define PAD_PIN_PGPIO17 (PAD_PIN_PGPIO_BASE + 17) ///< PGPIO17 +#define PAD_PIN_PGPIO18 (PAD_PIN_PGPIO_BASE + 18) ///< PGPIO18 +#define PAD_PIN_PGPIO19 (PAD_PIN_PGPIO_BASE + 19) ///< PGPIO19 +#define PAD_PIN_PGPIO20 (PAD_PIN_PGPIO_BASE + 20) ///< PGPIO20 +#define PAD_PIN_PGPIO21 (PAD_PIN_PGPIO_BASE + 21) ///< PGPIO21 +#define PAD_PIN_PGPIO22 (PAD_PIN_PGPIO_BASE + 22) ///< PGPIO22 +#define PAD_PIN_PGPIO23 (PAD_PIN_PGPIO_BASE + 23) ///< PGPIO23 +#define PAD_PIN_PGPIO24 (PAD_PIN_PGPIO_BASE + 24) ///< PGPIO24 +#define PAD_PIN_PGPIO25 (PAD_PIN_PGPIO_BASE + 25) ///< PGPIO25 +#define PAD_PIN_PGPIO26 (PAD_PIN_PGPIO_BASE + 26) ///< PGPIO26 +#define PAD_PIN_PGPIO27 (PAD_PIN_PGPIO_BASE + 27) ///< PGPIO27 +#define PAD_PIN_PGPIO28 (PAD_PIN_PGPIO_BASE + 28) ///< PGPIO28 +#define PAD_PIN_PGPIO29 (PAD_PIN_PGPIO_BASE + 29) ///< PGPIO29 +#define PAD_PIN_PGPIO30 (PAD_PIN_PGPIO_BASE + 30) ///< PGPIO30 +#define PAD_PIN_PGPIO31 (PAD_PIN_PGPIO_BASE + 31) ///< PGPIO31 + +#define PAD_PIN_PGPIO32 (PAD_PIN_PGPIO_BASE + 32) ///< PGPIO32 +#define PAD_PIN_PGPIO33 (PAD_PIN_PGPIO_BASE + 33) ///< PGPIO33 +#define PAD_PIN_PGPIO34 (PAD_PIN_PGPIO_BASE + 34) ///< PGPIO34 +#define PAD_PIN_PGPIO35 (PAD_PIN_PGPIO_BASE + 35) ///< PGPIO35 +#define PAD_PIN_PGPIO36 (PAD_PIN_PGPIO_BASE + 36) ///< PGPIO36 +#define PAD_PIN_PGPIO37 (PAD_PIN_PGPIO_BASE + 37) ///< PGPIO37 +#define PAD_PIN_PGPIO38 (PAD_PIN_PGPIO_BASE + 38) ///< PGPIO38 +#define PAD_PIN_PGPIO39 (PAD_PIN_PGPIO_BASE + 39) ///< PGPIO39 +#define PAD_PIN_PGPIO40 (PAD_PIN_PGPIO_BASE + 40) ///< PGPIO40 +#define PAD_PIN_PGPIO41 (PAD_PIN_PGPIO_BASE + 41) ///< PGPIO41 +#define PAD_PIN_PGPIO42 (PAD_PIN_PGPIO_BASE + 42) ///< PGPIO42 +#define PAD_PIN_PGPIO43 (PAD_PIN_PGPIO_BASE + 43) ///< PGPIO43 +#define PAD_PIN_PGPIO44 (PAD_PIN_PGPIO_BASE + 44) ///< PGPIO44 +#define PAD_PIN_PGPIO45 (PAD_PIN_PGPIO_BASE + 45) ///< PGPIO45 +#define PAD_PIN_PGPIO46 (PAD_PIN_PGPIO_BASE + 46) ///< PGPIO46 +#define PAD_PIN_PGPIO47 (PAD_PIN_PGPIO_BASE + 47) ///< PGPIO47 +//PGPIOx group end + + +//LGPIOx group begin +#define PAD_PIN_LGPIO_BASE 250 +#define PAD_PIN_LGPIO0 (PAD_PIN_LGPIO_BASE + 0) ///< LGPIO0 +#define PAD_PIN_LGPIO1 (PAD_PIN_LGPIO_BASE + 1) ///< LGPIO1 +#define PAD_PIN_LGPIO2 (PAD_PIN_LGPIO_BASE + 2) ///< LGPIO2 +#define PAD_PIN_LGPIO3 (PAD_PIN_LGPIO_BASE + 3) ///< LGPIO3 +#define PAD_PIN_LGPIO4 (PAD_PIN_LGPIO_BASE + 4) ///< LGPIO4 +#define PAD_PIN_LGPIO5 (PAD_PIN_LGPIO_BASE + 5) ///< LGPIO5 +#define PAD_PIN_LGPIO6 (PAD_PIN_LGPIO_BASE + 6) ///< LGPIO6 +#define PAD_PIN_LGPIO7 (PAD_PIN_LGPIO_BASE + 7) ///< LGPIO7 +#define PAD_PIN_LGPIO8 (PAD_PIN_LGPIO_BASE + 8) ///< LGPIO8 +#define PAD_PIN_LGPIO9 (PAD_PIN_LGPIO_BASE + 9) ///< LGPIO9 +#define PAD_PIN_LGPIO10 (PAD_PIN_LGPIO_BASE + 10) ///< LGPIO10 +#define PAD_PIN_LGPIO11 (PAD_PIN_LGPIO_BASE + 11) ///< LGPIO11 +#define PAD_PIN_LGPIO12 (PAD_PIN_LGPIO_BASE + 12) ///< LGPIO12 +#define PAD_PIN_LGPIO13 (PAD_PIN_LGPIO_BASE + 13) ///< LGPIO13 +#define PAD_PIN_LGPIO14 (PAD_PIN_LGPIO_BASE + 14) ///< LGPIO14 +#define PAD_PIN_LGPIO15 (PAD_PIN_LGPIO_BASE + 15) ///< LGPIO15 + +#define PAD_PIN_LGPIO16 (PAD_PIN_LGPIO_BASE + 16) ///< LGPIO16 +#define PAD_PIN_LGPIO17 (PAD_PIN_LGPIO_BASE + 17) ///< LGPIO17 +#define PAD_PIN_LGPIO18 (PAD_PIN_LGPIO_BASE + 18) ///< LGPIO18 +#define PAD_PIN_LGPIO19 (PAD_PIN_LGPIO_BASE + 19) ///< LGPIO19 +#define PAD_PIN_LGPIO20 (PAD_PIN_LGPIO_BASE + 20) ///< LGPIO20 +#define PAD_PIN_LGPIO21 (PAD_PIN_LGPIO_BASE + 21) ///< LGPIO21 +#define PAD_PIN_LGPIO22 (PAD_PIN_LGPIO_BASE + 22) ///< LGPIO22 +#define PAD_PIN_LGPIO23 (PAD_PIN_LGPIO_BASE + 23) ///< LGPIO23 +#define PAD_PIN_LGPIO24 (PAD_PIN_LGPIO_BASE + 24) ///< LGPIO24 +#define PAD_PIN_LGPIO25 (PAD_PIN_LGPIO_BASE + 25) ///< LGPIO25 +#define PAD_PIN_LGPIO26 (PAD_PIN_LGPIO_BASE + 26) ///< LGPIO26 +#define PAD_PIN_LGPIO27 (PAD_PIN_LGPIO_BASE + 27) ///< LGPIO27 +#define PAD_PIN_LGPIO28 (PAD_PIN_LGPIO_BASE + 28) ///< LGPIO28 +#define PAD_PIN_LGPIO29 (PAD_PIN_LGPIO_BASE + 29) ///< LGPIO29 +#define PAD_PIN_LGPIO30 (PAD_PIN_LGPIO_BASE + 30) ///< LGPIO30 +#define PAD_PIN_LGPIO31 (PAD_PIN_LGPIO_BASE + 31) ///< LGPIO31 +#define PAD_PIN_LGPIO32 (PAD_PIN_LGPIO_BASE + 32) ///< LGPIO32 +//LGPIOx group end + +//DGPIO group begin +#define PAD_PIN_DGPIO_BASE 300 +#define PAD_PIN_DGPIO0 (PAD_PIN_DGPIO_BASE + 0) ///< DGPIO0 +#define PAD_PIN_DGPIO1 (PAD_PIN_DGPIO_BASE + 1) ///< DGPIO1 +#define PAD_PIN_DGPIO2 (PAD_PIN_DGPIO_BASE + 2) ///< DGPIO2 +#define PAD_PIN_DGPIO3 (PAD_PIN_DGPIO_BASE + 3) ///< DGPIO3 +#define PAD_PIN_DGPIO4 (PAD_PIN_DGPIO_BASE + 4) ///< DGPIO4 +#define PAD_PIN_DGPIO5 (PAD_PIN_DGPIO_BASE + 5) ///< DGPIO5 +#define PAD_PIN_DGPIO6 (PAD_PIN_DGPIO_BASE + 6) ///< DGPIO6 +#define PAD_PIN_DGPIO7 (PAD_PIN_DGPIO_BASE + 7) ///< DGPIO7 +#define PAD_PIN_DGPIO8 (PAD_PIN_DGPIO_BASE + 8) ///< DGPIO8 +#define PAD_PIN_DGPIO9 (PAD_PIN_DGPIO_BASE + 9) ///< DGPIO9 +#define PAD_PIN_DGPIO10 (PAD_PIN_DGPIO_BASE + 10) ///< DGPIO10 +#define PAD_PIN_DGPIO11 (PAD_PIN_DGPIO_BASE + 11) ///< DGPIO11 +#define PAD_PIN_DGPIO12 (PAD_PIN_DGPIO_BASE + 12) ///< DGPIO12 +//DGPIO group end + +//@} + + + +#define PAD_DS_GROUP4_10 0x0000 +#define PAD_DS_GROUP6_16 0x1000 +#define PAD_DS_GROUP8 0x2000 +#define PAD_DS_GROUP16 0x4000 +#define PAD_DS_GROUP5_40 0x8000 + +/** + @name Pad driving pin ID. + + Pad driving pin ID. + + Pad ID of pad_setDrivingSink() +*/ +//@{ +//CGPIO group begin +#define PAD_DS_CGPIO_BASE 0 +#define PAD_DS_CGPIO0 (PAD_DS_CGPIO_BASE + 0) ///< CGPIO0 +#define PAD_DS_CGPIO1 (PAD_DS_CGPIO_BASE + 1) ///< CGPIO1 +#define PAD_DS_CGPIO2 (PAD_DS_CGPIO_BASE + 2) ///< CGPIO2 +#define PAD_DS_CGPIO3 (PAD_DS_CGPIO_BASE + 3) ///< CGPIO3 +#define PAD_DS_CGPIO4 (PAD_DS_CGPIO_BASE + 4) ///< CGPIO4 +#define PAD_DS_CGPIO5 (PAD_DS_CGPIO_BASE + 5) ///< CGPIO5 +#define PAD_DS_CGPIO6 (PAD_DS_CGPIO_BASE + 6) ///< CGPIO6 +#define PAD_DS_CGPIO7 (PAD_DS_CGPIO_BASE + 7) ///< CGPIO7 +#define PAD_DS_CGPIO8 (PAD_DS_CGPIO_BASE + 8) ///< CGPIO8 +#define PAD_DS_CGPIO9 ((PAD_DS_CGPIO_BASE + 9) | PAD_DS_GROUP6_16) ///< CGPIO9 +#define PAD_DS_CGPIO10 (PAD_DS_CGPIO_BASE + 10) ///< CGPIO10 +#define PAD_DS_CGPIO11 (PAD_DS_CGPIO_BASE + 11) ///< CGPIO11 +#define PAD_DS_CGPIO12 (PAD_DS_CGPIO_BASE + 12) ///< CGPIO12 +#define PAD_DS_CGPIO13 (PAD_DS_CGPIO_BASE + 13) ///< CGPIO13 +#define PAD_DS_CGPIO14 (PAD_DS_CGPIO_BASE + 14) ///< CGPIO14 +#define PAD_DS_CGPIO15 (PAD_DS_CGPIO_BASE + 15) ///< CGPIO15 + +#define PAD_DS_CGPIO16 ((PAD_DS_CGPIO_BASE + 16) | PAD_DS_GROUP5_40) ///< CGPIO16 +#define PAD_DS_CGPIO17 ((PAD_DS_CGPIO_BASE + 17) | PAD_DS_GROUP5_40) ///< CGPIO17 +#define PAD_DS_CGPIO18 ((PAD_DS_CGPIO_BASE + 18) | PAD_DS_GROUP5_40) ///< CGPIO18 +#define PAD_DS_CGPIO19 ((PAD_DS_CGPIO_BASE + 19) | PAD_DS_GROUP5_40) ///< CGPIO19 +#define PAD_DS_CGPIO20 ((PAD_DS_CGPIO_BASE + 20) | PAD_DS_GROUP5_40) ///< CGPIO20 +#define PAD_DS_CGPIO21 ((PAD_DS_CGPIO_BASE + 21) | PAD_DS_GROUP5_40) ///< CGPIO21 +#define PAD_DS_CGPIO22 ((PAD_DS_CGPIO_BASE + 22) | PAD_DS_GROUP5_40) ///< CGPIO22 +#define PAD_DS_CGPIO23 ((PAD_DS_CGPIO_BASE + 23) | PAD_DS_GROUP5_40) ///< CGPIO23 +#define PAD_DS_CGPIO24 ((PAD_DS_CGPIO_BASE + 24) | PAD_DS_GROUP5_40) ///< CGPIO24 +#define PAD_DS_CGPIO25 ((PAD_DS_CGPIO_BASE + 25) | PAD_DS_GROUP5_40) ///< CGPIO25 +#define PAD_DS_CGPIO26 ((PAD_DS_CGPIO_BASE + 26) | PAD_DS_GROUP5_40) ///< CGPIO26 +#define PAD_DS_CGPIO27 ((PAD_DS_CGPIO_BASE + 27) | PAD_DS_GROUP5_40) ///< CGPIO27 +#define PAD_DS_CGPIO28 ((PAD_DS_CGPIO_BASE + 28) | PAD_DS_GROUP6_16) ///< CGPIO28 +#define PAD_DS_CGPIO29 (PAD_DS_CGPIO_BASE + 29) ///< CGPIO29 +#define PAD_DS_CGPIO30 (PAD_DS_CGPIO_BASE + 30) ///< CGPIO30 +#define PAD_DS_CGPIO31 (PAD_DS_CGPIO_BASE + 31) ///< CGPIO31 + +#define PAD_DS_CGPIO32 (PAD_DS_CGPIO_BASE + 32) ///< CGPIO32 +#define PAD_DS_CGPIO33 (PAD_DS_CGPIO_BASE + 33) ///< CGPIO33 +//CGPIO group end + +//SGPIO group Driving/Sink begin +#define PAD_DS_SGPIO_BASE 48 +#define PAD_DS_SGPIO0 ((PAD_DS_SGPIO_BASE + 0) | PAD_DS_GROUP6_16) ///< SGPIO0 +#define PAD_DS_SGPIO1 ((PAD_DS_SGPIO_BASE + 1) | PAD_DS_GROUP8) ///< SGPIO1 +#define PAD_DS_SGPIO2 ((PAD_DS_SGPIO_BASE + 2) | PAD_DS_GROUP8) ///< SGPIO2 +#define PAD_DS_SGPIO3 ((PAD_DS_SGPIO_BASE + 3) | PAD_DS_GROUP8) ///< SGPIO3 +#define PAD_DS_SGPIO4 ((PAD_DS_SGPIO_BASE + 4) | PAD_DS_GROUP8) ///< SGPIO4 +#define PAD_DS_SGPIO5 ((PAD_DS_SGPIO_BASE + 5) | PAD_DS_GROUP6_16) ///< SGPIO5 +#define PAD_DS_SGPIO6 ((PAD_DS_SGPIO_BASE + 6) | PAD_DS_GROUP8) ///< SGPIO6 +#define PAD_DS_SGPIO7 ((PAD_DS_SGPIO_BASE + 7) | PAD_DS_GROUP8) ///< SGPIO7 +#define PAD_DS_SGPIO8 (PAD_DS_SGPIO_BASE + 8) ///< SGPIO8 +#define PAD_DS_SGPIO9 (PAD_DS_SGPIO_BASE + 9) ///< SGPIO9 +#define PAD_DS_SGPIO10 (PAD_DS_SGPIO_BASE + 10) ///< SGPIO10 +#define PAD_DS_SGPIO11 (PAD_DS_SGPIO_BASE + 11) ///< SGPIO11 +//SGPIO group Driving/Sink end + +//PGPIO group Driving/Sink begin +#define PAD_DS_PGPIO_BASE 64 +#define PAD_DS_PGPIO0 (PAD_DS_PGPIO_BASE + 0) ///< PGPIO0 +#define PAD_DS_PGPIO1 (PAD_DS_PGPIO_BASE + 1) ///< PGPIO1 +#define PAD_DS_PGPIO2 (PAD_DS_PGPIO_BASE + 2) ///< PGPIO2 +#define PAD_DS_PGPIO3 (PAD_DS_PGPIO_BASE + 3) ///< PGPIO3 +#define PAD_DS_PGPIO4 (PAD_DS_PGPIO_BASE + 4) ///< PGPIO4 +#define PAD_DS_PGPIO5 (PAD_DS_PGPIO_BASE + 5) ///< PGPIO5 +#define PAD_DS_PGPIO6 (PAD_DS_PGPIO_BASE + 6) ///< PGPIO6 +#define PAD_DS_PGPIO7 (PAD_DS_PGPIO_BASE + 7) ///< PGPIO7 +#define PAD_DS_PGPIO8 (PAD_DS_PGPIO_BASE + 8) ///< PGPIO8 +#define PAD_DS_PGPIO9 (PAD_DS_PGPIO_BASE + 9) ///< PGPIO9 +#define PAD_DS_PGPIO10 (PAD_DS_PGPIO_BASE + 10) ///< PGPIO10 +#define PAD_DS_PGPIO11 (PAD_DS_PGPIO_BASE + 11) ///< PGPIO11 +#define PAD_DS_PGPIO12 (PAD_DS_PGPIO_BASE + 12) ///< PGPIO12 +#define PAD_DS_PGPIO13 (PAD_DS_PGPIO_BASE + 13) ///< PGPIO13 +#define PAD_DS_PGPIO14 (PAD_DS_PGPIO_BASE + 14) ///< PGPIO14 +#define PAD_DS_PGPIO15 (PAD_DS_PGPIO_BASE + 15) ///< PGPIO15 + +#define PAD_DS_PGPIO16 (PAD_DS_PGPIO_BASE + 16) ///< PGPIO16 +#define PAD_DS_PGPIO17 (PAD_DS_PGPIO_BASE + 17) ///< PGPIO17 +#define PAD_DS_PGPIO18 (PAD_DS_PGPIO_BASE + 18) ///< PGPIO18 +#define PAD_DS_PGPIO19 (PAD_DS_PGPIO_BASE + 19) ///< PGPIO19 +#define PAD_DS_PGPIO20 ((PAD_DS_PGPIO_BASE + 20) | PAD_DS_GROUP6_16) ///< PGPIO20 +#define PAD_DS_PGPIO21 ((PAD_DS_PGPIO_BASE + 21) | PAD_DS_GROUP6_16) ///< PGPIO21 +#define PAD_DS_PGPIO22 ((PAD_DS_PGPIO_BASE + 22) | PAD_DS_GROUP6_16) ///< PGPIO22 +#define PAD_DS_PGPIO23 ((PAD_DS_PGPIO_BASE + 23) | PAD_DS_GROUP6_16) ///< PGPIO23 +#define PAD_DS_PGPIO24 (PAD_DS_PGPIO_BASE + 24) ///< PGPIO24 +#define PAD_DS_PGPIO25 (PAD_DS_PGPIO_BASE + 25) ///< PGPIO25 +#define PAD_DS_PGPIO26 (PAD_DS_PGPIO_BASE + 26) ///< PGPIO26 +#define PAD_DS_PGPIO27 (PAD_DS_PGPIO_BASE + 27) ///< PGPIO27 +#define PAD_DS_PGPIO28 (PAD_DS_PGPIO_BASE + 28) ///< PGPIO28 +#define PAD_DS_PGPIO29 (PAD_DS_PGPIO_BASE + 29) ///< PGPIO29 +#define PAD_DS_PGPIO30 (PAD_DS_PGPIO_BASE + 30) ///< PGPIO30 +#define PAD_DS_PGPIO31 (PAD_DS_PGPIO_BASE + 31) ///< PGPIO31 + +#define PAD_DS_PGPIO32 (PAD_DS_PGPIO_BASE + 32) ///< PGPIO32 +#define PAD_DS_PGPIO33 (PAD_DS_PGPIO_BASE + 33) ///< PGPIO33 +#define PAD_DS_PGPIO34 (PAD_DS_PGPIO_BASE + 34) ///< PGPIO34 +#define PAD_DS_PGPIO35 (PAD_DS_PGPIO_BASE + 35) ///< PGPIO35 +#define PAD_DS_PGPIO36 (PAD_DS_PGPIO_BASE + 36) ///< PGPIO36 +#define PAD_DS_PGPIO37 (PAD_DS_PGPIO_BASE + 37) ///< PGPIO37 +#define PAD_DS_PGPIO38 (PAD_DS_PGPIO_BASE + 38) ///< PGPIO38 +#define PAD_DS_PGPIO39 (PAD_DS_PGPIO_BASE + 39) ///< PGPIO39 +#define PAD_DS_PGPIO40 (PAD_DS_PGPIO_BASE + 40) ///< PGPIO40 +#define PAD_DS_PGPIO41 (PAD_DS_PGPIO_BASE + 41) ///< PGPIO41 +#define PAD_DS_PGPIO42 ((PAD_DS_PGPIO_BASE + 42) | PAD_DS_GROUP8) ///< PGPIO42 +#define PAD_DS_PGPIO43 ((PAD_DS_PGPIO_BASE + 43) | PAD_DS_GROUP8) ///< PGPIO43 +#define PAD_DS_PGPIO44 ((PAD_DS_PGPIO_BASE + 44) | PAD_DS_GROUP8) ///< PGPIO44 +#define PAD_DS_PGPIO45 ((PAD_DS_PGPIO_BASE + 45) | PAD_DS_GROUP8) ///< PGPIO45 +#define PAD_DS_PGPIO46 ((PAD_DS_PGPIO_BASE + 46) | PAD_DS_GROUP8) ///< PGPIO46 +#define PAD_DS_PGPIO47 ((PAD_DS_PGPIO_BASE + 47) | PAD_DS_GROUP8) ///< PGPIO47 +//PGPIO group Driving/Sink end + +//LCD group Driving/Sink begin +#define PAD_DS_LGPIO_BASE 112 +#define PAD_DS_LGPIO0 ((PAD_DS_LGPIO_BASE + 0) | PAD_DS_GROUP6_16) ///< LGPIO0 +#define PAD_DS_LGPIO1 ((PAD_DS_LGPIO_BASE + 1) | PAD_DS_GROUP6_16) ///< LGPIO1 +#define PAD_DS_LGPIO2 ((PAD_DS_LGPIO_BASE + 2) | PAD_DS_GROUP6_16) ///< LGPIO2 +#define PAD_DS_LGPIO3 ((PAD_DS_LGPIO_BASE + 3) | PAD_DS_GROUP6_16) ///< LGPIO3 +#define PAD_DS_LGPIO4 ((PAD_DS_LGPIO_BASE + 4) | PAD_DS_GROUP6_16) ///< LGPIO4 +#define PAD_DS_LGPIO5 ((PAD_DS_LGPIO_BASE + 5) | PAD_DS_GROUP6_16) ///< LGPIO5 +#define PAD_DS_LGPIO6 ((PAD_DS_LGPIO_BASE + 6) | PAD_DS_GROUP6_16) ///< LGPIO6 +#define PAD_DS_LGPIO7 ((PAD_DS_LGPIO_BASE + 7) | PAD_DS_GROUP6_16) ///< LGPIO7 +#define PAD_DS_LGPIO8 ((PAD_DS_LGPIO_BASE + 8) | PAD_DS_GROUP6_16) ///< LGPIO8 +#define PAD_DS_LGPIO9 ((PAD_DS_LGPIO_BASE + 9) | PAD_DS_GROUP6_16) ///< LGPIO9 +#define PAD_DS_LGPIO10 ((PAD_DS_LGPIO_BASE + 10)| PAD_DS_GROUP6_16) ///< LGPIO10 +#define PAD_DS_LGPIO11 ((PAD_DS_LGPIO_BASE + 11)| PAD_DS_GROUP6_16) ///< LGPIO11 +#define PAD_DS_LGPIO12 ((PAD_DS_LGPIO_BASE + 12)| PAD_DS_GROUP6_16) ///< LGPIO12 +#define PAD_DS_LGPIO13 ((PAD_DS_LGPIO_BASE + 13)| PAD_DS_GROUP6_16) ///< LGPIO13 +#define PAD_DS_LGPIO14 ((PAD_DS_LGPIO_BASE + 14)| PAD_DS_GROUP6_16) ///< LGPIO14 +#define PAD_DS_LGPIO15 ((PAD_DS_LGPIO_BASE + 15)| PAD_DS_GROUP6_16) ///< LGPIO15 + +#define PAD_DS_LGPIO16 ((PAD_DS_LGPIO_BASE + 16)| PAD_DS_GROUP6_16) ///< LGPIO16 +#define PAD_DS_LGPIO17 ((PAD_DS_LGPIO_BASE + 17)| PAD_DS_GROUP6_16) ///< LGPIO17 +#define PAD_DS_LGPIO18 ((PAD_DS_LGPIO_BASE + 18)| PAD_DS_GROUP6_16) ///< LGPIO18 +#define PAD_DS_LGPIO19 ((PAD_DS_LGPIO_BASE + 19)| PAD_DS_GROUP6_16) ///< LGPIO19 +#define PAD_DS_LGPIO20 ((PAD_DS_LGPIO_BASE + 20)| PAD_DS_GROUP6_16) ///< LGPIO20 +#define PAD_DS_LGPIO21 ((PAD_DS_LGPIO_BASE + 21)| PAD_DS_GROUP6_16) ///< LGPIO21 +#define PAD_DS_LGPIO22 ((PAD_DS_LGPIO_BASE + 22)| PAD_DS_GROUP6_16) ///< LGPIO22 +#define PAD_DS_LGPIO23 ((PAD_DS_LGPIO_BASE + 23)| PAD_DS_GROUP6_16) ///< LGPIO23 +#define PAD_DS_LGPIO24 ((PAD_DS_LGPIO_BASE + 24)| PAD_DS_GROUP6_16) ///< LGPIO24 +#define PAD_DS_LGPIO25 ((PAD_DS_LGPIO_BASE + 25)| PAD_DS_GROUP6_16) ///< LGPIO25 +#define PAD_DS_LGPIO26 ((PAD_DS_LGPIO_BASE + 26)| PAD_DS_GROUP6_16) ///< LGPIO26 +#define PAD_DS_LGPIO27 ((PAD_DS_LGPIO_BASE + 27)| PAD_DS_GROUP6_16) ///< LGPIO27 +#define PAD_DS_LGPIO28 ((PAD_DS_LGPIO_BASE + 28)| PAD_DS_GROUP6_16) ///< LGPIO28 +#define PAD_DS_LGPIO29 ((PAD_DS_LGPIO_BASE + 29)| PAD_DS_GROUP6_16) ///< LGPIO29 +#define PAD_DS_LGPIO30 ((PAD_DS_LGPIO_BASE + 30)| PAD_DS_GROUP4_10) ///< LGPIO30 +#define PAD_DS_LGPIO31 ((PAD_DS_LGPIO_BASE + 31)| PAD_DS_GROUP4_10) ///< LGPIO31 +#define PAD_DS_LGPIO32 ((PAD_DS_LGPIO_BASE + 32)| PAD_DS_GROUP4_10) ///< LGPIO32 +//LCD group Driving/Sink end + +//DGPIO group Driving/Sink begin +#define PAD_DS_DGPIO_BASE 160 +#define PAD_DS_DGPIO0 ((PAD_DS_DGPIO_BASE + 0) | PAD_DS_GROUP16) ///< DGPIO0 +#define PAD_DS_DGPIO1 ((PAD_DS_DGPIO_BASE + 1) | PAD_DS_GROUP16) ///< DGPIO1 +#define PAD_DS_DGPIO2 ((PAD_DS_DGPIO_BASE + 2) | PAD_DS_GROUP16) ///< DGPIO2 +#define PAD_DS_DGPIO3 ((PAD_DS_DGPIO_BASE + 3) | PAD_DS_GROUP16) ///< DGPIO3 +#define PAD_DS_DGPIO4 ((PAD_DS_DGPIO_BASE + 4) | PAD_DS_GROUP16) ///< DGPIO4 +#define PAD_DS_DGPIO5 ((PAD_DS_DGPIO_BASE + 5) | PAD_DS_GROUP16) ///< DGPIO5 +#define PAD_DS_DGPIO6 ((PAD_DS_DGPIO_BASE + 6) | PAD_DS_GROUP8) ///< DGPIO6 +#define PAD_DS_DGPIO7 ((PAD_DS_DGPIO_BASE + 7) | PAD_DS_GROUP8) ///< DGPIO7 +#define PAD_DS_DGPIO8 ((PAD_DS_DGPIO_BASE + 8) | PAD_DS_GROUP8) ///< DGPIO8 +#define PAD_DS_DGPIO9 ((PAD_DS_DGPIO_BASE + 9) | PAD_DS_GROUP8) ///< DGPIO9 +#define PAD_DS_DGPIO10 ((PAD_DS_DGPIO_BASE + 10)| PAD_DS_GROUP8) ///< DGPIO10 +#define PAD_DS_DGPIO11 ((PAD_DS_DGPIO_BASE + 11)| PAD_DS_GROUP4_10) ///< DGPIO11 +#define PAD_DS_DGPIO12 ((PAD_DS_DGPIO_BASE + 12)| PAD_DS_GROUP4_10) ///< DGPIO12 +//DGPIO group Driving/Sink end +//@} + +#endif + +/** + @addtogroup mIDrvSys_PAD +*/ +//@{ + + +#define PAD_C_GPIO_BASE 0 +#define PAD_S_GPIO_BASE 96 +#define PAD_P_GPIO_BASE 128 +#define PAD_L_GPIO_BASE 224 +#define PAD_D_GPIO_BASE 288 +#define PAD_H_GPIO_BASE 320 +#define PAD_A_GPIO_BASE 352 +#define PAD_DS_GROUP_10 0x00000000 +#define PAD_DS_GROUP_16 0x10000000 +#define PAD_DS_GROUP_40 0x80000000 + +/** + @name Pad type pin ID. + + Pad type pin ID. + + Pad ID of pad_set_pull_up_down (), pad_get_pull_up_down (). +*/ +#define PAD_PIN_NOT_EXIST (64) // For backward compatible +//@{ +typedef enum { + + //C_GPIO group + PAD_PIN_CGPIO0 = (PAD_C_GPIO_BASE + 0), ///< C_GPIO_0 + PAD_PIN_CGPIO1 = (PAD_C_GPIO_BASE + 2), ///< C_GPIO_1 + PAD_PIN_CGPIO2 = (PAD_C_GPIO_BASE + 4), ///< C_GPIO_2 + PAD_PIN_CGPIO3 = (PAD_C_GPIO_BASE + 6), ///< C_GPIO_3 + PAD_PIN_CGPIO4 = (PAD_C_GPIO_BASE + 8), ///< C_GPIO_4 + PAD_PIN_CGPIO5 = (PAD_C_GPIO_BASE + 10), ///< C_GPIO_5 + PAD_PIN_CGPIO6 = (PAD_C_GPIO_BASE + 12), ///< C_GPIO_6 + PAD_PIN_CGPIO7 = (PAD_C_GPIO_BASE + 14), ///< C_GPIO_7 + PAD_PIN_CGPIO8 = (PAD_C_GPIO_BASE + 16), ///< C_GPIO_8 + PAD_PIN_CGPIO9 = (PAD_C_GPIO_BASE + 18), ///< C_GPIO_9 + PAD_PIN_CGPIO10 = (PAD_C_GPIO_BASE + 20), ///< C_GPIO_10 + PAD_PIN_CGPIO11 = (PAD_C_GPIO_BASE + 22), ///< C_GPIO_11 + PAD_PIN_CGPIO12 = (PAD_C_GPIO_BASE + 24), ///< C_GPIO_12 + PAD_PIN_CGPIO13 = (PAD_C_GPIO_BASE + 26), ///< C_GPIO_13 + PAD_PIN_CGPIO14 = (PAD_C_GPIO_BASE + 28), ///< C_GPIO_14 + PAD_PIN_CGPIO15 = (PAD_C_GPIO_BASE + 30), ///< C_GPIO_15 + PAD_PIN_CGPIO16 = (PAD_C_GPIO_BASE + 32), ///< C_GPIO_16 + PAD_PIN_CGPIO17 = (PAD_C_GPIO_BASE + 34), ///< C_GPIO_17 + PAD_PIN_CGPIO18 = (PAD_C_GPIO_BASE + 36), ///< C_GPIO_18 + PAD_PIN_CGPIO19 = (PAD_C_GPIO_BASE + 38), ///< C_GPIO_19 + PAD_PIN_CGPIO20 = (PAD_C_GPIO_BASE + 40), ///< C_GPIO_20 + PAD_PIN_CGPIO21 = (PAD_C_GPIO_BASE + 42), ///< C_GPIO_21 + PAD_PIN_CGPIO22 = (PAD_C_GPIO_BASE + 44), ///< C_GPIO_22 + + //S_GPIO group + PAD_PIN_SGPIO0 = (PAD_S_GPIO_BASE + 0), ///< S_GPIO_0 + PAD_PIN_SGPIO1 = (PAD_S_GPIO_BASE + 2), ///< S_GPIO_1 + PAD_PIN_SGPIO2 = (PAD_S_GPIO_BASE + 4), ///< S_GPIO_2 + PAD_PIN_SGPIO3 = (PAD_S_GPIO_BASE + 6), ///< S_GPIO_3 + PAD_PIN_SGPIO4 = (PAD_S_GPIO_BASE + 8), ///< S_GPIO_4 + PAD_PIN_SGPIO5 = (PAD_S_GPIO_BASE + 10), ///< S_GPIO_5 + PAD_PIN_SGPIO6 = (PAD_S_GPIO_BASE + 12), ///< S_GPIO_6 + PAD_PIN_SGPIO7 = (PAD_S_GPIO_BASE + 14), ///< S_GPIO_7 + PAD_PIN_SGPIO8 = (PAD_S_GPIO_BASE + 16), ///< S_GPIO_8 + PAD_PIN_SGPIO9 = (PAD_S_GPIO_BASE + 18), ///< S_GPIO_9 + PAD_PIN_SGPIO10 = (PAD_S_GPIO_BASE + 20), ///< S_GPIO_10 + PAD_PIN_SGPIO11 = (PAD_S_GPIO_BASE + 22), ///< S_GPIO_11 + PAD_PIN_SGPIO12 = (PAD_S_GPIO_BASE + 24), ///< S_GPIO_12 + + //P_GPIO group + PAD_PIN_PGPIO0 = (PAD_P_GPIO_BASE + 0), ///< P_GPIO_0 + PAD_PIN_PGPIO1 = (PAD_P_GPIO_BASE + 2), ///< P_GPIO_1 + PAD_PIN_PGPIO2 = (PAD_P_GPIO_BASE + 4), ///< P_GPIO_2 + PAD_PIN_PGPIO3 = (PAD_P_GPIO_BASE + 6), ///< P_GPIO_3 + PAD_PIN_PGPIO4 = (PAD_P_GPIO_BASE + 8), ///< P_GPIO_4 + PAD_PIN_PGPIO5 = (PAD_P_GPIO_BASE + 10), ///< P_GPIO_5 + PAD_PIN_PGPIO6 = (PAD_P_GPIO_BASE + 12), ///< P_GPIO_6 + PAD_PIN_PGPIO7 = (PAD_P_GPIO_BASE + 14), ///< P_GPIO_7 + PAD_PIN_PGPIO8 = (PAD_P_GPIO_BASE + 16), ///< P_GPIO_8 + PAD_PIN_PGPIO9 = (PAD_P_GPIO_BASE + 18), ///< P_GPIO_9 + PAD_PIN_PGPIO10 = (PAD_P_GPIO_BASE + 20), ///< P_GPIO_10 + PAD_PIN_PGPIO11 = (PAD_P_GPIO_BASE + 22), ///< P_GPIO_11 + PAD_PIN_PGPIO12 = (PAD_P_GPIO_BASE + 24), ///< P_GPIO_12 + PAD_PIN_PGPIO13 = (PAD_P_GPIO_BASE + 26), ///< P_GPIO_13 + PAD_PIN_PGPIO14 = (PAD_P_GPIO_BASE + 28), ///< P_GPIO_14 + PAD_PIN_PGPIO15 = (PAD_P_GPIO_BASE + 30), ///< P_GPIO_15 + PAD_PIN_PGPIO16 = (PAD_P_GPIO_BASE + 32), ///< P_GPIO_16 + PAD_PIN_PGPIO17 = (PAD_P_GPIO_BASE + 34), ///< P_GPIO_17 + PAD_PIN_PGPIO18 = (PAD_P_GPIO_BASE + 36), ///< P_GPIO_18 + PAD_PIN_PGPIO19 = (PAD_P_GPIO_BASE + 38), ///< P_GPIO_19 + PAD_PIN_PGPIO20 = (PAD_P_GPIO_BASE + 40), ///< P_GPIO_20 + PAD_PIN_PGPIO21 = (PAD_P_GPIO_BASE + 42), ///< P_GPIO_21 + PAD_PIN_PGPIO22 = (PAD_P_GPIO_BASE + 44), ///< P_GPIO_22 + PAD_PIN_PGPIO23 = (PAD_P_GPIO_BASE + 46), ///< P_GPIO_23 + PAD_PIN_PGPIO24 = (PAD_P_GPIO_BASE + 48), ///< P_GPIO_24 + + //L_GPIO group + PAD_PIN_LGPIO0 = (PAD_L_GPIO_BASE + 0), ///< L_GPIO_0 + PAD_PIN_LGPIO1 = (PAD_L_GPIO_BASE + 2), ///< L_GPIO_1 + PAD_PIN_LGPIO2 = (PAD_L_GPIO_BASE + 4), ///< L_GPIO_2 + PAD_PIN_LGPIO3 = (PAD_L_GPIO_BASE + 6), ///< L_GPIO_3 + PAD_PIN_LGPIO4 = (PAD_L_GPIO_BASE + 8), ///< L_GPIO_4 + PAD_PIN_LGPIO5 = (PAD_L_GPIO_BASE + 10), ///< L_GPIO_5 + PAD_PIN_LGPIO6 = (PAD_L_GPIO_BASE + 12), ///< L_GPIO_6 + PAD_PIN_LGPIO7 = (PAD_L_GPIO_BASE + 14), ///< L_GPIO_7 + PAD_PIN_LGPIO8 = (PAD_L_GPIO_BASE + 16), ///< L_GPIO_8 + PAD_PIN_LGPIO9 = (PAD_L_GPIO_BASE + 18), ///< L_GPIO_9 + PAD_PIN_LGPIO10 = (PAD_L_GPIO_BASE + 20), ///< L_GPIO_10 + PAD_PIN_LGPIO11 = (PAD_L_GPIO_BASE + 22), ///< L_GPIO_11 + PAD_PIN_LGPIO12 = (PAD_L_GPIO_BASE + 24), ///< L_GPIO_12 + PAD_PIN_LGPIO13 = (PAD_L_GPIO_BASE + 26), ///< L_GPIO_13 + PAD_PIN_LGPIO14 = (PAD_L_GPIO_BASE + 28), ///< L_GPIO_14 + PAD_PIN_LGPIO15 = (PAD_L_GPIO_BASE + 30), ///< L_GPIO_15 + PAD_PIN_LGPIO16 = (PAD_L_GPIO_BASE + 32), ///< L_GPIO_16 + PAD_PIN_LGPIO17 = (PAD_L_GPIO_BASE + 34), ///< L_GPIO_17 + PAD_PIN_LGPIO18 = (PAD_L_GPIO_BASE + 36), ///< L_GPIO_18 + PAD_PIN_LGPIO19 = (PAD_L_GPIO_BASE + 38), ///< L_GPIO_19 + PAD_PIN_LGPIO20 = (PAD_L_GPIO_BASE + 40), ///< L_GPIO_20 + PAD_PIN_LGPIO21 = (PAD_L_GPIO_BASE + 42), ///< L_GPIO_21 + PAD_PIN_LGPIO22 = (PAD_L_GPIO_BASE + 44), ///< L_GPIO_22 + PAD_PIN_LGPIO23 = (PAD_L_GPIO_BASE + 46), ///< L_GPIO_23 + PAD_PIN_LGPIO24 = (PAD_L_GPIO_BASE + 48), ///< L_GPIO_23 + + //D_GPIO group + PAD_PIN_DGPIO0 = (PAD_D_GPIO_BASE + 0), ///< D_GPIO_0 + PAD_PIN_DGPIO1 = (PAD_D_GPIO_BASE + 2), ///< D_GPIO_1 + PAD_PIN_DGPIO2 = (PAD_D_GPIO_BASE + 4), ///< D_GPIO_2 + PAD_PIN_DGPIO3 = (PAD_D_GPIO_BASE + 6), ///< D_GPIO_3 + PAD_PIN_DGPIO4 = (PAD_D_GPIO_BASE + 8), ///< D_GPIO_4 + PAD_PIN_DGPIO5 = (PAD_D_GPIO_BASE + 10), ///< D_GPIO_5 + PAD_PIN_DGPIO6 = (PAD_D_GPIO_BASE + 12), ///< D_GPIO_6 + PAD_PIN_DGPIO7 = (PAD_D_GPIO_BASE + 14), ///< D_GPIO_7 + + //HSI_GPIO group + PAD_PIN_HSIGPIO0 = (PAD_H_GPIO_BASE + 0), ///< HSI_GPIO_0 + PAD_PIN_HSIGPIO1 = (PAD_H_GPIO_BASE + 2), ///< HSI_GPIO_1 + PAD_PIN_HSIGPIO2 = (PAD_H_GPIO_BASE + 4), ///< HSI_GPIO_2 + PAD_PIN_HSIGPIO3 = (PAD_H_GPIO_BASE + 6), ///< HSI_GPIO_3 + PAD_PIN_HSIGPIO4 = (PAD_H_GPIO_BASE + 8), ///< HSI_GPIO_4 + PAD_PIN_HSIGPIO5 = (PAD_H_GPIO_BASE + 10), ///< HSI_GPIO_5 + PAD_PIN_HSIGPIO6 = (PAD_H_GPIO_BASE + 12), ///< HSI_GPIO_6 + PAD_PIN_HSIGPIO7 = (PAD_H_GPIO_BASE + 14), ///< HSI_GPIO_7 + PAD_PIN_HSIGPIO8 = (PAD_H_GPIO_BASE + 16), ///< HSI_GPIO_8 + PAD_PIN_HSIGPIO9 = (PAD_H_GPIO_BASE + 18), ///< HSI_GPIO_9 + PAD_PIN_HSIGPIO10 = (PAD_H_GPIO_BASE + 20), ///< HSI_GPIO_10 + PAD_PIN_HSIGPIO11 = (PAD_H_GPIO_BASE + 22), ///< HSI_GPIO_11 + + //A_GPIO group + PAD_PIN_AGPIO0 = (PAD_A_GPIO_BASE + 0), ///< A_GPIO_0 + PAD_PIN_AGPIO1 = (PAD_A_GPIO_BASE + 2), ///< A_GPIO_1 + PAD_PIN_AGPIO2 = (PAD_A_GPIO_BASE + 4), ///< A_GPIO_2 + + PAD_PIN_MAX = PAD_PIN_AGPIO2, + ENUM_DUMMY4WORD(PAD_PIN) +} PAD_PIN; +//@} + +/** + Pad type select + + Pad type select + + Pad type value for pad_set_pull_up_down(), pad_get_pull_up_down(). +*/ +typedef enum { + PAD_NONE = 0x00, ///< none of pull up/down + PAD_PULLDOWN = 0x01, ///< pull down + PAD_PULLUP = 0x02, ///< pull up + PAD_KEEPER = 0x03, ///< keeper + + ENUM_DUMMY4WORD(PAD_PULL) +} PAD_PULL; + +/** + Pad driving select + + Pad driving select + + Pad driving value for pad_set_driving_sink(), pad_get_driving_sink(). +*/ +typedef enum { + PAD_DRIVINGSINK_4MA = 0x0001, ///< Pad driver/sink 4mA + PAD_DRIVINGSINK_10MA = 0x0202, ///< Pad driver/sink 10mA + + PAD_DRIVINGSINK_6MA = 0x0010, ///< Pad driver/sink 6mA + PAD_DRIVINGSINK_16MA = 0x0020, ///< Pad driver/sink 16mA + + PAD_DRIVINGSINK_5MA = 0x0100, ///< Pad driver/sink 5mA + PAD_DRIVINGSINK_15MA = 0x0400, ///< Pad driver/sink 15mA + PAD_DRIVINGSINK_20MA = 0x0800, ///< Pad driver/sink 20mA + PAD_DRIVINGSINK_25MA = 0x1000, ///< Pad driver/sink 25mA + PAD_DRIVINGSINK_30MA = 0x2000, ///< Pad driver/sink 30mA + PAD_DRIVINGSINK_35MA = 0x4000, ///< Pad driver/sink 35mA + PAD_DRIVINGSINK_40MA = 0x8000, ///< Pad driver/sink 40mA + + ENUM_DUMMY4WORD(PAD_DRIVINGSINK) +} PAD_DRIVINGSINK; + +/** + @name Pad driving pin ID. + + Pad driving pin ID. + + Pad ID of pad_set_driving_sink(), pad_get_driving_sink() +*/ +//@{ +typedef enum { + + //C_GPIO group + PAD_DS_CGPIO0 = ((PAD_C_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< C_GPIO_0 + PAD_DS_CGPIO1 = ((PAD_C_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< C_GPIO_1 + PAD_DS_CGPIO2 = ((PAD_C_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< C_GPIO_2 + PAD_DS_CGPIO3 = ((PAD_C_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< C_GPIO_3 + PAD_DS_CGPIO4 = ((PAD_C_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< C_GPIO_4 + PAD_DS_CGPIO5 = ((PAD_C_GPIO_BASE + 10) | PAD_DS_GROUP_10), ///< C_GPIO_5 + PAD_DS_CGPIO6 = ((PAD_C_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< C_GPIO_6 + PAD_DS_CGPIO7 = ((PAD_C_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< C_GPIO_7 + PAD_DS_CGPIO8 = ((PAD_C_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< C_GPIO_8 + PAD_DS_CGPIO9 = ((PAD_C_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< C_GPIO_9 + PAD_DS_CGPIO10 = ((PAD_C_GPIO_BASE + 20) | PAD_DS_GROUP_10), ///< C_GPIO_10 + PAD_DS_CGPIO11 = ((PAD_C_GPIO_BASE + 0) | PAD_DS_GROUP_40), ///< C_GPIO_11 + PAD_DS_CGPIO12 = ((PAD_C_GPIO_BASE + 4) | PAD_DS_GROUP_40), ///< C_GPIO_12 + PAD_DS_CGPIO13 = ((PAD_C_GPIO_BASE + 8) | PAD_DS_GROUP_40), ///< C_GPIO_13 + PAD_DS_CGPIO14 = ((PAD_C_GPIO_BASE + 12) | PAD_DS_GROUP_40), ///< C_GPIO_14 + PAD_DS_CGPIO15 = ((PAD_C_GPIO_BASE + 16) | PAD_DS_GROUP_40), ///< C_GPIO_15 + PAD_DS_CGPIO16 = ((PAD_C_GPIO_BASE + 20) | PAD_DS_GROUP_40), ///< C_GPIO_16 + PAD_DS_CGPIO17 = ((PAD_C_GPIO_BASE + 24) | PAD_DS_GROUP_40), ///< C_GPIO_17 + PAD_DS_CGPIO18 = ((PAD_C_GPIO_BASE + 36) | PAD_DS_GROUP_16), ///< C_GPIO_18 + PAD_DS_CGPIO19 = ((PAD_C_GPIO_BASE + 38) | PAD_DS_GROUP_16), ///< C_GPIO_19 + PAD_DS_CGPIO20 = ((PAD_C_GPIO_BASE + 40) | PAD_DS_GROUP_16), ///< C_GPIO_20 + PAD_DS_CGPIO21 = ((PAD_C_GPIO_BASE + 42) | PAD_DS_GROUP_16), ///< C_GPIO_21 + PAD_DS_CGPIO22 = ((PAD_C_GPIO_BASE + 44) | PAD_DS_GROUP_16), ///< C_GPIO_22 + + //S_GPIO group + PAD_DS_SGPIO0 = ((PAD_S_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< S_GPIO_0 + PAD_DS_SGPIO1 = ((PAD_S_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< S_GPIO_1 + PAD_DS_SGPIO2 = ((PAD_S_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< S_GPIO_2 + PAD_DS_SGPIO3 = ((PAD_S_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< S_GPIO_3 + PAD_DS_SGPIO4 = ((PAD_S_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< S_GPIO_4 + PAD_DS_SGPIO5 = ((PAD_S_GPIO_BASE + 10) | PAD_DS_GROUP_16), ///< S_GPIO_5 + PAD_DS_SGPIO6 = ((PAD_S_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< S_GPIO_6 + PAD_DS_SGPIO7 = ((PAD_S_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< S_GPIO_7 + PAD_DS_SGPIO8 = ((PAD_S_GPIO_BASE + 16) | PAD_DS_GROUP_10), ///< S_GPIO_8 + PAD_DS_SGPIO9 = ((PAD_S_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< S_GPIO_9 + PAD_DS_SGPIO10 = ((PAD_S_GPIO_BASE + 20) | PAD_DS_GROUP_10), ///< S_GPIO_10 + PAD_DS_SGPIO11 = ((PAD_S_GPIO_BASE + 22) | PAD_DS_GROUP_10), ///< S_GPIO_11 + PAD_DS_SGPIO12 = ((PAD_S_GPIO_BASE + 24) | PAD_DS_GROUP_10), ///< S_GPIO_12 + + //P_GPIO group + PAD_DS_PGPIO0 = ((PAD_P_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< P_GPIO_0 + PAD_DS_PGPIO1 = ((PAD_P_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< P_GPIO_1 + PAD_DS_PGPIO2 = ((PAD_P_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< P_GPIO_2 + PAD_DS_PGPIO3 = ((PAD_P_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< P_GPIO_3 + PAD_DS_PGPIO4 = ((PAD_P_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< P_GPIO_4 + PAD_DS_PGPIO5 = ((PAD_P_GPIO_BASE + 10) | PAD_DS_GROUP_10), ///< P_GPIO_5 + PAD_DS_PGPIO6 = ((PAD_P_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< P_GPIO_6 + PAD_DS_PGPIO7 = ((PAD_P_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< P_GPIO_7 + PAD_DS_PGPIO8 = ((PAD_P_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< P_GPIO_8 + PAD_DS_PGPIO9 = ((PAD_P_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< P_GPIO_9 + PAD_DS_PGPIO10 = ((PAD_P_GPIO_BASE + 20) | PAD_DS_GROUP_10), ///< P_GPIO_10 + PAD_DS_PGPIO11 = ((PAD_P_GPIO_BASE + 22) | PAD_DS_GROUP_10), ///< P_GPIO_11 + PAD_DS_PGPIO12 = ((PAD_P_GPIO_BASE + 24) | PAD_DS_GROUP_10), ///< P_GPIO_12 + PAD_DS_PGPIO13 = ((PAD_P_GPIO_BASE + 26) | PAD_DS_GROUP_10), ///< P_GPIO_13 + PAD_DS_PGPIO14 = ((PAD_P_GPIO_BASE + 28) | PAD_DS_GROUP_10), ///< P_GPIO_14 + PAD_DS_PGPIO15 = ((PAD_P_GPIO_BASE + 30) | PAD_DS_GROUP_10), ///< P_GPIO_15 + PAD_DS_PGPIO16 = ((PAD_P_GPIO_BASE + 32) | PAD_DS_GROUP_10), ///< P_GPIO_16 + PAD_DS_PGPIO17 = ((PAD_P_GPIO_BASE + 34) | PAD_DS_GROUP_10), ///< P_GPIO_17 + PAD_DS_PGPIO18 = ((PAD_P_GPIO_BASE + 36) | PAD_DS_GROUP_10), ///< P_GPIO_18 + PAD_DS_PGPIO19 = ((PAD_P_GPIO_BASE + 38) | PAD_DS_GROUP_10), ///< P_GPIO_19 + PAD_DS_PGPIO20 = ((PAD_P_GPIO_BASE + 40) | PAD_DS_GROUP_10), ///< P_GPIO_20 + PAD_DS_PGPIO21 = ((PAD_P_GPIO_BASE + 42) | PAD_DS_GROUP_10), ///< P_GPIO_21 + PAD_DS_PGPIO22 = ((PAD_P_GPIO_BASE + 44) | PAD_DS_GROUP_10), ///< P_GPIO_22 + PAD_DS_PGPIO23 = ((PAD_P_GPIO_BASE + 46) | PAD_DS_GROUP_10), ///< P_GPIO_23 + PAD_DS_PGPIO24 = ((PAD_P_GPIO_BASE + 48) | PAD_DS_GROUP_10), ///< P_GPIO_24 + + //L_GPIO group + PAD_DS_LGPIO0 = ((PAD_L_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< L_GPIO_0 + PAD_DS_LGPIO1 = ((PAD_L_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< L_GPIO_1 + PAD_DS_LGPIO2 = ((PAD_L_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< L_GPIO_2 + PAD_DS_LGPIO3 = ((PAD_L_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< L_GPIO_3 + PAD_DS_LGPIO4 = ((PAD_L_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< L_GPIO_4 + PAD_DS_LGPIO5 = ((PAD_L_GPIO_BASE + 10) | PAD_DS_GROUP_10), ///< L_GPIO_5 + PAD_DS_LGPIO6 = ((PAD_L_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< L_GPIO_6 + PAD_DS_LGPIO7 = ((PAD_L_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< L_GPIO_7 + PAD_DS_LGPIO8 = ((PAD_L_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< L_GPIO_8 + PAD_DS_LGPIO9 = ((PAD_L_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< L_GPIO_9 + PAD_DS_LGPIO10 = ((PAD_L_GPIO_BASE + 20) | PAD_DS_GROUP_10), ///< L_GPIO_10 + PAD_DS_LGPIO11 = ((PAD_L_GPIO_BASE + 22) | PAD_DS_GROUP_10), ///< L_GPIO_11 + PAD_DS_LGPIO12 = ((PAD_L_GPIO_BASE + 24) | PAD_DS_GROUP_10), ///< L_GPIO_12 + PAD_DS_LGPIO13 = ((PAD_L_GPIO_BASE + 26) | PAD_DS_GROUP_10), ///< L_GPIO_13 + PAD_DS_LGPIO14 = ((PAD_L_GPIO_BASE + 28) | PAD_DS_GROUP_10), ///< L_GPIO_14 + PAD_DS_LGPIO15 = ((PAD_L_GPIO_BASE + 30) | PAD_DS_GROUP_10), ///< L_GPIO_15 + PAD_DS_LGPIO16 = ((PAD_L_GPIO_BASE + 32) | PAD_DS_GROUP_10), ///< L_GPIO_16 + PAD_DS_LGPIO17 = ((PAD_L_GPIO_BASE + 34) | PAD_DS_GROUP_10), ///< L_GPIO_17 + PAD_DS_LGPIO18 = ((PAD_L_GPIO_BASE + 36) | PAD_DS_GROUP_10), ///< L_GPIO_18 + PAD_DS_LGPIO19 = ((PAD_L_GPIO_BASE + 38) | PAD_DS_GROUP_10), ///< L_GPIO_19 + PAD_DS_LGPIO20 = ((PAD_L_GPIO_BASE + 40) | PAD_DS_GROUP_10), ///< L_GPIO_20 + PAD_DS_LGPIO21 = ((PAD_L_GPIO_BASE + 42) | PAD_DS_GROUP_10), ///< L_GPIO_21 + PAD_DS_LGPIO22 = ((PAD_L_GPIO_BASE + 44) | PAD_DS_GROUP_10), ///< L_GPIO_22 + PAD_DS_LGPIO23 = ((PAD_L_GPIO_BASE + 46) | PAD_DS_GROUP_10), ///< L_GPIO_23 + PAD_DS_LGPIO24 = ((PAD_L_GPIO_BASE + 48) | PAD_DS_GROUP_10), ///< L_GPIO_23 + + //D_GPIO group + PAD_DS_DGPIO0 = ((PAD_D_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< D_GPIO_0 + PAD_DS_DGPIO1 = ((PAD_D_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< D_GPIO_1 + PAD_DS_DGPIO2 = ((PAD_D_GPIO_BASE + 4) | PAD_DS_GROUP_16), ///< D_GPIO_2 + PAD_DS_DGPIO3 = ((PAD_D_GPIO_BASE + 6) | PAD_DS_GROUP_16), ///< D_GPIO_3 + PAD_DS_DGPIO4 = ((PAD_D_GPIO_BASE + 8) | PAD_DS_GROUP_16), ///< D_GPIO_4 + PAD_DS_DGPIO5 = ((PAD_D_GPIO_BASE + 10) | PAD_DS_GROUP_16), ///< D_GPIO_5 + PAD_DS_DGPIO6 = ((PAD_D_GPIO_BASE + 12) | PAD_DS_GROUP_16), ///< D_GPIO_6 + PAD_DS_DGPIO7 = ((PAD_D_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< D_GPIO_7 + + //HSI_GPIO group + PAD_DS_HSIGPIO0 = ((PAD_H_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< HSI_GPIO_0 + PAD_DS_HSIGPIO1 = ((PAD_H_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< HSI_GPIO_1 + PAD_DS_HSIGPIO2 = ((PAD_H_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< HSI_GPIO_2 + PAD_DS_HSIGPIO3 = ((PAD_H_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< HSI_GPIO_3 + PAD_DS_HSIGPIO4 = ((PAD_H_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< HSI_GPIO_4 + PAD_DS_HSIGPIO5 = ((PAD_H_GPIO_BASE + 10) | PAD_DS_GROUP_10), ///< HSI_GPIO_5 + PAD_DS_HSIGPIO6 = ((PAD_H_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< HSI_GPIO_6 + PAD_DS_HSIGPIO7 = ((PAD_H_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< HSI_GPIO_7 + PAD_DS_HSIGPIO8 = ((PAD_H_GPIO_BASE + 16) | PAD_DS_GROUP_10), ///< HSI_GPIO_8 + PAD_DS_HSIGPIO9 = ((PAD_H_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< HSI_GPIO_9 + PAD_DS_HSIGPIO10 = ((PAD_H_GPIO_BASE + 20) | PAD_DS_GROUP_10), ///< HSI_GPIO_10 + PAD_DS_HSIGPIO11 = ((PAD_H_GPIO_BASE + 22) | PAD_DS_GROUP_10), ///< HSI_GPIO_11 + + //A_GPIO group + PAD_DS_AGPIO0 = ((PAD_A_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< A_GPIO_0 + PAD_DS_AGPIO1 = ((PAD_A_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< A_GPIO_1 + PAD_DS_AGPIO2 = ((PAD_A_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< A_GPIO_2 + + PAD_DS_MAX = PAD_DS_AGPIO2, + ENUM_DUMMY4WORD(PAD_DS) +} PAD_DS; +//@} + +/** + Pad power ID select + + Pad power ID for PAD_POWER_STRUCT. +*/ +typedef enum { + PAD_POWERID_MC0 = 0x00, ///< Pad power id for MC0 + PAD_POWERID_MC1 = 0x01, ///< Pad power id for MC1 + PAD_POWERID_ADC = 0x02, ///< Pad power id for Audio ADC + PAD_POWERID_CSI = 0x04, ///< Pad power id for CSI/LVDS + + ENUM_DUMMY4WORD(PAD_POWERID) +} PAD_POWERID; + +/** + Pad power select + + Pad power value for PAD_POWER_STRUCT. +*/ +typedef enum { + PAD_3P3V = 0x00, ///< Pad power is 3.3V + PAD_AVDD = 0x00, ///< Pad power is AVDD ( for PAD_POWERID_ADC use) + PAD_1P8V = 0x01, ///< Pad power is 1.8V + PAD_PAD_VAD = 0x01, ///< Pad power is PAD_ADC_VAD ( for PAD_POWERID_ADC use) + + ENUM_DUMMY4WORD(PAD_POWER) +} PAD_POWER; + +/** + Pad power VAD for PAD_POWERID_ADC + + Pad power VAD value for PAD_POWER_STRUCT. +*/ +typedef enum { + PAD_VAD_2P9V = 0x00, ///< Pad power VAD = 2.9V + PAD_VAD_3P0V = 0x01, ///< Pad power VAD = 3.0V + PAD_VAD_3P1V = 0x03, ///< Pad power VAD = 3.1V + + PAD_VAD_2P4V = 0x100, ///< Pad power VAD = 2.4V + PAD_VAD_2P5V = 0x101, ///< Pad power VAD = 2.5V + PAD_VAD_2P6V = 0x103, ///< Pad power VAD = 2.6V + + ENUM_DUMMY4WORD(PAD_VAD) +} PAD_VAD; + + +/** + PAD power structure + + PAD power setting for pad_set_power() +*/ +typedef struct { + PAD_POWERID power_id; ///< Pad power id + PAD_POWER power; ///< Pad power + BOOL bias_current; ///< Regulator bias current selection + ///< - @b FALSE: disable + ///< - @b TRUE: enable + BOOL opa_gain; ///< Regulator OPA gain/phase selection + ///< - @b FALSE: disable + ///< - @b TRUE: enable + BOOL pull_down; ///< Regulator output pull down control + ///< - @b FALSE: none + ///< - @b TRUE: pull down enable + BOOL regulator_en; ///< Regulator enable + ///< - @b FALSE: disable + ///< - @b TRUE: enable + PAD_VAD vad; ///< Pad VAD of PAD_POWERID_ADC when PAD_PAD_VAD = 1 +} PAD_POWER_STRUCT; + + + + + + + + +// Backward compatible usages +#define PAD_PIN_CGPIO23 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO23 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO24 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO25 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO26 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO27 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO28 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO29 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO30 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO31 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO32 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO33 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_PGPIO39 PAD_PIN_NOT_EXIST // For backward compatible + + +/* + Exporting APIs +*/ + +extern ER pad_setPullUpDown(UINT32 pin, PAD_PULL pulltype); +extern ER pad_setDrivingSink(UINT32 name, PAD_DRIVINGSINK driving); +//@} + + + +//@} + +#endif diff --git a/board/novatek/na51055/loader/Include/Driver/regdef.h b/board/novatek/na51055/loader/Include/Driver/regdef.h new file mode 100755 index 000000000000..93a938095645 --- /dev/null +++ b/board/novatek/na51055/loader/Include/Driver/regdef.h @@ -0,0 +1,199 @@ +/* + * MIPS register definitions, originally from: + * + * include/asm-mips/regdefs.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License, Version 2. See the file "COPYING" in the main directory of this + * archive for more details. + * + * Copyright (C) 1994, 1995 by Ralf Baechle + */ + +/* + * Symbolic register names for 32 bit ABI + */ +# define Mode_USR 0x10 /* M[4:0] = 01010 */ +# define Mode_FIQ 0x11 /* M[4:0] = 10001 */ +# define Mode_IRQ 0x12 /* M[4:0] = 10010 */ +# define Mode_SVC 0x13 /* M[4:0] = 10011 */ +# define Mode_ABT 0x17 /* M[4:0] = 10111 */ +# define Mode_UNDEF 0x1B /* M[4:0] = 11011 */ +# define Mode_SYS 0x1F /* M[4:0] = 11111 */ +# define Mode_MSK 0x1F /* M[4:0] = 11111 */ +# define I_Bit 0x80 /* 7 6 5 4 3 2 1 0 */ +# define F_Bit 0x40 /* I F T M4 M3 M2 M1 M0 */ + +/* + ************************************************************************ + * Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |W|W|R|W|NumSets |Associativity |L | + * |T|B|A|A| | |S | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CCSIDR_WT 31 +#define M_CCSIDR_WT (0x1 << S_CCSIDR_WT) /* Support write-through */ +#define S_CCSIDR_WB 30 +#define M_CCSIDR_WB (0x1 << S_CCSIDR_WB) /* Support write-back */ +#define S_CCSIDR_RA 29 +#define M_CCSIDR_RA (0x1 << S_CCSIDR_RA) /* Support read-allocation */ +#define S_CCSIDR_WA 28 +#define M_CCSIDR_WA (0x1 << S_CCSIDR_WA) /* Support write-allocation */ +#define S_CCSIDR_SETS 13 +#define M_CCSIDR_SETS (0x7fff << S_CCSIDR_SETS) /* Number of sets */ +#define S_CCSIDR_A 3 +#define M_CCSIDR_A (0x3ff << S_CCSIDR_A) /* Number of associatiovity */ +#define S_CCSIDR_LS 0 +#define M_CCSIDR_LS (0x7 << S_CCSIDR_LS) /* Cache line size */ + +/* + ************************************************************************ + * Cache Level ID Register, CLIDR (cp15, 1, c0, c0, 1) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |0|0|LoUU |LoC |LoUIS|CT7 |CT6 |CT5 |CT4 |CT3 |CT2 |CT1 | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CLIDR_LoUU 27 +#define M_CLIDR_LoUU (0x7 << S_CLIDR_LoUU) +#define S_CLIDR_LoC 24 +#define M_CLIDR_LoC (0x7 << S_CLIDR_LoC) /* Cache cohernecy level */ +#define S_CLIDR_LoUIS 21 +#define M_CLIDR_LoUIS (0x7 << S_CLIDR_LoUIS) +#define S_CLIDR_Ctype7 18 +#define M_CLIDR_Ctype7 (0x7 << S_CLIDR_Ctype7) /* Cache type of level 7 cache */ +#define S_CLIDR_Ctype6 15 +#define M_CLIDR_Ctype6 (0x7 << S_CLIDR_Ctype6) /* Cache type of level 6 cache */ +#define S_CLIDR_Ctype5 12 +#define M_CLIDR_Ctype5 (0x7 << S_CLIDR_Ctype5) /* Cache type of level 5 cache */ +#define S_CLIDR_Ctype4 9 +#define M_CLIDR_Ctype4 (0x7 << S_CLIDR_Ctype4) /* Cache type of level 4 cache */ +#define S_CLIDR_Ctype3 6 +#define M_CLIDR_Ctype3 (0x7 << S_CLIDR_Ctype3) /* Cache type of level 3 cache */ +#define S_CLIDR_Ctype2 3 +#define M_CLIDR_Ctype2 (0x7 << S_CLIDR_Ctype2) /* Cache type of level 2 cache */ +#define S_CLIDR_Ctype1 0 +#define M_CLIDR_Ctype1 (0x7 << S_CLIDR_Ctype1) /* Cache type of level 1 cache */ + +#define K_CLIDR_Ctype_NO 0 /* No cache */ +#define K_CLIDR_Ctype_IC 1 /* Instruction cache only */ +#define K_CLIDR_Ctype_DC 2 /* Data cache only */ +#define K_CLIDR_Ctype_ID 3 /* Seperate instruction and data caches, Harvard cache */ +#define K_CLIDR_Ctype_U 4 /* Unified cache, von Neumann cacge */ + +/* + ************************************************************************ + * Cache Size Selection Register, CCSELR (cp15, 2, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |Reserved |Level|I| + * | | |n| + * | | |D| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CCSELR_Level 1 +#define M_CCSELR_Level (0x7 << S_CCSELR_Level) /* Cache level */ +#define S_CCSELR_InD 0 +#define M_CCSELR_InD (0x1 << S_CCSELR_InD) /* I$ or D$ */ + +/* + ************************************************************************ + * System Control Register, SCTLR (cp15, 0, c1, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |R|T|A|T|N|0|E|V|1|U|F|U|W|1|H|1|0|R|V|I|Z|S|0|0|B|1|B|1|1|C|A|M| + * | |E|F|R|M| |E|E| | |I|W|X| |A| | | | | | |W| | | | |E| | | | | | + * | | |E|E|F| | | | | | |X|N| | | | | | | | | | | | | |N| | | | | | + * | | | | |I| | | | | | |N| | | | | | | | | | | | | | | | | | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_SCTLR_TE 30 +#define M_SCTLR_TE (0x1 << S_SCTLR_TE) /* Thumb exception enable */ +#define S_SCTLR_AFE 29 +#define M_SCTLR_AFE (0x1 << S_SCTLR_AFE) /* Access flag enable */ +#define S_SCTLR_TRE 28 +#define M_SCTLR_TRE (0x1 << S_SCTLR_TRE) /* TXE remap enable */ +#define S_SCTLR_NMFI 27 +#define M_SCTLR_NMFI (0x1 << S_SCTLR_NMFI) /* None-maskable FIQ enbale (RO) */ +#define S_SCTLR_EE 25 +#define M_SCTLR_EE (0x1 << S_SCTLR_EE) /* Exception Endianness: big-endian */ +#define S_SCTLR_VE 24 +#define M_SCTLR_VE (0x1 << S_SCTLR_VE) /* Interrupt Vector Enable */ +#define S_SCTLR_FI 21 +#define M_SCTLR_FI (0x1 << S_SCTLR_FI) /* Fast interrupt configuraiont enable */ +#define S_SCTLR_UWXN 20 +#define M_SCTLR_UWXN (0x1 << S_SCTLR_UWXN) /* */ +#define S_SCTLR_WXN 19 +#define M_SCTLR_WXN (0x1 << S_SCTLR_WXN) +#define S_SCTLR_HA 17 +#define M_SCTLR_HA (0x1 << S_SCTLR_HA) /* Hardware access flag enable */ +#define S_SCTLR_RR 14 +#define M_SCTLR_RR (0x1 << S_SCTLR_RR) /* Round-robin select */ +#define S_SCTLR_V 13 +#define M_SCTLR_V (0x1 << S_SCTLR_V) /* Vector bits */ +#define S_SCTLR_I 12 +#define M_SCTLR_I (0x1 << S_SCTLR_I) /* Instruction cache enable */ +#define S_SCTLR_Z 11 +#define M_SCTLR_Z (0x1 << S_SCTLR_Z) /* Branch prediction enable */ +#define S_SCTLR_SW 10 +#define M_SCTLR_SW (0x1 << S_SCTLR_SW) /* SW and SWP enable */ +#define S_SCTLR_CP15BEN 5 +#define M_SCTLR_CP15BEN (0x1 << S_SCTLR_CP15BEN) /* CP15 barrier support */ +#define S_SCTLR_C 2 +#define M_SCTLR_C (0x1 << S_SCTLR_C) /* Data and Unidied cache enable */ +#define S_SCTLR_A 1 +#define M_SCTLR_A (0x1 << S_SCTLR_A) /* Alignment fault checking enable */ +#define S_SCTLR_M 0 +#define M_SCTLR_M (0x1 << S_SCTLR_M) /* PL1&0 stage MMU enable */ + +/************************************************************************ + * Auxiliary Control Register, ACTLR (cp15, 0, c1, c0, 1) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |UNP/SBZP |P|A|E|S|RAZ|W|L|L|F| + * | |a|l|X|M| | |1|2|W| + * | |r|l|C|P| |f| | | | + * | | |o|L| | |l|p|p| | + * | |o|c| | | | |r|r| | + * | |n| | | | |z|e|e| | + * | | |o| | | |e|f|f| | + * | | |n| | | |r| | | | + * | | |e| | | |o|e|e| | + * | | | | | | |s|n|n| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_ACTLR_PAR_ON 9 +#define M_ACTLR_PAR_ON (0x1 << S_ACTLR_PAR_ON) /* Parity on */ +#define S_ACTLR_ALLOC_ONE 8 +#define M_ACTLR_ALLOC_ONE (0x1 << S_ACTLR_ALLOC_ONE) /* Alloc in one way */ +#define S_ACTLR_EXCL 7 +#define M_ACTLR_EXCL (0x1 << S_ACTLR_EXCL) /* Exclusive cache */ +#define S_ACTLR_SMP 6 +#define M_ACTLR_SMP (0x1 << S_ACTLR_SMP) /* SMP */ +#define S_ACTLR_W_FL_ZEROS 3 +#define M_ACTLR_W_FL_ZEROS (0x1 << S_ACTLR_W_FL_ZEROS) /* Write full line of zeros mode */ +#define S_ACTLR_L1_PERF_EN 2 +#define M_ACTLR_L1_PERF_EN (0x1 << S_ACTLR_L1_PERF_EN) /* Dside prefetch enable */ +#define S_ACTLR_L2_PERF_EN 1 +#define M_ACTLR_L2_PERF_EN (0x1 << S_ACTLR_L2_PERF_EN) /* L2 prefetch enable */ +#define S_ACTLR_FW 0 +#define M_ACTLR_FW (0x1 << S_ACTLR_FW) /* Cache and TLB maintenance boardcast */ + + diff --git a/board/novatek/na51055/loader/Include/IOReg.h b/board/novatek/na51055/loader/Include/IOReg.h new file mode 100755 index 000000000000..7f4e2f31885e --- /dev/null +++ b/board/novatek/na51055/loader/Include/IOReg.h @@ -0,0 +1,190 @@ +/** + I/O Access header file + + I/O Access header file + + @file IOReg.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef __IO_REG_H +#define __IO_REG_H + +#include "constant.h" +#include "CMacro.h" +#include "Memory.h" + +/** + @addtogroup mISYSUtil +*/ +//@{ + +/** + @name Input 8bit IO register + + Input 8bit IO register + + @param[in] x I/O address + + @return register value +*/ +//@{ +#define INREG8(x) (*((volatile UINT8*)(x))) ///< Read 8bits IO register +//@} + +/** + @name Output 8bit IO register + + Output to 8bit IO register + + @param[in] x I/O address + @param[in] y Value to be output + + @return void +*/ +//@{ +#define OUTREG8(x, y) (*((volatile UINT8*)(x)) = (y)) ///< Write 8bits IO register +//@} + +/** + @name Set bits to 8bit IO register + + Set bits to 8bit IO register + + @param[in] x I/O address + @param[in] y Value to be set. y will be ORed to this address + + @return register value +*/ +//@{ +#define SETREG8(x, y) OUTREG8((x), INREG8(x) | (y)) ///< Set 8bits IO register +//@} + +/** + @name Clear bits from 8bit IO register + + Clear bits from 8bit IO register + + @param[in] x I/O address + @param[in] y Value to be clear. ~(y) will be ANDed to this address + + @return register value +*/ +//@{ +#define CLRREG8(x, y) OUTREG8((x), INREG8(x) & ~(y)) ///< Clear 8bits IO register +//@} + +/** + @name Input 16bit IO register + + Input 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + + @return register value +*/ +//@{ +#define INREG16(x) (*((volatile UINT16*)(x))) ///< Read 16bits IO register +//@} + +/** + @name Output 16bit IO register + + Output to 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + @param[in] y Value to be output + + @return void +*/ +//@{ +#define OUTREG16(x, y) (*((volatile UINT16*)(x)) = (y)) ///< Write 16bits IO register +//@} + +/** + @name Set bits to 16bit IO register + + Set bits to 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + @param[in] y Value to be set. y will be ORed to this address + + @return register value +*/ +//@{ +#define SETREG16(x, y) OUTREG16((x), INREG16(x) | (y)) ///< Set 16bits IO register +//@} + +/** + @name Clear bits from 16bit IO register + + Clear bits from 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + @param[in] y Value to be clear. ~(y) will be ANDed to this address + + @return register value +*/ +//@{ +#define CLRREG16(x, y) OUTREG16((x), INREG16(x) & ~(y)) ///< Clear 16bits IO register +//@} + +/** + @name Input 32bit IO register + + Input 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + + @return register value +*/ +//@{ +#define INREG32(x) (*((volatile UINT32*)(x))) ///< Read 32bits IO register +//@} + +/** + @name Output 32bit IO register + + Output to 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + @param[in] y Value to be output + + @return void +*/ +//@{ +#define OUTREG32(x, y) (*((volatile UINT32*)(x)) = (y)) ///< Write 32bits IO register +//@} + +/** + @name Set bits to 32bit IO register + + Set bits to 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + @param[in] y Value to be set. y will be ORed to this address + + @return register value +*/ +//@{ +#define SETREG32(x, y) OUTREG32((x), INREG32(x) | (y)) ///< Set 32bits IO register +//@} + +/** + @name Clear bits from 32bit IO register + + Clear bits from 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + @param[in] y Value to be clear. ~(y) will be ANDed to this address + + @return register value +*/ +//@{ +#define CLRREG32(x, y) OUTREG32((x), INREG32(x) & ~(y)) ///< Clear 32bits IO register +//@} + +//@} + +#endif // __IO_REG_H diff --git a/board/novatek/na51055/loader/Include/SMacro.h b/board/novatek/na51055/loader/Include/SMacro.h new file mode 100755 index 000000000000..372ea3898671 --- /dev/null +++ b/board/novatek/na51055/loader/Include/SMacro.h @@ -0,0 +1,129 @@ +; Global vars for arg parsing + + GBLS _arg0 + GBLS _arg1 + +; _spaces_remove +; remove start and end spaces from global variable wstring + + MACRO + _spaces_remove $wstring + WHILE ( ("*" :CC: $wstring) :RIGHT: 1 = " ") +$wstring SETS ($wstring :LEFT: (:LEN: $wstring - 1)) + WEND + WHILE ( ($wstring :CC: "*") :LEFT: 1 = " ") +$wstring SETS ($wstring :RIGHT: (:LEN: $wstring - 1)) + WEND + MEND + +; _lbracket_remove +; Attempt to remove a single left bracket - error if not there + + MACRO + _lbracket_remove $s + ASSERT $s:LEFT:1 = "(" +$s SETS $s:RIGHT:(:LEN:$s-1) + _spaces_remove $s + MEND + +; _rbracket_remove +; Attempt to remove a single right bracket - error if not there +; then removes excess spaces + + MACRO + _rbracket_remove $s + ASSERT $s:RIGHT:1 = ")" +$s SETS $s:LEFT:(:LEN:$s-1) + _spaces_remove $s + MEND + +; _comment_remove +; Remove any comment from line end and then strip any spaces + + MACRO + _comment_remove $s + _spaces_remove $s + IF (("**":CC:$s):RIGHT:2) = "*/" + WHILE ($s:RIGHT:2) <> "/*" +$s SETS $s:LEFT:(:LEN:$s-1) + WEND +$s SETS $s:LEFT:(:LEN:$s-2) + _spaces_remove $s + ENDIF + MEND + +; _arg_remove +; Pull an argument from the front of a spaces stripped string + + MACRO + _arg_remove $s,$arg + LCLA _arglen + LCLL _ok +_arglen SETA 0 +_ok SETL {TRUE} + WHILE _ok + IF _arglen>=:LEN:$s +_ok SETL {FALSE} ; break if used up input string + ELSE +$arg SETS ($s:LEFT:(_arglen+1)):RIGHT:1 ; next character + IF $arg=" " +_ok SETL {FALSE} + ELSE +_arglen SETA _arglen+1 + ENDIF + ENDIF + WEND +$arg SETS $s:LEFT:_arglen +$s SETS $s:RIGHT:(:LEN:$s-_arglen) + _spaces_remove $s + MEND + +; ifndef +; Purpose: Allow #ifndef for common C headers (Just for guarded C header file) +; Syntax : #ifndef + + MACRO + ifndef $a + MEND + +; define +; Purpose: Allow #defines for common C/Assembler headers +; Syntax : #define + + MACRO +$la define $a +_arg0 SETS "$a" + ASSERT "$la"="#" ; syntax: # define fred 1 + _comment_remove _arg0 + _arg_remove _arg0,_arg1 + IF "$_arg0"<>"" +$_arg1 EQU $_arg0 + ENDIF + MEND + + +; COMMENT +; Purpose: Allow comments in common C/Assembler headers +; Syntax : COMMENT + + MACRO + COMMENT $a,$b,$c,$d,$e,$f,$g,$h + MEND + +; local labels use label$l to get a local label and LOCAL to start a new +; area + + GBLA LocalCount + GBLS l +LocalCount SETA 1 +l SETS "x$LocalCount" + +; increment local variable number + + MACRO + LOCAL +LocalCount SETA LocalCount+1 +l SETS "x$LocalCount" + MEND + + END diff --git a/board/novatek/na51055/loader/Include/StorageDef.h b/board/novatek/na51055/loader/Include/StorageDef.h new file mode 100755 index 000000000000..cd1c9f444f8e --- /dev/null +++ b/board/novatek/na51055/loader/Include/StorageDef.h @@ -0,0 +1,446 @@ +/** + Storage module driver. + + This file is the driver of storage module. + + @file StorageDef.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _STORAGE_DEF_ +#define _STORAGE_DEF_ + +#include "constant.h" + +#define _STORAGE_OBJ_ 1 +/** + @addtogroup mIDrvStorage +*/ +//@{ + +/** + @name External storage type + +*/ +//@{ +#define EXT_STORAGE_TYPE_NONE (0) +#define EXT_STORAGE_TYPE_SDIO1 (1) +#define EXT_STORAGE_TYPE_SDIO2 (2) +#define EXT_STORAGE_TYPE_USB (3) +#define EXT_STORAGE_TYPE_ETH (4) +//*} + +/** + @name SPI Quad read type + + @note for SPI_IDENTIFY +*/ +//@{ +#define SPI_QUAD_NONE 0 ///< Not support +#define SPI_QUAD_TYPE1 1 ///< Support quad read, QE(Quad Enable) bit is in Status Reigster[bit 6] and 0x6B command requires 8 dummy clocks. +#define SPI_QUAD_TYPE2 2 ///< Support quad read, QE(Quad Enable) bit is in Status Register[bit 9] and 0x6B command requires 8 dummy clocks. +#define SPI_QUAD_TYPE3 3 ///< Support quad read, QE(Quad Enable) NOT exist and 0x6B command requires 8 dummy clocks +#define SPI_QUAD_TYPE4 4 ///< Support quad read, QE(Quad Enable) bit is in Status Register[bit 9] and 0x6B command requires 8 dummy clocks. + ///< But QE should be modified by 0x31 command +//@} + + +/** + @name SPI RDCR read type + + @note for SPI_IDENTIFY +*/ +//@{ +#define SPI_RDCR_NONE 0 ///< Not support +#define SPI_RDCR_TYPE1 1 ///< Support RDCR(0x15) bit[7..6] need config as 0x3 + +//@} + +/** + SPI flash identify descriptor + + @note For STRG_IDENTIFY_CB +*/ +typedef struct +{ + BOOL bSupportEWSR; ///< EWSR(0x50) command capability + ///< - @b TRUE: support EWSR command + ///< - @b FALSE: NOT support EWSR command + BOOL bSupportAAI; ///< AAI program(0xAD) command capability + ///< - @b TRUE: ONLY support AAI program command + ///< - @b FALSE: NOT support AAI program command, but support page program command + BOOL bDualRead; ///< Dual read (0x3B) command capability + ///< - @b TRUE: support dual read comand. (Command value should be 0x3B.) + ///< - @b FALSE: NOT support dual read command + UINT32 uiQuadReadType; ///< Quad read type capability. (ONLY support quad command 0x6B) + ///< - @b SPI_QUAD_NONE: NOT support quad read command + ///< - @b SPI_QUAD_TYPE1: Support quad read command, QE in Status Register bit 6 + ///< - @b SPI_QUAD_TYPE2: Support quad read command, QE in Status Register bit 9 + ///< - @b SPI_QUAD_TYPE3: Support quad read command, QE NOT exist + ///< - @b SPI_QUAD_TYPE4: Support quad read command, QE in Status Register bit 9 (but need 0x31 command) + UINT32 uiFlashSize; ///< Flash total byte size. (unit: byte) +} SPI_IDENTIFY, *PSPI_IDENTIFY; + +/** + @name Storage Access CallBack + + Storage Access CallBack Prototype + + @return void +*/ +//@{ +typedef void (*STRG_ACCESS_CB)(void); ///< Storage access call back prototype +//@} + +/** + @name Storage Identify CallBack + + Storage Identify CallBack Prototype + + @param[in] UINT32 uiMfgID (JEDEC) manufacturer ID read from spi flash + @param[in] UINT32 uiTypeID (JEDEC) type ID read from spi flash + @param[in] UINT32 uiCapacityID (JEDEC) capacity ID read from spi flash + @param[out] PSPI_IDENTIFY flash identification returned to spi flash driver + + @return + - @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information + - @b FALSE: input ID is NOT supported/identified by call back +*/ +//@{ +typedef BOOL (*STRG_IDENTIFY_CB)(UINT32, UINT32, UINT32, PSPI_IDENTIFY); ///< Storage identify call back prototype +//@} + +/** + @name Storage return value + + @note for flash_open(), flash_readSectors(), and flash_writeSectors() +*/ +//@{ +#define E_OK 0 ///< Success +#define E_NAND_IDENTIFY_ERR -1 ///< Read NAND ID (information) error +#define E_NAND_INSUFFICINET_BLK -2 ///< Bad block is too much to write data +#define E_NAND_BLK_NOT_FOUND -3 ///< Logic block number not found in physical block +#define E_NAND_WRITE_PAGEDATA_ERR -4 ///< Logic block number not found in physical block +#define E_NAND_ERASEE_BLK_ERR -5 ///< NAND erase block error +#define E_NAND_READ_PAGE_ERR -6 ///< NAND read page data error +#define E_NAND_READ_BLK_ERR -7 ///< NAND read block data error +#define E_NAND_ID_NOT_SUPPORT -8 ///< Not support NAND ID +#define E_IDENTIFY_ERR -9 ///< SPI IDENTIFY error +#define E_SYS -10 ///< System Error +#define E_NAND_ALIGN_ERR -11 ///< Not block alignment +#define E_OK_TABLE_FOUND 1 ///< Success & NAND table find +#define E_OK_TABLE_NOT_FOUND 2 ///< Success & NAND table not find +//@} + +/** + @name Internal Storage Update Region + + @note for flash_readSectors(), and flash_writeSectors() +*/ +//@{ +#define NAND_RW_LOADER 0 ///< Update Region is Loader (Update size is assumed 16 KB) +#define NAND_RW_RESERVED 1 ///< Update Region is reserved area (Update size is assumed 16 KB) +#define NAND_RW_FIRMWARE 2 ///< Update Region is FW (Update size is variable) +#define NAND_RW_FIRMWARE_2 3 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_3 4 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_4 5 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_5 6 ///< Update Region is FW from 2-5(Update size is variable) +//@} + +/** + @name Internal Storage Configuration ID + + @note for flash_setConfig() +*/ +//@{ +#define FLASH_CFG_ID_NONE 0 +#define FLASH_CFG_ID_SPI_SUPPORT_4BITS 1 ///< Enable your project to support 4 bit SPI flash. ONLY enable when you ENSURE SPI_D0~SPI_D3 are connected to SPI flash in your PCB!!! +#define FLASH_CFG_ID_EMMC_SUPPORT_8BITS 2 ///< Enable your project to support 8 bit EMMC. ONLY enable when you ENSURE EMMC_D0~SPI_D7 are connected to EMMC flash in your PCB!!! +#define FLASH_CFG_ID_CS_SELECT 3 ///< Select this flash (nand/nor) is connected with CS0 or CS1 +#define FLASH_CFG_ID_SPI_IDENTIFY_CB 4 ///< Install flash identify call back +//@} + +#if (_STORAGE_OBJ_== 1) + + +#define BOOT_SOURCE_SPI 0x00 +#define BOOT_SOURCE_SPI_NAND_2K 0x02 +#define BOOT_SOURCE_SPI_NAND_4K 0x06 +#define BOOT_SOURCE_EMMC_4BIT 0x08 +#define BOOT_SOURCE_EMMC_8BIT 0x09 + +/** + @name New storage object interface + + For new version storage device driver +*/ +//@{ +typedef struct { + INT32(*flash_open)(void); ///< Flash Open + void(*flash_close)(void); ///< Flash Close + INT32(*flash_readSectors)(UINT32, UINT32, UINT8 *,UINT32); ///< Flash Read Sector + INT32(*flash_writeSectors)(UINT32, UINT32, UINT8 *, UINT32); ///< Flash Write Sector + UINT32(*flash_getBlockSize)(void); ///< Flash Get Block Size + void(*flash_setReservedBadBlockNumber)(UINT32); ///< Flash Set Reserved Bad Block Number + void(*flash_setReservedAreaMaxBlockNumber)(UINT32); ///< Flash Set Reserved Area Block Number + UINT64(*flash_getTotalSize)(void); + void(*flash_installAccessCB)(STRG_ACCESS_CB); + void(*flash_installIdentifyCB)(STRG_IDENTIFY_CB); + void(*flash_setFrequency)(UINT32); + INT32(*flash_setConfig)(UINT32, UINT32); + INT32(*flash_get_spare_data)(UINT32, UINT32 *); +} STORAGE_OBJ, *PSTORAGE_OBJ; + +extern PSTORAGE_OBJ emmc_get_storage_object(void); +extern PSTORAGE_OBJ nand_get_storage_object(void); +extern PSTORAGE_OBJ nor_get_storage_object(void); + +//@} +#else +#define FLASH_OPEN(m) flash_open() +#define FLASH_CLOSE(m) flash_close() +#define FLASH_READSECTOR(m, n, o, x, y) flash_readSectors(n,o,x,y) ///< Flash Read Sector +#define FLASH_WRITESECTOR(m, n, o, x, y) flash_writeSectors(n,o,x,y) ///< Flash Write Sector +#define FLASH_GETBLKSIZE(m) flash_getBlockSize() + + void(*flash_setReservedBadBlockNumber)(UINT32); ///< Flash Set Reserved Bad Block Number + void(*flash_setReservedAreaMaxBlockNumber)(UINT32); ///< Flash Set Reserved Area Block Number + UINT64(*flash_getTotalSize)(void); + void(*flash_installAccessCB)(STRG_ACCESS_CB); + void(*flash_installIdentifyCB)(STRG_IDENTIFY_CB); + void(*flash_setFrequency)(UINT32); + INT32(*flash_setConfig)(UINT32, UINT32); +} STORAGE_OBJ, *PSTORAGE_OBJ; + +/** + Flash Open + + This function will initialize internal flash driver + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return + - @b E_OK: open success + - @b E_IDENTIFY_ERR: identify fail (SPI path) + - @b E_NAND_IDENTIFY_ERR: identify fail (NAND path) + - @b E_NAND_ID_NOT_SUPPORT: not supported NAND flash +*/ +extern INT32 flash_open(void); +/** + Flash Close + + This function will close internal flash driver + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return void +*/ +extern void flash_close(void); + +/** + Flash Read Sector + + This function will read data from internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] startblk Start block of this read operation (unit: flash block) + @param[in] length Length of read operation (unit: byte) + @param[out] buffer Pointer to DRAM buffer to receive read data (word alignment) + @param[in] updateType Operation Access Region + - @b NAND_RW_LOADER: loader region + - @b NAND_RW_RESERVED: reserved area + - @b NAND_RW_FIRMWARE: f/w region + + @return + - @b E_OK: read success + - @b E_NAND_BLK_NOT_FOUND: can not find available physical block + - @b E_NAND_READ_BLK_ERR: NAND access block error + - @b E_NAND_READ_PAGE_ERR: NAND access page error +*/ +extern INT32 flash_readSectors(UINT32 startblk, UINT32 length, UINT8 * buffer, UINT32 updateType); + +/** + Flash Write Sector + + This function will write data to internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] startblk Start block of this write operation (unit: flash block) + @param[in] length Length of write operation (unit: byte) + @param[in] buffer Pointer to DRAM buffer of written data (word alignment) + @param[in] updateType Operation Access Region + - @b NAND_RW_LOADER: loader region + - @b NAND_RW_RESERVED: reserved area + - @b NAND_RW_FIRMWARE: f/w region + + @return + - @b E_OK: read success + - @b E_NAND_BLK_NOT_FOUND: can not find available physical block + - @b E_NAND_ERASEE_BLK_ERR: erase block error + - @b E_NAND_WRITE_PAGEDATA_ERR: page program error + - @b E_NAND_INSUFFICINET_BLK: insufficient good block +*/ +extern INT32 flash_writeSectors(UINT32 startblk, UINT32 length, UINT8 * buffer, UINT32 updateType); + +/** + Flash Get Block Size + + This function will return block size of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return block size (unit: byte) +*/ +extern UINT32 flash_getBlockSize(void); + +/** + Flash Set Reserved Bad Block Number + + This function will set block count reserved to do bad block replacement + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] badBlkNum reserved bad block count (unit: block) + + @return void +*/ +extern void flash_setReservedBadBlockNumber(UINT32 badBlkNum); + +//#NT#2010/04/20#Steven Wang -begin +//#NT#Autumn reserved area from 2 ~ 23 +/** + Flash Set Reserved Area Block Number + + This function will set reserved area max block count + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] RsvMaxBlkNum max reserved area block count (unit: block) + + @return void +*/ +extern void flash_setReservedAreaMaxBlockNumber(UINT32 RsvMaxBlkNum); +//#NT#2010/04/20#Steven Wang -end + +/** + Flash Get Total Size + + This function will return total size of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return total size (unit: byte) +*/ +extern UINT64 flash_getTotalSize(void); + +/** + Install Flash Access CallBack + + This function will install access callback. + The installed callback will be invoked when one block/page is programmed + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @param[in] accessCB installed callback + + @return void +*/ +extern void flash_installAccessCB(STRG_ACCESS_CB accessCB); + +/** + Install Flash Identify CallBack + + This function will install identification callback. + The installed callback will be invoked when spi flash driver is opened. + + @note NAND driver will NOT invoke the installed call back + + @param[in] identifyCB installed callback + + @return void +*/ +extern void flash_installIdentifyCB(STRG_IDENTIFY_CB identifyCB); + +/** + Flash Set Bus Frequency + + This function will set operating frequency of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] uiFreq Operating frequency (unit: MHz) + + @return void +*/ +extern void flash_setFrequency(UINT32 uiFreq); + +/** + Flash Set Configuration + + This function will set specific configuration for internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] uiConfigId Configuration ID, can be: + - @b FLASH_CFG_ID_SPI_SUPPORT_4BITS: configure to support 4 bit SPI flash + @param[in] uiContext Configuration context for uiConfigId + When uiConfigId == FLASH_CFG_ID_SPI_SUPPORT_4BITS: + - @b TRUE: use 4 bit read when attached SPI flash support 4 bit read + - @b FALSE: won't use 4 bit read + + @return + - @b E_OK: success + - @b Else: fail +*/ +extern INT32 flash_setConfig(UINT32 uiConfigId, UINT32 uiContext); +#endif +// External storage public API ( SDIO/MS/xD ) +/** + Open card driver + + This function will initialize card driver and register it to file system + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return + - @b TRUE: open success + - @b FALSE: open fail +*/ +extern INT32 card_open(void); + +/** + Close card driver + + This function will close card driver + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return void +*/ +extern void card_close(void); + +/** + Get card type + + This function is used to get card storage type + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return void +*/ + +extern UINT32 card_get_type(void); + +//@} + +extern void USBOTGReset(void); +//extern INT32 USB3Download(void); +extern INT32 USBDownload(void); +extern void USBSetResult(UINT32 uiResult); +extern INT32 USBStateMachine(void); +#endif diff --git a/board/novatek/na51055/loader/Include/Type.h b/board/novatek/na51055/loader/Include/Type.h new file mode 100755 index 000000000000..74a00059eaaa --- /dev/null +++ b/board/novatek/na51055/loader/Include/Type.h @@ -0,0 +1,9 @@ +#ifndef __TYPE_H +#define __TYPE_H + +#include +//#include + +#define _ALIGNED(x) __attribute__((aligned(x))) + +#endif // __TYPE_H diff --git a/board/novatek/na51055/loader/Include/constant.h b/board/novatek/na51055/loader/Include/constant.h new file mode 100755 index 000000000000..3dea2682ef8d --- /dev/null +++ b/board/novatek/na51055/loader/Include/constant.h @@ -0,0 +1,112 @@ +#ifndef _CONSTANT_H +#define _CONSTANT_H + +//Size MNEMONIC + +#define SZ_1 (1 << 0) /* 0x00000001 */ +#define SZ_2 (1 << 1) /* 0x00000002 */ +#define SZ_4 (1 << 2) /* 0x00000004 */ +#define SZ_8 (1 << 3) /* 0x00000008 */ +#define SZ_16 (1 << 4) /* 0x00000010 */ +#define SZ_32 (1 << 5) /* 0x00000020 */ +#define SZ_64 (1 << 6) /* 0x00000040 */ +#define SZ_128 (1 << 7) /* 0x00000080 */ +#define SZ_256 (1 << 8) /* 0x00000100 */ +#define SZ_512 (1 << 9) /* 0x00000200 */ + +#define SZ_1K (1 << 10) /* 0x00000400 */ +#define SZ_2K (1 << 11) /* 0x00000800 */ +#define SZ_4K (1 << 12) /* 0x00001000 */ +#define SZ_8K (1 << 13) /* 0x00002000 */ +#define SZ_16K (1 << 14) /* 0x00004000 */ +#define SZ_32K (1 << 15) /* 0x00008000 */ +#define SZ_64K (1 << 16) /* 0x00010000 */ +#define SZ_128K (1 << 17) /* 0x00020000 */ +#define SZ_256K (1 << 18) /* 0x00040000 */ +#define SZ_512K (1 << 19) /* 0x00080000 */ + +#define SZ_1M (1 << 20) /* 0x00100000 */ +#define SZ_2M (1 << 21) /* 0x00200000 */ +#define SZ_4M (1 << 22) /* 0x00400000 */ +#define SZ_8M (1 << 23) /* 0x00800000 */ +#define SZ_16M (1 << 24) /* 0x01000000 */ +#define SZ_32M (1 << 25) /* 0x02000000 */ +#define SZ_64M (1 << 26) /* 0x04000000 */ +#define SZ_128M (1 << 27) /* 0x08000000 */ +#define SZ_256M (1 << 28) /* 0x10000000 */ +#define SZ_512M (1 << 29) /* 0x20000000 */ + +#define SZ_1G (1 << 30) /* 0x40000000 */ +#define SZ_2G (1 << 31) /* 0x80000000 */ + +#define SZ_30M (SZ_32M - SZ_2M) + +// ASCII code + +#define CR 0x0D +#define LF 0x0A +#define BS 0x08 +#define ESC 27 + +// Boolean constant definition + +#if 0 +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef ON +#define ON 1 +#endif + +#ifndef OFF +#define OFF 0 +#endif + +#ifndef ENABLE +#define ENABLE 1 +#endif + +#ifndef DISABLE +#define DISABLE 0 +#endif + +#ifndef DISK_FULL +#define DISK_FULL (-1) +#endif + +// type declaration + +typedef int BOOLEAN; +typedef unsigned long long UINT64; +typedef long long INT64; +typedef unsigned long UINT32; +typedef long INT32; +typedef unsigned short UINT16; +typedef short INT16; +typedef unsigned char UINT8; +typedef char INT8; +typedef unsigned long long u64; +typedef unsigned int u32; +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int uint; +typedef unsigned short ushort; +typedef unsigned char uchar; +typedef unsigned int UINT; +typedef int INT; + +typedef enum {FALSE, TRUE} BOOL; + +// error codes +typedef long ER; + +#endif diff --git a/board/novatek/na51055/loader/Include/ctype.h b/board/novatek/na51055/loader/Include/ctype.h new file mode 100755 index 000000000000..dbbc7cf7dd9c --- /dev/null +++ b/board/novatek/na51055/loader/Include/ctype.h @@ -0,0 +1,36 @@ + + +#ifndef NVT_CTYPES_H__ +#define NVT_CTYPES_H__ + + +#define _U 0x01 /* upper */ +#define _L 0x02 /* lower */ +#define _D 0x04 /* digit */ +#define _C 0x08 /* cntrl */ +#define _P 0x10 /* punct */ +#define _S 0x20 /* white space (space/lf/tab) */ +#define _X 0x40 /* hex digit */ +#define _SP 0x80 /* hard space (0x20) */ + +extern unsigned char _ctype[]; + +#define __ismask(x) (_ctype[(int)(unsigned char)(x)]) + +#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) +#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) +#define iscntrl(c) ((__ismask(c)&(_C)) != 0) +#define isdigit(c) ((__ismask(c)&(_D)) != 0) +#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) +#define islower(c) ((__ismask(c)&(_L)) != 0) +#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) +#define ispunct(c) ((__ismask(c)&(_P)) != 0) +#define isspace(c) ((__ismask(c)&(_S)) != 0) +#define isupper(c) ((__ismask(c)&(_U)) != 0) +#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) + +#define isascii(c) (((unsigned char)(c))<=0x7f) +#define toascii(c) (((unsigned char)(c))&0x7f) + + +#endif diff --git a/board/novatek/na51055/loader/Include/debug.h b/board/novatek/na51055/loader/Include/debug.h new file mode 100755 index 000000000000..e5a72564556d --- /dev/null +++ b/board/novatek/na51055/loader/Include/debug.h @@ -0,0 +1,29 @@ +/** + string header + + string header + + @file string.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_DEBUG_H__ +#define __NVT_DEBUG_H__ + +/** \addtogroup mISYSClib */ +//@{ + +extern void debug_err(char *str); +extern void debug_err_var(char *str, int var); +extern void debug_msg(char *str) __attribute__ ((section (".part1"))); +extern void debug_msg_var(char *str, int var) __attribute__ ((section (".part1"))); +extern void debug_dump_addr(UINT32 addr, UINT32 size); + + +//@} + +#endif + diff --git a/board/novatek/na51055/loader/Include/fat.h b/board/novatek/na51055/loader/Include/fat.h new file mode 100755 index 000000000000..f1082903ea32 --- /dev/null +++ b/board/novatek/na51055/loader/Include/fat.h @@ -0,0 +1,48 @@ +/** + File system library + + This file is the library of file system + + @file fat.h + @ingroup mISYSFile + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _FAT_H +#define _FAT_H + +#include "constant.h" +#include "StorageDef.h" + +/** + @addtogroup mISYSFile +*/ +//@{ + +#define FAT_READ_TOTAL_FILE_LENGTH 0 + +typedef void (*TOGGLE_LED)(UINT8 WithCount); + +extern BOOL fat_initFAT(UINT32 uiBuf, UINT32 uiSize); +extern UINT32 fat_getPartitionCount(void); +extern BOOL fat_mountPartition(UINT32 partition_id); +extern void fat_closeFAT(void); +extern BOOL fat_open_rootfile(UINT8 *pfilename); +extern UINT32 fat_read_rootfile(UINT8 *pbuf, UINT32 uiRdLen); +extern UINT32 fat_getRootfileSize(void); +extern void fat_close_rootfile(void); +extern void fat_regToggleLED(TOGGLE_LED pToggleLED); +extern void fat_installAccessCB(STRG_ACCESS_CB accessCB); + +// For SD registration +extern BOOL fat_internal_initFAT(UINT32 uiBuf, UINT32 uiSize); +extern BOOL fat_internal_open_rootfile(UINT8 *pfilename); +extern UINT32 fat_internal_read_rootfile(UINT8 *pbuf, UINT32 uiRdLen); +extern void fat_internal_close_rootfile(void); + +//@} + +#endif + diff --git a/board/novatek/na51055/loader/Include/fdt/compiler.h b/board/novatek/na51055/loader/Include/fdt/compiler.h new file mode 100755 index 000000000000..7fa9b3831ab4 --- /dev/null +++ b/board/novatek/na51055/loader/Include/fdt/compiler.h @@ -0,0 +1,56 @@ +/* + * Keep all the ugly #ifdef for system stuff here + */ + +#ifndef __COMPILER_H__ +#define __COMPILER_H__ + +#ifndef NULL +#define NULL 0 +#endif + +#if 0 +#define uswap_16(x) (x) +#define uswap_32(x) (x) +#define _uswap_64(x, sfx) (x) +#else +#define uswap_16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) +#define uswap_32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) +#define _uswap_64(x, sfx) \ + ((((x) & 0xff00000000000000##sfx) >> 56) | \ + (((x) & 0x00ff000000000000##sfx) >> 40) | \ + (((x) & 0x0000ff0000000000##sfx) >> 24) | \ + (((x) & 0x000000ff00000000##sfx) >> 8) | \ + (((x) & 0x00000000ff000000##sfx) << 8) | \ + (((x) & 0x0000000000ff0000##sfx) << 24) | \ + (((x) & 0x000000000000ff00##sfx) << 40) | \ + (((x) & 0x00000000000000ff##sfx) << 56)) +#endif +#if defined(__GNUC__) +#define uswap_64(x) _uswap_64(x, ull) +#else +#define uswap_64(x) _uswap_64(x, ) +#endif +#define cpu_to_le16(x) (x) +#define cpu_to_le32(x) (x) +#define cpu_to_le64(x) (x) +#define le16_to_cpu(x) (x) +#define le32_to_cpu(x) (x) +#define le64_to_cpu(x) (x) +#define cpu_to_be16(x) uswap_16(x) +#define cpu_to_be32(x) uswap_32(x) +#define cpu_to_be64(x) uswap_64(x) +#define be16_to_cpu(x) uswap_16(x) +#define be32_to_cpu(x) uswap_32(x) +#define be64_to_cpu(x) uswap_64(x) + +/* Type for `void *' pointers. */ +typedef unsigned long int uintptr_t; + +#endif diff --git a/board/novatek/na51055/loader/Include/fdt/fdt.h b/board/novatek/na51055/loader/Include/fdt/fdt.h new file mode 100755 index 000000000000..0187749f19b6 --- /dev/null +++ b/board/novatek/na51055/loader/Include/fdt/fdt.h @@ -0,0 +1,111 @@ +#ifndef _FDT_H +#define _FDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ASSEMBLY__ + +struct fdt_header { + fdt32_t magic; /* magic word FDT_MAGIC */ + fdt32_t totalsize; /* total size of DT block */ + fdt32_t off_dt_struct; /* offset to structure */ + fdt32_t off_dt_strings; /* offset to strings */ + fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ + fdt32_t version; /* format version */ + fdt32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + fdt32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + fdt32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + fdt32_t size_dt_struct; /* size of the structure block */ +}; + +struct fdt_reserve_entry { + fdt64_t address; + fdt64_t size; +}; + +struct fdt_node_header { + fdt32_t tag; + char name[0]; +}; + +struct fdt_property { + fdt32_t tag; + fdt32_t len; + fdt32_t nameoff; + char data[0]; +}; + +#endif /* !__ASSEMBLY */ + +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_TAGSIZE sizeof(fdt32_t) + +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, + size, content */ +#define FDT_NOP 0x4 /* nop */ +#define FDT_END 0x9 + +#define FDT_V1_SIZE (7*sizeof(fdt32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) +#define FDT_V16_SIZE FDT_V3_SIZE +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) + +#endif /* _FDT_H */ diff --git a/board/novatek/na51055/loader/Include/fdt/libfdt.h b/board/novatek/na51055/loader/Include/fdt/libfdt.h new file mode 100644 index 000000000000..42c5e9d0e6e5 --- /dev/null +++ b/board/novatek/na51055/loader/Include/fdt/libfdt.h @@ -0,0 +1,1580 @@ +#ifndef _LIBFDT_H +#define _LIBFDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "libfdt_env.h" +#include "fdt.h" + +#define FDT_FIRST_SUPPORTED_VERSION 0x10 +#define FDT_LAST_SUPPORTED_VERSION 0x11 + +/* Error codes: informative error codes */ +#define FDT_ERR_NOTFOUND 1 + /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ +#define FDT_ERR_EXISTS 2 + /* FDT_ERR_EXISTS: Attemped to create a node or property which + * already exists */ +#define FDT_ERR_NOSPACE 3 + /* FDT_ERR_NOSPACE: Operation needed to expand the device + * tree, but its buffer did not have sufficient space to + * contain the expanded tree. Use fdt_open_into() to move the + * device tree to a buffer with more space. */ + +/* Error codes: codes for bad parameters */ +#define FDT_ERR_BADOFFSET 4 + /* FDT_ERR_BADOFFSET: Function was passed a structure block + * offset which is out-of-bounds, or which points to an + * unsuitable part of the structure for the operation. */ +#define FDT_ERR_BADPATH 5 + /* FDT_ERR_BADPATH: Function was passed a badly formatted path + * (e.g. missing a leading / for a function which requires an + * absolute path) */ +#define FDT_ERR_BADPHANDLE 6 + /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle + * value. phandle values of 0 and -1 are not permitted. */ +#define FDT_ERR_BADSTATE 7 + /* FDT_ERR_BADSTATE: Function was passed an incomplete device + * tree created by the sequential-write functions, which is + * not sufficiently complete for the requested operation. */ + +/* Error codes: codes for bad device tree blobs */ +#define FDT_ERR_TRUNCATED 8 + /* FDT_ERR_TRUNCATED: Structure block of the given device tree + * ends without an FDT_END tag. */ +#define FDT_ERR_BADMAGIC 9 + /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a + * device tree at all - it is missing the flattened device + * tree magic number. */ +#define FDT_ERR_BADVERSION 10 + /* FDT_ERR_BADVERSION: Given device tree has a version which + * can't be handled by the requested operation. For + * read-write functions, this may mean that fdt_open_into() is + * required to convert the tree to the expected version. */ +#define FDT_ERR_BADSTRUCTURE 11 + /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt + * structure block or other serious error (e.g. misnested + * nodes, or subnodes preceding properties). */ +#define FDT_ERR_BADLAYOUT 12 + /* FDT_ERR_BADLAYOUT: For read-write functions, the given + * device tree has it's sub-blocks in an order that the + * function can't handle (memory reserve map, then structure, + * then strings). Use fdt_open_into() to reorganize the tree + * into a form suitable for the read-write operations. */ + +/* "Can't happen" error indicating a bug in libfdt */ +#define FDT_ERR_INTERNAL 13 + /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. + * Should never be returned, if it is, it indicates a bug in + * libfdt itself. */ + +#define FDT_ERR_MAX 13 + +/**********************************************************************/ +/* Low-level functions (you probably don't need these) */ +/**********************************************************************/ + +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); +static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) +{ + return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); +} + +uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); + +/**********************************************************************/ +/* Traversal functions */ +/**********************************************************************/ + +int fdt_next_node(const void *fdt, int offset, int *depth); + +/** + * fdt_first_subnode() - get offset of first direct subnode + * + * @fdt: FDT blob + * @offset: Offset of node to check + * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + */ +int fdt_first_subnode(const void *fdt, int offset); + +/** + * fdt_next_subnode() - get offset of next direct subnode + * + * After first calling fdt_first_subnode(), call this function repeatedly to + * get direct subnodes of a parent node. + * + * @fdt: FDT blob + * @offset: Offset of previous subnode + * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes + */ +int fdt_next_subnode(const void *fdt, int offset); + +/**********************************************************************/ +/* General functions */ +/**********************************************************************/ + +#define fdt_get_header(fdt, field) \ + (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) +#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) +#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) +#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) +#define fdt_version(fdt) (fdt_get_header(fdt, version)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) + +#define __fdt_set_hdr(name) \ + static inline void fdt_set_##name(void *fdt, uint32_t val) \ + { \ + struct fdt_header *fdth = (struct fdt_header*)fdt; \ + fdth->name = cpu_to_fdt32(val); \ + } +__fdt_set_hdr(magic); +__fdt_set_hdr(totalsize); +__fdt_set_hdr(off_dt_struct); +__fdt_set_hdr(off_dt_strings); +__fdt_set_hdr(off_mem_rsvmap); +__fdt_set_hdr(version); +__fdt_set_hdr(last_comp_version); +__fdt_set_hdr(boot_cpuid_phys); +__fdt_set_hdr(size_dt_strings); +__fdt_set_hdr(size_dt_struct); +#undef __fdt_set_hdr + +/** + * fdt_check_header - sanity check a device tree or possible device tree + * @fdt: pointer to data which might be a flattened device tree + * + * fdt_check_header() checks that the given buffer contains what + * appears to be a flattened device tree with sane information in its + * header. + * + * returns: + * 0, if the buffer appears to contain a valid device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings, as above + */ +int fdt_check_header(const void *fdt); + +/** + * fdt_move - move a device tree around in memory + * @fdt: pointer to the device tree to move + * @buf: pointer to memory where the device is to be moved + * @bufsize: size of the memory space at buf + * + * fdt_move() relocates, if possible, the device tree blob located at + * fdt to the buffer at buf of size bufsize. The buffer may overlap + * with the existing device tree blob at fdt. Therefore, + * fdt_move(fdt, fdt, fdt_totalsize(fdt)) + * should always succeed. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_move(const void *fdt, void *buf, int bufsize); + +/**********************************************************************/ +/* Read-only functions */ +/**********************************************************************/ + +int fdt_check_full(const void *fdt, size_t bufsize); + +/** + * fdt_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * + * fdt_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds + */ +const char *fdt_string(const void *fdt, int stroffset); + +/** + * fdt_num_mem_rsv - retrieve the number of memory reserve map entries + * @fdt: pointer to the device tree blob + * + * Returns the number of entries in the device tree blob's memory + * reservation map. This does not include the terminating 0,0 entry + * or any other (0,0) entries reserved for expansion. + * + * returns: + * the number of entries + */ +int fdt_num_mem_rsv(const void *fdt); + +/** + * fdt_get_mem_rsv - retrieve one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: pointers to 64-bit variables + * + * On success, *address and *size will contain the address and size of + * the n-th reserve map entry from the device tree blob, in + * native-endian format. + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); + +/** + * fdt_subnode_offset_namelen - find a subnode based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_subnode_offset(), but only examine the first + * namelen characters of name for matching the subnode name. This is + * useful for finding subnodes based on a portion of a larger string, + * such as a full path. + */ +int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, + const char *name, int namelen); +/** + * fdt_subnode_offset - find a subnode of a given node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node at structure block + * offset parentoffset with the given name. name may include a unit + * address, in which case fdt_subnode_offset() will find the subnode + * with that unit address, or the unit address may be omitted, in + * which case fdt_subnode_offset() will find an arbitrary subnode + * whose name excluding unit address matches the given name. + * + * returns: + * structure block offset of the requested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); + +/** + * fdt_path_offset - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * + * fdt_path_offset() finds a node of a given path in the device tree. + * Each path component may omit the unit address portion, but the + * results of this are undefined if any such path component is + * ambiguous (that is if there are multiple nodes at the relevant + * level matching the given component, differentiated only by unit + * address). + * + * returns: + * structure block offset of the node with the requested path (>=0), on success + * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_NOTFOUND, if the requested node does not exist + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_path_offset(const void *fdt, const char *path); + +/** + * fdt_get_name - retrieve the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the starting node + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_name() retrieves the name (including unit address) of the + * device tree node at structure block offset nodeoffset. If lenp is + * non-NULL, the length of this name is also returned, in the integer + * pointed to by lenp. + * + * returns: + * pointer to the node's name, on success + * If lenp is non-NULL, *lenp contains the length of that name (>=0) + * NULL, on error + * if lenp is non-NULL *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); + +/** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** + * fdt_get_property_namelen - find a property based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_get_property_namelen(), but only examine the first + * namelen characters of name for matching the property name. + */ +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int nodeoffset, + const char *name, + int namelen, int *lenp); + +/** + * fdt_get_property - find a given property in a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property() retrieves a pointer to the fdt_property + * structure within the device tree blob corresponding to the property + * named 'name' of the node at offset nodeoffset. If lenp is + * non-NULL, the length of the property value is also returned, in the + * integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, + const char *name, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @ffset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); + +/** + * fdt_getprop_namelen - get property value based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_getprop(), but only examine the first namelen + * characters of name for matching the property name. + */ +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp); + +/** + * fdt_getprop - retrieve the value of a given property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline void *fdt_getprop_w(void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_get_phandle - retrieve the phandle of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the node + * + * fdt_get_phandle() retrieves the phandle of the device tree node at + * structure block offset nodeoffset. + * + * returns: + * the phandle of the node at nodeoffset, on success (!= 0, != -1) + * 0, if the node has no phandle, or another error occurs + */ +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); + +/** + * fdt_get_alias_namelen - get alias based on substring + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * @namelen: number of characters of name to consider + * + * Identical to fdt_get_alias(), but only examine the first namelen + * characters of name for matching the alias name. + */ +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen); + +/** + * fdt_get_alias - retrieve the path referenced by a given alias + * @fdt: pointer to the device tree blob + * @name: name of the alias to look up + * + * fdt_get_alias() retrieves the value of a given alias. That is, the + * value of the property named 'name' in the node /aliases. + * + * returns: + * a pointer to the expansion of the alias named 'name', if it exists + * NULL, if the given alias or the /aliases node does not exist + */ +const char *fdt_get_alias(const void *fdt, const char *name); + +/** + * fdt_get_path - determine the full path of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose path to find + * @buf: character buffer to contain the returned path (will be overwritten) + * @buflen: size of the character buffer at buf + * + * fdt_get_path() computes the full path of the node at offset + * nodeoffset, and records that path in the buffer at buf. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * 0, on success + * buf contains the absolute path of the node at + * nodeoffset, as a NUL-terminated string. + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) + * characters and will not fit in the given buffer. + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); + +/** + * fdt_supernode_atdepth_offset - find a specific ancestor of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * @supernodedepth: depth of the ancestor to find + * @nodedepth: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_supernode_atdepth_offset() finds an ancestor of the given node + * at a specific depth from the root (where the root itself has depth + * 0, its immediate subnodes depth 1 and so forth). So + * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); + * will always return 0, the offset of the root node. If the node at + * nodeoffset has depth D, then: + * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); + * will return nodeoffset itself. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + + * structure block offset of the node at node offset's ancestor + * of depth supernodedepth (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag +* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth); + +/** + * fdt_node_depth - find the depth of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_node_depth() finds the depth of a given node. The root node + * has depth 0, its immediate subnodes depth 1 and so forth. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * depth of the node at nodeoffset (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_depth(const void *fdt, int nodeoffset); + +/** + * fdt_parent_offset - find the parent of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_parent_offset() locates the parent node of a given node (that + * is, it finds the offset of the node which contains the node at + * nodeoffset as a subnode). + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset, *twice*. + * + * returns: + * structure block offset of the parent of the node at nodeoffset + * (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_parent_offset(const void *fdt, int nodeoffset); + +/** + * fdt_node_offset_by_prop_value - find nodes with a given property value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * + * fdt_node_offset_by_prop_value() returns the offset of the first + * node after startoffset, which has a property named propname whose + * value is of length proplen and has value equal to propval; or if + * startoffset is -1, the very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, + * propval, proplen); + * while (offset != -FDT_ERR_NOTFOUND) { + * ... other code here ... + * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, + * propval, proplen); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen); + +/** + * fdt_node_offset_by_phandle - find the node with a given phandle + * @fdt: pointer to the device tree blob + * @phandle: phandle value + * + * fdt_node_offset_by_phandle() returns the offset of the node + * which has the given phandle value. If there is more than one node + * in the tree with the given phandle (an invalid tree), results are + * undefined. + * + * returns: + * structure block offset of the located node (>= 0), on success + * -FDT_ERR_NOTFOUND, no node with that phandle exists + * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); + +/** + * fdt_node_check_compatible: check a node's compatible property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @compatible: string to match against + * + * + * fdt_node_check_compatible() returns 0 if the given node contains a + * 'compatible' property with the given string as one of its elements, + * it returns non-zero otherwise, or on error. + * + * returns: + * 0, if the node has a 'compatible' property listing the given string + * 1, if the node has a 'compatible' property, but it does not list + * the given string + * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property + * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible); + +/** + * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @compatible: 'compatible' string to match against + * + * fdt_node_offset_by_compatible() returns the offset of the first + * node after startoffset, which has a 'compatible' property which + * lists the given compatible string; or if startoffset is -1, the + * very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); + * while (offset != -FDT_ERR_NOTFOUND) { + * ... other code here ... + * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible); + +/** + * fdt_stringlist_contains - check a string list property for a string + * @strlist: Property containing a list of strings to check + * @listlen: Length of property + * @str: String to search for + * + * This is a utility function provided for convenience. The list contains + * one or more strings, each terminated by \0, as is found in a device tree + * "compatible" property. + * + * @return: 1 if the string is found in the list, 0 not found, or invalid list + */ +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); + +/**********************************************************************/ +/* Write-in-place functions */ +/**********************************************************************/ + +/** + * fdt_setprop_inplace - change a property's value, but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * fdt_setprop_inplace() replaces the value of a given property with + * the data in val, of length len. This function cannot change the + * size of a property, and so will only work if len is equal to the + * current length of the property. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if len is not equal to the property's current length + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to replace the property with + * + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_nop_property - replace a property with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_nop_property() will replace a given property's representation + * in the blob with FDT_NOP tags, effectively removing it from the + * tree. + * + * This function will alter only the bytes in the blob which contain + * the property, and will not alter or move any other part of the + * tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_property(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_nop_node - replace a node (subtree) with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_nop_node() will replace a given node's representation in the + * blob, including all its subnodes, if any, with FDT_NOP tags, + * effectively removing it from the tree. + * + * This function will alter only the bytes in the blob which contain + * the node and its properties and subnodes, and will not alter or + * move any other part of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Sequential write functions */ +/**********************************************************************/ + +int fdt_create(void *buf, int bufsize); +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); +int fdt_finish_reservemap(void *fdt); +int fdt_begin_node(void *fdt, const char *name); +int fdt_property(void *fdt, const char *name, const void *val, int len); +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} +#define fdt_property_string(fdt, name, str) \ + fdt_property(fdt, name, str, strlen(str)+1) +int fdt_end_node(void *fdt); +int fdt_finish(void *fdt); + +/**********************************************************************/ +/* Read-write functions */ +/**********************************************************************/ + +int fdt_create_empty_tree(void *buf, int bufsize); +int fdt_open_into(const void *fdt, void *buf, int bufsize); +int fdt_pack(void *fdt); + +/** + * fdt_add_mem_rsv - add one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: 64-bit values (native endian) + * + * Adds a reserve map entry to the given blob reserving a region at + * address address of length size. + * + * This function will insert data into the reserve map and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new reservation entry + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); + +/** + * fdt_del_mem_rsv - remove a memory reserve map entry + * @fdt: pointer to the device tree blob + * @n: entry to remove + * + * fdt_del_mem_rsv() removes the n-th memory reserve map entry from + * the blob. + * + * This function will delete data from the reservation table and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there + * are less than n+1 reserve map entries) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_mem_rsv(void *fdt, int n); + +/** + * fdt_set_name - change the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * @name: name to give the node + * + * fdt_set_name() replaces the name (including unit address, if any) + * of the given node with the given string. NOTE: this function can't + * efficiently check if the new name is unique amongst the given + * node's siblings; results are undefined if this function is invoked + * with a name equal to one of the given node's siblings. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob + * to contain the new name + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_set_name(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_setprop - create or change a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_setprop() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_u32 - set a property to a 32-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) + * + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_setprop_string - set a property to a string value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value for the property + * + * fdt_setprop_string() sets the value of the named property in the + * given node to the given string value (using the length of the + * string to determine the new length of the property), or creates a + * new property with that value if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_string(fdt, nodeoffset, name, str) \ + fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_u32 - append a 32-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_delprop - delete a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_del_property() will delete the given property. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_delprop(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_add_subnode_namelen - creates a new node based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_add_subnode(), but use only the first namelen + * characters of name as the name of the new node. This is useful for + * creating subnodes based on a portion of a larger string, such as a + * full path. + */ +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen); + +/** + * fdt_add_subnode - creates a new node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_add_subnode() creates a new node as a subnode of the node at + * structure block offset parentoffset, with the given name (which + * should include the unit address, if any). + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + + * returns: + * structure block offset of the created nodeequested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * fdt_del_node - delete a node (subtree) + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_del_node() will remove the given node, including all its + * subnodes if any, from the blob. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Debugging / informational functions */ +/**********************************************************************/ + +const char *fdt_strerror(int errval); + +struct fdt_region { + int offset; + int size; +}; + +/** + * fdt_find_regions() - find regions in device tree + * + * Given a list of nodes to include and properties to exclude, find + * the regions of the device tree which describe those included parts. + * + * The intent is to get a list of regions which will be invariant provided + * those parts are invariant. For example, if you request a list of regions + * for all nodes but exclude the property "data", then you will get the + * same region contents regardless of any change to "data" properties. + * + * This function can be used to produce a byte-stream to send to a hashing + * function to verify that critical parts of the FDT have not changed. + * + * Nodes which are given in 'inc' are included in the region list, as + * are the names of the immediate subnodes nodes (but not the properties + * or subnodes of those subnodes). + * + * For eaxample "/" means to include the root node, all root properties + * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter + * ensures that we capture the names of the subnodes. In a hashing situation + * it prevents the root node from changing at all Any change to non-excluded + * properties, names of subnodes or number of subnodes would be detected. + * + * When used with FITs this provides the ability to hash and sign parts of + * the FIT based on different configurations in the FIT. Then it is + * impossible to change anything about that configuration (include images + * attached to the configuration), but it may be possible to add new + * configurations, new images or new signatures within the existing + * framework. + * + * Adding new properties to a device tree may result in the string table + * being extended (if the new property names are different from those + * already added). This function can optionally include a region for + * the string table so that this can be part of the hash too. + * + * The device tree header is not included in the list. + * + * @fdt: Device tree to check + * @inc: List of node paths to included + * @inc_count: Number of node paths in list + * @exc_prop: List of properties names to exclude + * @exc_prop_count: Number of properties in exclude list + * @region: Returns list of regions + * @max_region: Maximum length of region list + * @path: Pointer to a temporary string for the function to use for + * building path names + * @path_len: Length of path, must be large enough to hold the longest + * path in the tree + * @add_string_tab: 1 to add a region for the string table + * @return number of regions in list. If this is >max_regions then the + * region array was exhausted. You should increase max_regions and try + * the call again. + */ +int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, + char * const exc_prop[], int exc_prop_count, + struct fdt_region region[], int max_regions, + char *path, int path_len, int add_string_tab); + +#endif /* _LIBFDT_H */ diff --git a/board/novatek/na51055/loader/Include/fdt/libfdt_env.h b/board/novatek/na51055/loader/Include/fdt/libfdt_env.h new file mode 100755 index 000000000000..5573b3f8c523 --- /dev/null +++ b/board/novatek/na51055/loader/Include/fdt/libfdt_env.h @@ -0,0 +1,63 @@ +/* + * libfdt - Flat Device Tree manipulation (build/run environment adaptation) + * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * Original version written by David Gibson, IBM Corporation. + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef _LIBFDT_ENV_H +#define _LIBFDT_ENV_H + +#include "compiler.h" + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +typedef __u8 uint8_t; +typedef __u16 uint16_t; +typedef __u32 uint32_t; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __u64 uint64_t; +typedef __u64 u_int64_t; +typedef __s64 int64_t; +#endif + +#define __bitwise + +typedef __u16 __bitwise __le16; +typedef __u16 __bitwise __be16; +typedef __u32 __bitwise __le32; +typedef __u32 __bitwise __be32; +#if defined(__GNUC__) +typedef __u64 __bitwise __le64; +typedef __u64 __bitwise __be64; +#endif + +extern struct fdt_header *working_fdt; /* Pointer to the working fdt */ + +typedef __be16 fdt16_t; +typedef __be32 fdt32_t; +typedef __be64 fdt64_t; + +#define fdt32_to_cpu(x) be32_to_cpu(x) +#define cpu_to_fdt32(x) cpu_to_be32(x) +#define fdt64_to_cpu(x) be64_to_cpu(x) +#define cpu_to_fdt64(x) cpu_to_be64(x) + +/* adding a ramdisk needs 0x44 bytes in version 2008.10 */ +#define FDT_RAMDISK_OVERHEAD 0x80 + +#endif /* _LIBFDT_ENV_H */ diff --git a/board/novatek/na51055/loader/Include/fuart.h b/board/novatek/na51055/loader/Include/fuart.h new file mode 100755 index 000000000000..82e8414e444d --- /dev/null +++ b/board/novatek/na51055/loader/Include/fuart.h @@ -0,0 +1,58 @@ +/** + Header file for UART + + This file is the header file for UART driver + + @file fuart.h + @ingroup mIIOUART + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + + +#ifndef _FUART_H +#define _FUART_H + +#include "constant.h" + +/** + @addtogroup mIIOUART +*/ +//@{ + +/** + @name Put system UART string + + Print string to UART + + @param[in] m printed string +*/ +//@{ +#define uart_putSystemUARTStr(m) fLib_PutSerialStr(m) ///< Print string MACRO +//@} + +/** + @name Put system UART character + + Print character to UART + + @param[in] m printed character +*/ +//@{ +#define uart_putSystemUARTChar(m) fLib_PutSerialChar(m) ///< Print character MACRO +//@} + +extern void fLib_PutSerialChar(char Ch) __attribute__ ((section (".part1"))); +extern void fLib_PutSerialStr(char *Str) __attribute__ ((section (".part1"))); +extern void uart_openSystemUART(void); +extern void uart_openSystemUART2(void); + +extern void uart_getChar_polling(char * c); +extern void uart_chkChar(char * c); +extern void uart_getStr_polling(char * c); +extern void uart_getBinary(char *pcString, UINT32 BufferLen); + +//@} + +#endif diff --git a/board/novatek/na51055/loader/Include/gic.h b/board/novatek/na51055/loader/Include/gic.h new file mode 100755 index 000000000000..e916c2c65cb0 --- /dev/null +++ b/board/novatek/na51055/loader/Include/gic.h @@ -0,0 +1,195 @@ + +#ifndef _ASM_ARMV8_GIC_H_ +#define _ASM_ARMV8_GIC_H_ +//#include "FLibARM.h" +#define UART_INTID 43 + + + +#define GIC_UART_INTID (UART_INTID + 32) +#if 0 +/* + * Distributor layout + */ +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_IGROUP 0x0080 +#define GICD_ISENABLE 0x0100 +#define GICD_ICENABLE 0x0180 +#define GICD_ISPEND 0x0200 +#define GICD_ICPEND 0x0280 +#define GICD_ISACTIVE 0x0300 +#define GICD_ICACTIVE 0x0380 +#define GICD_IPRIORITY 0x0400 +#define GICD_ITARGETS 0x0800 +#define GICD_ICFG 0x0c00 +#define GICD_PPISR 0x0d00 +#define GICD_SPISR 0x0d04 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGI 0x0f10 +#define GICD_SPENDSGI 0x0f20 +#define GICD_PIDR4 0x0fd0 +#define GICD_PIDR5 0x0fd4 +#define GICD_PIDR6 0x0fd8 +#define GICD_PIDR7 0x0fdc +#define GICD_PIDR0 0x0fe0 +#define GICD_PIDR1 0x0fe4 +#define GICD_PIDR2 0x0fe8 +#define GICD_PIDR3 0x0fec +#define GICD_CIDR0 0x0ff0 +#define GICD_CIDR1 0x0ff4 +#define GICD_CIDR2 0x0ff8 +#define GICD_CIDR3 0x0ffc + +/* + * CPU Interface layout + */ +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000c +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APR0 0x00d0 +#define GICC_NSAPR0 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 +#endif + +#define MAX_SPIS 480 + +#define MAX_PPIS 14 +#define MAX_SGIS 16 + +#define MIN_SGI_ID 0 +#define MIN_PPI_ID 16 +#define MIN_SPI_ID 32 + +#define GRP0 0 +#define GRP1 1 + +#define _GICD_ 0x1000 +#define _GICC_ 0x2000 +#define _GICH_ 0x4000 +#define _GICV_ 0x6000 + +#define GIC_PRI_MASK 0xff +#define GIC_HIGHEST_SEC_PRIORITY 0 +#define GIC_LOWEST_SEC_PRIORITY 127 +#define GIC_HIGHEST_NS_PRIORITY 128 +#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ +#define GIC_SPURIOUS_INTERRUPT 1023 +#define GIC_TARGET_CPU_MASK 0xff + +/* Distributor interface definitions */ +#define GICD_CTLR _GICD_ + 0x0 +#define GICD_TYPER _GICD_ + 0x4 +#define GICD_IGROUPR _GICD_ + 0x80 +#define GICD_ISENABLER _GICD_ + 0x100 +#define GICD_ICENABLER _GICD_ + 0x180 +#define GICD_ISPENDR _GICD_ + 0x200 +#define GICD_ICPENDR _GICD_ + 0x280 +#define GICD_ISACTIVER _GICD_ + 0x300 +#define GICD_ICACTIVER _GICD_ + 0x380 +#define GICD_IPRIORITYR _GICD_ + 0x400 +#define GICD_ITARGETSR _GICD_ + 0x800 +#define GICD_ICFGR _GICD_ + 0xC00 +#define GICD_SGIR _GICD_ + 0xF00 +#define GICD_CPENDSGIR _GICD_ + 0xF10 +#define GICD_SPENDSGIR _GICD_ + 0xF20 + +#define IGROUPR_SHIFT 5 +#define ISENABLER_SHIFT 5 +#define ICENABLER_SHIFT ISENABLER_SHIFT +#define ISPENDR_SHIFT 5 +#define ICPENDR_SHIFT ISPENDR_SHIFT +#define ISACTIVER_SHIFT 5 +#define ICACTIVER_SHIFT ISACTIVER_SHIFT +#define IPRIORITYR_SHIFT 2 +#define ITARGETSR_SHIFT 2 +#define ICFGR_SHIFT 4 +#define CPENDSGIR_SHIFT 2 +#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT + +/* GICD_TYPER bit definitions */ +#define IT_LINES_NO_MASK 0x1f + +/* GICD_ICFGR bit definitions */ +#define LEVEL_SENSITIVE 0x0 +#define TRIGGER_SENSITIVE 0x1 + +/* Physical CPU Interface registers */ +#define GICC_CTLR _GICC_ + 0x0 +#define GICC_PMR _GICC_ + 0x4 +#define GICC_BPR _GICC_ + 0x8 +#define GICC_IAR _GICC_ + 0xC +#define GICC_EOIR _GICC_ + 0x10 +#define GICC_RPR _GICC_ + 0x14 +#define GICC_HPPIR _GICC_ + 0x18 +#define GICC_AHPPIR _GICC_ + 0x28 +#define GICC_IIDR _GICC_ + 0xFC +#define GICC_DIR _GICC_ + 0x1000 +#define GICC_PRIODROP _GICC_ + GICC_EOIR + +/* GICC_CTLR bit definitions */ +#define EOI_MODE_NS (1 << 10) +#define EOI_MODE_S (1 << 9) +#define IRQ_BYP_DIS_GRP1 (1 << 8) +#define FIQ_BYP_DIS_GRP1 (1 << 7) +#define IRQ_BYP_DIS_GRP0 (1 << 6) +#define FIQ_BYP_DIS_GRP0 (1 << 5) +#define CBPR (1 << 4) +#define FIQ_EN (1 << 3) +#define ACK_CTL (1 << 2) +#define ENABLE_GRP1 (1 << 1) +#define ENABLE_GRP0 (1 << 0) + +/* GICC_IIDR bit masks and shifts */ +#define GICC_IIDR_PID_SHIFT 20 +#define GICC_IIDR_ARCH_SHIFT 16 +#define GICC_IIDR_REV_SHIFT 12 +#define GICC_IIDR_IMP_SHIFT 0 + +#define GICC_IIDR_PID_MASK 0xfff +#define GICC_IIDR_ARCH_MASK 0xf +#define GICC_IIDR_REV_MASK 0xf +#define GICC_IIDR_IMP_MASK 0xfff + +/* HYP view virtual CPU Interface registers */ +#define GICH_CTL 0x0 +#define GICH_VTR 0x4 +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_APR0 0xF0 +#define GICH_LR_BASE 0x100 + +/* Virtual CPU Interface registers */ +#define GICV_CTL 0x0 +#define GICV_PRIMASK 0x4 +#define GICV_BP 0x8 +#define GICV_INTACK 0xC +#define GICV_EOI 0x10 +#define GICV_RUNNINGPRI 0x14 +#define GICV_HIGHESTPEND 0x18 +#define GICV_DEACTIVATE 0x1000 + +extern void nvt_enable_irq(int number); +extern void nvt_disable_irq(int number); +extern void arm_gic_cpuif_setup(void); +extern void arm_gic_distif_setup(void); +extern void gicd_write_igroupr(UINT32 id, UINT32 val); +extern void gicd_write_ipriorityr(UINT32 id, UINT32 val); + +extern UINT32 gicc_get_IAR(void); +extern void gicc_set_EOIR(UINT32 val); + + + + +#endif /* _ASM_ARMV8_GIC_H_ */ diff --git a/board/novatek/na51055/loader/Include/global.h b/board/novatek/na51055/loader/Include/global.h new file mode 100755 index 000000000000..33257312f916 --- /dev/null +++ b/board/novatek/na51055/loader/Include/global.h @@ -0,0 +1,43 @@ +/** + Global utility header file + + Global utility header file + + @file global.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef _GLOBAL_H +#define _GLOBAL_H + +#include "constant.h" + +/** + @addtogroup mISYSUtil +*/ +//@{ + +extern UINT32 bitCount(UINT32 data); +extern void UTL_setDrvTmpBufferAddress(UINT32 addr); +extern UINT32 UTL_getDrvTmpBufferAddress(void); +extern char* Dec2HexStr(UINT32 data); +//extern void PrintDec2Hex(UINT32 data) __attribute__ ((section (".part1"))); +extern void rom_Dec2HexStr(UINT32 data) __attribute__ ((section (".part1"))); +#define PrintDec2Hex(m) rom_Dec2HexStr(m) +extern char* Dec2HexStr2Bytes(UINT32 data); +extern void PrintDec2HexStr2Bytes(UINT32 data) __attribute__ ((section (".part1"))); +extern UINT32 DecStr2Int(char* str); +extern BOOL UTL_canUpdateSecKey(void); +extern BOOL utl_is_sram_fw(UINT32 fw_addr); +extern void utl_test_checksum(UINT32 addr, UINT32 size); +extern void utl_dram_protect_enable(UINT32 addr, UINT32 size); +extern void utl_dram_protect_disable(void); +extern UINT32 utl_dram_protect_check(void); + +extern void load_dram_scan(UINT32 addr, UINT32 size) __attribute__ ((section (".dram_text"))); +extern void timer_delay(UINT32 US) __attribute__ ((section (".part1"))); + +//@} + +#endif diff --git a/board/novatek/na51055/loader/Include/limits.h b/board/novatek/na51055/loader/Include/limits.h new file mode 100755 index 000000000000..20a514867336 --- /dev/null +++ b/board/novatek/na51055/loader/Include/limits.h @@ -0,0 +1,31 @@ + + +#ifndef __NVT_LIBC_LIMITS_H +#define __NVT_LIBC_LIMITS_H + +#define CHAR_BIT 8 /* number of bits in a char */ +#define SCHAR_MIN (-128) /* minimum signed char value */ +#define SCHAR_MAX 127 /* maximum signed char value */ +#define UCHAR_MAX 0xff /* maximum unsigned char value */ + +#ifndef _CHAR_UNSIGNED +#define CHAR_MIN SCHAR_MIN /* mimimum char value */ +#define CHAR_MAX SCHAR_MAX /* maximum char value */ +#else +#define CHAR_MIN 0 +#define CHAR_MAX UCHAR_MAX +#endif /* _CHAR_UNSIGNED */ + +#define MB_LEN_MAX 2 /* max. # bytes in multibyte char */ +#define SHRT_MIN (-32768) /* minimum (signed) short value */ +#define SHRT_MAX 32767 /* maximum (signed) short value */ +#define USHRT_MAX 0xffff /* maximum unsigned short value */ +#define INT_MIN (-2147483647 - 1) /* minimum (signed) int value */ +#define INT_MAX 2147483647 /* maximum (signed) int value */ +#define UINT_MAX 0xffffffff /* maximum unsigned int value */ +#define LONG_MIN (-2147483647L - 1) /* minimum (signed) long value */ +#define LONG_MAX 2147483647L /* maximum (signed) long value */ +#define ULONG_MAX 0xffffffffUL /* maximum unsigned long value */ + +#endif + diff --git a/board/novatek/na51055/loader/Include/loader.h b/board/novatek/na51055/loader/Include/loader.h new file mode 100755 index 000000000000..2e480d112137 --- /dev/null +++ b/board/novatek/na51055/loader/Include/loader.h @@ -0,0 +1,83 @@ +/** + Global loader header file + + Global loader header file + + @file loader.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef _LOADER_H +#define _LOADER_H + +#include "constant.h" +#include "StorageDef.h" + +/** + @name Special key detect CallBack + + Special key detect Prototype + + Project layer can detect special key in this callback. + If callback returns TRUE, loader will try to find files on SD card. + + @return + - @b TRUE: special key is pressed + - @b FALSE: special key is NOT pressed +*/ +//@{ +typedef BOOL (*LDR_SPECIAL_KEY_CB)(void); +//@} + +/** + @name Card detect CallBack + + Card detect Prototype + + Project layer can detect SD card existence in this callback. + If callback returns TRUE, loader will consider SD is plugged + + @return + - @b TRUE: SD exist + - @b FALSE: SD NOT exist +*/ +//@{ +typedef BOOL (*LDR_CARD_DETECT_CB)(void); +//@} +/** + @name Recovery Trigger CallBack + + Recovery trigger Prototype + + Project layer can detect if the recovery flow should started. + If callback returns TRUE, recovery flow will start. + + @return + - @b TRUE: Recovery flow is triggered. + - @b FALSE: Recovery flow is NOT triggered. +*/ +//@{ +typedef BOOL (*LDR_RECOVERY_TRIGGER_CB)(void); +//@} + +typedef enum _STORAGEINT { + STORAGEINT_UNOKNOWN, + STORAGEINT_SPI_NAND, + STORAGEINT_SPI_NOR, + STORAGEINT_EMMC, +} STORAGEINT; + +extern void loader_setUpdateFwName(char* fileName); +extern void loader_setUpdateLdrName(char* fileName); +extern void loader_setRunFwName(char* fileName); +extern void loader_setRecoveryFwName(char *fileName); +extern void loader_setRecoveryPartitionID(UINT32 partition_id); +extern void loader_setVersion(UINT32 version); +extern void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj); +extern void loader_installSpecialKeyCB(LDR_SPECIAL_KEY_CB callback); +extern void loader_installCardDetectCB(LDR_CARD_DETECT_CB callback); +extern void loader_installRecoveryTriggerCB(LDR_RECOVERY_TRIGGER_CB callback); + +#endif + diff --git a/board/novatek/na51055/loader/Include/lz.h b/board/novatek/na51055/loader/Include/lz.h new file mode 100755 index 000000000000..574d9d22c1a3 --- /dev/null +++ b/board/novatek/na51055/loader/Include/lz.h @@ -0,0 +1,25 @@ +/** + Decompress library header file + + Decompress library header file + + @file lz.h + @ingroup mISYSUtil + @note Nothing +*/ +#ifndef __NVT_LZ_DEF__ +#define __NVT_LZ_DEF__ + +#include "constant.h" + +/** + @addtogroup mISYSUtil +*/ +//@{ + +extern unsigned int LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize) __attribute__ ((section (".part1"))); +//extern void LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize) __attribute__ ((section (".part1"), far)); + +//@} + +#endif diff --git a/board/novatek/na51055/loader/Include/modelext/bin_info.h b/board/novatek/na51055/loader/Include/modelext/bin_info.h new file mode 100755 index 000000000000..a864df4f04b6 --- /dev/null +++ b/board/novatek/na51055/loader/Include/modelext/bin_info.h @@ -0,0 +1,191 @@ +/** + Bin File Information + + Bin file layout + + ----------------------------------------------------- + HEADINFO 0x00 ~ 0x80 = 128 bytes = 32 WORDS + ----------------------------------------------------- + + EXCEPTION_TABLE: 0x180 ~ 0x200 = 128 bytes = 32 WORDS (see exception_MIPS.s) + + ----------------------------------------------------- + + VECTOR_TABLE: 0x200 ~ 0x2f0 = 240 bytes = 60 WORDS (see isr_MIPS.s) + + ----------------------------------------------------- + + Code Info: 0x2f0 ~ 0x400 = 272 bytes = 68 WORDS (see CodeInfo_MIPS.s) + + ----------------------------------------------------- + + Code Entry: 0x400 (see Loader_MIPS.s) + + : + + PART-1 + PART-2 + PART-3 + : + PART-N + + ----------------------------------------------------- + + @file bin_info.h + @ingroup mMODELEXT + @note THESE STRUCTS ARE VERY VERY IMPORTANT FORMAT DEFINITION OF SYSTEM, + DO NOT MODIFY ANY ITEM OR INSERT/REMOVE ANY ITEM OF THESE STRUCTS!!! + + Copyright Novatek Microelectronics Corp. 2011. All rights reserved. +*/ +#ifndef _BINI_NFO_H +#define _BINI_NFO_H + +#define BIN_INFO_VER 0x19062115 ///< YYYY/MM/DD HH +#if UITRON_FW +#define BIN_INFO_OFFSET_RTOS 0x00000100 ///< uITRON HEADINFO.o attached to this offset +#else +#define BIN_INFO_OFFSET_RTOS 0x00000200 ///< uITRON HEADINFO.o attached to this offset +#endif +#define BIN_INFO_OFFSET_UBOOT 0x00000300 ///< uboot HEADINFO.o attached to this +#define BIN_INFO_OFFSET_NUTTX 0x00000100 ///< nuttx +#define BIN_INFO_OFFSET_TEEOS 0x00000100 ///< teeos + +//Ep: Encryption Program (CheckSum version) +//Epcrc: Encryption Program (CRC version) +//Bfc: Bin File Compress +//Ld: Loader +//Fw: Firmware + +//Head control flag for HEADINFO.BinCtrl +#define HDCF_LZCOMPRESS_EN 0x0000001 ///< BIT 0.compressed enable (0=no,1=yes) + +/** + @name Ld control flag for LDINFO.LdCtrl +*/ +//@{ +#define BOOT_FLAG_PARTLOAD_EN 0x0000001 ///< BIT 0.PARTLOAD_EN (0=no,1=yes) +//@} + +//HEADINFO::Resv field definition +typedef enum _HEADINFO_RESV_IDX_{ + HEADINFO_RESV_IDX_FDT_ADDR = 0, + HEADINFO_RESV_IDX_SHM_ADDR = 1, + HEADINFO_RESV_IDX_BOOT_FLAG = 2, + HEADINFO_RESV_IDX_COUNTS = 19, +} HEADINFO_RESV_IDX; + +//HEADINFO::Resv field definition for teeos +typedef enum HEADINFO_TEEOS_RESV_IDX{ + HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR = 0, + HEADINFO_TEEOS_RESV_IDX_UBOOT_ADDR = 1, //< write by loader + HEADINFO_TEEOS_RESV_IDX_COUNTS = 19, +} HEADINFO_TEEOS_RESV_IDX; + +/** + Header information + + 0x00 ~ 0x80 = 128 bytes = 32 WORDS +*/ +typedef struct HEADINFO { + unsigned int CodeEntry; ///< [0x00] fw CODE entry (4) ----- r by Ld + unsigned int Resv1[HEADINFO_RESV_IDX_COUNTS]; + ///< [0x04~0x50] reserved (4*19) -- reserved, its mem value will filled by Ld + ///< Resv1[HEADINFO_RESV_IDX_FDT_ADDR]: store fdt addr for rtos + ///< Resv1[HEADINFO_RESV_IDX_SHM_ADDR]: store shm addr for rtos + ///< Resv1[HEADINFO_RESV_IDX_BOOT_FLAG]: boot flag for rtos + char BinInfo_1[8]; ///< [0x50~0x58] CHIP-NAME (8) ---- r by Ep + char BinInfo_2[8]; ///< [0x58~0x60] SDK version (8) + char BinInfo_3[8]; ///< [0x60~0x68] SDK releasedate (8) + unsigned int BinLength; ///< [0x68] Bin File Length (4) --- w by Ep/bfc + unsigned int Checksum; ///< [0x6c] Check Sum or CRC (4) ----- w by Ep/Epcrc + unsigned int CRCLenCheck; ///< [0x70~0x74] Length check for CRC (4) ----- w by Epcrc (total len ^ 0xAA55) + unsigned int ModelextAddr;///< [0x74~0x78] where modelext data is. w by Ld / u-boot + unsigned int BinCtrl; ///< [0x78~0x7C] Bin flag (4) --- w by bfc + ///< BIT 0.compressed enable (w by bfc) + ///< BIT 1.Linux SMP enable (1: SMP/VOS, 0: Dual OS) + unsigned int CRCBinaryTag;///< [0x7C~0x80] Binary Tag for CRC (4) ----- w by Epcrc (0xAA55 + "NT") +} +HEADINFO; + +STATIC_ASSERT(sizeof(HEADINFO) == 128); + + +/** + Loader information + + 0x80 ~ 0xc0 = 64 bytes = 16 WORDS +*/ +typedef struct _LDINFO { + char LdInfo_1[16]; ///< [0x80~0x90] LD-NAME(16) ------ w by Ld + UINT32 LdCtrl; ///< [0x90] Fw flag (4) ----------- r by Ld + ///< BIT 0.enable part-load (0=full load,1=part load) + UINT32 LdCtrl2; ///< [0x94] Ld flag (4) ----------- w by Ld + ///< BIT 0.UPDATE_FW (0=no,1=yes) + ///< BIT 1.UPDATE_LOADER (0=no,1=yes) + ///< BIT 2.BOOT_CARD (0=no,1=yes) + ///< BIT 3.BOOT_FLASH (0=no,1=yes) + ///< BIT 4.UPDATE_CAL (0=no,1=yes) + ///< BIT 8.UPDATE_FW_DONE (0=no,1=yes) + //< BIT 9.BOOT FROM S3 STATE (0=no,1=yes) + UINT32 LdLoadSize; ///< [0x98] Ld load size (4) ------ w by Ld (NOTE: this value must be block size align) + UINT32 LdLoadTime; ///< [0x9c] Ld exec time(us) (4) -- w by Ld + UINT32 LdResvSize; ///< [0xa0] Ld size (by bytes, reserved size in partition) (4) ------ w by Ld + UINT32 FWResvSize; ///< [0xa4] FW reserved size (4) ------ w by Ld + UINT16 LdPackage; ///< [0xa8] IC package expected by Ld (0xFF: ES, 0: 660, 3: 663, 5: 665, etc...) + UINT16 LdStorage; ///< [0xaa] Internal storage expected by Ld (0: unkown, 1: nand, 2: spi nand, 3: spi nor) + UINT32 Resv[5]; ///< [0xac~0xc0] (4*5) ------------ reserved for project Ld +} +LDINFO; + +STATIC_ASSERT(sizeof(LDINFO) == 64); +/** + Binary file information + + 0x00 ~ 0x180 = 384 bytes = 96 WORDS +*/ +typedef struct _BININFO { + HEADINFO head; ///< 0x00 ~ 0x80 = 128 bytes = 32 WORDS, header information + LDINFO ld; ///< 0x80 ~ 0xc0 = 64 bytes = 16 WORDS, loader information + unsigned int Resv[48]; ///< 0x80 ~ 0x180 = 384 bytes = 64 WORDS, reserved information +} +BININFO; + +STATIC_ASSERT(sizeof(BININFO) == 384); + +/////////////////////////////////////////////////////////////////////////////// +//Code Info: 0x2f0 ~ 0x400 +#if UITRON_FW +#define ZI_SECTION_OFFSET (0x2f0+0x10) ///< ZI area information of starting offset //cliff +#define CODE_SECTION_OFFSET (0x2f0+0x18) ///< code section information of starting offset //cliff + +/////////////////////////////////////////////////////////////////////////////// +//Code Entry: 0x0 ~ +#define CODE_ENTRY_OFFSET (0x0) ///< code entry starting offset (660/510 is 0x400, 680 is 0x0) //cliff +#else +#define ZI_SECTION_OFFSET (0x3f0+0x10) ///< ZI area information of starting offset +#define CODE_SECTION_OFFSET (0x3f0+0x18) ///< code section information of starting offset + +#endif +/* +bfc syntex + +bfc.exe p1 p2 p3 p4 p5 p6 p7 p8 p9 + +p1: compress/decompress +p2: compress method +p3: input file name +p4: output file name +p5: partial load flag ('1' means partial load) +p6: partial load file start [locate offset of bin file] +p7: output binary file length [locate offset of bin file] +p8: partial compress flag [locate offset of bin file] +p9: NAND block size (option) + +NOTE: p6~p9 must be hex format (0x****) + +@$(BFC) c lz $(BIN_R) tmp 1 0x310 0x68 0x78 $(EMBMEM_BLK_SIZE) +*/ + +#endif + diff --git a/board/novatek/na51055/loader/Include/modelext/dram_partition_info.h b/board/novatek/na51055/loader/Include/modelext/dram_partition_info.h new file mode 100755 index 000000000000..0441da45bd93 --- /dev/null +++ b/board/novatek/na51055/loader/Include/modelext/dram_partition_info.h @@ -0,0 +1,55 @@ +#ifndef _DRAM_PARTITION_INFO_H +#define _DRAM_PARTITION_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#else +#include "nvt_type.h" +#endif + +/** + DRAM Partition + + This is common header used between firmware of uITRON, eCos, Linux, DSP + so !!!!!! DO NOT modify it !!!!!! +*/ + +#define DRAM_PARTITION_INFO_VER 0x17032309 ///< YYYY/MM/DD HH + +typedef struct _DRAM_PARTITION { + unsigned int fourcc; ///< FourCC DRAM + unsigned int info_size; ///< sizeof(CORE_INFO) + unsigned int dram_addr; ///< whole dram starting address + unsigned int dram_size; ///< whole dram size + unsigned int rev_addr; ///< reversed starting address + unsigned int rev_size; ///< reversed size + unsigned int fdt_addr; ///< ipc starting address + unsigned int fdt_size; ///< ipc size + unsigned int linux_addr;///< linux-kernel starting address + unsigned int linux_size;///< linux-kernel size + unsigned int uboot_addr;///< u-boot starting address + unsigned int uboot_size;///< u-boot size + unsigned int rtos_addr; ///< rtos starting address + unsigned int rtos_size; ///< rtos size + unsigned int dsp1_addr; ///< DSP1 starting address + unsigned int dsp1_size; ///< DSP1 size + unsigned int dsp2_addr; ///< ecos(na51023) / DSP2(na51000) starting address + unsigned int dsp2_size; ///< ecos(na51023) / DSP2(na51000) size + unsigned int loader_addr; ///< loader starting address + unsigned int loader_size; ///< loader size + unsigned int nuttx_addr; ///< nuttx starting address + unsigned int nuttx_size; ///< nuttx size + unsigned int teeos_addr; ///< teeos starting address + unsigned int teeos_size; ///< teeos size + unsigned int hdal1_addr; ///< hdal[0] starting address + unsigned int hdal1_size; ///< hdal[0] size + unsigned int hdal2_addr; ///< hdal[1] starting address for dram2 + unsigned int hdal2_size; ///< hdal[1] size for dram2 + unsigned int core2_entry1_addr; ///< for smp boot, cpu2 start at 0 then jump to core2_entry2 for addr 0 can be reuse. + unsigned int core2_entry1_size; ///< for smp boot, cpu2 start at 0 then jump to core2_entry2 for addr 0 can be reuse. + unsigned int core2_entry2_addr; ///< asm code to start smp + unsigned int core2_entry2_size; ///< asm code to start smp + +}DRAM_PARTITION; + +#endif \ No newline at end of file diff --git a/board/novatek/na51055/loader/Include/modelext/emb_partition_info.h b/board/novatek/na51055/loader/Include/modelext/emb_partition_info.h new file mode 100755 index 000000000000..cd968cab7e8a --- /dev/null +++ b/board/novatek/na51055/loader/Include/modelext/emb_partition_info.h @@ -0,0 +1,56 @@ +#ifndef _EMB_PARTITION_INFO_H +#define _EMB_PARTITION_INFO_H + +#define EMB_PARTITION_INFO_VER 0x16072117 ///< YYYY/MM/DD HH + +/** + Partition Infomation + This is common header used between firmware of uITRON, eCos, Linux, DSP + so !!!!!! DO NOT modify it !!!!!! +*/ + +#define EMB_PARTITION_INFO_COUNT 16 + +#define EMBTYPE_UNKNOWN 0x00 +#define EMBTYPE_LOADER 0x01 /* loader must always put in partition[0] */ +#define EMBTYPE_MODELEXT 0x02 /* modelext must always put in partition[1] */ +#define EMBTYPE_UITRON 0x03 +#define EMBTYPE_ECOS 0x04 +#define EMBTYPE_UBOOT 0x05 +#define EMBTYPE_LINUX 0x06 +#define EMBTYPE_DSP 0x07 +#define EMBTYPE_PSTORE 0x08 +#define EMBTYPE_FAT 0x09 +#define EMBTYPE_EXFAT 0x0A +#define EMBTYPE_ROOTFS 0x0B +#define EMBTYPE_RAMFS 0x0C +#define EMBTYPE_UENV 0x0D /* u-boot environment data */ +#define EMBTYPE_MBR 0x0E /* for emmc partition, mbr always put in partition[0] instead of loader */ +#define EMBTYPE_NUTTX 0x0F +#define EMBTYPE_RTOS 0x10 +#define EMBTYPE_TEEOS 0x11 + +/** + customer defined data partition format +*/ +#define EMBTYPE_USER0 0x80 +#define EMBTYPE_USER1 0x81 +#define EMBTYPE_USER2 0x82 +#define EMBTYPE_USER3 0x83 +#define EMBTYPE_USER4 0x84 +#define EMBTYPE_USER5 0x85 +#define EMBTYPE_USER6 0x86 +#define EMBTYPE_USER7 0x87 + + +/* for reason of compatiable linux, we use original type to decalre */ + +typedef struct _EMB_PARTITION { + unsigned short EmbType; /* EMBTYPE_ */ + unsigned short OrderIdx; /* Order index of the same EmbType based on '0' */ + unsigned long long PartitionOffset; /* Phyical offset of partition */ + unsigned long long PartitionSize; /* Size of this partition */ + unsigned long long ReversedSize; /* Reserved size for bad block */ +} EMB_PARTITION, *PEMB_PARTITION; + +#endif diff --git a/board/novatek/na51055/loader/Include/modelext/gpio_info.h b/board/novatek/na51055/loader/Include/modelext/gpio_info.h new file mode 100755 index 000000000000..7a49e37cd60c --- /dev/null +++ b/board/novatek/na51055/loader/Include/modelext/gpio_info.h @@ -0,0 +1,42 @@ +/** + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. + + @file gpio_info.h + @ingroup mMODELEXT + + @brief Header file of IO config + This file is the header file of IO config + + @note Nothing. + @date 2016/06/24 +*/ + +/** \addtogroup mIPRJAPCommonIO */ +//@{ + +#ifndef _GPIO_INFO_H +#define _GPIO_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#else +#include "nvt_type.h" +#endif + +#define GPIO_INFO_VER 0x16062414 ///< YYYY/MM/DD HH + + +//-------------------------------------------------------------------- +// GPIO common +//-------------------------------------------------------------------- +typedef struct _GPIO_INIT_OBJ{ + UINT32 GpioPin; + UINT32 GpioDir; + UINT32 PadDir; + UINT32 PadPin; +} GPIO_INIT_OBJ,*PGPIO_INIT_OBJ; + +#endif + +//@} + diff --git a/board/novatek/na51055/loader/Include/modelext/interrupt.h b/board/novatek/na51055/loader/Include/modelext/interrupt.h new file mode 100755 index 000000000000..c5c2e20db2f8 --- /dev/null +++ b/board/novatek/na51055/loader/Include/modelext/interrupt.h @@ -0,0 +1,764 @@ +/** + Header file for Interrupt module + + This file is the header file that define the API for Interrupt module. + + @file Interrupt.h + @ingroup mIDrvSys_Interrupt + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2010. All rights reserved. +*/ + +#ifndef _INTERRUPT_H +#define _INTERRUPT_H + +#if defined(__UITRON) +#include "Type.h" +#include "cc.h" +#else +#include "nvt_type.h" +#include "modelext/cc.h" +#define _ARM_GIC_USAGE_ ENABLE +#endif + +// Interrupt number <= 32 +//typedef UINT32 INT_PTN; +// Interrupt number > 32 +typedef UINT64 INT_PTN; + +/** + @addtogroup mIDrvSys_Interrupt +*/ +//@{ +#define INT_GIC_ID_DST_VER 0x16080216 + + +/** + Interrupt configuration identifier + + @note For int_setConfig() +*/ +typedef enum +{ + INT_CONFIG_ID_GIC_DESTINATION = 0, ///< Configured Interrupt exception destination to CPU/CPU2 + ///< @note + ///< Context is : + ///< - @b PINT_ID_GIC_DST : Point of destination table + + INT_CONFIG_ID_INTC_DESTINATION, ///< Configured Interrupt exception destination to DSP/DSP2 + ///< @note + ///< Context is : + ///< - @b PINT_ID_INTC_DST : Point of destination table + + + + ENUM_DUMMY4WORD(INT_CONFIG_ID) +} INT_CONFIG_ID; + +/** + Interrupt module ID + + Interrupt module ID for int_getIRQId() and int_getDummyId(). +*/ +#if(_ARM_GIC_USAGE_ == DISABLE) +#define INT_GIC_SPI_START_ID 0 +#else +#define INT_GIC_SPI_START_ID 32 +#endif + +typedef enum +{ + INT_ID_TIMER = INT_GIC_SPI_START_ID, + INT_ID_SIE, + INT_ID_SIE2, + INT_ID_SIE3, + + INT_ID_SIE4, + INT_ID_IPE, + INT_ID_IME, + INT_ID_DCE, + + INT_ID_IFE, + INT_ID_IFE2, + INT_ID_DIS, + INT_ID_FDE, + +// INT_ID_RDE, //Removed @ NT96680 + INT_ID_ETH_LPI, //Ethernet_LPI + INT_ID_RHE, + INT_ID_DRE, + INT_ID_DAI, //15 + + INT_ID_H26X, + INT_ID_JPEG, + INT_ID_GRAPHIC, + INT_ID_GRAPHIC2, + + INT_ID_AFFINE, + INT_ID_ISE, + INT_ID_TGE, + INT_ID_TSMUX, + + INT_ID_GPIO, + INT_ID_REMOTE, + INT_ID_PWM, + INT_ID_USB, + + INT_ID_USB3, + INT_ID_NAND, + INT_ID_SDIO, + INT_ID_SDIO2, //31 + + INT_ID_SDIO3, + INT_ID_DMA, + INT_ID_ETHERNET, + INT_ID_SPI, + + INT_ID_SPI2, + INT_ID_SPI3, + INT_ID_SPI4, +// INT_ID_SPI5, //Removed @ NT96680 + INT_ID_ETH_REV_MII, //Ethernet_RevMII + + INT_ID_SIF, + INT_ID_I2C, + INT_ID_I2C2, + INT_ID_UART, //43 + + INT_ID_UART2, + INT_ID_UART3, + INT_ID_UART4, + INT_ID_ADC, + + INT_ID_IDE, + INT_ID_IDE2, + INT_ID_DSI, + INT_ID_MI, //51 + + INT_ID_HDMI, +// INT_ID_VX1, //Removed @ NT96680 + INT_ID_DMA2, //New @ NT96680 + INT_ID_LVDS, + INT_ID_LVDS2, //55 + + INT_ID_RTC, + INT_ID_WDT, + INT_ID_CG, + INT_ID_CC, //59 + + INT_ID_I2C3, //60 +// New add @ NT96680 + INT_ID_SLVS_EC, + INT_ID_LVDS3, //share with HiSPi3/CSI3 + INT_ID_LVDS4, //share with HiSPi4/CSI4 + + INT_ID_LVDS5, //share with HiSPi5/CSI5 + INT_ID_LVDS6, //share with HiSPi6/CSI6 + INT_ID_LVDS7, //share with HiSPi7/CSI7 + INT_ID_LVDS8, //share with HiSPi8/CSI8 + + INT_ID_SIE5, + INT_ID_SIE6, + INT_ID_SIE7, + INT_ID_SIE8, + + INT_ID_IVE, + INT_ID_SVM, + INT_ID_SDE, + INT_ID_CNN, //75 + + INT_ID_DSP, + INT_ID_DSP2, + INT_ID_CANBUS, + INT_ID_CRYPTO, //79 + + INT_ID_COPY, + INT_ID_ROTATE, + INT_ID_I2C4, + INT_ID_I2C5, //83 + +// INT_ID_I2C6, +// INT_ID_I2C7, + INT_ID_DRTC, + INT_ID_ISE2, + INT_ID_TIMER2, + INT_ID_GPIO2, //87 + + INT_ID_PWM2, + INT_ID_CC2, //89 + INT_ID_SIF2, + + INT_ID_DSP_2, + INT_ID_DSP_2_2, + INT_ID_TSDEMUX, //93 + + INT_ID_CNT, + INT_ID_MAX = INT_ID_CNT - INT_GIC_SPI_START_ID, //94 + + + INT_ID_WFI = 229, + INT_ID_GIC_TOTAL = 256, + ENUM_DUMMY4WORD(INT_ID) +} INT_ID; + +typedef enum +{ + INT_TARGET_CORE0 = 1, + INT_TARGET_CORE1, + ENUM_DUMMY4WORD(INT_CORE_ID) +} INT_CORE_ID; + +/* + Interrupt module ID of GIC + + Indicate which core will configured as destination + + @note For DMA_WRITEPROT_ATTR +*/ + + +typedef union +{ + INT_PTN Reg[2]; + struct + { + //INT0 + UINT32 bInt_ID_TIMER:1; + UINT32 bInt_ID_SIE:1; + UINT32 bInt_ID_SIE2:1; + UINT32 bInt_ID_SIE3:1; + + UINT32 bInt_ID_SIE4:1; + UINT32 bInt_ID_IPE:1; + UINT32 bInt_ID_IME:1; + UINT32 bInt_ID_DCE:1; + + UINT32 bInt_ID_IFE:1; + UINT32 bInt_ID_IFE2:1; + UINT32 bInt_ID_DIS:1; + UINT32 bInt_ID_FDE:1; + +// UINT32 bInt_ID_RDE:1; + UINT32 bInt_ID_Ethernet_LPI:1; + UINT32 bInt_ID_RHE:1; + UINT32 bInt_ID_DRE:1; + UINT32 bInt_ID_DAI:1; + + + //INT16 + UINT32 bInt_ID_H264:1; + UINT32 bInt_ID_JPEG:1; + UINT32 bInt_ID_GRAPHIC:1; + UINT32 bInt_ID_GRAPHIC2:1; + + UINT32 bInt_ID_AFFINE:1; + UINT32 bInt_ID_ISE:1; + UINT32 bInt_ID_TGE:1; + UINT32 bInt_ID_TSMUX:1; + + UINT32 bInt_ID_GPIO:1; + UINT32 bInt_ID_REMOTE:1; + UINT32 bInt_ID_PWM:1; + UINT32 bInt_ID_USB:1; + + UINT32 bInt_ID_USB3:1; + UINT32 bInt_ID_NAND:1; + UINT32 bInt_ID_SDIO:1; + UINT32 bInt_ID_SDIO2:1; + + //INT32 + UINT32 bInt_ID_SDIO3:1; + UINT32 bInt_ID_DMA:1; + UINT32 bInt_ID_ETHERNET:1; + UINT32 bInt_ID_SPI:1; + + UINT32 bInt_ID_SPI2:1; + UINT32 bInt_ID_SPI3:1; + UINT32 bInt_ID_SPI4:1; + UINT32 bInt_ID_Ehternet_RevMII:1; +// UINT32 bInt_ID_SPI5:1; + + + UINT32 bInt_ID_SIF:1; + UINT32 bInt_ID_I2C:1; + UINT32 bInt_ID_I2C2:1; + UINT32 bInt_ID_UART:1; + + UINT32 bInt_ID_UART2:1; + UINT32 bInt_ID_UART3:1; + UINT32 bInt_ID_UART4:1; + UINT32 bInt_ID_ADC:1; + + //INT48 + UINT32 bInt_ID_IDE:1; + UINT32 bInt_ID_IDE2:1; + UINT32 bInt_ID_DSI:1; + UINT32 bInt_ID_MI:1; + + //INT52 + UINT32 bInt_ID_HDMI:1; +// UINT32 bInt_ID_VX1:1; + UINT32 bInt_ID_DMA2:1; + UINT32 bInt_ID_LVDS:1; // LVDS& HiSPI& CSI + UINT32 bInt_ID_LVDS2:1; //LVDS2&HiSPI2&CSI2 + + //INT56 + UINT32 bInt_ID_RTC:1; + UINT32 bInt_ID_WDT:1; + UINT32 bInt_ID_CG:1; + UINT32 bInt_ID_CC:1; + + //INT60 + UINT32 bInt_ID_I2C3:1; + UINT32 bInt_ID_SLVS_EC:1; + UINT32 bInt_ID_LVDS3:1; //LVDS3&HiSPI3&CSI3 + UINT32 bInt_ID_LVDS4:1; //LVDS4&HiSPI4&CSI4 + + //INT64 + UINT32 bInt_ID_LVDS5:1; //LVDS5&HiSPI5&CSI5 + UINT32 bInt_ID_LVDS6:1; //LVDS6&HiSPI6&CSI6 + UINT32 bInt_ID_LVDS7:1; //LVDS7&HiSPI7&CSI7 + UINT32 bInt_ID_LVDS8:1; //LVDS8&HiSPI8&CSI8 + + //INT68 + UINT32 bInt_ID_SIE5:1; + UINT32 bInt_ID_SIE6:1; + UINT32 bInt_ID_SIE7:1; + UINT32 bInt_ID_SIE8:1; + + //INT72 + UINT32 bInt_ID_IVE:1; + UINT32 bInt_ID_SVM:1; + UINT32 bInt_ID_SDE:1; + UINT32 bInt_ID_CNN:1; + + //INT76 + UINT32 bInt_ID_DSP:1; + UINT32 bInt_ID_DSP2:1; + UINT32 bInt_ID_CANBUS:1; + UINT32 bInt_ID_CRYPTO:1; + + //INT80 + UINT32 bInt_ID_HWCOPY:1; + UINT32 bInt_ID_ROTATE:1; + UINT32 bInt_ID_I2C4:1; + UINT32 bInt_ID_I2C5:1; + + //INT84 + UINT32 bInt_ID_I2C6:1; + UINT32 bInt_ID_I2C7:1; + UINT32 bInt_ID_TIMER2:1; //Timer to CA53 core2 + UINT32 bInt_ID_GPIO2:1; //GPIO to CA53 core2 + + //INT88 + UINT32 bInt_ID_PWM2:1; + UINT32 bInt_ID_CC2:1; + UINT32 bInt_ID_SIF2:1; //Timer to CA53 core2 + UINT32 bInt_ID_DSP_2:1; //?? + + //INT92 + UINT32 bInt_ID_DSP2_2:1; //?? + UINT32 bInt_ID_TMDEMUX:1; + UINT32 bReserved92:2; + //INT96 => 4 + UINT32 bReserved96:4; + //INT100=> 4 + UINT32 bReserved100:4; + //INT104=> 4 + UINT32 bReserved104:4; + //INT108=> 4 + UINT32 bReserved108:4; + //INT112=> 4 + UINT32 bReserved112:4; + //INT116=> 4 + UINT32 bReserved116:4; + //INT120=> 4 + UINT32 bReserved120:4; + //INT124=> 4 + UINT32 bReserved124:4; + }Bit; +} INT_GIC_ID_DST, *PINT_GIC_ID_DST; + +/* + Interrupt module ID of INTC + + Indicate which core will configured as destination + + @note For DMA_WRITEPROT_ATTR +*/ + + +typedef union +{ + INT_PTN Reg[2]; + struct + { + //INT0 + UINT32 bInt_ID_TIMER:1; + UINT32 bInt_ID_SIE:1; + UINT32 bInt_ID_SIE2:1; + UINT32 bInt_ID_SIE3:1; + + UINT32 bInt_ID_SIE4:1; + UINT32 bInt_ID_IPE:1; + UINT32 bInt_ID_IME:1; + UINT32 bInt_ID_DCE:1; + + UINT32 bInt_ID_IFE:1; + UINT32 bInt_ID_IFE2:1; + UINT32 bInt_ID_DIS:1; + UINT32 bInt_ID_FDE:1; + + //INT12 + UINT32 bReserved12:1; + UINT32 bInt_ID_RHE:1; + UINT32 bInt_ID_DRE:1; + UINT32 bInt_ID_DAI:1; + + + //INT16 + UINT32 bInt_ID_H264:1; + UINT32 bInt_ID_JPEG:1; + UINT32 bInt_ID_GRAPHIC:1; + UINT32 bInt_ID_GRAPHIC2:1; + + //INT20 + UINT32 bInt_ID_AFFINE:1; + UINT32 bInt_ID_ISE:1; + UINT32 bInt_ID_TGE:1; + UINT32 bInt_ID_TSMUX:1; + + UINT32 bInt_ID_GPIO:1; + UINT32 bInt_ID_REMOTE:1; + UINT32 bInt_ID_PWM:1; + UINT32 bInt_ID_USB:1; + + UINT32 bInt_ID_USB3:1; + UINT32 bInt_ID_NAND:1; + UINT32 bInt_ID_SDIO:1; + UINT32 bInt_ID_SDIO2:1; + + //INT32 + UINT32 bInt_ID_SDIO3:1; + UINT32 bInt_ID_DMA:1; + UINT32 bInt_ID_ETHERNET:1; + UINT32 bInt_ID_SPI:1; + + //INT36 + UINT32 bInt_ID_SPI2:1; + UINT32 bInt_ID_SPI3:1; + UINT32 bInt_ID_SPI4:1; + UINT32 bReserved39:1; +// UINT32 bInt_ID_SPI5:1; + + //INT40 + UINT32 bReserved40:1; + UINT32 bInt_ID_I2C:1; + UINT32 bInt_ID_I2C2:1; + UINT32 bInt_ID_UART:1; + + UINT32 bInt_ID_UART2:1; + UINT32 bInt_ID_UART3:1; + UINT32 bInt_ID_UART4:1; + UINT32 bInt_ID_ADC:1; + + //INT48 + UINT32 bInt_ID_IDE:1; + UINT32 bInt_ID_IDE2:1; + UINT32 bInt_ID_DSI:1; + UINT32 bInt_ID_MI:1; + + //INT52 + UINT32 bInt_ID_HDMI:1; +// UINT32 bInt_ID_VX1:1; + UINT32 bInt_ID_DMA2:1; + UINT32 bInt_ID_LVDS:1; // LVDS& HiSPI& CSI + UINT32 bInt_ID_LVDS2:1; //LVDS2&HiSPI2&CSI2 + + //INT56 + UINT32 bInt_ID_RTC:1; + UINT32 bInt_ID_WDT:1; + UINT32 bInt_ID_CG:1; + UINT32 bInt_ID_CC:1; + + //INT60 + UINT32 bInt_ID_I2C3:1; + UINT32 bInt_ID_SLVS_EC:1; + UINT32 bInt_ID_LVDS3:1; //LVDS3&HiSPI3&CSI3 + UINT32 bInt_ID_LVDS4:1; //LVDS4&HiSPI4&CSI4 + + //INT64 + UINT32 bInt_ID_LVDS5:1; //LVDS5&HiSPI5&CSI5 + UINT32 bInt_ID_LVDS6:1; //LVDS6&HiSPI6&CSI6 + UINT32 bInt_ID_LVDS7:1; //LVDS7&HiSPI7&CSI7 + UINT32 bInt_ID_LVDS8:1; //LVDS8&HiSPI8&CSI8 + + //INT68 + UINT32 bInt_ID_SIE5:1; + UINT32 bInt_ID_SIE6:1; + UINT32 bInt_ID_SIE7:1; + UINT32 bInt_ID_SIE8:1; + + //INT72 + UINT32 bInt_ID_IVE:1; + UINT32 bInt_ID_SVM:1; + UINT32 bInt_ID_SDE:1; + UINT32 bInt_ID_CNN:1; + + //INT76 + UINT32 bInt_ID_DSP:1; + UINT32 bInt_ID_DSP2:1; + UINT32 bInt_ID_CANBUS:1; + UINT32 bInt_ID_CRYPTO:1; + + //INT80 + UINT32 bInt_ID_HWCOPY:1; + UINT32 bInt_ID_ROTATE:1; + UINT32 bInt_ID_I2C4:1; + UINT32 bInt_ID_I2C5:1; + + //INT84 + UINT32 bInt_ID_I2C6:1; + UINT32 bInt_ID_I2C7:1; + UINT32 bReserved86:1; + UINT32 bReserved87:1; + + //INT88 + UINT32 bInt_ID_TMDEMUX:1; + UINT32 bReserved89:3; + + //INT92 + UINT32 bReserved92:4; + //INT96 => 4 + UINT32 bReserved96:4; + //INT100=> 4 + UINT32 bReserved100:4; + //INT104=> 4 + UINT32 bReserved104:4; + //INT108=> 4 + UINT32 bReserved108:4; + //INT112=> 4 + UINT32 bReserved112:4; + //INT116=> 4 + UINT32 bReserved116:4; + //INT120=> 4 + UINT32 bReserved120:4; + //INT124=> 4 + UINT32 bReserved124:4; + }Bit; +} INT_INTC_ID_DST, *PINT_INTC_ID_DST; + +typedef union +{ + INT_PTN Reg[4]; + struct + { + //INT0 + UINT32 bInt_ID_TIMER:1; + UINT32 bInt_ID_SIE:1; + UINT32 bInt_ID_SIE2:1; + UINT32 bInt_ID_SIE3:1; + + UINT32 bInt_ID_SIE4:1; + UINT32 bInt_ID_IPE:1; + UINT32 bInt_ID_IME:1; + UINT32 bInt_ID_DCE:1; + + UINT32 bInt_ID_IFE:1; + UINT32 bInt_ID_IFE2:1; + UINT32 bInt_ID_DIS:1; + UINT32 bInt_ID_FDE:1; + +// UINT32 bInt_ID_RDE:1; + UINT32 bInt_ID_Ethernet_LPI:1; + UINT32 bInt_ID_RHE:1; + UINT32 bInt_ID_DRE:1; + UINT32 bInt_ID_DAI:1; + + + //INT16 + UINT32 bInt_ID_H264:1; + UINT32 bInt_ID_JPEG:1; + UINT32 bInt_ID_GRAPHIC:1; + UINT32 bInt_ID_GRAPHIC2:1; + + UINT32 bInt_ID_AFFINE:1; + UINT32 bInt_ID_ISE:1; + UINT32 bInt_ID_TGE:1; + UINT32 bInt_ID_TSMUX:1; + + UINT32 bInt_ID_GPIO:1; + UINT32 bInt_ID_REMOTE:1; + UINT32 bInt_ID_PWM:1; + UINT32 bInt_ID_USB:1; + + UINT32 bInt_ID_USB3:1; + UINT32 bInt_ID_NAND:1; + UINT32 bInt_ID_SDIO:1; + UINT32 bInt_ID_SDIO2:1; + + //INT32 + UINT32 bInt_ID_SDIO3:1; + UINT32 bInt_ID_DMA:1; + UINT32 bInt_ID_ETHERNET:1; + UINT32 bInt_ID_SPI:1; + + UINT32 bInt_ID_SPI2:1; + UINT32 bInt_ID_SPI3:1; + UINT32 bInt_ID_SPI4:1; + UINT32 bInt_ID_Ehternet_RevMII:1; +// UINT32 bInt_ID_SPI5:1; + + + UINT32 bInt_ID_SIF:1; + UINT32 bInt_ID_I2C:1; + UINT32 bInt_ID_I2C2:1; + UINT32 bInt_ID_UART:1; + + UINT32 bInt_ID_UART2:1; + UINT32 bInt_ID_UART3:1; + UINT32 bInt_ID_UART4:1; + UINT32 bInt_ID_ADC:1; + + //INT48 + UINT32 bInt_ID_IDE:1; + UINT32 bInt_ID_IDE2:1; + UINT32 bInt_ID_DSI:1; + UINT32 bInt_ID_MI:1; + + //INT52 + UINT32 bInt_ID_HDMI:1; +// UINT32 bInt_ID_VX1:1; + UINT32 bInt_ID_DMA2:1; + UINT32 bInt_ID_LVDS:1; // LVDS& HiSPI& CSI + UINT32 bInt_ID_LVDS2:1; //LVDS2&HiSPI2&CSI2 + + //INT56 + UINT32 bInt_ID_RTC:1; + UINT32 bInt_ID_WDT:1; + UINT32 bInt_ID_CG:1; + UINT32 bInt_ID_CC:1; + + //INT60 + UINT32 bInt_ID_I2C3:1; + UINT32 bInt_ID_SLVS_EC:1; + UINT32 bInt_ID_LVDS3:1; //LVDS3&HiSPI3&CSI3 + UINT32 bInt_ID_LVDS4:1; //LVDS4&HiSPI4&CSI4 + + //INT64 + UINT32 bInt_ID_LVDS5:1; //LVDS5&HiSPI5&CSI5 + UINT32 bInt_ID_LVDS6:1; //LVDS6&HiSPI6&CSI6 + UINT32 bInt_ID_LVDS7:1; //LVDS7&HiSPI7&CSI7 + UINT32 bInt_ID_LVDS8:1; //LVDS8&HiSPI8&CSI8 + + //INT68 + UINT32 bInt_ID_SIE5:1; + UINT32 bInt_ID_SIE6:1; + UINT32 bInt_ID_SIE7:1; + UINT32 bInt_ID_SIE8:1; + + //INT72 + UINT32 bInt_ID_IVE:1; + UINT32 bInt_ID_SVM:1; + UINT32 bInt_ID_SDE:1; + UINT32 bInt_ID_CNN:1; + + //INT76 + UINT32 bInt_ID_DSP:1; + UINT32 bInt_ID_DSP2:1; + UINT32 bInt_ID_CANBUS:1; + UINT32 bInt_ID_CRYPTO:1; + + //INT80 + UINT32 bInt_ID_HWCOPY:1; + UINT32 bInt_ID_ROTATE:1; + UINT32 bInt_ID_I2C4:1; + UINT32 bInt_ID_I2C5:1; + + //INT84 + UINT32 bInt_ID_I2C6:1; + UINT32 bInt_ID_I2C7:1; + UINT32 bInt_ID_TIMER2:1; //Timer to CA53 core2 + UINT32 bInt_ID_GPIO2:1; //GPIO to CA53 core2 + + //INT88 + UINT32 bInt_ID_PWM2:1; + UINT32 bInt_ID_CC2:1; + UINT32 bInt_ID_SIF2:1; //Timer to CA53 core2 + UINT32 bInt_ID_DSP_2:1; //?? + + //INT92 + UINT32 bInt_ID_DSP2_2:1; //?? + UINT32 bInt_ID_TMDEMUX:1; + UINT32 bReserved92:2; + //INT96 => 4 + UINT32 bReserved96:4; + //INT100=> 4 + UINT32 bReserved100:4; + //INT104=> 4 + UINT32 bReserved104:4; + //INT108=> 4 + UINT32 bReserved108:4; + //INT112=> 4 + UINT32 bReserved112:4; + //INT116=> 4 + UINT32 bReserved116:4; + //INT120=> 4 + UINT32 bReserved120:4; + //INT124=> 4 + UINT32 bReserved124:4; + }Bit; +} INT_GIC_ID_ENABLE, *PINT_GIC_ID_ENABLE; + +typedef struct +{ + INT_GIC_ID_DST int_id_dst[CC_CORE_CA53_CORE_NUM]; +} INT_GIC_DST, *PINT_GIC_DST; + +typedef struct +{ + INT_INTC_ID_DST int_id_dst[CC_CORE_DSP_NUM]; +} INT_INTC_DST, *PINT_INTC_DST; + +typedef struct +{ + INT_GIC_ID_ENABLE int_id_enable; +} INT_INTC_ENABLE, *PINT_INTC_ENABLE; + + +// MIPI CSI share the interrupt ID with LVDS / HiSPi +#define INT_ID_CSI INT_ID_LVDS +#define INT_ID_CSI2 INT_ID_LVDS2 + +#define INT_ID_CSI3 INT_ID_LVDS3 +#define INT_ID_CSI4 INT_ID_LVDS4 + +#define INT_ID_CSI5 INT_ID_LVDS5 +#define INT_ID_CSI6 INT_ID_LVDS6 +#define INT_ID_CSI7 INT_ID_LVDS7 +#define INT_ID_CSI8 INT_ID_LVDS8 + +#define INT_ID_VX1 INT_ID_LVDS5 +#define INT_ID_VX1_2 INT_ID_LVDS6 + +// Macro to generate bit value from ID +#define INT_ID_TO_BIT(Id) ((INT_PTN)(1) << (Id)) + +// check type and ID +STATIC_ASSERT((INT_ID_MAX - INT_GIC_SPI_START_ID) <= (sizeof(INT_PTN) << 3)); + +#define INT_ALL_MODULES ((sizeof(INT_PTN) == 4) ? 0xFFFFFFFFul : 0xFFFFFFFFFFFFFFFFull) + +extern INT_PTN int_getEnable(void); +extern INT_PTN int_getFlag(void); +extern INT_ID int_getIRQId(void); +extern INT_ID int_getDummyId(void); +extern UINT32 int_getLatency(void); +extern void int_setConfig(INT_CONFIG_ID ConfigID, UINT32 uiConfig); +extern void int_get_gic_enable(PINT_INTC_ENABLE gic_int_en); + + +//@} + +#endif diff --git a/board/novatek/na51055/loader/Include/modelext/model_cfg.h b/board/novatek/na51055/loader/Include/modelext/model_cfg.h new file mode 100755 index 000000000000..eb7be844cc5e --- /dev/null +++ b/board/novatek/na51055/loader/Include/modelext/model_cfg.h @@ -0,0 +1,8 @@ +#ifndef _MODEL_CFG_H +#define _MODEL_CFG_H + +#define MODEL_CFG_VER 0x16072510 ///< YYYY/MM/DD HH + +//No data structure, just a string. + +#endif diff --git a/board/novatek/na51055/loader/Include/modelext/modelext_info.h b/board/novatek/na51055/loader/Include/modelext/modelext_info.h new file mode 100755 index 000000000000..b96b50b966dd --- /dev/null +++ b/board/novatek/na51055/loader/Include/modelext/modelext_info.h @@ -0,0 +1,35 @@ +#ifndef _MODELEXT_INFO_H +#define _MODELEXT_INFO_H + +#define MODELEXT_INFO_VER 0x16072219 ///< YYYY/MM/DD HH + +typedef enum _MODELEXT_TYPE { + MODELEXT_TYPE_DUMMY = 0, + MODELEXT_TYPE_INFO , + MODELEXT_TYPE_BIN_INFO , + MODELEXT_TYPE_PINMUX_CFG , + MODELEXT_TYPE_INTDIR_CFG , + MODELEXT_TYPE_EMB_PARTITION, + MODELEXT_TYPE_GPIO_INFO , + MODELEXT_TYPE_DRAM_PARTITION, + MODELEXT_TYPE_MODEL_CFG, + MODELEXT_TYPE_MAX +} MODELEXT_TYPE; + +typedef struct _MODELEXT_HEADER { + unsigned int size; ///< header size + container size + unsigned int type; ///< MODELEXT_TYPE + unsigned int number; ///< number of carried data elements + unsigned int version; ///< data header version +} MODELEXT_HEADER; + +typedef struct _MODELEXT_INFO { + char name[8]; ///< always be 'M','O','D','E','L','E','X','T' + char chip_name[8]; ///< CHIP_NAME (8) ---- check by encrypt_bin + char version[8]; ///< Reversed + char date[8]; ///< date + unsigned int ext_bin_length; ///< Bin File Length (4) --- write by encrypt_bin + unsigned int check_sum; ///< Check Sum Value (4) ----- write by encrypt_bin +} MODELEXT_INFO; + +#endif diff --git a/board/novatek/na51055/loader/Include/modelext/modelext_parser.h b/board/novatek/na51055/loader/Include/modelext/modelext_parser.h new file mode 100755 index 000000000000..e00170ea1a85 --- /dev/null +++ b/board/novatek/na51055/loader/Include/modelext/modelext_parser.h @@ -0,0 +1,78 @@ +#ifndef _MODELEXT_PARSER_H +#define _MODELEXT_PARSER_H + +#include "modelext_info.h" + +/** + modelext inline parse. + + modelext info tables are set to an certain memory address, + which use to get data pointer you want. + + @param[in] modelext info address. + @param[in] refer to MODELEXT_TYPE_ + @param[in] a memory space will be stored with description of modelext type. + @return + - @b address: the data pointer of result. +*/ +static inline unsigned char *modelext_get_cfg(unsigned char *buf, unsigned int type, MODELEXT_HEADER **header) +{ +#define MAGIC "MODELEXT" + + MODELEXT_HEADER *h = (MODELEXT_HEADER*)buf; + MODELEXT_INFO *d = (MODELEXT_INFO*)(buf + sizeof(MODELEXT_HEADER)); + + if(type >= MODELEXT_TYPE_MAX) + { + if(header) + { + *header = NULL; + } + return NULL; + } + + if(memcmp(d->name, MAGIC, strlen(MAGIC))) + { + if(header) + { + *header = NULL; + } + return NULL; + } + + MODELEXT_HEADER* h_tail = (MODELEXT_HEADER*)(buf + d->ext_bin_length); + + while(h->size) + { + if(h->type == type) + { + break; + } + else + { + h = (MODELEXT_HEADER*)(((char*)h) + h->size); + if(h >= h_tail) + { + return NULL; + } + } + } + + if(!h->size) + { + if(header) + { + *header = NULL; + } + return NULL; + } + + if(header) + { + *header = h; + } + + return (unsigned char*)(((unsigned char*)h) + sizeof(MODELEXT_HEADER)); +} + +#endif diff --git a/board/novatek/na51055/loader/Include/modelext/shm_info.h b/board/novatek/na51055/loader/Include/modelext/shm_info.h new file mode 100755 index 000000000000..4ffaeaa3e637 --- /dev/null +++ b/board/novatek/na51055/loader/Include/modelext/shm_info.h @@ -0,0 +1,131 @@ +/** + @file shm_info.h + @ingroup + @note THESE STRUCTS ARE VERY VERY IMPORTANT FORMAT DEFINITION OF SYSTEM, + DO NOT MODIFY ANY ITEM OR INSERT/REMOVE ANY ITEM OF THESE STRUCTS!!! + + Copyright Novatek Microelectronics Corp. 2018. All rights reserved. +*/ +#ifndef __ARCH_COMMON_SHM_INFO_H +#define __ARCH_COMMON_SHM_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#elif defined(_NVT_LINUX_) +#include +#else +#include +#endif + +#define SHM_INFO_VER 0x18060815 ///< YYYY/MM/DD HH + +/** + @name Ld control flag for LDINFO.LdCtrl +*/ +//@{ +#define LDCF_PARTLOAD_EN 0x0000001 ///< BIT 0.PARTLOAD_EN (0=no,1=yes) +//@} + +/** + @name Ld control flag for LDINFO.LdCtrl2 +*/ +//@{ +#define LDCF_UPDATE_FW 0x0000001 ///< BIT 0.UPDATE_FW (0=no,1=yes) +#define LDCF_UPDATE_LD 0x0000002 ///< BIT 1.UPDATE_LD (0=no,1=yes) +#define LDCF_BOOT_CARD 0x0000004 ///< BIT 2.BOOT_CARD (0=no,1=yes) +#define LDCF_BOOT_FLASH 0x0000008 ///< BIT 3.BOOT_FLASH (0=no,1=yes) +#define LDCF_UPDATE_CAL 0x0000010 ///< BIT 4.UPDATE_CAL (0=no,1=yes) +#define LDCF_UPDATE_FW_DONE 0x0000100 ///< BIT 8.UPDATE_FW_DONE (0=no,1=yes) +#define LDCF_S3_BOOT 0x0000200 ///< BIT 9.BOOT FROM S3 STATE (0=no,1=yes) +//@} + +/** + Loader information + + MUST 28 WORDS +*/ +typedef struct _BOOTINFO { + char LdInfo_1[16]; ///< LD-NAME(16) ------ w by Ld + UINT32 LdCtrl; ///< Fw flag (4) ----------- r by Ld + ///< BIT 0.enable part-load (0=full load,1=part load) + UINT32 LdCtrl2; ///< Ld flag (4) ----------- w by Ld + ///< BIT 0.UPDATE_FW (0=no,1=yes) + ///< BIT 1.UPDATE_LOADER (0=no,1=yes) + ///< BIT 2.BOOT_CARD (0=no,1=yes) + ///< BIT 3.BOOT_FLASH (0=no,1=yes) + ///< BIT 4.UPDATE_CAL (0=no,1=yes) + ///< BIT 8.UPDATE_FW_DONE (0=no,1=yes) + //< BIT 9.BOOT FROM S3 STATE (0=no,1=yes) + UINT32 LdLoadSize; ///< Ld load size (4) ------ w by Ld (NOTE: this value must be block size align) + UINT32 LdLoadTime; ///< Ld exec time(us) (4) -- w by Ld + UINT32 LdResvSize; ///< Ld size (by bytes, reserved size in partition) (4) ------ w by Ld + UINT32 FWResvSize; ///< FW reserved size (4) ------ w by Ld + UINT16 LdPackage; ///< IC package expected by Ld (0xFF: ES, 0: 660, 3: 663, 5: 665, etc...) + UINT16 LdStorage; ///< Internal storage expected by Ld (0: unkown, 1: nand, 2: spi nand, 3: spi nor) + UINT32 fdt_addr; + UINT32 Resv[16]; ///< (4*5) ------------ reserved for project Ld +} BOOTINFO; + +STATIC_ASSERT(sizeof(BOOTINFO) == 112); + +/** + communication information + + MUST 54 WORDS +*/ +//BOOT_REASON +#define BOOT_REASON_NORMAL 0 // normal or from sd +#define BOOT_REASON_FWUPDFW 1 // Firmware update Firmware +#define BOOT_REASON_FROM_USB 2 // Update from USB +#define BOOT_REASON_FROM_ETH 3 // Update from ethernet +#define BOOT_REASON_FORMAT_ROOTFS 4 // Format rootfs because rootfs broken is detected +#define BOOT_REASON_RECOVERY_SYS 5 // System recovery from eMMC +#define BOOT_REASON_FROM_UART 6 // Update from uart + +//COMMINFO::Resv field definition +typedef enum _COMM_RESV_IDX_{ + COMM_RESV_IDX_BOOT_REASON = 0, + COMM_RESV_IDX_CORE1_START = 1, + COMM_RESV_IDX_CORE2_START = 2, + COMM_RESV_IDX_UITRON_COMP_ADDR = 3, + COMM_RESV_IDX_UITRON_COMP_LEN = 4, + COMM_RESV_IDX_FW_UPD_ADDR = 5, + COMM_RESV_IDX_FW_UPD_LEN = 6, + COMM_RESV_IDX_OTA_NAME_ADDR = 7, + COMM_RESV_IDX_S3_APB_ADDR = 8, + COMM_RESV_IDX_S3_APB_LEN = 9, +} COMM_RESV_IDX; + +typedef struct _COMMINFO { + char CommInfo_1[16];///< COMMINFO (16) + UINT32 Resv[45];///< reversed data for communication between loader, uboot, uitron, linux + // Resv[0]: COMM_RESV_IDX_BOOT_REASON, + // BYTE[0]: BOOT_REASON: use #define COMM_BOOT_REASON_ + // BYTE[1]: BOOT_DONE: 0:Not yet, 1:Done 2:NG + // BYTE[2]: DSP_DONE: 0:Not yet, 1:Done 2:NG + // Resv[1]: COMM_CORE1_START (used on uboot trigger loader to start uitron) + // Resv[2]: COMM_CORE2_START (used on uitron trigger linux resume) + // Resv[3]: COMM_UITRON_COMP_ADDR + // Resv[4]: COMM_UITRON_COMP_LEN + // Resv[5]: COMM_FW_UPD_ADDR + // Resv[6]: COMM_FW_UPD_LEN + // Resv[7]: COMM_OTA_NAME_ADDR : OTA name + // Resv[8]: COMM_S3_APB_ADDR : S3-resume's apb register info addr + // Resv[9]: COMM_S3_APB_LEN : S3-resume's apb register info len + UINT32 UserDef[5]; ///< can be used for customer +} COMMINFO; + +STATIC_ASSERT(sizeof(COMMINFO) == 216); + +/** + Binary file information + + MUST 82 WORDS +*/ +typedef struct _SHMINFO { + BOOTINFO boot; + COMMINFO comm; +} SHMINFO; + +STATIC_ASSERT(sizeof(SHMINFO) == 328); +#endif /* __ARCH_COMMON_SHM_INFO_H */ diff --git a/board/novatek/na51055/loader/Include/modelext/top.h b/board/novatek/na51055/loader/Include/modelext/top.h new file mode 100755 index 000000000000..2011294fca65 --- /dev/null +++ b/board/novatek/na51055/loader/Include/modelext/top.h @@ -0,0 +1,1382 @@ +/** + TOP controller header + + Sets the pinmux of each module. + + @file top.h + @ingroup mIDrvSys_TOP + @note Refer NT96650 data sheet for PIN/PAD naming + + Copyright Novatek Microelectronics Corp. 2013. All rights reserved. +*/ + +#ifndef _TOP_H +#define _TOP_H + +#if defined(__UITRON) +#include "Type.h" +#else +#include "nvt_type.h" +#endif +//#define TOP_NEW_API (0) + +/** + @addtogroup mIDrvSys_TOP +*/ +//@{ +#define PIN_GROUP_CONFIG_VER 0x16062910 + +/** + Debug port select ID + + Debug port select value for pinmux_select_debugport(). +*/ +typedef enum +{ + PINMUX_DEBUGPORT_CKG = 0x0000, ///< CKGen + PINMUX_DEBUGPORT_ARB = 0x0001, ///< Arbiter + PINMUX_DEBUGPORT_DDR = 0x0002, ///< DDR + PINMUX_DEBUGPORT_APBTG = 0x0003, ///< APBTG + PINMUX_DEBUGPORT_OCPBRG = 0x0004, ///< OCP BRG + PINMUX_DEBUGPORT_INTC = 0x0005, ///< INTC + PINMUX_DEBUGPORT_IDE = 0x0006, ///< IDE + PINMUX_DEBUGPORT_IDE2 = 0x0007, ///< IDE2 + PINMUX_DEBUGPORT_MI = 0x0008, ///< MI + PINMUX_DEBUGMIPI_DSI = 0x0009, ///< MIPI DSI + PINMUX_DEBUGMIPI_CC = 0x000A, ///< CC + PINMUX_DEBUGMIPI_EFUSE = 0x000B, ///< EFUSE + PINMUX_DEBUGMIPI_ETH = 0x000C, ///< ETH + PINMUX_DEBUGMIPI_AHBC_ETH = 0x000D, ///< AHBC ETH + PINMUX_DEBUGMIPI_TSMUX = 0x000E, ///< TSMUX + + PINMUX_DEBUGPORT_TIMER = 0x0010, ///< Timer + PINMUX_DEBUGPORT_WDT = 0x0011, ///< WDT + PINMUX_DEBUGPORT_GPIO = 0x0012, ///< GPIO + PINMUX_DEBUGPORT_SSP = 0x0013, ///< SSP (DAI) + PINMUX_DEBUGPORT_AUDIO = 0x0014, ///< AUDIO + PINMUX_DEBUGPORT_SDIO1 = 0x0015, ///< SDIO1 + PINMUX_DEBUGPORT_SDIO2 = 0x0016, ///< SDIO2 + PINMUX_DEBUGPORT_SDIO3 = 0x0017, ///< SDIO3 + PINMUX_DEBUGPORT_SMMC = 0x0018, ///< XD/NAND/SMC + PINMUX_DEBUGPORT_USB = 0x0019, ///< USB + PINMUX_DEBUGPORT_USB2 = 0x001A, ///< USB2 + PINMUX_DEBUGPORT_AHBC_USB = 0x001B, ///< AHBC_USB + PINMUX_DEBUGPORT_AHBC_USB2 = 0x001C, ///< AHBC_USB2 + PINMUX_DEBUGPORT_I2C = 0x001D, ///< I2C + PINMUX_DEBUGPORT_I2C2 = 0x001E, ///< I2C2 + PINMUX_DEBUGPORT_SIF = 0x001F, ///< SIF + PINMUX_DEBUGPORT_SPI = 0x0020, ///< SPI + PINMUX_DEBUGPORT_SPI2 = 0x0021, ///< SPI2 + PINMUX_DEBUGPORT_SPI3 = 0x0022, ///< SPI3 + PINMUX_DEBUGPORT_SPI4 = 0x0023, ///< SPI4 + PINMUX_DEBUGPORT_SPI5 = 0x0024, ///< SPI5 + PINMUX_DEBUGPORT_PWM = 0x0025, ///< PWM + PINMUX_DEBUGPORT_ADM = 0x0026, ///< ADC + PINMUX_DEBUGPORT_REMOTE = 0x0027, ///< Remote + PINMUX_DEBUGPORT_CRYPTO = 0x0028, ///< Crypto + + PINMUX_DEBUGPORT_OCP2BRG = 0x0030, ///< OCP2 BRG + PINMUX_DEBUGPORT_DSP = 0x0031, ///< DSP + PINMUX_DEBUGPORT_H264 = 0x0038, ///< H.264 + + PINMUX_DEBUGMIPI_CSI = 0x0040, ///< MIPI CSI + PINMUX_DEBUGMIPI_CSI2 = 0x0041, ///< MIPI CSI2 + PINMUX_DEBUGMIPI_VX1 = 0x0042, ///< VX1 + PINMUX_DEBUGPORT_SIE = 0x0043, ///< SIE + PINMUX_DEBUGMIPI_SIE2 = 0x0044, ///< SIE2 + PINMUX_DEBUGPORT_SIE3 = 0x0045, ///< SIE3 + PINMUX_DEBUGMIPI_SIE4 = 0x0046, ///< SIE4 + PINMUX_DEBUGPORT_TGE = 0x0047, ///< TGE + PINMUX_DEBUGPORT_DIS = 0x0048, ///< DIS + PINMUX_DEBUGPORT_FDE = 0x0049, ///< FDE + PINMUX_DEBUGPORT_JPEG = 0x004A, ///< JPEG + PINMUX_DEBUGPORT_GRAPHIC = 0x004B, ///< GRAPHIC + PINMUX_DEBUGPORT_GRAPHIC2 = 0x004C, ///< GRAPHIC2 + PINMUX_DEBUGPORT_IFE = 0x004D, ///< IFE + PINMUX_DEBUGPORT_AFFINE = 0x004E, ///< Affine + PINMUX_DEBUGPORT_ISE = 0x004F, ///< ISE + PINMUX_DEBUGPORT_RDE = 0x0050, ///< RDE + PINMUX_DEBUGPORT_RHE = 0x0051, ///< RHE + PINMUX_DEBUGPORT_I2C3 = 0x0052, ///< I2C3 + + PINMUX_DEBUGPORT_IPE = 0x0060, ///< IPE + PINMUX_DEBUGPORT_IME = 0x0061, ///< IME + PINMUX_DEBUGPORT_IFE2 = 0x0062, ///< IFE2 + PINMUX_DEBUGPORT_HDMI = 0x0063, ///< HDMI + PINMUX_DEBUGPORT_DCE = 0x0064, ///< DCE + PINMUX_DEBUGPORT_DRE = 0x0065, ///< DRE + +/* //remove for NT96660 + PINMUX_DEBUGPORT_AMBARD = 0x0000, ///< AMBA RD + PINMUX_DEBUGPORT_AMBAWR = 0x0001, ///< AMBA WR + PINMUX_DEBUGPORT_AHB = 0x0002, ///< AHB + PINMUX_DEBUGPORT_AHBC0 = 0x0003, ///< AHB C0 + PINMUX_DEBUGPORT_AHBC1 = 0x0004, ///< AHB C1 + PINMUX_DEBUGPORT_APBBRG = 0x0005, ///< APB BRG + PINMUX_DEBUGPORT_DDRIO = 0x0006, ///< DDRIO + PINMUX_DEBUGPORT_LVDS = 0x001F, ///< LVDS + PINMUX_DEBUGPORT_SDIO1_FIFO = 0x0022, ///< SDIO1 FIFO + PINMUX_DEBUGPORT_SDIO2_FIFO = 0x0023, ///< SDIO2 FIFO + PINMUX_DEBUGPORT_BMC = 0x0024, ///< BMC + PINMUX_DEBUGPORT_IRDA1 = 0x0025, ///< IRDA1 + PINMUX_DEBUGPORT_IRDA2 = 0x0026, ///< IRDA2 + PINMUX_DEBUGMIPI_OCP = 0x0029, ///< OCP + PINMUX_DEBUGPORT_PRE = 0x0030, ///< PRE +*/ + PINMUX_DEBUGPORT_GROUP_NONE = 0x0000, ///< No debug port is output + PINMUX_DEBUGPORT_GROUP1 = 0x0100, ///< Output debug port to MC[18..0] + PINMUX_DEBUGPORT_GROUP2 = 0x0200, ///< Output debug port to LCD[18..0] + + ENUM_DUMMY4WORD(PINMUX_DEBUGPORT) +} PINMUX_DEBUGPORT; + +// for backward compatible +#define PINMUX_DEBUGMIPI_OCP PINMUX_DEBUGPORT_OCPBRG + +/* + PIN state for SDIO + + (Reserved for driver internal usage) + + @note For pinmux_getPinmux() +*/ +typedef enum +{ + PIN_SDIO_STATE_NONE, + PIN_SDIO_STATE_ACTIVE = 0x0100, //< SD active + ENUM_DUMMY4WORD(PIN_SDIO_STATE) +} PIN_SDIO_STATE; + +/* + PIN state for SPI + + (Reserved for driver internal usage) + + @note For pinmux_getPinmux() +*/ +typedef enum +{ + PIN_SPI_STATE_NONE, + PIN_SPI_STATE_ACTIVE = 0x10000, //< SPI active + ENUM_DUMMY4WORD(PIN_SPI_STATE) +} PIN_SPI_STATE; + +/* + PIN state for NAND + + (Reserved for driver internal usage) + + @note For pinmux_getPinmux() +*/ +typedef enum +{ + PIN_NAND_STATE_NONE, + PIN_NAND_STATE_ACTIVE = 0x0400, //< NAND active + ENUM_DUMMY4WORD(PIN_NAND_STATE) +} PIN_NAND_STATE; + +/* + PINMUX selection for I2C + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_I2C_SEL_INACTIVE, //< I2C inactive + PINMUX_I2C_SEL_ACTIVE, //< I2C active + ENUM_DUMMY4WORD(PINMUX_I2C_SEL) +} PINMUX_I2C_SEL; + +/* + PINMUX selection for PWM + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_PWM_SEL_INACTIVE, //< PWM inactive + PINMUX_PWM_SEL_ACTIVE, //< PWM active + ENUM_DUMMY4WORD(PINMUX_PWM_SEL) +} PINMUX_PWM_SEL; + +/* + PINMUX selection for SIF + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_SIF_SEL_INACTIVE, //< SIF inactive + PINMUX_SIF_SEL_ACTIVE, //< SIF active + ENUM_DUMMY4WORD(PINMUX_SIF_SEL) +} PINMUX_SIF_SEL; + +/* + PINMUX selection for I2S + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_I2S_SEL_INACTIVE, //< I2S inactive + PINMUX_I2S_SEL_ACTIVE, //< I2S active + ENUM_DUMMY4WORD(PINMUX_I2S_SEL) +} PINMUX_I2S_SEL; + +/* + PINMUX selection for UART + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_UART_SEL_INACTIVE, //< UART inactive + PINMUX_UART_SEL_ACTIVE, //< UART active + ENUM_DUMMY4WORD(PINMUX_UART_SEL) +} PINMUX_UART_SEL; + + +/** + OCP Debug port select ID + + Debug port select value for pinmux_select_ocp_debugport(). +*/ +typedef enum +{ + PINMUX_DEBUGPORT_OCPCMD_DMA_APB = 0x0, ///< OCP CMD vs. DMA/APB + PINMUX_DEBUGPORT_OCPCMD_HANDSHAKE = 0x1, ///< OCP CMD handshaking + PINMUX_DEBUGPORT_OCP_DMA = 0x2, ///< OCP vs. DMA + PINMUX_DEBUGPORT_OCP_DEBUG_3 = 0x3, ///< OCP debug 3 + PINMUX_DEBUGPORT_OCP_DEBUG_4 = 0x4, ///< OCP debug 4 + + ENUM_DUMMY4WORD(PINMUX_DEBUGPORT_OCP) +} PINMUX_DEBUGPORT_OCP; + +/** + Function group + + @note For pinmux_init() +*/ +typedef enum +{ + PIN_FUNC_SDIO, ///< SDIO. Configuration refers to PIN_SDIO_CFG. + PIN_FUNC_SDIO2, ///< SDIO2. Configuration refers to PIN_SDIO_CFG. + PIN_FUNC_SDIO3, ///< SDIO3. Configuration refers to PIN_SDIO_CFG. + PIN_FUNC_NAND, ///< NAND. Configuration refers to PIN_NAND_CFG. + PIN_FUNC_SENSOR, ///< sensor interface. Configuration refers to PIN_SENSOR_CFG. + PIN_FUNC_SENSOR2, ///< sensor2 interface. Configuration refers to PIN_SENSOR2_CFG. + PIN_FUNC_SENSOR3, ///< sensor3 interface. Configuration refers to PIN_SENSOR3_CFG. + PIN_FUNC_SENSOR4, ///< sensor4 interface. Configuration refers to PIN_SENSOR4_CFG. + PIN_FUNC_SENSOR5, ///< sensor5 interface. Configuration refers to PIN_SENSOR5_CFG. + PIN_FUNC_SENSOR6, ///< sensor6 interface. Configuration refers to PIN_SENSOR6_CFG. + PIN_FUNC_SENSOR7, ///< sensor7 interface. Configuration refers to PIN_SENSOR7_CFG. + PIN_FUNC_SENSOR8, ///< sensor8 interface. Configuration refers to PIN_SENSOR8_CFG. + PIN_FUNC_MIPI_LVDS, ///< MIPI/LVDS interface configuration. Configuration refers to PIN_MIPI_LVDS_CFG. + PIN_FUNC_I2C, ///< I2C. Configuration refers to PIN_I2C_CFG. + PIN_FUNC_SIF, ///< SIF. Configuration refers to PIN_SIF_CFG. + PIN_FUNC_UART, ///< UART. Configuration refers to PIN_UART_CFG. + PIN_FUNC_SPI, ///< SPI. Configuration refers to PIN_SPI_CFG. + PIN_FUNC_REMOTE, ///< REMOTE. Configuration refers to PIN_REMOTE_CFG. + PIN_FUNC_PWM, ///< PWM. Configuration refers to PIN_PWM_CFG. + PIN_FUNC_AUDIO, ///< AUDIO. Configuration refers to PIN_PWM_CFG. + PIN_FUNC_LCD, ///< LCD interface. Configuration refers to PINMUX_LCDINIT, PINMUX_PMI_CFG, PINMUX_DISPMUX_SEL. + PIN_FUNC_LCD2, ///< LCD2 interface. Configuration refers to PINMUX_LCDINIT, PINMUX_PMI_CFG, PINMUX_DISPMUX_SEL. + PIN_FUNC_TV, ///< TV interface. Configuration refers to PINMUX_TV_HDMI_CFG. + PIN_FUNC_HDMI, ///< HDMI. Configuration refers to PINMUX_LCDINIT, PINMUX_TV_HDMI_CFG, PINMUX_HDMI_CFG. + PIN_FUNC_ETH, ///< ETH. Configuration refers to + + ENUM_DUMMY4WORD(PIN_FUNC) +} PIN_FUNC; + +/** + PIN config for SDIO + + @note For pinmux_init() with PIN_FUNC_SDIO or PIN_FUNC_SDIO2 or PIN_FUNC_SDIO3.\n + For example, you can use {PIN_FUNC_SDIO, PIN_SDIO_CFG_1ST_PINMUX|PIN_SDIO_CFG_4BITS}\n + to declare SDIO is 4 bits and located in 1st pinmux location. +*/ +typedef enum +{ + PIN_SDIO_CFG_NONE, + PIN_SDIO_CFG_4BITS = 0x01, ///< 4 bits wide + PIN_SDIO_CFG_8BITS = 0x02, ///< 8 bits wide + + PIN_SDIO_CFG_1ST_PINMUX = 0x00, ///< 1st pinmux location + ///< For SDIO: enable SD_CLK/SD_CMD/SD_D[0..3] on MC[16..21] (C_GPIO[16..21]) + ///< For SDIO2: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[22..27] (C_GPIO[22..27]) + ///< For SDIO3: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[28..33] (C_GPIO[28..33]) + PIN_SDIO_CFG_2ND_PINMUX = 0x10, ///< 2nd pinmux location + ///< For SDIO: enable SD_CLK/SD_CMD/SD_D[0..3] on MC[16..21] (C_GPIO[16..21]) (SDIO only has one pinmux pad group) + ///< For SDIO2: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[22..27] (C_GPIO[22..27]) (SDIO2 only has one pinmux pad group) + ///< For SDIO3: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[0..3]/MC9/MC11 (C_GPIO[0..3], 9, 11) + ///< When 8 bits, enable MC[0..7]/MC9/MC11 (C_GPIO[0..7], 9, 11) + + ENUM_DUMMY4WORD(PIN_SDIO_CFG) +} PIN_SDIO_CFG; + +/** + PIN config for NAND + + @note For pinmux_init() with PIN_FUNC_NAND.\n + For example, you can use {PIN_FUNC_NAND, PIN_NAND_CFG_1CS} to declare NAND with 1 CS. +*/ +typedef enum +{ + PIN_NAND_CFG_NONE, + PIN_NAND_CFG_1CS = 0x01, ///< 1 chip select. Enable NAND_D[0..7]/NAND_CS0/NAND_WE/NAND_RE/NAND_CLE/NAND_ALE/NAND_WP/NAND_RDY on MC[0..8]/MC[10..15] (C_GPIO[0..8], C_GPIO[10..15]) + PIN_NAND_CFG_2CS = 0x02, ///< 2 chip select. Enable NAND_D[0..7]/NAND_CS[0..1]/NAND_WE/NAND_RE/NAND_CLE/NAND_ALE/NAND_WP/NAND_RDY on MC[0..8]/MC[10..15] (C_GPIO[0..15]) + PIN_NAND_CFG_SPI_NAND = 0x4, ///< Virtual enum for project layer configuration + PIN_NAND_CFG_SPI_NOR = 0x8, ///< Virtual enum for project layer configuration + ENUM_DUMMY4WORD(PIN_NAND_CFG) +} PIN_NAND_CFG; + +/** + PIN config for Sensor + + @note For pinmux_init() with PIN_FUNC_SENSOR.\n + For example, you can use {PIN_FUNC_SENSOR, PIN_SENSOR_CFG_10BITS|PIN_SENSOR_CFG_SHUTTER|PIN_SENSOR_CFG_MCLK}\n + to declare sensor interface is 10 bits sensor, has SHUTTER and MCLK. +*/ +typedef enum +{ + PIN_SENSOR_CFG_NONE, + PIN_SENSOR_CFG_8BITS = 0x01, ///< 8 bits sensor. Enable SN_D[4..11]/SN_PXCLK/SN_VD/SN_HD on HSI_D[1..4]N/HSI_D[1..4]P/SN_PXCLK/SN_VD/SN_HD (S_GPI[1..3]/S_GPI[1..3]) + PIN_SENSOR_CFG_10BITS = 0x02, ///< 10 bits sensor. Enable SN_D[2..11]/SN_PXCLK/SN_VD/SN_HD on HSI_D[0..4]N/HSI_D[0..4]P0/SN_PXCLK/SN_VD/SN_HD (S_GPI[1..3]/S_GPI[1..3]) + PIN_SENSOR_CFG_12BITS = 0x04, ///< 12 bits sensor. Enable SN_D[0..11]/SN_PXCLK/SN_VD/SN_HD on HSI_D[0..4]N/HSI_D[0..4]P/HSI_CK0N/HSI_CK0P/SN_PXCLK/SN_VD/SN_HD (S_GPI[1..3]/S_GPI[1..3]) + PIN_SENSOR_CFG_MIPI = 0x20, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR_CFG_LVDS = 0x40, ///< LVDS sensor PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR_CFG_LVDS_VDHD = 0x80, ///< Backward compatible + + PIN_SENSOR_CFG_SHUTTER = 0x100, ///< Enable SN_SHUTTER on SN_GPIO[10] (SN_GPIO[10]) + PIN_SENSOR_CFG_MCLK = 0x200, ///< Enable SN_MCLK on SN_MCLK (S_GPIO[0]) + PIN_SENSOR_CFG_MCLK2 = 0x400, ///< Enable SN_MCLK2 on SBCS0 (S_GPIO[4]) + PIN_SENSOR_CFG_MES0 = 0x800, ///< Enable ME_SHUT0 on PWM0 (P_GPIO[0]) + PIN_SENSOR_CFG_MES0_2ND = 0x1000, ///< Enable (2nd) ME_SHUT0 on PWM16 (P_GPIO[16]) + PIN_SENSOR_CFG_MES1 = 0x2000, ///< Enable ME_SHUT1 on PWM1 (P_GPIO[1]) + PIN_SENSOR_CFG_MES1_2ND = 0x4000, ///< Enable (2nd) ME_SHUT1 on PWM17 (P_GPIO[17]) + PIN_SENSOR_CFG_FLCTR = 0x8000, ///< Enable SN_FLCTR on SN_FLCTR (P_GPIO[40]) + PIN_SENSOR_CFG_STROBE = 0x10000, ///< Enable SN_FLASH on SN_GPIO[9] (SN_GPIO[9]) + PIN_SENSOR_CFG_SPCLK = 0x20000, ///< Enable SP_CLK on SN_SPCLK (P_GPIO[20]) + PIN_SENSOR_CFG_SPCLK_2ND = 0x40000, ///< Enable SP_CLK on LCD27 (L_GPIO[27]) + PIN_SENSOR_CFG_SP2CLK = 0x80000, ///< Enable SP2_CLK on REMOTE_RX(P_GPIO[39]) + PIN_SENSOR_CFG_SP2CLK_2ND = 0x100000,///< Enable SP2_CLK on SBCS3 (P_GPIO[24]) + PIN_SENSOR_CFG_MES2 = 0x200000, ///< Enable ME_SHUT2 on PWM2 (P_GPIO[2]) + PIN_SENSOR_CFG_MES2_2ND = 0x400000, ///< Enable (2nd) ME_SHUT2 on PWM18 (P_GPIO[18]) + PIN_SENSOR_CFG_MES3 = 0x800000, ///< Enable ME_SHUT3 on PWM3 (P_GPIO[3]) + PIN_SENSOR_CFG_MES3_2ND = 0x1000000, ///< Enable (2nd) ME_SHUT3 on PWM19 (P_GPIO[19]) + PIN_SENSOR_CFG_LOCKN = 0x2000000, ///< Enable LOCKN on PGPIO30 + PIN_SENSOR_CFG_LOCKN2= 0x4000000, ///< Enable LOCKN2 on PGPIO31 + + + ENUM_DUMMY4WORD(PIN_SENSOR_CFG) +} PIN_SENSOR_CFG; + +/** + PIN config for Sensor2 + + @note For pinmux_init() with PIN_FUNC_SENSOR2.\n + For example, you can use {PIN_FUNC_SENSOR2, PIN_SENSOR2_CFG_CCIR8BITS}\n + to declare sensor2 interface connect a CCIR 8 bits sensor. +*/ +typedef enum +{ + PIN_SENSOR2_CFG_NONE, + PIN_SENSOR2_CFG_CCIR8BITS = 0x08, ///< Backward compatible + PIN_SENSOR2_CFG_CCIR16BITS = 0x10, ///< Backward compatible + PIN_SENSOR2_CFG_MIPI = 0x20, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR2_CFG_LVDS = 0x40, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR2_CFG_LVDS_VDHD = 0x80, ///< Backward compatible + PIN_SENSOR2_CFG_10BITS = 0x100, ///< Backward compatible + + PIN_SENSOR2_CFG_MCLK2 = 0x200, ///< Enable SN_MCLK2 on SBCS0 (S_GPIO[4]) + PIN_SENSOR2_CFG_MES2 = 0x400, ///< Enable ME_SHUT2 on PWM2 (P_GPIO[2]) + PIN_SENSOR2_CFG_MES2_2ND = 0x800, ///< Enable (2nd) ME_SHUT2 on PWM18 (P_GPIO[18]) + PIN_SENSOR2_CFG_MES3 = 0x1000, ///< Enable ME_SHUT3 on PWM3 (P_GPIO[3]) + PIN_SENSOR2_CFG_MES3_2ND = 0x2000, ///< Enable (2nd) ME_SHUT3 on PWM19 (P_GPIO[19]) + + ENUM_DUMMY4WORD(PIN_SENSOR2_CFG) +} PIN_SENSOR2_CFG; + +/** + PIN config for Sensor3 + + @note For pinmux_init() with PIN_FUNC_SENSOR3.\n + For example, you can use {PIN_FUNC_SENSOR3, PIN_SENSOR3_CFG_8BITS}\n + to declare sensor3 interface connect a 8 bits sensor. +*/ +typedef enum +{ + PIN_SENSOR3_CFG_NONE, + PIN_SENSOR3_CFG_8BITS = 0x01, ///< 8 bits sensor. Enable SIE3[0..7]/SIE3_PXCEL/SIE3_VD/SIE3_HD on P_GPIO[0..10] + PIN_SENSOR3_CFG_10BITS = 0x02, ///< 10 bits sensor. + PIN_SENSOR3_CFG_12BITS = 0x04, ///< 12 bits sensor. + PIN_SENSOR3_CFG_16BITS = 0x08, ///< 16 bits sensor. + PIN_SENSOR3_CFG_MIPI = 0x10, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR3_CFG_LVDS = 0x20, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR3_CFG_MCLK2 = 0x100, ///< MCLK2 + + ENUM_DUMMY4WORD(PIN_SENSOR3_CFG) +} PIN_SENSOR3_CFG; + +/** + PIN config for Sensor4 + + @note For pinmux_init() with PIN_FUNC_SENSOR4.\n + For example, you can use {PIN_FUNC_SENSOR4, xxxx} +*/ +typedef enum +{ + PIN_SENSOR4_CFG_NONE, + PIN_SENSOR4_CFG_8BITS = 0x01, ///< Backward compatible + PIN_SENSOR4_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR4_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR4_CFG_MCLK2 = 0x10, ///< MCLK2 + + ENUM_DUMMY4WORD(PIN_SENSOR4_CFG) +} PIN_SENSOR4_CFG; + +/** + PIN config for Sensor5 + + @note For pinmux_init() with PIN_FUNC_SENSOR5.\n + For example, you can use {PIN_FUNC_SENSOR5, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR5_CFG_NONE, + PIN_SENSOR5_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR5_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR5_CFG_MCLK2 = 0x10, ///< MCLK2 + + ENUM_DUMMY4WORD(PIN_SENSOR5_CFG) +} PIN_SENSOR5_CFG; + +/** + PIN config for Sensor6 + + @note For pinmux_init() with PIN_FUNC_SENSOR6.\n + For example, you can use {PIN_FUNC_SENSOR6, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR6_CFG_NONE, + PIN_SENSOR6_CFG_8BITS = 0x01, ///< 8 bit sensor + PIN_SENSOR6_CFG_16BITS= 0x02, ///< 16 bit sensor + PIN_SENSOR6_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR6_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR6_CFG_MCLK2 = 0x10, ///< + + ENUM_DUMMY4WORD(PIN_SENSOR6_CFG) +} PIN_SENSOR6_CFG; + +/** + PIN config for Sensor7 + + @note For pinmux_init() with PIN_FUNC_SENSOR7.\n + For example, you can use {PIN_FUNC_SENSOR7, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR7_CFG_NONE, + PIN_SENSOR7_CFG_8BITS = 0x01, ///< 8 bit sensor + PIN_SENSOR7_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR7_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR7_CFG_MCLK2 = 0x10, ///< + + ENUM_DUMMY4WORD(PIN_SENSOR7_CFG) +} PIN_SENSOR7_CFG; + +/** + PIN config for Sensor8 + + @note For pinmux_init() with PIN_FUNC_SENSOR8.\n + For example, you can use {PIN_FUNC_SENSOR8, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR8_CFG_NONE, + PIN_SENSOR8_CFG_8BITS = 0x01, ///< 8 bit sensor + PIN_SENSOR8_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR8_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR8_CFG_MCLK2 = 0x10, ///< + + ENUM_DUMMY4WORD(PIN_SENSOR8_CFG) +} PIN_SENSOR8_CFG; + + +/** + PIN config for MIPI/LVDS + + @note For pinmux_init() with PIN_FUNC_MIPI_LVDS.\n + For example, you can use {PIN_FUNC_MIPI_LVDS, PIN_MIPI_LVDS_CFG_CLK0|PIN_MIPI_LVDS_CFG_DAT0|PIN_MIPI_LVDS_CFG_DAT4|PIN_MIPI_LVDS_CFG_DAT7|PIN_MIPI_LVDS_CFG_DAT9}\n + to declare LVDS/MIPI connect sensor with CLK0/D0/D4/D7/D9 lanes. +*/ +typedef enum +{ + PIN_MIPI_LVDS_CFG_NONE, + + PIN_MIPI_LVDS_CFG_CLK0 = 0x1, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK1 = 0x2, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK2 = 0x4, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK3 = 0x8, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK4 = 0x10, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK5 = 0x20, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK6 = 0x40, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK7 = 0x80, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + + PIN_MIPI_LVDS_CFG_DAT0 = 0x100, ///< DATA lane 0. Enable HSI_D0N/HSI_D0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT1 = 0x200, ///< DATA lane 1. Enable HSI_D1N/HSI_D1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT2 = 0x400, ///< DATA lane 2. Enable HSI_D2N/HSI_D2P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT3 = 0x800, ///< DATA lane 3. Enable HSI_D3N/HSI_D3P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT4 = 0x1000, ///< DATA lane 4. Enable HSI_D4N/HSI_D4P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT5 = 0x2000, ///< DATA lane 5. Enable HSI_D5N/HSI_D5P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT6 = 0x4000, ///< DATA lane 6. Enable HSI_D6N/HSI_D6P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT7 = 0x8000, ///< DATA lane 7. Enable HSI_D7N/HSI_D7P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT8 = 0x10000, ///< Backward compatible + PIN_MIPI_LVDS_CFG_DAT9 = 0x20000, ///< Backward compatible + + ENUM_DUMMY4WORD(PIN_MIPI_LVDS_CFG) +} PIN_MIPI_LVDS_CFG; + +/** + PIN config for I2C + + @note For pinmux_init() with PIN_FUNC_I2C.\n + For example, you can use {PIN_FUNC_I2C, PIN_I2C_CFG_CH1|PIN_I2C_CFG_CH1_2ND_PINMUX}\n + to declare I2C channel1 both output to 1st and 2nd pinmux location. +*/ +typedef enum +{ + PIN_I2C_CFG_NONE, + PIN_I2C_CFG_CH1 = 0x1, ///< Enable channel 1. + PIN_I2C_CFG_CH1_2ND_PINMUX = 0x2, ///< Enable 2nd pinmux of channel 1. + PIN_I2C_CFG_CH2 = 0x10, ///< Enable channel 2. + PIN_I2C_CFG_CH2_2ND_PINMUX = 0x20, ///< Enable 2nd pinmux of channel 2. + PIN_I2C_CFG_CH3 = 0x100, ///< Enable channel 3. + PIN_I2C_CFG_CH3_2ND_PINMUX = 0x200, ///< Enable 2nd pinmux of channel 3. + PIN_I2C_CFG_CH3_3RD_PINMUX = 0x400, ///< Enable 3nd pinmux of channel 3. + PIN_I2C_CFG_CH4 = 0x1000, ///< Enable channel 4. + PIN_I2C_CFG_CH4_2ND_PINMUX = 0x2000, ///< Enable 2nd pinmux of channel 4. + PIN_I2C_CFG_CH4_3RD_PINMUX = 0x4000, ///< Enable 3nd pinmux of channel 4. + PIN_I2C_CFG_CH4_4TH_PINMUX = 0x8000, ///< Enable 4th pinmux of channel 4. + PIN_I2C_CFG_CH5 = 0x10000, ///< Enable channel 5. + PIN_I2C_CFG_CH5_2ND_PINMUX = 0x20000, ///< Enable 2nd pinmux of channel 5. + + ENUM_DUMMY4WORD(PIN_I2C_CFG) +} PIN_I2C_CFG; + +/** + PIN config for SIF + + *note For pinmux_init() with PIN_FUNC_SIF.\n + For example, you can use {PIN_FUNC_SIF, PIN_SIF_CFG_CH0|PIN_SIF_CFG_CH2}\n + to declare SIF channel0 and channel2 pinmux are enabled. +*/ +typedef enum +{ + PIN_SIF_CFG_NONE, + + PIN_SIF_CFG_CH0 = 0x01, ///< Enable SIF channel 0. Enable SN_CS0/SN_SCK0/SN_DAT0 (L_GPIO 27/28/29) + PIN_SIF_CFG_CH0_2ND_PINMUX = 0x02, ///< Enable SIF channel 0 2'nd pinmux. Enable SN_CS0/SN_SCK0/SN_SAT0 (P_GPIO 16/18/19) + PIN_SIF_CFG_CH0_3RD_PINMUX = 0x04, ///< Enable SIF channel 0 3'rd pinmux. Enable SN_CS0/SN_SCK0/SN_SAT0 (P_GPIO 17/18/19) + + PIN_SIF_CFG_CH1 = 0x08, ///< Enable SIF channel 1. Enable SN_CS1/SN_SCK1/SN_DAT1 (L_GPIO 30/31/32) + PIN_SIF_CFG_CH1_2ND_PINMUX = 0x10, ///< Backward compatible + + PIN_SIF_CFG_CH2 = 0x20, ///< Enable SIF channel 2. Enable SB_CS2/SB_CK23/SB_DAT23 (P_GPIO 30/32/33) + PIN_SIF_CFG_CH2_2ND_PINMUX = 0x40, ///< Enable SIF channel 2 2'nd pinmux. Enable SB_CS2/SB_CK23/SB_DAT23 (P_GPIO 8/10/11) + + PIN_SIF_CFG_CH3 = 0x80, ///< Enable SIF channel 3. Enable SB_CS3/SB_CK23/SB_DAT23 (P_GPIO 31/32/33) + PIN_SIF_CFG_CH3_2ND_PINMUX = 0x100, ///< Enable SIF channel 3 2'nd pinmux. Enable SB_CS2/SB_CK23/SB_DAT23 (P_GPIO 9/10/11) + + PIN_SIF_CFG_CH4 = 0x200, ///< Enable SIF channel 4. Enable SB_CS4/SB_CK45/SB_DAT45 (P_GPIO 24/26/27) + + PIN_SIF_CFG_CH5 = 0x400, ///< Enable SIF channel 5. Enable SB_CS5/SB_CK45/SB_DAT45 (P_GPIO 25/26/27) + + PIN_SIF_CFG_CH6 = 0x800, ///< Enable SIF channel 6. Enable SB_CS6/SB_CK67/SB_DAT67 (S_GPIO 8/9/10) + + PIN_SIF_CFG_CH7 = 0x1000, ///< Enable SIF channel 7. Enable SB_CS7/SB_CK67/SB_DAT67 (S_GPIO 11/8/9) + + ENUM_DUMMY4WORD(PIN_SIF_CFG) +} PIN_SIF_CFG; + +/** + PIN config for UART + + @note For pinmux_init() with PIN_FUNC_UART.\n + For example, you can use {PIN_FUNC_UART, PIN_UART_CFG_CH1}\n + to declare UART1 pinmux is enabled. +*/ +typedef enum +{ + PIN_UART_CFG_NONE, + + PIN_UART_CFG_CH1 = 0x01, ///< Enable channel 1. Enable UART TX and RX + PIN_UART_CFG_CH1_TX = 0x02, ///< Enalbe channel 1. Enable only UART_TX + + PIN_UART_CFG_CH2 = 0x04, ///< Enable channel 2. Enable UART2 TX and RX + PIN_UART_CFG_CH2_CTSRTS = 0x08, ///< Enable channel 2 HW handshake. Enable UART2 CTS and RTS + PIN_UART_CFG_CH2_2ND = 0x10, ///< Enable channel 2 to 2ND pinmux (UART2_2) + + PIN_UART_CFG_CH3 = 0x20, ///< Enable channel 3. Enable UART3 TX and RX + PIN_UART_CFG_CH3_CTSRTS = 0x40, ///< Enable channel 3 HW handshake. Enable UART3 CTS and RTS + PIN_UART_CFG_CH3_2ND = 0x80, ///< Enable channel 3 to 2ND pinmux (UART3_2) + + PIN_UART_CFG_CH4 = 0x100, ///< Enable channel 4. Enable UART4 TX and RX + PIN_UART_CFG_CH4_CTSRTS = 0x200, ///< Enable channel 4 HW handshake. Enable UART4 CTS and RTS + PIN_UART_CFG_CH4_2ND = 0x400, ///< Enable channel 4 to 2ND pinmux (UART4_2) + + ENUM_DUMMY4WORD(PIN_UART_CFG) +} PIN_UART_CFG; + +/** + PIN config for SPI + + @note For pinmux_init() with PIN_FUNC_SPI.\n + For example, you can use {PIN_FUNC_SPI, PIN_SPI_CFG_CH1|PIN_SPI_CFG_CH3}\n + to declare SPI channel1 and channel3 are enabled. +*/ +typedef enum +{ + PIN_SPI_CFG_NONE, + + PIN_SPI_CFG_CH1 = 0x1, ///< Enable channel 1. Enable SPI_DO/SPI_CLK/SPI_CS on MC[0]/MC[2]/MC8 (C_GPIO[0]/C_GPIO[2]/C_GPIO[8]) + PIN_SPI_CFG_CH1_2BITS = 0x2, ///< Enable channel 1 with 2 bits mode. Enable SPI_DO/SPI_DI/SPI_CLK/SPI_CS on MC[0..2]/MC8 (C_GPIO[0..2]/C_GPIO[8]) + PIN_SPI_CFG_CH1_4BITS = 0x4, ///< Backward compatible + PIN_SPI_CFG_CH1_2ND_PINMUX = 0x8, ///< Enable 2nd pinmux of channel 1. + + PIN_SPI_CFG_CH2 = 0x10, ///< Enable channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO on SPI_CS/SPI_CLK/SPI_DO(P_GPIO[35..37]) + PIN_SPI_CFG_CH2_2BITS = 0x20, ///< Enable channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO/SPI2_DI on SPI_CS/SPI_CLK/SPI_DO/SPI_DI(P_GPIO[35..38]) + PIN_SPI_CFG_CH2_2ND_PINMUX = 0x40, ///< Enable 2nd pinmux of channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO/SPI2_DI on (P_GPIO[16..19]) + PIN_SPI_CFG_CH2_3RD_PINMUX = 0x80, ///< Enable 3rd pinmux of channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO/SPI2_DI on (P_GPIO[16..19]) + + + PIN_SPI_CFG_CH3 = 0x100, ///< Enable channel 3. Eanble SPI3_CS/SPI3_CLK/SPI3_DO on SB_CS2/SB_CK23/SB_DAT23 (P_GPIO[23]/P_GPIO[25..26]) + PIN_SPI_CFG_CH3_2BITS = 0x200, ///< Enable channel 3. Eanble SPI3_CS/SPI3_DI/SPI3_CLK/SPI3_DO on SB_CS2/SB_CS3/SB_CK23/SB_DAT23 (P_GPIO[23..26]) + PIN_SPI_CFG_CH3_2ND_PINMUX = 0x400, ///< Enable 2nd pinmux of channel 3. Enable SPI3_CLK/SPI3_CS/SPI3_DO/SPI3_DI on PWM[12..15] (P_GPIO[12..15]) + PIN_SPI_CFG_CH3_3RD_PINMUX = 0x800, ///< Backward compatible + PIN_SPI_CFG_CH3_RDY = 0x1000, + PIN_SPI_CFG_CH3_RDY_2ND_PINMUX = 0x2000, + + PIN_SPI_CFG_CH4 = 0x10000, ///< Enable channel 4. Eanble SPI4_CS/SPI4_CLK/SPI4_DO on MC[28..29]/MC[31] (C_GPIO[28..29]/C_GPIO[31]) + PIN_SPI_CFG_CH4_2BITS = 0x20000, ///< Enable channel 4. Eanble SPI4_CS/SPI4_DI/SPI4_CLK/SPI4_DO on MC[28..31] (C_GPIO[28..31]) + PIN_SPI_CFG_CH4_2ND_PINMUX = 0x40000, ///< Enable 2nd pinmux of channel 4. Enable SPI4_CLK/SPI4_CS/SPI4_DO/SPI4_DI on PWM[8..11] (P_GPIO[8..11]) + PIN_SPI_CFG_CH4_RDY = 0x80000, ///< Backward compatible + PIN_SPI_CFG_CH4_3RD_PINMUX = 0x100000, ///< Enable 3rd pinmux of channel 4. + + PIN_SPI_CFG_CH5 = 0x1000000,///< Backward compatible + PIN_SPI_CFG_CH5_2BITS = 0x2000000,///< Backward compatible + PIN_SPI_CFG_CH5_2ND_PINMUX = 0x4000000,///< Backward compatible + + ENUM_DUMMY4WORD(PIN_SPI_CFG) +} PIN_SPI_CFG; + +/** + PIN config for REMOTE + + @note For pinmux_init() with PIN_FUNC_REMOTE.\n + For example, you can use {PIN_FUNC_REMOTE, PIN_REMOTE_CFG_CH1}\n + to declare remote pinmux is enabled. +*/ +typedef enum +{ + PIN_REMOTE_CFG_NONE, + PIN_REMOTE_CFG_CH1, ///< Enable remote rx channel 1. Enable REMOTE_RX (on P_GPIO[39]) + + ENUM_DUMMY4WORD(PIN_REMOTE_CFG) +} PIN_REMOTE_CFG; + +/** + PIN config for PWM + + @note For pinmux_init() with PIN_FUNC_PWM.\n + For example, you can use {PIN_FUNC_PWM, PIN_PWM_CFG_PWM0|PIN_PWM_CFG_PWM1|PIN_PWM_CFG_PWM2|PIN_PWM_CFG_PWM3}\n + to declare your system need PWM channel0/1/2/3. +*/ +typedef enum +{ + PIN_PWM_CFG_NONE, + PIN_PWM_CFG_PWM0 = 0x01, ///< Enable PWM0 (on P_GPIO[0]) + PIN_PWM_CFG_PWM1 = 0x02, ///< Enable PWM1 (on P_GPIO[1]) + PIN_PWM_CFG_PWM2 = 0x04, ///< Enable PWM2 (on P_GPIO[2]) + PIN_PWM_CFG_PWM3 = 0x08, ///< Enable PWM3 (on P_GPIO[3]) + PIN_PWM_CFG_PWM4 = 0x10, ///< Enable PWM4 (on P_GPIO[4]) + PIN_PWM_CFG_PWM5 = 0x20, ///< Enable PWM5 (on P_GPIO[5]) + PIN_PWM_CFG_PWM6 = 0x40, ///< Enable PWM6 (on P_GPIO[6]) + PIN_PWM_CFG_PWM7 = 0x80, ///< Enable PWM7 (on P_GPIO[7]) + PIN_PWM_CFG_PWM8 = 0x100, ///< Enable PWM8 (on P_GPIO[8]) + PIN_PWM_CFG_PWM9 = 0x200, ///< Enable PWM9 (on P_GPIO[9]) + PIN_PWM_CFG_PWM10= 0x400, ///< Enable PWM10 (on P_GPIO[10]) + PIN_PWM_CFG_PWM11= 0x800, ///< Enable PWM11 (on P_GPIO[11]) + PIN_PWM_CFG_PWM12= 0x1000, ///< Enable PWM12 (on P_GPIO[12]) + PIN_PWM_CFG_PWM13= 0x2000, ///< Enable PWM13 (on P_GPIO[13]) + PIN_PWM_CFG_PWM14= 0x4000, ///< Enable PWM14 (on P_GPIO[14]) + PIN_PWM_CFG_PWM15= 0x8000, ///< Enable PWM15 (on P_GPIO[15]) + PIN_PWM_CFG_PWM16= 0x10000, ///< Enable PWM16 (on P_GPIO[16]) + PIN_PWM_CFG_PWM17= 0x20000, ///< Enable PWM17 (on P_GPIO[17]) + PIN_PWM_CFG_PWM18= 0x40000, ///< Enable PWM18 (on P_GPIO[18]) + PIN_PWM_CFG_PWM19= 0x80000, ///< Enable PWM19 (on P_GPIO[19]) + + PIN_PWM_CFG_CCNT = 0x1000000, ///< Enable PICNT_1 + PIN_PWM_CFG_CCNT_2ND = 0x2000000, ///< Enable PICNT_2 + PIN_PWM_CFG_CCNT2 = 0x4000000, ///< Enable PICNT2_1 + PIN_PWM_CFG_CCNT2_2ND = 0x8000000, ///< Enable PICNT2_2 + PIN_PWM_CFG_CCNT3 = 0x10000000, ///< Enable PICNT3 + PIN_PWM_CFG_CCNT3_2ND = 0x20000000, ///< Enable PICNT3_2 + PIN_PWM_CFG_CCNT4 = 0x40000000, ///< Enable PICNT4_1 + PIN_PWM_CFG_CCNT4_2ND = 0x80000000, ///< Enable PICNT4_2 + + ENUM_DUMMY4WORD(PIN_PWM_CFG) +} PIN_PWM_CFG; + +/** + PIN config for AUDIO + + @note For pinmux_init() with PIN_FUNC_AUDIO.\n + For example, you can use {PIN_FUNC_AUDIO, PIN_AUDIO_CFG_I2S|PIN_AUDIO_CFG_MCLK}\n + to declare pinmux of I2S and I2S MCLK are enabled. +*/ +typedef enum +{ + PIN_AUDIO_CFG_NONE, + PIN_AUDIO_CFG_I2S = 0x01, ///< Enable I2S channel. Enable I2S_BCK/I2S_FCK/I2S_DO/I2S_DI/ (on P_GPIO[31..34]) + PIN_AUDIO_CFG_I2S_2ND_PINMUX = 0x02,///< Backward compatible + + PIN_AUDIO_CFG_MCLK = 0x10, ///< Enable audio MCLK. Enable I2S_MCLK (on P_GPIO[20]) + PIN_AUDIO_CFG_MCLK_2ND_PINMUX = 0x20,///< Backward compatible + + ENUM_DUMMY4WORD(PIN_AUDIO_CFG) +} PIN_AUDIO_CFG; + +/** + PIN config of LCD modes + + @note For pinmux_init() with PIN_FUNC_LCD or PIN_FUNC_LCD2.\n + For example, you can use {PIN_FUNC_LCD, PINMUX_DISPMUX_SEL_LCD | PINMUX_LCDMODE_RGB_SERIAL}\n + to tell display object that PIN_FUNC_LCD is located on primary LCD pinmux,\n + and it's LCD mode is RGB serial. +*/ +typedef enum +{ + PINMUX_LCDMODE_RGB_SERIAL = 0, ///< LCD MODE is RGB Serial or UPS051 + PINMUX_LCDMODE_RGB_PARALL = 1, ///< LCD MODE is RGB Parallel (888) + PINMUX_LCDMODE_YUV640 = 2, ///< LCD MODE is YUV640 + PINMUX_LCDMODE_YUV720 = 3, ///< LCD MODE is YUV720 + PINMUX_LCDMODE_RGBD360 = 4, ///< LCD MODE is RGB Dummy 360 + PINMUX_LCDMODE_RGBD320 = 5, ///< LCD MODE is RGB Dummy 320 + PINMUX_LCDMODE_RGB_THROUGH = 6, ///< LCD MODE is RGB through mode + PINMUX_LCDMODE_CCIR601 = 7, ///< LCD MODE is CCIR601 + PINMUX_LCDMODE_CCIR656 = 8, ///< LCD MODE is CCIR656 + PINMUX_LCDMODE_RGB_PARALL666 = 9, ///< LCD MODE is RGB Parallel 666 + PINMUX_LCDMODE_RGB_PARALL565 = 10, ///< LCD MODE is RGB Parallel 565 + PINMUX_LCDMODE_RGB_PARALL_DELTA = 11, ///< LCD MODE is RGB Parallel Delta + PINMUX_LCDMODE_MIPI = 12, ///< LCD MODE is MIPI Display + + PINMUX_LCDMODE_MI_OFFSET = 32, ///< Memory LCD MODE offset + PINMUX_LCDMODE_MI_FMT0 = 32+0, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT1 = 32+1, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT2 = 32+2, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT3 = 32+3, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT4 = 32+4, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT5 = 32+5, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT6 = 32+6, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT7 = 32+7, ///< LCD MODE is Memory(Parallel Interface) 9bits + PINMUX_LCDMODE_MI_FMT8 = 32+8, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT9 = 32+9, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT10 = 32+10, ///< LCD MODE is Memory(Parallel Interface) 18bits + PINMUX_LCDMODE_MI_FMT11 = 32+11, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT12 = 32+12, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT13 = 32+13, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT14 = 32+14, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_SERIAL_BI = 32+20, ///< LCD MODE is Serial Interface bi-direction + PINMUX_LCDMODE_MI_SERIAL_SEP = 32+21, ///< LCD MODE is Serial Interface separation + + PINMUX_LCDMODE_AUTO_PINMUX = 0x01<<22, ///< Set display device to GPIO mode when display device is closed. Select this filed will inform display object to switch to GPIO when display device is closed. + + + PINMUX_HDMIMODE_OFFSET = 64, ///< HDMI MODE offset + PINMUX_HDMIMODE_640X480P60 = 64+1, ///< HDMI Video format is 640x480 & Progressive 60fps + PINMUX_HDMIMODE_720X480P60 = 64+2, ///< HDMI Video format is 720x480 & Progressive 60fps & 4:3 + PINMUX_HDMIMODE_720X480P60_16X9 = 64+3, ///< HDMI Video format is 720x480 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_1280X720P60 = 64+4, ///< HDMI Video format is 1280x720 & Progressive 60fps + PINMUX_HDMIMODE_1920X1080I60 = 64+5, ///< HDMI Video format is 1920x1080 & Interlaced 60fps + PINMUX_HDMIMODE_720X480I60 = 64+6, ///< HDMI Video format is 720x480 & Interlaced 60fps + PINMUX_HDMIMODE_720X480I60_16X9 = 64+7, ///< HDMI Video format is 720x480 & Interlaced 60fps & 16:9 + PINMUX_HDMIMODE_720X240P60 = 64+8, ///< HDMI Video format is 720x240 & Progressive 60fps + PINMUX_HDMIMODE_720X240P60_16X9 = 64+9, ///< HDMI Video format is 720x240 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_1440X480I60 = 64+10, ///< HDMI Video format is 1440x480 & Interlaced 60fps + PINMUX_HDMIMODE_1440X480I60_16X9 = 64+11, ///< HDMI Video format is 1440x480 & Interlaced 60fps & 16:9 + PINMUX_HDMIMODE_1440X240P60 = 64+12, ///< HDMI Video format is 1440x240 & Progressive 60fps + PINMUX_HDMIMODE_1440X240P60_16X9 = 64+13, ///< HDMI Video format is 1440x240 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_1440X480P60 = 64+14, ///< HDMI Video format is 1440x480 & Progressive 60fps + PINMUX_HDMIMODE_1440X480P60_16X9 = 64+15, ///< HDMI Video format is 1440x480 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_720X576P50 = 64+17, ///< HDMI Video format is 720x576 & Progressive 50fps + PINMUX_HDMIMODE_720X576P50_16X9 = 64+18, ///< HDMI Video format is 720x576 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1280X720P50 = 64+19, ///< HDMI Video format is 1280x720 & Progressive 50fps + PINMUX_HDMIMODE_1920X1080I50 = 64+20, ///< HDMI Video format is 1920x1080 & Interlaced 50fps + PINMUX_HDMIMODE_720X576I50 = 64+21, ///< HDMI Video format is 720x576 & Interlaced 50fps + PINMUX_HDMIMODE_720X576I50_16X9 = 64+22, ///< HDMI Video format is 720x576 & Interlaced 50fps & 16:9 + PINMUX_HDMIMODE_720X288P50 = 64+23, ///< HDMI Video format is 720x288 & Progressive 50fps + PINMUX_HDMIMODE_720X288P50_16X9 = 64+24, ///< HDMI Video format is 720x288 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1440X576I50 = 64+25, ///< HDMI Video format is 1440x576 & Interlaced 50fps + PINMUX_HDMIMODE_1440X576I50_16X9 = 64+26, ///< HDMI Video format is 1440x576 & Interlaced 50fps & 16:9 + PINMUX_HDMIMODE_1440X288P50 = 64+27, ///< HDMI Video format is 1440x288 & Progressive 50fps + PINMUX_HDMIMODE_1440X288P50_16X9 = 64+28, ///< HDMI Video format is 1440x288 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1440X576P50 = 64+29, ///< HDMI Video format is 1440x576 & Progressive 50fps + PINMUX_HDMIMODE_1440X576P50_16X9 = 64+30, ///< HDMI Video format is 1440x576 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1920X1080P50 = 64+31, ///< HDMI Video format is 1920x1080 & Progressive 50fps + PINMUX_HDMIMODE_1920X1080P24 = 64+32, ///< HDMI Video format is 1920x1080 & Progressive 24fps + PINMUX_HDMIMODE_1920X1080P25 = 64+33, ///< HDMI Video format is 1920x1080 & Progressive 25fps + PINMUX_HDMIMODE_1920X1080P30 = 64+34, ///< HDMI Video format is 1920x1080 & Progressive 30fps + PINMUX_HDMIMODE_1920X1080I50_VT1250 = 64+39, ///< HDMI Video format is 1920x1080 & Interlaced 50fps & V-total is 1250 lines + PINMUX_HDMIMODE_1920X1080I100 = 64+40, ///< HDMI Video format is 1920x1080 & Interlaced 100fps + PINMUX_HDMIMODE_1280X720P100 = 64+41, ///< HDMI Video format is 1280X720 & Progressive 100fps + PINMUX_HDMIMODE_720X576P100 = 64+42, ///< HDMI Video format is 720X576 & Progressive 100fps + PINMUX_HDMIMODE_720X576P100_16X9 = 64+43, ///< HDMI Video format is 720X576 & Progressive 100fps & 16:9 + PINMUX_HDMIMODE_720X576I100 = 64+44, ///< HDMI Video format is 720X576 & Interlaced 100fps + PINMUX_HDMIMODE_720X576I100_16X9 = 64+45, ///< HDMI Video format is 720X576 & Interlaced 100fps & 16:9 + PINMUX_HDMIMODE_1920X1080I120 = 64+46, ///< HDMI Video format is 1920X1080 & Interlaced 120fps + PINMUX_HDMIMODE_1280X720P120 = 64+47, ///< HDMI Video format is 1280X720 & Progressive 120fps + PINMUX_HDMIMODE_720X480P120 = 64+48, ///< HDMI Video format is 720X480 & Progressive 120fps + PINMUX_HDMIMODE_720X480P120_16X9 = 64+49, ///< HDMI Video format is 720X480 & Progressive 120fps & 16:9 + PINMUX_HDMIMODE_720X480I120 = 64+50, ///< HDMI Video format is 720X480 & Interlaced 120fps + PINMUX_HDMIMODE_720X480I120_16X9 = 64+51, ///< HDMI Video format is 720X480 & Interlaced 120fps & 16:9 + PINMUX_HDMIMODE_720X576P200 = 64+52, ///< HDMI Video format is 720X576 & Progressive 200fps + PINMUX_HDMIMODE_720X576P200_16X9 = 64+53, ///< HDMI Video format is 720X576 & Progressive 200fps & 16:9 + PINMUX_HDMIMODE_720X576I200 = 64+54, ///< HDMI Video format is 720X576 & Interlaced 200fps + PINMUX_HDMIMODE_720X576I200_16X9 = 64+55, ///< HDMI Video format is 720X576 & Interlaced 200fps & 16:9 + PINMUX_HDMIMODE_720X480P240 = 64+56, ///< HDMI Video format is 720X480 & Progressive 240fps + PINMUX_HDMIMODE_720X480P240_16X9 = 64+57, ///< HDMI Video format is 720X480 & Progressive 240fps & 16:9 + PINMUX_HDMIMODE_720X480I240 = 64+58, ///< HDMI Video format is 720X480 & Interlaced 240fps + PINMUX_HDMIMODE_720X480I240_16X9 = 64+59, ///< HDMI Video format is 720X480 & Interlaced 240fps & 16:9 + + PINMUX_DSI_1_LANE_CMD_MODE_RGB565 = 128+0, ///< DSI command mode with RGB565 format + PINMUX_DSI_1_LANE_CMD_MODE_RGB666P = 128+1, ///< DSI command mode with RGB666 packed + PINMUX_DSI_1_LANE_CMD_MODE_RGB666L = 128+2, ///< DSI command mode with RGB666 loosely + PINMUX_DSI_1_LANE_CMD_MODE_RGB888 = 128+3, ///< DSI command mode with RGB888 + + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB565 = 128+4, ///< DSI video sync pulse mode with RGB565 format + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB666P = 128+5, ///< DSI video sync pulse mode with RGB666 packed + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB666L = 128+6, ///< DSI video sync pulse mode with RGB666 loosely + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB888 = 128+7, ///< DSI video sync pulse mode with RGB888 + + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB565 = 128+8, ///< DSI video sync event burst mode with RGB565 format + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB666P = 128+9, ///< DSI video sync event burst mode with RGB666 packed + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB666L = 128+10,///< DSI video sync event burst mode with RGB666 loosely + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB888 = 128+11,///< DSI video sync event burst mode with RGB888 + + PINMUX_DSI_2_LANE_CMD_MODE_RGB565 = 128+12,///< DSI command mode with RGB565 format + PINMUX_DSI_2_LANE_CMD_MODE_RGB666P = 128+13,///< DSI command mode with RGB666 packed + PINMUX_DSI_2_LANE_CMD_MODE_RGB666L = 128+14,///< DSI command mode with RGB666 loosely + PINMUX_DSI_2_LANE_CMD_MODE_RGB888 = 128+15,///< DSI command mode with RGB888 + + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB565 = 128+16,///< DSI video sync pulse mode with RGB565 format + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB666P = 128+17,///< DSI video sync pulse mode with RGB666 packed + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB666L = 128+18,///< DSI video sync pulse mode with RGB666 loosely + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB888 = 128+19,///< DSI video sync pulse mode with RGB888 + + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB565 = 128+20,///< DSI video sync event burst mode with RGB565 format + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB666P = 128+21,///< DSI video sync event burst mode with RGB666 packed + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB666L = 128+22,///< DSI video sync event burst mode with RGB666 loosely + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB888 = 128+23,///< DSI video sync event burst mode with RGB888 + + PINMUX_DSI_4_LANE_CMD_MODE_RGB565 = 128+24,///< DSI command mode with RGB565 format + PINMUX_DSI_4_LANE_CMD_MODE_RGB666P = 128+25,///< DSI command mode with RGB666 packed + PINMUX_DSI_4_LANE_CMD_MODE_RGB666L = 128+26,///< DSI command mode with RGB666 loosely + PINMUX_DSI_4_LANE_CMD_MODE_RGB888 = 128+27,///< DSI command mode with RGB888 + + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB565 = 128+28,///< DSI video sync pulse mode with RGB565 format + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB666P = 128+29,///< DSI video sync pulse mode with RGB666 packed + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB666L = 128+30,///< DSI video sync pulse mode with RGB666 loosely + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB888 = 128+31,///< DSI video sync pulse mode with RGB888 + + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB565 = 128+32,///< DSI video sync event burst mode with RGB565 format + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB666P = 128+33,///< DSI video sync event burst mode with RGB666 packed + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB666L = 128+34,///< DSI video sync event burst mode with RGB666 loosely + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB888 = 128+35,///< DSI video sync event burst mode with RGB888 + + + + ENUM_DUMMY4WORD(PINMUX_LCDINIT) +} PINMUX_LCDINIT; + +/** + PIN config for Parallel MI + + @note For pinmux_init() with PIN_FUNC_LCD or PIN_FUNC_LCD2.\n + For example, you can use {PIN_FUNC_LCD, PINMUX_DISPMUX_SEL_LCD|PINMUX_PMI_CFG_NORMAL|PINMUX_LCDMODE_MI_FMT0}\n + to tell display object that PIN_FUNC_LCD is bound to MI and format is FMT0,\n + and MI is located at primary location. +*/ +typedef enum +{ + PINMUX_PMI_CFG_NORMAL = 0x00, ///< Normal Parallel MI location (at LCD) + PINMUX_PMI_CFG_2ND_PINMUX = 0x01<<26, ///< Secondary Parallel MI location (at LGPIO[12..25]) + + PINMUX_PMI_CFG_MASK = 0x03<<26, + ENUM_DUMMY4WORD(PINMUX_PMI_CFG) +} PINMUX_PMI_CFG; + +/** + PIN config for TV/HDMI + + @note For pinmux_init() for PIN_FUNC_TV or PIN_FUNC_HDMI.\n + For example, you can use {PIN_FUNC_HDMI, PINMUX_TV_HDMI_CFG_NORMAL|PINMUX_HDMIMODE_1280X720P60}\n + to tell display object that HDMI activation will disable PANEL,\n + and HDMI mode is 1280x720 P60. +*/ +typedef enum +{ + PINMUX_TV_HDMI_CFG_GPIO = 0x00, ///< TV activation will disable PINMUX to GPIO + PINMUX_TV_HDMI_CFG_NORMAL = 0x00, ///< TV activation will disable PANEL which shared the same IDE + PINMUX_TV_HDMI_CFG_PINMUX_ON = 0x01<<28, ///< TV activation will keep PINMUX setting + + PINMUX_TV_HDMI_CFG_MASK = 0x03<<28, + ENUM_DUMMY4WORD(PINMUX_TV_HDMI_CFG) +} PINMUX_TV_HDMI_CFG; + +/** + PIN config for HDMI + + @note For pinmux_init() for PIN_FUNC_HDMI.\n + For example, you can use {PIN_FUNC_HDMI, PINMUX_HDMI_CFG_CEC|PINMUX_TV_HDMI_CFG_NORMAL}\n + to declare HDMI CEC pinmux is enabled. +*/ +typedef enum +{ + PINMUX_HDMI_CFG_GPIO = 0x00, ///< HDMI specific PIN to GPIO + PINMUX_HDMI_CFG_HOTPLUG = 0x01<<26, ///< HDMI HOTPLUG. Enable HDMI_PLUG (on P_GPIO[30]) + PINMUX_HDMI_CFG_CEC = 0x02<<26, ///< HDMI CEC. Enable HDMI_CEC (on P_GPIO[27]) + + PINMUX_HDMI_CFG_MASK = 0x03<<26, + ENUM_DUMMY4WORD(PINMUX_HDMI_CFG) +} PINMUX_HDMI_CFG; + +/** + PIN location of LCD + + @note For pinmux_init() with PIN_FUNC_LCD or PIN_FUNC_LCD2.\n + For example, you can use {PIN_FUNC_LCD, PINMUX_DISPMUX_SEL_LCD2|PINMUX_LCDMODE_XXX}\n + to tell display object that PIN_FUNC_LCD is located on secondary LCD pinmux. +*/ +typedef enum +{ + PINMUX_DISPMUX_SEL_NONE = 0x00<<28, ///< PINMUX none + PINMUX_DISPMUX_SEL_LCD = 0x01<<28, ///< PINMUX at LCD interface + PINMUX_DISPMUX_SEL_LCD2 = 0x02<<28, ///< PINMUX at LCD2 interface + + PINMUX_DISPMUX_SEL_MASK = 0x03<<28, + ENUM_DUMMY4WORD(PINMUX_DISPMUX_SEL) +} PINMUX_DISPMUX_SEL; + +/** + PIN config for ETH + + @note For pinmux_init() for PIN_FUNC_ETH.\n + For example, you can use {PIN_FUNC_ETH, PINMUX_ETH_CFG_MII}\n + to select USB as device. +*/ +typedef enum +{ + PIN_ETH_CFG_NONE = 0x00, ///< PINMUX none + PIN_ETH_CFG_MII = 0x01, ///< ETH MII + PIN_ETH_CFG_RMII = 0x02, ///< ETH RMII + PIN_ETH_CFG_GMII = 0x04, ///< ETH GMII + PIN_ETH_CFG_RGMII = 0x08, ///< ETH RGMII + PIN_ETH_CFG_REVMII_10_100 = 0x10, ///< ETH REVMII_10_100 + PIN_ETH_CFG_REVMII_10_1000 = 0x20, ///< ETH REVMII_10_1000 + + ENUM_DUMMY4WORD(PINMUX_ETH_CFG) +} PINMUX_ETH_CFG; + + +/** + Pinmux Function identifier + + @note For pinmux_getDispMode(), pinmux_setPinmux(). +*/ +typedef enum +{ + PINMUX_FUNC_ID_LCD, ///< 1st Panel (LCD), pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + ///< - @b PINMUX_LCD_SEL_CCIR656 + ///< - @b PINMUX_LCD_SEL_CCIR601 + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_6BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_8BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_YCbCr_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_9BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDIO + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDI_SDO + ///< ORed with + ///< - @b PINMUX_LCD_SEL_DE_ENABLE + ///< - @b PINMUX_LCD_SEL_TE_ENABLE + PINMUX_FUNC_ID_LCD2, ///< 2nd Panel (LCD), pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + ///< - @b PINMUX_LCD_SEL_CCIR656 + ///< - @b PINMUX_LCD_SEL_CCIR601 + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_6BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_8BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_YCbCr_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_9BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDIO + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDI_SDO + ///< ORed with + ///< - @b PINMUX_LCD_SEL_DE_ENABLE + PINMUX_FUNC_ID_TV, ///< TV, pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + PINMUX_FUNC_ID_HDMI, ///< HDMI, pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + PINMUX_FUNC_ID_SN_MES0, ///< Sensor MES0, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MES1, ///< Sensor MES1, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MES2, ///< Sensor MES2, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MES3, ///< Sensor MES3, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_FLCTR, ///< Sensor Flash Control, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MCLK, ///< Sensor MCLK, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SPI2, ///< SPI channel2 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_SPI3, ///< SPI channel3 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_SPI4, ///< SPI channel4 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_SPI5, ///< SPI channel5 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_COUNT, //< Total function count + + ENUM_DUMMY4WORD(PINMUX_FUNC_ID) +} PINMUX_FUNC_ID; + +/** + Pinmux selection for LCD + + @note For PINMUX_FUNC_ID_LCD, PINMUX_FUNC_ID_LCD2 +*/ +typedef enum +{ + PINMUX_LCD_SEL_GPIO, ///< GPIO + PINMUX_LCD_SEL_CCIR656, ///< CCIR-656 8 bits. Enable CCIR_YC[0..7]/CCIR_CLK on LCD[0..8] (L_GPIO[0..8]) + PINMUX_LCD_SEL_CCIR656_16BITS, ///< CCIR-656 16 bits. Enable CCIR_Y[0..7]/CCIR_CLK/CCIR_C[0..7] on LCD[0..8]/LCD[12..19] (L_GPIO[0..8]/L_GPIO[12..19]) + PINMUX_LCD_SEL_CCIR601, ///< CCIR-601 8 bits. Enable CCIR_YC[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD on LCD[0..10] (L_GPIO[0..10]) + PINMUX_LCD_SEL_CCIR601_16BITS, ///< CCIR-601 16 bits. Enable CCIR_Y[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD/CCIR_C[0..7] on LCD[0..19] (L_GPIO[0..19]) + PINMUX_LCD_SEL_SERIAL_RGB_6BITS, ///< Serial RGB 6 bits. Enable RGB_D[2..7]/RGB_CLK/RGB_VD/RGB_HD on LCD[2..10] (L_GPIO[2..10]) + PINMUX_LCD_SEL_SERIAL_RGB_8BITS, ///< Serial RGB 8 bits. Enable RGB_D[0..7]/RGB_CLK/RGB_VD/RGB_HD on LCD[0..10] (L_GPIO[0..10]) + PINMUX_LCD_SEL_SERIAL_YCbCr_8BITS, ///< Serial YCbCr 8 bits. Enable CCIR_YC[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD on LCD[0..10] (L_GPIO[0..10]) + PINMUX_LCD_SEL_PARALLE_RGB565, ///< Parallel RGB565. Enable RGB_C0_[0..4]/RGB_DCLK/RGB_VS/RGB_HS/RGB_C1_[0..5]/RGB_C2_[0..4] on LCD[3..10]/LCD[14..19]/LCD[23..27] (L_GPIO[3..10]/L_GPIO[14..19]/L_GPIO[23..27]) + PINMUX_LCD_SEL_PARALLE_RGB666, ///< Parallel RGB666. Enable RGB_C0_[0..5]/RGB_DCLK/RGB_VS/RGB_HS/RGB_C1_[0..5]/RGB_C2_[0..5] on LCD[2..10]/LCD[14..19]/LCD[22..27] (L_GPIO[2..10]/L_GPIO[14..19]/L_GPIO[22..27]) + PINMUX_LCD_SEL_PARALLE_RGB888, ///< Parallel RGB888. Enable RGB_C0_[0..7]/RGB_DCLK/RGB_VS/RGB_HS/RGB_C1_[0..7]/RGB_C2_[0..7] on LCD[0..10]/LCD[12..27] (L_GPIO[2..10]/L_GPIO[12..27]) + PINMUX_LCD_SEL_RGB_16BITS, ///< RGB 16 bits. Enable CCIR_Y[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD/CCIR_C[0..7] on LCD[0..19] (L_GPIO[0..19]) + PINMUX_LCD_SEL_PARALLE_MI_8BITS, ///< Parallel MI 8 bits. + ///< When PINMUX_PMI_CFG_NORMAL is set, Enable MPU_D[0..7]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..12] (L_GPIO[0..7]/L_GPIO[9..12]) + ///< When PINMUX_PMI_CFG_2ND_PINMUX is set, Enable MPU2_RS/MPU2_CS/MPU2_D[0..7]/MPU2_WR/MPU2_RD on LCD[12..22]/LCD[24] (L_GPIO[12..22]/L_GPIO[24]) + PINMUX_LCD_SEL_PARALLE_MI_9BITS, ///< Parallel MI 9 bits. + ///< When PINMUX_PMI_CFG_NORMAL is set, Enable MPU_D[0..8]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..13] (L_GPIO[0..7]/L_GPIO[9..13]) + ///< When PINMUX_PMI_CFG_2ND_PINMUX is set, Enable MPU2_RS/MPU2_CS/MPU2_D[0..8]/MPU2_WR/MPU2_RD on LCD[12..24] (L_GPIO[12..24]) + PINMUX_LCD_SEL_PARALLE_MI_16BITS, ///< Parallel MI 16 bits. Enable MPU_D[0..15]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..20] (L_GPIO[0..7]/L_GPIO[9..20]) + PINMUX_LCD_SEL_PARALLE_MI_18BITS, ///< Parallel MI 18 bits. Enable MPU_D[0..17]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..22] (L_GPIO[0..7]/L_GPIO[9..22]) + PINMUX_LCD_SEL_SERIAL_MI_SDIO, ///< Serial MI SDIO bi-direction. Enable MPU_CS/MPU_RS/MPU_CLK/MPU_SDIO on LCD[15..18] (L_GPIO[15..18]) + PINMUX_LCD_SEL_SERIAL_MI_SDI_SDO, ///< Serial MI SDI/SDO seperate. Enable MPU_SDO/MPU_SDI/MPU_CS/MPU_RS/MPU_CLK on LCD[13..17] (L_GPIO[13..17]) + PINMUX_LCD_SEL_MIPI, ///< MIPI DSI + + PINMUX_LCD_SEL_TE_ENABLE = 0x01<<23, ///< TE Enable (For Parallel/Serial MI) + ///< When normal (PINMUX_PMI_CFG_NORMAL) parallel MI, enable MPU_TE on LCD8 (L_GPIO[8]). + ///< When 2nd (PINMUX_PMI_CFG_2ND_PINMUX) parallel MI, enable MPU_TE on LCD25 (L_GPIO[25]). + ///< When serial MI, enable MI_TE on LCD19 (L_GPIO[19]). + PINMUX_LCD_SEL_DE_ENABLE = 0x01<<24, ///< DE Enable (For CCIR656 8/16bits, CCIR601 16bits, Serial RGB 6/8bits, Serial YCbCr 8 bits, RGB 16 bits) + ///< When corresponding item in pinmux_init() is set with PINMUX_DISPMUX_SEL_LCD, enable CCIR_DE on LCD11 (L_GPIO[11]). + ///< When corresponding item in pinmux_init() is set with PINMUX_DISPMUX_SEL_LCD2, enable CCIR2_DE on LCD23 (L_GPIO[23]). + PINMUX_LCD_SEL_HVLD_VVLD = 0x01<<25, ///< HVLD/VVLD Enable (For CCIR-601 8 bits). Enable CCIR_HVLD/CCIR_VVLD on LCD[12..13] (L_GPIO[12..13]) + PINMUX_LCD_SEL_FIELD = 0x01<<26, ///< FIELD Enable (For CCIR-601 8 bits). Enable CCIR_FIELD on LCD14 (L_GPIO[14]) + + PINMUX_LCD_SEL_FEATURE_MSK = 0x0F<<23, + + ENUM_DUMMY4WORD(PINMUX_LCD_SEL) +} PINMUX_LCD_SEL; + +/** + Pinmux selection for Storage + + @note For PINMUX_FUNC_ID_SDIO, PINMUX_FUNC_ID_SPI, PINMUX_FUNC_ID_NAND +*/ +typedef enum +{ + PINMUX_STORAGE_SEL_INACTIVE, ///< Inactive storage + PINMUX_STORAGE_SEL_ACTIVE, ///< Active storage + PINMUX_STORAGE_SEL_INEXIST, ///< Inexist storage + PINMUX_STORAGE_SEL_EXIST, ///< Exist storage + ENUM_DUMMY4WORD(PINMUX_STORAGE_SEL) +} PINMUX_STORAGE_SEL; + +/** + Pinmux selection for sensor + + @note For PINMUX_FUNC_ID_SN_MES0, PINMUX_FUNC_ID_SN_MES1, PINMUX_FUNC_ID_SN_FLCTR +*/ +typedef enum +{ + PINMUX_SENSOR_SEL_INACTIVE, ///< Inactive + PINMUX_SENSOR_SEL_ACTIVE, ///< Active + ENUM_DUMMY4WORD(PINMUX_SENSOR_SEL) +} PINMUX_SENSOR_SEL; + +/** + Pinmux selection for sensor + + @note For PINMUX_FUNC_ID_USB_VBUSI +*/ +typedef enum +{ + PINMUX_USB_SEL_INACTIVE, ///< Inactive + PINMUX_USB_SEL_ACTIVE, ///< Active + ENUM_DUMMY4WORD(PINMUX_USB_SEL) +} PINMUX_USB_SEL; + +/** + Pinmux selection for SPI + + @note For PINMUX_FUNC_ID_SPI2, PINMUX_FUNC_ID_SPI3 +*/ +typedef enum +{ + PINMUX_SPI_SEL_INACTIVE, ///< Inactive + PINMUX_SPI_SEL_ACTIVE, ///< Active + ENUM_DUMMY4WORD(PINMUX_SPI_SEL) +} PINMUX_SPI_SEL; + +/** + Pinmux group + + @note For pinmux_init() +*/ +typedef struct +{ + PIN_FUNC pin_function; ///< PIN Function group + UINT32 config; ///< Configuration for pinFunction +} PIN_GROUP_CONFIG; + +/* + Pinmux Function identifier for driver only + + @note For pinmux_setPinmux(). +*/ +typedef enum +{ + PINMUX_FUNC_ID_SDIO = 0x8000000, ///< SDIO, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_SDIO2, ///< SDIO2, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_SDIO3, ///< SDIO3, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_SPI, ///< SPI, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_NAND, ///< NAND, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_BMC, ///< BMC, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_USB_VBUSI, ///< USB VBUSI, pinmux can be: + ///< - @b PINMUX_USB_SEL_INACTIVE + ///< - @b PINMUX_USB_SEL_ACTIVE + PINMUX_FUNC_ID_USB2_VBUSI, ///< USB2 VBUSI, pinmux can be: + ///< - @b PINMUX_USB_SEL_INACTIVE + ///< - @b PINMUX_USB_SEL_ACTIVE + PINMUX_FUNC_ID_I2C1_1ST, ///< I2C channel1 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C1_2ND, ///< I2C channel1 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C2_1ST, ///< I2C channel2 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C2_2ND, ///< I2C channel2 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C3_1ST, ///< I2C channel3 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C3_2ND, ///< I2C channel3 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C3_3RD, ///< I2C channel3 3rd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_1ST, ///< I2C channel4 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_2ND, ///< I2C channel4 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_3RD, ///< I2C channel4 3rd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_4TH, ///< I2C channel4 4th pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C5_1ST, ///< I2C channel5 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C5_2ND, ///< I2C channel5 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_SN_VDHD, ///< SN VD/HD, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_0, ///< PWM channel 0 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_1, ///< PWM channel 1 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_2, ///< PWM channel 2 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_3, ///< PWM channel 3 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_4, ///< PWM channel 4 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_5, ///< PWM channel 5 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_6, ///< PWM channel 6 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_7, ///< PWM channel 7 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_8, ///< PWM channel 8 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_9, ///< PWM channel 9 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_10, ///< PWM channel 10 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_11, ///< PWM channel 11 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_12, ///< PWM channel 12 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_13, ///< PWM channel 13 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_14, ///< PWM channel 14 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_15, ///< PWM channel 15 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_16, ///< PWM channel 16 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_17, ///< PWM channel 17 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_18, ///< PWM channel 18 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_19, ///< PWM channel 19 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_0, ///< SIF channel 0 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_1, ///< SIF channel 1 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_2, ///< SIF channel 2 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_3, ///< SIF channel 3 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_4, ///< SIF channel 4 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_5, ///< SIF channel 5 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_6, ///< SIF channel 6 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_7, ///< SIF channel 7 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_UART_1, ///< UART channel 1 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_UART_2, ///< UART channel 2 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_UART_3, ///< UART channel 3 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_UART_4, ///< UART channel 4 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_I2S, ///< I2S + ///< - @b PINMUX_I2S_SEL_INACTIVE + ///< - @b PINMUX_I2S_SEL_ACTIVE + PINMUX_FUNC_ID_I2S_MCLK, ///< I2S MCLK + ///< - @b PINMUX_I2S_SEL_INACTIVE + ///< - @b PINMUX_I2S_SEL_ACTIVE + + ENUM_DUMMY4WORD(PINMUX_FUNC_ID_DRV) +} PINMUX_FUNC_ID_DRV; + +// +// API for Top controller +// +extern void pinmux_select_debugport(PINMUX_DEBUGPORT uiDebug); +extern void pinmux_select_ocp_debugport(PINMUX_DEBUGPORT_OCP uiDebug); + +extern ER pinmux_init(PIN_GROUP_CONFIG *pConfig); +extern ER pinmux_setDispMode(PINMUX_FUNC_ID id, PINMUX_LCDINIT dispMode); +extern PINMUX_LCDINIT pinmux_getDispMode(PINMUX_FUNC_ID id); +extern ER pinmux_set_pinmux(PINMUX_FUNC_ID id, UINT32 pinmux); +extern BOOL pinmux_chkPinmux(PINMUX_FUNC_ID id, UINT32 pinmux); +//@} //addtogroup mIHALSysCfg + +#endif + diff --git a/board/novatek/na51055/loader/Include/nvtpack/nvtpack.h b/board/novatek/na51055/loader/Include/nvtpack/nvtpack.h new file mode 100755 index 000000000000..d59c5c0001bc --- /dev/null +++ b/board/novatek/na51055/loader/Include/nvtpack/nvtpack.h @@ -0,0 +1,193 @@ +#ifndef _NVTPACK_H +#define _NVTPACK_H + +#define NVTPACK_CHKSUM_HDR_VERSION 0x16040719U +#define NVTPACK_FW_HDR2_VERSION 0x16071515U + +typedef enum _NVTPACK_ER { + NVTPACK_ER_SUCCESS = 0, + NVTPACK_ER_FAILED = -1, + NVTPACK_ER_UNKNOWN_FORMAT = -2, + NVTPACK_ER_CHECK_SUM = -3, + NVTPACK_ER_NOT_FOUND = -4, + NVTPACK_ER_USER_BREAK = -5, + NVTPACK_ER_PARAM = -6, + NVTPACK_ER_MEM_NOT_ENOUGH = -7, + NVTPACK_ER_UITRON_SIZE_ALIGN4 = -8, ///< uITRON size must align by 4 + NVTPACK_ER_INVALID_WHOLE_SIZE = -9, ///< after nvtpack, whole size must align by 4 + NVTPACK_ER_SRC_NAME_BLANK = -10, ///< resource's SrcName cannot be NULL or blank + NVTPACK_ER_SRC_NAME_EXCEED = -11, ///< resource's SrcName cannot exceed 12 bytes + NVTPACK_ER_SRC_NAME_INVALID = -12, ///< resource's SrcName include invalid character + NVTPACK_ER_SRC_NAME_ALIKE = -13, ///< there resource's SrcName are alike. +} NVTPACK_ER; + +typedef enum _NVTPACK_VER { + NVTPACK_VER_UNKNOWN, ///< UNKNOWN + NVTPACK_VER_13012816, ///< NT9666X, NT9850X + NVTPACK_VER_16072017, ///< NT9668X +} NVTPACK_VER; + +#if !defined(_WIN32) +typedef struct _GUID { + unsigned int Data1; + unsigned short Data2; + unsigned short Data3; + unsigned char Data4[8]; +} GUID; +#endif + +typedef struct _NVTPACK_RES_HDR { + GUID guid; ///< {B5CB64AE-05DD-46FA-B906-0C62D22958D6} + unsigned int TotalSize; + unsigned int CheckSum; + unsigned int ContentSize; + char SrcName[16]; ///< original packed bin file name + char DstName[16]; ///< target file name +} NVTPACK_RES_HDR; + +typedef struct _NVTPACK_FW_HDR { + GUID guid; ///< {8827BE90-36CD-4FC2-A987-73A8484E84B1} + unsigned int TotalSize; ///< sizeof(NVTPACK_FW_HDR) + n*sizeof(NVTPACK_PARTITION_HDR) + unsigned int CheckSum; ///< check sum of sizeof(NVTPACK_FW_HDR) + n*sizeof(NVTPACK_PARTITION_HDR) + unsigned int TotalRes; ///< total partitions +} NVTPACK_FW_HDR; + +typedef struct _NVTPACK_FW_HDR2 { + GUID guid; ///< {D6012E07-10BC-4F91-B28A-352F82261A50} + unsigned int uiVersion; ///< NVTPACK_FW_HDR2_VERSION + unsigned int uiHdrSize; ///< sizeof(NVTPACK_FW_HDR2); + unsigned int TotalRes; ///< total resource counts + unsigned int TotalSize; ///< whole bin size + unsigned int uiChkMethod; ///< 0: CheckSum + unsigned int uiChkValue; ///< check sum value or crc value within NVTPACK_FW_HDR2 + unsigned int uiUserData[4]; ///< user defined data that may be used in future + unsigned int uiReversed[18];///< align to 128 bytes +} NVTPACK_FW_HDR2; + +typedef struct _NVTPACK_PARTITION_HDR { + unsigned int Offset; + unsigned int Size; + unsigned int PartitionID; +} NVTPACK_PARTITION_HDR; + +typedef struct _NVTPACK_CHKSUM_HDR { + unsigned int uiFourCC ; ///< 'C','K','S','M' + unsigned int uiVersion; ///< NVTPACK_CHKSUM_HDR header version + unsigned int uiChkMethod; ///< 0: CheckSum + unsigned int uiChkValue; ///< check sum value or crc value within NVTPACK_CHKSUM_HDR + unsigned int uiDataOffset; ///< real data starting offset without NVTPACK_CHKSUM_HDR + unsigned int uiDataSize; ///< real data size without NVTPACK_CHKSUM_HDR + unsigned int uiPaddingSize; ///< padding bytes for check sum + unsigned int uiEmbType; ///< relate to EMBTYPE_????? + unsigned int uiReversed[8]; ///< align to 64 bytes +} NVTPACK_CHKSUM_HDR; + +typedef struct _NVTPACK_BFC_HDR { + unsigned int uiFourCC; ///< FourCC = BCL1 + unsigned int uiAlgorithm; ///< algorithm always is 9 + unsigned int uiSizeUnComp;///< big endian uncompressed size + unsigned int uiSizeComp; ///< big endian compressed size +} NVTPACK_BFC_HDR; + +typedef struct _NVTPACK_BININFO_HDR { + unsigned int CodeEntry; ///< [0x00] fw CODE entry (4) ----- r by Ld + unsigned int Resv1[19]; ///< [0x04~0x50] reserved (4*19) -- reserved, its mem value will filled by Ld + char BinInfo_1[8]; ///< [0x50~0x58] CHIP-NAME (8) ---- r by Ep + char BinInfo_2[8]; ///< [0x58~0x60] SDK version (8) + char BinInfo_3[8]; ///< [0x60~0x68] SDK release-date (8) + unsigned int BinLength; ///< [0x68] Bin File Length (4) --- w by Ep/bfc + unsigned int Checksum; ///< [0x6c] Check Sum or CRC (4) ----- w by Ep/Epcrc + unsigned int CRCLenCheck; ///< [0x70~0x74] Length check for CRC (4) ----- w by Epcrc (total len ^ 0xAA55) + unsigned int Resv2; ///< [0x74~0x78] reserved (4) --- reserved for other bin tools + unsigned int BinCtrl; ///< [0x78~0x7C] Bin flag (4) --- w by bfc + ///< BIT 0.compressed enable (w by bfc) + unsigned int CRCBinaryTag; ///< [0x7C~0x80] Binary Tag for CRC (4) ----- w by Epcrc (0xAA55 + "NT") +} NVTPACK_BININFO_HDR; + +typedef struct _NVTPACK_MEM { + void *p_data; + unsigned int len; +} NVTPACK_MEM; + +typedef struct _NVTPACK_VERIFY_OUTPUT { + NVTPACK_VER ver; ///< indicate package type + unsigned int partition_cnt; ///< total partition counts +} NVTPACK_VERIFY_OUTPUT; + +typedef struct _NVTPACK_GET_PARTITION_INPUT { + unsigned int id; + NVTPACK_MEM mem; +} NVTPACK_GET_PARTITION_INPUT; + +typedef struct _NVTPACK_GET_RESOURCE_INPUT { + const char *filename; + NVTPACK_MEM mem; +} NVTPACK_GET_RESOURCE_INPUT; + +typedef struct _NVTPACK_ENUM_PARTITION_INPUT { + NVTPACK_MEM mem; + void *p_user_data; ///< [Optional] e.g. if use c class, you can pass that class point to your static callback. + int (*fp_enum)(unsigned int id, NVTPACK_MEM *p_mem, void *p_user_data); +} NVTPACK_ENUM_PARTITION_INPUT; + +typedef struct _NVTPACK_ENUM_RESOURCE_INPUT { + NVTPACK_MEM mem; + void *p_user_data; ///< [Optional] e.g. if use c class, you can pass that class point to your static callback. + int (*fp_enum)(NVTPACK_RES_HDR *p_hdr, NVTPACK_MEM *p_mem, void *p_user_data); +} NVTPACK_ENUM_RESOURCE_INPUT; + +typedef struct _NVTPACK_PARTITION_ITEM { + unsigned int id; + NVTPACK_MEM mem; +} NVTPACK_PARTITION_ITEM; + +typedef struct _NVTPACK_MAKE_PARTITION_INPUT { + NVTPACK_VER ver; ///< package version + NVTPACK_PARTITION_ITEM *p_list; ///< data list + int num; ///< data counts + NVTPACK_MEM mem_work; ///< working buffer +} NVTPACK_MAKE_PARTITION_INPUT; + +typedef struct _NVTPACK_RESOURCE_ITEM { + char SrcName[16]; ///< original name + char DstName[16]; ///< target file name + NVTPACK_MEM mem; +} NVTPACK_RESOURCE_ITEM; + +typedef struct _NVTPACK_MAKE_RESOURCE_INPUT { + NVTPACK_RESOURCE_ITEM *p_list; + int num; + NVTPACK_MEM mem_work; +} NVTPACK_MAKE_RESOURCE_INPUT; + +#ifndef IsEqualGUID +#define IsEqualGUID(rguid1, rguid2) (!memcmp(rguid1, rguid2, sizeof(GUID))) +#endif + +#ifndef MAKEFOURCC +#define MAKEFOURCC(ch0, ch1, ch2, ch3) ((unsigned int)(unsigned char)(ch0) | ((unsigned int)(unsigned char)(ch1) << 8) | ((unsigned int)(unsigned char)(ch2) << 16) | ((unsigned int)(unsigned char)(ch3) << 24 )) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +extern unsigned int nvtpack_calc_nvt_sum(NVTPACK_MEM *p_mem); +extern NVTPACK_ER nvtpack_getver(NVTPACK_MEM *p_mem, NVTPACK_VER *p_ver); +extern NVTPACK_ER nvtpack_verify(NVTPACK_MEM *p_mem, NVTPACK_VERIFY_OUTPUT *p_output); +extern NVTPACK_ER nvtpack_get_partition(NVTPACK_GET_PARTITION_INPUT *p_input, NVTPACK_MEM *p_out); +extern NVTPACK_ER nvtpack_enum_partition(NVTPACK_ENUM_PARTITION_INPUT *p_input); +//NVTPACK_VER_13012816: need sizeof(NVTPACK_FW_HDR) +n*(sizeof(NVTPACK_PARTITION_HDR) + 4) + whole_data_size +//NVTPACK_VER_16072017: need sizeof(NVTPACK_FW_HDR2) +n*(sizeof(NVTPACK_PARTITION_HDR) + 4) + whole_data_size +extern NVTPACK_ER nvtpack_make_parition_pkg(NVTPACK_MAKE_PARTITION_INPUT *p_input, NVTPACK_MEM *p_out); + +extern NVTPACK_ER nvtpack_get_resource(NVTPACK_GET_RESOURCE_INPUT *p_input, NVTPACK_MEM *p_out); +extern NVTPACK_ER nvtpack_enum_resource(NVTPACK_ENUM_RESOURCE_INPUT *p_input); +//buf need n*(sizeof(NVTPACK_RES_HDR)+32)+ whole_data_size +extern NVTPACK_ER nvtpack_make_resource_pkg(NVTPACK_MAKE_RESOURCE_INPUT *p_input, NVTPACK_MEM *p_out); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/board/novatek/na51055/loader/Include/rtc.h b/board/novatek/na51055/loader/Include/rtc.h new file mode 100755 index 000000000000..fb0fa3999aa7 --- /dev/null +++ b/board/novatek/na51055/loader/Include/rtc.h @@ -0,0 +1,49 @@ +/** + Header file for RTC module. + + This file is the header file that define the API and data type + for RTC module. + + @file rtc.h + @ingroup mIHALRTC + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __RTC_H +#define __RTC_H +#include "IOReg.h" + +/** + @addtogroup mIHALRTC +*/ +//@{ + +/** + @name RTC power on source + + RTC power on source + + @note For rtc_getPWRONSource() +*/ +//@{ +#define RTC_PWR_SW_STS 0x00000100 ///< Power on from switch +#define RTC_PWR_SW2_STS 0x00000200 ///< power on from power switch 2 +#define RTC_PWR_SW3_STS 0x00000400 ///< power on from power switch 3 (Usually for USB VBUS, depend on project) +#define RTC_PWR_VBUS_STS (RTC_PWR_SW3_STS) ///< power on from VBUS (identical to RTC_PWR_SW3_STS) +#define RTC_PWR_SW4_STS 0x00000800 ///< power on from power switch 4 (Usually for VBAT, depend on project) +#define RTC_PWR_VBAT_STS (RTC_PWR_SW4_STS) ///< power on from VBAT (identical to RTC_PWR_SW4_STS) +#define RTC_PWR_ALARM_STS 0x00010000 ///< Power on from PWR ALARM +//@} + +extern void rtc_resetShutDownTimer(void); +extern void rtc_poweroffPWR(void); +extern UINT32 rtc_getPWRONSource(void); +extern UINT32 rtc_chkS3boot_init(void) __attribute__ ((section (".part1"))); +extern void rtc_chkS3boot_wait_init(void) __attribute__ ((section (".part1"))); +extern UINT32 rtc_chkS3boot(void) __attribute__ ((section (".part1"))); + +//@} +#endif // __RTC_H + diff --git a/board/novatek/na51055/loader/Include/signal.h b/board/novatek/na51055/loader/Include/signal.h new file mode 100755 index 000000000000..5a2a7078c80c --- /dev/null +++ b/board/novatek/na51055/loader/Include/signal.h @@ -0,0 +1,4 @@ +#ifndef _NVT_LIBC_SIGNAL_H__ +#define _NVT_LIBC_SIGNAL_H__ +int raise(int sig); +#endif diff --git a/board/novatek/na51055/loader/Include/stdarg.h b/board/novatek/na51055/loader/Include/stdarg.h new file mode 100755 index 000000000000..f9af3123244d --- /dev/null +++ b/board/novatek/na51055/loader/Include/stdarg.h @@ -0,0 +1,19 @@ +#ifndef __NVT_STDARG_H__ +#define __NVT_STDARG_H__ + +typedef char *va_list; + +/* + * Storage alignment properties + */ +#define _AUPBND (sizeof (int) - 1) +#define _ADNBND (sizeof (int) - 1) + +/* + * Variable argument list macro definitions + */ +#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd))) +#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND)))) +#define va_end(ap) (void) 0 +#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND)))) +#endif diff --git a/board/novatek/na51055/loader/Include/stdio.h b/board/novatek/na51055/loader/Include/stdio.h new file mode 100755 index 000000000000..ec8eff4318d4 --- /dev/null +++ b/board/novatek/na51055/loader/Include/stdio.h @@ -0,0 +1,23 @@ +/** + STDIO header + + STDIO header + + @file stdio.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_STDIO_H__ +#define __NVT_STDIO_H__ + +/** \addtogroup mISYSClib */ +//@{ + +int sprintf(char * buf, const char *fmt, ...); +int sscanf(const char * buf, const char * fmt, ...); + +//@} +#endif diff --git a/board/novatek/na51055/loader/Include/stdlib.h b/board/novatek/na51055/loader/Include/stdlib.h new file mode 100755 index 000000000000..9f8540807eb6 --- /dev/null +++ b/board/novatek/na51055/loader/Include/stdlib.h @@ -0,0 +1,4 @@ +#ifndef __NVT_LIBC_STDLIB_H__ +#define __NVT_LIBC_STDLIB_H__ +int atoi(const char *nptr); +#endif diff --git a/board/novatek/na51055/loader/Include/string.h b/board/novatek/na51055/loader/Include/string.h new file mode 100755 index 000000000000..aed82db58077 --- /dev/null +++ b/board/novatek/na51055/loader/Include/string.h @@ -0,0 +1,47 @@ +/** + string header + + string header + + @file string.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_LIBC_STRING_H__ +#define __NVT_LIBC_STRING_H__ + +/** \addtogroup mISYSClib */ +//@{ + +/** + size_t data type + + data type to store value return by sizeof keyword +*/ +typedef unsigned int size_t; + +extern size_t strlen(const char *s); +extern size_t strnlen(const char *s, size_t count); +extern char *strncpy(char *dest, const char *src, size_t count); +extern char *strncat(char *dest, const char *src, size_t count); +extern char *strstr(const char *s1, const char *s2); +extern int strncmp(const char *cs, const char *ct, size_t count); +extern char *strrchr(const char *s, int c); +extern char *strcpy(char *dest, const char *src); +extern char *strcat(char *dest, const char *src); +extern char *strchr(const char *s, int c); +extern char* strtok(char *s, const char *delim); +extern int strcmp(const char *cs, const char *ct); + +extern void *utl_memset(void *s, int c, size_t count); +extern void *utl_memcpy(void *dest, const void *src, size_t count); +extern int memcmp(const void *cs, const void *ct, size_t count); +extern void *memmove(void *dest, const void *src, size_t count); +extern void *memchr(const void *ptr, int value, size_t count); +//@} + +#endif + diff --git a/board/novatek/na51055/loader/Include/timer.h b/board/novatek/na51055/loader/Include/timer.h new file mode 100755 index 000000000000..22992bc1145d --- /dev/null +++ b/board/novatek/na51055/loader/Include/timer.h @@ -0,0 +1,31 @@ +/** + Public header file for timer module. + + This file is the header file that define the API and data type for timer + module. + + @file timer.h + @ingroup mIHALTimer + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _TIMER_H +#define _TIMER_H + +#include "IOReg.h" + +/** + @addtogroup mIHALTimer +*/ +//@{ + +extern UINT32 timer_getLdrElapse(void); +extern void timer_delay(UINT32 US); +#define timer_getLdrElapse() INREG32(0xF0040108) +#define timer_getSysTick() INREG32(0xF0040108) +//extern UINT32 timer_getSysTick(void) __attribute__ ((section (".part1"))); + //@} + +#endif diff --git a/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.c b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.c new file mode 100644 index 000000000000..b2e5b40331ea --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.c @@ -0,0 +1,1033 @@ +/* LzmaDec.c -- LZMA Decoder +2009-09-20 : Igor Pavlov : Public domain */ + +/* + * OpenIPC: U-Boot's lib/lzma/LzmaDec.c for the loader, which has no + * libc: memcpy is the loader's, and there is no watchdog to feed. + */ +/* OpenIPC: small, in Thumb, to fit the loader's 32 KiB */ +#pragma GCC target("thumb") +#pragma GCC optimize("Os") + +#include "LzmaDec.h" +#include "string.h" + +#define memcpy utl_memcpy +#define WATCHDOG_RESET() do { } while (0) + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_INIT_SIZE 5 + +#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); } + +#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) +#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits)); +#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits)); +#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \ + { UPDATE_0(p); i = (i + i); A0; } else \ + { UPDATE_1(p); i = (i + i) + 1; A1; } +#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;) + +#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); } +#define TREE_DECODE(probs, limit, i) \ + { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; } + +/* OpenIPC: the loop form, smaller */ +#define _LZMA_SIZE_OPT + +#ifdef _LZMA_SIZE_OPT +#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i) +#else +#define TREE_6_DECODE(probs, i) \ + { i = 1; \ + TREE_GET_BIT(probs, i); \ + TREE_GET_BIT(probs, i); \ + TREE_GET_BIT(probs, i); \ + TREE_GET_BIT(probs, i); \ + TREE_GET_BIT(probs, i); \ + TREE_GET_BIT(probs, i); \ + i -= 0x40; } +#endif + +#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); } + +#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) +#define UPDATE_0_CHECK range = bound; +#define UPDATE_1_CHECK range -= bound; code -= bound; +#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \ + { UPDATE_0_CHECK; i = (i + i); A0; } else \ + { UPDATE_1_CHECK; i = (i + i) + 1; A1; } +#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;) +#define TREE_DECODE_CHECK(probs, limit, i) \ + { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 +#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp))) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +#define LZMA_DIC_MIN (1 << 12) + +/* First LZMA-symbol is always decoded. +And it decodes new LZMA-symbols while (buf < bufLimit), but "buf" is without last normalization +Out: + Result: + SZ_OK - OK + SZ_ERROR_DATA - Error + p->remainLen: + < kMatchSpecLenStart : normal remain + = kMatchSpecLenStart : finished + = kMatchSpecLenStart + 1 : Flush marker + = kMatchSpecLenStart + 2 : State Init Marker +*/ + +static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit) +{ + CLzmaProb *probs = p->probs; + + unsigned state = p->state; + UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3]; + unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1; + unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1; + unsigned lc = p->prop.lc; + + Byte *dic = p->dic; + SizeT dicBufSize = p->dicBufSize; + SizeT dicPos = p->dicPos; + + UInt32 processedPos = p->processedPos; + UInt32 checkDicSize = p->checkDicSize; + unsigned len = 0; + + const Byte *buf = p->buf; + UInt32 range = p->range; + UInt32 code = p->code; + + WATCHDOG_RESET(); + + do + { + CLzmaProb *prob; + UInt32 bound; + unsigned ttt; + unsigned posState = processedPos & pbMask; + + prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; + IF_BIT_0(prob) + { + unsigned symbol; + UPDATE_0(prob); + prob = probs + Literal; + if (checkDicSize != 0 || processedPos != 0) + prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) + + (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc)))); + + if (state < kNumLitStates) + { + state -= (state < 4) ? state : 3; + symbol = 1; + + WATCHDOG_RESET(); + + do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100); + } + else + { + unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; + unsigned offs = 0x100; + state -= (state < 10) ? 3 : 6; + symbol = 1; + + WATCHDOG_RESET(); + + do + { + unsigned bit; + CLzmaProb *probLit; + matchByte <<= 1; + bit = (matchByte & offs); + probLit = prob + offs + bit + symbol; + GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit) + } + while (symbol < 0x100); + } + dic[dicPos++] = (Byte)symbol; + processedPos++; + continue; + } + else + { + UPDATE_1(prob); + prob = probs + IsRep + state; + IF_BIT_0(prob) + { + UPDATE_0(prob); + state += kNumStates; + prob = probs + LenCoder; + } + else + { + UPDATE_1(prob); + if (checkDicSize == 0 && processedPos == 0) + return SZ_ERROR_DATA; + prob = probs + IsRepG0 + state; + IF_BIT_0(prob) + { + UPDATE_0(prob); + prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; + IF_BIT_0(prob) + { + UPDATE_0(prob); + dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; + dicPos++; + processedPos++; + state = state < kNumLitStates ? 9 : 11; + continue; + } + UPDATE_1(prob); + } + else + { + UInt32 distance; + UPDATE_1(prob); + prob = probs + IsRepG1 + state; + IF_BIT_0(prob) + { + UPDATE_0(prob); + distance = rep1; + } + else + { + UPDATE_1(prob); + prob = probs + IsRepG2 + state; + IF_BIT_0(prob) + { + UPDATE_0(prob); + distance = rep2; + } + else + { + UPDATE_1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = probs + RepLenCoder; + } + { + unsigned limit, offset; + CLzmaProb *probLen = prob + LenChoice; + IF_BIT_0(probLen) + { + UPDATE_0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + limit = (1 << kLenNumLowBits); + } + else + { + UPDATE_1(probLen); + probLen = prob + LenChoice2; + IF_BIT_0(probLen) + { + UPDATE_0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + limit = (1 << kLenNumMidBits); + } + else + { + UPDATE_1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + limit = (1 << kLenNumHighBits); + } + } + TREE_DECODE(probLen, limit, len); + len += offset; + } + + if (state >= kNumStates) + { + UInt32 distance; + prob = probs + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); + TREE_6_DECODE(prob, distance); + if (distance >= kStartPosModelIndex) + { + unsigned posSlot = (unsigned)distance; + int numDirectBits = (int)(((distance >> 1) - 1)); + distance = (2 | (distance & 1)); + if (posSlot < kEndPosModelIndex) + { + distance <<= numDirectBits; + prob = probs + SpecPos + distance - posSlot - 1; + { + UInt32 mask = 1; + unsigned i = 1; + + WATCHDOG_RESET(); + + do + { + GET_BIT2(prob + i, i, ; , distance |= mask); + mask <<= 1; + } + while (--numDirectBits != 0); + } + } + else + { + numDirectBits -= kNumAlignBits; + + WATCHDOG_RESET(); + + do + { + NORMALIZE + range >>= 1; + + { + UInt32 t; + code -= range; + t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */ + distance = (distance << 1) + (t + 1); + code += range & t; + } + /* + distance <<= 1; + if (code >= range) + { + code -= range; + distance |= 1; + } + */ + } + while (--numDirectBits != 0); + prob = probs + Align; + distance <<= kNumAlignBits; + { + unsigned i = 1; + GET_BIT2(prob + i, i, ; , distance |= 1); + GET_BIT2(prob + i, i, ; , distance |= 2); + GET_BIT2(prob + i, i, ; , distance |= 4); + GET_BIT2(prob + i, i, ; , distance |= 8); + } + if (distance == (UInt32)0xFFFFFFFF) + { + len += kMatchSpecLenStart; + state -= kNumStates; + break; + } + } + } + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + rep0 = distance + 1; + if (checkDicSize == 0) + { + if (distance >= processedPos) + return SZ_ERROR_DATA; + } + else if (distance >= checkDicSize) + return SZ_ERROR_DATA; + state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3; + } + + len += kMatchMinLen; + + if (limit == dicPos) + return SZ_ERROR_DATA; + { + SizeT rem = limit - dicPos; + unsigned curLen = ((rem < len) ? (unsigned)rem : len); + SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0); + + processedPos += curLen; + + len -= curLen; + if (pos + curLen <= dicBufSize) + { + Byte *dest = dic + dicPos; + ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos; + const Byte *lim = dest + curLen; + dicPos += curLen; + + WATCHDOG_RESET(); + + do + *(dest) = (Byte)*(dest + src); + while (++dest != lim); + } + else + { + + WATCHDOG_RESET(); + + do + { + dic[dicPos++] = dic[pos]; + if (++pos == dicBufSize) + pos = 0; + } + while (--curLen != 0); + } + } + } + } + while (dicPos < limit && buf < bufLimit); + + WATCHDOG_RESET(); + + NORMALIZE; + p->buf = buf; + p->range = range; + p->code = code; + p->remainLen = len; + p->dicPos = dicPos; + p->processedPos = processedPos; + p->reps[0] = rep0; + p->reps[1] = rep1; + p->reps[2] = rep2; + p->reps[3] = rep3; + p->state = state; + + return SZ_OK; +} + +static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit) +{ + if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart) + { + Byte *dic = p->dic; + SizeT dicPos = p->dicPos; + SizeT dicBufSize = p->dicBufSize; + unsigned len = p->remainLen; + UInt32 rep0 = p->reps[0]; + if (limit - dicPos < len) + len = (unsigned)(limit - dicPos); + + if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len) + p->checkDicSize = p->prop.dicSize; + + p->processedPos += len; + p->remainLen -= len; + while (len-- != 0) + { + dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; + dicPos++; + } + p->dicPos = dicPos; + } +} + +static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit) +{ + do + { + SizeT limit2 = limit; + if (p->checkDicSize == 0) + { + UInt32 rem = p->prop.dicSize - p->processedPos; + if (limit - p->dicPos > rem) + limit2 = p->dicPos + rem; + } + RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit)); + if (p->processedPos >= p->prop.dicSize) + p->checkDicSize = p->prop.dicSize; + LzmaDec_WriteRem(p, limit); + } + while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart); + + if (p->remainLen > kMatchSpecLenStart) + { + p->remainLen = kMatchSpecLenStart; + } + return 0; +} + +typedef enum +{ + DUMMY_ERROR, /* unexpected end of input stream */ + DUMMY_LIT, + DUMMY_MATCH, + DUMMY_REP +} ELzmaDummy; + +static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize) +{ + UInt32 range = p->range; + UInt32 code = p->code; + const Byte *bufLimit = buf + inSize; + CLzmaProb *probs = p->probs; + unsigned state = p->state; + ELzmaDummy res; + + { + CLzmaProb *prob; + UInt32 bound; + unsigned ttt; + unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1); + + prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK + + /* if (bufLimit - buf >= 7) return DUMMY_LIT; */ + + prob = probs + Literal; + if (p->checkDicSize != 0 || p->processedPos != 0) + prob += (LZMA_LIT_SIZE * + ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) + + (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc)))); + + if (state < kNumLitStates) + { + unsigned symbol = 1; + do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100); + } + else + { + unsigned matchByte = p->dic[p->dicPos - p->reps[0] + + ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)]; + unsigned offs = 0x100; + unsigned symbol = 1; + do + { + unsigned bit; + CLzmaProb *probLit; + matchByte <<= 1; + bit = (matchByte & offs); + probLit = prob + offs + bit + symbol; + GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit) + } + while (symbol < 0x100); + } + res = DUMMY_LIT; + } + else + { + unsigned len; + UPDATE_1_CHECK; + + prob = probs + IsRep + state; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK; + state = 0; + prob = probs + LenCoder; + res = DUMMY_MATCH; + } + else + { + UPDATE_1_CHECK; + res = DUMMY_REP; + prob = probs + IsRepG0 + state; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK; + prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK; + NORMALIZE_CHECK; + return DUMMY_REP; + } + else + { + UPDATE_1_CHECK; + } + } + else + { + UPDATE_1_CHECK; + prob = probs + IsRepG1 + state; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK; + } + else + { + UPDATE_1_CHECK; + prob = probs + IsRepG2 + state; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK; + } + else + { + UPDATE_1_CHECK; + } + } + } + state = kNumStates; + prob = probs + RepLenCoder; + } + { + unsigned limit, offset; + CLzmaProb *probLen = prob + LenChoice; + IF_BIT_0_CHECK(probLen) + { + UPDATE_0_CHECK; + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + limit = 1 << kLenNumLowBits; + } + else + { + UPDATE_1_CHECK; + probLen = prob + LenChoice2; + IF_BIT_0_CHECK(probLen) + { + UPDATE_0_CHECK; + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + limit = 1 << kLenNumMidBits; + } + else + { + UPDATE_1_CHECK; + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + limit = 1 << kLenNumHighBits; + } + } + TREE_DECODE_CHECK(probLen, limit, len); + len += offset; + } + + if (state < 4) + { + unsigned posSlot; + prob = probs + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + + /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */ + + if (posSlot < kEndPosModelIndex) + { + prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + NORMALIZE_CHECK + range >>= 1; + code -= range & (((code - range) >> 31) - 1); + /* if (code >= range) code -= range; */ + } + while (--numDirectBits != 0); + prob = probs + Align; + numDirectBits = kNumAlignBits; + } + { + unsigned i = 1; + do + { + GET_BIT_CHECK(prob + i, i); + } + while (--numDirectBits != 0); + } + } + } + } + } + NORMALIZE_CHECK; + return res; +} + + +static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data) +{ + p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]); + p->range = 0xFFFFFFFF; + p->needFlush = 0; +} + +static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) +{ + p->needFlush = 1; + p->remainLen = 0; + p->tempBufSize = 0; + + if (initDic) + { + p->processedPos = 0; + p->checkDicSize = 0; + p->needInitState = 1; + } + if (initState) + p->needInitState = 1; +} + +void LzmaDec_Init(CLzmaDec *p) +{ + p->dicPos = 0; + LzmaDec_InitDicAndState(p, True, True); +} + +static void LzmaDec_InitStateReal(CLzmaDec *p) +{ + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp)); + UInt32 i; + CLzmaProb *probs = p->probs; + for (i = 0; i < numProbs; i++) + probs[i] = kBitModelTotal >> 1; + p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1; + p->state = 0; + p->needInitState = 0; +} + +SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, + ELzmaFinishMode finishMode, ELzmaStatus *status) +{ + SizeT inSize = *srcLen; + (*srcLen) = 0; + LzmaDec_WriteRem(p, dicLimit); + + *status = LZMA_STATUS_NOT_SPECIFIED; + + while (p->remainLen != kMatchSpecLenStart) + { + int checkEndMarkNow; + + if (p->needFlush != 0) + { + for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--) + p->tempBuf[p->tempBufSize++] = *src++; + if (p->tempBufSize < RC_INIT_SIZE) + { + *status = LZMA_STATUS_NEEDS_MORE_INPUT; + return SZ_OK; + } + if (p->tempBuf[0] != 0) + return SZ_ERROR_DATA; + + LzmaDec_InitRc(p, p->tempBuf); + p->tempBufSize = 0; + } + + checkEndMarkNow = 0; + if (p->dicPos >= dicLimit) + { + if (p->remainLen == 0 && p->code == 0) + { + *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK; + return SZ_OK; + } + if (finishMode == LZMA_FINISH_ANY) + { + *status = LZMA_STATUS_NOT_FINISHED; + return SZ_OK; + } + if (p->remainLen != 0) + { + *status = LZMA_STATUS_NOT_FINISHED; + return SZ_ERROR_DATA; + } + checkEndMarkNow = 1; + } + + if (p->needInitState) + LzmaDec_InitStateReal(p); + + if (p->tempBufSize == 0) + { + SizeT processed; + const Byte *bufLimit; + if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) + { + int dummyRes = LzmaDec_TryDummy(p, src, inSize); + if (dummyRes == DUMMY_ERROR) + { + memcpy(p->tempBuf, src, inSize); + p->tempBufSize = (unsigned)inSize; + (*srcLen) += inSize; + *status = LZMA_STATUS_NEEDS_MORE_INPUT; + return SZ_OK; + } + if (checkEndMarkNow && dummyRes != DUMMY_MATCH) + { + *status = LZMA_STATUS_NOT_FINISHED; + return SZ_ERROR_DATA; + } + bufLimit = src; + } + else + bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX; + p->buf = src; + if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0) + return SZ_ERROR_DATA; + processed = (SizeT)(p->buf - src); + (*srcLen) += processed; + src += processed; + inSize -= processed; + } + else + { + unsigned rem = p->tempBufSize, lookAhead = 0; + while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize) + p->tempBuf[rem++] = src[lookAhead++]; + p->tempBufSize = rem; + if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) + { + int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem); + if (dummyRes == DUMMY_ERROR) + { + (*srcLen) += lookAhead; + *status = LZMA_STATUS_NEEDS_MORE_INPUT; + return SZ_OK; + } + if (checkEndMarkNow && dummyRes != DUMMY_MATCH) + { + *status = LZMA_STATUS_NOT_FINISHED; + return SZ_ERROR_DATA; + } + } + p->buf = p->tempBuf; + if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0) + return SZ_ERROR_DATA; + lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf)); + (*srcLen) += lookAhead; + src += lookAhead; + inSize -= lookAhead; + p->tempBufSize = 0; + } + } + if (p->code == 0) + *status = LZMA_STATUS_FINISHED_WITH_MARK; + return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; +} + +SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status) +{ + SizeT outSize = *destLen; + SizeT inSize = *srcLen; + *srcLen = *destLen = 0; + for (;;) + { + SizeT inSizeCur = inSize, outSizeCur, dicPos; + ELzmaFinishMode curFinishMode; + SRes res; + if (p->dicPos == p->dicBufSize) + p->dicPos = 0; + dicPos = p->dicPos; + if (outSize > p->dicBufSize - dicPos) + { + outSizeCur = p->dicBufSize; + curFinishMode = LZMA_FINISH_ANY; + } + else + { + outSizeCur = dicPos + outSize; + curFinishMode = finishMode; + } + + res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status); + src += inSizeCur; + inSize -= inSizeCur; + *srcLen += inSizeCur; + outSizeCur = p->dicPos - dicPos; + memcpy(dest, p->dic + dicPos, outSizeCur); + dest += outSizeCur; + outSize -= outSizeCur; + *destLen += outSizeCur; + if (res != 0) + return res; + if (outSizeCur == 0 || outSize == 0) + return SZ_OK; + } +} + +void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) +{ + alloc->Free(alloc, p->probs); + p->probs = 0; +} + +static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) +{ + alloc->Free(alloc, p->dic); + p->dic = 0; +} + +void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc) +{ + LzmaDec_FreeProbs(p, alloc); + LzmaDec_FreeDict(p, alloc); +} + +SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) +{ + UInt32 dicSize; + Byte d; + + if (size < LZMA_PROPS_SIZE) + return SZ_ERROR_UNSUPPORTED; + else + dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24); + + if (dicSize < LZMA_DIC_MIN) + dicSize = LZMA_DIC_MIN; + p->dicSize = dicSize; + + d = data[0]; + if (d >= (9 * 5 * 5)) + return SZ_ERROR_UNSUPPORTED; + + p->lc = d % 9; + d /= 9; + p->pb = d / 5; + p->lp = d % 5; + + return SZ_OK; +} + +static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc) +{ + UInt32 numProbs = LzmaProps_GetNumProbs(propNew); + if (p->probs == 0 || numProbs != p->numProbs) + { + LzmaDec_FreeProbs(p, alloc); + p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb)); + p->numProbs = numProbs; + if (p->probs == 0) + return SZ_ERROR_MEM; + } + return SZ_OK; +} + +SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) +{ + CLzmaProps propNew; + RINOK(LzmaProps_Decode(&propNew, props, propsSize)); + RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); + p->prop = propNew; + return SZ_OK; +} + +SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) +{ + CLzmaProps propNew; + SizeT dicBufSize; + RINOK(LzmaProps_Decode(&propNew, props, propsSize)); + RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); + dicBufSize = propNew.dicSize; + if (p->dic == 0 || dicBufSize != p->dicBufSize) + { + LzmaDec_FreeDict(p, alloc); + p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize); + if (p->dic == 0) + { + LzmaDec_FreeProbs(p, alloc); + return SZ_ERROR_MEM; + } + } + p->dicBufSize = dicBufSize; + p->prop = propNew; + return SZ_OK; +} + +SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, + const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, + ELzmaStatus *status, ISzAlloc *alloc) +{ + CLzmaDec p; + SRes res; + SizeT inSize = *srcLen; + SizeT outSize = *destLen; + *srcLen = *destLen = 0; + if (inSize < RC_INIT_SIZE) + return SZ_ERROR_INPUT_EOF; + + LzmaDec_Construct(&p); + res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc); + if (res != 0) + return res; + p.dic = dest; + p.dicBufSize = outSize; + + LzmaDec_Init(&p); + + *srcLen = inSize; + res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status); + + if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT) + res = SZ_ERROR_INPUT_EOF; + + (*destLen) = p.dicPos; + LzmaDec_FreeProbs(&p, alloc); + return res; +} diff --git a/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.h b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.h new file mode 100644 index 000000000000..8e9b4410a0b7 --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.h @@ -0,0 +1,223 @@ +/* LzmaDec.h -- LZMA Decoder +2009-02-07 : Igor Pavlov : Public domain */ + +#ifndef __LZMA_DEC_H +#define __LZMA_DEC_H + +#include "LzmaTypes.h" + +/* #define _LZMA_PROB32 */ +/* _LZMA_PROB32 can increase the speed on some CPUs, + but memory usage for CLzmaDec::probs will be doubled in that case */ + +#ifdef _LZMA_PROB32 +#define CLzmaProb UInt32 +#else +#define CLzmaProb UInt16 +#endif + + +/* ---------- LZMA Properties ---------- */ + +#define LZMA_PROPS_SIZE 5 + +typedef struct _CLzmaProps +{ + unsigned lc, lp, pb; + UInt32 dicSize; +} CLzmaProps; + +/* LzmaProps_Decode - decodes properties +Returns: + SZ_OK + SZ_ERROR_UNSUPPORTED - Unsupported properties +*/ + +SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size); + + +/* ---------- LZMA Decoder state ---------- */ + +/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case. + Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */ + +#define LZMA_REQUIRED_INPUT_MAX 20 + +typedef struct +{ + CLzmaProps prop; + CLzmaProb *probs; + Byte *dic; + const Byte *buf; + UInt32 range, code; + SizeT dicPos; + SizeT dicBufSize; + UInt32 processedPos; + UInt32 checkDicSize; + unsigned state; + UInt32 reps[4]; + unsigned remainLen; + int needFlush; + int needInitState; + UInt32 numProbs; + unsigned tempBufSize; + Byte tempBuf[LZMA_REQUIRED_INPUT_MAX]; +} CLzmaDec; + +#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } + +void LzmaDec_Init(CLzmaDec *p); + +/* There are two types of LZMA streams: + 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. + 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ + +typedef enum +{ + LZMA_FINISH_ANY, /* finish at any point */ + LZMA_FINISH_END /* block must be finished at the end */ +} ELzmaFinishMode; + +/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!! + + You must use LZMA_FINISH_END, when you know that current output buffer + covers last bytes of block. In other cases you must use LZMA_FINISH_ANY. + + If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK, + and output value of destLen will be less than output buffer size limit. + You can check status result also. + + You can use multiple checks to test data integrity after full decompression: + 1) Check Result and "status" variable. + 2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize. + 3) Check that output(srcLen) = compressedSize, if you know real compressedSize. + You must use correct finish mode in that case. */ + +typedef enum +{ + LZMA_STATUS_NOT_SPECIFIED, /* use main error code instead */ + LZMA_STATUS_FINISHED_WITH_MARK, /* stream was finished with end mark. */ + LZMA_STATUS_NOT_FINISHED, /* stream was not finished */ + LZMA_STATUS_NEEDS_MORE_INPUT, /* you must provide more input bytes */ + LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK /* there is probability that stream was finished without end mark */ +} ELzmaStatus; + +/* ELzmaStatus is used only as output value for function call */ + + +/* ---------- Interfaces ---------- */ + +/* There are 3 levels of interfaces: + 1) Dictionary Interface + 2) Buffer Interface + 3) One Call Interface + You can select any of these interfaces, but don't mix functions from different + groups for same object. */ + + +/* There are two variants to allocate state for Dictionary Interface: + 1) LzmaDec_Allocate / LzmaDec_Free + 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs + You can use variant 2, if you set dictionary buffer manually. + For Buffer Interface you must always use variant 1. + +LzmaDec_Allocate* can return: + SZ_OK + SZ_ERROR_MEM - Memory allocation error + SZ_ERROR_UNSUPPORTED - Unsupported properties +*/ + +SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc); +void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc); + +SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc); +void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc); + +/* ---------- Dictionary Interface ---------- */ + +/* You can use it, if you want to eliminate the overhead for data copying from + dictionary to some other external buffer. + You must work with CLzmaDec variables directly in this interface. + + STEPS: + LzmaDec_Constr() + LzmaDec_Allocate() + for (each new stream) + { + LzmaDec_Init() + while (it needs more decompression) + { + LzmaDec_DecodeToDic() + use data from CLzmaDec::dic and update CLzmaDec::dicPos + } + } + LzmaDec_Free() +*/ + +/* LzmaDec_DecodeToDic + + The decoding to internal dictionary buffer (CLzmaDec::dic). + You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! + +finishMode: + It has meaning only if the decoding reaches output limit (dicLimit). + LZMA_FINISH_ANY - Decode just dicLimit bytes. + LZMA_FINISH_END - Stream must be finished after dicLimit. + +Returns: + SZ_OK + status: + LZMA_STATUS_FINISHED_WITH_MARK + LZMA_STATUS_NOT_FINISHED + LZMA_STATUS_NEEDS_MORE_INPUT + LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK + SZ_ERROR_DATA - Data error +*/ + +SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, + const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); + + +/* ---------- Buffer Interface ---------- */ + +/* It's zlib-like interface. + See LzmaDec_DecodeToDic description for information about STEPS and return results, + but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need + to work with CLzmaDec variables manually. + +finishMode: + It has meaning only if the decoding reaches output limit (*destLen). + LZMA_FINISH_ANY - Decode just destLen bytes. + LZMA_FINISH_END - Stream must be finished after (*destLen). +*/ + +SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, + const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); + + +/* ---------- One Call Interface ---------- */ + +/* LzmaDecode + +finishMode: + It has meaning only if the decoding reaches output limit (*destLen). + LZMA_FINISH_ANY - Decode just destLen bytes. + LZMA_FINISH_END - Stream must be finished after (*destLen). + +Returns: + SZ_OK + status: + LZMA_STATUS_FINISHED_WITH_MARK + LZMA_STATUS_NOT_FINISHED + LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK + SZ_ERROR_DATA - Data error + SZ_ERROR_MEM - Memory allocation error + SZ_ERROR_UNSUPPORTED - Unsupported properties + SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src). +*/ + +SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, + const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, + ELzmaStatus *status, ISzAlloc *alloc); + +#endif diff --git a/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaTypes.h b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaTypes.h new file mode 100644 index 000000000000..da502ffc2279 --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaTypes.h @@ -0,0 +1,239 @@ +/* Types.h -- Basic types +2010-10-09 : Igor Pavlov : Public domain */ + +#ifndef __7Z_TYPES_H +#define __7Z_TYPES_H + +/* OpenIPC: the loader has no libc headers; size_t is its string.h's */ +#include "string.h" +typedef int ptrdiff_t; +#ifndef NULL +#define NULL ((void *)0) +#endif + +#ifdef _WIN32 +#include +#endif + +#define SZ_OK 0 + +#define SZ_ERROR_DATA 1 +#define SZ_ERROR_MEM 2 +#define SZ_ERROR_CRC 3 +#define SZ_ERROR_UNSUPPORTED 4 +#define SZ_ERROR_PARAM 5 +#define SZ_ERROR_INPUT_EOF 6 +#define SZ_ERROR_OUTPUT_EOF 7 +#define SZ_ERROR_READ 8 +#define SZ_ERROR_WRITE 9 +#define SZ_ERROR_PROGRESS 10 +#define SZ_ERROR_FAIL 11 +#define SZ_ERROR_THREAD 12 + +#define SZ_ERROR_ARCHIVE 16 +#define SZ_ERROR_NO_ARCHIVE 17 + +typedef int SRes; + +#ifdef _WIN32 +typedef DWORD WRes; +#else +typedef int WRes; +#endif + +#ifndef RINOK +#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; } +#endif + +typedef unsigned char Byte; +typedef short Int16; +typedef unsigned short UInt16; + +#ifdef _LZMA_UINT32_IS_ULONG +typedef long Int32; +typedef unsigned long UInt32; +#else +typedef int Int32; +typedef unsigned int UInt32; +#endif + +#ifdef _SZ_NO_INT_64 + +/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers. + NOTES: Some code will work incorrectly in that case! */ + +typedef long Int64; +typedef unsigned long UInt64; + +#else + +#if defined(_MSC_VER) || defined(__BORLANDC__) +typedef __int64 Int64; +typedef unsigned __int64 UInt64; +#define UINT64_CONST(n) n +#else +typedef long long int Int64; +typedef unsigned long long int UInt64; +#define UINT64_CONST(n) n ## ULL +#endif + +#endif + +#ifdef _LZMA_NO_SYSTEM_SIZE_T +typedef UInt32 SizeT; +#else +typedef size_t SizeT; +#endif + +typedef int Bool; +#define True 1 +#define False 0 + + +#ifdef _MSC_VER + +#if _MSC_VER >= 1300 +#define MY_NO_INLINE __declspec(noinline) +#else +#define MY_NO_INLINE +#endif + +#define MY_CDECL __cdecl +#define MY_FAST_CALL __fastcall + +#else + +#define MY_CDECL +#define MY_FAST_CALL + +#endif + + +/* The following interfaces use first parameter as pointer to structure */ + +typedef struct +{ + Byte (*Read)(void *p); /* reads one byte, returns 0 in case of EOF or error */ +} IByteIn; + +typedef struct +{ + void (*Write)(void *p, Byte b); +} IByteOut; + +typedef struct +{ + SRes (*Read)(void *p, void *buf, size_t *size); + /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. + (output(*size) < input(*size)) is allowed */ +} ISeqInStream; + +/* it can return SZ_ERROR_INPUT_EOF */ +SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size); +SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType); +SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf); + +typedef struct +{ + size_t (*Write)(void *p, const void *buf, size_t size); + /* Returns: result - the number of actually written bytes. + (result < size) means error */ +} ISeqOutStream; + +typedef enum +{ + SZ_SEEK_SET = 0, + SZ_SEEK_CUR = 1, + SZ_SEEK_END = 2 +} ESzSeek; + +typedef struct +{ + SRes (*Read)(void *p, void *buf, size_t *size); /* same as ISeqInStream::Read */ + SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); +} ISeekInStream; + +typedef struct +{ + SRes (*Look)(void *p, const void **buf, size_t *size); + /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. + (output(*size) > input(*size)) is not allowed + (output(*size) < input(*size)) is allowed */ + SRes (*Skip)(void *p, size_t offset); + /* offset must be <= output(*size) of Look */ + + SRes (*Read)(void *p, void *buf, size_t *size); + /* reads directly (without buffer). It's same as ISeqInStream::Read */ + SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); +} ILookInStream; + +SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size); +SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset); + +/* reads via ILookInStream::Read */ +SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType); +SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size); + +#define LookToRead_BUF_SIZE (1 << 14) + +typedef struct +{ + ILookInStream s; + ISeekInStream *realStream; + size_t pos; + size_t size; + Byte buf[LookToRead_BUF_SIZE]; +} CLookToRead; + +void LookToRead_CreateVTable(CLookToRead *p, int lookahead); +void LookToRead_Init(CLookToRead *p); + +typedef struct +{ + ISeqInStream s; + ILookInStream *realStream; +} CSecToLook; + +void SecToLook_CreateVTable(CSecToLook *p); + +typedef struct +{ + ISeqInStream s; + ILookInStream *realStream; +} CSecToRead; + +void SecToRead_CreateVTable(CSecToRead *p); + +typedef struct +{ + SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize); + /* Returns: result. (result != SZ_OK) means break. + Value (UInt64)(Int64)-1 for size means unknown value. */ +} ICompressProgress; + +typedef struct +{ + void *(*Alloc)(void *p, size_t size); + void (*Free)(void *p, void *address); /* address can be 0 */ +} ISzAlloc; + +#define IAlloc_Alloc(p, size) (p)->Alloc((p), size) +#define IAlloc_Free(p, a) (p)->Free((p), a) + +#ifdef _WIN32 + +#define CHAR_PATH_SEPARATOR '\\' +#define WCHAR_PATH_SEPARATOR L'\\' +#define STRING_PATH_SEPARATOR "\\" +#define WSTRING_PATH_SEPARATOR L"\\" + +#else + +#define CHAR_PATH_SEPARATOR '/' +#define WCHAR_PATH_SEPARATOR u'/' +#define STRING_PATH_SEPARATOR "/" +#define WSTRING_PATH_SEPARATOR u"/" + +#endif + +#endif diff --git a/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile new file mode 100755 index 000000000000..609176a22395 --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile @@ -0,0 +1,63 @@ +#---------------------------------------------------------------------- +# include make config file +#---------------------------------------------------------------------- +include ../../../Project/Model/ModelConfig.txt +include ../../../Project/Model/ModelConfig_$(MODEL).txt +include ../../../Project/Model/MakeConfig.txt + +#---------------------------------------------------------------------- +# set the library name here +#---------------------------------------------------------------------- +PRJ_NAME = Ctrl_Flow + + +#---------------------------------------------------------------------- +# add/delete source files here +#---------------------------------------------------------------------- +SRC = \ + bl_func.c \ + main.c \ + nand_ids.c\ + spi_nor_ids.c\ + bl_lzma.c\ + LzmaDec.c\ + + + +ASM = + +#---------------------------------------------------------------------- +# set the include directory here +#---------------------------------------------------------------------- +INC_DIR = . \ + ../../../Include + +#---------------------------------------------------------------------- +# set the image output directory here +#---------------------------------------------------------------------- +IMG_BASE_DIR = ../../../ARC/Lib + +#---------------------------------------------------------------------- +# add additional C and assembly flags here +#---------------------------------------------------------------------- +CFLAGS_D = -O2 +ASMFLAGS_D = + +CFLAGS_R = -O2 +ASMFLAGS_R = + +C_DEFINE_EXT = \ + $(EXTSTRG_PARAM) \ + $(SECURE_DECRYPT_UBOOT_PARAM)\ + $(SECURE_DECRYPT_OPTEE_PARAM)\ + $(OPTEE_UBOOT_SIGNATURE_PARAM) \ + $(LOADER_TYPE_PARAM) \ + $(CARDDET_PIN_PARAM)\ + +CFLAGS_R = $(C_DEFINE_EXT) + +#---------------------------------------------------------------------- +# include common parts of the makefile +#---------------------------------------------------------------------- +MAKE_COMMON_DIR = ../../../MakeCommon +include $(MAKE_COMMON_DIR)/OutputLib.txt \ No newline at end of file diff --git a/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c new file mode 100755 index 000000000000..7f99c928e41d --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c @@ -0,0 +1,3396 @@ +/* + Main control function + + This file is implement by user mode + + @file bl_func.c + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ + +#include "fuart.h" +#include "fat.h" +#include "rtc.h" +#include "timer.h" +#include "StorageDef.h" +#include "global.h" +#include "Clock.h" +#include "bl_func.h" +#include "Cache.h" +#include "string.h" +#include "lz.h" +#include "debug.h" +#include "CC.h" +#include "loader.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "emb_partition_info.h" +#include "modelext_parser.h" +#include "bin_info.h" +#include "shm_info.h" +#include "gic.h" +#include "libfdt.h" +#include +#include "crypto.h" +#include "nand.h" +#include "nor.h" +#include "bl_lzma.h" + + +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +static uint32_t global_timer_freq = 3000000; //3MHz = 3000000 Hz +#endif +static PSTORAGE_OBJ int_strg_obj = NULL; + +#define FW_PART1_SIZE_OFFSET (CODE_SECTION_OFFSET + 0x04) //ref to CodeInfo.S on rtos (addr of _section_01_size) +//#define TEE_HEADER_SIZE 0x1C // refer to: optee_header_t + +#define _THUMB2 __attribute__((target("thumb"))) + +#define bl_memcpy utl_memcpy +#define bl_memset utl_memset +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#define SIZE_PRELOAD 0x400 +#define SIZE_PRESERVE_USB 0x2000 + +#define HEADINFO_UBOOT(p_parti) ((HEADINFO *)(p_parti->uboot_addr + BIN_INFO_OFFSET_UBOOT)) +#define HEADINFO_TEEOS(p_parti) ((HEADINFO *)(p_parti->teeos_addr + BIN_INFO_OFFSET_TEEOS)) +#define IS_BIN_OVERLAP(addr1, size1, addr2, size2) (!(((addr1 + size1 - 1) < addr2) || (addr1 > (addr2 + size2 - 1)))) +#if (STORAGE_EXT_TYPE == STORAGE_EXT_USB) +#define USB_SET_RESULT(x) USBSetResult(x) +#else +#define USB_SET_RESULT(x) +#endif + +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +extern void set_usb_suspend(void); +#endif + + +extern char _loader_exec_compres_start[]; +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base[]; +extern void core1_reset(void); + +// Function from Timer.c +//extern UINT32 timer_getLdrElapse(void); + +// Define in MakeConfig.txt +static UINT8 UPDATE_FW_NAME[] = {"FW98520A.BIN"}; +static UINT8 UPDATE_LOADER_NAME[] = {"LD98520A.BIN"}; +static UINT8 RUN_FW_NAME[] = {"FW98520T.BIN"}; +static UINT8 *LOADER_START_STR = {(UINT8 *)"\r\nLoader Start ..."}; +//#if !USB_WRITELOADER +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +//static UINT8 *RUN_WRKEY_NAME = {(UINT8 *)"WRKEY.BIN"}; +#if UPDATE_SIM_CODE +static UINT8 *RUN_WRKEY_NAME = {(UINT8 *)"SIM.BIN"}; +#endif +#endif +static UINT8 RECOVERY_FW_NAME[] = {"FW98520R.BIN"}; +static UINT32 g_uiPartitionID = 2; + +static UINT32 g_uiVersion = 0; + +// Error message +static char FWErrorMsg[] = "\r\nFW check fail\r\n"; +static char RWErrorMsg[] = "\r\nR/W error\r\n"; +static char LoaderErrorMsg[] = "\r\nLoader check fail\r\n"; + +UINT32 TopOfStack; +UINT32 BaseOfStack; + +extern char _loader_heap_base[]; + +static BOOL g_is_flash_open = FALSE; // indicate flash is open for updating non-fully all-in-one bin. + +static LDR_SPECIAL_KEY_CB gSpecialKeyCallBack = NULL; +static LDR_CARD_DETECT_CB gCardDetectCallBack = NULL; +static STORAGEINT gStorageIntType = STORAGEINT_UNOKNOWN; + +static LDR_RECOVERY_TRIGGER_CB gRecoveryTriggerCallBack = NULL; +//#if (!USB_WRITELOADER) +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +static BOOL g_is_recovery_triggered = FALSE; // indicate recovery flow is triggered. +#endif +_THUMB2 static int bl_is_smp(unsigned char *p_fdt); +static UINT32 g_uiStartBlkUpdateFW = StartNandBlkUpdateFW; +static UINT32 g_uiNandBlkSize = 0; +static UINT32 g_rtos_load_addr = 0; +static UINT32 g_rtos_target_addr = 0; +static UINT32 g_rtos_size = 0; + +#if (FDT_SUPPORT) +#define PATH_MEM_DRAM "/nvt_memory_cfg/dram" +#define PATH_MEM_LOADER "/nvt_memory_cfg/loader" +#define PATH_MEM_UBOOT "/nvt_memory_cfg/uboot" +#define PATH_MEM_FDT "/nvt_memory_cfg/fdt" +#define PATH_MEM_SHMEM "/nvt_memory_cfg/shmem" +#define PATH_MEM_RTOS "/nvt_memory_cfg/rtos" +#define PATH_MEM_NUTTX "/nvt_memory_cfg/nuttx" +#define PATH_MEM_TEEOS "/nvt_memory_cfg/teeos" +#define PATH_MEM_HDAL "/hdal-memory/media" +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +#define PATH_MEM_CORE2_ENTRY1 "/nvt_memory_cfg/core2entry1" +#define PATH_MEM_CORE2_ENTRY2 "/nvt_memory_cfg/core2entry2" +#endif +#define PATH_NVT_INFO "/nvt_info" +#define PATH_NVTPACK_INDEX "nvtpack/index" +#define PATH_PARTITION_LOADER "partition_loader" +#define PATH_PARTITION_FDT "partition_fdt" +#define PATH_PARTITION_UBOOT "partition_uboot" +#define PATH_PARTITION_NUTTX "partition_nuttx" +#define PATH_PARTITION_TEEOS "partition_teeos" +#define PATH_PARTITION_RTOS "partition_rtos" +#define PROPERTY_REG "reg" +#define PROPERTY_LABEL "label" +#define PROPERTY_PARTITION_NAME "partition_name" +#define PROPERTY_NVT_LINUX_SMP "NVT_LINUX_SMP" +static DRAM_PARTITION g_dram_partition = {0}; +static EMB_PARTITION g_emb_uboot = {0}; +#if (NUTTX_SUPPORT) +static EMB_PARTITION g_emb_nuttx = {0}; +#endif +static EMB_PARTITION g_emb_teeos = {0}; +static EMB_PARTITION g_emb_rtos = {0}; +#else // NO FDT_SUPPORT +// refer to met-tbl.dtsi /nvt_memory_cfg +static DRAM_PARTITION g_dram_partition = { + .dram_addr = 0x00000000, + .dram_size = 0x20000000, + .rev_addr = 0x00007E00, ///< shmem + .rev_size = 0x00000200, ///< shmem + .loader_addr = 0x01000000, + .loader_size = 0x00800000, + .fdt_addr = 0x01800000, + .fdt_size = 0x00040000, + .uboot_addr = 0x1E000000, + .uboot_size = 0x01FC0000, + .rtos_addr = 0x01840000, ///< optional, only for fast-boot, + .rtos_size = 0x00780000, ///< optional, only for fast-boot + .core2_entry1_addr = 0x00000000, ///< optional, only for dual core IC (fixed here, and must be) + .core2_entry1_size = 0x00004000, ///< optional, only for dual core IC + .core2_entry2_addr = 0x1FFC0000, ///< optional, only for dual core IC (address better in the bottom of dram to avoid memory space overlap) + .core2_entry2_size = 0x00040000, ///< optional, only for dual core IC +}; +// refer to storage-partition.dtsi +static EMB_PARTITION g_emb_uboot = { + .PartitionOffset = 0xC0000, + .PartitionSize = 0xA0000, +}; +static EMB_PARTITION g_emb_rtos = { ///< optional, only for fast-boot, + .PartitionOffset = 0x2B40000, + .PartitionSize = 0xA00000, +}; +static EMB_PARTITION g_emb_teeos = { ///< optional, only for optee, + .PartitionOffset = 0, + .PartitionSize = 0, +}; +//following just for processing all-in-one bin (nvtpack) +//refer to nvtpack.dtsi +#define NVTPACK_IDX_UBOOT 3 +#define NVTPACK_IDX_TEEOS -1 +#define NVTPACK_IDX_RTOS 10 +#endif + +#if (UART_UPDATE_ == ENABLE) +static char g_strLength[80]; // buffer to store length string +#endif + +//--------------------------------------------------------------------------- +// Static function +//--------------------------------------------------------------------------- +static int bl_boot_uboot(unsigned char *p_fdt); +static void *bl_get_rtos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/); + +/** + Display error message. + + Display error message. + CPU loop forever and LED is red. + + @param Msg: Message to display + @return void +*/ +_THUMB2 static void bl_displayErrMsg(char *Msg) +{ + // Display error message to UART + uart_putSystemUARTStr(Msg); + +#if (STORAGE_EXT_TYPE == STORAGE_EXT_USB) + USBStateMachine(); +#endif + + // Loop forever + while (1) { + ; + } +} + +#if 0 +/** + Do power off. + + Do power off. + + @return void +*/ +static void bl_turnOffPower(void) +{ + volatile UINT32 uiReg; + + uiReg = INREG32((CPE_RTC_BASE + 0x18)); + + // Reset shutdown timer + OUTREG32(CPE_RTC_BASE + 0x18, uiReg | 0x00000001); + // Do power off + OUTREG32(CPE_RTC_BASE + 0x18, uiReg | 0x00000002); + + // Because there is some latency between FW do power off and HW + // really power off, we have to loop forever to prevent CPU run + // other instructions. + while (1) { + ; + } +} +#endif + +#if (FW_CHECK_METHOD == FW_CHECK_CRC) +/** + Create CRC table. + + Create CRC table for CRC32 checking. + + @return void +*/ +static void bl_makeCRCTable(void) +{ + UINT32 uiValue, i, j; + + for (i = 0; i < 256; i++) { + uiValue = i; + for (j = 0; j < 8; j++) { + uiValue = uiValue & 1 ? 0xEDB88320 ^ (uiValue >> 1) : (uiValue >> 1); + } + g_uiCRCTable[i] = uiValue; + } +} +#endif + +/** + Invert endianess of input word + + + @param[in] a input word + + @return translated word +*/ +static UINT32 invertEndian(UINT32 a) +{ + return __builtin_bswap32(a); +} + +#if 0 +static void bl_compareFW(UINT32 uiAddr1, UINT32 uiAddr2, UINT32 size) +{ + UINT32 i; + UINT32 *p1, *p2; + + debug_msg_var("bl_compareFW uiAddr1=", uiAddr1); + debug_msg_var("bl_compareFW uiAddr2=", uiAddr2); + debug_msg_var("bl_compareFW size=", size); + + p1 = (UINT32 *)uiAddr1; + p2 = (UINT32 *)uiAddr2; + for (i = 0; i < size; i += 4) { + if (*p1 != *p2) { + debug_err_var("p1", (UINT32)p1); + debug_err_var("p2", (UINT32)p2); + debug_err_var("*p1", *p1); + debug_err_var("*p2", *p2); + } + p1++; + p2++; + } +} +#endif + + +/** + Check FW code. + + Check FW code and file length. + The FW binary file must be post-proecessd by encrypt_bin.exe. + This function must sync to encrypt_bin.exe. + If FW checking is fail, the CPU will loop forever and LED is red. + + @param[in] uiAddress FW code in DRAM starting address + @param[in] uiFileLen FW code length + @return void +*/ +_THUMB2 static void bl_checkFW(UINT32 uiAddress, UINT32 uiFileLen) +{ + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)uiAddress; + mem.len = uiFileLen; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + USB_SET_RESULT(USB_RESULT_LOADER_FAIL_FW_INVALID); + bl_displayErrMsg(FWErrorMsg); + } +} + +/** + Check boot loader code. + + Check boot loader code. + + @return void +*/ +_THUMB2 static void bl_checkLoader(UINT32 uiAddr, UINT32 uiSize) +{ + UINT16 *puiValue, uiSum; + UINT32 i; + + puiValue = (UINT16 *)uiAddr; + uiSum = 0; + + for (i = 0; i < (uiSize >> 1); i++) { + uiSum += (*puiValue + i); + puiValue++; + } + + if ((*(UINT16 *)(uiAddr + LOADER_TAG_OFFSET) != LOADER_TAG_VALUE) || + (uiSum != 0)) { + USB_SET_RESULT(USB_RESULT_LOADER_INVALIE_FW_FAIL); + bl_displayErrMsg(LoaderErrorMsg); + } +} +#if (SECURE_DECRYPT_UBOOT || SECURE_DECRYPT_OPTEE_OS) + + +_THUMB2 static void get_bininfo_size_offset(unsigned char* bininfo,unsigned int* size,unsigned int *offset) +{ + /****this headinfo is for encrypt header + BinInfo will set partition offset and size + BinInfo_1[0~3] public key offset + BinInfo_1[4~7] public key length + BinInfo_2[0~3] signature offset + BinInfo_2[4~7] signature length + BinInfo_3[0~3] encrypted offset + BinInfo_3[4~7] encrypted size + BinLength total bin size + Checksum total bin checksum + others parameters set 0 + */ + *size = bininfo[4] | bininfo[5]<<8 | bininfo[6] << 16 | bininfo[7] << 24; + *offset = bininfo[0] | bininfo[1] << 8 | bininfo[2] << 16 | bininfo[3] <<24; +} + + + + +_THUMB2 static int decrypt_aes_cbc(unsigned int input, unsigned int output, unsigned int len) +{ + + CRYPT_OP crypt_op_param; + + if(len &0x0f) + { + //debug_msg_var("enc size", len); + //debug_err("not align 16\r\n"); + return -21; + } + if((input & 0x03) || (output & 0x03) || (len & 0x03) ){ //check word alignment + //debug_msg_var("input", input); + //debug_msg_var("output", output); + //debug_msg_var("len", len); + //debug_err("not word align\r\n"); + return -22; + } + crypt_op_param.op_mode = CRYPTO_CBC; + crypt_op_param.en_de_crypt = CRYPTO_DECRYPT; + crypt_op_param.src_addr = input; + crypt_op_param.dst_addr = output; + crypt_op_param.length = len; //Need align to 16bytes align + //debug_msg_var("src",(unsigned int)crypt_op_param.src_addr); + //debug_msg_var("dst",(unsigned int)crypt_op_param.dst_addr); + + #if 0 + debug_msg_var("input",input); + debug_msg_var("output",output); + debug_msg_var("len",len); + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i=0; + debug_msg_var("encryped buf addr",(unsigned int)tmp); + for(i=0;i<16;i++){ + debug_msg_var("encryped buf",(unsigned int)tmp[i]); + } + #endif + if(crypto_data_operation(EFUSE_OTP_1ST_KEY_SET_FIELD, crypt_op_param) != 0) + { + //debug_err("aes dec fail\r\n"); + return -23; + } + #if 0 + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i=0; + tmp = (unsigned char *) crypt_op_param.dst_addr; + debug_msg_var("decryped addr",(unsigned int)&tmp[0]); + for(i=0;i<16;i++){ + debug_msg_var("decryped buf",(unsigned int)tmp[i]); + } + + #endif + return 0; + +} +#if (SECURE_SIGNATURE_BY_AES == 0) +_THUMB2 static void data_reverse(unsigned char* input_data, unsigned int size) +{ + unsigned int i=0; + unsigned char tmp=0; + for(i=0;i< (size/2);i++) + { + tmp = input_data[size - 1 - i]; + input_data[size - 1 - i] = input_data[i]; + input_data[i] = tmp; + } + +} +#endif +_THUMB2 static int do_decrypt_aes(unsigned int input_data, unsigned int output_data, unsigned int* output_size,unsigned int partition_size) +{ + + unsigned int encrypt_offset =0; + unsigned int encrypt_size =0; + unsigned int data_size = 0; + HEADINFO *p_headinfo = (HEADINFO *)input_data; + int er=0; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_3, &encrypt_size, &encrypt_offset); + data_size = p_headinfo->BinLength - encrypt_offset; +#if 1 //for signature check + unsigned int signature_offset =0; + unsigned int signature_size = 0; + UINT32 hash_buf[8]; + unsigned int sha256_align_size =0; + UINT32 * signature_buff = NULL; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_2, &signature_size, &signature_offset); + #if (SECURE_SIGNATURE_BY_AES == 0) + unsigned int key_offset =0; + unsigned int key_size =0; + unsigned int n_size=0; + unsigned int e_size=0; + UINT32 sign_rsa_output[64]; + UINT32 *key_n = NULL; + UINT32 *key_e = NULL; + UINT32 *signature_addr = NULL; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_1, &key_size, &key_offset); + n_size = signature_size;// if rsa 2048 , signature_size should be 256 bytes + e_size = key_size - n_size; + key_n = (UINT32 *)(input_data + key_offset); + // now only support rsa 2048 + key_e = (UINT32 *)(input_data + key_offset + signature_size); // signature_size should be 256 bytes, n key should be 256 + data_reverse((unsigned char *)(key_n),n_size); + data_reverse((unsigned char *)(key_e),e_size); + + er = rsa_keycheck(key_n, 1);// check rsa n key in efuse 1 and 2 field, 0 field for aes key + if(er == 0) + { + debug_err("key fail\r\n"); + return -20; + } + signature_addr = (UINT32 *)(input_data + signature_offset); + data_reverse((unsigned char *)signature_addr, signature_size); + + //decrypt signature + rsa_decrypt(signature_addr, signature_size, key_n, n_size, key_e, e_size,sign_rsa_output); + + data_reverse((unsigned char *)sign_rsa_output, signature_size); + + //remove pending data 0, the last 32 bytes will be signature data + signature_buff = (UINT32 *)&sign_rsa_output[(sizeof(sign_rsa_output)/4 ) - (32/4 )];// offset need devided by 4, because of UINT32 type + #else + //UINT32 sign_aes_output[8]; + + er = decrypt_aes_cbc((UINT32 )(input_data + signature_offset), output_data,signature_size); + if(er != 0) + { + debug_err("decrypt_aes_cbc fail\r\n"); + return -20; + } + signature_buff =(UINT32 *)output_data; + + #endif + //hash encrypt data + + if((data_size & 0x3f) != 0) + { + // hardware sha256 need align 64, need set pending 0 + sha256_align_size = ((data_size/0x40) + 1)*0x40; + bl_memset((unsigned char *)(input_data + encrypt_offset + data_size),0, sha256_align_size - data_size); + } + else + { + sha256_align_size = data_size; + } + + shahw((unsigned char *)(input_data + encrypt_offset), sha256_align_size, hash_buf); + + + //compare signature and current hash + if(memcmp((void *)hash_buf, (void *)signature_buff, sizeof(hash_buf)) != 0) + { + debug_err("sig fail\r\n"); + return -20; + } +#endif + + //decrypt data + //dma addr should 4 alignment, input_data address is 4 alignment + if((input_data + encrypt_offset) & 0x03) + { + utl_memcpy((void *)input_data,(unsigned char*)(input_data + encrypt_offset), data_size); + er = decrypt_aes_cbc(input_data, output_data, encrypt_size); + } + else + { + er = decrypt_aes_cbc(input_data + encrypt_offset, output_data, encrypt_size); + } + if(er != 0) + { + debug_err("aes fail\r\n"); + return er; + } + + *output_size = data_size; + + //add plaintext data to output buf--> aes should 16 alignment, if data not alignment, the last bytes we will not encrypt data + int plaintext_size = data_size - encrypt_size; + unsigned char *p_output = (unsigned char *)output_data; + if( plaintext_size > 0) + { + utl_memcpy(&p_output[encrypt_size], (unsigned char*)(input_data + encrypt_offset+ encrypt_size),plaintext_size); + } + return 0; + +} +#endif + +//#NT#2013/04/25#Steven Wang -begin +//#NT#Show Duty calibration log +#if (_LOADER_DUTY_CALIBRATION_ == ENABLE && _LOADER_DUTY_CALIBRATION_LOG_ == ENABLE) +void BL_showROMLog(UINT32 buffer) +{ + UINT32 value; + UINT32 index; + UINT32 P_duty; + UINT32 N_duty; + UINT32 diff; + + index = 0; + diff = 0; + P_duty = 0; + N_duty = 0; + uart_putSystemUARTStr("\r\n"); + while (1) { + value = INREG32(buffer + index); + + if ((value & 0xF0000000) == 0xF0000000) { + value &= ~(0x40000000); + uart_putSystemUARTStr(Dec2HexStr(value)); + uart_putSystemUARTStr(" = "); + } + + else if ((value & 0xF0000000) == 0x50000000) { + uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr("\r\n"); + } + + else if ((value & 0xF0000000) == 0x20000000) { +// uart_putSystemUARTStr("P_duty = "); + P_duty = value & 0xFFFFFFF; + //uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr(Dec2HexStr(P_duty)); + uart_putSystemUARTStr("\r\n"); + } + + else if ((value & 0xF0000000) == 0x30000000) { +// uart_putSystemUARTStr("N_duty = "); + N_duty = value & 0xFFFFFFF; + //uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr(Dec2HexStr(N_duty)); + uart_putSystemUARTStr("\r\n"); + if (P_duty > N_duty) { + if (diff == 2) { + uart_putSystemUARTStr("============\r\n"); + P_duty = 0; + N_duty = 0; + diff = 0; +// diff = 3; + } else { + diff = 1; + } + } else { + if (diff == 1) { + uart_putSystemUARTStr("============\r\n"); + P_duty = 0; + N_duty = 0; + diff = 0; +// diff = 3; + } else { + diff = 2; + } + } + } else if ((value & 0xF0000000) == 0x60000000) { + uart_putSystemUARTStr("N+P = "); + uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr("\r\n"); + } else if ((value & 0xF0000000) == 0x70000000) { + if ((value & 0xFFFFFFF) == 0x0654321) { + break; + } + } else { + uart_putSystemUARTStr("Unknow \r\n"); + } + index += 4; + } + uart_putSystemUARTStr("\r\n[0xC0001000] = 0x"); + uart_putSystemUARTStr(Dec2HexStr(INREG32(0xC0001000))); + uart_putSystemUARTStr(" [0xC000101C] = 0x"); + uart_putSystemUARTStr(Dec2HexStr(INREG32(0xC000101C))); + uart_putSystemUARTStr("\r\n"); +} +#endif +//#NT#2013/04/25#Steven Wang -end + + +#if (DRAM_RANGE_SCAN_EN == ENABLE) +/** + Check Sram code. + + Check is dram scan code or not + + @param[in] uiAddress Scan FW code in DRAM starting address + @return void +*/ +static BOOL bl_checkDramScanFW(UINT32 uiAddress) +{ + if ((*(UINT32 *)uiAddress & SRAM_TAG) == SRAM_TAG) { + return TRUE; + } else { + return FALSE; + } +} +#endif + +#if 0 +static BOOL bl_spiIdentify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + // Sample to support SST25VF032 + if ((uiMfgID == 0xBF) && + (uiCapacityID == 0x4A)) { + pIdentify->bDualRead = FALSE; + pIdentify->bSupportAAI = TRUE; + pIdentify->bSupportEWSR = TRUE; + pIdentify->uiFlashSize = 4 * 1024 * 1024; + return TRUE; + } + + return FALSE; +} +#endif + +/* + Update multi-binary image + + + @param[in] uiFwBuf buffer store fw read from card + + @return + -@ b TRUE: success + -@ b FALSE: fail +*/ + +#if !REMOVED_FLASH +#if 0 +static void bl_interrupt_init(void) +{ + debug_msg("arm_gic_distif_setup\r\n"); + arm_gic_distif_setup(); + debug_msg("arm_gic_cpuif_setup\r\n"); + arm_gic_cpuif_setup(); + + // + //debug_dump_addr(0xF1500000+0x1000,0x500); + //debug_dump_addr(0xF1500000+0x2000,0x100); +} +#endif + +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +#define OUTW(addr,value) (*(UINT32 volatile *)(addr) = (UINT32)(value)) +#define INW(addr) (*(UINT32 volatile *)(addr)) + + +_THUMB2 static void bl_cpu_timer_init(UINT32 value) +{ + UINT32 dwVal; + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_LOAD_OFFSET, value); + + dwVal = INW(configARM_TIMER_BASEADDR + ARM_TIMER_CONTROL_OFFSET); + /* Enable Auto reload mode. */ + dwVal |= ARM_TIMER_CONTROL_AUTO_RELOAD_MASK; + /* Clear prescaler control bits */ + dwVal &= ~ARM_TIMER_CONTROL_PRESCALER_MASK; + /* Set prescaler value */ + dwVal |= ((CYGHWR_HAL_RTC_PRESCALER - 1) << ARM_TIMER_CONTROL_PRESCALER_SHIFT); + /* Enable the decrementer */ + //dwVal |= ARM_TIMER_CONTROL_ENABLE_MASK; + /* Enable the interrupt */ + dwVal |= ARM_TIMER_CONTROL_IRQ_ENABLE_MASK; + + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_CONTROL_OFFSET, dwVal); + + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_ISR_OFFSET, + ARM_TIMER_ISR_EVENT_FLAG_MASK); + +} +#endif +#endif +_THUMB2 static int bl_flash_open(void) +{ + int er; + //UINT32 uiStorageVersion = (UINT32)&_load_nand_table_start_base; + + if (g_is_flash_open) { + return 0; + } + //========================================================================== + //= User define SPI-NAND id table sample code = + //= You can remove // to use it = + //========================================================================== + //int_strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_IDENTIFY_CB, (UINT32)nand_identify); + + //========================================================================== + //= User define SPI-NOR id table sample code = + //= You can remove // to use it = + //========================================================================== + //int_strg_obj->flash_installIdentifyCB(nor_identify); + + er = int_strg_obj->flash_open(); + if (er < 0) { + debug_err("flash open fail\r\n"); + return -1; + } + + //OUTREG32(NAND_TABLE_VERSION_ADDR, INREG32(uiStorageVersion)); + + //if (er == E_OK) { + // OUTREG32(NAND_TABLE_FLAG_ADDR, 0x46495053); //'S''P''I''F' + //} else { // E_OK_TABLE_FOUND(1) or E_OK_TABLE_NOT_FOUND(2) + // OUTREG32(NAND_TABLE_FLAG_ADDR, er); + //} + g_uiNandBlkSize = int_strg_obj->flash_getBlockSize(); + if (g_uiNandBlkSize == 0x10000) { + debug_msg("SPI NOR\r\n"); + g_uiStartBlkUpdateFW = 1; + } else if (g_uiNandBlkSize == EMMC_BLOCK_SIZE) { + debug_msg("EMMC\r\n"); + g_uiStartBlkUpdateFW = FDT_OFFSET / EMMC_BLOCK_SIZE; + } else { + g_uiStartBlkUpdateFW = StartNandBlkUpdateFW; + } + + g_is_flash_open = TRUE; + return 0; +} + +#if 0 //[-Werror=unused-function] +static int bl_flash_close(void) +{ + if (!g_is_flash_open) { + return 0; + } + + flash_close(); + g_is_flash_open = FALSE; + return 0; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static const void *bl_get_fdt_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + int nodeoffset; /* next node offset from libfdt */ + const void *nodep; /* property node pointer */ + + nodeoffset = fdt_path_offset(p_dtb, p_path); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} +#endif + + +_THUMB2 static unsigned char *bl_get_fdt_cfg(const void *p_dtb, MODELEXT_TYPE type) +{ +#if (FDT_SUPPORT) + int len; + const int *nodep; + + UINT8 *p_rt = NULL; + + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_DRAM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get dram fail\r\n"); + return NULL; + } + g_dram_partition.dram_addr = be32_to_cpu(nodep[0]); + g_dram_partition.dram_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_LOADER, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get loader fail\r\n"); + return NULL; + } + g_dram_partition.loader_addr = be32_to_cpu(nodep[0]); + g_dram_partition.loader_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_UBOOT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get uboot fail\r\n"); + return NULL; + } + g_dram_partition.uboot_addr = be32_to_cpu(nodep[0]); + g_dram_partition.uboot_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_FDT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get fdt fail\r\n"); + return NULL; + } + g_dram_partition.fdt_addr = be32_to_cpu(nodep[0]); + g_dram_partition.fdt_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_RTOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.rtos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.rtos_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_NUTTX, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.nuttx_addr = be32_to_cpu(nodep[0]); + g_dram_partition.nuttx_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_TEEOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.teeos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.teeos_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_HDAL, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get hdal fail\r\n"); + return NULL; + } + g_dram_partition.hdal1_addr = be32_to_cpu(nodep[0]); + g_dram_partition.hdal1_size = be32_to_cpu(nodep[1]); + if (len >= 16) { + g_dram_partition.hdal2_addr = be32_to_cpu(nodep[2]); + g_dram_partition.hdal2_size = be32_to_cpu(nodep[3]); + } + +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_CORE2_ENTRY1, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.core2_entry1_addr = be32_to_cpu(nodep[0]); + g_dram_partition.core2_entry1_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_CORE2_ENTRY2, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.core2_entry2_addr = be32_to_cpu(nodep[0]); + g_dram_partition.core2_entry2_size = be32_to_cpu(nodep[1]); + } +#endif + p_rt = (UINT8 *)&g_dram_partition; + break; + + case MODELEXT_TYPE_BIN_INFO: + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_SHMEM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get shmem fail\r\n"); + return NULL; + } + + if (sizeof(SHMINFO) > be32_to_cpu(nodep[1])) { + debug_err("shmem size mismatch\r\n"); + return NULL; + } + + p_rt = (UINT8 *)be32_to_cpu(nodep[0]); + break; + + default: + debug_err_var("not handle type\r\n", type); + return NULL; + } + return p_rt; +#else // NO FDT_SUPPORT + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + return (UINT8 *)&g_dram_partition; + case MODELEXT_TYPE_BIN_INFO: + return (UINT8 *)g_dram_partition.rev_addr; + default: + return NULL; + } +#endif +} + +_THUMB2 static int bl_chk_valid_all_in_one(NVTPACK_MEM *p_mem_all_in_one) +{ + NVTPACK_ER er; + NVTPACK_VER ver; + + er = nvtpack_getver(p_mem_all_in_one, &ver); + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + if (ver == NVTPACK_VER_16072017) { + return 0; + } + + return -1; +} + + +#if !REMOVED_FLASH +_THUMB2 static int bl_chk_fdt(unsigned int addr, unsigned int size) +{ + DRAM_PARTITION *p_dram_partition = NULL; + + if (fdt_check_full((void *)addr, size) != 0) { + debug_err("invalid dtb\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)addr, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("invalid dram_partition\r\n"); + return -1; + } + + // check tmp memory (file load) cannot overlap with uboot and teeos + // we allow to overlap with linux, root-fs because uboot will reload bin file later + debug_msg_var("tmp_addr", SDRAM_Start_FW); + +// if ((addr < p_dram_partition->uboot_addr && addr + size > p_dram_partition->uboot_addr) || +// (addr > p_dram_partition->uboot_addr && addr + size < p_dram_partition->uboot_addr + p_dram_partition->uboot_size)) { + if (IS_BIN_OVERLAP(addr, size, p_dram_partition->uboot_addr, p_dram_partition->uboot_size)) { + debug_err_var("a", addr); + debug_err_var("s", size); + debug_err("uboot olp\r\n"); + return -1; + } +#if 1 + //if ((addr < p_dram_partition->teeos_addr && addr + size > p_dram_partition->teeos_addr) || + // (addr > p_dram_partition->teeos_addr && addr + size < p_dram_partition->teeos_addr + p_dram_partition->teeos_size)) { + if (p_dram_partition->teeos_size) { + if (IS_BIN_OVERLAP(addr, size, p_dram_partition->teeos_addr, p_dram_partition->teeos_size)) { + debug_err_var("a", addr); + debug_err_var("s", size); + debug_err("teeos olp\r\n"); + return -1; + } + } +#endif + // check if memory size matched real size + UINT32 ld_dram1_size = dma_get_dram_capacity(DMA_ID_1); + if (p_dram_partition->dram_size > ld_dram1_size) { + debug_err_var("fw_d1_s", p_dram_partition->dram_size); + debug_err_var("ld_d1_s", ld_dram1_size); + debug_err("d1 s not matched.\r\n"); + return -1; + } + UINT32 ld_dram2_size = dma_get_dram_capacity(DMA_ID_2); + if (p_dram_partition->hdal2_size > ld_dram2_size) { + debug_err_var("fw_d2_s", p_dram_partition->hdal2_size); + debug_err_var("ld_d2_s", ld_dram2_size); + debug_err("d2 s not matched.\r\n"); + return -1; + } + return 0; +} +#endif + +#if !REMOVED_FLASH +_THUMB2 static int bl_chk_uboot(unsigned int addr, unsigned int size) +{ +#if (_FPGA_EMULATION_ == 0) + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)addr; + mem.len = size; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + debug_err("uboot check sum fail"); + return -1; + } +#endif + return 0; +} + +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +_THUMB2 static void bl_core2_reset(void) +{ + UINT32 core_reg; + + debug_msg("core2_reset\r\n"); + + core_reg = *(volatile UINT32 *)0xF0E400F0; + core_reg &= ~(1<<3); + core_reg &= ~(1<<11); + *(volatile UINT32 *)0xF0E400F0 = core_reg; + core_reg |= (1<<2)|(1<<10) | (1<<21); + core_reg |= (1<<17); + *(volatile UINT32 *)0xF0E400F0 = core_reg; +} + +_THUMB2 static void bl_core2_prepare(DRAM_PARTITION *p_dram_partition, unsigned int last_addr) +{ + extern char _load_core2_jump_program_start_base[]; + extern char _load_core2_jump_program_end_base[]; + extern char _load_core2_entry_program_start_base[]; + extern char _load_core2_entry_program_end_base[]; + UINT32 code2JumpCodelen, code2EntryCodelen; + + //check core2_entry1 must at addr 0 + if (p_dram_partition->core2_entry1_addr != CORE2_JUMP_ADDR) { + bl_displayErrMsg("core2entry1 != 0"); + } + + // copy core2 jump code to dram 0x0 + code2JumpCodelen = _load_core2_jump_program_end_base - _load_core2_jump_program_start_base; + utl_memcpy((void *)p_dram_partition->core2_entry1_addr, _load_core2_jump_program_start_base, code2JumpCodelen); +// CPUflushWriteCache(p_dram_partition->core2_entry1_addr, code2JumpCodelen); + +// debug_msg_var("core2_jump_program", (int)_load_core2_jump_program_start_base); + debug_msg_var("code2JumpCodelen", (int)code2JumpCodelen); + debug_msg_var("core2_entry2_addr", (int)p_dram_partition->core2_entry2_addr); + + // copy core2 entry code to dram specified by fdt + *(volatile UINT32 *)(NVT_CORE2_START) = p_dram_partition->core2_entry2_addr; + code2EntryCodelen = _load_core2_entry_program_end_base - _load_core2_entry_program_start_base; + utl_memcpy((void *)p_dram_partition->core2_entry2_addr, _load_core2_entry_program_start_base, code2EntryCodelen); +// CPUflushWriteCache(p_dram_partition->core2_entry2_addr, code2EntryCodelen); + + debug_msg_var("core2_entry_program", (int)_load_core2_entry_program_start_base); + debug_msg_var("code2EntryCodelen", (int)code2EntryCodelen); + + *(volatile UINT32 *)0xF07F8000 = last_addr; + + debug_msg_var("0xF07F8000=", (int)*(volatile UINT32 *)0xF07F8000); +} + +_THUMB2 static int bl_smp_start(unsigned char *p_modelext, UINT32 uboot_entry) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_modelext, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_modelext, MODELEXT_TYPE_DRAM_PARTITION); + if (p_bininfo == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + debug_msg_var("fdt", (UINT32)p_modelext); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_modelext; + + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + // clear cc_core1_addr, cc_core2_addr +//#if USB_WRITELOADER +#if (STORAGE_EXT_TYPE == STORAGE_EXT_USB) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; +#else +// if (card_get_type() == EXT_STORAGE_TYPE_ETH) +// p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +// else if (g_is_recovery_triggered) +// p_bininfo->comm.Resv[0] = BOOT_REASON_RECOVERY_SYS; +// else +#if (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +#else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif +#endif + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + + debug_msg("smp(no tee)\r\n"); + + bl_core2_prepare(p_dram_partition, 0); + +//#if USB_WRITELOADER +#if 0 + USBStateMachine(); + uart_putSystemUARTStr("USB update Done\n\r"); + timer_delay(1000000); + USBOTGReset(); +#endif + + + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + //reset core2 + bl_core2_reset(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)uboot_entry; + debug_msg_var("jump", uboot_entry); + p_func(); + } + + return 0; +} +#endif +_THUMB2 static int bl_entry_boot(unsigned char *p_fdt, UINT32 uboot_entry) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + debug_msg_var("fdt", (UINT32)p_fdt); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_fdt; + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + // clear cc_core1_addr, cc_core2_addr +#if (STORAGE_EXT_TYPE == STORAGE_EXT_USB) + CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; +#else + if (card_get_type() == EXT_STORAGE_TYPE_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; + else if (g_is_recovery_triggered) + p_bininfo->comm.Resv[0] = BOOT_REASON_RECOVERY_SYS; + else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + +#if 0//USB_WRITELOADER + USBStateMachine(); + uart_putSystemUARTStr("USB update Done\n\r"); + timer_delay(1000000); + USBOTGReset(); +#endif + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)uboot_entry; + debug_msg_var("jump", uboot_entry); + p_func(); + } + + return 0; +} + +_THUMB2 static int bl_copy_fdt_to_fdt_addr(unsigned char *p_fdt /*IN*/, unsigned char **pp_fdt /*OUT*/) +{ + DRAM_PARTITION *p_dram_partition; + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("bl_copy_fdt_to_fdt_addr failed.\r\n"); + return -1; + } + + // load fdt to fdt buffer + utl_memcpy((void *)p_dram_partition->fdt_addr, p_fdt, fdt_totalsize(p_fdt)); + *pp_fdt = (unsigned char *)p_dram_partition->fdt_addr; + + //reset shminfo + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + bl_memset(p_bininfo, 0, sizeof(SHMINFO)); + return 0; +} + +_THUMB2 static int bl_load_fdt_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char **pp_fdt /*OUT*/) +{ + NVTPACK_ER er; + NVTPACK_MEM emb_fdt; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + USB_SET_RESULT(USB_RESULT_LOADER_OK_FW_INVALID); + debug_err("packbin verify failed.\r\n"); + return -1; + } + + np_get_input.id = 1; // fdt must always put in partition[1] + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt); + + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } else if (er == NVTPACK_ER_SUCCESS) { + debug_msg_var("fdt addr", (int)emb_fdt.p_data); + debug_msg_var("fdt size", (int)emb_fdt.len); + if (bl_chk_fdt((unsigned int)emb_fdt.p_data, emb_fdt.len) == 0) { + return bl_copy_fdt_to_fdt_addr(emb_fdt.p_data, pp_fdt); + } + } + return -1; +} + +_THUMB2 static unsigned int bl_load_rtos_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_rtos; + int rtos_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + EMB_PARTITION *p_emb_partition_rtos = bl_get_rtos_partition(p_fdt, &rtos_partition_id); + + if (p_emb_partition_rtos == NULL) { + debug_err("null p_emb_partition_rtos\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + if(bl_is_smp(p_fdt)) { + bl_core2_prepare(p_dram_partition, 0); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + bl_core2_reset(); + } +#endif + + // get partition data address and size + input.id = (unsigned int)rtos_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_rtos); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + HEADINFO *p_headinfo = (HEADINFO *)(mem_rtos.p_data + BIN_INFO_OFFSET_RTOS); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_rtos.p_data; // describe compressed u-boot + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Uncompress(mem_rtos.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->rtos_addr, size_comp_le); + } else { + utl_memcpy((void *)p_dram_partition->rtos_addr, mem_rtos.p_data, p_headinfo->BinLength); + } + + if (p_dram_partition->rtos_addr != p_headinfo->CodeEntry) { + debug_msg_var("rtos_addr(fdt)=", p_dram_partition->rtos_addr); + debug_msg_var("rtos_addr(fw)=", p_headinfo->CodeEntry); + return -1; + } + + p_headinfo = (HEADINFO *)(p_dram_partition->rtos_addr+ BIN_INFO_OFFSET_RTOS); + // update loaded size + p_shminfo->boot.LdLoadSize = p_headinfo->BinLength; + // set LDCF_BOOT_CARD to disable partial load, becasue fw has loaded by loader + p_headinfo->Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] &= ~BOOT_FLAG_PARTLOAD_EN; + + + return 0; +} + +_THUMB2 static int bl_load_fdt_from_flash(unsigned char *p_tmp, unsigned int tmp_size, unsigned char **pp_fdt /*OUT*/) +{ + + // read first block to get dtb size + int blk_size = (int)int_strg_obj->flash_getBlockSize(); + int er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, blk_size, p_tmp, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash"); + return -1; + } + + int total_size = ALIGN_CEIL(fdt_totalsize(p_tmp), blk_size); + if ((int)tmp_size < total_size) { + debug_err_var("tmp_size too small, require:", fdt_totalsize(p_tmp)); + return -1; + } + + total_size -= blk_size; + if (total_size > 0) { + // read remain to get uboot starting addr on dram and offset in flash + er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW+1, total_size, p_tmp+blk_size, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash"); + return -1; + } + } + + if (bl_chk_fdt((unsigned int)p_tmp, fdt_totalsize(p_tmp)) == 0) { + return bl_copy_fdt_to_fdt_addr(p_tmp, pp_fdt); + } + + return -1; +} + +#if (FDT_SUPPORT) +_THUMB2 static char *bl_get_partition_name(unsigned char *p_fdt) +{ + const static char *p_names[3] = { + "/nand", + "/nor", + "/mmc@f0510000" + }; + + const char *name = NULL; + switch(gStorageIntType) { + case STORAGEINT_SPI_NAND: + name = p_names[0]; + break; + case STORAGEINT_SPI_NOR: + name = p_names[1]; + break; + case STORAGEINT_EMMC: + name = p_names[2]; + break; + default: + debug_err("loader_setStorageIntType needs.\r\n"); + return NULL; + } + + if (fdt_path_offset(p_fdt, name) > 0) { + return (char *)name; + } + + debug_err("E:bl_get_partition_name\r\n"); + return NULL; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static char *bl_make_fdt_path(char *root, char *name) +{ + //for fdt to combine the full path of node + static char g_tmp_path[64] = {0}; + g_tmp_path[0] = 0; + strcat(g_tmp_path, "/"); + strcat(g_tmp_path, root); + strcat(g_tmp_path, "/"); + strcat(g_tmp_path, name); + return g_tmp_path; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static int bl_get_partition(unsigned char *p_fdt /*IN*/, char *p_emb_name /*IN*/, EMB_PARTITION *p_emb/*OUT*/, int *p_id) +{ + int len; + const unsigned long long *nodep; + char *p_name = bl_get_partition_name(p_fdt); + char *p_path = NULL; + + if (p_name == NULL) { + return -1; + } + + p_path = bl_make_fdt_path(p_name, p_emb_name); + + // get partition offset and size + nodep = (const unsigned long long *)bl_get_fdt_property(p_fdt, p_path, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("bl_get_partition-1\r\n"); + return -1; + } + + p_emb->PartitionOffset = be64_to_cpu(nodep[0]); + p_emb->PartitionSize = be64_to_cpu(nodep[1]); + + // get partition label + char *p_label_name = (char *)bl_get_fdt_property(p_fdt, p_path, PROPERTY_LABEL, &len); + if (p_label_name == NULL) { + debug_err("bl_get_partition-2\r\n"); + return -1; + } + + // get id + p_path = bl_make_fdt_path(p_name, PATH_NVTPACK_INDEX); + int nodeoffset = fdt_path_offset(p_fdt, p_path); + + for (nodeoffset = fdt_first_subnode(p_fdt, nodeoffset); + (nodeoffset >= 0); + (nodeoffset = fdt_next_subnode(p_fdt, nodeoffset))) { + const struct fdt_property *prop; + + if (!(prop = fdt_get_property(p_fdt, nodeoffset, PROPERTY_PARTITION_NAME, &len))) { + break; + } + const char *p_id_name = fdt_get_name(p_fdt, nodeoffset, &len); + + if (strcmp(p_label_name, (char *)prop->data) == 0) { + *p_id = atoi(p_id_name + strlen("id")); + return 0; + } + } + + return -1; +} +#endif + +_THUMB2 static void *bl_get_uboot_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_UBOOT, &g_emb_uboot, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_UBOOT; +#endif + g_emb_uboot.EmbType = EMBTYPE_UBOOT; + return &g_emb_uboot; +} + +_THUMB2 static void *bl_get_rtos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_RTOS, &g_emb_rtos, p_id) != 0) { + return NULL; + } + +#else + *p_id = NVTPACK_IDX_RTOS; +#endif + g_emb_rtos.EmbType = EMBTYPE_RTOS; + return &g_emb_rtos; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static void *bl_get_nuttx_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ + if (bl_get_partition(p_fdt, PATH_PARTITION_NUTTX, &g_emb_nuttx, p_id) != 0) { + return NULL; + } + g_emb_nuttx.EmbType = EMBTYPE_NUTTX; + + return &g_emb_nuttx; +} +#endif + +_THUMB2 static void *bl_get_teeos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_TEEOS, &g_emb_teeos, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_TEEOS; +#endif + g_emb_teeos.EmbType = EMBTYPE_TEEOS; + return &g_emb_teeos; +} +#endif + +// return decompress_fw_size +_THUMB2 static unsigned int bl_decompress_rtos(UINT32 compress_addr, UINT32 compress_size, UINT32 fw_base_addr) +{ + UINT32 decoded_size; + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)compress_addr; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + + size_comp_le = (compress_size < size_comp_le) ? compress_size : size_comp_le; + decoded_size = LZ_Uncompress((UINT8 *)compress_addr + sizeof(NVTPACK_BFC_HDR), (UINT8 *)fw_base_addr, size_comp_le); + + //because some padding bytes are decoded, we must return real rtos size + return (decoded_size < size_uncomp_le) ? decoded_size : size_uncomp_le; +} + +#if !REMOVED_FLASH +_THUMB2 static int bl_load_uboot_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_uboot; + int uboot_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)uboot_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_uboot); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); +// debug_msg_var("uboot_size", p_dram_partition->uboot_size); +# if 1 + if(0) { +#else + if(is_secure_enable() == 0) { +#endif + if (bl_chk_uboot((unsigned int)mem_uboot.p_data, mem_uboot.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_uboot.p_data + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_uboot.p_data; // describe compressed u-boot + + // load uboot bin to dram partiton location + //debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + //debug_msg_var("uboot_size", p_dram_partition->uboot_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Uncompress(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->uboot_addr, size_comp_le); + } else { + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, p_headinfo->BinLength); + } + } else { +#if (SECURE_DECRYPT_UBOOT) + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, mem_uboot.len); + unsigned int plaintext_size =0; + + if((er = do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size))!= 0 ) + { + //debug_err("aes fail\r\n"); + return er; + } + if (bl_chk_uboot((unsigned int)p_dram_partition->uboot_addr, plaintext_size) != 0) { + return -1; + } +#else + if (bl_chk_uboot((unsigned int)mem_uboot.p_data, mem_uboot.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_uboot.p_data + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_uboot.p_data; // describe compressed u-boot + + // load uboot bin to dram partiton location + //debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + //debug_msg_var("uboot_size", p_dram_partition->uboot_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Uncompress(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->uboot_addr, size_comp_le); + } else { + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, p_headinfo->BinLength); + } +#endif + } + + return 0; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static int bl_load_nuttx_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_nuttx; + int nuttx_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_nuttx = bl_get_nuttx_partition(p_fdt, &nuttx_partition_id); + + if (p_emb_partition_nuttx == NULL) { + debug_err("null p_emb_partition_nuttx\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)nuttx_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_nuttx); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + // using check uboot's check sum is ok + if (bl_chk_uboot((unsigned int)mem_nuttx.p_data, mem_nuttx.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_nuttx.p_data + BIN_INFO_OFFSET_NUTTX); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_nuttx.p_data; // describe compressed u-boot + + // load nuttx bin to dram partiton location + debug_msg_var("nuttx_addr", p_dram_partition->nuttx_addr); + debug_msg_var("nuttx_size", p_dram_partition->nuttx_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Uncompress(mem_nuttx.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->nuttx_addr, size_comp_le); + } else { + utl_memcpy((void *)p_dram_partition->nuttx_addr, mem_nuttx.p_data, p_headinfo->BinLength); + } + + return 0; +} +#endif + +_THUMB2 static int bl_load_teeos_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_teeos; + int teeos_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_teeos = bl_get_teeos_partition(p_fdt, &teeos_partition_id); + HEADINFO *p_headinfo = NULL; + if (p_emb_partition_teeos == NULL) { + debug_err("null p_emb_partition_teeos\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)teeos_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_teeos); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + +#if 0 + if(1){ +#else + if(is_secure_enable()) { +#endif +#if (SECURE_DECRYPT_OPTEE_OS) + unsigned int plaintext_size =0; + utl_memcpy((void *)p_dram_partition->teeos_addr, mem_teeos.p_data, mem_teeos.len); + if((er = do_decrypt_aes(p_dram_partition->teeos_addr, p_dram_partition->teeos_addr,&plaintext_size, p_dram_partition->teeos_size))!= 0) + { + //debug_err("aes fail\r\n"); + return er; + } + + //this is the second headinfo information , not encrpyted headinfo + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); +#else + debug_err("please enable SECURE_DECRYPT_OPTEE_OS"); + return -1; +#endif + } + else{ + p_headinfo = (HEADINFO *)(mem_teeos.p_data + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot + utl_memcpy((void *)p_dram_partition->teeos_addr, (unsigned char*)mem_teeos.p_data, p_headinfo->BinLength); + } + UINT32 teeos_addr = p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR]; + + //check addr matched or not + debug_msg_var("teeos_addr", p_dram_partition->teeos_addr); + if (teeos_addr != p_dram_partition->teeos_addr) { + debug_msg_var("teeos_addr(bin)", teeos_addr); + debug_err("teeos addr not matched.\r\n"); + return -1; + } + + // using check uboot's check sum is ok + if (bl_chk_uboot((unsigned int)teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } + + return 0; +} + +_THUMB2 static int bl_load_uboot_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int uboot_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + +#if (SECURE_DECRYPT_UBOOT) + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(BIN_INFO_OFFSET_UBOOT + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read uboot failed + return -1; + } +#else + + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(BIN_INFO_OFFSET_UBOOT + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read uboot failed + return -1; + } + +#endif + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + debug_msg_var("uboot_size", p_dram_partition->uboot_size); +#if 0 + if(0){ +#else + if(is_secure_enable() == 0) { +#endif + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) + { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(size_comp_le, blk_size),p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash_comp,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + /* OpenIPC: algorithm 11, LZMA, as NA51089's loader takes it */ + if ((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF) == 11) { + if (invertEndian(pBfc->uiSizeUnComp) > p_dram_partition->uboot_size) { + debug_err_var("uboot_size", invertEndian(pBfc->uiSizeUnComp)); + return -1; + } + if (bl_lzma_inflate(p_tmp + sizeof(NVTPACK_BFC_HDR), size_comp_le, + (unsigned char *)p_dram_partition->uboot_addr, + invertEndian(pBfc->uiSizeUnComp)) < 0) { + debug_err("lzma\r\n"); + return -1; + } + debug_msg("lzma "); + } else + LZ_Uncompress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->uboot_addr, size_comp_le); + } + else + { + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + } + else + { +#if (SECURE_DECRYPT_UBOOT) + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); // describe uncompressed u-boot + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + unsigned int plaintext_size=0; + if((er =do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size))!= 0) + { + //debug_err("aes fail\r\n"); + return er; + } + + +#else + debug_msg("plase enable SECURE_DECRYPT_UBOOT config\r\n"); + return -1; +#endif + + } + + + + + return 0; +} + +_THUMB2 static int bl_load_rtos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int rtos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_rtos = bl_get_rtos_partition(p_fdt, &rtos_partition_id); + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + if (p_emb_partition_rtos == NULL) { + debug_err("null p_emb_partition_rtos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + if(bl_is_smp(p_fdt)) { + bl_core2_prepare(p_dram_partition, 0); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + bl_core2_reset(); + } +#endif + + // load 1st block of rtos to tmp dram (to detect compressed u-boot) + unsigned int bininfo_preload_size = ALIGN_CEIL(BIN_INFO_OFFSET_RTOS + sizeof(HEADINFO), blk_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, bininfo_preload_size, p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read rtos failed + } + + // flow to handle compressed u-boot and uncompressed one. + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + // load rtos bin to dram partiton location + //debug_msg_var("rtos_addr", p_dram_partition->rtos_addr); + //debug_msg_var("rtos_size", p_dram_partition->rtos_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) + { + /* lzma compressed image*/ + debug_msg("lzma, use uboot\r\n"); + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, ALIGN_CEIL(size_comp_le, blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_comp,er=", er); // read bfc-rtos failed + bl_displayErrMsg(RWErrorMsg); + } + LZ_Uncompress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->rtos_addr, size_comp_le); + } + } else { + BININFO *p_bininfo = (BININFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); // describe uncompressed u-boot + if (p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN) { + // copy bininfo_preload to rtos_addr + bl_memcpy((UINT8 *)p_dram_partition->rtos_addr, p_tmp, bininfo_preload_size); + // preload some to get part-1 size for partial load and partial compressed load + UINT32 preload_size = ALIGN_CEIL(FW_PART1_SIZE_OFFSET, blk_size) - bininfo_preload_size; + + if (preload_size!= 0) { + er = int_strg_obj->flash_readSectors( + (p_emb_partition_rtos->PartitionOffset + bininfo_preload_size) / blk_size, + preload_size, + (UINT8 *)(p_dram_partition->rtos_addr + bininfo_preload_size), NAND_RW_FIRMWARE + ); + + if (er < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + UINT32 part1_size = *(UINT32 *)(p_dram_partition->rtos_addr + FW_PART1_SIZE_OFFSET); + debug_msg_var("part1_size",part1_size); + part1_size = ALIGN_CEIL(part1_size, blk_size); + //debug_msg_var("part1_size_aligned",part1_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, part1_size, (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = part1_size; + } else { + // full load + debug_msg_var("rtos_size", p_bininfo->head.BinLength); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset /blk_size, ALIGN_CEIL(p_bininfo->head.BinLength, blk_size), (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = p_bininfo->head.BinLength; + } + } + return 0; +} + +_THUMB2 static int bl_load_teeos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int teeos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_teeos = bl_get_teeos_partition(p_fdt, &teeos_partition_id); + + if (p_emb_partition_teeos == NULL) { + debug_err("null p_emb_partition_teeos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // load 1st block of u-boot to tmp dram (to detect compressed u-boot) + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_teeos->PartitionOffset / blk_size, ALIGN_CEIL(BIN_INFO_OFFSET_TEEOS + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_teeos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read teeos failed + } + + // flow to handle compressed u-boot and uncompressed one. +#if (SECURE_DECRYPT_OPTEE_OS) + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); // describe uncompressed u-boot +#else + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot + +#endif + + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_teeos->PartitionOffset / blk_size, ALIGN_CEIL(p_headinfo->BinLength, blk_size), (UINT8 *)p_dram_partition->teeos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_teeos_from_flash,er=", er); // read bfc-teeos failed + bl_displayErrMsg(RWErrorMsg); + } +#if 0 + if(1){ +#else + if(is_secure_enable()) { +#endif +#if (SECURE_DECRYPT_OPTEE_OS) + + unsigned int plaintext_size=0; + if((er = do_decrypt_aes(p_dram_partition->teeos_addr, p_dram_partition->teeos_addr, &plaintext_size, p_dram_partition->teeos_size)) != 0) + { + //debug_err("aes fail\r\n"); + return er; + } + + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot +#else + debug_err("please ENABLE SECURE_DECRYPT_OPTEE_OS config\n"); + return -1; +#endif + } + + // load teeos bin to dram partiton location + UINT32 teeos_addr = p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR]; + debug_msg_var("teeos_addr", p_dram_partition->teeos_addr); + if (teeos_addr != p_dram_partition->teeos_addr) { + debug_msg_var("teeos_addr(bin)", teeos_addr); + debug_err("teeos addr not matched.\r\n"); + return -1; + } + //check check sum + if (bl_chk_uboot((unsigned int)teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } + return 0; +} +#endif + +//#if !USB_WRITELOADER +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +_THUMB2 static int bl_load_rtos_from_non_nvtpack(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + HEADINFO *p_headinfo = (HEADINFO *)(src_addr + BIN_INFO_OFFSET_RTOS); + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + // to avoid rtos_addr is overlapped by src_addr, we need extract some bits to get real rtos addr. + // compressed firmware + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr + SIZE_PRELOAD); + p_headinfo = (HEADINFO *)(src_addr + SIZE_PRELOAD + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = fat_read_rootfile((UINT8 *)src_addr, compress_size); + } else { + return -1; + } + } else if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + // uncompressed firmware + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + + src_size = fat_read_rootfile((UINT8 *)src_addr, uncompress_size); + src_addr = uncompress_addr; + src_size = uncompress_size; + debug_msg("uncompressed t.bin\r\n"); +#if (DRAM_RANGE_SCAN_EN == ENABLE) + } else if (utl_is_sram_fw(src_addr) == TRUE) { + debug_msg("detected as SRAM fw\r\n"); + src_size = fat_read_rootfile((UINT8 *)src_addr, FAT_READ_TOTAL_FILE_LENGTH); +#endif + } else { + return -1; + } + + *p_dst_addr = src_addr; + *p_dst_size = src_size; + return 0; +} +#endif + +#if (STORAGE_EXT_TYPE == STORAGE_EXT_USB) +_THUMB2 static int bl_load_rtos_from_usb_raw(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + HEADINFO *p_headinfo = (HEADINFO *)(src_addr + BIN_INFO_OFFSET_RTOS); + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + // to avoid rtos_addr is overlapped by src_addr, we need extract some bits to get real rtos addr. + // compressed firmware + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + // assume usb write loader receive full fw at 0x0200_0000, decompress it to smaller address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr - SIZE_PRESERVE_USB); + p_headinfo = (HEADINFO *)(src_addr - SIZE_PRESERVE_USB + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + utl_memcpy((void *)(uncompress_addr + uncompress_size), (void *)src_addr, compress_size); + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = compress_size; + } else { + return -1; + } + } else if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + // uncompressed firmware + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + debug_msg("uncompressed t.bin\r\n"); + utl_memcpy((void *)uncompress_addr, (void *)src_addr, uncompress_size); + src_size = uncompress_size; +#if (DRAM_RANGE_SCAN_EN == ENABLE) + } else if (utl_is_sram_fw(src_addr) == TRUE) { + debug_msg("detected as SRAM fw. NOt Support from USB\r\n"); +#endif + } else { + return -1; + } + + *p_dst_addr = src_addr; + *p_dst_size = src_size; + return 0; +} +#endif + +//#if !USB_WRITELOADER +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +_THUMB2 static int bl_load_rtos_from_uart(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ +#if UART_UPDATE_ + UINT32 tick_kms = 10; // timeout 1000 ms + char key; + + debug_msg("UART press Enter to\r\n"); + + while (--tick_kms) { + uart_chkChar(&key); + + if (key != 0x00) { + break; + } + timer_delay(100000); //100000 + debug_msg("."); + } + + if (tick_kms) { + UINT32 uiLength; + debug_msg("\r\nEnter uboot length (Decimal):\r\n"); //must \r\n at the end because of auto_test tool + uart_getStr_polling(g_strLength); + uiLength = DecStr2Int(g_strLength); + debug_msg("\r\nPlz pass uboot bin > "); + uart_getBinary((char *)src_addr, uiLength); // Temp Receive to DRAM start + debug_msg("\r\nGot it\r\n"); +#if (DRAM_RANGE_SCAN_EN == ENABLE) + // First word is code entry point address, once if entry address is 0xC000XXXX + // represent code is running on sram. + if (bl_checkDramScanFW(src_addr) == TRUE) { + UINT32 i; + + // Enable sram usage + SETREG32(0xF0900128, 0x00000002); + SETREG32(0xF0800128, 0x00000006); + SETREG32(0xF0020060, 0x00030002); + + uiLength = ((uiLength + 3) & 0xFFFFFFFC); + + for (i = 0; i < uiLength; i += 4) { + *(UINT32 *)(src_addr + i) = *(UINT32 *)(src_addr + i); + } + *(UINT32 *)(src_addr) = *(UINT32 *)(src_addr); + return 1; + } +#endif + if (*(UINT32 *)src_addr == MAKEFOURCC('B', 'C', 'L', '1')) { + HEADINFO *p_headinfo = NULL; + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + bl_checkFW(src_addr, uiLength); + debug_msg_var("uiLength", uiLength); + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr + uiLength); + p_headinfo = (HEADINFO *)(src_addr + uiLength + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + unsigned int ori_src_addr = src_addr; + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = uncompress_size; + utl_memcpy((void *)src_addr, (void *)ori_src_addr, uiLength); + *p_dst_addr = src_addr; + *p_dst_size = compress_size; + return 0; + } else { + return -1; + } + return 0; + } + } +#endif + return -1; +} +#endif + +_THUMB2 static void bl_update_uItron_headInfo(UINT32 fw_base_addr, DRAM_PARTITION *p_dram_partition) +{ + HEADINFO *pHeadInfo; +#if (UITRON_FW == ENABLE) + BININFO *pBinInfo; +#endif + pHeadInfo = (HEADINFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + if (p_dram_partition) { + pHeadInfo->ModelextAddr = p_dram_partition->fdt_addr; + } else { + pHeadInfo->ModelextAddr = 0; +#if (UITRON_FW == ENABLE) + pBinInfo = (BININFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + pBinInfo->ld.Resv[0] = LoaderInternalInfo[1]; + pBinInfo->ld.LdPackage = (LoaderInternalInfo[3] & 0xFFFF); +#endif + } +} + +_THUMB2 static int bl_update_loader_bininfo(unsigned char *p_fdt, unsigned int ld_flag, unsigned int rtos_loaded_size) +{ + BOOTINFO *p_ld; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + BININFO *p_bininfo = (BININFO *)(p_dram_partition->rtos_addr + BIN_INFO_OFFSET_RTOS); + + p_ld = &p_shminfo->boot; + if (!(p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN)) { + // LdLoadSize updated on uboot or bl_load_rtos_from_flash(), if BOOT_FLAG_PARTLOAD_EN + p_ld->LdLoadSize = rtos_loaded_size; + } + p_ld->LdLoadTime = timer_getLdrElapse(); + p_ld->LdResvSize = 0; //unused + p_ld->FWResvSize = 0; //unused + return 0; +} + +_THUMB2 static int bl_is_smp(unsigned char *p_fdt) +{ +#if (FDT_SUPPORT) + int len; + const char *nodep; + nodep = (const char *)bl_get_fdt_property(p_fdt, PATH_NVT_INFO, PROPERTY_NVT_LINUX_SMP, &len); + debug_msg_var("nodep", (UINT32)nodep); + if (nodep == NULL) { + return 0; + } + debug_msg((char *)nodep); + if (strcmp(nodep, "NVT_LINUX_SMP_ON") == 0) { + return 1; + } + return 0; +#elif (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + return 1; +#else + return 0; +#endif +} + +#if !REMOVED_FLASH +_THUMB2 static int bl_boot_uboot(unsigned char *p_fdt) +{ +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + UINT32 No_CPU; +#endif + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update shminfo + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + unsigned int *p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_shminfo->boot.LdPackage = p_param[3] & 0xFFFF; + p_shminfo->boot.LdStorage = (p_param[3] >> 16) & 0xFF; + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->uboot_addr + BIN_INFO_OFFSET_UBOOT); + + if (bl_chk_uboot(p_dram_partition->uboot_addr, p_headinfo->BinLength) != 0) { + return -1; + } + // start cpu2 + if (p_dram_partition->uboot_addr != p_headinfo->CodeEntry) { + debug_err_var("drampat-uboot_addr ", (int)p_dram_partition->uboot_addr); + debug_err_var("bin-uboot_addr ", (int)p_headinfo->CodeEntry); + return -1; + } + // for uboot to indicate this boot is all-in-one fw or non-all-in-one boot from uart or usb + // if boot from uart or usb with non-all-in-one fw, the uboot's ModelextAddr will be zero + p_headinfo->ModelextAddr = p_dram_partition->fdt_addr; + + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + UINT32 isSMP = bl_is_smp(p_fdt); + +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + No_CPU = *(UINT32 *)0xFFD00004; + No_CPU &= 0x3; + debug_msg_var("core No.=", No_CPU+1); +#endif + // init cpu timer +// bl_cpu_timer_init(CPU_TIMER_SETTING); +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + if (!isSMP || !No_CPU) +#else + if (!isSMP) +#endif + { +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + debug_msg_var("Bin core=", isSMP+1); +#endif + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + } else { +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + // init cpu timer + bl_cpu_timer_init(global_timer_freq); + + bl_smp_start(p_fdt, p_headinfo->CodeEntry); + // boot u-boot and never return back to loader +#else + //bl_smp_start(p_fdt, p_headinfo->CodeEntry); + debug_err("not support smp\r\n"); +#endif + } + return 0; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static int bl_boot_nuttx(unsigned char *p_fdt) +{ + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->nuttx_addr + BIN_INFO_OFFSET_NUTTX); + + if (bl_chk_uboot(p_dram_partition->nuttx_addr, p_headinfo->BinLength) != 0) { + return -1; + } + + // start cpu2 + if (p_dram_partition->nuttx_addr != p_headinfo->CodeEntry) { + debug_err_var("drampat-nuttx_addr ", (int)p_dram_partition->nuttx_addr); + debug_err_var("bin-nuttx_addr ", (int)p_headinfo->CodeEntry); + return -1; + } + + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + + // init cpu timer + bl_cpu_timer_init(CPU_TIMER_SETTING); + + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + // boot nuttx and never return back to loader + return 0; +} +#endif + +_THUMB2 static int bl_boot_teeos(unsigned char *p_fdt) +{ + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); + + // update uboot addr for teeos + p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_UBOOT_ADDR] = p_dram_partition->uboot_addr; + + +#if 0 //do not checksum, because teeos header has removed cause checksum failed + if (bl_chk_uboot(p_dram_partition->teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } +#endif + + //flush uboot + CPUflushWriteCache(p_dram_partition->uboot_addr, p_dram_partition->uboot_size); + //flush teeos + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + + // init cpu timer + +#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + bl_cpu_timer_init(CPU_TIMER_SETTING); + // boot core2 (after teeos is loaded) + if (HEADINFO_UBOOT(p_dram_partition)->BinCtrl & 0x00000002) { + //if SMP, trigger core2 + debug_msg("smp(tee2)\r\n"); + bl_core2_prepare(p_dram_partition, p_headinfo->CodeEntry); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + bl_core2_reset(); + } else { + debug_msg_var("not smp\r\n", p_headinfo->BinCtrl); + } +#endif + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + // boot teeos and never return back to loader + return 0; +} + +_THUMB2 static int bl_update_loader_flag(unsigned char *p_fdt, UINT32 uiLoaderFunc) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + + p_bininfo->boot.LdCtrl2 = 0; + if (uiLoaderFunc & FUNC_UPDATE_FW) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_FW; + } + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_LD; + } + if (uiLoaderFunc & FUNC_RUN_CARD) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_CARD; + } + if (uiLoaderFunc & FUNC_RUN_FLASH) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_FLASH; + } + //CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + debug_msg_var("LdCtrl2", p_bininfo->boot.LdCtrl2); + + unsigned int ver; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + BOOTINFO *p_ld = &p_shminfo->boot; + + utl_memset(p_ld->LdInfo_1, 0, sizeof(p_ld->LdInfo_1)); + utl_memcpy(p_ld->LdInfo_1, "LD_NVT", 6); + + ver = (((LoaderInternalInfo[1] >> 28) & 0xF) << 24) | + (((LoaderInternalInfo[1] >> 24) & 0xF) << 16) | + ((LoaderInternalInfo[1] >> 16) & 0xFF); + + if (g_uiVersion == 0) { + g_uiVersion = ver; + } + + utl_memcpy(&p_ld->LdInfo_1[8], &g_uiVersion, sizeof(g_uiVersion)); + unsigned int *p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_ld->LdPackage = p_param[3] & 0xFFFF; + p_ld->LdStorage = (p_param[3] >> 16) & 0xFF; + + return 0; +} + +// return uItron_fw_addr +_THUMB2 static unsigned int bl_process_all_in_one(UINT32 uiFwBuf, UINT32 uiFwBufSize, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + + + // load fdt + er = bl_load_fdt_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, &p_fdt); + if (er == -2) { // try to load from nand + debug_msg("fdt from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + er = bl_load_fdt_from_flash(p_tmp, 0x2000000, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + if (uiLoaderFunc & FUNC_UPDATE_FW) { + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + p_bininfo->comm.Resv[5] = uiFwBuf; // COMM_FW_UPD_ADDR + p_bininfo->comm.Resv[6] = uiFwBufSize; // COMM_FW_UPD_LEN + debug_msg_var("upd_src_addr=", uiFwBuf); + debug_msg_var("upd_src_size=", uiFwBufSize); + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + //check loader addr is matched with loader self. + extern char _loader_exec_compres_start[]; + if (p_dram_partition->loader_addr != (UINT32)_loader_exec_compres_start) { + debug_msg_var("p_dram_partition->loader_addr", p_dram_partition->loader_addr); + debug_msg_var("_loader_exec_compres_start", (UINT32)_loader_exec_compres_start); + bl_displayErrMsg("loader addr is not match."); + } + + //when rtos boot from flash, the boot from loader directly, + //but when rtos need to burn image, the uboot is still required. + //so, any one need to burn image, uboot is always needed to boot. + //if ((uiLoaderFunc & FUNC_UPDATE_FW) || p_dram_partition->rtos_addr == 0) { + if (1) { + // always use uboot to handle all-in-one bin + if (p_dram_partition->nuttx_size == 0 && p_dram_partition->teeos_size == 0) { + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er == -2) { // try to load from nand + debug_msg("uboot from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + } + + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else if (p_dram_partition->nuttx_size) { +#if (NUTTX_SUPPORT) + // load nuttx + er = bl_load_nuttx_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load nuttx failed\r\n"); + } + er = bl_boot_nuttx((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot nuttx failed\r\n"); + } +#else + bl_displayErrMsg("NUTTX_SUPPORT disabled\r\n"); +#endif + } else if (p_dram_partition->teeos_size) { + // load teeos + er = bl_load_teeos_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load teeos failed\r\n"); + } + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } + } + return er; + } else { + // this upgrade flow, skip uboot, boot rtos directly as T.bin + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + *pOut_dram_partition = p_dram_partition; + er = bl_load_rtos_from_all_in_one(p_fdt, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("boot rtos failed\r\n"); + } + + // add LDCF_BOOT_CARD to force rtos run as T.bin + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_CARD; + return p_dram_partition->rtos_addr; + } +} +#endif + +// return uItron_fw_addr, no need to fully decode +_THUMB2 static unsigned int bl_process_rtos_only(UINT32 uiFwBuf, UINT32 uiFwBufSize, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + UINT32 uItron_fw_addr; + NVTPACK_BFC_HDR *pBFC; + HEADINFO *p_headinfo; + + debug_msg("\r\nbl_process_rtos_only\r\n"); + pBFC = (NVTPACK_BFC_HDR *)uiFwBuf; + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 compressSize; + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + LZ_Uncompress((UINT8 *)uiFwBuf + LDC_HEADER_SIZE, p_tmp, SIZE_PRELOAD); + p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; +#if UITRON_FW + uItron_fw_addr = p_headinfo->CodeEntry - CODE_ENTRY_OFFSET; // cliff +#endif + + if ((uItron_fw_addr & 0x0000FFFF) != 0) { //cc engine's limitation + debug_err_var("rtos addr must match (&0x0000FFFF)==0", uItron_fw_addr); // but 660 allow + uItron_fw_addr = uItron_fw_addr & 0xFFFF0000; + } + compressSize = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //debug_dump_addr(tmpBuf,0x200); + debug_msg_var("F compress uItron_fw_addr", uItron_fw_addr); + // uiFwBuf has adjusted on bl_load_rtos_from_non_nvtpack() + *p_comp_addr = uiFwBuf; + *p_comp_size = compressSize; + } else { + p_headinfo = (HEADINFO *)(uiFwBuf + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; +#if UITRON_FW + uItron_fw_addr = p_headinfo->CodeEntry - CODE_ENTRY_OFFSET; // cliff +#endif + + if ((uItron_fw_addr & 0x0000FFFF) != 0) { //cc engine's limitation + debug_err_var("rtos addr must match (&0x0000FFFF)==0", uItron_fw_addr); // but 660 allow + uItron_fw_addr = uItron_fw_addr & 0xFFFF0000; + } + + debug_msg_var("Normal uItron_fw_addr", uItron_fw_addr); + *p_comp_addr = 0; + *p_comp_size = 0; + } + return uItron_fw_addr; +} +#if !UPDATE_EMU_CODE && !REMOVED_FLASH +_THUMB2 static unsigned int bl_process_flash_boot(unsigned char *p_tmp, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // load fdt + er = bl_load_fdt_from_flash(p_tmp, SDRAM_Start_FW, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition->teeos_size) { + // load teeos + er = bl_load_teeos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load teeos failed\r\n"); + } + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } + } else if (p_dram_partition->rtos_addr == 0) { + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { + // load rtos + er = bl_load_rtos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load rtos failed\r\n"); + } + } + + // update compressed rtos information + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((unsigned char *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + *p_comp_addr = p_bininfo->comm.Resv[3]; // COMM_UITRON_COMP_ADDR + *p_comp_size = p_bininfo->comm.Resv[4]; // COMM_UITRON_COMP_LEN + + *pOut_dram_partition = p_dram_partition; + return p_dram_partition->rtos_addr; +} +#endif + +/** + bl_process_update_loader. + + Write loader will update loader binary file + + @param[in] loader_addr loader in DRAM starting address + @param[in] loader_size loader code length (from loader header offset 0x24) + @return void +*/ +_THUMB2 static int bl_process_update_loader(unsigned int loader_addr, unsigned int loader_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card + if(is_secure_enable() == 0) { + +#if ((STORAGE_EXT_TYPE == STORAGE_EXT_ETH)|(STORAGE_EXT_TYPE == STORAGE_EXT_USB)) + UINT32 uiOffset; + uiOffset = *((UINT32 *)(loader_addr + 0x80)); + if(uiOffset) {//Combo loader + if(*(UINT32*)0xF00100F0 == 0x50210000) { + debug_msg("combo loader 528\r\n"); + bl_checkLoader(loader_addr+uiOffset, COMBINATION_LOADER_SIZE - uiOffset); //check 528 + } else{ + debug_msg("combo loader 52X\r\n"); + bl_checkLoader(loader_addr, loader_size); //check 52x + } + }else + bl_checkLoader(loader_addr, loader_size); +#else +#if (LOADER_TYPE == COMBINATION_528) + debug_msg("CB8\r\n"); + bl_checkLoader(loader_addr + loader_size, (COMBINATION_LOADER_SIZE - loader_size)); +#else //STAND_ALONE_LOADER or combination 52x loader + //debug_msg("STD\r\n"); + bl_checkLoader(loader_addr, loader_size); +#endif +#endif + } + debug_msg("update loader\r\n"); + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // Program loader +#if ((STORAGE_EXT_TYPE == STORAGE_EXT_ETH)|(STORAGE_EXT_TYPE == STORAGE_EXT_USB)) + UINT32 uiOffset; + uiOffset = *((UINT32 *)(loader_addr + 0x80)); + if(uiOffset) //Combo loader + loader_size = COMBINATION_LOADER_SIZE; + //If single loader , it already got +#else +#if (LOADER_TYPE == STAND_ALONE_LOADER_52x) || (LOADER_TYPE == STAND_ALONE_LOADER_528) +#else //Combination loader + loader_size = COMBINATION_LOADER_SIZE; +#endif +#endif + if (int_strg_obj->flash_writeSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)loader_addr, NAND_RW_LOADER) < 0) { + USB_SET_RESULT(USB_RESULT_LOADER_FAIL_FW_FAIL); + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = loader_addr + loader_size; + if (int_strg_obj->flash_readSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)reload_addr, NAND_RW_LOADER) < 0) { + USB_SET_RESULT(USB_RESULT_LOADER_INVALIE_FW_FAIL); + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)loader_addr, (void *)reload_addr, loader_size) != 0) { + USB_SET_RESULT(USB_RESULT_LOADER_INVALIE_FW_FAIL); + bl_displayErrMsg("verify fail\r\n"); + } + return 0; +} +#if UPDATE_EMU_CODE +_THUMB2 static int bl_process_update_emu_firmware(unsigned int emu_addr, unsigned int emu_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card +// bl_checkFW(emu_addr, emu_size); + debug_msg("update emu firmware size"); + uart_putSystemUARTStr(Dec2HexStr(emu_size)); + uart_putSystemUARTStr("\r\n"); + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // Program firmware + if (int_strg_obj->flash_writeSectors(g_uiStartBlkUpdateFW, emu_size, (UINT8 *)emu_addr, NAND_RW_FIRMWARE) < 0) { + USB_SET_RESULT(USB_RESULT_LOADER_OK_FW_FAIL); + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = emu_addr + emu_size; + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, emu_size, (UINT8 *)reload_addr, NAND_RW_FIRMWARE) < 0) { + USB_SET_RESULT(USB_RESULT_LOADER_OK_FW_FAIL); + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)emu_addr, (void *)reload_addr, emu_size) != 0) { + USB_SET_RESULT(USB_RESULT_LOADER_INVALIE_FW_FAIL); + bl_displayErrMsg("verify fail\r\n"); + } + return 0; +} +#endif + +_THUMB2 void bl_read_rtos_addr(UINT32 *pLoadAddr, UINT32 *pTargetAddr, UINT32 *pSize) +{ + *pLoadAddr = g_rtos_load_addr; + *pTargetAddr = g_rtos_target_addr; + *pSize = g_rtos_size; +} + +/** + main flow code + + If there is Calibration Firmware code store in NAND, running flow as follow + O's work flow + + @return fw base addr +*/ + +_THUMB2 UINT32 bl_mainFlow(void) +{ + UINT32 uiUpdateFileLen = 0; + UINT32 uiLoaderFunc = 0; + UINT32 uiLoaderSize = 32 * 1024; // pre-assume 32KB, actual size is parsed from loader + //Show Duty calibration log +#if (_LOADER_DUTY_CALIBRATION_ == ENABLE && _LOADER_DUTY_CALIBRATION_LOG_ == ENABLE) + UINT32 uiLoaderAddress; + UINT32 uiLogSramAddress; +#endif + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; + UINT32 uiFwBaseAddr = SDRAM_Start_FW; // FW base address + DRAM_PARTITION *p_dram_partition = NULL; + + // BaseOfStack is initialized at doRemapLZ.s + UINT32 uiheapBufferAddr = (UINT32)_loader_heap_base; +// UINT32 uiheapBufferAddr = BaseOfStack + 0x40000; // reserve 16KB for tmp buffer usage + UINT32 uiTmpBufferAddr = uiheapBufferAddr + FAT_HEAP_BUFFER_SIZE; + UINT32 uiUpdateBootloaderBufAddr = uiTmpBufferAddr + 0x4000; + UINT32 uiUpdateMainBinBufAddr = SDRAM_Start_FW; + + // UART initial sequence + //uart_openSystemUART(); + // rtc reset shutdown timer + // rtc_resetShutDownTimer(); + + + + +#if 0 + // adjust PAD driving (if required) + bl_adjustDriving(); + /* + - @b RTC_PWR_SW_STS: Power on source is PWR_SW + - @b RTC_PWR_VBAT_STS: Power on source is PWR_VBAT + - @b RTC_PWR_VBUS_STS: Power on source is PWR_VBUS + */ + uiPowerOnSrc = rtc_getPWRONSource(); + + if (uiPowerOnSrc & RTC_PWR_SW_STS) { + uart_putSystemUARTStr("\r\nSW PON\r\n"); + } else if (uiPowerOnSrc & RTC_PWR_VBAT_STS) { + uart_putSystemUARTStr("\r\nVBAT PON\r\n"); + } else if (uiPowerOnSrc & RTC_PWR_VBUS_STS) { + uart_putSystemUARTStr("\r\nVBUS PON\r\n"); + } else if (rtc_getIsAlarmPowerOn()) { + uart_putSystemUARTStr("\r\nPwrAlarm PON\r\n"); + } else { + uart_putSystemUARTStr("\r\nPOR PON\r\n"); + } +#endif + // Display Loader Version + debug_msg((char *)LOADER_START_STR); + UTL_setDrvTmpBufferAddress(uiTmpBufferAddr); + + +#if 0 // for now, reduce code size + if (rtc_chkS3boot()) { + UINT32 resume_addr; + + uart_putSystemUARTStr("main selfing..\r\n"); + resume_addr = bl_resume_cpu1((unsigned char *)_BOARD_IPC_ADDR_); + if (resume_addr == 0) { + // in codition for MODELEXT_BUILT_IN_ON + resume_addr = RESUME_ADDR; + } + return resume_addr; + } else { + + uart_putSystemUARTStr("main not selfing..\r\n"); + } +#endif + +#if 0 + // Sample to hook spi flash extending function + flash_installIdentifyCB(bl_spiIdentify); +#endif + prj_main(); + +//#if !USB_WRITELOADER +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) + set_usb_suspend(); + + if (bl_load_rtos_from_uart(uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH, &adjusted_addr, &adjusted_size) == 0) { + //specail case, load small rtos from uart + uiUpdateMainBinBufAddr = adjusted_addr; + uiUpdateFileLen = adjusted_size; + uiLoaderFunc |= FUNC_RUN_CARD; + } else if ((int_strg_obj->flash_getBlockSize() == EMMC_BLOCK_SIZE) && gRecoveryTriggerCallBack && gRecoveryTriggerCallBack()) { + debug_msg("Recovery triggered not support currently.\r\n"); +#if 0 + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } else { + flash_mount_fs(0, BaseOfStack + 0x4000, FAT_HEAP_BUFFER_SIZE); + if (flash_mount_partition(g_uiPartitionID) == E_OK) { + if (flash_open_file(RECOVERY_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + flash_read_file((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = flash_read_file((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + g_is_recovery_triggered = TRUE; + } else { + debug_msg("Recovery should be all in one bin!\r\n"); + } + } else { + debug_msg("no recovery bin!\r\n"); + } + } else { + debug_msg("Partition error!\r\n"); + } + } +#endif + } else if (((gSpecialKeyCallBack == NULL) || gSpecialKeyCallBack()) && + ((gCardDetectCallBack == NULL) || gCardDetectCallBack())) { + if (card_open() == TRUE && fat_initFAT(uiheapBufferAddr, FAT_HEAP_BUFFER_SIZE) == TRUE) { +#if UPDATE_SIM_CODE + BOOL bWDTInit = UTL_canUpdateSecKey(); + if (bWDTInit && fat_open_rootfile(RUN_WRKEY_NAME) == TRUE) { + debug_msg("sim.bin exist\r\n"); // the others A or T are skipped. + // Read byte count specified in file directory entry + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_WRBIN; + } else { // exclude others update if FUNC_RUN_WRBIN is existing. +#endif + // Update loader or not, loader is fixed to 16 KB + if (fat_open_rootfile(UPDATE_LOADER_NAME) == TRUE) { + // Read byte count specified in file directory entry + fat_read_rootfile((UINT8 *)uiUpdateBootloaderBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_UPDATE_LOADER; + uiLoaderSize = *((UINT32 *)(uiUpdateBootloaderBufAddr + 0x24)); + } + // "Update FW" or "Run FW" function + // Update FW has higher priority + if (fat_open_rootfile(UPDATE_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + } else { + // only rtos + debug_msg("not all-in-one, force behavior as T bin.\r\n"); + adjusted_addr = 0; + adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) == 0) { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } else { + bl_displayErrMsg("invalid firmware"); + } +#if UPDATE_EMU_CODE + uiLoaderFunc |= FUNC_UPDATE_FW; +#else + uiLoaderFunc |= FUNC_RUN_CARD; +#endif + + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + } + // Run FW has lower priority + else if (fat_open_rootfile(RUN_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + } else { + // Read rtos + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) != 0) { + bl_displayErrMsg("invalid firmware"); + } else { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } + uiLoaderFunc |= FUNC_RUN_CARD; + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_CARD; + } +#if UPDATE_SIM_CODE + } +#endif + card_close(); + } else { + debug_msg("card open fail\r\n"); +// while (1); + } + } else if (((gSpecialKeyCallBack == NULL) || gSpecialKeyCallBack()) && + ((gCardDetectCallBack != NULL) || (gCardDetectCallBack() == FALSE))) { + debug_msg("No card inserted\r\n"); + } +#else +// Boot from USB + { + UINT32 *pCfgBuf; + + // Clear UPDATE_CFG buffer + pCfgBuf = (UINT32 *)(UPDATE_CFG_BUFADDR + UPDATE_CFG_LOADER_OFS); + pCfgBuf[UPDATE_CFG_TAG] = 0; + pCfgBuf = (UINT32 *)(UPDATE_CFG_BUFADDR + UPDATE_CFG_FW_OFS); + pCfgBuf[UPDATE_CFG_TAG] = 0; + + CPUCleanInvalidateDCacheAll(); + + uart_putSystemUARTStr("Download from USB.\r\n"); + USBDownload(); + + CPUCleanInvalidateDCacheAll(); + + pCfgBuf = (UINT32 *)(UPDATE_CFG_BUFADDR + UPDATE_CFG_LOADER_OFS); + if ((pCfgBuf[UPDATE_CFG_TAG] == UPDATE_CFG_TAGCODE) && (pCfgBuf[UPDATE_CFG_ITEM] == UPDATE_CFG_ITEM_LD)) { + uiLoaderFunc |= FUNC_UPDATE_LOADER; + uiUpdateBootloaderBufAddr = pCfgBuf[UPDATE_CFG_ADDR]; + + // loader size from loader content + uiLoaderSize = *((UINT32 *)(uiUpdateBootloaderBufAddr + 0x24)); + + uart_putSystemUARTStr("Update Loader Flag OK.\r\n"); + } + + pCfgBuf = (UINT32 *)(UPDATE_CFG_BUFADDR + UPDATE_CFG_FW_OFS); + if ((pCfgBuf[UPDATE_CFG_TAG] == UPDATE_CFG_TAGCODE) && (pCfgBuf[UPDATE_CFG_ITEM] == UPDATE_CFG_ITEM_FW)) { + NVTPACK_MEM mem_in ; + + if ((pCfgBuf[UPDATE_CFG_ADDR]) != SDRAM_Start_FW) { + uart_putSystemUARTStr("ERROR: NvtUSBD.ini 's FW_ADDR must config to 0x02000000\r\n"); + while (1); + } + + uiUpdateFileLen = pCfgBuf[UPDATE_CFG_LEN]; + + mem_in.p_data = (void *)pCfgBuf[UPDATE_CFG_ADDR]; + mem_in.len = uiUpdateFileLen; + + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiLoaderFunc |= FUNC_UPDATE_FW; + } else { + // only rtos + debug_msg("not all-in-one, force behavior as T bin.\r\n"); + adjusted_addr = 0; + adjusted_size = 0; + if (bl_load_rtos_from_usb_raw(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) != 0) { + bl_displayErrMsg("invalid firmware"); + } else { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateMainBinBufAddr = adjusted_addr; + uiUpdateFileLen = adjusted_size; + } + uiLoaderFunc |= FUNC_RUN_CARD; + } + + uart_putSystemUARTStr("Update Firmware Flag OK.\r\n"); + USB_SET_RESULT(USB_RESULT_LOADER_OK_FW_OK); // pre-assume update is OK + } + } +#endif + + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + bl_process_update_loader(uiUpdateBootloaderBufAddr, uiLoaderSize); + } + + // Run FW + UINT32 comp_addr = 0; + UINT32 comp_size = 0; + if (uiLoaderFunc & (FUNC_RUN_CARD | FUNC_UPDATE_FW)) { + debug_msg("RC\r\n"); + NVTPACK_MEM mem_in ; + int chk_valid_all_in_one; +#if (DRAM_RANGE_SCAN_EN == ENABLE) + // First word is code entry point address, once if entry address is 0xC000XXXX + // represent code is running on sram. + debug_msg("Check SRAM fw\r\n"); + if (bl_checkDramScanFW(uiUpdateMainBinBufAddr) == TRUE) { + + debug_msg("This fw is on SRAM\r\n"); + // Enable sram usage + SETREG32(0xF0900128, 0x00000002); + SETREG32(0xF0800128, 0x00000006); + SETREG32(0xF0020060, 0x00030002); + + debug_msg(Dec2HexStr(*((UINT32 *)SRAM_Start_FW))); + debug_msg("before jump\r\n"); +// while (b_debug_go == FALSE); + load_dram_scan(uiUpdateMainBinBufAddr, uiUpdateFileLen); + return *((UINT32 *)SRAM_Start_FW); + } +#endif + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + chk_valid_all_in_one = bl_chk_valid_all_in_one(&mem_in); + if (chk_valid_all_in_one == 0) { + // all-in-one flow + // File len got from fat_read_rootfile() may exceed actual file size. + // In such condition, we should use info in NVTPACK_FW_HDR2 + if (((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize < uiUpdateFileLen) { + uiUpdateFileLen = ((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize; + mem_in.len = uiUpdateFileLen; + } +#if (REMOVED_FLASH == ENABLE) + bl_displayErrMsg("cannot process all-in-one fw"); +#else + uiFwBaseAddr = bl_process_all_in_one(uiUpdateMainBinBufAddr, uiUpdateFileLen, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); +#endif + } else { + // non-all-in-one flow + // check valid + if (uiLoaderFunc & FUNC_UPDATE_FW) { +#if UPDATE_EMU_CODE + bl_process_update_emu_firmware(uiUpdateMainBinBufAddr, uiUpdateFileLen); +#else + USB_SET_RESULT(USB_RESULT_LOADER_OK_FW_FAIL); + bl_displayErrMsg("cannot write non-all-in-one fw"); +#endif + } + uiFwBaseAddr = bl_process_rtos_only(uiUpdateMainBinBufAddr, mem_in.len, uiLoaderFunc, &comp_addr, &comp_size); + } + + // here uiFwBaseAddr is ready to use. + if (comp_addr == 0) { + HEADINFO *p_headinfo = (HEADINFO *)(uiFwBaseAddr + BIN_INFO_OFFSET_RTOS); + debug_msg("Nrml\r\n"); + if (chk_valid_all_in_one == 0) { + uiUpdateFileLen = p_headinfo->BinLength; + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + // uiUpdateFileLen is already set when file is loaded + } + } else { + debug_msg("Fcompress\r\n"); + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + debug_msg_var("uiUpdateFileLen", uiUpdateFileLen); + //boot from flash or update fw is no need to check sanity because of ecc, turn on it just for debug + if (uiLoaderFunc & FUNC_RUN_CARD) { + bl_checkFW(uiUpdateMainBinBufAddr, uiUpdateFileLen); + } + if (chk_valid_all_in_one == 0) { + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); + } else { + debug_msg_var("fw load addr", uiUpdateMainBinBufAddr); + bl_update_uItron_headInfo(uiUpdateMainBinBufAddr, p_dram_partition); + } + } else { //boot from flash +#if (REMOVED_FLASH == DISABLE) +#if UPDATE_EMU_CODE +// UINT32 uiNandBlkSize; + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + debug_msg("RFlash\r\n"); + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, g_uiNandBlkSize, (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiUpdateFileLen = *(volatile UINT32 *)(SDRAM_Start_FW + 0x168); + + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW + 1, uiUpdateFileLen - g_uiNandBlkSize, (UINT8 *)(SDRAM_Start_FW + g_uiNandBlkSize), NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiFwBaseAddr = bl_process_rtos_only(SDRAM_Start_FW, uiUpdateFileLen, uiLoaderFunc, &comp_addr, &comp_size); + bl_checkFW(SDRAM_Start_FW, uiUpdateFileLen); + uiUpdateMainBinBufAddr = SDRAM_Start_FW; + if (comp_addr == 0) { + debug_msg("Nrml\r\n"); + } else { + debug_msg("Fcompress not support\r\n"); + } + +#else + uiFwBaseAddr = bl_process_flash_boot((UINT8 *)SDRAM_Start_FW, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); + if (comp_addr == 0) { + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + // no need to bl_checkFW, because check sanity in flash_read + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); +#endif +#endif + } + + if (p_dram_partition) { + bl_update_loader_bininfo((unsigned char *)p_dram_partition->fdt_addr, uiLoaderFunc, uiUpdateFileLen); + } + +#if (STORAGE_EXT_TYPE == STORAGE_EXT_USB) + USBStateMachine(); + uart_putSystemUARTStr("USB update Done\n\r"); + timer_delay(1000000); + USBOTGReset(); +#endif +#if UPDATE_EMU_CODE + debug_msg_var("emu fw len", uiUpdateFileLen); +#endif + g_rtos_load_addr = uiUpdateMainBinBufAddr; + g_rtos_target_addr = uiFwBaseAddr; + g_rtos_size = uiUpdateFileLen; + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + debug_msg_var("rtos start", uiFwBaseAddr); + return uiFwBaseAddr; + +} + +_THUMB2 void loader_setUpdateFwName(char *fileName) +{ + strncpy((char *)UPDATE_FW_NAME, fileName, sizeof(UPDATE_FW_NAME)); +} + +_THUMB2 void loader_setUpdateLdrName(char *fileName) +{ + strncpy((char *)UPDATE_LOADER_NAME, fileName, sizeof(UPDATE_LOADER_NAME)); +} + +_THUMB2 void loader_setRunFwName(char *fileName) +{ + strncpy((char *)RUN_FW_NAME, fileName, sizeof(RUN_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryFwName(char *fileName) +{ + strncpy((char *)RECOVERY_FW_NAME, fileName, sizeof(RECOVERY_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryPartitionID(UINT32 partition_id) +{ + g_uiPartitionID = partition_id; +} + +_THUMB2 void loader_setVersion(UINT32 version) +{ + g_uiVersion = version; +} + +_THUMB2 void loader_installSpecialKeyCB(LDR_SPECIAL_KEY_CB callback) +{ + gSpecialKeyCallBack = callback; +} + +_THUMB2 void loader_installCardDetectCB(LDR_CARD_DETECT_CB callback) +{ + gCardDetectCallBack = callback; +} + +_THUMB2 void loader_installRecoveryTriggerCB(LDR_RECOVERY_TRIGGER_CB callback) +{ + gRecoveryTriggerCallBack = callback; +} + +_THUMB2 void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj) +{ + gStorageIntType = type; + int_strg_obj = strg_obj; +} diff --git a/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h new file mode 100755 index 000000000000..48b07bb85348 --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h @@ -0,0 +1,300 @@ +/** + @file bl_func.h + @brief Header file for main function + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ +#ifndef _BL_MAIN_H +#define _BL_MAIN_H + +#include "main.h" +#include "IOReg.h" +#include "GPIO.h" + +//------------------------------------------------------------------------------ +// Compiler option +// +// These compiler option are define in MakeConfig.txt +//!!!!!!!!!!!!!!!!!!! DO NOT MODIFY COMPILER OPTION HERE !!!!!!!!!!!!!!!!!!!! +//------------------------------------------------------------------------------ +#ifndef SECURE_DECRYPT_UBOOT +#define SECURE_DECRYPT_UBOOT 0 //Decrypt uboot sample code +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt + +#ifndef SECURE_DECRYPT_OPTEE_OS +#define SECURE_DECRYPT_OPTEE_OS 0 //Decrypt optee_os sample code +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt +#ifndef SECURE_SIGNATURE_BY_AES +#define SECURE_SIGNATURE_BY_AES 0 //using aes to decrypt signature +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt + + +#if (SECURE_DECRYPT_UBOOT || SECURE_DECRYPT_OPTEE_OS) +#define SECURE_OFFSET 1024 //Decrypt uboot from which offset +#endif + +// Define LED_FUNCTION == ENABLE will enable LED on/off in boot loader +#define LED_FUNCTION ENABLE//DISABLE + +// FW checking method, support checksum & CRC now +//#define FW_CHECK_NOCHECK 0 +//#define FW_CHECK_CHECKSUM 1 +//#define FW_CHECK_CRC 2 +#ifndef FW_CHECK_METHOD +#define FW_CHECK_METHOD FW_CHECK_CHECKSUM +#endif + +///#define FW_CHECK_INSTRUCTION0 0xE59FF018 + +// Optional pseudo string for checksum & CRC checking +#define FW_CHECK_PSEUDO_STR_EN DISABLE +#if (FW_CHECK_PSEUDO_STR_EN == ENABLE) + // Must sync to MakeConfig.txt + #define FW_CHECK_PSEUDO_STR "DSC_FW" +#endif + +// Determine if need to support compressable main code +#ifndef _MAINCODE_COMPRESS_ +#define _MAINCODE_COMPRESS_ 0 +#endif + +#ifndef STORAGEINT_SPI +#define STORAGEINT_SPI 0 +#endif + +//#NT#2011/06/30#Steven Wang -begin +//#NT#NTK self test flow enable / disable +#define FW_EXCEED_16MB_TEST DISABLE +//#NT#2011/06/30#Steven Wang -end + +//------------------------------------------------------------------------------ +// Global definition +//------------------------------------------------------------------------------ +#define LOADER_CODE_SIZE 0x8000 // Reserve 32 KB +//#NT#2011/06/10#Scottie -begin +//#NT#Remove, modify the mechanism of recording FW_CODE_SIZE & CALFW_CODE_SIZE + +#define RESERVED_DATA_SIZE 0x4000 // Fixed to 16 KB + +//#NT#2011/06/10#Scottie -end + +//Once if optee exist need modify to 0x08000000 +//#define SDRAM_Start_FW 0x08000000 // DRAM uITRON starting address +#define SDRAM_Start_FW 0x02000000 // DRAM uITRON starting address +//#endif + +#define SRAM_Start_FW 0xF07c0000 // SRAM FW starting address + +#define SRAM_TAG 0xF0000000 // SRAM tag + +#define CORE2_JUMP_ADDR 0x00000000 // Core2 entry code should put on 0, because when core2 reset is released, core2 will jump to 0 and run + +#define CPU_TIMER_SETTING 0x00B71B00 //0x016E3600 + +#define _BOARD_IPC_ADDR_ 0x00002000 // must be the same with BOARD_IPC_ADDR on ModelConfig. + + +#define UPDATE_CFG_BUFADDR 0x05000000 +#define UPDATE_CFG_TAGCODE 0xABCD0043 +#define UPDATE_CFG_LOADER_OFS 0x00 +#define UPDATE_CFG_FW_OFS 0x10 + +#define UPDATE_CFG_ITEM_LD 0xABCD0001 +#define UPDATE_CFG_ITEM_FW 0xABCD0002 + +#define UPDATE_CFG_TAG 0 +#define UPDATE_CFG_ITEM 1 +#define UPDATE_CFG_ADDR 2 +#define UPDATE_CFG_LEN 3 + +#define USB_RESULT_LOADER_INVALID_FW_INVALID (0) +#define USB_RESULT_LOADER_INVALID_FW_OK (1) +#define USB_RESULT_LOADER_INVALIE_FW_FAIL (2) +#define USB_RESULT_LOADER_OK_FW_INVALID (3) +#define USB_RESULT_LOADER_FAIL_FW_INVALID (4) +#define USB_RESULT_LOADER_OK_FW_OK (5) +#define USB_RESULT_LOADER_FAIL_FW_OK (6) +#define USB_RESULT_LOADER_OK_FW_FAIL (7) +#define USB_RESULT_LOADER_FAIL_FW_FAIL (8) +#define USB_RESULT_OTHER (9) + +// Loader checking +#define LOADER_TAG_OFFSET 0x30 +#define LOADER_TAG_VALUE 0xAA55 + +//#NT#2011/06/30#Steven Wang -begin +//#NT#Checksum offset +///#define CHECKSUM_OFFSET 0x1C +#define CHECKSUM_TAG 0xAA55 +//#NT#2011/06/30#Steven Wang -end + +// Config table tag value (for USB flow) +#define CFG_TABLE_TAG (0x4B54564E) // 'N' 'V' 'T' 'K' + +#define COMPRESS_TAG_VALUE (0x314C4342) // use to distinguish full compressed main code + +#define SPI_FLASH_IDENTIFY (0x46495053) //'S''P''I''F' + +#define BOOTVER_SET(OutMaj,OutMin,InnMaj,InnMin) (((OutMaj)<<24)|((OutMin)<<16)|((InnMaj)<<8)|((InnMin))) + +#define BOOTVER_GETOuterMajor(Ver) (((Ver)&0xFF000000)>>24) +#define BOOTVER_GETOuterMinor(Ver) (((Ver)&0x00FF0000)>>16) +#define BOOTVER_GETInnerMajor(Ver) (((Ver)&0x0000FF00)>>8) +#define BOOTVER_GETInnerMinor(Ver) (((Ver)&0x000000FF)) + +// Define loader version (_LDR_VER_) in MakeConfig.txt +#define BOOTLOADER_OUTERMAJOR (((_LDR_VER_)&0xFF000000)>>24) +#define BOOTLOADER_OUTERMINOR (((_LDR_VER_)&0x00FF0000)>>16) +#define BOOTLOADER_INNERMAJOR (((_LDR_VER_)&0x0000FF00)>>8) +#define BOOTLOADER_INNERMINOR (((_LDR_VER_)&0x000000FF)) + +// Binary tag value +#define FW_BINARY_TAG 0xAA55544E // 'N' 'T' 0x55 0xAA + +// CAL FW size exit tag +#define CAL_SIZE_TAG 0x5A534C43 // CLSZ +// FW size exit tag +#define FW_SIZE_TAG 0x5A535746 // FWSZ + +// Reserved area FW size offset +#define RESERVED_AREA_FW_SIZE_OFFSET 0x00 +// Reserved area CAL size offset +#define RESERVED_AREA_CAL_SIZE_OFFSET 0x04 +// Reserved area FW size tag offset +#define RESERVED_AREA_FW_TAG_OFFSET 0x08 +// Reserved area CAL size tag offset +#define RESERVED_AREA_CAL_TAG_OFFSET 0x0C + +// Operation of boot loader +#define FUNC_UPDATE_FW 0x01 // Read FW code from card and update to NAND and run +#define FUNC_UPDATE_LOADER 0x02 // Read boot loader code from card and update to NAND +#define FUNC_RUN_CARD 0x04 // Read FW code from card and run +#define FUNC_RUN_FLASH 0x08 // Read FW code from internal flash and run +#define FUNC_UPDATE_CAL 0X10 // Update CAL data +#define FUNC_RUN_WRBIN 0X20 // RUN wrkey data +#define FUNC_RUN_UBOOT 0X40 // Read Uboot from card and run +#define FUNC_UPDATE_FW_DONE 0x0100 // update f/w to NAND/SPI done + +// API to turn on / off LED +#if (LED_FUNCTION == ENABLE) +// Red LED (DGPIO 6) +// Green LED (DGPIO 9) +#define TurnOff_RedLED() OUTREG32(CPE_GPIO_BASE + 0x4C, 0x00000040) +#define TurnOn_RedLED() OUTREG32(CPE_GPIO_BASE + 0x38, 0x00000040) +#define TurnOff_GreenLED() OUTREG32(CPE_GPIO_BASE + 0x4C, 0x00000200) +#define TurnOn_GreenLED() OUTREG32(CPE_GPIO_BASE + 0x38, 0x00000200) +#else +#define TurnOff_RedLED() +#define TurnOn_RedLED() +#define TurnOff_GreenLED() +#define TurnOn_GreenLED() +#endif + +//#define USB_WRITELOADER ENABLE +#define UART_UPDATE_ DISABLE +#define UPDATE_EMU_CODE DISABLE +#define REMOVED_FLASH DISABLE +#define NUTTX_SUPPORT DISABLE +#define UPDATE_SIM_CODE DISABLE +#define UITRON_FW DISABLE +#define FDT_SUPPORT ENABLE + +#define STAND_ALONE_LOADER_52x 0 +#define STAND_ALONE_LOADER_528 1 +#define COMBINATION_52x 2 +#define COMBINATION_528 3 + +/* OpenIPC: MakeConfig.txt picks it from CHIP (-DLOADER_TYPE) */ +#ifndef LOADER_TYPE +#define LOADER_TYPE STAND_ALONE_LOADER_52x +#endif + +#define COMBINATION_LOADER_SIZE 0x18000 + + +#if UITRON_FW + +#define CODE_ENTRY_OFFSET (0x0) ///< code entry starting offset (660/510 is 0x400, 680 is 0x0) //cliff +#endif + +#define EMUKIT 0 +#define DEMOKIT 0x1800000 +#define RESUME_ADDR DEMOKIT + +//#NT#2018/03/07#Ben Wang -begin +//#NT#Support EMMC boot flow +#define EMMC_BLOCK_SIZE 0x200 +#define FDT_OFFSET 0x40000 +//#NT#2018/03/07#Ben Wang -end + +#if (STORAGEINT_SPI == 1) + #define StartNandBlkUpdateLoader 0 + #define StartNandBlkReserved 0 + //#NT#2012/12/17#HH Chuang -begin + //#NT#Sync spi erase unit to best access size of f/w storage object + #define StartNandBlkUpdateFW 16 + //#NT#2012/12/17#HH Chuang -end +#else + #define StartNandBlkUpdateLoader 0 + #define StartNandBlkUpdateFW 2 +#endif + +#if (FW_CHECK_METHOD == FW_CHECK_CRC) +static UINT32 g_uiCRCTable[256]; +#endif + +//Define @prj_main.h +#if 0 +// Card detect GPIO offset +#define DGPIO_CARD_DETECT (P_GPIO_17) + + +#define CHECK_CARD_EXIST (ENABLE) +#if (CHECK_CARD_EXIST == ENABLE) +// MC16 default is config as input and pull up +#define bl_checkCardExist() (gpio_getPin(DGPIO_CARD_DETECT) == 0 ? TRUE : FALSE) +#else +#define bl_checkCardExist() TRUE +#endif +#endif +/** + @name Assert macros +*/ +//@{ +#define ASSERT_CONCAT_(a, b) a##b +#define ASSERT_CONCAT(a, b) ASSERT_CONCAT_(a, b) + +#if defined(__COUNTER__) + +#define STATIC_ASSERT(expr) \ +enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __COUNTER__) = 1/(expr) } + +#else + +// This might cause compile error when writing STATIC_ASSERT at the same line +// in two (or more) files and one file include another one. +#define STATIC_ASSERT(expr) \ +enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __LINE__) = 1/(expr) } + +#endif +//@} + +//#NT#2010/05/21#Steven Wang -begin +//#NT#Check if FW size > EXEC base address +extern UINT32 _load_BOOT_EXEC_start_base; +//#NT#2010/05/21#Steven Wang -end + +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[]; + +extern UINT32 LoaderInternalInfo[]; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern UINT32 bl_mainFlow(void); +extern UINT32 BaseOfStack; + +// project(customer) main function +extern void prj_main(void); +extern void bl_read_rtos_addr(UINT32* pLoadAddr, UINT32* pTargetAddr, UINT32* pSize); +#endif diff --git a/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.c b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.c new file mode 100644 index 000000000000..c545ab81cde0 --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.c @@ -0,0 +1,50 @@ +/* + * OpenIPC: LZMA for U-Boot's BCL1 container (algorithm 11). NA51089's + * mask ROM has a decoder the loader calls; NA51055's has none, so the + * loader carries its own, Igor Pavlov's public domain LzmaDec as U-Boot + * has it (lib/lzma). The input is an .lzma stream: 5 bytes of properties, + * the unpacked size as a 64-bit word, then the data. + */ +/* OpenIPC: small, in Thumb, to fit the loader's 32 KiB */ +#pragma GCC target("thumb") +#pragma GCC optimize("Os") + +#include "LzmaDec.h" +#include "bl_lzma.h" + +/* lc + lp <= 4: at most 1846 + 768 << 4 probabilities of 16 bits */ +static unsigned char lzma_heap[0x8000] __attribute__((aligned(8))); + +static void *lzma_alloc(void *p, size_t size) +{ + (void)p; + return size <= sizeof(lzma_heap) ? lzma_heap : NULL; +} + +static void lzma_free(void *p, void *address) +{ + (void)p; + (void)address; +} + +int bl_lzma_inflate(unsigned char *in, unsigned int in_size, + unsigned char *out, unsigned int out_size) +{ + ISzAlloc alloc = { lzma_alloc, lzma_free }; + SizeT src_len, dst_len = out_size; + ELzmaStatus status; + unsigned int len; + + if (in_size < LZMA_PROPS_SIZE + 8) + return -1; + len = in[LZMA_PROPS_SIZE] | in[LZMA_PROPS_SIZE + 1] << 8 | + in[LZMA_PROPS_SIZE + 2] << 16 | + (unsigned int)in[LZMA_PROPS_SIZE + 3] << 24; + if (len < dst_len) + dst_len = len; + src_len = in_size - LZMA_PROPS_SIZE - 8; + if (LzmaDecode(out, &dst_len, in + LZMA_PROPS_SIZE + 8, &src_len, in, + LZMA_PROPS_SIZE, LZMA_FINISH_END, &status, &alloc) != SZ_OK) + return -1; + return (int)dst_len; +} diff --git a/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.h b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.h new file mode 100644 index 000000000000..3ba773801442 --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.h @@ -0,0 +1,9 @@ +/* OpenIPC: LZMA for U-Boot's BCL1 container (bl_lzma.c) */ +#ifndef _BL_LZMA_H +#define _BL_LZMA_H + +/* Returns the unpacked length, or -1 */ +int bl_lzma_inflate(unsigned char *in, unsigned int in_size, + unsigned char *out, unsigned int out_size); + +#endif diff --git a/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c new file mode 100755 index 000000000000..47b9ce2136b1 --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c @@ -0,0 +1,146 @@ +/* + Main control function + + This file is implement by user mode + + @file main.c + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ +#include "main.h" +#include "bl_func.h" +#include "Cache.h" +#include "global.h" +#include "fuart.h" +#include "debug.h" + +extern char _loader_exec_compres_start[]; +extern char _loader_exec_compress_load_cpu_addr[]; +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[]; + +extern char _loader_data_start_base[]; +#define _THUMB2 __attribute__((target("thumb"))) +//--------------------------------------------------------------------------- +// Static function +//--------------------------------------------------------------------------- +/* + BL_RunPartOne + + Expend loader if use compress + + @return void +*/ +_THUMB2 static void BL_RunPartOne(void) +{ +#if (_LOADER_COMPRESSED_ == ENABLE) + UINT8 *in_addr = (UINT8 *)(_loader_exec_compress_load_cpu_addr); + UINT8 *out_addr = (UINT8 *)(_loader_exec_compres_start); + UINT32 uiCompressedOutSize; + + // Get decompress size within specific header + uiCompressedOutSize = (((UINT32)*(in_addr + 12)) << 24) + + (((UINT32)*(in_addr + 13)) << 16) + + (((UINT32)*(in_addr + 14)) << 8) + + ((UINT32)*(in_addr + 15)); + + // Decompress loader image + LZ_Uncompress((unsigned char *)(in_addr + LDC_HEADER_SIZE), (unsigned char *)(out_addr), uiCompressedOutSize); + + // Need to clean data cache + CPUInvalidateICacheAll(); + CPUCleanInvalidateDCacheAll(); + debug_msg("\r\nUNZOK!"); +#else +#endif +} + +/* +void BL_PostHandle(void) +{ + UINT32 uiParamCnt; + UINT32 *pParamOffset; + UINT32 *pDramParam; + + pParamOffset = (UINT32*)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[5*4]); + pDramParam = (UINT32*)(*pParamOffset); + for (uiParamCnt=0; uiParamCnt < 7*2; uiParamCnt++) + { + OUTREG32(DDR_PARAM_LEVEL_0_ADDR + uiParamCnt*4, pDramParam[uiParamCnt]); + } + + // Disable IDE2 clock + CLRREG32(0xC0020070, 1<<17); + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); +} +*/ +_THUMB2 UINT32 main(void) +{ + UINT32 uiReturn; + UINT32 load_addr, target_addr, uitron_size; + UINT32 i; + UINT32 *pSrc, *pDst; + // Run part one loader + // If using compressed loader, just decompress the loader image at first! + BL_RunPartOne(); + utl_dram_protect_enable((UINT32)_loader_exec_compres_start, (UINT32)(_loader_data_start_base - _loader_exec_compres_start)); + uiReturn = bl_mainFlow(); + utl_dram_protect_check(); + utl_dram_protect_disable(); + + bl_read_rtos_addr(&load_addr, &target_addr, &uitron_size); + if (load_addr != target_addr) { + uart_putSystemUARTStr("uitron target_addr= "); + PrintDec2Hex(target_addr); + uart_putSystemUARTStr("\r\n"); + uart_putSystemUARTStr("uitron load_addr= "); + PrintDec2Hex(load_addr); + uart_putSystemUARTStr("\r\n"); + uart_putSystemUARTStr("Copy from load to target by loader, this may has longer boot time\r\n"); + CPUflushReadCache(0, 128*1024); + CPUInvalidateICacheAll(); + +#if 1 + // disable MMU + { \ + __asm__ __volatile__( \ + "mrc p15, 0, r0, c1, c0, 0\n\t" \ + "bic r0, r0, #0x5\n\t" \ + "bic r0, r0, #0x1000\n\t" \ + "mcr p15, 0, r0, c1, c0, 0\n\t" \ + : \ + : \ + : "r0" \ + ); \ + } + asm volatile("dsb"); + asm volatile("isb"); + uart_putSystemUARTStr("disable MMU done\r\n"); +#endif + + pSrc = (UINT32*)load_addr; + pDst = (UINT32*)target_addr; + for (i=0; ipagesize = nvt_nand_ids[ui_nand_ids].pagesize; + pIdentify->erasesize= nvt_nand_ids[ui_nand_ids].erasesize; + pIdentify->qe_opt = nvt_nand_ids[ui_nand_ids].qe_opt; + pIdentify->plane_opt= nvt_nand_ids[ui_nand_ids].plane_opt; + nand_ids_found = TRUE; + break; + } + } + return nand_ids_found; +} diff --git a/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c new file mode 100755 index 000000000000..f1e5f15d1715 --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c @@ -0,0 +1,38 @@ +/* + * nand_ids.c + * + * nand id table + * + * Copyright (c) 2018 Novatek, ALL Rights Reserve + */ +#include "main.h" +#include "nor.h" +#include "constant.h" +#include "compiler.h" +#include "fuart.h" + +#define _THUMB2 __attribute__((target("thumb"))) + + +NOR_FLASH_DEV nvt_nor_ids[] = { + // manufactor ID device id capacity id, dual read quad type flash size + SPI_ID_NOR(0xEF, 0x40, 0x18, TRUE, SPI_QUAD_TYPE2, (16<<20)), +}; + +_THUMB2 BOOL nor_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + BOOL nor_ids_found = FALSE; + UINT32 ui_nor_ids; + for (ui_nor_ids = 0; ui_nor_ids < (sizeof(nvt_nor_ids) / sizeof(NOR_FLASH_DEV)); ui_nor_ids++) { + if (uiMfgID == nvt_nor_ids[ui_nor_ids].mfr_id && uiTypeID == nvt_nor_ids[ui_nor_ids].dev_id && uiCapacityID == nvt_nor_ids[ui_nor_ids].capacity_id) { + // For SPI Nor flash only + pIdentify->bDualRead = nvt_nor_ids[ui_nor_ids].bDualRead; + pIdentify->uiQuadReadType = nvt_nor_ids[ui_nor_ids].uiQuadReadType; + pIdentify->uiFlashSize = nvt_nor_ids[ui_nor_ids].uiFlashSize; + nor_ids_found = TRUE; + break; + } + } + + return nor_ids_found; +} diff --git a/board/novatek/na51055/loader/LibExt/Makefile b/board/novatek/na51055/loader/LibExt/Makefile new file mode 100755 index 000000000000..c37cab5becbe --- /dev/null +++ b/board/novatek/na51055/loader/LibExt/Makefile @@ -0,0 +1,62 @@ +include ../MakeCommon/MakeOption.txt + +ifeq "$(shell uname)" "Linux" +MAKEFILE_SEARCH := $(sort $(dir $(shell find . -name 'Makefile'))) +else +MAKEFILE_SEARCH := $(sort $(dir $(shell find . -name \'Makefile\'))) +endif +mk_all := $(filter-out ./, $(MAKEFILE_SEARCH)) + +ifeq "$(ISOLATE_DEP)" "ON" +.PHONY: all $(mk_all) clean rebuild debug release dep + +all: + @make dep + @make debug + @make release +else +.PHONY: all $(mk_all) clean rebuild debug release + +all: rm_log $(mk_all) +endif + +$(mk_all): + @$(MAKE) --directory=$@ $(MAKECMDGOALS) + +rm_log: +ifeq "$(CLEAN_LOG)" "ON" + @-rm -f log*.txt +endif + +PRJ_NAME_ALL = $(shell find -name 'Makefile' -not -path "./Makefile" -print | xargs grep "PRJ_NAME" | sed 's/[[:digit:][:alpha:][:punct:]]*:PRJ_NAME[ ]*=[ ]*//g') +LIB_R = $(addprefix "../ARC/Lib/Release/", $(addsuffix ".a", $(PRJ_NAME_ALL))) +LIB_D = $(addprefix "../ARC/Lib/Debug/", $(addsuffix "_D.a", $(PRJ_NAME_ALL))) + +clean: + @-echo Clean LibExt ... \ + && find ./ -type d -name '*_Data' | xargs rm -rf --no-preserve-root $(LIB_D) $(LIB_R) log*.txt lint*.txt + +ifeq "$(ISOLATE_DEP)" "ON" +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: rm_log $(mk_all) +else +rebuild: rm_log $(mk_all) +endif + +debug: rm_log $(mk_all) + +release: rm_log $(mk_all) + +rm_lint_log: + @-rm -f lint*.txt + +lint: rm_lint_log $(mk_all) + +lintclean: + @-echo Clean LibExt lint data ... \ + && find ./ -type d -name 'CheckData' | xargs rm -rf --no-preserve-root lint*.txt \ No newline at end of file diff --git a/board/novatek/na51055/loader/MakeCommon/InputSource.txt b/board/novatek/na51055/loader/MakeCommon/InputSource.txt new file mode 100755 index 000000000000..631265678903 --- /dev/null +++ b/board/novatek/na51055/loader/MakeCommon/InputSource.txt @@ -0,0 +1,177 @@ +#---------------------------------------------------------------------- +# get the source full path, convert upper case extension to lower case +#---------------------------------------------------------------------- +ifeq "$(shell uname)" "Linux" +SRC := $(addprefix $(shell pwd)/, $(SRC:.C=.c)) +ASM := $(addprefix $(shell pwd)/, $(ASM:.s=.S)) +CPP_SRC := $(addprefix $(shell pwd)/, $(CPP_SRC:.CPP=.cpp)) +else +SRC := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(SRC:.C=.c)) +ASM := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(ASM:.s=.S)) +CPP_SRC := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(CPP_SRC:.CPP=.cpp)) +endif + +#---------------------------------------------------------------------- +# set the basic include directories +#---------------------------------------------------------------------- +# Get working directory +MYPWD := $(shell pwd) +ALG_PATH := $(findstring /Alg/, $(MYPWD)) +APP_PATH := $(findstring /App/, $(MYPWD)) +APPEXT_PATH := $(findstring /AppExt/, $(MYPWD)) +LIB_PATH := $(findstring /Lib/, $(MYPWD)) +LIBEXT_PATH := $(findstring /LibExt/, $(MYPWD)) +DRV_PATH := $(findstring /Drv/, $(MYPWD)) +DRVEXT_PATH := $(findstring /DrvExt/, $(MYPWD)) +COM_PATH := $(findstring /Common/, $(MYPWD)) +UTIL_PATH := $(findstring /Common/Common_src/Utility, $(MYPWD)) +PRJ_PATH := $(shell find ./ -maxdepth 1 -name MakeConfig.txt) + +BASE_INC_DIR := $(filter %../../Include, $(INC_DIR)) +APPEXT_INC_DIR := -I$(BASE_INC_DIR)/AppExt +APP_INC_DIR := -I$(BASE_INC_DIR)/App +LIBEXT_INC_DIR := -I$(BASE_INC_DIR)/LibExt +LIB_INC_DIR := -I$(BASE_INC_DIR)/Lib +DRVEXT_INC_DIR := -I$(BASE_INC_DIR)/DrvExt +DRV_INC_DIR := -I$(BASE_INC_DIR)/Drv +LIBC_INC_DIR := -I$(BASE_INC_DIR)/Common/LibC + +#BASE_INC_ALG_DIR := $(BASE_INC_DIR)/../Alg/Include +#BASE_INC_PROTECT_DIR := $(subst Include,IncludeProtected,$(BASE_INC_DIR)) + +#change replace /Include/ to /IncludeProtected/ +define protected +$(subst ../../Include/,../../IncludeProtected/,$1) +endef + + +ifeq "$(USE_ECOS_KERNEL)" "ON" +#eCos include path like ThirdParty/eCos/Include ThirdParty/live555/Include +ECOS_INC_DIR := $(addprefix -I,$(addsuffix /include, $(shell find $(BASE_INC_DIR)/../ThirdParty/ -maxdepth 1 -mindepth 1 -type d))) +endif + +ifeq "$(shell uname)" "Linux" +INC_DIR := $(addprefix -I, $(sort $(dir $(shell find $(INC_DIR) -name '*.h')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_PROTECT_DIR) -name '*.h')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_ALG_DIR) -name '*.h')))) +else +INC_DIR := $(addprefix -I, $(sort $(dir $(shell find $(INC_DIR) -name \'\*\.h\')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_PROTECT_DIR) -name \'\*\.h\')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_ALG_DIR) -name \'\*\.h\')))) +endif + +# For uITRON (MIPS) platform, we use proprietary standard C library. +# We must filter out proprietary header file if we are in others platform (ARM or eCos...) +# Filter out standard C library header file +# ifeq "$(ARCH)" "ARM" +# INC_DIR := $(filter-out $(LIBC_INC_DIR)/%, $(INC_DIR)) +# endif + +ifeq "$(USE_ECOS_KERNEL)" "ON" + INC_DIR := $(filter-out $(LIBC_INC_DIR)/%, $(INC_DIR)) + INC_DIR += $(ECOS_INC_DIR) +endif + +ifeq "$(INCLUDE_RULE)" "ON" + +#---------------------------------------------------------------------- +# Filter out upper layer's include path +#---------------------------------------------------------------------- + + +# /Common can't access /App or /AppExt or /Lib or /LibExt or /Drv or /DrvExt +# except: /Common/Common_src/Utility can access /Drv +ifneq "$(COM_PATH)" "" +ifneq "$(UTIL_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)% $(DRVEXT_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%) $(call protected,$(DRVEXT_INC_DIR)%),$(INC_DIR)) +else +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)% $(DRVEXT_INC_DIR)% $(DRV_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%) $(call protected,$(DRVEXT_INC_DIR)%) $(call protected,$(DRV_INC_DIR)%),$(INC_DIR)) +endif +endif + +# /Drv can't access /App or /AppExt or /Lib or /LibExt +ifneq "$(DRV_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%),$(INC_DIR)) +endif + +# /DrvExt can't access /App or /AppExt or /Lib or /LibExt +ifneq "$(DRVEXT_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%), $(INC_DIR)) +endif + +# /Lib can't access /App or /AppExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%), $(INC_DIR)) +endif + +# /LibExt can't access /App or /AppExt +ifneq "$(LIBEXT_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%), $(INC_DIR)) +endif + +#---------------------------------------------------------------------- +# Filter out under layer's include path +#---------------------------------------------------------------------- + +# /App can't access /Drv +#ifneq "$(APP_PATH)" "" +#INC_DIR := $(filter-out $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +# /App can't access /DrvExt or /LibExt +ifneq "$(APP_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)% $(LIBEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /AppExt can't access /Drv +#ifneq "$(APPEXT_PATH)" "" +#INC_DIR := $(filter-out $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +# /Lib can't access /DrvExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /Prj can't access /Drv or /DrvExt +#ifneq "$(PRJ_PATH)" "" +#INC_DIR := $(filter-out $(DRVEXT_INC_DIR)% $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +ifneq "$(UI_STYLE)" "" +ifeq ($(filter $(UI_STYLE), $(UI_STYLE_ALL)),) +$(error add your style into $$UI_STYLE_ALL in MakeConfig.txt) +else +PRJ_FILT_OUT := $(filter-out $(UI_STYLE), $(UI_STYLE_ALL)) +endif +PRJ_FILT_OUT_DIR := $(addsuffix %,$(addprefix -I./SrcCode/UIWnd/, $(subst UI_STYLE_,,$(PRJ_FILT_OUT)))) +#INC_DIR := $(shell echo $(INC_DIR)|tr a-z A-Z) +INC_DIR := $(filter-out $(PRJ_FILT_OUT_DIR) , $(INC_DIR)) +endif + +#---------------------------------------------------------------------- +# Filter out external layer's include path +#---------------------------------------------------------------------- + +# /Drv can't access /DrvExt +ifneq "$(DRV_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /Lib can't access /LibExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(LIBEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /App can't access /AppExt +ifneq "$(APP_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)%, $(INC_DIR)) +endif + +endif \ No newline at end of file diff --git a/board/novatek/na51055/loader/MakeCommon/MakeCommon.txt b/board/novatek/na51055/loader/MakeCommon/MakeCommon.txt new file mode 100755 index 000000000000..95aeec679e6d --- /dev/null +++ b/board/novatek/na51055/loader/MakeCommon/MakeCommon.txt @@ -0,0 +1,632 @@ +#---------------------------------------------------------------------- +# Get the source full path, include directories +#---------------------------------------------------------------------- +# query SRC, ASM, INC_DIR +include $(MAKE_COMMON_DIR)/InputSource.txt + +#---------------------------------------------------------------------- +# set the basic ASM flags +# PLATFORM_AFLAGS := -march=armv7-a -mcpu=cortex-a9 -mabi=aapcs -msoft-float +# -mfloat-abi=softfp <==> -mfloat-abi=hard +#---------------------------------------------------------------------- +ifeq "$(FPU)" "hard" +PLATFORM_AFLAGS := -mcpu=$(CPU) -mfpu=neon -mfloat-abi=$(FPU) +else +PLATFORM_AFLAGS := -mcpu=$(CPU) -mfloat-abi=$(FPU) +endif + + + +#---------------------------------------------------------------------- +# set the basic C flags +# Reference +# http://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/ +# http://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/Option-Summary.html#Option-Summary +#---------------------------------------------------------------------- +#---------------------------------------------------------------------- +# Overall Options +#---------------------------------------------------------------------- +# -c : Compile the source files, but do not link +# -pipe : Use pipes rather than temporary files for communication between the various stages of compilation +PLATFORM_CFLAGS := -c -pipe + +#---------------------------------------------------------------------- +# Machine Dependent Options +#---------------------------------------------------------------------- +# -march=24kec : Generate code that will run on MIPS 24KEc +# -mtune=24kec : Optimize for MIPS 24KEc +# -mdsp : Use revision 1 of the MIPS DSP ASE +# -EL : Generate little-endian code +# -msoft-float : Do not use floating-point coprocessor instructions +# -marm : Tell compiler do not build c code as thumb2 instruction +#---------------------------------------------------------------------- +ifeq "$(USE_NEON)" "on" +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=softfp -mfpu=neon-fp-armv8 -ftree-vectorize +else +ifeq "$(FPU)" "hard" +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=$(FPU) -mfpu=neon -ftree-vectorize +else +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=$(FPU) +endif +endif +# PLATFORM_CFLAGS += -mtune=$(CPU) -march=armv7-a -marm -mhard-float -mfpu=neon-vfpv4 -mno-thumb-interwork -mno-sched-prolog +# PLATFORM_CFLAGS += -mtune=$(CPU) -march=armv7-a -marm -msoft-float -mno-thumb-interwork -mno-sched-prolog + +#---------------------------------------------------------------------- +# Warning Options +#---------------------------------------------------------------------- +# -Wall : This enables all the warnings about constructions that some users consider questionable, +# and that are easy to avoid (or modify to prevent the warning), even in conjunction with macros. +# NOTE: -Wall turns on the following warning flags: +# -Waddress +# -Warray-bounds (only with -O2) +# -Wc++11-compat +# -Wchar-subscripts +# -Wenum-compare (in C/ObjC; this is on by default in C++) +# -Wimplicit-int (C and Objective-C only) +# -Wimplicit-function-declaration (C and Objective-C only) +# -Wcomment +# -Wformat +# -Wmain (only for C/ObjC and unless -ffreestanding) +# -Wmaybe-uninitialized +# -Wmissing-braces (only for C/ObjC) +# -Wnonnull +# -Wparentheses +# -Wpointer-sign +# -Wreorder +# -Wreturn-type +# -Wsequence-point +# -Wsign-compare (only in C++) +# -Wstrict-aliasing +# -Wstrict-overflow=1 +# -Wswitch +# -Wtrigraphs +# -Wuninitialized +# -Wunknown-pragmas +# -Wunused-function +# -Wunused-label +# -Wunused-value +# -Wunused-variable +# -Wvolatile-register-var +# -Wundef : Warn if an undefined identifier is evaluated in an `#if' directive +# -Wsign-compare : Warn when a comparison between signed and unsigned values could produce an incorrect result when the signed value is converted to unsigned +# -Wno-missing-braces : Trun off "Warn if an aggregate or union initializer is not fully bracketed". For XXX = {0}; statement. +# -Wstrict-prototypes : Warn if a function is declared or defined without specifying the argument types +# -Wimplicit-function-declaration : Warn when a function is used before being declared +# -Wmissing-prototypes : Warn about global funcs without prototypes +# -Wmissing-declarations: Warn about global funcs without previous declarations +# -Werror : Warnning as error +#---------------------------------------------------------------------- +PLATFORM_CFLAGS += -Wall -Wundef -Wsign-compare -Wno-missing-braces -Wstrict-prototypes -Wno-unused-const-variable -Wno-misleading-indentation +ifeq "$(OUTPUT_FILE)" "BIN" +else +ifeq "$(INCLUDE_RULE)" "ON" +# PLATFORM_CFLAGS += -Werror=implicit-function-declaration -Werror=missing-prototypes -Werror=missing-declarations + PLATFORM_CFLAGS += -Wimplicit-function-declaration -Wmissing-prototypes -Wmissing-declarations +endif +endif + +ifeq "$(shell uname)" "Linux" +PLATFORM_CFLAGS += -Werror +endif + +#---------------------------------------------------------------------- +# C Language Options +#---------------------------------------------------------------------- +# -fno-builtin : Don't recognize built-in functions that do not begin with `__builtin_' as prefix +# -ffreestanding: Assert that compilation takes place in a freestanding environment +#---------------------------------------------------------------------- +# Code Generation Options +#---------------------------------------------------------------------- +# -fno-common : The compiler should place uninitialized global variables in the data section of the object file, rather than generating them as common blocks +# -fshort-wchar : Override the underlying type for `wchar_t' to be `short unsigned int' instead of the default for the target. +#---------------------------------------------------------------------- +# Optimization Options +#---------------------------------------------------------------------- +# -fno-strict-aliasing : Do not warn about code that breaks strict aliasing rules +# -fno-optimize-sibling-calls : Don't optimize sibling and tail recursive calls +# -fno-omit-frame-pointer : Keep the frame pointer in a register for functions that don't need one +#---------------------------------------------------------------------- +PLATFORM_CFLAGS += -fno-builtin -ffreestanding -fno-common -fshort-enums -fshort-wchar -fno-strict-aliasing -fno-optimize-sibling-calls -fno-omit-frame-pointer + +# C Language Options for eCos system +ifeq "$(USE_ECOS_KERNEL)" "ON" + PLATFORM_CFLAGS += -D__ECOS +else + PLATFORM_CFLAGS += -nostdinc -D__UITRON +# For make dep + GCCFLAGS +=-D__UITRON +endif + +# Remove -Otime (There is no such option in GCC, GCC default is optimize for time) +# Replace -OSpace (-Os in GCC) +CFLAGS_D := $(filter-out -Otime, $(CFLAGS_D)) +CFLAGS_D := $(CFLAGS_D:-Ospace=-Os) +CFLAGS_R := $(filter-out -Otime, $(CFLAGS_R)) +CFLAGS_R := $(CFLAGS_R:-Ospace=-Os) + +# Slove sub-folder cannot include parent folder header file +INC_DIR += -I$(CURDIR) + +# For Debug target +CFLAGS_D += $(INC_DIR) -g -ggdb -O0 $(PLATFORM_CFLAGS) +ASMFLAGS_D += -g $(INC_DIR) $(PLATFORM_AFLAGS) -D__ASSEMBLY__ + +# For Release target (use -Os instead of -O2, because loader is size dominant) +CFLAGS_R += $(INC_DIR) -Os $(PLATFORM_CFLAGS) +ASMFLAGS_R += $(INC_DIR) $(PLATFORM_AFLAGS) -D__ASSEMBLY__ + +# Generate debug symbol in release target +ifeq "$(RELEASE_SYMBOL)" "ON" + CFLAGS_R += -g -ggdb + ASMFLAGS_R += -L -g +endif + +# Generate debug callback of entry and exit to functions +ifeq "$(INSTRUMENT_FUNCTION)" "ON" + CFLAGS_R += -finstrument-functions -finstrument-functions-exclude-file-list=Common_src/LibC,Common_src/Kernel,Common_src/Debug,Common_src/OS,Include/Common/LibC,Include/Common/Kernel,Include/Common/Debug,Include/Common/OS,Drv_src/Driver,Include/Drv/Driver + CFLAGS_D += -finstrument-functions -finstrument-functions-exclude-file-list=Common_src/LibC,Common_src/Kernel,Common_src/Debug,Common_src/OS,Include/Common/LibC,Include/Common/Kernel,Include/Common/Debug,Include/Common/OS,Drv_src/Driver,Include/Drv/Driver + CFLAGS_R += -D_INSTRUMENT_FUNCTION_=1 + CFLAGS_D += -D_INSTRUMENT_FUNCTION_=1 +else + CFLAGS_R += -D_INSTRUMENT_FUNCTION_=0 + CFLAGS_D += -D_INSTRUMENT_FUNCTION_=0 +endif + +#---------------------------------------------------------------------- +# Generate one ELF section for each function +# Only apply to release target +# Note: -fdata-sections will generate larger code size +#---------------------------------------------------------------------- +ifeq "$(SECTION_BY_FUNC)" "ON" +# CFLAGS_R += -ffunction-sections -fdata-sections + CFLAGS_R += -ffunction-sections +endif + +#---------------------------------------------------------------------- +# Definition for source code check build debug or release +#---------------------------------------------------------------------- +CFLAGS_R += -DNDEBUG +CFLAGS_D += -D_DEBUG + +#---------------------------------------------------------------------- +# FPGA notification for drivers +#---------------------------------------------------------------------- +ifeq "$(EMULATION)" "ON" + ifeq "$(FPGA_EMULATION)" "ON" + CFLAGS_R += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + CFLAGS_D += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + GCCFLAGS += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + else + CFLAGS_R += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + CFLAGS_D += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + GCCFLAGS += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + endif +else + CFLAGS_R += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 + CFLAGS_D += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 + GCCFLAGS += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 +endif + +#---------------------------------------------------------------------- +# PM demo based on customized building way +#---------------------------------------------------------------------- +ifeq "$(PM_DEMO)" "ON" + CFLAGS_R += -D_PM_DEMO_=1 + CFLAGS_D += -D_PM_DEMO_=1 +else + CFLAGS_R += -D_PM_DEMO_=0 + CFLAGS_D += -D_PM_DEMO_=0 +endif + +#---------------------------------------------------------------------- +# GIC usage ON/OFF +#---------------------------------------------------------------------- +ifeq "$(ARM_GIC_400)" "ON" + CFLAGS_R += -D_ARM_GIC_USAGE_=1 + CFLAGS_D += -D_ARM_GIC_USAGE_=1 + ASMFLAGS_R += -D_ARM_GIC_USAGE_=1 + ASMFLAGS_D += -D_ARM_GIC_USAGE_=1 +else + CFLAGS_R += -D_ARM_GIC_USAGE_=0 + CFLAGS_D += -D_ARM_GIC_USAGE_=0 + ASMFLAGS_R += -D_ARM_GIC_USAGE_=0 + ASMFLAGS_D += -D_ARM_GIC_USAGE_=0 +endif + +#---------------------------------------------------------------------- +# Architecture definition +#---------------------------------------------------------------------- +CFLAGS_R += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 +CFLAGS_D += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 +GCCFLAGS += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 + +ifeq "$(ARCH)" "ARM" + CFLAGS_R += -D_ARCH_=_ARCH_ARM_ + CFLAGS_D += -D_ARCH_=_ARCH_ARM_ + GCCFLAGS += -D_ARCH_=_ARCH_ARM_ +else ifeq "$(ARCH)" "MIPS" + CFLAGS_R += -D_ARCH_=_ARCH_MIPS_ + CFLAGS_D += -D_ARCH_=_ARCH_MIPS_ + GCCFLAGS += -D_ARCH_=_ARCH_MIPS_ +endif + +ifeq "$(FPU)" "hard" +ASMFLAGS_D += -D_NEON_ON_=1 +ASMFLAGS_R += -D_NEON_ON_=1 +else +ASMFLAGS_D += -D_NEON_ON_=0 +ASMFLAGS_R += -D_NEON_ON_=0 +endif + +#---------------------------------------------------------------------- +# Definition from environment +#---------------------------------------------------------------------- +ifeq "$(NMAKE_DEF)" "" +CFLAGS_R += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +CFLAGS_D += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +else +CFLAGS_R += $(NMAKE_DEF) +CFLAGS_D += $(NMAKE_DEF) +endif +ifeq "$(NMAKE_DEF_ASM)" "" +ASMFLAGS_R += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +ASMFLAGS_D += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +else +ASMFLAGS_R += $(NMAKE_DEF_ASM) +ASMFLAGS_D += $(NMAKE_DEF_ASM) +endif +#---------------------------------------------------------------------- +# Set image base directory according to kernel type +# eCos : /ARC +# uITRON : /ARC_eCos +#---------------------------------------------------------------------- +ifeq "$(USE_ECOS_KERNEL)" "ON" + ifeq "$(OUTPUT_FILE)" "LIB" + # This is for library, project's image base directory is $(PRJ_NAME)_Data + # IMG_BASE_DIR looks like ../../ARC/Common (There is backslash succeeding to /ARC) + IMG_BASE_DIR := $(subst /ARC/,/ARC_eCos/,$(IMG_BASE_DIR)) + endif + ifeq "$(OUTPUT_FILE)" "BIN" + # This is for project, library doesn't have this variable + # ARC_BASE_DIR looks like ../../ARC (There is No backslash succeeding to /ARC) + ARC_BASE_DIR := $(subst /ARC,/ARC_eCos,$(ARC_BASE_DIR)) + endif + KERNEL_STR := eCos +else + KERNEL_STR := uITRON +endif + +#---------------------------------------------------------------------- +# Set branched project name +#---------------------------------------------------------------------- +ifneq "$(_BRANCH_PROJECT_)" "" + CFLAGS_R += -D_PROJECT_CODE_=$(_BRANCH_PROJECT_) + CFLAGS_D += -D_PROJECT_CODE_=$(_BRANCH_PROJECT_) +endif + +#---------------------------------------------------------------------- +# Set the directory for debug/release objects and images here +#---------------------------------------------------------------------- +OBJ_DEBUG = $(PRJ_NAME)_Data/Debug/ObjectCode +OBJ_RELEASE = $(PRJ_NAME)_Data/Release/ObjectCode +IMG_DEBUG = $(IMG_BASE_DIR)/Debug +IMG_RELEASE = $(IMG_BASE_DIR)/Release + + +#---------------------------------------------------------------------- +# Filter the GCC Command Options for debug/release mode +#---------------------------------------------------------------------- +FILTER_GCC_D = $(foreach v, $(CFLAGS_D), $(if $(findstring -D, $(v)), , $(v))) +GCC_OPT_D = $(filter-out $(INC_DIR), $(FILTER_GCC_D)) +FILTER_GCC_R = $(foreach v, $(CFLAGS_R), $(if $(findstring -D, $(v)), , $(v))) +GCC_OPT_R = $(filter-out $(INC_DIR), $(FILTER_GCC_R)) + + +#---------------------------------------------------------------------- +# Set the make outputs +#---------------------------------------------------------------------- +SRC_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(SRC:.c=.o))) +ASM_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(ASM:.S=.o))) +CPP_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(CPP_SRC:.cpp=.o))) +ALL_OBJ_D := $(ASM_OBJ_D) $(SRC_OBJ_D) $(CPP_OBJ_D) +DEPFILE_D := $(subst .o,.d,$(ALL_OBJ_D)) + +SRC_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(SRC:.c=.o))) +ASM_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(ASM:.S=.o))) +CPP_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(CPP_SRC:.cpp=.o))) +ALL_OBJ_R := $(ASM_OBJ_R) $(SRC_OBJ_R) $(CPP_OBJ_R) +DEPFILE_R := $(subst .o,.d,$(ALL_OBJ_R)) + +ifeq "$(ISOLATE_DEP)" "ON" + ALL_DEP := $(DEPFILE_D) $(DEPFILE_R) +endif + +LINT_ROOTDIR = $(PRJ_NAME)_Lint +LINT_DIR = $(PRJ_NAME)_Lint/LintData +LINT_FILE := $(addprefix $(LINT_DIR)/, $(notdir $(SRC:.c=.lob))) + +#---------------------------------------------------------------------- +# For dependency +#---------------------------------------------------------------------- +GCCFLAGS += $(INC_DIR) -c -w + +#---------------------------------------------------------------------- +# For coding rule +#---------------------------------------------------------------------- +PCLINTFLAGS = $(PCLINT_PARAMETER) $(C_DEFINE_EXT) $(INC_DIR) -i$(MAKE_COMMON_DIR)/LintRule std.lnt options.lnt $$(lintopt_file) + +#---------------------------------------------------------------------- +# define host environment is linux if we build on linux server +#---------------------------------------------------------------------- +ifeq ($(OS),Linux) +CFLAGS_R += -D_HOST_ENV_LINUX_ +CFLAGS_D += -D_HOST_ENV_LINUX_ +GCCFLAGS += -D_HOST_ENV_LINUX_ +endif + +#---------------------------------------------------------------------- +# CPP FLAGS derived from CFLAGS_R / CFLAGS_D +#---------------------------------------------------------------------- +CPPFLAGS_R = $(filter-out -Wstrict-prototypes -Wimplicit-function-declaration -Wmissing-prototypes, $(CFLAGS_R)) +CPPFLAGS_D = $(filter-out -Wstrict-prototypes -Wimplicit-function-declaration -Wmissing-prototypes, $(CFLAGS_D)) + +#---------------------------------------------------------------------- +# Set the make targets +#---------------------------------------------------------------------- +build_all: rm_log build_D build_R + +make_debug_begin: + @-echo \ + && echo Checking $(KERNEL_STR) - $(basename $(notdir $(IMAGE_D))) debug target ... \ + && mkdir -p $(IMG_DEBUG) $(OBJ_DEBUG) + +make_release_begin: + @-echo \ + && echo Checking $(KERNEL_STR) - $(basename $(notdir $(IMAGE_R))) release target ... \ + && mkdir -p $(IMG_RELEASE) $(OBJ_RELEASE) + +make_dep_begin: + @-echo Checking $(basename $(notdir $(IMAGE_R))) dependency ... \ + && mkdir -p $(OBJ_DEBUG) $(OBJ_RELEASE) + +make_lint_begin: + @-echo Checking \"$(basename $(notdir $(IMAGE_R)))\" with coding rules ... \ + && mkdir -p $(LINT_DIR) + +make_option_begin: + @-echo [GCC Command Options - Release] + @-echo $(GCC_OPT_R) + @-echo + @-echo [GCC Command Options - Debug ] + @-echo $(GCC_OPT_D) + +#---------------------------------------------------------------------- +# Compile rule functions +#---------------------------------------------------------------------- +BUILD_DATE = 20`date +'%y%m%d'` +ifeq "$(ISOLATE_DEP)" "ON" + + # $(call compile_rule,object,source,cflags) + define compile_rule + $1: $2 + @echo Compiling $(notdir $2)\ + && $(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_asm,object,source,asmflags) + define compile_rule_asm + $1: $2 + @echo Compiling $(notdir $2) \ + && $(CC) $(PLATFORM_AFLAGS) -c $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_cpp,object,source,cflags) + define compile_rule_cpp + $1: $2 + @echo Compiling $(notdir $2) \ + && $(CXX) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + +else + + # $(call compile_rule,object,source,cflags) + define compile_rule + $1: $2 + @-$(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_asm,object,source,asmflags) + define compile_rule_asm + $1: $2 + @-$(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_cpp,object,source,cflags) + define compile_rule_cpp + $1: $2 + @-$(CXX) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CXX) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + +endif + +# $(call get_obj,obj_dir,source) +get_obj = $(addprefix $1/, $(subst .c,.o,$(notdir $2))) + +# $(call get_obj_asm,obj_dir,source) +get_obj_asm = $(addprefix $1/, $(subst .S,.o,$(notdir $2))) + +# $(call get_obj,obj_dir,source) +get_obj_cpp = $(addprefix $1/, $(subst .cpp,.o,$(notdir $2))) + +# $(call compile_all,obj_dir,cflags) +define compile_all +$(foreach i, $(SRC), \ + $(call compile_rule,$(call get_obj,$1,$i),$i,$2)) +endef + +# $(call compile_all_asm,obj_dir,asmflags) +define compile_all_asm +$(foreach i, $(ASM), \ + $(call compile_rule_asm,$(call get_obj_asm,$1,$i),$i,$2)) +endef + +# $(call compile_all_cpp,obj_dir,cflags) +define compile_all_cpp +$(foreach i, $(CPP_SRC), \ + $(call compile_rule_cpp,$(call get_obj_cpp,$1,$i),$i,$2)) +endef + +#----------------------------------------------------------------- +# Dependency rule functions +#----------------------------------------------------------------- +# $(call depend_rule,depend,source) +define depend_rule +$1: $2 + @echo Depending $(notdir $2) \ + && $(GCC) -MM -MF $1 -MP -MT $(basename $1).o $(GCCFLAGS) $2 \ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) + +endef + +define depend_rule_asm +$1: $2 + @echo Depending $(notdir $2) \ + && $(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) \ + && rm -f $(basename $1).o + +endef + +define depend_rule_cpp +$1: $2 + @echo Depending $(notdir $2) \ + && $(CXX) -MM -MF $1 -MP -MT $(basename $1).o $(GCCFLAGS) $2\ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) + +endef + +# $(call get_dep,dep_dir,source) +get_dep = $(addprefix $1/, $(subst .c,.d,$(notdir $2))) + +# $(call get_dep_asm,dep_dir,source) +get_dep_asm = $(addprefix $1/, $(subst .S,.d,$(notdir $2))) + +# $(call get_dep_cpp,dep_dir,source) +get_dep_cpp = $(addprefix $1/, $(subst .cpp,.d,$(notdir $2))) + +define depend_all +$(foreach i, $(SRC), \ + $(call depend_rule,$(call get_dep,$1,$i),$i)) +endef + +# $(call dep_all_asm,dep_dir) +define depend_all_asm +$(foreach i, $(ASM), \ + $(call depend_rule_asm,$(call get_dep_asm,$1,$i),$i)) +endef + +define depend_all_cpp +$(foreach i, $(CPP_SRC), \ + $(call depend_rule_cpp,$(call get_dep_cpp,$1,$i),$i)) +endef + +#---------------------------------------------------------------------- +# LINT rule functions +#---------------------------------------------------------------------- +# $(call get_lint,lint_dir,source) +get_lint = $(addprefix $1/, $(subst .c,.lob,$(notdir $2))) + +# $(call lint_rule,output,source) +define lint_rule +$1: $2 + @-echo Review $(notdir $2) \ + && $(LT) $(PCLINTFLAGS) -u -zero -oo[$1] $2 >> $$(lint_file) + +endef + +# && $(LT) $(PCLINTFLAGS) $2 >> $$(lint_file) + +define lint_all +$1: +$(foreach i, $(SRC), \ + $(call lint_rule,$(call get_lint,$1,$i),$i)) + @-echo Review \(Internal Relation\) \ + && $(LT) $(PCLINTFLAGS) $(LINT_DIR)/"*.lob" >> $$(lint_file) + -rm -rf --no-preserve-root $(LINT_ROOTDIR) + +endef + +#---------------------------------------------------------------------- +# Goals +#---------------------------------------------------------------------- +ifeq "$(ISOLATE_DEP)" "ON" + + ifeq "$(MAKECMDGOALS)" "dep" + $(eval $(call depend_all,$(OBJ_RELEASE))) + $(eval $(call depend_all_asm,$(OBJ_RELEASE))) + $(eval $(call depend_all_cpp,$(OBJ_RELEASE))) + $(eval $(call depend_all,$(OBJ_DEBUG))) + $(eval $(call depend_all_asm,$(OBJ_DEBUG))) + $(eval $(call depend_all_cpp,$(OBJ_DEBUG))) + endif + + ifeq "$(MAKECMDGOALS)" "" + .DEFAULT_GOAL := all + endif + +else + + ifeq "$(MAKECMDGOALS)" "" + -include $(DEPFILE_D) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) + endif + + ifeq "$(MAKECMDGOALS)" "rebuild" + -include $(DEPFILE_D) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) + endif + +endif + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),debug build_pipe_D)) + -include $(DEPFILE_D) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) +endif + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),release build_pipe_R)) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) +endif + +ifeq "$(MAKECMDGOALS)" "lint" + $(eval $(call lint_all,$(LINT_DIR))) +endif diff --git a/board/novatek/na51055/loader/MakeCommon/MakeOption.txt b/board/novatek/na51055/loader/MakeCommon/MakeOption.txt new file mode 100755 index 000000000000..e1127c97d1cc --- /dev/null +++ b/board/novatek/na51055/loader/MakeCommon/MakeOption.txt @@ -0,0 +1,280 @@ +ifeq "$(OPTION_LOADED)" "" + +#---------------------------------------------------------------------- +# Set option file loaded +#---------------------------------------------------------------------- +export OPTION_LOADED := TRUE + +#---------------------------------------------------------------------- +# Set the target CPU architecture +# +# ARM : ARM CPU +# MIPS : MIPS CPU (24KEc) +#---------------------------------------------------------------------- +export ARCH := ARM +#export ARCH := MIPS + +#---------------------------------------------------------------------- +# Set the toolchain +# +# ARM : ARM ADS, RealView +# GNU : GNU C, ASM and linker +#---------------------------------------------------------------------- +#export TOOLCHAIN := ARM +export TOOLCHAIN := GNU + +#---------------------------------------------------------------------- +# Set the floating point +# +# SW/HW : soft or hard float point unit +#---------------------------------------------------------------------- +#export FPU := hard +export FPU := soft + +#---------------------------------------------------------------------- +# Set the CPU type +# +# cortex-a9 or a53 +#---------------------------------------------------------------------- +export CPU := cortex-a9 +#export CPU := cortex-a53 + + +#---------------------------------------------------------------------- +# Set branched project code +# +# The project code must be 4 characters, please refer to +# http://mynvt.novatek.com.tw/deptsites/IM/Shared%20Documents/VersionControl.doc +# for more detailed information. +# Leaves this variable empty if not branched yet. +#---------------------------------------------------------------------- +export _BRANCH_PROJECT_ := + +#---------------------------------------------------------------------- +# PClint parameters +#---------------------------------------------------------------------- +export PCLINT_PARAMETER := -b -v + +#---------------------------------------------------------------------- +# Set log file option +# +# ON : Save warning/error message to log files (Win32 Default) +# OFF : Just output warning/error message to stdout (Linux Default) +#---------------------------------------------------------------------- +ifeq "$(shell uname)" "Linux" +export LOG_ERR := OFF +else +export LOG_ERR := ON +endif + +#---------------------------------------------------------------------- +# Set clean log file option +# +# ON : Clean log files before make +# OFF : Don't clean log files before make +# (You should execute "make clean" to clean the log files) +#---------------------------------------------------------------------- +export CLEAN_LOG := ON +#export CLEAN_LOG := OFF + +#---------------------------------------------------------------------- +# Keep going when encounter error or not +# +# ON : Make will keep going when encounter error +# OFF : Make will stop when encounter error +#---------------------------------------------------------------------- +#export KEEP_GOING := ON +export KEEP_GOING := OFF + +#---------------------------------------------------------------------- +# Isolate creating dependency files process +# +# ON : You have to run "make dep" to create dependency files +# OFF : dependency file will be created when making the file +#---------------------------------------------------------------------- +export ISOLATE_DEP := ON +#export ISOLATE_DEP := OFF + +#---------------------------------------------------------------------- +# Generate debug symbol in release target +# Release target won't generate debug symbol by default, if you want to +# generate debug symbol in release target, please turn on this option +# +# ON : Generate debug symbol in release target +# OFF : Don't generate debug symbol in release target (default value) +#---------------------------------------------------------------------- +#export RELEASE_SYMBOL := ON +export RELEASE_SYMBOL := OFF + +#---------------------------------------------------------------------- +# Generate debug callback of entry and exit to functions +# Only support on MIPS (This is GCC Extension) +# Reference: http://blog.linux.org.tw/~jserv/archives/001870.html +# +# ON : Generate debug callback +# OFF : Don't generate debug callback (default value) +#---------------------------------------------------------------------- +#export INSTRUMENT_FUNCTION := ON +export INSTRUMENT_FUNCTION := OFF + +#---------------------------------------------------------------------- +# Generate one ELF section for each function +# Compiler will generate one ELF section for one .c file by default. +# If the .c file contains lots of function that are unused, turn on +# this function can reduce code size. +# (Linker will remove unused section by default) +# Valid only in release target +# +# ON : One ELF section for each function +# OFF : One ELF section for each .c file (default value of ADS/GNU C compiler) +#---------------------------------------------------------------------- +export SECTION_BY_FUNC := ON +#export SECTION_BY_FUNC := OFF + +#---------------------------------------------------------------------- +# Copy bin file to storage after bin file is created +# You have to set an environment variable named "NVT_STG_PATH" (without +# quote) to work with this function. +# Example: set "NVT_STG_PATH" to "H:/" (without quote). +# +# ON : Copy bin file to storage after bin file is created +# OFF : Don't copy bin file to storage after bin file is created +#---------------------------------------------------------------------- +export COPY_BIN_2_STG := ON +#export COPY_BIN_2_STG := OFF + +#---------------------------------------------------------------------- +# Select emulation or design-in (Release code) environment +# +# ON : Emulation environment +# OFF : Design-in environment +#---------------------------------------------------------------------- +#export EMULATION := ON +export EMULATION := OFF + +#---------------------------------------------------------------------- +# Select FPGA or Realchip platform for emulation. +# Valid only when EMULATION is ON +# +# ON : FPGA platform +# OFF : Realchip platform +#---------------------------------------------------------------------- +export FPGA_EMULATION := ON +#export FPGA_EMULATION := OFF + +#---------------------------------------------------------------------- +# Set PLL OSC frequency for FPGA EMULATION +# Valid only when FPGA_EMULATION is ON +# +# For example, you should set it to 27000000 if your FPGA is connected +# with a 27 MHz OSC. +#---------------------------------------------------------------------- +export FPGA_PLL_OSC := 24000000 + +#---------------------------------------------------------------------- +# Set INCLUDE RULE +# +# ON : Enable include rule checking of platform +# OFF : Disable include rule checking of platform +#---------------------------------------------------------------------- +export INCLUDE_RULE := ON +#export INCLUDE_RULE := OFF + +#---------------------------------------------------------------------- +# Use eCos kernel or uITRON kernel +# +# ON : Use eCos kernel and light weight uITRON kernel compatible wrapper +# OFF : Use light weight uITRON kernel +#---------------------------------------------------------------------- +#export USE_ECOS_KERNEL := ON +export USE_ECOS_KERNEL := OFF + +#---------------------------------------------------------------------- +# PM demo based on customized building way +# +# ON : compile rule depends on _PM_DEMO_ that is informal way. +# OFF : formal way to build code +#---------------------------------------------------------------------- +#export PM_DEMO := ON +export PM_DEMO := OFF + +#---------------------------------------------------------------------- +# Set the dump encrypt binary tool +# +# ARCH := ARM 'Use ARMv4 as target +# ARCH := MIPS 'Use MIPS24Ke as target +#---------------------------------------------------------------------- +export ENCRYPT_DUMP := ON +#export ENCRYPT_DUMP := OFF + +#---------------------------------------------------------------------- +# Use ARM GIC as interrupt controller +# +# ON : Use GIC +# OFF : Use Lagacy interrupt as interrupt controller +#---------------------------------------------------------------------- +export ARM_GIC_400 := ON +#export ARM_GIC_400 := OFF + +#---------------------------------------------------------------------- +# Set the parameters of GNU toolchain +#---------------------------------------------------------------------- +ifeq "$(TOOLCHAIN)" "GNU" +ifeq "$(shell uname)" "Linux" + #CROSS_COMPILE := /opt/arm/gcc-linaro-arm-none-eabi-4.9-2014.09_linux/bin/arm-none-eabi- + CROSS_COMPILE := /opt/ivot/gcc-linaro-6.4.1-2018.05-x86_64_arm-eabi/bin/arm-eabi- + TOOLS_DIR = ../../Tools/Bin + TOOLS_SUFFIX = +else + CROSS_COMPILE := arm-eabi- + TOOLS_DIR = ../../Tools/Bin + TOOLS_SUFFIX = .exe +endif + export CC = $(CROSS_COMPILE)gcc + export AS = $(CROSS_COMPILE)as + export LD = $(CROSS_COMPILE)ld + export AR = $(CROSS_COMPILE)ar + export OBJDUMP = $(CROSS_COMPILE)objdump + export FE = $(CROSS_COMPILE)objcopy + export NM = $(CROSS_COMPILE)nm + export LT = "C:/lint/lint-nt.exe" + export GCC = $(CROSS_COMPILE)gcc + export CXX = $(CROSS_COMPILE)g++ + export EBIN = $(TOOLS_DIR)/encrypt_bin$(TOOLS_SUFFIX) + export BFC = $(TOOLS_DIR)/bfc$(TOOLS_SUFFIX) + export LDNVT = $(TOOLS_DIR)/nvt-ld-op$(TOOLS_SUFFIX) + export EBIN = $(TOOLS_DIR)/encrypt_boot_dump$(TOOLS_SUFFIX) + export CFGRAM = $(TOOLS_DIR)/Configram520$(TOOLS_SUFFIX) + export ARMINC_DIR := +endif + + +#---------------------------------------------------------------------- +# Set make flags +# +# Note: Don't modify this if you didn't add new option +#---------------------------------------------------------------------- +# Slient mode +MAKEFLAGS := s + +# Keep going or not +ifeq "$(KEEP_GOING)" "ON" + MAKEFLAGS := $(MAKEFLAGS)k +endif + +#---------------------------------------------------------------------- +# OS Type and Number of CPUs +#---------------------------------------------------------------------- +NPROCS=1 +export OS:=$(shell uname -s) + +ifeq ($(OS),Linux) + NPROCS:=$(shell grep -c ^processor /proc/cpuinfo) +endif +ifeq ($(findstring CYGWIN_NT,$(OS)),CYGWIN_NT) + NPROCS:=$(NUMBER_OF_PROCESSORS) +endif + +export JOB_FLAGS:= -j$(NPROCS) + +endif diff --git a/board/novatek/na51055/loader/MakeCommon/Makefile b/board/novatek/na51055/loader/MakeCommon/Makefile new file mode 100755 index 000000000000..83ea369cfc1a --- /dev/null +++ b/board/novatek/na51055/loader/MakeCommon/Makefile @@ -0,0 +1,126 @@ +include MakeOption.txt + +module_Common := $(dir $(wildcard ../Common/Makefile)) +module_Drv := $(dir $(wildcard ../Drv/Makefile)) +module_DrvExt := $(dir $(wildcard ../DrvExt/Makefile)) +module_Lib := $(dir $(wildcard ../Lib/Makefile)) +module_LibExt := $(dir $(wildcard ../LibExt/Makefile)) +module_App := $(dir $(wildcard ../App/Makefile)) +module_AppExt := $(dir $(wildcard ../AppExt/Makefile)) +module_Alg := $(dir $(wildcard ../Alg/Makefile)) + +-include ../Project/ProjectConfig.txt + +ifneq "$(ACTIVE_PROJECT)" "" +module_Prj := ../Project/$(ACTIVE_PROJECT)/ +else +# Find the first folder in ../Project/ that contains "Makefile" +ifeq "$(shell uname)" "Linux" +module_Prj := $(dir $(firstword $(sort $(shell find ../Project -name 'Makefile')))) +else +module_Prj := $(dir $(firstword $(sort $(shell find ../Project -name \'Makefile\')))) +endif +endif +test_if_unix_file_fmt = $(shell cd $(1); ret=`if [ "$(OS)" == "Linux" ]; then tools/recursive_dir -t . --exclude-ext .o .a .bin .axf .7z --exclude-dir .svn .git; else tools/recursive_dir.exe -t . --exclude-ext .o .a .bin .axf .7z --exclude-dir .svn .git; fi`; echo "$$ret";) + +module_all := \ + $(module_Common) \ + $(module_Drv) \ + $(module_DrvExt) \ + $(module_Lib) \ + $(module_LibExt) \ + $(module_App) \ + $(module_AppExt) \ + $(module_Alg) + +ifeq "$(LOG_ERR)" "ON" +define copy_log + @-cp \ + $(module_Common)log*.txt \ + $(module_Drv)log*.txt \ + $(module_DrvExt)log*.txt \ + $(module_Lib)log*.txt \ + $(module_LibExt)log*.txt \ + $(module_App)log*.txt \ + $(module_AppExt)log*.txt \ + $(module_Alg)log*.txt \ + $(module_Prj)log*.txt \ + . +endef +else +define copy_log +endef +endif + +ifeq "$(ISOLATE_DEP)" "ON" +.PHONY: all rm_log $(module_all) $(module_Prj) clean rebuild debug release dep + +all: rm_log + @make dep + @make debug + @make release + $(call copy_log) +else +.PHONY: all rm_log $(module_all) $(module_Prj) clean rebuild debug release + +all: rm_log $(module_all) $(module_Prj) + $(call copy_log) +endif + +$(module_all): +ifeq ($(OS),Linux) + @$(MAKE) --directory=$@ $(MAKECMDGOALS) +else + @$(MAKE) --directory=$@ $(MAKECMDGOALS) $(JOB_FLAGS) +endif + +$(module_Prj):$(module_all) + @$(MAKE) --directory=$@ $(MAKECMDGOALS) + +rm_log: + @-rm -f log*.txt + +clean: rm_log $(module_all) $(module_Prj) + +ifeq "$(ISOLATE_DEP)" "ON" +rebuild: + @make clean + @make dep + @make debug + @make release + $(call copy_log) + +dep: $(module_all) $(module_Prj) +else +rebuild: rm_log $(module_all) $(module_Prj) + $(call copy_log) +endif + +debug: rm_log $(module_Prj) + $(call copy_log) + +release: rm_log $(module_Prj) + $(call copy_log) + +rm_chk_log: + @-rm -f chk*.txt + +chk: rm_chk_log $(module_all) $(module_Prj) + +chkclean: $(module_all) $(module_Prj) + +rm_lint_log: + @-rm -f lint*.txt + +lint: rm_lint_log $(module_all) $(module_Prj) + +lintclean: $(module_all) $(module_Prj) + +chk_unix: + @result="$(call test_if_unix_file_fmt, ../)"; if [ ! -z "$$result" ]; then \ + echo -e "\e[1;31mUNIX file format check failed:\e[0m" >&2; \ + for n in $$result; do \ + echo -e "\t$$n" >&2; \ + done; \ + exit 1; \ + fi \ No newline at end of file diff --git a/board/novatek/na51055/loader/MakeCommon/OutputImg.txt b/board/novatek/na51055/loader/MakeCommon/OutputImg.txt new file mode 100755 index 000000000000..3dc0f7ed8498 --- /dev/null +++ b/board/novatek/na51055/loader/MakeCommon/OutputImg.txt @@ -0,0 +1,556 @@ +#---------------------------------------------------------------------- +# Local variable to determine create library or binary file +#---------------------------------------------------------------------- +OUTPUT_FILE = BIN + +#---------------------------------------------------------------------- +# include make common and make option files +#---------------------------------------------------------------------- +include $(MAKE_COMMON_DIR)/MakeOption.txt +include $(MAKE_COMMON_DIR)/MakeCommon.txt + +#---------------------------------------------------------------------- +# CHIPCFG parameters +#---------------------------------------------------------------------- +ifeq "$(CHIPCFG)" "" + CHIPCFG := CHIPCFG +endif + +#---------------------------------------------------------------------- +# get force link ThirdParty symbols for both debug and release +#---------------------------------------------------------------------- +ifeq "$(USE_ECOS_KERNEL)" "ON" +rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d)) +LIB_ECOS_RTK_WIFI_DIR = $(ROOT_DIR)/ThirdParty/devs_eCos-rtl +LIB_ECOS_SELECT_RTK_WIFI_DIR = $(ROOT_DIR)/ThirdParty/devs_eCos-rtl$(WIFIMDL)es +LIB_ECOS_BASE_DIR = $(ROOT_DIR)/ThirdParty +LIB_ECOS_TMP = $(call rwildcard,$(LIB_ECOS_BASE_DIR)/,*.a) +LIB_ECOS_WO_RTK_WIFI_LIB = $(filter-out $(LIB_ECOS_RTK_WIFI_DIR)%, $(LIB_ECOS_TMP)) +LIB_ECOS_RTK_WIFI_LIB = $(call rwildcard,$(LIB_ECOS_SELECT_RTK_WIFI_DIR)/,*.a) +LIB_ECOS = $(LIB_ECOS_WO_RTK_WIFI_LIB) $(LIB_ECOS_RTK_WIFI_LIB) +#There are two eCos .o not in archive +ALL_OBJ_R += $(wildcard $(LIB_ECOS_BASE_DIR)/eCos/lib/*.o) +ALL_OBJ_D += $(wildcard $(LIB_ECOS_BASE_DIR)/eCos/lib/*.o) +endif + +#---------------------------------------------------------------------- +# get force link IPL symbols for both debug and release +#---------------------------------------------------------------------- +SYMBOL_IPL := IPL_SetDZoomFCB IPL_SetSleepFCB IPL_SetWakeupFCB IPL_GetCapRawFCB IPL_SetPauseDMAFCB IPL_SetResumeDMAFCB IPL_SetImgInOutFCB IPL_SetVAFCB IPL_GetIMEHalIdxFCB IPL_GetIPLInfoFCB IPL_TrigFCB IPL_SetTrigInfoFCB IPL_Stream2PauseFCB IPL_Pause2StreamFCB DCE_D2D_CB IPE_D2D_CB IFE_D2D_CB IFE2_D2D_CB IME_D2D_CB DRE_D2D_CB RHEIME_D2D_IFECB RHEIME_D2D_DCECB RHEIME_D2D_IPECB RHEIME_D2D_IMECB RHEIME_D2D_RHECB IPL_GetCtrlFlowFCB IQUC_InitCtrlItem + +#---------------------------------------------------------------------- +# include the libraries +#---------------------------------------------------------------------- +# +# get Debug LIBs +# +LIB_ALG_DIR_D = $(ARC_BASE_DIR)/../Alg/ARC/Debug +LIB_APP_DIR_D = $(ARC_BASE_DIR)/App/Debug +LIB_COM_DIR_D = $(ARC_BASE_DIR)/Common/Debug +LIB_DRV_DIR_D = $(ARC_BASE_DIR)/Drv/Debug +LIB_LIB_DIR_D = $(ARC_BASE_DIR)/Lib/Debug + +# get Alg libraries +LIB_ALG_D := $(wildcard $(LIB_ALG_DIR_D)/*.a) + +# get App/AppExt libraries +LIB_APP_D := $(wildcard $(LIB_APP_DIR_D)/*.a) + +# get Common libraries +LIB_COM_D := $(wildcard $(LIB_COM_DIR_D)/*.a) + +# get Drv/DrvExt libraries +LIB_DRV_ALL_D := $(wildcard $(LIB_DRV_DIR_D)/*.a) + +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_DIR_D = $(ARC_BASE_DIR)/Lib/Debug +LIB_STRGEXT_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/STRGEXT_*.a) +LIB_STRGEXT_D := $(wildcard $(LIB_LIB_DIR_D)/STRGEXT_$(STORAGEEXT)_D.a) +LIB_STRGINT_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/STRGINT_*.a) +LIB_STRGINT_D := $(wildcard $(LIB_LIB_DIR_D)/STRGINT_$(STORAGEINT)_D.a) +LIB_REMAP_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/Remap_*.a) +LIB_REMAP_D := $(wildcard $(LIB_LIB_DIR_D)/Remap_$(RESETFLAG)_D.a) +LIB_RESET_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/Reset_*.a) +LIB_RESET_D := $(wildcard $(LIB_LIB_DIR_D)/Reset_$(RESETCHIP)_D.a) +LIB_COMMON_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/Common_*.a) +LIB_COMMON_D := $(wildcard $(LIB_LIB_DIR_D)/Common_$(COMMON_LIB)_D.a) +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_ALL_D := $(filter-out $(LIB_PARSER_ALL_D) $(LIB_SLIDE_ALL_D), $(wildcard $(LIB_LIB_DIR_D)/*.a)) + +LIB_LIB_D := $(filter-out $(LIB_STRGEXT_ALL_D) $(LIB_STRGINT_ALL_D) $(LIB_REMAP_ALL_D) $(LIB_RESET_ALL_D) $(LIB_COMMON_ALL_D), $(LIB_LIB_ALL_D)) + +# +# get Release LIBs +# +LIB_LIB_DIR_R = $(ARC_BASE_DIR)/Lib/Release +LIB_STRGEXT_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/STRGEXT_*.a) +LIB_STRGEXT_R := $(wildcard $(LIB_LIB_DIR_R)/STRGEXT_$(STORAGEEXT).a) +LIB_STRGINT_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/STRGINT_*.a) +LIB_STRGINT_R := $(wildcard $(LIB_LIB_DIR_R)/STRGINT_$(STORAGEINT).a) +LIB_REMAP_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/Remap_*.a) +LIB_REMAP_R := $(wildcard $(LIB_LIB_DIR_R)/Remap_$(RESETFLAG).a) +LIB_RESET_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/Reset_*.a) +LIB_RESET_R := $(wildcard $(LIB_LIB_DIR_R)/Reset_$(RESETCHIP).a) +LIB_COMMON_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/Common_*.a) +LIB_COMMON_R := $(wildcard $(LIB_LIB_DIR_R)/Common_$(COMMON_LIB).a) +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_ALL_R := $(filter-out $(LIB_PARSER_ALL_R) $(LIB_SLIDE_ALL_R), $(wildcard $(LIB_LIB_DIR_R)/*.a)) + +#LIB_LIB_R := $(filter-out $(LIB_STRGEXT_ALL_R) $(LIB_STRGINT_ALL_R) $(LIB_REMAP_ALL_R), $(LIB_LIB_ALL_R)) +LIB_LIB_R := $(filter-out $(LIB_STRGEXT_ALL_R) $(LIB_REMAP_ALL_R) $(LIB_RESET_ALL_R) $(LIB_COMMON_ALL_R), $(LIB_LIB_ALL_R)) + + +# get total libraries for Debug & Release mode; note we cannot get string of LIB_R from LIB_D, or vice versa, +# because we may build Debug and Release output separately, the library of one mode maybe not exist, and cause +# the link problem. So, while adding/deleting libraries, please be patient to do it for Debug and Release mode both. + +LIB_R := \ + $(LIB_LIB_R) \ + $(LIB_STRGEXT_R) \ + $(LIB_REMAP_R) \ + $(LIB_RESET_R) \ + $(LIB_COMMON_R) + +LIB_D := \ + $(LIB_LIB_D) \ + $(LIB_STRGEXT_D) \ + $(LIB_REMAP_D) \ + $(LIB_RESET_D) \ + $(LIB_COMMON_D) + +# If some libraries only available in Release mode, add these libraries in Debug mode too. +LIB_D += $(filter-out $(subst Debug/,Release/,$(LIB_D:_D.a=.a)),$(LIB_R)) + +# Append eCos library to both Debug and Release mode +# (We don't have debug mode's eCos library) +LIB_R += $(LIB_ECOS) +LIB_D += $(LIB_ECOS) + +#---------------------------------------------------------------------- +# set the make outputs +#---------------------------------------------------------------------- +# for debug target +IMAGE_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.axf +BIN_D = $(IMG_DEBUG)/$(LDR_NAME).bin +MAP_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.txt +MAP2_D = $(IMG_DEBUG)/$(PRJ_NAME)_ldmap_D.txt +SYM_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.sym +DASM_D = $(IMG_DEBUG)/$(PRJ_NAME)_dasm_D.txt +ifeq "$(MODELEXT_BUILT_IN)" "MODELEXT_BUILT_IN_OFF" +MODELEXT_D = $(IMG_DEBUG)/$(BIN_NAME).ext.bin +endif + + +# for release target +IMAGE_R = $(IMG_RELEASE)/$(PRJ_NAME).axf +BIN_R = $(IMG_RELEASE)/$(LDR_NAME).bin +MAP_R = $(IMG_RELEASE)/$(PRJ_NAME).txt +MAP2_R = $(IMG_RELEASE)/$(PRJ_NAME)_ldmap.txt +SYM_R = $(IMG_RELEASE)/$(PRJ_NAME).sym +DASM_R = $(IMG_RELEASE)/$(PRJ_NAME)_dasm.txt +ifeq "$(MODELEXT_BUILT_IN)" "MODELEXT_BUILT_IN_OFF" +MODELEXT_R = $(IMG_RELEASE)/$(BIN_NAME).ext.bin +endif + +#---------------------------------------------------------------------- +# if enable LDS_MAP +#---------------------------------------------------------------------- +ifeq "$(LDS_MAP)" "ON" +LDMAP_D = -Map $(MAP2_D) +LDMAP_R = -Map $(MAP2_R) +endif + +#---------------------------------------------------------------------- +# set the warning/error log file option +#---------------------------------------------------------------------- +log_file = log_Prj.txt + +# 0: Standard input (stdin), 1: Standard output (stdout), 2: Standard error (stderr) +# 2>>$(log_file) means redirect standard error to $(log_file) +# 2>>/dev/null means redirect standard error to NULL (Don't display error message) +ifeq "$(LOG_ERR)" "ON" +LOG_OPTION = 2>>$(log_file) +endif + +#---------------------------------------------------------------------- +# set robustness checking log file +#---------------------------------------------------------------------- +lint_file = lint_Prj.txt +lintopt_file = options_Prj.lnt +lintsum_file = lintsum_Prj.txt + +#---------------------------------------------------------------------- +# set the make targets +#---------------------------------------------------------------------- +build_D: make_debug_begin prepare_log $(IMAGE_D) $(BIN_D) +build_R: make_release_begin prepare_log $(IMAGE_R) $(BIN_R) +build_pipe_D: $(IMAGE_D) $(BIN_D) +build_pipe_R: $(IMAGE_R) $(BIN_R) + +ifeq "$(ISOLATE_DEP)" "ON" +build_DEP: make_dep_begin $(SRC) $(ASM) $(CPP_SRC) $(ALL_DEP) +endif + +build_LINT: make_lint_begin $(LINT_FILE) + +prepare_log: + @$(LOG_OPTION) + +ifeq "$(ARCH)" "ARM" +#arm-none-eabi-gcc -march=armv7-a -mcpu=cortex-a9 -mfpu=neon -mfloat-abi=softfp -print-file-name=libm.a +ifeq "$(FPU)" "hard" +libgcc_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mabi=aapcs -mfpu=neon -mfloat-abi=$(FPU) -print-libgcc-file-name) +libgcc_dir_el = $(shell dirname "$(libgcc_path)") +libstdc_path = $(shell $(CC) -msoft-float -print-file-name=libstdc++.a) +libstdc_dir_el = $(shell dirname "$(libstdc_path)") +libm_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mfpu=neon -mfloat-abi=$(FPU) -print-file-name=libm.a) +libm_dir = $(shell dirname "$(libm_path)") +else +libgcc_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mabi=aapcs -mfloat-abi=$(FPU) -print-libgcc-file-name) +libgcc_dir_el = $(shell dirname "$(libgcc_path)") +libstdc_path = $(shell $(CC) -msoft-float -print-file-name=libstdc++.a) +libstdc_dir_el = $(shell dirname "$(libstdc_path)") +libm_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mfloat-abi=$(FPU) -print-file-name=libm.a) +libm_dir = $(shell dirname "$(libm_path)") +endif +endif + +define append_modelext + echo Append $1 into $4. \ + && $(AR) x $3 $1.o \ + && $(FE) --only-section=modelext_header.$1 -O binary -S -R .comment -R .note $1.o $2/$1.header \ + && cat $2/$1.header >> $4 \ + && $(FE) --only-section=modelext_data.$1 -O binary -S -R .comment -R .note $1.o $2/$1.data \ + && cat $2/$1.data >> $4 +endef + + +#Replace string existing in lds file +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_256" + BOARD_UITRON_ADDR = 0x8000000 +endif +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_512" + BOARD_UITRON_ADDR = 0x10000000 +endif +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_1024" + BOARD_UITRON_ADDR = 0x20000000 +endif +endif + +LD_REMAP_LIB = Remap_$(RESETFLAG) +LD_DOREMAP = doremap$(RESETFLAG) +LD_RESET_LIB = Reset_$(RESETCHIP) +LD_COMMON_LIB = Common_$(COMMON_LIB) +ifeq "$(BL_COMPRESS)" "ENABLE" +LD_CONFIGRAM = configramLZ +else +LD_CONFIGRAM = configramNM +endif +LD_REPLACE_VAR = sed \ + -e 's/$$LD_REMAP_LIB/$(LD_REMAP_LIB)/g' \ + -e 's/$$LD_DOREMAP/$(LD_DOREMAP)/g' \ + -e 's/$$LD_CONFIGRAM/$(LD_CONFIGRAM)/g' \ + -e 's/$$LD_BASE_ADDR/$(LD_BASE_ADDR)/g' \ + -e 's/$$LD_RESET_LIB/$(LD_RESET_LIB)/g' \ + -e 's/$$LD_COMMON_LIB/$(LD_COMMON_LIB)/g' \ + $(SCATTER) + +#The folder, the working space to fill the full path into lds file +LD_DIR_WORKING_D= $(IMG_BASE_DIR)/Debug/ObjectLds +#Generate the working folder and temp lds file called replace.lds +LD_REPLACE_LDS_D= $(shell mkdir -p $(LD_DIR_WORKING_D)) $(shell $(OBJDUMP) -h $(LIB_D) | grep ".version.info" > tmp_awk1) $(shell $(LD_REPLACE_VAR) > $(LD_DIR_WORKING_D)/replace.lds) +#The real lds file replaced of using by linker +LD_PATH_LDS_D = $(LD_DIR_WORKING_D)/$(basename $(SCATTER))_D.lds +#Here have some steps as following to get a some files explained below, +#Step 1: Generate temp lds file +#Step 2: export the contents of $(LIB_D) into libs.txt +#Step 3: export the contents of $(ALL_OBJ_D) into objs.txt +#Step 4: Give mips-nvt.exe libs.txt, objs.txt and replace.lds to get ld_ext.d, ld_lib.txt, ld_lib_ban.txt and real lds file for linker. +# Where, +# ld_ext.d is a decency file depends on .o used in lds file +# ld_lib_ban is a list of .a files to ban, because linker should use the .a file after extracting .o. +# real lds file is replaced by full path. +LD_DFILE_D = $(LD_REPLACE_LDS_D) $(shell echo $(LIB_D) > $(LD_DIR_WORKING_D)/libs.txt ) $(shell echo $(ALL_OBJ_D) > $(LD_DIR_WORKING_D)/objs.txt ) $(shell $(LDNVT) --lds-dst=$(LD_PATH_LDS_D) --lds-dir=$(LD_DIR_WORKING_D) --lds-src=$(LD_DIR_WORKING_D)/replace.lds --libs-src=$(LD_DIR_WORKING_D)/libs.txt --objs-src=$(LD_DIR_WORKING_D)/objs.txt --objs-dir=$(OBJ_DEBUG)) $(LD_DIR_WORKING_D)/ld_ext.d +#Getting the contents of ld_lib.txt +LD_LIB_D = $(shell cat $(LD_DIR_WORKING_D)/ld_lib.txt 2>>/dev/null) +#Getting the contents of ld_lib_ban.txt +LD_LIB_BAN_D = $(shell cat $(LD_DIR_WORKING_D)/ld_lib_ban.txt 2>>/dev/null) +tmp_awk2 = $(shell awk -F" " '{print $$2}' tmp_awk1 | awk -F"." '{print $$5}') +tmp_awk3 = $(addsuffix _LIBRARY_VERSION_INFO, $(tmp_awk2)) + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),debug build_pipe_D)) +include $(LD_DFILE_D) +endif + +$(LD_LIB_D): $(MODELEXT_D) + +#$(MODELEXT_D): $(LIB_MODELEXT_D) +# @echo Creating modelext $@ ... \ +# && rm -f $@ \ +# && $(call append_modelext,modelext_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,bin_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,pinmux_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,intdir_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,emb_partition_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,gpio_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,dram_partition_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,model_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(EBIN) $(EBIN_METHOD) $@ 0x18 $(EBIN_MNAME) +# @BIN_SIZE=`ls -l $@ | cut -d ' ' -f 5`; \ +# RESIDUAL=$$(($${BIN_SIZE} % 4)); \ +# if [ "$${RESIDUAL}" -ne "0" ]; then \ +# echo "sizeof($@) is not 4-byte aligned"; \ +# exit 1; \ +# fi + +$(IMAGE_D): $(SRC) $(ASM) $(CPP_SRC) $(ALL_OBJ_D) $(LIB_D) $(LD_LIB_D) $(MODELEXT_D) + $(shell mv *.o $(IMG_BASE_DIR)/Debug/ObjectCode 2>>/dev/null) + @echo '-o $@ $(ALL_OBJ_D)'> ld_d.tmp + @echo '--start-group $(LD_LIB_D) $(filter-out $(LD_LIB_BAN_D),$(LIB_D)) --end-group -Bstatic -EL --no-wchar-size-warning --gc-sections -T $(LD_PATH_LDS_D) -L "$(libgcc_dir_el)" -L"$(libstdc_dir_el)" -L"$(libm_dir)" -lgcc $(LDMAP_D)' >> ld_d.tmp +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" + @echo "Linking CA53_core2...$(LD_PATH_LDS_D)" \ + && echo Creating image $@ ... \ + && $(LD) @ld_d.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_D) \ + && $(NM) -n $@ > tmp_sym_d \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_d > $(SYM_D) \ + && rm -f tmp_sym_d \ + && rm -f ld_d.tmp \ + && rm -f tmp_awk1 +else + @echo "Linking ..." \ + && echo Creating image $@ ... \ + && $(LD) @ld_d.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_D) \ + && $(NM) -n $@ > tmp_sym_d \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_d > $(SYM_D) \ + && rm -f tmp_sym_d \ + && rm -f ld_d.tmp \ + && rm -f tmp_awk1 +endif + + +$(BIN_D): $(IMAGE_D) +ifeq "$(MULTI_REGIONS)" "ON" + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ \ + && mv $(IMG_DEBUG)/SPECIAL_RO $(BIN_D) +else + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ +endif +ifeq "$(LDS_MAP)" "ON" + @echo Generate LDS map file $(MAP2_D): ok +endif +ifeq "$(AXF_DIS)" "ON" + @echo Translate AXF $< to disassembly... \ + && $(OBJDUMP) -D $(IMAGE_D) > $(DASM_D) +endif + +ifeq "$(BL_COMPRESS)" "ENABLE" + @echo Compressing file $(@)\ + && $(BFC) c lz $(BIN_D) tmp 1 $(UNCOMPRESSEDPART_SIZE_OFFSET) \ + && cp -f tmp $(BIN_D) \ + && rm -f tmp \ + && echo Encrypt binary file $@ for $(CHIP)... $(CHIP_VER) $(DMA_CLOCK) $(SDRAM_SIZE) $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE)\ + && $(EBIN) $@ $@ 680 + $(CFGRAM) $@ -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI_STR) -chip=660 -package=$(CHIP) -ldver=$(LOADER_VERSION) -gui=$(CONFIG_RAM_GUI_EN) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) +# $(CFGRAM) $@ ../../Tools/ConfigRam/$(CHIP)_$(CHIP_VER)_$(DMA_CLOCK)_$(SDRAM_SIZE)$(DDR_FILE_STR).ini 650 $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE) $(LV1_CLK) +else + @echo Encrypt binary file $@ for $(CHIP)...\ + && $(EBIN) $@ $@ 680 $(SECURE_BOOT) +endif + +ifeq "$(COPY_BIN_2_STG)" "ON" +ifneq "$(NVT_STG_PATH)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH) ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH)$(notdir $(BIN_D)) +endif +ifneq "$(NVT_STG_PATH_MIPS2)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin +endif + +ifneq "$(NVT_STG_PATH_CA532)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH_CA532)_FWCA532.bin ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH_CA532)_FWCA532.bin +endif +endif + +#Please refer LD_DIR_WORKING_D for getting explanation. Ohters are in the same way. +LD_DIR_WORKING_R= $(IMG_BASE_DIR)/Release/ObjectLds +LD_REPLACE_LDS_R= $(shell mkdir -p $(LD_DIR_WORKING_R)) $(shell $(OBJDUMP) -h $(LIB_R) | grep ".version.info" > tmp_awk1) $(shell $(LD_REPLACE_VAR) > $(LD_DIR_WORKING_R)/replace.lds) +LD_PATH_LDS_R = $(LD_DIR_WORKING_R)/$(basename $(SCATTER))_R.lds +LD_DFILE_R = $(LD_REPLACE_LDS_R) $(shell echo $(LIB_R) > $(LD_DIR_WORKING_R)/libs.txt ) $(shell echo $(ALL_OBJ_R) > $(LD_DIR_WORKING_R)/objs.txt ) $(shell $(LDNVT) --lds-dst=$(LD_PATH_LDS_R) --lds-dir=$(LD_DIR_WORKING_R) --lds-src=$(LD_DIR_WORKING_R)/replace.lds --libs-src=$(LD_DIR_WORKING_R)/libs.txt --objs-src=$(LD_DIR_WORKING_R)/objs.txt --objs-dir=$(OBJ_RELEASE)) $(LD_DIR_WORKING_R)/ld_ext.d +LD_LIB_R = $(shell cat $(LD_DIR_WORKING_R)/ld_lib.txt 2>>/dev/null) +LD_LIB_BAN_R = $(shell cat $(LD_DIR_WORKING_R)/ld_lib_ban.txt 2>>/dev/null) +tmp_awk2 = $(shell awk -F" " '{print $$2}' tmp_awk1 | awk -F"." '{print $$5}') +tmp_awk3 = $(addsuffix _LIBRARY_VERSION_INFO, $(tmp_awk2)) + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),release build_pipe_R)) +include $(LD_DFILE_R) +endif + +$(LD_LIB_R): $(MODELEXT_R) + +#$(MODELEXT_R): $(LIB_MODELEXT_R) +# @echo Creating modelext $@ \ +# && rm -f $@ \ +# && $(call append_modelext,modelext_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,bin_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,pinmux_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,intdir_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,emb_partition_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,gpio_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,dram_partition_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,model_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(EBIN) $(EBIN_METHOD) $@ 0x18 $(EBIN_MNAME) +# @BIN_SIZE=`ls -l $@ | cut -d ' ' -f 5`; \ +# RESIDUAL=$$(($${BIN_SIZE} % 4)); \ +# if [ "$${RESIDUAL}" -ne "0" ]; then \ +# echo "sizeof($@) is not 4-byte aligned"; \ +# exit 1; \ +# fi + +$(IMAGE_R): $(SRC) $(ASM) $(CPP_SRC) $(ALL_OBJ_R) $(LIB_R) $(LD_LIB_R) $(MODELEXT_R) + $(shell mv *.o $(IMG_BASE_DIR)/Release/ObjectCode 2>>/dev/null) + @echo '-o $@ $(ALL_OBJ_R) '> ld_r.tmp + @echo '--start-group $(LD_LIB_R) $(filter-out $(LD_LIB_BAN_R),$(LIB_R)) --end-group -Bstatic -EL --no-wchar-size-warning --gc-sections -T $(LD_PATH_LDS_R) -L"$(libgcc_dir_el)" -L"$(libstdc_dir_el)" -lgcc $(LDMAP_R)' >> ld_r.tmp + +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" + @echo "Linking CA53_core2...$(LD_PATH_LDS_R)" \ + && echo Creating image $@ ... \ + && $(LD) @ld_r.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_R) \ + && $(NM) -n $@ > tmp_sym_r \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_r > $(SYM_R) \ + && rm -f tmp_sym_r \ + && rm -f ld_r.tmp \ + && rm -f tmp_awk1 +else + @echo "Linking ..." \ + && echo Creating image $@ ... \ + && $(LD) @ld_r.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t -marm $@ > $(MAP_R) \ + && $(NM) -n $@ > tmp_sym_r \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_r > $(SYM_R) \ + && rm -f tmp_sym_r \ + && rm -f ld_r.tmp \ + && rm -f tmp_awk1 +endif + +$(BIN_R): $(IMAGE_R) +ifeq "$(MULTI_REGIONS)" "ON" + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ \ + && mv $(IMG_RELEASE)/SPECIAL_RO $(BIN_R) +else + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ +endif + +ifeq "$(LDS_MAP)" "ON" + @echo Generate LDS map file $(MAP2_R): ok +endif +ifeq "$(AXF_DIS)" "ON" + @echo Translate AXF $< to disassembly... \ + && $(OBJDUMP) -D $(IMAGE_R) > $(DASM_R) +endif +ifeq "$(BL_COMPRESS)" "ENABLE" + @echo Compressing file $(@)\ + && $(BFC) c lz $(BIN_R) tmp 1 $(UNCOMPRESSEDPART_SIZE_OFFSET) \ + && cp -f tmp $(BIN_R) \ + && rm -f tmp \ + && echo Encrypt binary file $@ for $(CHIP)... $(CHIP_VER) $(DMA_CLOCK) $(SDRAM_SIZE) $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE)\ + && $(EBIN) $@ $@ $(CHIPID) +ifeq "$(NC520_525_COMBO)" "ON" + $(CFGRAM) $@ -freq=$(DRAM1_CLK) -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI2_STR) -chip=$(CHIPID) -package=$(CHIP) -ldver=$(LOADER_VERSION) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) -dram_number=$(DRAM_NUMBER_DET_PARAM) -ini_NC520_525_combo=../../Tools/ConfigRam/$(DDR_INI_STR_NC520_525_COMBO) -dram_ssc=$(DRAM_SSC_PARAM) -52x_combo_528=$(52x_528_COMBO) -dram_wt=$(DDR_TREFI_PARAM) + $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) $(ENCRYPT_DATA) $(SECUREBOOT_MSG) $(AES_KEY_FILE_DIR) $(RSA_PUB_KEY_FILE_DIR) $(RSA_PRV_KEY_FILE_DIR) +else +ifeq "$(CHIPID)" "520" + $(CFGRAM) $@ -freq=$(DRAM1_CLK) -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI2_STR) -chip=$(CHIPID) -package=$(CHIP) -ldver=$(LOADER_VERSION) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) -dram_number=$(DRAM_NUMBER_DET_PARAM) -dram_ssc=$(DRAM_SSC_PARAM) -52x_combo_528=$(52x_528_COMBO) -dram_wt=$(DDR_TREFI_PARAM) -dram_2nd_tlb=$(2ND_INI) -dram_2nd_tlb_gpio_no=$(GPIO_NUM) -2nd_ini=../../Tools/ConfigRam/$(DDR_INI_STR2) -2nd_ini2=../../Tools/ConfigRam/$(DDR_INI2_STR2) + $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) $(ENCRYPT_DATA) $(SECUREBOOT_MSG) $(AES_KEY_FILE_DIR) $(RSA_PUB_KEY_FILE_DIR) $(RSA_PRV_KEY_FILE_DIR) +endif + +ifeq "$(CHIPID)" "528" + $(CFGRAM) $@ -freq=$(DRAM1_CLK) -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI2_STR) -chip=$(CHIPID) -package=$(CHIP) -ldver=$(LOADER_VERSION) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) -dram_number=$(DRAM_NUMBER_DET_PARAM) -dram_ssc=$(DRAM_SSC_PARAM) -dram_wt=$(DDR_TREFI_PARAM) -dram_2nd_tlb=$(2ND_INI) -dram_2nd_tlb_gpio_no=$(GPIO_NUM) -2nd_ini=../../Tools/ConfigRam/$(DDR_INI_STR2) -2nd_ini2=../../Tools/ConfigRam/$(DDR_INI2_STR2) -fast_k=$(FAST_K_PARAM) + $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) $(ENCRYPT_DATA) $(SECUREBOOT_MSG) $(AES_KEY_FILE_DIR) $(RSA_PUB_KEY_FILE_DIR) $(RSA_PRV_KEY_FILE_DIR) +endif +endif +# $(CFGRAM) $@ -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI_STR) -chip=660 -package=$(CHIP) -ldver=$(LOADER_VERSION) -gui=$(CONFIG_RAM_GUI_EN) -storage=$(STORAGEINT) +# $(CFGRAM) $@ ../../Tools/ConfigRam/$(CHIP)_$(CHIP_VER)_$(DMA_CLOCK)_$(SDRAM_SIZE)$(DDR_FILE_STR).ini 650 $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE) $(LV1_CLK) +else + @echo Encrypt binary file $@ for $(CHIP)...\ + && $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) \ + && $(CFGRAM) $@ -freq=$(DRAM1_CLK) -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI2_STR) -chip=$(CHIPID) -package=$(CHIP) -ldver=$(LOADER_VERSION) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) -dram_number=$(DRAM_NUMBER_DET_PARAM) -dram_ssc=$(DRAM_SSC_PARAM) -dram_wt=$(DDR_TREFI_PARAM) +endif + +ifeq "$(COPY_BIN_2_STG)" "ON" +ifneq "$(NVT_STG_PATH)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH) ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH)$(notdir $(BIN_R)) +endif +ifneq "$(NVT_STG_PATH_MIPS2)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH_MIPS2) ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin +endif + +ifneq "$(NVT_STG_PATH_CA532)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH_CA532)_FWCA532.bin ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH_CA532)_FWCA532.bin +endif +endif + +.PHONY: +rm_log: +ifeq "$(CLEAN_LOG)" "ON" + @-rm -f $(log_file) +endif + +clean: + @-echo Clean $(basename $(notdir $(IMAGE_R))) ... \ + && rm -rf --no-preserve-root $(IMG_BASE_DIR) $(log_file) $(lint_file) + +ifeq "$(ISOLATE_DEP)" "ON" +all: rm_log + @make dep + @make debug + @make release + +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: build_DEP +else +rebuild: clean build_D build_R +endif + +debug: rm_log make_debug_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_D +else + $(MAKE) build_pipe_D $(JOB_FLAGS) +endif + +release: rm_log make_release_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_R +else + $(MAKE) build_pipe_R $(JOB_FLAGS) +endif + +#remove unused remap.a for sdk +remap: + rm -v $(filter-out $(LIB_REMAP_D), $(LIB_REMAP_ALL_D)) $(filter-out $(LIB_REMAP_R), $(LIB_REMAP_ALL_R)) + +codesize: $(IMAGE_R) + @$(OBJDUMP) -t $< > $<.sym && \ + $(LDNVT) -j $<.sym && \ + mv RO_RW.txt ZI.txt $(IMG_RELEASE) diff --git a/board/novatek/na51055/loader/MakeCommon/OutputLib.txt b/board/novatek/na51055/loader/MakeCommon/OutputLib.txt new file mode 100755 index 000000000000..cf436efaa33d --- /dev/null +++ b/board/novatek/na51055/loader/MakeCommon/OutputLib.txt @@ -0,0 +1,155 @@ +#---------------------------------------------------------------------- +# Local variable to determine create library or binary file +#---------------------------------------------------------------------- +OUTPUT_FILE = LIB + +#---------------------------------------------------------------------- +# include make common and make option files +#---------------------------------------------------------------------- +ifeq "$(OPTION_LOADED)" "" + include $(MAKE_COMMON_DIR)/MakeOption.txt + LOCAL_CLEAN_LOG = $(CLEAN_LOG) +else + LOCAL_CLEAN_LOG = OFF +endif + +include $(MAKE_COMMON_DIR)/MakeCommon.txt + +#---------------------------------------------------------------------- +# set the make outputs +#---------------------------------------------------------------------- +IMAGE_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.a +IMAGE_R = $(IMG_RELEASE)/$(PRJ_NAME).a + +#---------------------------------------------------------------------- +# set the warning/error log file option +#---------------------------------------------------------------------- +# $(APP_PATH), $(APPEXT_PATH), $(LIB_PATH), $(LIBEXT_PATH) will be assigned value in MakeCommon.txt +ifneq "$(ALG_PATH)" "" + log_file := $(subst MakeCommon,Alg/log_Alg.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Alg/lint_Alg.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Alg.lnt + lintsum_file := $(subst MakeCommon,App/lintsum_Alg.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(APP_PATH)" "" + log_file := $(subst MakeCommon,App/log_App.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,App/lint_App.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_App.lnt + lintsum_file := $(subst MakeCommon,App/lintsum_App.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(APPEXT_PATH)" "" + log_file := $(subst MakeCommon,AppExt/log_AppExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,AppExt/lint_AppExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_AppExt.lnt + lintsum_file := $(subst MakeCommon,AppExt/lintsum_AppExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(LIB_PATH)" "" + log_file := $(subst MakeCommon,Lib/log_Lib.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Lib/lint_Lib.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Lib.lnt + lintsum_file := $(subst MakeCommon,Lib/lintsum_Lib.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(LIBEXT_PATH)" "" + log_file := $(subst MakeCommon,LibExt/log_LibExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,LibExt/lint_LibExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_LibExt.lnt + lintsum_file := $(subst MakeCommon,LibExt/lintsum_LibExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(DRV_PATH)" "" + log_file := $(subst MakeCommon,Drv/log_Drv.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Drv/lint_Drv.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Drv.lnt + lintsum_file := $(subst MakeCommon,Drv/lintsum_Drv.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(DRVEXT_PATH)" "" + log_file := $(subst MakeCommon,DrvExt/log_DrvExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,DrvExt/lint_DrvExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_DrvExt.lnt + lintsum_file := $(subst MakeCommon,DrvExt/lintsum_DrvExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(COM_PATH)" "" + log_file := $(subst MakeCommon,Common/log_Common.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Common/lint_Common.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Common.lnt + lintsum_file := $(subst MakeCommon,Common/lintsum_Common.txt,$(MAKE_COMMON_DIR)) +else + log_file := /dev/null + lint_file := /dev/null + lintopt_file := /dev/null + lintsum_file := /dev/null +endif + +ifeq "$(LOG_ERR)" "ON" + LOG_OPTION = 2>>$(log_file) + LOG_DATE = date >>$(log_file) + LOG_SPACE = echo >>$(log_file) +endif + +#---------------------------------------------------------------------- +# set the make targets +#---------------------------------------------------------------------- +build_D: make_debug_begin $(IMAGE_D) +build_R: make_release_begin $(IMAGE_R) +build_pipe_D: $(IMAGE_D) +build_pipe_R: $(IMAGE_R) + +ifeq "$(ISOLATE_DEP)" "ON" +build_DEP: make_dep_begin $(ALL_DEP) +endif + +build_LINT: make_lint_begin $(LINT_FILE) + +$(IMAGE_D): $(ALL_OBJ_D) + @echo Creating library $(notdir $@) ... \ + && rm -f $(IMAGE_D) \ + && $(AR) -cru $@ $^ + +$(IMAGE_R): $(ALL_OBJ_R) + @echo Creating library $(notdir $@) ... \ + && rm -f $(IMAGE_R) \ + && $(AR) -cru $@ $^ + +.PHONY: +rm_log: +ifeq "$(LOCAL_CLEAN_LOG)" "ON" + @-rm -f $(log_file) +endif + +clean: + @-echo Clean $(basename $(notdir $(IMAGE_R))) ... \ + && rm -rf --no-preserve-root $(PRJ_NAME)_Data $(log_file) $(lint_file) + +ifeq "$(ISOLATE_DEP)" "ON" +all: rm_log + @make dep + @make debug + @make release + +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: build_DEP +else +rebuild: clean build_D build_R +endif + +debug: rm_log make_debug_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_D +else + $(MAKE) build_pipe_D $(JOB_FLAGS) +endif + +release: rm_log make_release_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_R +else + $(MAKE) build_pipe_R $(JOB_FLAGS) +endif + +rm_lint_log: +ifeq "$(LOCAL_CLEAN_LOG)" "ON" + @-rm -f $(lint_file) +endif + +lint: rm_lint_log build_LINT + +lintclean: + @-echo Clean Lint $(basename $(notdir $(IMAGE_R))) checking data ... \ + && rm -rf --no-preserve-root $(LINT_DIR) $(lint_file) diff --git a/board/novatek/na51055/loader/MakeCommon/dump_tmp b/board/novatek/na51055/loader/MakeCommon/dump_tmp new file mode 100755 index 000000000000..e69de29bb2d1 diff --git a/board/novatek/na51055/loader/MakeCommon/make_combo_loader.sh b/board/novatek/na51055/loader/MakeCommon/make_combo_loader.sh new file mode 100755 index 000000000000..355662ca8a54 --- /dev/null +++ b/board/novatek/na51055/loader/MakeCommon/make_combo_loader.sh @@ -0,0 +1,229 @@ +#!/bin/bash +MODEL_BUILD_LIST=("lunch rtos cfg_TEST_REALCHIP gcc-linaro-6.4.1-2018.05-x86_64_arm-eabi" + "lunch rtos cfg_TEST_RTOS_RUN_CORE2 gcc-linaro-6.4.1-2018.05-x86_64_arm-eabi") + +function make_NT98525_loader_only(){ + cp ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h ../LibExt/LIBExt_src/Ctrl_Flow/bl_func_tmp.h + cp ../Project/Model/ModelConfig_EMU_EVB_528.txt ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt + cp ../Project/Model/ModelConfig_EMU_EVB.txt ../Project/Model/ModelConfig_EMU_EVB_tmp.txt + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_52x/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean "MODEL=EMU_EVB" + make clean "MODEL=EMU_EVB_528" + make release "MODEL=EMU_EVB" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name LD*.bin -exec cp {} ../output \; + cp ../LibExt/LIBExt_src/Ctrl_Flow/bl_func_tmp.h ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + cp ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt ../Project/Model/ModelConfig_EMU_EVB_528.txt + cp ../Project/Model/ModelConfig_EMU_EVB_tmp.txt ../Project/Model/ModelConfig_EMU_EVB.txt + #cp ../Project/Model/Loader525_Data/Release/LD98525A.bin ../output +} + +function make_NT98528_loader_only(){ + cp ../Project/Model/ModelConfig_EMU_EVB_528.txt ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt + cp ../Project/Model/ModelConfig_EMU_EVB.txt ../Project/Model/ModelConfig_EMU_EVB_tmp.txt + cp ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h ../LibExt/LIBExt_src/Ctrl_Flow/bl_func_tmp.h + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_528/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean "MODEL=EMU_EVB" + make clean "MODEL=EMU_EVB_528" + make release "MODEL=EMU_EVB_528" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name LD*.bin -exec cp {} ../output \; + cp ../LibExt/LIBExt_src/Ctrl_Flow/bl_func_tmp.h ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + cp ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt ../Project/Model/ModelConfig_EMU_EVB_528.txt + cp ../Project/Model/ModelConfig_EMU_EVB_tmp.txt ../Project/Model/ModelConfig_EMU_EVB.txt + #cp ../Project/Model/Loader528_Data/Release/LD98528A.bin ../output +} + +function make_NT9852x_combo_loader(){ + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE COMBINATION_52x/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean "MODEL=EMU_EVB" + make release "MODEL=EMU_EVB" "BIN_NAME=LDCOMBOA" "52x_528_COMBO=ON" + find ../Project/Model/ -name LD*.bin -exec cp {} ../output/LD9852XA.bin \; + #cp ../Project/Model/Loader525_Data/Release/LDCOMBOA.bin ../output/LD98525A.bin + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE COMBINATION_528/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean + make release "MODEL=EMU_EVB_528" "BIN_NAME=LDCOMBOA" + find ../Project/Model/ -name LD*.bin -exec cp {} ../output/LD98528A.bin \; + #cp ../Project/Model/Loader528_Data/Release/LDCOMBOA.bin ../output/LD98528A.bin + cat ../output/LD9852XA.bin ../output/LD98528A.bin > ../output/LDCOMBOA.bin + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_52x/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h +} + +function make_NT98525_eth_write_loader(){ + cp ../Project/Model/ModelConfig_EMU_EVB.txt ../Project/Model/ModelConfig_EMU_EVB_tmp.txt + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_52x/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + sed -i 's/^STORAGEEXT =[ \t].*/STORAGEEXT = Eth/g' ../Project/Model/ModelConfig_EMU_EVB.txt + make clean "MODEL=EMU_EVB" + make clean "MODEL=EMU_EVB_528" + make release "MODEL=EMU_EVB" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name loader.bin -exec cp {} ../output \; + cp ../Project/Model/ModelConfig_EMU_EVB_tmp.txt ../Project/Model/ModelConfig_EMU_EVB.txt + rm -rf ../Project/Model/ModelConfig_EMU_EVB_tmp.txt + #cp ../Project/Model/Loader525_Data/Release/LD98525A.bin ../output +} + +function make_NT98528_eth_write_loader(){ + cp ../Project/Model/ModelConfig_EMU_EVB_528.txt ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_528/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + sed -i 's/^STORAGEEXT =[ \t].*/STORAGEEXT = Eth/g' ../Project/Model/ModelConfig_EMU_EVB_528.txt + make clean "MODEL=EMU_EVB" + make clean "MODEL=EMU_EVB_528" + make release "MODEL=EMU_EVB_528" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name loader.bin -exec cp {} ../output/loader.bin \; + cp ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt ../Project/Model/ModelConfig_EMU_EVB_528.txt + rm -rf ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt +} + +function make_NT98525_usb_write_loader(){ + cp ../Project/Model/ModelConfig_EMU_EVB.txt ../Project/Model/ModelConfig_EMU_EVB_tmp.txt + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_52x/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + sed -i 's/^STORAGEEXT =[ \t].*/STORAGEEXT = Usb/g' ../Project/Model/ModelConfig_EMU_EVB.txt + make clean "MODEL=EMU_EVB" + make clean "MODEL=EMU_EVB_528" + make release "MODEL=EMU_EVB" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name LD98525A.bin -exec cp {} ../output/Wrldr525.bin \; + #cp ../Project/Model/Loader525_Data/Release/LD98525A.bin ../output + cp ../Project/Model/ModelConfig_EMU_EVB_tmp.txt ../Project/Model/ModelConfig_EMU_EVB.txt + rm -rf ../Project/Model/ModelConfig_EMU_EVB_tmp.txt +} + +function make_NT98528_usb_write_loader(){ + cp ../Project/Model/ModelConfig_EMU_EVB_528.txt ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_528/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + sed -i 's/^STORAGEEXT =[ \t].*/STORAGEEXT = Usb/g' ../Project/Model/ModelConfig_EMU_EVB_528.txt + make clean "MODEL=EMU_EVB" + make clean "MODEL=EMU_EVB_528" + make release "MODEL=EMU_EVB_528" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name LD98528A.bin -exec cp {} ../output/Wrldr528.bin \; + cp ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt ../Project/Model/ModelConfig_EMU_EVB_528.txt + rm -rf ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt +} + +make_NT98528_sqa_fastboot_test_nand(){ + cp ../Project/Model/ModelConfig_EMU_EVB_528.txt ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt + cp ../Project/Model/ModelConfig_EMU_EVB.txt ../Project/Model/ModelConfig_EMU_EVB_tmp.txt + cp ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h ../LibExt/LIBExt_src/Ctrl_Flow/bl_func_tmp.h + cp ../Project/Model/Src/prj_main.h ../Project/Model/Src/prj_main_tmp.h + + sed -i 's/^SDRAM2_SIZE =[ \t].*/SDRAM2_SIZE = 0/g' ../Project/Model/ModelConfig_EMU_EVB_528.txt + sed -i 's/^#define DEBUG_MSG[ \t].*/#define DEBUG_MSG (DISABLE)/g' ../Project/Model/Src/prj_main.h + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_528/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + sed -i 's/^[ \t]\/\/strg_obj->flash_setFrequency(96);*/strg_obj->flash_setFrequency(96);/g' ../Project/Model/Src/prj_main.c + make clean "MODEL=EMU_EVB" + make clean "MODEL=EMU_EVB_528" + make release "MODEL=EMU_EVB_528" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name LD*.bin -exec cp {} ../output \; + cp ../LibExt/LIBExt_src/Ctrl_Flow/bl_func_tmp.h ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + cp ../Project/Model/ModelConfig_EMU_EVB_528_tmp.txt ../Project/Model/ModelConfig_EMU_EVB_528.txt + cp ../Project/Model/ModelConfig_EMU_EVB_tmp.txt ../Project/Model/ModelConfig_EMU_EVB.txt + cp ../Project/Model/Src/prj_main_tmp.h ../Project/Model/Src/prj_main.h + #cp ../Project/Model/Loader528_Data/Release/LD98528A.bin ../output +} + +echo -e "Please select NMAKE environment:" +echo -e "1. make NT9852x standalone loader(MODEL = EMU_EVB)" +echo -e "2. make NT98528/NT98529 standalone loader(MODEL = EMU_EVB_528)" +echo -e "3. make NT9852x & NT98528 combination loader" +echo -e "4. make NT9852x Eth write loader(MODEL = EMU_EVB)" +echo -e "5. make NT98528/NT98529 Eth write loader(MODEL = EMU_EVB_528)" +echo -e "6. make NT9852x Usb write loader(MODEL = EMU_EVB)" +echo -e "7. make NT98528/NT98529 Usb write loader(MODEL = EMU_EVB_528)" +echo -e "-------------------------------------------------------" +echo -e "8. make NT9852x (tee) & NT98528 (tee) combination loader" +echo -e "-------------------------------------------------------" +echo -e "z. make NT9852x MT version loader(in house usage)" +echo -e "-------------------------------------------------------" +echo -e "s. make NT98528 for SQA fastboot test(internal usage)" +echo -e "-------------------------------------------------------" + + +read NMAKE_ENV +case ${NMAKE_ENV} in + "1") + make_NT98525_loader_only; + ;; + "2") + make_NT98528_loader_only; + ;; + "3") + make_NT9852x_combo_loader; + ;; + "4") + make_NT98525_eth_write_loader; + ;; + "5") + make_NT98528_eth_write_loader; + ;; + "6") + make_NT98525_usb_write_loader; + ;; + "7") + make_NT98528_usb_write_loader; + ;; + "8") + sed -i 's/^#define SDRAM_Start_FW[ \t].*/#define SDRAM_Start_FW 0x08000000/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make_NT9852x_combo_loader; + sed -i 's/^#define SDRAM_Start_FW[ \t].*/#define SDRAM_Start_FW 0x02000000/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + ;; + "z") + sed -i 's/^#define UITRON_FW[ \t].*/#define UITRON_FW ENABLE/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make_NT98525_loader_only; + sed -i 's/^#define UITRON_FW[ \t].*/#define UITRON_FW DISABLE/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + ;; + "s") + make_NT98528_sqa_fastboot_test_nand; + ;; + + *) + echo -e "exit" + ;; +esac + + + diff --git a/board/novatek/na51055/loader/Project/Model/LDS_LZ.lds b/board/novatek/na51055/loader/Project/Model/LDS_LZ.lds new file mode 100755 index 000000000000..8987f20ed14c --- /dev/null +++ b/board/novatek/na51055/loader/Project/Model/LDS_LZ.lds @@ -0,0 +1,168 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xF07C0000|0x00000000: + AT (0) + { + _load_BOOT_EXEC_start_base = .; + KEEP($LD_RESET_LIB/reset.o(.data*)); + $LD_RESET_LIB/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xF07C0000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP($LD_RESET_LIB/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + } + .LOADER_CONFIGRAM2 (0xF07C0000|0x00000000) + 0x300: + AT (0x300) + { + KEEP($LD_RESET_LIB/config_dram1_tbl.o(.rodata*)); + config_dram2_tbl_start_base = .; + KEEP($LD_RESET_LIB/config_dram2_tbl.o(.rodata*)); + config_dram1_tbl_2_start_base = .; + KEEP($LD_RESET_LIB/config_dram1_2_tbl.o(.rodata*)); + KEEP($LD_RESET_LIB/config_dram1_tbl2.o(.rodata*)); + KEEP($LD_RESET_LIB/config_dram2_tbl2.o(.rodata*)); + } + .LOADER_REMAP (0xF07C0000|0x00000000) + 0x630: + AT (0x630) + { + _load_vector_int_table_start_base = .; + KEEP($LD_RESET_LIB/isr.o(.text)); + _load_vector_int_table_end_base = .; + $LD_REMAP_LIB/$LD_DOREMAP.o(.text*); + _load_LOADER_REMAP_end_base = .; + _load_vector_exp_table_start_base = .; + KEEP($LD_RESET_LIB/exp.o(.text*)); + _load_vector_exp_table_end_base = .; + KEEP($LD_RESET_LIB/configDDR.o(.text*)); + KEEP($LD_RESET_LIB/configDDR.o(.rodata*)); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + + . = ALIGN(4); + .LOADER_EXEC ADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP) : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + KEEP(Driver/rtc.o(.part1*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .text $LD_BASE_ADDR: + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _loader_exec_compres_end = .; + } + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + } + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(8); /* This is MUST. Ensure ro size is 2 word aligned. */ + } + .dram_text : + AT (LOADADDR(.rodata) + SIZEOF(.rodata)) + { + _loader_dram_text_start_base = .; + * (.dram_text) + } + _loader_dram_text_cpu_addr = LOADADDR(.dram_text) + ADDR(.BOOT_EXEC); + _loader_dram_text_size = SIZEOF(.dram_text); + .data : + AT (LOADADDR(.dram_text) + SIZEOF(.dram_text)) + { + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + *(.data*) + _image_general_var_limit = .; + } + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got) } + . = ALIGN(4); + .bss : { /* locate bss at DRAM end */ + _image_general_zi_zi_base = .; + *(.bss) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + . = ALIGN(0x400); + _ttb_lv2 = .; + . = . + 0x400; + } + .common : + { + __common_base = ABSOLUTE(.); + /* collect "small" un-initialized global data (mark "C" in sym file) */ + *(.scommon*) + /* collect "large" un-initialized global data (mark "B" in sym file) */ + *(COMMON) + __common_limit = ABSOLUTE(.); + } + . = ALIGN(64); + _image_general_zi_zi_limit = ABSOLUTE(.); + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; + +} diff --git a/board/novatek/na51055/loader/Project/Model/LDS_LZ_528.lds b/board/novatek/na51055/loader/Project/Model/LDS_LZ_528.lds new file mode 100755 index 000000000000..4b73d7cdec53 --- /dev/null +++ b/board/novatek/na51055/loader/Project/Model/LDS_LZ_528.lds @@ -0,0 +1,193 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xF07C0000|0x00000000: + AT (0) + { + _load_BOOT_EXEC_start_base = .; + KEEP($LD_RESET_LIB/reset.o(.data*)); + $LD_RESET_LIB/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xF07C0000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP($LD_RESET_LIB/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + } + .LOADER_CONFIGRAM2 (0xF07C0000|0x00000000) + 0x300: + AT (0x300) + { + KEEP($LD_RESET_LIB/config_dram1_tbl.o(.rodata*)); + KEEP($LD_RESET_LIB/config_dram2_tbl.o(.rodata*)); + KEEP($LD_RESET_LIB/config_dram1_tbl2.o(.rodata*)); + KEEP($LD_RESET_LIB/config_dram2_tbl2.o(.rodata*)); + } + .LOADER_CORE2_ENTRY_PROGRAM (0xF07C0000|0x00000000) + 0x580: + AT (0x580) + { + _load_core2_jump_program_start_base = .; + KEEP($LD_RESET_LIB/core2_jump.o(.text)); + _load_core2_jump_program_end_base = .; + _load_core2_entry_program_start_base = .; + KEEP($LD_RESET_LIB/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + .LOADER_REMAP (0xF07C0000|0x00000000) + 0x750: + AT (0x750) + { + _load_vector_int_table_start_base = .; + _load_vector_int_table_end_base = .; + $LD_REMAP_LIB/$LD_DOREMAP.o(.text* .data*); + _load_LOADER_REMAP_end_base = .; + _load_vector_exp_table_start_base = .; + _load_vector_exp_table_end_base = .; + KEEP($LD_RESET_LIB/configDDR.o (.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/ddr_basic.o (.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/ddr_control.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/ddr_globals.o (.data*)); + KEEP($LD_RESET_LIB/ddr_io.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/clk_tree_k.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/zqk.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/dutyk.o (.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/qsen.o (.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/issue_cmd.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/phy_bist.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/psdk.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/read_eye.o (.text* .rodata* .data*)); + KEEP($LD_RESET_LIB/write_eye.o (.text* .rodata* .data*)); + KEEP($LD_RESET_LIB/write_leveling.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/register_673c.o(.text* .rodata* .data* .bss*)); + *libgcc.a:*(.text*); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + + . = ALIGN(4); + .LOADER_EXEC ADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP) : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + KEEP(Driver/rtc.o(.part1*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .LOADER_REMAP_BSS (0xF07D0000|0x00000000): + { + KEEP($LD_RESET_LIB/ddr_io.o(.bss*)); + KEEP($LD_RESET_LIB/write_eye.o(.bss*)); + } + .text $LD_BASE_ADDR: + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _loader_exec_compres_end = .; + } + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + } + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(8); /* This is MUST. Ensure ro size is 2 word aligned. */ + } + .dram_text : + AT (LOADADDR(.rodata) + SIZEOF(.rodata)) + { + _loader_dram_text_start_base = .; + * (.dram_text) + } + _loader_dram_text_cpu_addr = LOADADDR(.dram_text) + ADDR(.BOOT_EXEC); + _loader_dram_text_size = SIZEOF(.dram_text); + .data : + AT (LOADADDR(.dram_text) + SIZEOF(.dram_text)) + { + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + *(.data*) + _image_general_var_limit = .; + } + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got) } + . = ALIGN(4); + .bss : { /* locate bss at DRAM end */ + _image_general_zi_zi_base = .; + *(.bss) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + . = ALIGN(0x400); + _ttb_lv2 = .; + . = . + 0x400; + } + .common : + { + __common_base = ABSOLUTE(.); + /* collect "small" un-initialized global data (mark "C" in sym file) */ + *(.scommon*) + /* collect "large" un-initialized global data (mark "B" in sym file) */ + *(COMMON) + __common_limit = ABSOLUTE(.); + } + . = ALIGN(64); + _image_general_zi_zi_limit = ABSOLUTE(.); + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; + +} diff --git a/board/novatek/na51055/loader/Project/Model/LDS_NM.lds b/board/novatek/na51055/loader/Project/Model/LDS_NM.lds new file mode 100755 index 000000000000..586d5e9998ab --- /dev/null +++ b/board/novatek/na51055/loader/Project/Model/LDS_NM.lds @@ -0,0 +1,161 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xF07C0000|0x00000000: + AT (0) + { + _load_BOOT_EXEC_start_base = .; + KEEP(Reset/reset.o(.data*)); + Reset/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xF07C0000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP(Reset/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + KEEP(Reset/config_dram1_tbl.o(.rodata*)); + } + .LOADER_CONFIGRAM2 (0xF07C0000|0x00000000) + 0x200: + AT (0x200) + { + KEEP(Reset/config_dram2_tbl.o(.rodata*)); + } + .LOADER_CORE2_ENTRY_PROGRAM (0xF07C0000|0x00000000) + 0x300: + AT (0x300) + { + _load_core2_entry_program_start_base = .; + KEEP(Reset/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + .internal_stg_type (0xF07C0000|0x00000000) + 0x420: { LONG (0x46495053) } + .internal_stg_version : + AT (LOADADDR(.internal_stg_type) + SIZEOF(.internal_stg_type)) + { + _load_nand_table_start_base = .; + _load_nand_table_end_base = .; + } + .LOADER_REMAP (0xF07C0000|0x00000000) + 0x430: + AT (0x430) + { + _load_vector_int_table_start_base = .; + KEEP(Reset/isr.o(.text)); + _load_vector_int_table_end_base = .; + $LD_REMAP_LIB/$LD_DOREMAP.o(.text*); + _load_LOADER_REMAP_end_base = .; + _load_vector_exp_table_start_base = .; + KEEP(Reset/exp.o(.text*)); + _load_vector_exp_table_end_base = .; + KEEP(Reset/configDDR.o(.text*)); + KEEP(Reset/configDDR.o(.rodata*)); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + + . = ALIGN(4); + .LOADER_EXEC : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + KEEP(Driver/rtc.o(.part1*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .text : + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _loader_exec_compres_end = .; + } + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(4); /* This is MUST. Ensure ro size is word aligned. */ + } + .data 0xFF00000: + AT (LOADADDR(.rodata) + SIZEOF(.rodata)) + { + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + *(.data*) + _image_general_var_limit = .; + } + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got) } + . = ALIGN(4); + .bss : { /* locate bss at DRAM end */ + _image_general_zi_zi_base = .; + *(.bss) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + } + .common : + { + __common_base = ABSOLUTE(.); + /* collect "small" un-initialized global data (mark "C" in sym file) */ + *(.scommon*) + /* collect "large" un-initialized global data (mark "B" in sym file) */ + *(COMMON) + __common_limit = ABSOLUTE(.); + } + . = ALIGN(64); + _image_general_zi_zi_limit = ABSOLUTE(.); + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; + +} diff --git a/board/novatek/na51055/loader/Project/Model/MakeConfig.txt b/board/novatek/na51055/loader/Project/Model/MakeConfig.txt new file mode 100755 index 000000000000..2bc77654c792 --- /dev/null +++ b/board/novatek/na51055/loader/Project/Model/MakeConfig.txt @@ -0,0 +1,983 @@ +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +#------------------------------------------------------------------------------ +# Loader version : unsigned long loader version definition +#------------------------------------------------------------------------------ +LOADER_VERSION = 0x01000001 +BL_LOADER_VER_PARAM = \ + -D_LDR_VER_="$(LOADER_VERSION)" + +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +# +# Hardware device selection +# +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#------------------------------------------------------------------------------ +# Select main chip ID +#------------------------------------------------------------------------------ +#CHIP = 520 + +#------------------------------------------------------------------------------ +# Select chip version +#------------------------------------------------------------------------------ +#CHIP_VER = A +#CHIP_VER = B + +#------------------------------------------------------------------------------ +# Select LV1 clock rate +# LV1: 491MHz / 593MHz +#------------------------------------------------------------------------------ +#LV1_CLK = 491 +#LV1_CLK = 593 + +#------------------------------------------------------------------------------ +# Select DMA clock rate +#------------------------------------------------------------------------------ +#DMA_CLOCK = LV0 +#DMA_CLOCK = LV1 + +#ifeq "$(DMA_CLOCK)" "LV1" +#ifeq "$(LV1_CLK)" "491" +#DMA_CLOCK = LV1_4 +#else +#DMA_CLOCK = LV1_5 +#endif +#endif +ifeq "$(CHIP)" "525" +else +ifeq "$(NC520_525_COMBO)" "ON" +$(error NC520_525_COMBO only available while CHIP=525) +endif +endif + +ifeq "$(CHIP)" "528" +ifeq "$(52x_528_COMBO)" "ON" +$(error 52x_528_COMBO only available while CHIP!=528 && CHIP!=529 && CHIP!=580) +endif +else ifeq "$(CHIP)" "529" +ifeq "$(52x_528_COMBO)" "ON" +$(error 52x_528_COMBO only available while CHIP!=528 && CHIP!=529 && CHIP!=580) +endif +endif + + + +ifeq "$(CHIP)" "525" + +# DRAM1 external +# DRAM2 external + +ifeq "$(NC520_525_COMBO)" "ON" +else +NC520_COMBO_DRAM1_CLK = 0 +NC520_COMBO_SDRAM_SIZE = 0 +endif + +else ifeq "$(CHIP)" "523" + +DRAM1_CLK = 933 +DRAM1_2ND_CLK = 933 +# DRAM1 force @ 1Gb +SDRAM_SIZE = 1024 +SDRAM_2ND_SIZE = 1024 +# DRAM2 external + +else ifeq "$(CHIP)" "523_A" + +DRAM1_CLK = 933 +DRAM1_2ND_CLK = 933 +# DRAM1 force @ 1Gb +SDRAM_SIZE = 1024 +SDRAM_2ND_SIZE = 1024 +# DRAM2 external + +else ifeq "$(CHIP)" "522" + +DRAM1_CLK = 933 +DRAM1_2ND_CLK = 933 +# DRAM1 force @ 512Mb +SDRAM_SIZE = 512 +SDRAM_2ND_SIZE = 512 +# DRAM2 external + +else ifeq "$(CHIP)" "520" + +# DRAM1 external +DRAM2_CLK = 0 +SDRAM2_SIZE = 0 + +else ifeq "$(CHIP)" "NC520" +# DRAM1 external +DRAM2_CLK = 0 +SDRAM2_SIZE = 0 + +else ifeq "$(CHIP)" "575" + +DRAM1_CLK = 933 +DRAM1_2ND_CLK = 933 +SDRAM_SIZE = 1024 +SDRAM_2ND_SIZE = 1024 +# DRAM2 external + +else ifeq "$(CHIP)" "570" +# DRAM1 external +# DRAM2 external + +else ifeq "$(CHIP)" "528" +# DRAM1 external +# DRAM2 external + +else ifeq "$(CHIP)" "580" +# DRAM1 external +# DRAM2 external + +else ifeq "$(CHIP)" "529" +# DRAM1 external +# DRAM2 external + +else ifeq "$(CHIP)" "565" + +DRAM1_CLK = 933 +DRAM1_2ND_CLK = 933 +SDRAM_SIZE = 1024 +SDRAM_2ND_SIZE = 1024 +DRAM2_CLK = 0 +DRAM2_2ND_CLK = 0 +SDRAM2_SIZE = 0 +SDRAM2_2ND_SIZE = 0 + +else ifeq "$(CHIP)" "562" + +DRAM1_CLK = 666 +DRAM1_2ND_CLK = 666 +SDRAM_SIZE = 512 +SDRAM_2ND_SIZE = 512 +DRAM2_CLK = 0 +DRAM2_2ND_CLK = 0 +SDRAM2_SIZE = 0 +SDRAM2_2ND_SIZE = 0 +else +endif + +#------------------------------------------------------------------------------ +# Select DRAM Size (unit: Giga bit) +#------------------------------------------------------------------------------ +#SDRAM_SIZE = 1024 +#SDRAM_SIZE = 2048 +#SDRAM_SIZE = 4096 + +#------------------------------------------------------------------------------ +# Select DRAM Type (DDR3L curruently NOT available) +#------------------------------------------------------------------------------ +#DRAM_TYPE = DDR3 +#DRAM_TYPE = DDR3L + +#------------------------------------------------------------------------------ +# Select Phy analog block LV / HV +# (Don't modify this item) +#------------------------------------------------------------------------------ +PHY_ANALOG_HV = HV + +#------------------------------------------------------------------------------ +# CPU Core version configuration +# (Don't modify this item) +#------------------------------------------------------------------------------ +#CA53_ARCH32 +#CA9 +CPU_CORE = CA9 + +#------------------------------------------------------------------------------ +# Select internal storage device +#------------------------------------------------------------------------------ +#STORAGEINT = NandEccRS +#STORAGEINT = NandSpi +#STORAGEINT = SpiFlash + +#------------------------------------------------------------------------------ +# Select external storage device +#------------------------------------------------------------------------------ +#STORAGEEXT = Sdio1 +#STORAGEEXT = Sdio2 +#STORAGEEXT = Usb + +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +# +# Software function selection +# +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#------------------------------------------------------------------------------ +# Dram range scan loader support enable +# (Don't modify this item) +#------------------------------------------------------------------------------ +DRAM_RANGE_SCAN_SUPPORT_EN = ENABLE +#DRAM_RANGE_SCAN_SUPPORT_EN = DISABLE + +#------------------------------------------------------------------------------ +# Select GUI interface display or not +#------------------------------------------------------------------------------ +# [CONFIG_RAM_GUI_EN] +# ENABLE +# DISABLE +CONFIG_RAM_GUI_EN = DISABLE + +#------------------------------------------------------------------------------ +# Set binary file build name +#------------------------------------------------------------------------------ +CHIP_SHORT = $(shell echo $(CHIP)|awk '{print substr($$0,length($$0)-2,3)}') +ifeq "$(CHIP)" "575" +BIN_NAME = LD96575A +else ifeq "$(CHIP)" "570" +BIN_NAME = LD96570A +else ifeq "$(CHIP)" "580" +BIN_NAME = LD96580A +else ifeq "$(CHIP)" "565" +BIN_NAME = LD96565A +endif +ifeq "$(CHIP)" "523_A" +BIN_NAME = LD523_AA +endif +ifeq "$(STORAGEEXT)" "Eth" +LDR_NAME = loader +else +LDR_NAME = $(BIN_NAME) +endif +BL_UPDATE_CALNAME = FW96$(CHIP_SHORT)C.BIN +BL_CALIBRATION_FWNAME = CALFW680.BIN +TMP_NAME = LD96$(CHIP)1 + +#------------------------------------------------------------------------------ +# 1st NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_1st)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_1st_ = default_1 +else +ifeq "$(LOADER_SUPPORT_NAND_1st)" "" + _LOADER_NAND_SUPPORT_NAND_1st_ = default_1 +else + _LOADER_NAND_SUPPORT_NAND_1st_ = $(LOADER_SUPPORT_NAND_1st) +endif +endif +#------------------------------------------------------------------------------ +# 1st NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# 2nd NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_2nd)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_2nd_=default_2 +else +ifeq "$(LOADER_SUPPORT_NAND_2nd)" "" + _LOADER_NAND_SUPPORT_NAND_2nd_ = default_2 +else + _LOADER_NAND_SUPPORT_NAND_2nd_ = $(LOADER_SUPPORT_NAND_2nd) +endif +endif +#------------------------------------------------------------------------------ +# 2nd NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# 3rd NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_3rd)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_3rd_ = default_3 +else +ifeq "$(LOADER_SUPPORT_NAND_3rd)" "" + _LOADER_NAND_SUPPORT_NAND_3rd_ = default_3 +else + _LOADER_NAND_SUPPORT_NAND_3rd_ = $(LOADER_SUPPORT_NAND_3rd) +endif +endif + +#------------------------------------------------------------------------------ +# 3rd NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# Set bootloader specific strings +#------------------------------------------------------------------------------ +STR_MODEL = $(MODEL_DESC) +STR_DATE = $(shell date +%m/%d/%Y) +STR_TIME = $(shell date +%H:%M:%S) + +BL_START = "Loader NT98$(CHIP) Start ..." +BL_UPDATE_LOADERNAME = $(BIN_NAME).BIN +ifeq "$(CHIP)" "575" +BL_UPDATE_FWNAME := FW96575A.BIN +BL_UPDATE_CALNAME := FW96575C.BIN +BL_RUN_FWNAME := FW96575T.BIN +BL_CALIBRATION_FWNAME := CALFW575.BIN +BL_START = "Loader NT96$(CHIP) Start ..." +else ifeq "$(CHIP)" "570" +BL_UPDATE_FWNAME := FW96570A.BIN +BL_UPDATE_CALNAME := FW96570C.BIN +BL_RUN_FWNAME := FW96570T.BIN +BL_CALIBRATION_FWNAME := CALFW570.BIN +BL_START = "Loader NT96$(CHIP) Start ..." +else ifeq "$(CHIP)" "580" +BL_UPDATE_FWNAME := FW96580A.BIN +BL_UPDATE_CALNAME := FW96580C.BIN +BL_RUN_FWNAME := FW96580T.BIN +BL_CALIBRATION_FWNAME := CALFW580.BIN +BL_START = "Loader NT96$(CHIP) Start ..." +else ifeq "$(CHIP)" "565" +BL_UPDATE_FWNAME := FW96565A.BIN +BL_UPDATE_CALNAME := FW96565C.BIN +BL_RUN_FWNAME := FW96565T.BIN +BL_CALIBRATION_FWNAME := CALFW565.BIN +BL_START = "Loader NT96$(CHIP) Start ..." +endif +ifeq "$(CHIP)" "523_A" +BL_UPDATE_FWNAME := FW523_AA.BIN +BL_UPDATE_CALNAME := FW523_AC.BIN +BL_RUN_FWNAME := FW523_AT.BIN +BL_CALIBRATION_FWNAME := CALFW523.BIN +BL_START = "Loader NT98$(CHIP) Start ..." +endif + +BL_WRKEY_FWNAME := WRKEY.BIN +BL_UBOOT_FWNAME := UBOOTBIN.BIN + +ifeq "$(NC520_525_COMBO)" "ON" +MODEL_DESC = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE)Mb_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE)Mb_combo_NC520_DRAM1_$(NC520_COMBO_DRAM1_CLK)_$(NC520_COMBO_SDRAM_SIZE)Mb_DRAM2_NULL" +else + +ifneq "$(DRAM_2ND_TBL_DETECT)" "Normal" +ifeq "$(DRAM_ODT)" "Enabled" +MODEL_DESC2 = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_2ND_CLK)_$(SDRAM_2ND_SIZE)Mb_DRAM2_$(DRAM2_2ND_CLK)_$(SDRAM2_2ND_SIZE)Mb_ODT" +else +MODEL_DESC2 = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_2ND_CLK)_$(SDRAM_2ND_SIZE)Mb_DRAM2_$(DRAM2_2ND_CLK)_$(SDRAM2_2ND_SIZE)Mb" +endif +BL_VERSION2 = "$(MODEL_DESC2) $(STR_DATE) $(STR_TIME)" +endif + +ifeq "$(DRAM_ODT)" "Enabled" +MODEL_DESC = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE)Mb_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE)Mb_ODT" +else +MODEL_DESC = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE)Mb_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE)Mb" +endif +endif +BL_VERSION = "$(MODEL_DESC) $(STR_DATE) $(STR_TIME)" + +#------------------------------------------------------------------------------ +# Select bootloader compression +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [BL_COMPRESS] +# ENABLE +# DISABLE +BL_COMPRESS = ENABLE + +#Do not modify this parameter 0x08 if loader compress enabled +# [UNCOMPRESSEDPART_SIZE_OFFSET] +# 0x60 +# 0x08 +UNCOMPRESSEDPART_SIZE_OFFSET = 0x08 + +#------------------------------------------------------------------------------ +# Select compressable f/w (main code) +#------------------------------------------------------------------------------ +# [MAINCODE_COMPRESS] +# ENABLE +# DISABLE +MAINCODE_COMPRESS = DISABLE + +#------------------------------------------------------------------------------ +# Select firmware image checksum validation +#------------------------------------------------------------------------------ +# [CHKFWIMAGE] +# NOCHECK +# CHECKSUM +# CRC +CHKFWIMAGE = CHECKSUM + +#------------------------------------------------------------------------------ +# Select loader flow +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [LOADER_FLOW ] +# NORMAL_LDR_FLOW +# MODULE_TST_FLOW +LOADER_FLOW = NORMAL_LDR_FLOW + +ifeq "$(LOADER_FLOW)" "NORMAL_LDR_FLOW" +BL_LOADER_FLOW = 0 +else +BL_LOADER_FLOW = 1 +endif + +BL_LOADER_FLOW_PARAM = \ +-D_BL_MAIN_SPECIAL_FLOW_=$(BL_LOADER_FLOW) + +#------------------------------------------------------------------------------ +# OpenIPC: the NA51084 parts (528, 529) take the stand-alone 528 flow of +# bl_func.h, as the SDK's make_combo_loader.sh builds them; the others the +# stand-alone 52x one +#------------------------------------------------------------------------------ +ifneq "$(filter 528 529,$(CHIP))" "" +LOADER_TYPE_PARAM = -DLOADER_TYPE=STAND_ALONE_LOADER_528 +else +LOADER_TYPE_PARAM = -DLOADER_TYPE=STAND_ALONE_LOADER_52x +endif + +#------------------------------------------------------------------------------ +# Select Duty calibration ENABLE / DISABLE +#------------------------------------------------------------------------------ +DUTY_CALIBRATION = DISABLE + +#------------------------------------------------------------------------------ +# Select Duty calibration type +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [DUTY_CALIBRATION_TYPE ] +# AUTO +# MANUAL +DUTY_CALIBRATION_TYPE = AUTO + +ifeq "$(DUTY_CALIBRATION_TYPE)" "AUTO" +BL_DUTY_CALIBRATION_TYPE = 0 +else +BL_DUTY_CALIBRATION_TYPE = 1 +endif + +BL_DUTY_CALIBRATION_TYPE_PARAM = \ +-D_LOADER_DUTY_CALIBRATION_TYPE_=$(BL_DUTY_CALIBRATION_TYPE) + +#------------------------------------------------------------------------------ +# Select Duty calibration LOG ENABLE / DISABLE +#------------------------------------------------------------------------------ +# [DUTY_CALIBRATION_LOG] +# ENABLE +# DISABLE +DUTY_CALIBRATION_LOG = DISABLE + +ifeq "$(LOADER_FLOW)" "MODULE_TST_FLOW" +DUTY_CALIBRATION = DISABLE +endif + +ifeq "$(DUTY_CALIBRATION)" "DISABLE" +DUTY_CALIBRATION_LOG = DISABLE +else +ifeq "$(DUTY_CALIBRATION_TYPE)" "MANUAL" +DUTY_CALIBRATION_LOG = DISABLE +endif +endif + +ifeq "$(DUTY_CALIBRATION)" "ENABLE" +BL_DUTY_CALIBRATION = 1 +else +BL_DUTY_CALIBRATION = 0 +endif + +ifeq "$(DUTY_CALIBRATION_LOG)" "ENABLE" +BL_DUTY_CALIBRATION_LOG = 1 +else +BL_DUTY_CALIBRATION_LOG = 0 +endif + +BL_DUTY_CALIBRATION_PARAM = \ +-D_LOADER_DUTY_CALIBRATION_LOG_=$(BL_DUTY_CALIBRATION_LOG)\ +-D_LOADER_DUTY_CALIBRATION_=$(BL_DUTY_CALIBRATION) + + +#------------------------------------------------------------------------------ +# Bootloader update image file name parameters +#------------------------------------------------------------------------------ +BL_UPDATE_NAME_PARAM = \ + -D_UPDATE_FW_NAME_=\"$(BL_UPDATE_FWNAME)\" \ + -D_UPDATE_LOADER_NAME_=\"$(BL_UPDATE_LOADERNAME)\" \ + -D_RUN_FW_NAME_=\"$(BL_RUN_FWNAME)\" \ + -D_UPDATE_CALFW_NAME_=\"$(BL_UPDATE_CALNAME)\"\ + -D_RUN_CAL_FW_NAME_=\"$(BL_CALIBRATION_FWNAME)\" \ + -D_WR_KEY_FW_NAME_=\"$(BL_WRKEY_FWNAME)\" \ + -D_RUN_UBOOT_NAME_=\"$(BL_UBOOT_FWNAME)\" + + +#------------------------------------------------------------------------------ +# Bootloader specific strings parameters +#------------------------------------------------------------------------------ +BL_STRINGS_PARAM = \ +-D_LOADER_VERSION_STR_=\"\\\r\\\n$(BL_VERSION)\\\r\\\n\\\r\\\n\" \ +-D_LOADER_VERSION_STR2_=\"\\\r\\\n$(BL_VERSION2)\\\r\\\n\\\r\\\n\" \ +-D_LOADER_START_STR_=\"\\\r\\\n$(BL_START)\\\r\\\n\" + +#------------------------------------------------------------------------------ +# Bootloader compression parameters +#------------------------------------------------------------------------------ +ifeq "$(BL_COMPRESS)" "ENABLE" + BL_COMPRESS_CFG = 1 + ifeq "$(CHIP)" "52xES" + RESETFLAG = LZ52xES + else ifeq "$(CHIP)" "525" + RESETFLAG = LZ525 + else ifeq "$(CHIP)" "523" + RESETFLAG = LZ523 + else ifeq "$(CHIP)" "523_A" + RESETFLAG = LZ523_A + else ifeq "$(CHIP)" "575" + RESETFLAG = LZ575 + else ifeq "$(CHIP)" "570" + RESETFLAG = LZ570 + else ifeq "$(CHIP)" "522" + RESETFLAG = LZ522 + else ifeq "$(CHIP)" "520" + RESETFLAG = LZ520 + else ifeq "$(CHIP)" "528" + RESETFLAG = LZ528 + else ifeq "$(CHIP)" "529" + RESETFLAG = LZ529 + else ifeq "$(CHIP)" "580" + RESETFLAG = LZ580 + else ifeq "$(CHIP)" "NC520" + RESETFLAG = LZNC520 + else ifeq "$(CHIP)" "565" + RESETFLAG = LZ565 + else ifeq "$(CHIP)" "562" + RESETFLAG = LZ562 + else + RESETFLAG = LZ + endif + + ifeq "$(CHIP)" "528" + RESETCHIP = 528 + SCATTER_EXT= _528 + else ifeq "$(CHIP)" "580" + RESETCHIP = 528 + SCATTER_EXT= _528 + else ifeq "$(CHIP)" "529" + RESETCHIP = 528 + SCATTER_EXT= _528 + else + RESETCHIP = 52x + SCATTER_EXT= + endif + + ifeq "$(EXFAT_FILESYSTEM_SUPPORT)" "EXFAT" + COMMON_LIB = exFAT + else + COMMON_LIB = normal + endif + +else + BL_COMPRESS_CFG = 0 + ifeq "$(CHIP)" "525" + RESETFLAG = NM525 + else ifeq "$(CHIP)" "523" + RESETFLAG = NM523 + else ifeq "$(CHIP)" "522" + RESETFLAG = NM522 + else ifeq "$(CHIP)" "520" + RESETFLAG = NM520 + else + RESETFLAG = NM + endif + + ifeq "$(CHIP)" "528" + RESETCHIP = 528 + else ifeq "$(CHIP)" "580" + RESETCHIP = 580 + else ifeq "$(CHIP)" "529" + RESETCHIP = 529 + else + RESETCHIP = 52x + endif + + ifeq "$(EXFAT_FILESYSTEM_SUPPORT)" "EXFAT" + COMMON_LIB = exFAT + else + COMMON_LIB = normal + endif +endif + +ifeq "$(MAINCODE_COMPRESS)" "ENABLE" + FWCOMPRESS_PARAM = -D_MAINCODE_COMPRESS_=1 +else + FWCOMPRESS_PARAM = -D_MAINCODE_COMPRESS_=0 +endif + +BL_COMPRESS_PARAM = \ +-D_LOADER_COMPRESSED_=$(BL_COMPRESS_CFG) + +BL_COMPRESS_PARAM_ASM = +#\ +#-PD "_LOADER_COMPRESSED_ SETA $(BL_COMPRESS_CFG)" + +#------------------------------------------------------------------------------ +# Firmware image checksum validation parameters +#------------------------------------------------------------------------------ +ifeq "$(CHKFWIMAGE)" "NOCHECK" + CHKFWIMAGE_CFG = FW_CHECK_NOCHECK +endif + +ifeq "$(CHKFWIMAGE)" "CHECKSUM" + CHKFWIMAGE_CFG = FW_CHECK_CHECKSUM +endif + +ifeq "$(CHKFWIMAGE)" "CRC" + CHKFWIMAGE_CFG = FW_CHECK_CRC +endif + +CHKFWIMAGE_PARAM = \ + -DFW_CHECK_NOCHECK=0 \ + -DFW_CHECK_CHECKSUM=1 \ + -DFW_CHECK_CRC=2 \ + -DFW_CHECK_METHOD=$(CHKFWIMAGE_CFG) + +#------------------------------------------------------------------------------ +# External Storage define +#------------------------------------------------------------------------------ + +ifeq "$(STORAGEINT)" "EMMC_NAND_COMBO" +ifeq "$(STORAGEEXT)" "NONE" +else +$(error STORAGEEXT MUST = [NONE] if STORAGEINT= [EMMC_NAND_COMBO]=>Please check [ModelConfig_EMU_EVB.txt] configuration) +endif +endif + + +ifeq "$(STORAGEEXT)" "Sdio1" + STORAGE_EXT_TYPE = STORAGE_EXT_SDIO1 +else ifeq "$(STORAGEEXT)" "Sdio2" + STORAGE_EXT_TYPE = STORAGE_EXT_SDIO2 +else ifeq "$(STORAGEEXT)" "Usb" + STORAGE_EXT_TYPE = STORAGE_EXT_USB +else ifeq "$(STORAGEEXT)" "Eth" + STORAGE_EXT_TYPE = STORAGE_EXT_ETH +else ifeq "$(STORAGEEXT)" "NONE" + STORAGE_EXT_TYPE = STORAGE_EXT_NONE +else + STORAGE_EXT_TYPE = STORAGE_EXT_UNKOWN +endif + +EXTSTRG_PARAM = \ + -DSTORAGE_EXT_UNKOWN=0 \ + -DSTORAGE_EXT_SDIO1=1 \ + -DSTORAGE_EXT_SDIO2=2 \ + -DSTORAGE_EXT_USB=3 \ + -DSTORAGE_EXT_ETH=4 \ + -DSTORAGE_EXT_NONE=5\ + -DSTORAGE_EXT_TYPE=$(STORAGE_EXT_TYPE) + +ifeq "$(FAST_K)" "Enabled" + FAST_K_PARAM = 1 +else + FAST_K_PARAM = 0 +endif + +#------------------------------------------------------------------------------ +# SPI define +#------------------------------------------------------------------------------ +ifeq "$(STORAGEINT)" "SpiFlash" + STORAGE_INT_TYPE = -DSTORAGEINT_SPI=1 +else + STORAGE_INT_TYPE = +endif + +ifeq "$(SPI_SETTING)" "SPI_4BITS" + SPI_PINMUX = SPI_PINMUX_4BITS +endif + +ifeq "$(SPI_SETTING)" "SPI_NORMAL" + SPI_PINMUX = SPI_PINMUX_NORMAL +endif + +SPIPINMUX_PARAM = \ + -DSPI_PINMUX_NORMAL=0 \ + -DSPI_PINMUX_4BITS=1 \ + -DSPI_PINMUX_SETTING=$(SPI_PINMUX) + +#------------------------------------------------------------------------------ +# EMMC define +#------------------------------------------------------------------------------ +ifeq "$(EMMC_SETTING)" "EMMC_8BITS" + EMMC_PINMUX = EMMC_PINMUX_8BITS +endif + +ifeq "$(EMMC_SETTING)" "EMMC_NORMAL" + EMMC_PINMUX = EMMC_PINMUX_NORMAL +endif + +ifeq "$(EMMC_SETTING)" "" + EMMC_PINMUX = EMMC_PINMUX_8BITS +endif + +EMMCPINMUX_PARAM = \ + -DEMMC_PINMUX_NORMAL=0 \ + -DEMMC_PINMUX_8BITS=1 \ + -DEMMC_PINMUX_SETTING=$(EMMC_PINMUX) + +#------------------------------------------------------------------------------ +# Dram range scan support enable parameters +#------------------------------------------------------------------------------ +ifeq "$(DRAM_RANGE_SCAN_SUPPORT_EN)" "ENABLE" + DRAM_SCAN_EN = 1 +else + DRAM_SCAN_EN = 0 +endif + +DRAMSCAN_PARAM = -DDRAM_RANGE_SCAN_EN=$(DRAM_SCAN_EN) + +#------------------------------------------------------------------------------ +# Chip ID related parameters +#------------------------------------------------------------------------------ +ifeq "$(CHIP)" "528" +CHIPID = 528 +else ifeq "$(CHIP)" "580" +CHIPID = 528 +else ifeq "$(CHIP)" "529" +CHIPID = 528 +else +CHIPID = 520 +endif +#------------------------------------------------------------------------------ +# Secure boot parameters +#------------------------------------------------------------------------------ +ifeq "$(SECUREBOOT)" "Secure" +SECUREBOOT_MSG = 0 +ifeq "$(SIGNATUREMETHOD)" "AES128" +#Secure enable + AES signature +SECURE_BOOT = 1 +else +#Secure enable + RSA signature +SECURE_BOOT = 2 +endif +ifeq "$(ENCRYPTDATA)" "AES128" +ENCRYPT_DATA = 1 +else +ENCRYPT_DATA = 0 +endif +else +SECURE_BOOT = 0 +endif + + + +#------------------------------------------------------------------------------ +# DRAM ini file name generation +#------------------------------------------------------------------------------ +#ifeq "$(DRAM_TYPE)" "DDR3L" +# ifeq "$(DMA_CLOCK)" "LV0" +# $(error DDR3L only support DMA_CLOCK = LV1) +# endif +# ifeq "$(LV1_CLK)" "373" +# $(error DDR3L only support LV1_CLK = 400) +# endif +# DDR_FILE_STR = _DDR3L +#else +# DDR_FILE_STR = +#endif + +ifeq "$(DMA_CLOCK)" "LV0" + +DDR_INI_STR = $(CHIP)/51055A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE).ini +DDR_INI2_STR = $(CHIP)/51055A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE).ini +#DDR_INI_STR = 680_$(CHIP_VER)_LV0_$(SDRAM_SIZE).ini +ifeq "$(LV1_CLK)" "491" +#DDR_INI2_STR = 680_$(CHIP_VER)_LV1_4_$(SDRAM_SIZE).ini +else +#DDR_INI2_STR = 680_$(CHIP_VER)_LV1_5_$(SDRAM_SIZE).ini +endif + +else + +ifneq "$(DRAM_2ND_TBL_DETECT)" "Normal" + +ifeq "$(DRAM_ODT)" "Enabled" +DDR_INI_STR = $(CHIP)/51055A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE)_ODT.ini +DDR_INI2_STR = $(CHIP)/51055A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE)_ODT.ini + +DDR_INI_STR2 = $(CHIP)/51055A_DRAM1_$(DRAM1_2ND_CLK)_$(SDRAM_2ND_SIZE)_ODT.ini +DDR_INI2_STR2 = $(CHIP)/51055A_DRAM2_$(DRAM2_2ND_CLK)_$(SDRAM2_2ND_SIZE)_ODT.ini + +else +DDR_INI_STR = $(CHIP)/51055A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE).ini +DDR_INI2_STR = $(CHIP)/51055A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE).ini + +DDR_INI_STR2 = $(CHIP)/51055A_DRAM1_$(DRAM1_2ND_CLK)_$(SDRAM_2ND_SIZE).ini +DDR_INI2_STR2 = $(CHIP)/51055A_DRAM2_$(DRAM2_2ND_CLK)_$(SDRAM2_2ND_SIZE).ini +endif + +2ND_INI = $(DRAM_2ND_TBL_DETECT) +GPIO_NUM = $(DRAM_2ND_TBL_DETECT_GPIO_NO) + +else + +ifeq "$(DRAM_ODT)" "Enabled" +DDR_INI_STR = $(CHIP)/51055A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE)_ODT.ini +DDR_INI2_STR = $(CHIP)/51055A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE)_ODT.ini +else +DDR_INI_STR = $(CHIP)/51055A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE).ini +DDR_INI2_STR = $(CHIP)/51055A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE).ini +endif + +DDR_INI_STR2 = "" +DDR_INI2_STR2 = "" + +2ND_INI = "" +GPIO_NUM = 0 + +#DDR_INI_STR = 680_$(CHIP_VER)_$(DMA_CLOCK)_$(SDRAM_SIZE).ini +#DDR_INI2_STR = 680_$(CHIP_VER)_LV0_$(SDRAM_SIZE).ini +endif + +ifeq "$(NC520_525_COMBO)" "ON" +DDR_INI_STR_NC520_525_COMBO = NC520/51055A_DRAM1_$(NC520_COMBO_DRAM1_CLK)_$(NC520_COMBO_SDRAM_SIZE).ini +endif +endif + +ifeq "$(DRAM1_POWEROFF_S3)" "Enabled" +DRAM1_RST_PARAM = 1 +else +DRAM1_RST_PARAM = 0 +endif + +ifeq "$(DRAM_NUMBER_DETECT)" "Enabled" +DRAM_NUMBER_DET_PARAM = 1 +else +DRAM_NUMBER_DET_PARAM = 0 +endif + +ifeq "$(DRAM_SSC_ENABLE)" "Normal" +DRAM_SSC_PARAM = 0 +else ifeq "$(DRAM_SSC_ENABLE)" "1" +DRAM_SSC_PARAM = 1 +else ifeq "$(DRAM_SSC_ENABLE)" "2" +DRAM_SSC_PARAM = 2 +else ifeq "$(DRAM_SSC_ENABLE)" "3" +DRAM_SSC_PARAM = 3 +else ifeq "$(DRAM_SSC_ENABLE)" "4" +DRAM_SSC_PARAM = 4 +else ifeq "$(DRAM_SSC_ENABLE)" "5" +DRAM_SSC_PARAM = 5 +else +DRAM_SSC_PARAM = 0 +endif + +#------------------------------------------------------------------------------- +# set the scatter file name here +#------------------------------------------------------------------------------- +ifeq "$(BL_COMPRESS)" "ENABLE" +SCATTER = LDS_LZ$(SCATTER_EXT).lds +else +SCATTER = LDS_NM.lds +endif + +#------------------------------------------------------------------------------- +# set loader execution DRAM address +#------------------------------------------------------------------------------- +# 255MB +ifeq "$(SDRAM_SIZE)" "1024" +LD_BASE_ADDR = 0x7C00000 +else ifeq "$(SDRAM_SIZE)" "2048" +LD_BASE_ADDR = 0xFC00000 +else +LD_BASE_ADDR = 0xFC00000 +endif +BL_LDADDR_PARAM = \ +-DLD_BASE_ADDR=$(LD_BASE_ADDR) + +#------------------------------------------------------------------------------- +# set loader internal storage type +#------------------------------------------------------------------------------- +BL_STORAGEINT_PARAM = \ +-D_STORAGEINT_$(STORAGEINT)_ + +#------------------------------------------------------------------------------- +# Model parameters +#------------------------------------------------------------------------------- +ifeq "$(MODEL)" "EMU_EVB" + MODEL_TYPE = _MODEL_EMU_EVB_ +endif + +ifeq "$(MODEL)" "DEMO1_EVB" + MODEL_TYPE = _MODEL_DEMO1_EVB_ +endif + +ifeq "$(MODEL)" "ARTOSYN_EVB" + MODEL_TYPE = _MODEL_ARTOSYN_EVB_ +endif +MODEL_PARAM = \ + -D_MODEL_EMU_EVB_=0 \ + -D_MODEL_DEMO1_EVB_=1 \ + -D_MODEL_ARTOSYN_EVB_=2 \ + -D_MODEL_DSC_=$(MODEL_TYPE) + +#------------------------------------------------------------------------------- +# uboot encrypt binary or not parameters +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT_DECRYPT_UBOOT)" "Normal" + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_DISABLE_ +else ifeq "$(SECUREBOOT_DECRYPT_UBOOT)" "Secure" + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_ENABLE_ +else + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_DISABLE_ +endif + +SECURE_DECRYPT_UBOOT_PARAM = \ + -D_SECURE_DECRYPT_UBOOT_DISABLE_=0 \ + -D_SECURE_DECRYPT_UBOOT_ENABLE_=1 \ + -DSECURE_DECRYPT_UBOOT=$(UBOOT_DECRYPT_TYPE) + +#------------------------------------------------------------------------------- +# optee parameters +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT_DECRYPT_OPTEE)" "Normal" + OPTEE_DECRYPT_TYPE = _SECURE_DECRYPT_OPTEE_DISABLE_ +else ifeq "$(SECUREBOOT_DECRYPT_OPTEE)" "Secure" + OPTEE_DECRYPT_TYPE = _SECURE_DECRYPT_OPTEE_ENABLE_ +else + OPTEE_DECRYPT_TYPE = _SECURE_DECRYPT_OPTEE_DISABLE_ +endif + + +SECURE_DECRYPT_OPTEE_PARAM = \ + -D_SECURE_DECRYPT_OPTEE_DISABLE_=0 \ + -D_SECURE_DECRYPT_OPTEE_ENABLE_=1 \ + -DSECURE_DECRYPT_OPTEE_OS=$(OPTEE_DECRYPT_TYPE) + + +#------------------------------------------------------------------------------- +# optee or uboot digital signature parameters +#------------------------------------------------------------------------------- +ifeq "$(SIGNATUREMETHOD)" "AES128" +# => AES signature +OPTEE_UBOOT_DIGITAL_SIGNATURE_TYPE = _UBOOT_OPTEE_SIGNATURE_USE_AES128_ +else +# => RSA signature +OPTEE_UBOOT_DIGITAL_SIGNATURE_TYPE = _UBOOT_OPTEE_SIGNATURE_USE_RSA_ +endif + +OPTEE_UBOOT_SIGNATURE_PARAM = \ + -D_UBOOT_OPTEE_SIGNATURE_USE_RSA_=0 \ + -D_UBOOT_OPTEE_SIGNATURE_USE_AES128_=1 \ + -DSECURE_SIGNATURE_BY_AES=$(OPTEE_UBOOT_DIGITAL_SIGNATURE_TYPE) + + +#------------------------------------------------------------------------------- +# optee or uboot digital signature parameters +#------------------------------------------------------------------------------- +ifeq "$(CHIP)" "565" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_1_ +else ifeq "$(CHIP)" "562" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_2_ +else +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_0_ +endif + +CARDDET_PIN_PARAM = \ + -D_CARD_DETECT_TYPE_0_=0 \ + -D_CARD_DETECT_TYPE_1_=1 \ + -D_CARD_DETECT_TYPE_2_=2 \ + -DCARD_DETECT_PIN=$(CARD_DETECT_PIN_TYPE) + +ifeq "$(DDR_TREFI)" "Extend" +DDR_TREFI_PARAM = 1 +else +DDR_TREFI_PARAM = 0 +endif diff --git a/board/novatek/na51055/loader/Project/Model/Makefile b/board/novatek/na51055/loader/Project/Model/Makefile new file mode 100755 index 000000000000..594475b03a7c --- /dev/null +++ b/board/novatek/na51055/loader/Project/Model/Makefile @@ -0,0 +1,129 @@ +#---------------------------------------------------------------------- +# set the ROOT directory here +#---------------------------------------------------------------------- +ROOT_DIR = ../.. + +#---------------------------------------------------------------------- +# include make config file +#---------------------------------------------------------------------- +include ModelConfig.txt +include ModelConfig_$(MODEL).txt +include MakeConfig.txt + +#---------------------------------------------------------------------- +# set the project name here +#---------------------------------------------------------------------- +PRJ_NAME = Loader$(CHIP) + +#---------------------------------------------------------------------- +# set loader execution DRAM address +#---------------------------------------------------------------------- +ifeq "$(SDRAM_SIZE)" "1024" +# 1Gb*2 => 256MB => 0x1000_0000 +LD_BASE_ADDR = 0xF000000 +else ifeq "$(SDRAM_SIZE)" "2048" +# 2Gb*2 => 512MB => 0x2000_0000 +LD_BASE_ADDR = 0x1F000000 +else +# 4Gb*2 => 1024MB => 0x4000_0000 +LD_BASE_ADDR = 0x3F000000 +endif + +ifeq "$(LOADER_DRAM_ADDR)" "" +LD_BASE_ADDR = 0x1000000 +else +LD_BASE_ADDR = $(LOADER_DRAM_ADDR) +endif + +#---------------------------------------------------------------------- +# set the include directory here +#---------------------------------------------------------------------- +INC_DIR = . \ + ../../Include + +#---------------------------------------------------------------------- +# add/delete the project assembly files here +#---------------------------------------------------------------------- +#ASM = Src/reset.S \ +#Src/remap.S + + + + +#---------------------------------------------------------------------- +# add/delete the project C source files here +#---------------------------------------------------------------------- +SRC = \ + Src/prj_main.c + + + + +#---------------------------------------------------------------------- +# set the image output directory here +#---------------------------------------------------------------------- +IMG_BASE_DIR = $(PRJ_NAME)_Data + +#---------------------------------------------------------------------- +# set the library directory here +#---------------------------------------------------------------------- +LIB_BASE_DIR = ../../LIB + +#---------------------------------------------------------------------- +# set the library directory here +#---------------------------------------------------------------------- +ARC_BASE_DIR = $(ROOT_DIR)/ARC + +#---------------------------------------------------------------------- +# add additional C and assembly flags here, for example, -O2 +#---------------------------------------------------------------------- +C_DEFINE_EXT = \ + $(MODEL_PARAM) \ + $(BL_UPDATE_NAME_PARAM) \ + $(BL_STRINGS_PARAM) \ + $(BL_COMPRESS_PARAM) \ + $(CHKFWIMAGE_PARAM) \ + $(FWCOMPRESS_PARAM) \ + $(BL_LOADER_VER_PARAM) \ + $(BL_LDADDR_PARAM) \ + $(EXTSTRG_PARAM) \ + $(STORAGE_INT_TYPE)\ + $(SPIPINMUX_PARAM)\ + $(EMMCPINMUX_PARAM)\ + $(DRAMSCAN_PARAM)\ + $(BL_DUTY_CALIBRATION_PARAM)\ + $(BL_DUTY_CALIBRATION_TYPE_PARAM)\ + $(BL_LOADER_FLOW_PARAM) \ + $(BL_STORAGEINT_PARAM) \ + $(SECURE_DECRYPT_UBOOT_PARAM) \ + $(SECURE_DECRYPT_OPTEE_PARAM) \ + $(CARDDET_PIN_PARAM) + +CFLAGS_R = $(C_DEFINE_EXT) +CFLAGS_D = $(C_DEFINE_EXT) + +ASMFLAGS_R = \ + $(BL_COMPRESS_PARAM_ASM) + +ASMFLAGS_D = \ + $(BL_COMPRESS_PARAM_ASM) + +GCCFLAGS = \ + $(MODEL_PARAM) \ + $(BL_UPDATE_NAME_PARAM) \ + $(BL_STRINGS_PARAM) \ + $(BL_COMPRESS_PARAM) \ + $(CHKFWIMAGE_PARAM) \ + $(FWCOMPRESS_PARAM) \ + $(BL_LOADER_VER_PARAM) \ + $(STORAGE_INT_TYPE)\ + $(DRAMSCAN_PARAM)\ + $(BL_DUTY_CALIBRATION_PARAM)\ + $(BL_DUTY_CALIBRATION_TYPE_PARAM)\ + $(BL_LOADER_FLOW_PARAM) + +#---------------------------------------------------------------------- +# include common parts of the makefile +#---------------------------------------------------------------------- +MAKE_COMMON_DIR = ../../MakeCommon +include $(MAKE_COMMON_DIR)/OutputImg.txt diff --git a/board/novatek/na51055/loader/Project/Model/ModelConfig.txt b/board/novatek/na51055/loader/Project/Model/ModelConfig.txt new file mode 100755 index 000000000000..91c381c06d11 --- /dev/null +++ b/board/novatek/na51055/loader/Project/Model/ModelConfig.txt @@ -0,0 +1,6 @@ +#---------------------------------------------------------------------- +# Set model here +#---------------------------------------------------------------------- +# EMU_EVB => Model config as NT9852x +# EMU_EVB_528 => Model config as NT98528 +MODEL = EMU_EVB \ No newline at end of file diff --git a/board/novatek/na51055/loader/Project/Model/ModelConfig_EMU_EVB.txt b/board/novatek/na51055/loader/Project/Model/ModelConfig_EMU_EVB.txt new file mode 100755 index 000000000000..d1946f9025c8 --- /dev/null +++ b/board/novatek/na51055/loader/Project/Model/ModelConfig_EMU_EVB.txt @@ -0,0 +1,255 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN + +# Ext => DRAM is external die => Need user configuration +# KGD => DRAM is internal die => Depend on specific chip (force fixed dram size) +#===========+================+==================+ +# chip_name | DDR1 size | DDR2 size | +#===========+===============+===================+ +# 520 | 1/2/4Gb(Ext)| N/A | +#===========+===============+===================+ +# 522 | 512Mb(KGD) | 1/2/4Gb(Ext) | +#===========+===============+===================+ +# 523 | 1Gb(KGD) | 1/2/4Gb(Ext) | +#===========+===============+===================+ +# 575 | 1Gb(KGD) | 1/2/4Gb(Ext) | +#===========+===============+===================+ +# 525 | 1/2/4Gb(Ext)| 1/2/4Gb(Ext) | +#===========+===============+===================+ +# 565 | 1Gb(KGD) | N/A | +#===========+===============+===================+ +# [CHIP] : main chip ID +# 525 +# 523 +# 523_A +# 522 +# 520 +# NC520 +# 575 +# 570 +# 565 +# 562 + +CHIP = 525 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1(16-bit) clock rate +# 700 +# 793 +# 933 +DRAM1_CLK = 933 + +# [DRAM2_CLK] : DRAM2(16-bit) clock rate (must <= DRAM1_CLK) +# 793 +# 933 +DRAM2_CLK = 933 + +# [DMA_CLOCK] : DMA clock rate +# LV0 +# LV1 +#DMA_CLOCK = LV1 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +SDRAM2_SIZE = 4096 + +# [NT525 combo NC520] : Once CHIP = 520 can choose combo NC520 +# OFF +# ON +NC520_525_COMBO = OFF + +# [NC520_COMBO_DRAM1_CLK] : DRAM1(16-bit) clock rate +# 700 +# 793 +# 933 +NC520_COMBO_DRAM1_CLK = 933 + +# [2ND_525_SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +NC520_COMBO_SDRAM_SIZE = 4096 + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Normal + +# [DRAM_NUMBER_DETECT] : enable DRAM number detect by L_GPIO3 +# Normal +# Enabled +DRAM_NUMBER_DETECT = Normal + +# [DRAM_ODT] : enable DRAM ODT +# Disabled +# Enabled +DRAM_ODT = Disabled + +# [9852x combo 98528] : Once CHIP = 52x can choose combo 98528 +# OFF +# ON +52x_528_COMBO = OFF + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +DRAM_TYPE = DDR3 + +# [DDR_TREFI] : ddr refresh time select by temparature range +# Normal(0~85) +# Extend(85~95) +DDR_TREFI = Normal + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO (default: P_GPIO13) +# Normal (No GPIO detected) +# 0 (C_GPIO) +# 1 (P_GPIO) +# 2 (S_GPIO) +# 3 (L_GPIO) +# 4 (D_GPIO) +# 5 (HSI_GPI) +# 6 (ADC_GPIO) +# 7 (Reserved) +DRAM_2ND_TBL_DETECT = Normal + +# [DRAM_2ND_TBL_DETECT_GPIO_NO] : enable DRAM 2nd table detect by X_GPIO_n +# where +# C_GPIO --> n=0~22 +# P_GPIO --> n=0~25 +# S_GPIO --> n=0~12 +# L_GPIO --> n=0~24 +# D_GPIO --> n=0~10 +# HSI_GPI --> n=0~11 +# ADC_GPIO --> n=0~2 +DRAM_2ND_TBL_DETECT_GPIO_NO = 13 + +# [DRAM1_2ND_CLK] : DRAM1(16-bit) 2nd table clock rate +# 700 +# 793 +# 933 +DRAM1_2ND_CLK = 793 + +# [DRAM2_2ND_CLK] : DRAM2(16-bit) 2nd table clock rate (must <= DRAM1_CLK) +# 793 +# 933 +DRAM2_2ND_CLK = 793 + +# [SDRAM_2ND_SIZE] : 2nd table DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +SDRAM_2ND_SIZE = 4096 + +# [SDRAM2_2ND_SIZE] : 2nd table DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +SDRAM2_2ND_SIZE = 4096 + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +# EMMC +# EMMC_NAND_COMBO >>>[eMMC & NandSpi 2 in 1 & STORAGEEXT must choose NONE]<<< +STORAGEINT = SpiFlash + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth >>>[During this option => STORAGEINT MUST not choose @EMMC_NAND_COMBO]<<< +STORAGEEXT = Sdio1 + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = AES128 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal + +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x1000000 +LOADER_DRAM_ADDR = 0x1000000 + +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader decrypt optee option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_OPTEE] : Loader decrypt optee or not (Depend on optee build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_OPTEE = Normal + +#==============================================================================# +# exFAT support(Once customer want to use exFAT, need get license from $MS ) # +#==============================================================================# +# [exFAT] : Loader support exFAT or not +# NONE +# EXFAT +EXFAT_FILESYSTEM_SUPPORT = NONE + + diff --git a/board/novatek/na51055/loader/Project/Model/ModelConfig_EMU_EVB_528.txt b/board/novatek/na51055/loader/Project/Model/ModelConfig_EMU_EVB_528.txt new file mode 100755 index 000000000000..8d8ec629539a --- /dev/null +++ b/board/novatek/na51055/loader/Project/Model/ModelConfig_EMU_EVB_528.txt @@ -0,0 +1,236 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN + +# Ext => DRAM is external die => Need user configuration +# KGD => DRAM is internal die => Depend on specific chip (force fixed dram size) +#===========+================+==================+ +# chip_name | DDR1 size | DDR2 size | +#===========+===============+===================+ +# 528 | 1/2/4Gb(Ext)| 1/2/4Gb(Ext) | +#===========+===============+===================+ +# 529 | 1/2/4Gb(Ext)| 1/2/4Gb(Ext) | +#===========+===============+===================+ +# [CHIP] : main chip ID + +# 528 +# 580 +# 529 +CHIP = 528 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1(16-bit) clock rate +# 700 +# 793 +# 933 +# 1066 +DRAM1_CLK = 1066 + +# [DRAM2_CLK] : DRAM2(16-bit) clock rate (must <= DRAM1_CLK) +# 793 +# 933 +# 1066 +DRAM2_CLK = 1066 + +# [DMA_CLOCK] : DMA clock rate +# LV0 +# LV1 +#DMA_CLOCK = LV1 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +SDRAM2_SIZE = 4096 + +NC520_525_COMBO = OFF + +# [NC520_COMBO_DRAM1_CLK] : DRAM1(16-bit) clock rate +# 700 +# 793 +# 933 +NC520_COMBO_DRAM1_CLK = 933 + +# [2ND_525_SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +NC520_COMBO_SDRAM_SIZE = 4096 + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Normal + +# [DRAM_NUMBER_DETECT] : enable DRAM number detect by L_GPIO3 +# Normal +# Enabled +DRAM_NUMBER_DETECT = Normal + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +DRAM_TYPE = DDR3 + +# [DDR_TREFI] : ddr refresh time select by temparature range +# Normal(0~85) +# Extend(85~95) +DDR_TREFI = Normal + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO (default: P_GPIO13) +# Normal (No GPIO detected) +# 0 (C_GPIO) +# 1 (P_GPIO) +# 2 (S_GPIO) +# 3 (L_GPIO) +# 4 (D_GPIO) +# 5 (HSI_GPI) +# 6 (ADC_GPIO) +# 7 (Reserved) +DRAM_2ND_TBL_DETECT = Normal + +# [DRAM_2ND_TBL_DETECT_GPIO_NO] : enable DRAM 2nd table detect by X_GPIO_n +# where +# C_GPIO --> n=0~22 +# P_GPIO --> n=0~25 +# S_GPIO --> n=0~12 +# L_GPIO --> n=0~24 +# D_GPIO --> n=0~21 +# HSI_GPI --> n=0~11 +# ADC_GPIO --> n=0~2 +DRAM_2ND_TBL_DETECT_GPIO_NO = 13 + +# [DRAM1_2ND_CLK] : DRAM1(16-bit) 2nd table clock rate +# 700 +# 793 +# 933 +# 1066 +DRAM1_2ND_CLK = 933 + +# [DRAM2_2ND_CLK] : DRAM2(16-bit) 2nd table clock rate (must <= DRAM1_CLK) +# 793 +# 933 +# 1066 +DRAM2_2ND_CLK = 933 + +# [SDRAM_2ND_SIZE] : 2nd table DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +SDRAM_2ND_SIZE = 4096 + +# [SDRAM2_2ND_SIZE] : 2nd table DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +SDRAM2_2ND_SIZE = 4096 + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +# EMMC +# EMMC_NAND_COMBO >>>[eMMC & NandSpi 2 in 1 & STORAGEEXT must choose NONE]<<< +STORAGEINT = SpiFlash + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth >>>[During this option => STORAGEINT MUST not choose @EMMC_NAND_COMBO]<<< +STORAGEEXT = Sdio1 + +# [FAST_K] : enable fast k to shrink boot time +# Normal +# Enabled +FAST_K = Normal + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = AES128 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal + +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x1000000 +LOADER_DRAM_ADDR = 0x1000000 + +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader decrypt optee option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_OPTEE] : Loader decrypt optee or not (Depend on optee build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_OPTEE = Normal + +#==============================================================================# +# exFAT support(Once customer want to use exFAT, need get license from $MS ) # +#==============================================================================# +# [exFAT] : Loader support exFAT or not +# NONE +# EXFAT +EXFAT_FILESYSTEM_SUPPORT = NONE + + diff --git a/board/novatek/na51055/loader/Project/Model/Src/prj_main.c b/board/novatek/na51055/loader/Project/Model/Src/prj_main.c new file mode 100755 index 000000000000..8224de511bfd --- /dev/null +++ b/board/novatek/na51055/loader/Project/Model/Src/prj_main.c @@ -0,0 +1,207 @@ +/* + Project layer Main control function + + This file is implement by user mode + + @file prj_main.c + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ + +#include "fuart.h" +#include "fat.h" +#include "rtc.h" +#include "timer.h" +#include "StorageDef.h" +#include "global.h" +#include "Clock.h" +#include "string.h" +#include "prj_main.h" +#include "debug.h" + +#define _THUMB2 __attribute__((target("thumb"))) + +#if defined(_STORAGEINT_EMMC_NAND_COMBO_) +#if (CHECK_CARD_EXIST == ENABLE) +#undef CHECK_CARD_EXIST +#define CHECK_CARD_EXIST DISABLE +#endif + +#endif + +extern UINT32 LoaderInternalInfo[]; + +#if (DEBUG_MSG == DISABLE) +//weak function mechanism for debug msg output +extern void debug_disable_msg(void); +void debug_disable_msg(void) {} +#endif + +#if (SPECIAL_KEY_UPDATE == ENABLE) +/** + Check special key1(s) is(are) pressed. + + Check special key1(s) is(are) pressed or not. + + @return Key pressed status + - @b TRUE: Special key(s) is(are) pressed + - @b FALSE: Otherwise +*/ +static BOOL prj_isSpecialKeyPressed(void) +{ + // Detect key example, must press shutter2 and playback mode keys + // OUT_0: DGPIO 0 + // OUT_1: DGPIO 14 + // OUT_2: DGPIO 2 + // OUT_3: DGPIO 3 + // OUT_4: DGPIO 4 + // IN_0 : DGPIO 5 + // IN_1 : DGPIO 6 + // IN_2 : DGPIO 7 + // IN_3 : DGPIO 8 + // KEY_IN_0 KEY_IN_1 KEY_IN_2 KEY_IN_3 + // KEY_OUT_0 MENU SET PLAYBACK DISPLAY + // KEY_OUT_1 WIDE LEFT MOVIE + // KEY_OUT_2 TELE DOWN TRASH + // KEY_OUT_3 SHUTTER2 RIGHT CAPTURE + // KEY_OUT_4 SHUTTER1 UP + // Add the necessary code.. + return TRUE; +} +#endif + +#if (CHECK_CARD_EXIST == ENABLE) +// MC16 default is config as input and pull up +_THUMB2 static BOOL prj_checkCardExist(void) +{ +#if (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + return TRUE; // force ethernet probe DHCP server +#else + return (gpio_getPin(DGPIO_CARD_DETECT) == 0 ? TRUE : FALSE); +#endif +} +#endif + +#if 0 +static BOOL bl_spiIdentify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + // Sample to support SST25VF032 + if ((uiMfgID == 0xBF) && + (uiCapacityID == 0x4A)) { + pIdentify->bDualRead = FALSE; + pIdentify->bSupportAAI = TRUE; + pIdentify->bSupportEWSR = TRUE; + pIdentify->uiFlashSize = 4 * 1024 * 1024; + return TRUE; + } + + return FALSE; +} + +static void bl_flashLED(void) +{ + // use GPIO to control LED +} +#endif + +// main entry of project layer code +_THUMB2 void prj_main(void) +{ + PSTORAGE_OBJ strg_obj = NULL; + loader_setVersion(_LDR_VER_); + + debug_msg("\r\n"); + debug_msg("LD_VER "); + debug_msg(Dec2HexStr2Bytes((LoaderInternalInfo[1] >> 28) & 0xF)); + debug_msg("."); + debug_msg(Dec2HexStr2Bytes((LoaderInternalInfo[1] >> 24) & 0xF)); + debug_msg("."); + debug_msg(Dec2HexStr2Bytes((LoaderInternalInfo[1] >> 16) & 0xFF)); + debug_msg("\r\n"); + + // Print project layer info + if((LoaderInternalInfo[6] & 0x100000) == 0x100000) { + if(gpio_getPin((((LoaderInternalInfo[6]>>12)&0x7)*32) + ((LoaderInternalInfo[6]>>15)&0x1f))) { + debug_msg(_LOADER_VERSION_STR2_); + } else { + debug_msg(_LOADER_VERSION_STR_); + } + } else { + debug_msg(_LOADER_VERSION_STR_); + } + + // Setup loader/fw file names + loader_setUpdateFwName(_UPDATE_FW_NAME_); + loader_setUpdateLdrName(_UPDATE_LOADER_NAME_); + loader_setRunFwName(_RUN_FW_NAME_); + // Setup FW_MAC_CODE_SIZE (i.e. FWResvSize in RTOS) + +#if 0 + // Sample to hook spi flash extending function + flash_installIdentifyCB(bl_spiIdentify); +#endif + +#if 0 + // Sample to hook flash programming LED callback + flash_installAccessCB(bl_flashLED); +#endif + +#if (SPECIAL_KEY_UPDATE == ENABLE) + loader_installSpecialKeyCB(prj_isSpecialKeyPressed); +#endif + +#if (CHECK_CARD_EXIST == ENABLE) + loader_installCardDetectCB(prj_checkCardExist); +#endif + + +#if defined(_STORAGEINT_NandSpi_) + strg_obj = nand_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NAND, strg_obj); + + // set Nand Flash speed to 96MHz + //strg_obj->flash_setFrequency(96); +#elif defined(_STORAGEINT_SpiFlash_) + strg_obj = nor_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NOR, strg_obj); +#elif defined(_STORAGEINT_EMMC_) + strg_obj = emmc_get_storage_object(); + strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, TRUE); + loader_setStorageIntType(STORAGEINT_EMMC, strg_obj); +#elif defined(_STORAGEINT_EMMC_NAND_COMBO_) + if (top_get_bs() == BOOT_SOURCE_SPI_NAND_2K || top_get_bs() == BOOT_SOURCE_SPI_NAND_4K) { + debug_msg_var("NAND,BS=", top_get_bs()); + strg_obj = nand_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NAND, strg_obj); + } else if (top_get_bs() == BOOT_SOURCE_EMMC_4BIT || top_get_bs() == BOOT_SOURCE_EMMC_8BIT) { + debug_msg("eMMC"); + strg_obj = emmc_get_storage_object(); + if (top_get_bs() == BOOT_SOURCE_EMMC_8BIT) { + strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, TRUE); + debug_msg("[8bit]\r\n"); + } else { + debug_msg("[4bit]\r\n"); + } + loader_setStorageIntType(STORAGEINT_EMMC, strg_obj); + } else if (top_get_bs() == BOOT_SOURCE_SPI) { + debug_msg("NOR\r\n"); + strg_obj = nor_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NOR, strg_obj); + } else { + debug_msg_var("unknow BS=", top_get_bs()); + } +#endif +} + diff --git a/board/novatek/na51055/loader/Project/Model/Src/prj_main.h b/board/novatek/na51055/loader/Project/Model/Src/prj_main.h new file mode 100755 index 000000000000..7efa3fa71613 --- /dev/null +++ b/board/novatek/na51055/loader/Project/Model/Src/prj_main.h @@ -0,0 +1,82 @@ +/** + Loader project header file + + Loader project header file + + @file prj_main.h + @note Nothing +*/ + +#ifndef _PRJ_MAIN_H +#define _PRJ_MAIN_H + +#include "constant.h" +#include "loader.h" +#include "GPIO.h" + +// Define SPECIAL_KEY_UPDATE == ENABLE will require user to press special key +// to update firmware +#ifndef SPECIAL_KEY_UPDATE +#define SPECIAL_KEY_UPDATE DISABLE +#endif + +#ifndef SPI_PINMUX_NORMAL +#define SPI_PINMUX_NORMAL (0) +#endif + +#ifndef SPI_PINMUX_4BITS +#define SPI_PINMUX_4BITS (1) +#endif + +#ifndef SPI_PINMUX_SETTING +#define SPI_PINMUX_SETTING (SPI_PINMUX_4BITS) +#endif + +// Define MACROs for external storage +// +#ifndef STORAGE_EXT_UNKOWN +#define STORAGE_EXT_UNKOWN (0) +#endif + +#ifndef STORAGE_EXT_SDIO1 +#define STORAGE_EXT_SDIO1 (1) +#endif + +#ifndef STORAGE_EXT_SDIO2 +#define STORAGE_EXT_SDIO2 (2) +#endif + +#ifndef STORAGE_EXT_USB +#define STORAGE_EXT_USB (3) +#endif + +#ifndef STORAGE_EXT_ETH +#define STORAGE_EXT_ETH (4) +#endif + +#ifndef STORAGE_EXT_NONE +#define STORAGE_EXT_NONE (5) +#endif + +#ifndef STORAGE_EXT_TYPE +#define STORAGE_EXT_TYPE (STORAGE_EXT_SDIO1) +#endif + + + +// Card detect GPIO offset +#if (CARD_DETECT_PIN == _CARD_DETECT_TYPE_1_) +#define DGPIO_CARD_DETECT (P_GPIO_12) +#elif (CARD_DETECT_PIN == _CARD_DETECT_TYPE_2_) +#define DGPIO_CARD_DETECT (C_GPIO_9) +#else +#define DGPIO_CARD_DETECT (P_GPIO_17) +#endif + + +#define CHECK_CARD_EXIST (ENABLE) + +// disable debug msg +#define DEBUG_MSG (ENABLE) + +#endif diff --git a/board/novatek/na51055/loader/Tools/Bin/Configram520 b/board/novatek/na51055/loader/Tools/Bin/Configram520 new file mode 100755 index 000000000000..ca78ec39ee62 Binary files /dev/null and b/board/novatek/na51055/loader/Tools/Bin/Configram520 differ diff --git a/board/novatek/na51055/loader/Tools/Bin/bfc b/board/novatek/na51055/loader/Tools/Bin/bfc new file mode 100755 index 000000000000..03b06d7d9ab1 Binary files /dev/null and b/board/novatek/na51055/loader/Tools/Bin/bfc differ diff --git a/board/novatek/na51055/loader/Tools/Bin/encrypt_boot b/board/novatek/na51055/loader/Tools/Bin/encrypt_boot new file mode 100755 index 000000000000..899da5df7a16 Binary files /dev/null and b/board/novatek/na51055/loader/Tools/Bin/encrypt_boot differ diff --git a/board/novatek/na51055/loader/Tools/Bin/encrypt_boot_dump b/board/novatek/na51055/loader/Tools/Bin/encrypt_boot_dump new file mode 100755 index 000000000000..1a44cedcf2ce Binary files /dev/null and b/board/novatek/na51055/loader/Tools/Bin/encrypt_boot_dump differ diff --git a/board/novatek/na51055/loader/Tools/Bin/nvt-ld-op b/board/novatek/na51055/loader/Tools/Bin/nvt-ld-op new file mode 100755 index 000000000000..99cf292f35b3 Binary files /dev/null and b/board/novatek/na51055/loader/Tools/Bin/nvt-ld-op differ diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_400_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_400_1024.ini new file mode 100755 index 000000000000..77a58b73a478 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_400_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x11221021 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00215555 +#Dram Configuration register(0xF0000000) +config_reg = 0x00015063 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10606406 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0C2E002A +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x000C1415 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000302 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x07 +# reg_39 +reg_39 = 0x07 +# reg_40 +reg_40 = 0x0D +# reg_41 +reg_41 = 0x0D +# reg_42 +reg_42 = 0x08 +# reg_43 +reg_43 = 0x08 +# reg_44 +reg_44 = 0x08 +# reg_45 +reg_45 = 0x08 +# reg_46 +reg_46 = 0x08 +# reg_47 +reg_47 = 0x08 +# reg_53 +reg_53 = 0x07 +# reg_54 +reg_54 = 0x0B +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0B +# reg_58 +reg_58 = 0x07 +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_400_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_400_2048.ini new file mode 100755 index 000000000000..711265869635 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_400_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x11221021 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00215555 +#Dram Configuration register(0xF0000000) +config_reg = 0x00015064 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10606406 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0C2E003F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x000C1415 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000302 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x07 +# reg_39 +reg_39 = 0x07 +# reg_40 +reg_40 = 0x0D +# reg_41 +reg_41 = 0x0D +# reg_42 +reg_42 = 0x08 +# reg_43 +reg_43 = 0x08 +# reg_44 +reg_44 = 0x08 +# reg_45 +reg_45 = 0x08 +# reg_46 +reg_46 = 0x08 +# reg_47 +reg_47 = 0x08 +# reg_53 +reg_53 = 0x07 +# reg_54 +reg_54 = 0x0B +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0B +# reg_58 +reg_58 = 0x07 +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_400_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_400_4096.ini new file mode 100755 index 000000000000..c723466cac62 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_400_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x11221021 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00215555 +#Dram Configuration register(0xF0000000) +config_reg = 0x00015065 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10606406 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0C2E0069 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x000C1415 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000302 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x07 +# reg_39 +reg_39 = 0x07 +# reg_40 +reg_40 = 0x0D +# reg_41 +reg_41 = 0x0D +# reg_42 +reg_42 = 0x08 +# reg_43 +reg_43 = 0x08 +# reg_44 +reg_44 = 0x08 +# reg_45 +reg_45 = 0x08 +# reg_46 +reg_46 = 0x08 +# reg_47 +reg_47 = 0x08 +# reg_53 +reg_53 = 0x07 +# reg_54 +reg_54 = 0x0B +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0B +# reg_58 +reg_58 = 0x07 +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_507_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_507_1024.ini new file mode 100755 index 000000000000..261f6c2c5fc6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_507_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x11221021 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x002A4000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00016083 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F550035 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x07 +# reg_39 +reg_39 = 0x07 +# reg_40 +reg_40 = 0x0D +# reg_41 +reg_41 = 0x0D +# reg_42 +reg_42 = 0x08 +# reg_43 +reg_43 = 0x08 +# reg_44 +reg_44 = 0x08 +# reg_45 +reg_45 = 0x08 +# reg_46 +reg_46 = 0x08 +# reg_47 +reg_47 = 0x08 +# reg_53 +reg_53 = 0x07 +# reg_54 +reg_54 = 0x0B +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0B +# reg_58 +reg_58 = 0x07 +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_507_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_507_2048.ini new file mode 100755 index 000000000000..1e5c53e23b17 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_507_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x11221021 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x002A4000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00016084 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F55004F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x07 +# reg_39 +reg_39 = 0x07 +# reg_40 +reg_40 = 0x0D +# reg_41 +reg_41 = 0x0D +# reg_42 +reg_42 = 0x08 +# reg_43 +reg_43 = 0x08 +# reg_44 +reg_44 = 0x08 +# reg_45 +reg_45 = 0x08 +# reg_46 +reg_46 = 0x08 +# reg_47 +reg_47 = 0x08 +# reg_53 +reg_53 = 0x07 +# reg_54 +reg_54 = 0x0B +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0B +# reg_58 +reg_58 = 0x07 +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_507_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_507_4096.ini new file mode 100755 index 000000000000..3c1e6c664242 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_507_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x11221021 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x002A4000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00016085 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F550081 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x07 +# reg_39 +reg_39 = 0x07 +# reg_40 +reg_40 = 0x0D +# reg_41 +reg_41 = 0x0D +# reg_42 +reg_42 = 0x08 +# reg_43 +reg_43 = 0x08 +# reg_44 +reg_44 = 0x08 +# reg_45 +reg_45 = 0x08 +# reg_46 +reg_46 = 0x08 +# reg_47 +reg_47 = 0x08 +# reg_53 +reg_53 = 0x07 +# reg_54 +reg_54 = 0x0B +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0B +# reg_58 +reg_58 = 0x07 +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_793_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_793_1024.ini new file mode 100755 index 000000000000..02339f7973f1 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_793_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00421554 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17FC0058 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x0A +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x54 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_793_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_793_2048.ini new file mode 100755 index 000000000000..d99572962afd --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_793_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00421554 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17FC007F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x0A +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x54 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_793_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_793_4096.ini new file mode 100755 index 000000000000..36aa8746ecc8 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_793_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00421554 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17FC00D0 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x0A +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x54 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_933_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_933_1024.ini new file mode 100755 index 000000000000..95d0123a69e0 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_933_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004DC000 +#Dram Configuration register(0xF0000000) +config_reg = 0x000190D3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1C390067 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0C +# reg_0F +reg_0F = 0x0E +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x07 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x44 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_933_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_933_2048.ini new file mode 100755 index 000000000000..cebcefdfada3 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_933_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004DC000 +#Dram Configuration register(0xF0000000) +config_reg = 0x000190D4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1C390096 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0C +# reg_0F +reg_0F = 0x0E +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x07 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x44 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_933_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_933_4096.ini new file mode 100755 index 000000000000..b01f876a5d2b --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/520/51055A_DRAM1_933_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004DC000 +#Dram Configuration register(0xF0000000) +config_reg = 0x000190D5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1C3900F3 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0C +# reg_0F +reg_0F = 0x0E +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x07 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x44 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_507_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_507_1024.ini new file mode 100755 index 000000000000..68eaa21e0269 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_507_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116083 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F050035 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_507_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_507_2048.ini new file mode 100755 index 000000000000..4804289a2e8a --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_507_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116084 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F05004F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_507_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_507_4096.ini new file mode 100755 index 000000000000..b4e686d8de22 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_507_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116085 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F050081 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_700_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_700_1024.ini new file mode 100755 index 000000000000..e878164b46a7 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_700_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D7004B +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x06 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_700_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_700_2048.ini new file mode 100755 index 000000000000..ae195fc5b7c6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_700_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D7006E +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x06 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_700_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_700_4096.ini new file mode 100755 index 000000000000..bd176845b76f --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_700_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D700B4 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x06 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_793_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_793_1024.ini new file mode 100755 index 000000000000..ab0cd190fd26 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_793_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A20058 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_793_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_793_2048.ini new file mode 100755 index 000000000000..fb0a21f9988d --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_793_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A2007F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_793_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_793_4096.ini new file mode 100755 index 000000000000..fbce174389cc --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_793_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A200D0 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_933_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_933_1024.ini new file mode 100755 index 000000000000..8e0e9b9acdc6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_933_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA0067 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x05 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_933_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_933_2048.ini new file mode 100755 index 000000000000..5eb68a216f25 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_933_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA0096 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x05 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_933_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_933_4096.ini new file mode 100755 index 000000000000..983e0c00b9bf --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/522/51055A_DRAM2_933_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA00F3 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x05 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_507_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_507_1024.ini new file mode 100755 index 000000000000..68eaa21e0269 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_507_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116083 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F050035 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_507_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_507_2048.ini new file mode 100755 index 000000000000..4804289a2e8a --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_507_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116084 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F05004F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_507_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_507_4096.ini new file mode 100755 index 000000000000..b4e686d8de22 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_507_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116085 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F050081 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_700_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_700_1024.ini new file mode 100755 index 000000000000..e878164b46a7 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_700_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D7004B +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x06 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_700_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_700_2048.ini new file mode 100755 index 000000000000..ae195fc5b7c6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_700_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D7006E +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x06 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_700_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_700_4096.ini new file mode 100755 index 000000000000..bd176845b76f --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_700_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D700B4 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x06 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_793_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_793_1024.ini new file mode 100755 index 000000000000..ab0cd190fd26 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_793_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A20058 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_793_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_793_2048.ini new file mode 100755 index 000000000000..fb0a21f9988d --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_793_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A2007F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_793_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_793_4096.ini new file mode 100755 index 000000000000..fbce174389cc --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_793_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A200D0 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_933_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_933_1024.ini new file mode 100755 index 000000000000..8e0e9b9acdc6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_933_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA0067 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x05 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_933_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_933_2048.ini new file mode 100755 index 000000000000..5eb68a216f25 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_933_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA0096 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x05 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_933_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_933_4096.ini new file mode 100755 index 000000000000..983e0c00b9bf --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523/51055A_DRAM2_933_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA00F3 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x05 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_507_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_507_1024.ini new file mode 100755 index 000000000000..229160354f96 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_507_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116083 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F050035 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_507_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_507_2048.ini new file mode 100755 index 000000000000..4804289a2e8a --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_507_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116084 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F05004F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_507_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_507_4096.ini new file mode 100755 index 000000000000..b4e686d8de22 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_507_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116085 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F050081 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_700_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_700_1024.ini new file mode 100755 index 000000000000..e878164b46a7 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_700_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D7004B +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x06 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_700_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_700_2048.ini new file mode 100755 index 000000000000..ae195fc5b7c6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_700_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D7006E +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x06 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_700_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_700_4096.ini new file mode 100755 index 000000000000..bd176845b76f --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_700_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D700B4 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x06 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_793_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_793_1024.ini new file mode 100755 index 000000000000..ab0cd190fd26 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_793_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A20058 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_793_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_793_2048.ini new file mode 100755 index 000000000000..fb0a21f9988d --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_793_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A2007F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_793_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_793_4096.ini new file mode 100755 index 000000000000..fbce174389cc --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_793_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A200D0 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_933_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_933_1024.ini new file mode 100755 index 000000000000..8e0e9b9acdc6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_933_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA0067 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x05 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_933_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_933_2048.ini new file mode 100755 index 000000000000..5eb68a216f25 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_933_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA0096 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x05 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_933_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_933_4096.ini new file mode 100755 index 000000000000..983e0c00b9bf --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/523_A/51055A_DRAM2_933_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA00F3 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x05 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_507_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_507_1024.ini new file mode 100755 index 000000000000..582d10f3774a --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_507_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x002A4000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00016083 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F550035 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_507_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_507_2048.ini new file mode 100755 index 000000000000..dd9ff2311e19 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_507_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x002A4000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00016084 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F55004F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_507_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_507_4096.ini new file mode 100755 index 000000000000..843f7a286b3a --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_507_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x002A4000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00016085 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F550081 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_700_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_700_1024.ini new file mode 100755 index 000000000000..ca196f9741ca --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_700_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x003A5555 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x152C004B +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x09 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_700_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_700_2048.ini new file mode 100755 index 000000000000..2c5bba86dcfb --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_700_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x003A5555 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x152C006E +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x09 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_700_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_700_4096.ini new file mode 100755 index 000000000000..5d2376ff8486 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_700_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x003A5555 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x152C00B4 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x09 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0b +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_1024.ini new file mode 100755 index 000000000000..02339f7973f1 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00421554 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17FC0058 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x0A +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x54 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_2048.ini new file mode 100755 index 000000000000..d99572962afd --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00421554 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17FC007F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x0A +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x54 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_2048_ODT.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_2048_ODT.ini new file mode 100755 index 000000000000..9d245d01a09d --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_2048_ODT.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00421554 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17FC007F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x0A +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x54 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_4096.ini new file mode 100755 index 000000000000..36aa8746ecc8 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00421554 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17FC00D0 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x0A +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x54 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_4096_ODT.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_4096_ODT.ini new file mode 100755 index 000000000000..6e5b1dea98be --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_793_4096_ODT.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00421554 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17FC00D0 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x0A +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x08 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x54 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_933_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_933_1024.ini new file mode 100755 index 000000000000..00bd6ff93ffb --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_933_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004DC000 +#Dram Configuration register(0xF0000000) +config_reg = 0x000190D3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1C390067 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0C +# reg_0F +reg_0F = 0x0E +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x34 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_933_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_933_2048.ini new file mode 100755 index 000000000000..e75c6c0b7241 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_933_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004DC000 +#Dram Configuration register(0xF0000000) +config_reg = 0x000190D4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1C390096 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0C +# reg_0F +reg_0F = 0x0E +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x34 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_933_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_933_4096.ini new file mode 100755 index 000000000000..d21e4d1445b8 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM1_933_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004DC000 +#Dram Configuration register(0xF0000000) +config_reg = 0x000190D5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1C3900F3 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0C +# reg_0F +reg_0F = 0x0E +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x08 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x34 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_507_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_507_1024.ini new file mode 100755 index 000000000000..68eaa21e0269 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_507_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116083 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F050035 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_507_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_507_2048.ini new file mode 100755 index 000000000000..4804289a2e8a --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_507_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116084 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F05004F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_507_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_507_4096.ini new file mode 100755 index 000000000000..b4e686d8de22 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_507_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00296000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00116085 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F050081 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x02 +# reg_0F +reg_0F = 0x02 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x65 +# reg_B1 +reg_B1 = 0x43 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x04 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# descew_c1_reg00 +descew_c1_reg00 = 0x7F +# descew_c1_reg01 +descew_c1_reg01 = 0x7F +# descew_c1_reg02 +descew_c1_reg02 = 0x7F +# descew_c1_reg03 +descew_c1_reg03 = 0x7F +# descew_c1_reg04 +descew_c1_reg04 = 0x7F +# descew_c1_reg05 +descew_c1_reg05 = 0x7F +# descew_c1_reg06 +descew_c1_reg06 = 0x7F +# descew_c1_reg07 +descew_c1_reg07 = 0x7F +# descew_c1_reg08 +descew_c1_reg08 = 0x7F +# descew_c1_reg09 +descew_c1_reg09 = 0x7F +# descew_c1_reg0A +descew_c1_reg0A = 0x7F +# descew_c1_reg0B +descew_c1_reg0B = 0x7F +# descew_c1_reg0C +descew_c1_reg0C = 0x7F +# descew_c1_reg0D +descew_c1_reg0D = 0x7F +# descew_c1_reg0E +descew_c1_reg0E = 0x7F +# descew_c1_reg0F +descew_c1_reg0F = 0x7F +# descew_c1_reg10 +descew_c1_reg10 = 0x7F +# descew_c1_reg11 +descew_c1_reg11 = 0x7F +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_700_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_700_1024.ini new file mode 100755 index 000000000000..b6e8762982f8 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_700_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D7004B +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x07 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0c +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_700_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_700_2048.ini new file mode 100755 index 000000000000..25d57f9c1051 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_700_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D7006E +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x07 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0c +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_700_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_700_4096.ini new file mode 100755 index 000000000000..3d5f5ea7af12 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_700_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00396AAA +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x20A09509 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x14D700B4 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00151C22 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000504 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x07 +# reg_0F +reg_0F = 0x08 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0b +# reg_D6 +reg_D6 = 0x0c +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_1024.ini new file mode 100755 index 000000000000..ab0cd190fd26 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A20058 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_2048.ini new file mode 100755 index 000000000000..fb0a21f9988d --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A2007F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_2048_ODT.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_2048_ODT.ini new file mode 100755 index 000000000000..e8263ff80ee0 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_2048_ODT.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A2007F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_4096.ini new file mode 100755 index 000000000000..fbce174389cc --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A200D0 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x00 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_4096_ODT.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_4096_ODT.ini new file mode 100755 index 000000000000..2de7def2bee9 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_793_4096_ODT.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x00412000 +#Dram Configuration register(0xF0000000) +config_reg = 0x001180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x17A200D0 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC5 +# reg_0D +reg_0D = 0x09 +# reg_0F +reg_0F = 0x0A +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x11 +# reg_8A +reg_8A = 0x11 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x40 +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x02 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0C +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_933_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_933_1024.ini new file mode 100755 index 000000000000..2f15c75e32bb --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_933_1024.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA0067 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x45 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_933_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_933_2048.ini new file mode 100755 index 000000000000..6cad41fdff37 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_933_2048.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA0096 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x45 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_933_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_933_4096.ini new file mode 100755 index 000000000000..89bc2a6f95ab --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/525/51055A_DRAM2_933_4096.ini @@ -0,0 +1,130 @@ +ini_ver = 0x01210208 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004CB554 +#Dram Configuration register(0xF0000000) +config_reg = 0x001190D5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1BDA00F3 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x0D +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_61 +reg_61 = 0x01 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x07 +# reg_AF +reg_AF = 0x0F +# reg_B0 +reg_B0 = 0x60 +# reg_B1 +reg_B1 = 0x5E +# reg_B2 +reg_B2 = 0x06 +# reg_B3 +reg_B3 = 0x0F +# reg_B7 +reg_B7 = 0x1E +# reg_B8 +reg_B8 = 0x45 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# descew_c1_reg00 +descew_c1_reg00 = 0x7C +# descew_c1_reg01 +descew_c1_reg01 = 0x7C +# descew_c1_reg02 +descew_c1_reg02 = 0x7C +# descew_c1_reg03 +descew_c1_reg03 = 0x7C +# descew_c1_reg04 +descew_c1_reg04 = 0x7C +# descew_c1_reg05 +descew_c1_reg05 = 0x7D +# descew_c1_reg06 +descew_c1_reg06 = 0x7D +# descew_c1_reg07 +descew_c1_reg07 = 0x7D +# descew_c1_reg08 +descew_c1_reg08 = 0x7D +# descew_c1_reg09 +descew_c1_reg09 = 0x7D +# descew_c1_reg0A +descew_c1_reg0A = 0x7D +# descew_c1_reg0B +descew_c1_reg0B = 0x7D +# descew_c1_reg0C +descew_c1_reg0C = 0x7D +# descew_c1_reg0D +descew_c1_reg0D = 0x7D +# descew_c1_reg0E +descew_c1_reg0E = 0x7C +# descew_c1_reg0F +descew_c1_reg0F = 0x7C +# descew_c1_reg10 +descew_c1_reg10 = 0x7C +# descew_c1_reg11 +descew_c1_reg11 = 0x7C +#end \ No newline at end of file diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_1024.ini new file mode 100755 index 000000000000..ba98f54ae0a1 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x002c7000 +config_reg = 0x0001a0e3 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x203f0073 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x04 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x3c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_2048.ini new file mode 100755 index 000000000000..a67f963f8b26 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x002c7000 +config_reg = 0x0001a0e4 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x203f00a8 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_4096.ini new file mode 100755 index 000000000000..4f900769b572 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x60210205 +pllratio = 0x002c7000 +config_reg = 0x0001a0e5 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x203f0113 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_8192.ini new file mode 100755 index 000000000000..b0cb51b5e757 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_1066_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x20210205 +pllratio = 0x002c7000 +config_reg = 0x0001a0e6 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x203f0113 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x0c +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0xbc +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_1024.ini new file mode 100755 index 000000000000..62aff4c1a34f --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x00210aaa +config_reg = 0x180B3 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17FC0055 +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0x13 +reg_013 = 0x03 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x2d +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_2048.ini new file mode 100755 index 000000000000..a468afacd5ae --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x00210aaa +config_reg = 0x180B4 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17FC007D +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_4096.ini new file mode 100755 index 000000000000..0ca2dd927b2d --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x50210205 +pllratio = 0x00210aaa +config_reg = 0x180B5 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17FC00CD +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_8192.ini new file mode 100755 index 000000000000..e822134e436c --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_793_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x60210205 +pllratio = 0x00210aaa +config_reg = 0x180B6 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17FC00CD +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0x03 +reg_013 = 0x09 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_1024.ini new file mode 100755 index 000000000000..84f173a654dc --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x0026e000 +config_reg = 0x190D3 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1C390064 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x03 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x35 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_2048.ini new file mode 100755 index 000000000000..90e396332c74 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x0026e000 +config_reg = 0x190D4 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1C390093 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x4c +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_4096.ini new file mode 100755 index 000000000000..476c1858ccd6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x50210205 +pllratio = 0x0026e000 +config_reg = 0x190D5 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1C3900F0 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x7b +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_8192.ini new file mode 100755 index 000000000000..138ad97bbfaa --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM1_933_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x20210205 +pllratio = 0x0026e000 +config_reg = 0x190D6 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1C3900F0 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x0a +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0xa5 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_1024.ini new file mode 100755 index 000000000000..3f2744af5bb5 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x002be555 +config_reg = 0x0011a0e3 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x1fe00073 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x04 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x3c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_2048.ini new file mode 100755 index 000000000000..9ad6e0f8dd78 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x002be555 +config_reg = 0x0011a0e4 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x1fe000a8 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_4096.ini new file mode 100755 index 000000000000..020c9f3a9494 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x60210205 +pllratio = 0x002be555 +config_reg = 0x0011a0e5 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x1fe00113 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_8192.ini new file mode 100755 index 000000000000..1cf900f7cb37 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_1066_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x20210205 +pllratio = 0x002be555 +config_reg = 0x0011a0e6 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x1fe00113 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x0c +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0xbc +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_1024.ini new file mode 100755 index 000000000000..068bc503fef3 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x00209000 +config_reg = 0x1180B3 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17A20055 +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0x13 +reg_013 = 0x03 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x2d +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_2048.ini new file mode 100755 index 000000000000..ab193072fc9e --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x00209000 +config_reg = 0x1180B4 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17A2007D +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_4096.ini new file mode 100755 index 000000000000..0b6e5692569b --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x50210205 +pllratio = 0x00209000 +config_reg = 0x1180B5 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17A200CD +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_8192.ini new file mode 100755 index 000000000000..440046bfe358 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_793_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x60210205 +pllratio = 0x00209000 +config_reg = 0x1180B6 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17A200CD +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0x03 +reg_013 = 0x09 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_1024.ini new file mode 100755 index 000000000000..9ae140174ed6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x00265AAA +config_reg = 0x1190D3 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1BDA0064 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x03 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x35 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_2048.ini new file mode 100755 index 000000000000..9b44cc855342 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x00265AAA +config_reg = 0x1190D4 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1BDA0093 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x4c +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_4096.ini new file mode 100755 index 000000000000..4f05832ecfb4 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x50210205 +pllratio = 0x00265AAA +config_reg = 0x1190D5 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1BDA00F0 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x7b +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_8192.ini new file mode 100755 index 000000000000..b527323ffc8b --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/528/51055A_DRAM2_933_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x20210205 +pllratio = 0x00265AAA +config_reg = 0x1190D6 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1BDA00F0 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x0a +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0xa5 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_1024.ini new file mode 100755 index 000000000000..ba98f54ae0a1 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x002c7000 +config_reg = 0x0001a0e3 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x203f0073 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x04 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x3c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_2048.ini new file mode 100755 index 000000000000..a67f963f8b26 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x002c7000 +config_reg = 0x0001a0e4 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x203f00a8 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_4096.ini new file mode 100755 index 000000000000..4f900769b572 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x60210205 +pllratio = 0x002c7000 +config_reg = 0x0001a0e5 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x203f0113 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_8192.ini new file mode 100755 index 000000000000..b0cb51b5e757 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_1066_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x20210205 +pllratio = 0x002c7000 +config_reg = 0x0001a0e6 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x203f0113 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x0c +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0xbc +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_1024.ini new file mode 100755 index 000000000000..62aff4c1a34f --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x00210aaa +config_reg = 0x180B3 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17FC0055 +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0x13 +reg_013 = 0x03 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x2d +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_2048.ini new file mode 100755 index 000000000000..a468afacd5ae --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x00210aaa +config_reg = 0x180B4 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17FC007D +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_4096.ini new file mode 100755 index 000000000000..0ca2dd927b2d --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x50210205 +pllratio = 0x00210aaa +config_reg = 0x180B5 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17FC00CD +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_8192.ini new file mode 100755 index 000000000000..e822134e436c --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_793_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x60210205 +pllratio = 0x00210aaa +config_reg = 0x180B6 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17FC00CD +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0x03 +reg_013 = 0x09 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_1024.ini new file mode 100755 index 000000000000..84f173a654dc --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x0026e000 +config_reg = 0x190D3 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1C390064 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x03 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x35 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_2048.ini new file mode 100755 index 000000000000..90e396332c74 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x0026e000 +config_reg = 0x190D4 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1C390093 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x4c +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_4096.ini new file mode 100755 index 000000000000..476c1858ccd6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x50210205 +pllratio = 0x0026e000 +config_reg = 0x190D5 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1C3900F0 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x7b +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_8192.ini new file mode 100755 index 000000000000..138ad97bbfaa --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM1_933_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x20210205 +pllratio = 0x0026e000 +config_reg = 0x190D6 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1C3900F0 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x26 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x0a +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0xa5 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_1024.ini new file mode 100755 index 000000000000..3f2744af5bb5 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x002be555 +config_reg = 0x0011a0e3 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x1fe00073 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x04 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x3c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_2048.ini new file mode 100755 index 000000000000..9ad6e0f8dd78 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x002be555 +config_reg = 0x0011a0e4 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x1fe000a8 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_4096.ini new file mode 100755 index 000000000000..020c9f3a9494 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x60210205 +pllratio = 0x002be555 +config_reg = 0x0011a0e5 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x1fe00113 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_8192.ini new file mode 100755 index 000000000000..1cf900f7cb37 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_1066_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x20210205 +pllratio = 0x002be555 +config_reg = 0x0011a0e6 +timing_reg0 = 0x40f0d60d +timing_reg1 = 0x1fe00113 +timing_reg2 = 0x00202531 +timing_reg3 = 0x00000706 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x8f +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x0c +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0xbc +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_1024.ini new file mode 100755 index 000000000000..068bc503fef3 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x00209000 +config_reg = 0x1180B3 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17A20055 +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0x13 +reg_013 = 0x03 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x2d +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_2048.ini new file mode 100755 index 000000000000..ab193072fc9e --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x00209000 +config_reg = 0x1180B4 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17A2007D +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_4096.ini new file mode 100755 index 000000000000..0b6e5692569b --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x50210205 +pllratio = 0x00209000 +config_reg = 0x1180B5 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17A200CD +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_8192.ini new file mode 100755 index 000000000000..440046bfe358 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_793_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x60210205 +pllratio = 0x00209000 +config_reg = 0x1180B6 +timing_reg0 = 0x20B0A50A +timing_reg1 = 0x17A200CD +timing_reg2 = 0x00181F26 +timing_reg3 = 0x00000504 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x00000000 +reg_0BC = 0x00 +reg_14A = 0xf0 +reg_14C = 0xf0 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x70 +reg_011 = 0x06 +reg_012 = 0x03 +reg_013 = 0x09 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x00 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x15 +reg_021 = 0x0c +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_1024.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_1024.ini new file mode 100755 index 000000000000..9ae140174ed6 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_1024.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x40211104 +pllratio = 0x00265AAA +config_reg = 0x1190D3 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1BDA0064 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x03 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x35 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_2048.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_2048.ini new file mode 100755 index 000000000000..9b44cc855342 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_2048.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x30210205 +pllratio = 0x00265AAA +config_reg = 0x1190D4 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1BDA0093 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x4c +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_4096.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_4096.ini new file mode 100755 index 000000000000..4f05832ecfb4 --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_4096.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x50210205 +pllratio = 0x00265AAA +config_reg = 0x1190D5 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1BDA00F0 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x7b +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_8192.ini b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_8192.ini new file mode 100755 index 000000000000..b527323ffc8b --- /dev/null +++ b/board/novatek/na51055/loader/Tools/ConfigRam/529/51055A_DRAM2_933_8192.ini @@ -0,0 +1,123 @@ +#ini note : cs driving and phase fine tune +ini_ver = 0x20210205 +pllratio = 0x00265AAA +config_reg = 0x1190D6 +timing_reg0 = 0x40D0C50C +timing_reg1 = 0x1BDA00F0 +timing_reg2 = 0x001C202C +timing_reg3 = 0x00000605 +timing_reg4 = 0x02000000 +timing_reg5 = 0x00000106 +engineer_reg = 0x00280D21 +odt_reg = 0x01111113 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x0c +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0xc0 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xd1 +reg_0C2 = 0x27 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x01 +reg_0C8 = 0xdd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x40 +reg_164 = 0x46 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x11 +reg_0D3 = 0xdd +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x22 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x0a +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0xa5 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x00 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/Makefile b/board/novatek/na51068/Makefile new file mode 100644 index 000000000000..ea94d19864ac --- /dev/null +++ b/board/novatek/na51068/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += na51068.o diff --git a/board/novatek/na51068/loader/.gitattributes b/board/novatek/na51068/loader/.gitattributes new file mode 100644 index 000000000000..1c5b20e00b05 --- /dev/null +++ b/board/novatek/na51068/loader/.gitattributes @@ -0,0 +1,2 @@ +# The vendor loader, as the SDK ships it: no line-ending conversion +* -text diff --git a/board/novatek/na51068/loader/.gitignore b/board/novatek/na51068/loader/.gitignore new file mode 100644 index 000000000000..f84d41d3cbe0 --- /dev/null +++ b/board/novatek/na51068/loader/.gitignore @@ -0,0 +1,2 @@ +# The vendor libraries the loader links against +!*.a diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/CA9.a b/board/novatek/na51068/loader/ARC/Lib/Release/CA9.a new file mode 100644 index 000000000000..4df32c913b5b Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/CA9.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Common.a b/board/novatek/na51068/loader/ARC/Lib/Release/Common.a new file mode 100644 index 000000000000..9799a0723b69 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Common.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Compress.a b/board/novatek/na51068/loader/ARC/Lib/Release/Compress.a new file mode 100644 index 000000000000..647ba358915c Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Compress.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Ctrl_Flow.a b/board/novatek/na51068/loader/ARC/Lib/Release/Ctrl_Flow.a new file mode 100644 index 000000000000..80a173d09240 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Ctrl_Flow.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Debug.a b/board/novatek/na51068/loader/ARC/Lib/Release/Debug.a new file mode 100644 index 000000000000..a26501ba1b16 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Debug.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Driver.a b/board/novatek/na51068/loader/ARC/Lib/Release/Driver.a new file mode 100644 index 000000000000..899aba3e6dd3 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Driver.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ321.a b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ321.a new file mode 100644 index 000000000000..dd1bb8cb3886 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ321.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ323.a b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ323.a new file mode 100644 index 000000000000..9e81d4bd156d Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ323.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ621.a b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ621.a new file mode 100644 index 000000000000..ec9a9b86a34c Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ621.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ623.a b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ623.a new file mode 100644 index 000000000000..22e65764eb48 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZ623.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZNC321.a b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZNC321.a new file mode 100644 index 000000000000..4112d022ad3c Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZNC321.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZNC323.a b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZNC323.a new file mode 100644 index 000000000000..69f6407f77e1 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_LZNC323.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Remap_NM321.a b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_NM321.a new file mode 100644 index 000000000000..b9f016eac020 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Remap_NM321.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/Reset.a b/board/novatek/na51068/loader/ARC/Lib/Release/Reset.a new file mode 100644 index 000000000000..f31cd87d1836 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/Reset.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_Eth.a b/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_Eth.a new file mode 100644 index 000000000000..52779ff0cd82 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_Eth.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_NONE.a b/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_NONE.a new file mode 100644 index 000000000000..930b28a0c4dd Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_NONE.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_Sdio1.a b/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_Sdio1.a new file mode 100644 index 000000000000..64b2dd9a1601 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_Sdio1.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_Uart.a b/board/novatek/na51068/loader/ARC/Lib/Release/STRGEXT_Uart.a new file mode 100644 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differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/fdt.a b/board/novatek/na51068/loader/ARC/Lib/Release/fdt.a new file mode 100644 index 000000000000..6833c1dc0431 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/fdt.a differ diff --git a/board/novatek/na51068/loader/ARC/Lib/Release/nvtpack.a b/board/novatek/na51068/loader/ARC/Lib/Release/nvtpack.a new file mode 100644 index 000000000000..eeccff9b4f09 Binary files /dev/null and b/board/novatek/na51068/loader/ARC/Lib/Release/nvtpack.a differ diff --git a/board/novatek/na51068/loader/Include/Driver/Memory.h b/board/novatek/na51068/loader/Include/Driver/Memory.h new file mode 100755 index 000000000000..ca922899c0e4 --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/Memory.h @@ -0,0 +1,174 @@ +# ifndef _MEMORY_680_H +# define _MEMORY_680_H + + +# define DRAM_BASE_ADDR (0x0000000) +# define DRAM_EXP_BASE_ADDR (DRAM_BASE_ADDR + 0x180) +# define DRAM_INT_BASE_ADDR (DRAM_BASE_ADDR + 0x200) + +# define StackSize_KNL 0x1000 /* 4KB */ +# define StackSize_INT 0x400 /* 1KB */ + +# define FAT_HEAP_BUFFER_SIZE 0xA0000 +# define LOADER_TMP_BUFFER_SIZE 0x80000 + +# define BOOT_ROM_SP_LIMIT_ADDR 0xFE0F8000 +# define BOOT_ROM_RAM_TEMP_ADDR 0xF0800200 +# define BOOT_ROM_CFG_TEMP_ADDR 0xF0800248 +# define BOOT_ROM_RAM_BASE_ADDR 0x00000000 +# define DMA2_CTRL_REG_BASE_ADDR 0xF0100000 +# define DMA2_PHY_REG_BASE_ADDR 0xF0101000 +# define USB_OTG_REG_BASE_ADDR 0xF0600000 +# define DDR_CTRL_REG_BASE_ADDR 0xFC400000 /* DDR phy base address */ +# define DDR_PHY_REG_BASE_ADDR 0xFC408000 +# define DDR_ARB_REG_BASE_ADDR 0xF0008000 +# define DMA2_ARB_REG_BASE_ADDR 0xF0108000 + +# define GPIO_CTRL_REG_BASE_ADDR 0xF0070000 +# define PMC_REG_BASE 0xF00A0000 + + + +# define UART2_REG_BASE_ADDR 0xF0300000 +# define SM_HOST_REG_BASE_ADDR 0xF0400000 +# define MS_HOST_REG_BASE_ADDR 0xF0410000 +# define SD_HOST1_REG_BASE_ADDR 0xF0420000 +# define SD_HOST2_REG_BASE_ADDR 0xF0500000 +# define SD_HOST3_REG_BASE_ADDR 0xF0510000 +# define SPI_CTRL_REG_BASE_ADDR 0xF0230000 +# define ETH_CTRL_REG_BASE_ADDR 0xFCD00000 +# define IDE_SRAM_BASE_ADDR 0xF07F0000 +# define IDE_CTRL_REG_BASE_ADDR 0xF0800000 +# define TIMER_REG_BASE_ADDR 0xF0040000 +# define WDT_REG_BASE_ADDR 0xF0050000 + +# define BOOT_LOADER_TMP_BUFFER 0x00001000 +# define CHIP_REMAP_REG_OFFSET 0x00000088 +# define CPE_RTC_BASE 0xF0060000 /* RTC controller */ +# define CPE_GPIO_BASE 0xF0070000 /* GPIO controller */ +# define INTERRUPT_BASE_ADDR 0xF0080000 /* Interrupt controller */ +# define CC_BASE_ADDR 0xF0090000 /* CC controller */ +# define IOADDR_GIC_REG_BASE 0xF1500000 /* GIC Interrupt */ +# define PAD_REG_BASE 0xF0030000 + +#define EFUSE_CTRL_REG_BASE_ADDR 0xFECE0000 +#define CRYPTO_REG_BASE_ADDR 0xFEC60000 +#define HASH_REG_BASE_ADDR 0xFEC80000 +#define RSA_REG_BASE_ADDR 0xFECA0000 + +#define BASE_CA9_TIMER 0xF9C00000 +#define BASE_PMU 0xFE000000 //SCU + + +#define CC_CPU2_CPU1_CMDBUF_REG1 0xFE0B9000 //CC_CPU2_CPU1_CMDBUF_REG1 to store uboot starting address +#define CC_CPU2_CPU1_CMDBUF_REG2 0xFE0B9004 //CC_CPU2_CPU1_CMDBUF_REG1 has used in core2_entry.s +#define NVT_CORE2_START CC_CPU2_CPU1_CMDBUF_REG2 //core2_entry.S 's entry point + +// Crypto controller register address +#define CRYPTO_CONFIG_REG (CRYPTO_REG_BASE_ADDR + 0x00) +#define CRYPTO_CONTROL_REG (CRYPTO_REG_BASE_ADDR + 0x04) +#define CRYPTO_OUT_DATA_REG (CRYPTO_REG_BASE_ADDR + 0x08) +#define CRYPTO_STATUS_REG (CRYPTO_REG_BASE_ADDR + 0x0C) + +#define CRYPTO_PIO_KEY0_REG (CRYPTO_REG_BASE_ADDR + 0x10) +#define CRYPTO_PIO_KEY1_REG (CRYPTO_REG_BASE_ADDR + 0x14) +#define CRYPTO_PIO_KEY2_REG (CRYPTO_REG_BASE_ADDR + 0x18) +#define CRYPTO_PIO_KEY3_REG (CRYPTO_REG_BASE_ADDR + 0x1C) + +#define CRYPTO_PIO_INPUT0_REG (CRYPTO_REG_BASE_ADDR + 0x30) +#define CRYPTO_PIO_INPUT1_REG (CRYPTO_REG_BASE_ADDR + 0x34) +#define CRYPTO_PIO_INPUT2_REG (CRYPTO_REG_BASE_ADDR + 0x38) +#define CRYPTO_PIO_INPUT3_REG (CRYPTO_REG_BASE_ADDR + 0x3C) +#define CRYPTO_PIO_OUTPUT0_REG (CRYPTO_REG_BASE_ADDR + 0x40) +#define CRYPTO_PIO_OUTPUT1_REG (CRYPTO_REG_BASE_ADDR + 0x44) +#define CRYPTO_PIO_OUTPUT2_REG (CRYPTO_REG_BASE_ADDR + 0x48) +#define CRYPTO_PIO_OUTPUT3_REG (CRYPTO_REG_BASE_ADDR + 0x4C) + +// Hash +#define HASH_CONFIG_REG (HASH_REG_BASE_ADDR + 0x00) +#define HASH_STATUS_REG (HASH_REG_BASE_ADDR + 0x0C) +#define HASH_OUTPUT_DATA1_REG (HASH_REG_BASE_ADDR + 0x70) +#define HASH_INPUT_DATA_REG (HASH_REG_BASE_ADDR + 0x90) + +//RSA +#define RSA_CONFIG_REG (RSA_REG_BASE_ADDR + 0x00) +#define RSA_CONTROL_REG (RSA_REG_BASE_ADDR + 0x04) +#define RSA_STATUS_REG (RSA_REG_BASE_ADDR + 0x0C) +#define RSA_KEY_N_REG (RSA_REG_BASE_ADDR + 0x10) +#define RSA_KEY_N_ADDR_REG (RSA_REG_BASE_ADDR + 0x14) +#define RSA_KEY_ED_REG (RSA_REG_BASE_ADDR + 0x18) +#define RSA_KEY_ED_ADDR_REG (RSA_REG_BASE_ADDR + 0x1C) +#define RSA_DATA_REG (RSA_REG_BASE_ADDR + 0x20) +#define RSA_DATA_ADDR_REG (RSA_REG_BASE_ADDR + 0x24) +#define RSA_CRC32_DEFAULT_REG_OFS (RSA_REG_BASE_ADDR + 0x30) +#define RSA_CRC32_POLY_REG_OFS (RSA_REG_BASE_ADDR + 0x34) +#define RSA_CRC32_OUTPUT_REG_OFS (RSA_REG_BASE_ADDR + 0x38) + +// Crypto +#define CRYPTO_CONFREG_SWRST (1<<0) +#define CRYPTO_CONFREG_CRYPTO_EN (1<<1) +#define CRYPTO_CONFREG_AES128 (2<<4) +#define CRYPTO_CONFREG_DECRYPT (1<<8) + +#define CRYPTO_PIO_DONE (1<<0) + + +// Hash +#define HASH_CONFREG_INITSTATE (1<<20) +#define HASH_CONFREG_SHA256 (1<<4) +#define HASH_CONFREG_ENABLE (1<<1) + +//RSA +#define RSA_ENABLE (1<<0) + +#define RSA_KEYWIDTH_256 (0x0<<1) +#define RSA_KEYWIDTH_512 (0x1<<1) +#define RSA_KEYWIDTH_1024 (0x2<<1) +#define RSA_KEYWIDTH_2048 (0x3<<1) +#define RSA_KEYWIDTH_4096 (0x4<<1) + +#define RSA_NORMAL_MODE (0x0<<4) +#define RSA_MODE_CRC_KEY_N (0x1<<4) +#define RSA_MODE_CRC_KEY_ED (0x2<<4) + + +#define RSA_TRANSFER_END (0x1<<0) +#define RSA_BUSY (0x1<<1) + +#define HASH_TRANSFER_END (0x1<<0) + + +// DDR phy duty configuration register bit +#define DDR_PHY_INCREASE_DUTY 0x40 // P < N +#define DDR_PHY_DECREASE_DUTY 0x00 // P > N +#define DDR_PHY_DUTY_TYPE_MSK 0x40 // bit mask for increase/decrease duty +#define DDR_PHY_CLK_ADJ_EN 0x80 + +// DDR phy duty calibration control register bit +#define DDR_PHY_CLK_OP_ONGOING 0x10 +#define DDR_PHY_CLK_OP_DONE 0x00 +#define DDR_PHY_DQS_OP_ONGOING 0x20 +#define DDR_PHY_DQS_OP_DONE 0x00 + + + +# define DDR_PHY_CAL_CLK_ADJ_OFS 0x000 /* 0x00 */ +# define DDR_PHY_CAL_CMD_ADJ_OFS 0x01C /* 0x1C */ +# define DDR_PHY_CAL_CTRL_OFS 0x150 /* 0x54 */ +# define DDR_PHY_CAL_CLK_CFG_OFS 0x154 /* 0x55 */ +# define DDR_PHY_CAL_DQS_CFG_OFS 0x158 /* 0x56 */ +# define DDR_PHY_CAL_DTY_CNT_LB_OFS 0x15C /* 0x57 duty cnt low byte */ +# define DDR_PHY_CAL_DTY_CNT_HB_OFS 0x160 /* 0x58 duty cnt high byte */ +# define DDR_PHY_CAL_DQS0_ADJ_OFS 0x1D0 /* 0x1D0 */ +# define DDR_PHY_CAL_DQ_ADJ_OFS 0x1D4 /* 0x1D0 */ + + +# define IDENTIFY_ERR 2 +# define MBR_ERR 3 +# define PBR_ERR 4 +# define READ512_ERR 5 +# define READ_ERR 7 +# define HPA_ERR 8 +# define CHECKSUM_ERR 9 + +# endif diff --git a/board/novatek/na51068/loader/Include/Driver/bus.h b/board/novatek/na51068/loader/Include/Driver/bus.h new file mode 100755 index 000000000000..ba8ca5cc6abf --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/bus.h @@ -0,0 +1,37 @@ +#ifndef __BUS_H__ +#define __BUS_H__ + +/* FTAXIC030_Reg, size 256MB:8 512MB:9 1GB:A */ +//#ifdef DDR0_1600_SZ_4Gbx2 + unsigned int bus_arg[][2] ={ + {0x00000008, 0xFF800000},//default 0x10080000 + {0x00000010, 0x40090000},//ddr1, default 0x20080000, remap to 0x40000000, 512MB + {0x0000000C, 0x000A0000}, + {0x00000084, 0x60090000},//remap with PCIE + {0x00020084, 0x60090000}, + {0x00020088, 0x800A0000}, + {0x0002008C, 0xC0090000}, + {0x00020090, 0xE0070000}, + {0x000C0084, 0x60090000}, + {0x000C0088, 0x800A0000}, + {0x000C008C, 0xC0090000}, + {0x000C0090, 0xE0070000}, + {0x000E0084, 0x60090000}, + {0x000E0088, 0x800A0000}, + {0x000E008C, 0xC0090000}, + {0x000E0090, 0xE0070000}, + {0x00020000, 0x000A0000},//default 0x00080000 + {0x00020004, 0x40090000},//ddr1, default 0x20090000 + {0x00040000, 0x000A0000}, + {0x00060000, 0x000A0000}, + {0x00080000, 0x000A0000}, + {0x00080004, 0x40090000},//ddr1 + {0x000A0000, 0x000A0000}, + {0x000A0004, 0x40090000},//ddr1 + {0x000C0000, 0x000A0000}, + {0x000C0004, 0x40090000},//ddr1 + {0x000E0000, 0x000A0000}, + {0x000E0004, 0x40090000}};//ddr1 +//#endif //DDR0_SZ_4Gbx2 + +#endif \ No newline at end of file diff --git a/board/novatek/na51068/loader/Include/Driver/cache.h b/board/novatek/na51068/loader/Include/Driver/cache.h new file mode 100755 index 000000000000..e840ce007b2a --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/cache.h @@ -0,0 +1,511 @@ +/** + CPU module driver. + + This file is the driver of CPU module. + + @file Cache.h + @ingroup mIHALCore + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2005. All rights reserved. +*/ + +#ifndef _CACHE_H +#define _CACHE_H +#include "constant.h" + + +/* + csselrcache level & type selection + + Detailed reference to [trm p4-177 CSSELR] +*/ +typedef enum _CACHE_LV_TYPE_ +{ + LEVEL_1_DCACHE = 0x0, //< Level 1 data cache + LEVEL_1_ICACHE, //< Level 1 instruction cache + LEVEL_2_DCACHE, //< Level 2 data cache +} CACHE_LV_TYPE; + + +/* + Values for Ctype fields in CLIDR +*/ + +typedef enum _CLIDR_CTYPE_ +{ + CLIDR_CTYPE_NO_CACHE = 0x0, + CLIDR_CTYPE_INSTRUCTION_ONLY= 0x1, + CLIDR_CTYPE_DATA_ONLY = 0x2, + CLIDR_CTYPE_INSTRUCTION_DATA= 0x3, + CLIDR_CTYPE_UNIFIED = 0x4, +}CLIDR_CTYPE; + + +//Instruction Synchronization Barrier. +#define _ISB() \ + __asm__ __volatile__("isb\n\t") + +//Data Synchronization Barrier +#define _DSB() \ + __asm__ __volatile__("dsb\n\t") + +//Data Memory Barrier +#define _DMB() \ + __asm__ __volatile__("dmb\n\t") + + +/* + ************************************************************************ + * Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |W|W|R|W|NumSets |Associativity |L | + * |T|B|A|A| | |S | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_DC_SETS 8 +#define S_DC_W 2 +#define S_DC_LS 5 + +#define _DC_SETS (1 << S_DC_SETS) /* 256 sets */ +#define _DC_W (1 << S_DC_W) /* 4 way */ +#define _DC_LS (1 << S_DC_LS) /* 32 byte line size */ + +#define S_IC_SETS 8 +#define S_IC_W 2 +#define S_IC_LS 5 + +#define _IC_SETS (1 << S_IC_SETS) /* 256 sets */ +#define _IC_W (1 << S_IC_W) /* 4 way */ +#define _IC_LS (1 << S_IC_LS) /* 32 byte line size */ + +#define S_DC_W_L2 4 /* L2 way shift*/ + +#define S_SC_SETS 9 +#define S_SC_W 3 +#define S_SC_LS 5 + +#define _SC_SETS (1 << S_SC_SETS) /* 512 sets */ +#define _SC_W (1 << S_SC_W) /* 8 way */ +#define _SC_LS (1 << S_SC_LS) /* 32 byte line size */ + + +#define S_CCSIDR_WT 31 +#define M_CCSIDR_WT (0x1 << S_CCSIDR_WT) /* Support write-through */ +#define S_CCSIDR_WB 30 +#define M_CCSIDR_WB (0x1 << S_CCSIDR_WB) /* Support write-back */ +#define S_CCSIDR_RA 29 +#define M_CCSIDR_RA (0x1 << S_CCSIDR_RA) /* Support read-allocation */ +#define S_CCSIDR_WA 28 +#define M_CCSIDR_WA (0x1 << S_CCSIDR_WA) /* Support write-allocation */ +#define S_CCSIDR_SETS 13 +#define M_CCSIDR_SETS (0x7fff << S_CCSIDR_SETS) /* Number of sets */ +#define S_CCSIDR_A 3 +#define M_CCSIDR_A (0x3ff << S_CCSIDR_A) /* Number of associatiovity */ +#define S_CCSIDR_LS 0 +#define M_CCSIDR_LS (0x7 << S_CCSIDR_LS) /* Cache line size */ + + +/* + * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_WXN (1 << 19) /* Write Permision Imply XN */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ + +#define SCTLR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + : "=r" (val)); \ + val; \ + }) + +#define LEVEL_1 (1 - 1) +#define LEVEL_2 (2 - 1) + +#define CCSIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__( \ + "mrc p15, 1, %0, c0, c0, 0\n\t" \ + : "=r" (val)); \ + val; \ + }) + + +#define sel_CSSELR(InD) \ + __asm__ __volatile__( \ + "mcr p15, 2, %0, c0, c0, 0\n\t" \ + : \ + : "r"(InD)); + +#define _ICACHE_INV_ALL() _ICIALLU() \ + _BPIALL() + +/* + ICIALLU, Instruction Cache Invalidate All to PoU + The ICIALLU characteristics are: + + Invalidate all instruction caches to PoU. If branch predictors are + architecturally visible, also flush branch predictors. + + This register is part of the Cache maintenance instructions functional group. + + Usage constraints + If EL3 is implemented and is using AArch32, this operation can be performed at the following + exception levels: +*/ +#define _ICIALLU() \ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); + +/* + Branch Predictor Invalidate All + The BPIALL characteristics are: + + Invalidate all entries from branch predictors. + This register is part of the Cache maintenance instructions functional group. + Usage constraints + If EL3 is implemented and is using AArch32, this operation can be performed at the following + exception levels: +*/ +#define _BPIALL() \ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); + + +/* + ICIMVAU : Instruction Cache line Invalidate by VA to PoU +*/ +#define _ICACHE_INV_MVAU(addr) _ICIMVAU(addr) +#define _ICIMVAU(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c5, 1\n\t" \ + : \ + : "r"(addr)); + +#define _DCACHE_INV_MVAC(addr) _DCIMVAC(addr) +#define _DCIMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c6, 1\n\t" \ + : \ + : "r"(addr)); + +//DCCMVAC Clean data cache line by VA to PoC +#define _DCACHE_WBACK_MVAC(addr) _DCCMVAC(addr) +#define _DCCMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c10, 1\n\t" \ + : \ + : "r"(addr)); + +//_DCCIMVAC Clean and invalidate data cache line by VA to PoC +#define _DCACHE_WBACK_INV_MVAC(addr) _DCCIMVAC(addr) +#define _DCCIMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c14, 1\n\t" \ + : \ + : "r"(addr)); + +//DCCISW Clean and invalidate data cache line by set/way +#define _DCCISW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c14, 2\n\t" \ + : \ + : "r"(way_set)); + +//DCISW Invalidate data cache line by set/way +/* + The DCISW input value bit assignments are: + + |31......................4 | 3...1 | 0 | + Setway level rsv + bit[3..1] = 0x0 = Level 1 + bit[3..1] = 0x1 = Level 2 + ... +*/ +#define _DCISW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c6, 2\n\t" \ + : \ + : "r"(way_set)); + + +//DCCSW Clean data cache line by set/way +/* + The DCCSW input value bit assignments are: + + |31......................4 | 3...1 | 0 | + Setway level rsv + bit[3..1] = 0x0 = Level 1 + bit[3..1] = 0x1 = Level 2 + ... +*/ +#define _DCCSW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c10, 2\n\t" \ + : \ + : "r"(way_set)) + + + + +/* Cache dirty register () */ +#define read_CDSR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c7, c10, 6\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +/* Get CPU ID */ +#define read_MPIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c0, c0, 5\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +/* ead current CP15 Cache Level ID Register */ +#define read_CLIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 1, %0, c0, c0, 1\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +#define change_property() \ + ({ \ + __asm__ __volatile__( \ + ".arch_extension sec\n\t" \ + "smc #123\n\t" \ + : \ + : \ + ); \ + }) + +#define CLEAR_MMU() \ + __asm__ __volatile__("mcr p15, 0, r0, c8, c7, 0\n\t"); + + +#define DISABLE_MMU() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x1\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define DISABLE_DCACHE() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x4\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define DISABLE_ICACHE() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x1000\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define SETUP_TTBR0(val) \ + ({ \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c2, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) +/* Cache dirty register () */ +#define read_CDSR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c7, c10, 6\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) +/** + @addtogroup mIHALCore +*/ +//@{ + +/** + @name CPU clean invalidate all DCache + + Clean and invalidate all data cache + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCacheAll() cpu_cleanInvalidateDCacheAll() ///< clean invalidate all DCache +//@} + +/** + @name CPU clean invalidate DCache + + Clean and invalidate data cache + Cache line associated with input address will be clean and invalidated + + @param[in] addr data address to be clean and invalidated + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCache(addr) cpu_cleanInvalidateDCache(addr) ///< clean invalidate DCache +//@} + +/** + @name CPU clean invalidate DCache block + + Clean and invalidate data cache block + Cache line associated with input region will be clean and invalidated + + @param[in] m starting data address to be clean and invalidated + @param[in] n end data address to be clean and invalidated + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCacheBlock(m,n) cpu_cleanInvalidateDCacheBlock(m, n) ///< clean invalidate DCache block +//@} + +/** + @name CPU invalidate DCache + + Invalidate data cache + Cache line associated with input address will be invalidated + + @param[in] addr data address to be invalidated + + @return void +*/ +//@{ +#define CPUInvalidateDCache(m) cpu_invalidateDCache(m) ///< invalidate DCache +//@} + +/** + @name CPU invalidate DCache block + + Invalidate data cache block + Cache line associated with input region will be invalidated + + @param[in] m starting data address to be invalidated + @param[in] n end data address to be invalidated + + @return void +*/ +//@{ +#define CPUInvalidateDCacheBlock(m,n) cpu_invalidateDCacheBlock(m,n) ///< invalidate DCache block +//@} + +/** + @name CPU clean DCache + + Clean data cache + Cache line associated with input address will be clean + + @param[in] addr data address to be clean + + @return void +*/ +//@{ +#define CPUCleanDCache(m) cpu_cleanDCache(m) ///< clean DCache +//@} + +/** + @name CPU clean DCache block + + Clean data cache block + Cache line associated with input region will be clean + + @param[in] m starting data address to be clean + @param[in] n end data address to be clean + + @return void +*/ +//@{ +#define CPUCleanDCacheBlock(m, n) cpu_cleanDCacheBlock(m, n) ///< clean DCache block +//@} + +/** + @name CPU invalidate all DCache + + Invalidate all data cache + + @return void +*/ +//@{ +#define CPUInvalidateDCacheAll() cpu_invalidateDCacheAll() ///< invalidate all DCache +//@} + + +extern BOOL CPUChkDCacheEnabled(UINT32 addr); +extern void CPUInvalidateICacheAll(void) __attribute__ ((section (".part1"))); +//extern void CPUInvalidateICacheAll(void) __attribute__ ((section (".part1"), far)); +//extern void CPUInvalidateICache(UINT32 addr); +extern void CPUInvalidateICacheBlock(UINT32 start, UINT32 end); + +#if 0 +extern void CPUInvalidateDCacheAll(void); +extern void CPUInvalidateDCache(UINT32 addr); +extern void CPUInvalidateDCacheBlock(UINT32 start, UINT32 end); +#endif +extern void cpu_invalidateDCacheBlock(UINT32 start, UINT32 end); +extern void cpu_invalidateDCache(UINT32 addr); +extern void cpu_invalidateDCacheAll(void)__attribute__ ((section (".part1"))); +extern void cpu_cleanDCache(UINT32 addr); +extern void cpu_cleanDCacheBlock(UINT32 start, UINT32 end); +extern void _cache_clean_d_cache_all(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); +extern void _cache_invalidate_data_cache_all(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); +extern void _cache_clean_invalidate_d_cache_All(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); + + + +extern void cpu_cleanInvalidateDCacheAll(void)__attribute__ ((section (".part1"))); +//extern void cpu_cleanInvalidateDCacheAll(void)__attribute__ ((section (".part1"), far)); +extern void cpu_cleanInvalidateDCache(UINT32 addr); +extern void cpu_cleanInvalidateDCacheBlock(UINT32 start, UINT32 end); + +extern void CPUflushReadCache(UINT32 uiStartAddr, UINT32 uiLength); +extern void CPUflushWriteCache(UINT32 uiStartAddr, UINT32 uiLength); + + + +#endif + +//@} diff --git a/board/novatek/na51068/loader/Include/Driver/chipset.h b/board/novatek/na51068/loader/Include/Driver/chipset.h new file mode 100755 index 000000000000..6b2456070368 --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/chipset.h @@ -0,0 +1,347 @@ +# ifndef _CHIPSET_H +# define _CHIPSET_H + +/* Copyright (c) 2005 Novatek Microelectronics Corporation + +COMMENT Module Name: +COMMENT Chipset.h + +COMMENT Abstract: +COMMENT Definitions for CPU Mode, Interrupt and Stack +COMMENT This is a shared header file for ASM and C +COMMENT For more information, please refer to http://www.arm.com/support/faqdev/1208.html +COMMENT Only support "# define" now + +COMMENT Notes: +COMMENT Copyright (c) 2005 Novatek Microelectronics Corporation. All Rights Reserved. + +COMMENT Revision History: +COMMENT 03/11/05: Created by Chris Hsu */ + +/* CPU */ + + +#ifndef KNL_SUPPORT_ISR_DUMP_INTERVAL +#define KNL_SUPPORT_ISR_DUMP_INTERVAL 0 +#endif + +#ifndef KNL_SUPPORT_TASK_DUMP_UTILIZATION +#define KNL_SUPPORT_TASK_DUMP_UTILIZATION 0 +#endif + + +# define Mode_USR 0x10 /* M[4:0] = 01010 */ +# define Mode_FIQ 0x11 /* M[4:0] = 10001 */ +# define Mode_IRQ 0x12 /* M[4:0] = 10010 */ +# define Mode_SVC 0x13 /* M[4:0] = 10011 */ +# define Mode_ABT 0x17 /* M[4:0] = 10111 */ +# define Mode_UNDEF 0x1B /* M[4:0] = 11011 */ +# define Mode_SYS 0x1F /* M[4:0] = 11111 */ +# define Mode_MSK 0x1F /* M[4:0] = 11111 */ +# define I_Bit 0x80 /* 7 6 5 4 3 2 1 0 */ +# define F_Bit 0x40 /* I F T M4 M3 M2 M1 M0 */ + +//# define INT_CTRL_ADDR (0xF0080000) +//# define TIMER_CTRL_ADDR (0xF0040000) +# define L2_MEM_BASE (0xf9C20000) +/* + ************************************************************************ + * System Control Register, SCTLR (cp15, 0, c1, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |R|T|A|T|N|0|E|V|1|U|F|U|W|1|H|1|0|R|V|I|Z|S|0|0|B|1|B|1|1|C|A|M| + * | |E|F|R|M| |E|E| | |I|W|X| |A| | | | | | |W| | | | |E| | | | | | + * | | |E|E|F| | | | | | |X|N| | | | | | | | | | | | | |N| | | | | | + * | | | | |I| | | | | | |N| | | | | | | | | | | | | | | | | | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_SCTLR_TE 30 +#define M_SCTLR_TE (0x1 << S_SCTLR_TE) /* Thumb exception enable */ +#define S_SCTLR_AFE 29 +#define M_SCTLR_AFE (0x1 << S_SCTLR_AFE) /* Access flag enable */ +#define S_SCTLR_TRE 28 +#define M_SCTLR_TRE (0x1 << S_SCTLR_TRE) /* TXE remap enable */ +#define S_SCTLR_NMFI 27 +#define M_SCTLR_NMFI (0x1 << S_SCTLR_NMFI) /* None-maskable FIQ enbale (RO) */ +#define S_SCTLR_EE 25 +#define M_SCTLR_EE (0x1 << S_SCTLR_EE) /* Exception Endianness: big-endian */ +#define S_SCTLR_VE 24 +#define M_SCTLR_VE (0x1 << S_SCTLR_VE) /* Interrupt Vector Enable */ +#define S_SCTLR_FI 21 +#define M_SCTLR_FI (0x1 << S_SCTLR_FI) /* Fast interrupt configuraiont enable */ +#define S_SCTLR_UWXN 20 +#define M_SCTLR_UWXN (0x1 << S_SCTLR_UWXN) /* */ +#define S_SCTLR_WXN 19 +#define M_SCTLR_WXN (0x1 << S_SCTLR_WXN) +#define S_SCTLR_HA 17 +#define M_SCTLR_HA (0x1 << S_SCTLR_HA) /* Hardware access flag enable */ +#define S_SCTLR_RR 14 +#define M_SCTLR_RR (0x1 << S_SCTLR_RR) /* Round-robin select */ +#define S_SCTLR_V 13 +#define M_SCTLR_V (0x1 << S_SCTLR_V) /* Vector bits */ +#define S_SCTLR_I 12 +#define M_SCTLR_I (0x1 << S_SCTLR_I) /* Instruction cache enable */ +#define S_SCTLR_Z 11 +#define M_SCTLR_Z (0x1 << S_SCTLR_Z) /* Branch prediction enable */ +#define S_SCTLR_SW 10 +#define M_SCTLR_SW (0x1 << S_SCTLR_SW) /* SW and SWP enable */ +#define S_SCTLR_CP15BEN 5 +#define M_SCTLR_CP15BEN (0x1 << S_SCTLR_CP15BEN) /* CP15 barrier support */ +#define S_SCTLR_C 2 +#define M_SCTLR_C (0x1 << S_SCTLR_C) /* Data and Unidied cache enable */ +#define S_SCTLR_A 1 +#define M_SCTLR_A (0x1 << S_SCTLR_A) /* Alignment fault checking enable */ +#define S_SCTLR_M 0 +#define M_SCTLR_M (0x1 << S_SCTLR_M) /* PL1&0 stage MMU enable */ + +/************************************************************************ + * Auxiliary Control Register, ACTLR (cp15, 0, c1, c0, 1) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |UNP/SBZP |P|A|E|S|RAZ|W|L|L|F| + * | |a|l|X|M| | |1|2|W| + * | |r|l|C|P| |f| | | | + * | | |o|L| | |l|p|p| | + * | |o|c| | | | |r|r| | + * | |n| | | | |z|e|e| | + * | | |o| | | |e|f|f| | + * | | |n| | | |r| | | | + * | | |e| | | |o|e|e| | + * | | | | | | |s|n|n| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_ACTLR_PAR_ON 9 +#define M_ACTLR_PAR_ON (0x1 << S_ACTLR_PAR_ON) /* Parity on */ +#define S_ACTLR_ALLOC_ONE 8 +#define M_ACTLR_ALLOC_ONE (0x1 << S_ACTLR_ALLOC_ONE) /* Alloc in one way */ +#define S_ACTLR_EXCL 7 +#define M_ACTLR_EXCL (0x1 << S_ACTLR_EXCL) /* Exclusive cache */ +#define S_ACTLR_SMP 6 +#define M_ACTLR_SMP (0x1 << S_ACTLR_SMP) /* SMP */ +#define S_ACTLR_W_FL_ZEROS 3 +#define M_ACTLR_W_FL_ZEROS (0x1 << S_ACTLR_W_FL_ZEROS) /* Write full line of zeros mode */ +#define S_ACTLR_L1_PERF_EN 2 +#define M_ACTLR_L1_PERF_EN (0x1 << S_ACTLR_L1_PERF_EN) /* Dside prefetch enable */ +#define S_ACTLR_L2_PERF_EN 1 +#define M_ACTLR_L2_PERF_EN (0x1 << S_ACTLR_L2_PERF_EN) /* L2 prefetch enable */ +#define S_ACTLR_FW 0 +#define M_ACTLR_FW (0x1 << S_ACTLR_FW) /* Cache and TLB maintenance boardcast */ + +#define L2_REG0_BASE (L2_MEM_BASE + 0x000) /* Cache ID and Cache Type */ +#define L2_REG1_BASE (L2_MEM_BASE + 0x100) /* Control */ +#define L2_REG2_BASE (L2_MEM_BASE + 0X200) /* Interrupt and Counter Control Registers */ +#define L2_REG7_BASE (L2_MEM_BASE + 0x700) /* Cache Maintenance Operations */ +#define L2_REG9_BASE (L2_MEM_BASE + 0x900) /* Cache Lockdown */ +#define L2_REG12_BASE (L2_MEM_BASE + 0xC00) /* Address Filtering */ +#define L2_REG15_BASE (L2_MEM_BASE + 0xF00) /* Debug, Prefetch and Power */ + +/** + * Cache ID and Cache Type + */ +#define L2_REG0_CACHE_ID (*((volatile unsigned long *)(L2_REG0_BASE + 0x00))) +#define L2_REG0_CACHE_TYPE (*((volatile unsigned long *)(L2_REG0_BASE + 0x04))) + +#define S_L2_REG0_CACHE_TYPE_DB (31) +#define M_L2_REG0_CACHE_TYPE_DB (0xf << S_L2_REG0_CACHE_TYPE_DB) +#define S_L2_REG0_CACHE_TYPE_CTYPE (25) +#define M_L2_REG0_CACHE_TYPE_CTYPE (0xf << S_L2_REG0_CACHE_TYPE_CTYPE) +#define S_L2_REG0_CACHE_TYPE_H (24) +#define M_L2_REG0_CACHE_TYPE_H (0x1 << S_L2_REG0_CACHE_TYPE_H) +#define S_L2_REG0_CACHE_TYPE_DWS (20) +#define M_L2_REG0_CACHE_TYPE_DWS (0x7 << S_L2_REG0_CACHE_TYPE_DWS) +#define S_L2_REG0_CACHE_TYPE_DA (18) +#define M_L2_REG0_CACHE_TYPE_DA (0x1 << S_L2_REG0_CACHE_TYPE_DA) +#define S_L2_REG0_CACHE_TYPE_DLS (12) +#define M_L2_REG0_CACHE_TYPE_DLS (0x3 << S_L2_REG0_CACHE_TYPE_DLS) +#define S_L2_REG0_CACHE_TYPE_IWS (8) +#define M_L2_REG0_CACHE_TYPE_IWS (0x7 << S_L2_REG0_CACHE_TYPE_IWS) +#define S_L2_REG0_CACHE_TYPE_IA (6) +#define M_L2_REG0_CACHE_TYPE_IA (0x1 << S_L2_REG0_CACHE_TYPE_IA) +#define S_L2_REG0_CACHE_TYPE_ILS (0) +#define M_L2_REG0_CACHE_TYPE_ILS (0x3 << S_L2_REG0_CACHE_TYPE_ILS) + +#define K_L2_REG0_CACHE_TYPE_DA_16WAY (1) +#define K_L2_REG0_CACHE_TYPE_DA_8WAY (0) + + +/** + * Control + */ +#define L2_REG1_CONTROL (*((volatile unsigned long *)(L2_REG1_BASE + 0x00))) +#define L2_REG1_AUX_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x04))) +#define L2_REG1_TAG_RAM_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x08))) +#define L2_REG1_DATA_RAM_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x0C))) + +#define S_L2_REG1_CONTROL_EN (0) +#define M_L2_REG1_CONTROL_EN (0x1 << S_L2_REG1_CONTROL_EN) + +#define K_L2_REG1_CONTROL_EN_ON 1 +#define K_L2_REG1_CONTROL_EN_OFF 0 + +#define S_L2_REG1_AUX_CTRL_BRESP (30) +#define M_L2_REG1_AUX_CTRL_BRESP (0x1 << S_L2_REG1_AUX_CTRL_BRESP) +#define S_L2_REG1_AUX_CTRL_INSTR_PREF (29) +#define M_L2_REG1_AUX_CTRL_INSTR_PREF (0x1 << S_L2_REG1_AUX_CTRL_INSTR_PREF) +#define S_L2_REG1_AUX_CTRL_DATA_PERF (28) +#define M_L2_REG1_AUX_CTRL_DATA_PERF (0x1 << S_L2_REG1_AUX_CTRL_DATA_PERF) +#define S_L2_REG1_AUX_CTRL_NS_INT_CTRL (27) +#define M_L2_REG1_AUX_CTRL_NS_INT_CTRL (0x1 << S_L2_REG1_AUX_CTRL_NS_INT_CTRL) +#define S_L2_REG1_AUX_CTRL_NS_LOCK_EN (26) +#define M_L2_REG1_AUX_CTRL_NS_LOCK_EN (0x1 << S_L2_REG1_AUX_CTRL_NS_LOCK_EN) +#define S_L2_REG1_AUX_CTRL_CACHE_POLICY (25) +#define M_L2_REG1_AUX_CTRL_CACHE_POLICY (0x1 << S_L2_REG1_AUX_CTRL_CACHE_POLICY) +#define S_L2_REG1_AUX_CTRL_FORCE_WA (23) +#define M_L2_REG1_AUX_CTRL_FORCE_WA (0x3 << S_L2_REG1_AUX_CTRL_FORCE_WA) +#define S_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN (22) +#define M_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN (0x1 << S_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN) +#define S_L2_REG1_AUX_CTRL_PARITY_EN (21) +#define M_L2_REG1_AUX_CTRL_PARITY_EN (0x1 << S_L2_REG1_AUX_CTRL_PARITY_EN) +#define S_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN (20) +#define M_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN (0x1 << S_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN) +#define S_L2_REG1_AUX_CTRL_WAT_SIZE (17) +#define M_L2_REG1_AUX_CTRL_WAT_SIZE (0x7 << S_L2_REG1_AUX_CTRL_WAT_SIZE) +#define S_L2_REG1_AUX_CTRL_ASSOCIATIVITY (16) +#define M_L2_REG1_AUX_CTRL_ASSOCIATIVITY (0x1 << S_L2_REG1_AUX_CTRL_ASSOCIATIVITY) +#define S_L2_REG1_AUX_CTRL_SHARED_INV_EN (13) +#define M_L2_REG1_AUX_CTRL_SHARED_INV_EN (0x1 << S_L2_REG1_AUX_CTRL_SHARED_INV_EN) +#define S_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF (12) +#define M_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF (0x1 << S_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF) +#define S_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN (11) +#define M_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN (0x1 << S_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN) +#define S_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN (10) +#define M_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN (0x1 << S_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN) +#define S_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN (0) +#define M_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN (0x1 << S_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN) + +#define reg0_cache_type_ofs 0x004 //reg0_cache_type +#define CACHE_CTRL_REG_OFS 0x100 +#define CACHE_AUX_CTRL_REG_OFS 0x104 + +#define CACHE_TAG_RAM_CTRL_OFS 0x108 +#define CACHE_DATA_RAM_CTRL_OFS 0x10C + +#define reg2_int_clear_ofs 0x220 //reg2_int_clear +#define reg7_cache_sync 0x730 //reg7_cache_sync +#define reg7_inv_way 0x77C //reg7_inv_way +#define CACHE_PREFETCH_REG_OFS 0xF60 + + +/** + * Interrupt and Counter Control Registers + */ +#define L2_REG2_EV_CNT_CTRL (*((volatile unsigned long *)(L2_REG2_BASE + 0x00))) +#define L2_REG2_EV_CNT1_CFG (*((volatile unsigned long *)(L2_REG2_BASE + 0x04))) +#define L2_REG2_EV_CNT0_CFG (*((volatile unsigned long *)(L2_REG2_BASE + 0x08))) +#define L2_REG2_EV_CNT1 (*((volatile unsigned long *)(L2_REG2_BASE + 0x0C))) +#define L2_REG2_EV_CNT0 (*((volatile unsigned long *)(L2_REG2_BASE + 0x10))) +#define L2_REG2_INT_MASK (*((volatile unsigned long *)(L2_REG2_BASE + 0x14))) +#define L2_REG2_INT_MASK_STATUS (*((volatile unsigned long *)(L2_REG2_BASE + 0x18))) +#define L2_REG2_INT_RAW_STATUS (*((volatile unsigned long *)(L2_REG2_BASE + 0x1C))) +#define L2_REG2_INT_CLEAR (*((volatile unsigned long *)(L2_REG2_BASE + 0x20))) + +#define S_L2_REG2_INT_DECERR (8) +#define M_L2_REG2_INT_DECERR (0x1 << S_L2_REG2_INT_DECERR) /* Decode error */ +#define S_L2_REG2_INT_SLVERR (7) +#define M_L2_REG2_INT_SLVERR (0x1 << S_L2_REG2_INT_SLVERR) /* Slave error */ +#define S_L2_REG2_INT_ERRRD (6) +#define M_L2_REG2_INT_ERRRD (0x1 << S_L2_REG2_INT_ERRRD) /* Data RAM read error */ +#define S_L2_REG2_INT_ERRRT (5) +#define M_L2_REG2_INT_ERRRT (0x1 << S_L2_REG2_INT_ERRRT) /* Tag RAM read error */ +#define S_L2_REG2_INT_ERRWD (4) +#define M_L2_REG2_INT_ERRWD (0x1 << S_L2_REG2_INT_ERRWD) /* Data RAM write error */ +#define S_L2_REG2_INT_ERRWT (3) +#define M_L2_REG2_INT_ERRWT (0x1 << S_L2_REG2_INT_ERRWT) /* Tag RAM write error */ +#define S_L2_REG2_INT_PARRD (2) +#define M_L2_REG2_INT_PARRD (0x1 << S_L2_REG2_INT_PARRD) /* Parity error on data RAM read */ +#define S_L2_REG2_INT_PARRT (1) +#define M_L2_REG2_INT_PARRT (0x1 << S_L2_REG2_INT_PARRT) /* Pariry error on tag RAM read */ +#define S_L2_REG2_INT_ECNTR (0) +#define M_L2_REG2_INT_ECNTR (0x1 << S_L2_REG2_INT_ECNTR) /* Event counter1/0 overflow increment */ + +/** + * Cache Maintenance Operations + */ +#define L2_REG7_CACHE_SYNC (*((volatile unsigned long *)(L2_REG7_BASE + 0x30))) +#define L2_REG7_INV_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0x70))) +#define L2_REG7_INV_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0x7C))) +#define L2_REG7_CLEAN_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0xB0))) +#define L2_REG7_CLEAN_INDEX (*((volatile unsigned long *)(L2_REG7_BASE + 0xB8))) +#define L2_REG7_CLEAN_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0xBC))) +#define L2_REG7_CLEAN_INV_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0xF0))) +#define L2_REG7_CLEAN_INV_INDEX (*((volatile unsigned long *)(L2_REG7_BASE + 0xF8))) +#define L2_REG7_CLEAN_INV_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0xFC))) + + +#define K_L2_REG7_CACHE_SYNC_C (0x1) + +#define K_L2_REG7_INV_WAY_8WAY (0x00ff) +#define K_L2_REG7_INV_WAY_16WAY (0xffff) +#define K_L2_REG7_CLEAN_WAY_8WAY (0x00ff) +#define K_L2_REG7_CLEAN_WAY_16WAY (0xffff) +#define L2_INT_CLEAR_STATUS 0x1FF +/** + * Cache Lockdown + */ +#define L2_REG9_D_LOCKDOWN0 (*((volatile unsigned long *)(L2_REG9_BASE + 0x00))) +#define L2_REG9_I_LOCKDOWN0 (*((volatile unsigned long *)(L2_REG9_BASE + 0x04))) +#define L2_REG9_D_LOCKDOWN1 (*((volatile unsigned long *)(L2_REG9_BASE + 0x08))) +#define L2_REG9_I_LOCKDOWN1 (*((volatile unsigned long *)(L2_REG9_BASE + 0x0C))) +#define L2_REG9_D_LOCKDOWN2 (*((volatile unsigned long *)(L2_REG9_BASE + 0x10))) +#define L2_REG9_I_LOCKDOWN2 (*((volatile unsigned long *)(L2_REG9_BASE + 0x14))) +#define L2_REG9_D_LOCKDOWN3 (*((volatile unsigned long *)(L2_REG9_BASE + 0x18))) +#define L2_REG9_I_LOCKDOWN3 (*((volatile unsigned long *)(L2_REG9_BASE + 0x1C))) +#define L2_REG9_D_LOCKDOWN4 (*((volatile unsigned long *)(L2_REG9_BASE + 0x20))) +#define L2_REG9_I_LOCKDOWN4 (*((volatile unsigned long *)(L2_REG9_BASE + 0x24))) +#define L2_REG9_D_LOCKDOWN5 (*((volatile unsigned long *)(L2_REG9_BASE + 0x28))) +#define L2_REG9_I_LOCKDOWN5 (*((volatile unsigned long *)(L2_REG9_BASE + 0x2C))) +#define L2_REG9_D_LOCKDOWN6 (*((volatile unsigned long *)(L2_REG9_BASE + 0x30))) +#define L2_REG9_I_LOCKDOWN6 (*((volatile unsigned long *)(L2_REG9_BASE + 0x34))) +#define L2_REG9_D_LOCKDOWN7 (*((volatile unsigned long *)(L2_REG9_BASE + 0x38))) +#define L2_REG9_I_LOCKDOWN7 (*((volatile unsigned long *)(L2_REG9_BASE + 0x3C))) +#define L2_REG9_LOCK_LINE_EN (*((volatile unsigned long *)(L2_REG9_BASE + 0x50))) +#define L2_REG9_UNLOCK_WAY (*((volatile unsigned long *)(L2_REG9_BASE + 0x54))) + +/** + * Address Filtering + */ +#define L2_REG12_ADDR_FILTERING_START (*((volatile unsigned long *)(L2_REG12_BASE + 0x00))) +#define L2_REG12_ADDR_FILTERING_END (*((volatile unsigned long *)(L2_REG12_BASE + 0x04))) + +/** + * Debug, Prefetch and Power + */ +#define L2_REG15_DEBUG_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x40))) +#define L2_REG15_PREF_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x60))) +#define L2_REG15_POWER_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x80))) + +#define S_L2_REG15_DEBUG_CTRL_SPNIDEN (2) +#define M_L2_REG15_DEBUG_CTRL_SPNIDEN (0x1 << S_L2_REG15_DEBUG_CTRL_SPNIDEN) +#define S_L2_REG15_DEBUG_CTRL_DWB (1) +#define M_L2_REG15_DEBUG_CTRL_DWB (0x1 << S_L2_REG15_DEBUG_CTRL_DWB) +#define S_L2_REG15_DEBUG_CTRL_DCL (0) +#define M_L2_REG15_DEBUG_CTRL_DCL (0x1 << S_L2_REG15_DEBUG_CTRL_DCL) + +#define S_L2_REG15_PREF_CTRL_DL_FILL_EN (30) +#define M_L2_REG15_PREF_CTRL_DL_FILL_EN (0x1 << S_L2_REG15_PREF_CTRL_DL_FILL_EN) +#define S_L2_REG15_PREF_CTRL_INST_PREF_EN (29) +#define M_L2_REG15_PREF_CTRL_INST_PREF_EN (0x1 << S_L2_REG15_PREF_CTRL_INST_PREF_EN) +#define S_L2_REG15_PREF_CTRL_DATA_PREF_EN (28) +#define M_L2_REG15_PREF_CTRL_DATA_PREF_EN (0x1 << S_L2_REG15_PREF_CTRL_DATA_PREF_EN) +#define S_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS (27) +#define M_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS (0x1 << S_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS) +#define S_L2_REG15_PREF_CTRL_PREF_DROP_EN (24) +#define M_L2_REG15_PREF_CTRL_PREF_DROP_EN (0x1 << S_L2_REG15_PREF_CTRL_PREF_DROP+EN) +#define S_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN (23) +#define M_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN (0x1 << S_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN) +#define S_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN (21) +#define M_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN (0x1 << S_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN) +#define S_L2_REG15_PREF_CTRL_PREF_OFF (0) +#define M_L2_REG15_PREF_CTRL_PREF_OFF (0xf << S_L2_REG15_PREF_CTRL_PREF_OFF) +# endif + diff --git a/board/novatek/na51068/loader/Include/Driver/crypto.h b/board/novatek/na51068/loader/Include/Driver/crypto.h new file mode 100755 index 000000000000..8f59d8893e56 --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/crypto.h @@ -0,0 +1,97 @@ +/** + Header file for CC (Core Communicator) module. + + This file is the header file that define the API and data type + for CC module. + + @file CC.h + @ingroup mIDrvSys_CC + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ + +#include "constant.h" + +#ifndef _CRYPTO_H +#define _CRYPTO_H + +#define ROM_AES_SIZE (16) +#define ROM_SHA_SIZE (32) // unit: byte +#define ROM_RSA_SIZE (256) // RSA-2048 +#define ROM_RSA_EKEY_SIZE (32) +#define ROM_RSA_CRC32_SIZE (4) +/** + Crypto engine crypto mode +*/ +typedef enum { + CRYPTO_RSV0, + CRYPTO_RSV1, + CRYPTO_AES, ///< Select Crypto mode AES + CRYPTO_MODE_NUM, +} CRYPTO_MODE; + +/** + Crypto engine crypto Operating mode +*/ +typedef enum { + CRYPTO_EBC = 0x00, ///< Select Crypto opmode EBC + CRYPTO_CBC, ///< Select Crypto opmode CBC + CRYPTO_OPMODE_NUM, +} CRYPTO_OPMODE; + +/** + Crypto engine encrypt or decrypt +*/ +typedef enum { + CRYPTO_ENCRYPT = 0x00, ///< Select Crypto engine encrypt + CRYPTO_DECRYPT, ///< Select Crypto engine decrypt + CRYPTO_TYPE_NUM, + +} CRYPTO_TYPE; + +typedef enum { + EFUSE_OTP_1ST_KEY_SET_FIELD = 0x0, // This if for secure boot + EFUSE_OTP_2ND_KEY_SET_FIELD, + EFUSE_OTP_3RD_KEY_SET_FIELD, + EFUSE_OTP_4TH_KEY_SET_FIELD, + + EFUSE_OTP_TOTAL_KEY_SET_FIELD, +} EFUSE_OTP_KEY_SET_FIELD; + +typedef struct _CRYPT_OP { + CRYPTO_OPMODE op_mode; ///< Operation Mode (now support ECB only) + CRYPTO_TYPE en_de_crypt; ///< Encrypt or decrypt (CRYPTO_ENCRYPT or CRYPTO_DECRYPT) + UINT32 src_addr; ///< Source address + UINT32 dst_addr; ///< Destination address + UINT32 length; ///< length +} CRYPT_OP; + +/** + Crypto engine check +*/ +typedef enum { + SECUREBOOT_SECURE_EN = 0x00, ///< Quary if secure enable or not + SECUREBOOT_DATA_AREA_ENCRYPT, ///< Quary if data area encrypt to cypher text or not + SECUREBOOT_SIGN_RSA, ///< Quary if Signature methed is RSA or not(AES) + SECUREBOOT_SIGN_RSA_CHK, ///< Quary if Signature hash checksum RSA key correct or not + SECUREBOOT_STATUS_NUM, + +} SECUREBOOT_STATUS; + +#define is_secure_enable() quary_secure_boot(SECUREBOOT_SECURE_EN) //For backward compatitable +#define is_data_area_encrypted() quary_secure_boot(SECUREBOOT_DATA_AREA_ENCRYPT) //For backward compatitable +#define is_signature_rsa() quary_secure_boot(SECUREBOOT_SIGN_RSA) //For backward compatitable +#define is_signature_aes() !quary_secure_boot(SECUREBOOT_SIGN_RSA) //For backward compatitable +BOOL quary_secure_boot(SECUREBOOT_STATUS scu_status); +UINT32 crypto_data_operation(EFUSE_OTP_KEY_SET_FIELD key_set, CRYPT_OP crypt_op_param); +void rsa_setConfig(UINT32 mode); +void rsa_setkey_n(UINT8* key, UINT32 len); +void rsa_setkey_ed(UINT8* key, UINT32 len); +INT32 rsa_pio_enable(UINT8* data, UINT32 len); +void rsa_getOutput(UINT8 * Output, UINT32 len); +void shahw( const unsigned char *input, int ilen, UINT32 output[8]); +void rsa_decrypt(UINT32 *input ,UINT32 input_len, UINT32 *pRSAN, UINT32 RSAN_len, UINT32 *pRSAED, UINT32 RSAED_len , UINT32 *pShaOut); +BOOL rsa_keycheck(UINT32 *input , BOOL efuseCheck); + +#endif diff --git a/board/novatek/na51068/loader/Include/Driver/mmc.h b/board/novatek/na51068/loader/Include/Driver/mmc.h new file mode 100755 index 000000000000..1c04929cb08a --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/mmc.h @@ -0,0 +1,232 @@ +#ifndef __MMC_H__ +#define __MMC_H__ + +#define CONFIG_WITH_SDC_INIT + +#define SD_VERSION_SD 0x20000 +#define SD_VERSION_3 (SD_VERSION_SD | 0x300) +#define SD_VERSION_2 (SD_VERSION_SD | 0x20) +#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10) +#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a) +#define MMC_VERSION_MMC 0x10000 +#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) +#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12) +#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14) +#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22) +#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30) +#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40) + +#define MMC_MODE_HS 0x001 +#define MMC_MODE_HS_52MHz 0x010 +#define MMC_MODE_4BIT 0x100 +#define MMC_MODE_8BIT 0x200 +#define MMC_MODE_SPI 0x400 +#define MMC_MODE_HC 0x800 + +#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) +#define MMC_MODE_WIDTH_BITS_SHIFT 8 + +#define SD_DATA_4BIT 0x00040000 + +#define IS_SD(x) (x->version & SD_VERSION_SD) + +#define MMC_DATA_READ 1 +#define MMC_DATA_WRITE 2 + +#define NO_CARD_ERR -16 /* No SD/MMC card inserted */ +#define UNUSABLE_ERR -17 /* Unusable Card */ +#define COMM_ERR -18 /* Communications Error */ +#define TIMEOUT -19 + +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SWITCH 6 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_EXT_CSD 8 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_STOP_TRANSMISSION 12 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_SINGLE_BLOCK 24 +#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 +#define MMC_CMD_ERASE_GROUP_START 35 +#define MMC_CMD_ERASE_GROUP_END 36 +#define MMC_CMD_ERASE 38 +#define MMC_CMD_APP_CMD 55 +#define MMC_CMD_SPI_READ_OCR 58 +#define MMC_CMD_SPI_CRC_ON_OFF 59 + +#define SD_CMD_SEND_RELATIVE_ADDR 3 +#define SD_CMD_SWITCH_FUNC 6 +#define SD_CMD_SEND_IF_COND 8 + +#define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_ERASE_WR_BLK_START 32 +#define SD_CMD_ERASE_WR_BLK_END 33 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_SEND_SCR 51 + +/* SCR definitions in different words */ +#define SD_HIGHSPEED_BUSY 0x00020000 +#define SD_HIGHSPEED_SUPPORTED 0x00020000 + +#define MMC_HS_TIMING 0x00000100 +#define MMC_HS_52MHZ 0x2 + +#define OCR_BUSY 0x80000000 +#define OCR_HCS 0x40000000 +#define OCR_VOLTAGE_MASK 0x007FFF80 +#define OCR_ACCESS_MODE 0x60000000 + +#define SECURE_ERASE 0x80000000 + +#define MMC_STATUS_MASK (~0x0206BF7F) +#define MMC_STATUS_RDY_FOR_DATA (1 << 8) +#define MMC_STATUS_CURR_STATE (0xf << 9) +#define MMC_STATUS_ERROR (1 << 19) + +#define MMC_STATE_PRG (7 << 9) + +#if 0 +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#endif +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + /* Change the command set */ +#define MMC_SWITCH_MODE_CMD_SET 0x00 +/* Set bits in EXT_CSD byte addressed by index which are 1 in value field */ +#define MMC_SWITCH_MODE_SET_BITS 0x01 + /* Clear bits in EXT_CSD byte addressed by index, which are 1 in value field */ +#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 +/* Set target byte to value */ +#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 + +#define SD_SWITCH_CHECK 0 +#define SD_SWITCH_SWITCH 1 + +/* + * EXT_CSD fields + */ + +#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ +#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ +#define EXT_CSD_PART_CONF 179 /* R/W */ +#define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ +#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_BOOT_MULT 226 /* RO */ + +/* + * EXT_CSD field definitions + */ + +#define EXT_CSD_CMD_SET_NORMAL (1 << 0) +#define EXT_CSD_CMD_SET_SECURE (1 << 1) +#define EXT_CSD_CMD_SET_CPSECURE (1 << 2) + +#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ + +#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) + +#define MMCPART_NOAVAILABLE (0xff) +#define PART_ACCESS_MASK (0x7) +#define PART_SUPPORT (0x1) + +struct mmc_cmd { + uint cmdidx; + uint resp_type; + uint cmdarg; + uint response[4]; +}; + +struct mmc_data { + char *paddr; + uint flags; + uint blocks; + uint blocksize; +}; + +struct mmc { + void *priv; + uint voltages; + uint version; + uint has_init; + uint f_min; + uint f_max; + int high_capacity; + uint bus_width; + uint clock; + uint card_caps; + uint host_caps; + uint ocr; + uint scr[2]; + //uint csd[4]; + //uint cid[4]; + uint rca; + uint tran_speed; + uint read_bl_len; + uint write_bl_len; + uint erase_grp_size; + u32 capacity; + int (*send_cmd)(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data); +#ifdef CONFIG_WITH_SDC_INIT + void (*set_ios)(struct mmc *mmc); + int (*init)(struct mmc *mmc); +#endif + uint b_max; +}; + +int mmc_init(struct mmc *mmc); +struct mmc *get_mmc(void); +int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data); + +void sdhci_set_ios(struct mmc *mmc); +int sdhci_init(struct mmc *mmc); + +#endif /* __MMC_H__ */ diff --git a/board/novatek/na51068/loader/Include/Driver/mmc_api.h b/board/novatek/na51068/loader/Include/Driver/mmc_api.h new file mode 100755 index 000000000000..c15f6fbbee82 --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/mmc_api.h @@ -0,0 +1,13 @@ +#ifndef __MMC_API_H__ +#define __MMC_API_H__ + +int add_sdhci (void); +int mmc_bread(unsigned long start, unsigned long blkcnt, unsigned long dst); +//int mmc_loader(unsigned int load_addr, UINT8 * p_run_filename, UINT8 * p_update_filename, UINT32 * uiLoaderFunc); + +INT32 card_open(void); +void card_close(void); + + + +#endif /* __MMC_API_H__ */ diff --git a/board/novatek/na51068/loader/Include/Driver/nand.h b/board/novatek/na51068/loader/Include/Driver/nand.h new file mode 100755 index 000000000000..bb1d2112482c --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/nand.h @@ -0,0 +1,118 @@ +/** + nand module driver. + + This file is the driver of storage module. + + @file nand.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _NAND_DEF_ +#define _NAND_DEF_ + +#include "board.h" + +#define _SNAND_WINBOND_ID (0xEF) +#define _SNAND_ESMT_ID (0xC8) +#define _SNAND_GD_ID (0xC8) +#define _SNAND_MICRON_ID (0x2C) +#define _SNAND_ATO_ID (0x9B) +#define _SNAND_ETRON_ID (0xD5) +#define _SNAND_MXIC_ID (0xC2) +#define _SNAND_TOSHIBA_ID (0x98) + + + +#define _GD_SPI_NAND_1Gb (0xF1) +#define _MXIC_SPI_NAND_1Gb (0x12) + +/** + SPI NAND flash QE(quid enable) identify type + +*/ +//@{ +typedef enum { + SPINAND_QE_NONE = 0x0, ///< SPI NAND flash not with QE bit(only by quad command) + SPINAND_QE_FEATURE2_B0H_BIT0_TYPE1, ///< SPI NAND flash QE bit locate at feature field(0xB0H) bit[0] +} SPINAND_QE_TYPE; + + +/** + SPI NAND flash twp plane identify type + +*/ +//@{ +typedef enum { + SPINAND_2_PLANE_NONE = 0x0, ///< SPI NAND flash not 2 plane type + SPINAND_2_PLANE_COLUMN_ADDR_BIT_12_AS_PLANE_SEL,///< SPI NAND flash use column addr bit[12] as plane select +} SPINAND_PLANE_TYPE; + + + +/** + SPI flash identification structure + + @note For SPIFLASH_IDENTIFY_CB +*/ +typedef struct { + UINT32 pagesize; + UINT32 erasesize; + UINT32 qe_opt; + UINT32 plane_opt; +} SPINAND_IDENTIFY, *PSPINAND_IDENTIFY; + +/** + SPIFLASH identify callback + + Callback routine to be invoked after JEDEC ID is read from spi flash. + Callback routine should check if read ID is supported. + + @note STRG_EXT_CMD_SPI_IDENTIFY_CB + + @param[in] first parameter (JEDEC) manufacturer ID read from spi flash + @param[in] second parameter (JEDEC) type ID read from spi flash + @param[in] third parameter (JEDEC) capacity ID read from spi flash + @param[out] forth parameter flash identification returned to spi flash driver + + @return + - @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information + - @b FALSE: input ID is NOT supported/identified by call back +*/ +typedef BOOL (*SPINAND_IDENTIFY_CB)(UINT32, UINT32, PSPINAND_IDENTIFY); + + + + +/** + * struct nand_flash_dev - NAND Flash Device ID Structure + * @mfr_id: manufecturer ID part of the full chip ID array (refers the same + * memory address as @id[0]) + * @dev_id: the device ID (the second byte of the full chip ID array) + * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as + * well as the eraseblock size) is determined from the extended NAND + * chip ID array) + * @erasesize: NAND block size + * @qe_opt: Quad enable type(please reference document to select this option) + * @plane_opt: 2 plane nand option(please reference document to select this option) + * @options: stores various chip bit options + * + */ +typedef struct _nand_flash_dev { + UINT32 mfr_id; + UINT32 dev_id; + UINT32 pagesize; + UINT32 erasesize; + UINT32 qe_opt; + UINT32 plane_opt; +} NAND_FLASH_DEV, *PNAND_FLASH_DEV; + +#define SPI_ID_NAND(mfrid, devid, pagesz, erasesz, opts, plane_opt_type)\ + { .mfr_id =(mfrid), .dev_id = (devid), .pagesize = (pagesz), \ + .erasesize = (erasesz), .qe_opt = (opts), .plane_opt=(plane_opt_type) } + +extern BOOL nand_identify(UINT32 uiMfgID, UINT32 uiTypeID, PSPINAND_IDENTIFY pIdentify); + +#endif diff --git a/board/novatek/na51068/loader/Include/Driver/nor.h b/board/novatek/na51068/loader/Include/Driver/nor.h new file mode 100755 index 000000000000..c8ae1a44c77b --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/nor.h @@ -0,0 +1,51 @@ +/** + nand module driver. + + This file is the driver of storage module. + + @file nand.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _NOR_DEF_ +#define _NOR_DEF_ + +#include "board.h" +#include "StorageDef.h" + + +/** + * struct nand_flash_dev - NAND Flash Device ID Structure + * @name: a human-readable name of the NAND chip + * @dev_id: the device ID (the second byte of the full chip ID array) + * @mfr_id: manufecturer ID part of the full chip ID array (refers the same + * memory address as @id[0]) + * @dev_id: device ID part of the full chip ID array (refers the same memory + * address as @id[1]) + * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as + * well as the eraseblock size) is determined from the extended NAND + * chip ID array) + * @chipsize: total chip size in MiB + * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) + * @options: stores various chip bit options + * + */ +typedef struct _nor_flash_dev { + UINT32 mfr_id; + UINT32 dev_id; + UINT32 capacity_id; + UINT32 bDualRead; + UINT32 uiQuadReadType; + UINT32 uiFlashSize; +} NOR_FLASH_DEV, *PNOR_FLASH_DEV; + +#define SPI_ID_NOR(mfrid, devid, capacityid, dual_read, quad_read_type, flash_size)\ + { .mfr_id =(mfrid), .dev_id = (devid), .capacity_id =(capacityid), .bDualRead=(dual_read), \ + .uiQuadReadType=(quad_read_type), .uiFlashSize=(flash_size) } + + +extern BOOL nor_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify); +#endif diff --git a/board/novatek/na51068/loader/Include/Driver/pll.h b/board/novatek/na51068/loader/Include/Driver/pll.h new file mode 100755 index 000000000000..ff65b52bed23 --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/pll.h @@ -0,0 +1,24 @@ +#ifndef __PLL_H__ +#define __PLL_H__ + + /* + CPU 1200=0x027fff 0x01aaaa + DSP 800=0x855555 0x640000 + codec 400=0x42aaaa 0x3a5555 + ddr0 466=0x4daaaa 0x42aaaa + ddr1 466=0x42aaaa 0x42aaaa + */ +#ifdef MODE0//CPU 800, DSP 600, codec 350, ddr0 1600, ddr1 1600 + unsigned int PLL[5] = {0x01aaaa, 0x640000, 0x3a5555, 0x42aaaa, 0x42aaaa}; +#endif +#ifdef MODE1 + unsigned int PLL[5] = {0x01aaaa, 0x640000, 0x3a5555, 0x42aaaa, 0x42aaaa}; +#endif +#ifdef MODE2 + unsigned int PLL[5] = {0x01aaaa, 0x640000, 0x3a5555, 0x42aaaa, 0x42aaaa}; +#endif +#ifdef MODE3 + unsigned int PLL[5] = {0x01aaaa, 0x640000, 0x3a5555, 0x42aaaa, 0x42aaaa}; +#endif + +#endif \ No newline at end of file diff --git a/board/novatek/na51068/loader/Include/Driver/rcw_macro.h b/board/novatek/na51068/loader/Include/Driver/rcw_macro.h new file mode 100755 index 000000000000..032ea838a57c --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/rcw_macro.h @@ -0,0 +1,205 @@ +/* + Driver Register Cache Word (RCW) operation header file. + + Driver Register Cache Word (RCW) operation header file. + The macros defined in this header file is used to simply the register + bit field read and write. By adapting this way of register access, + it shall provide more error-proof and more readable way to write + drivers. It also does register access in load/store way which allow + one to accurately control the number of counts the register read and + write is proceeded from code writing. + + @file RCWMacro.h + @ingroup mIDriver + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2010. All rights reserved. +*/ + +#ifndef __ASM_ARCH_NVT_IVOT_RCW_MACRO_H +#define __ASM_ARCH_NVT_IVOT_RCW_MACRO_H +#include "constant.h" + +/** + @addtogroup mIDriver +*/ +//@{ + +/* + Translate DRAM address to non-cacheable address. + + Translate DRAM address to non-cacheable address. + + @param[in] addr DRAM address + + @return non-cacheable DRAM address +*/ +#define dma_getNonCacheAddr(addr) ((((UINT32)(addr))<0x60000000UL)?((UINT32)(addr)+0x60000000UL):(UINT32)(addr)) + + +#define dma_getPhyAddr(addr) ((((UINT32)(addr))>=0x60000000UL)?((UINT32)(addr)-0x60000000UL):(UINT32)(addr)) + +/** + Translate DRAM address to cacheable address. + + Translate DRAM address to cacheable address. + + @param[in] addr DRAM address + + @return Cacheable DRAM address +*/ +#define dma_getCacheAddr(addr) ((((UINT32)(addr))>=0x60000000UL)?((UINT32)(addr)-0x60000000UL):(UINT32)(addr)) + + +// +// Register word value type +// +// The size in bits of this type should match the RCW type +#define REGVALUE UINT32 + +#define UBITFIELD unsigned int /* Unsigned bit field */ +#define BITFIELD signed int /* Signed bit field */ + + +#define FALSE 0 +#define TRUE 1 + +/** + @name Assert macros +*/ +//@{ +#define ASSERT_CONCAT_(a, b) a##b +#define ASSERT_CONCAT(a, b) ASSERT_CONCAT_(a, b) + +#if defined(__COUNTER__) + +#define STATIC_ASSERT(expr) \ +enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __COUNTER__) = 1/(expr) } + +#else + +// This might cause compile error when writing STATIC_ASSERT at the same line +// in two (or more) files and one file include another one. +#define STATIC_ASSERT(expr) \ +enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __LINE__) = 1/(expr) } + +#endif + +#ifndef OUTW +#define OUTW(addr,value) (*(REGVALUE volatile *)(addr) = (REGVALUE)(value)) +#endif + +#ifndef INW +#define INW(addr) (*(REGVALUE volatile *)(addr)) +#endif + +#define INREG8(x) (*((volatile UINT8*)x)) +#define OUTREG8(x, y) (*((volatile UINT8*)x) = (y)) +#define SETREG8(x, y) OUTREG8(x, INREG8(x) | (y)) +#define CLRREG8(x, y) OUTREG8(x, INREG8(x) & ~(y)) + +#define OUTREG32(x, y) (*((volatile UINT32*)(x)) = (y)) ///< Write 32bits IO register +#define INREG32(addr) (*(UINT32 volatile *)(addr)) + +#define SETREG32(x, y) OUTREG32((x), INREG32(x) | (y)) +#define CLRREG32(x, y) OUTREG32((x), INREG32(x) & ~(y)) +#define SETCLRREG32(x, y, z) OUTREG32((x), (INREG32(x) & ~(z)) | (y)) + +// +// Macros for Register Cache Word (RCW) type definition +// +// Each RCW type should be exactly the same size with REGVALUE type +// For example, to declare a Register Cache Word type: +// +// #define rcwname_OFS 0x00 /* the name of RCW corresponding register address offset +// should be in specific format with "_OFS" appended */ +// REGDEF_BEGIN(rcwname) +// REGDEF_BIT(field1, 8) /* declare field1 as 8 bits width */ +// REGDEF_BIT(field2, 8) /* declare field1 as 8 bits width */ +// REGDEF_BIT(, 16) /* pad reserved (not-used) bits to fill RCW type same as REGVALUE size */ +// REGDEF_END(rcwname) +// +// Register Cache Word type defintion header +#define REGDEF_BEGIN(name) \ +typedef union \ +{ \ + REGVALUE reg; \ + struct \ + { + +// Register Cache Word bit defintion +#define REGDEF_BIT(field, bits) \ + UBITFIELD field : bits; + +// Register Cache Word type defintion trailer +#define REGDEF_END(name) \ + } bit; \ +} T_##name; \ +STATIC_ASSERT(sizeof(T_##name) == sizeof(REGVALUE)); + +// Macro to define register offset +#define REGDEF_OFFSET(name, ofs) static const UINT32 name##_OFS=(ofs); + +// +// Macros for prerequisite stuff initialization for Register Cache Word +// operations +// +// Macro to set register base address for current module +// One must call this macro somewhere to set register I/O base address for +// current module, either globally or locally before any RCW operations is +// invoked +// What this macro set is only effective in current C file +#define REGDEF_SETIOBASE(base) static const UINT32 _REGIOBASE=(base) + +// Macro to set register repeat group offset address in byte +// This macro is optional and only used where register with repeat group exist, +// only one repeat group is allowed in one file +// If registers with repeat group exist, then one only have to define the RCW type +// for the first group, respective group of registers can be accessed through +// RCW_LD2, RCW_ST2, RCW_LD2OF macros +// What this macro set is only effective in current C file +#define REGDEF_SETGRPOFS(grpofs) static const UINT32 _REGGRPOFS=(grpofs) + +// +// Macros for Register Cache Word (RCW) operations +// +// These RCW operations are most likely to be used inside C functions +// It is not recommended to use RCW_DEF(RCW) in global scope which +// declare RCW as global variable +// RCW_LD/RCW_ST/RCW_LDOF pair is for normal single register access while +// RCW_LD2/RCW_ST2/RCW_LD2OF pair is for repeat group register access +// Beware that the RCW_LD/RCW_ST/RCW_LDOF and RCW_LD2/RCW_ST2/RCW_LD2OF +// must not be mixed used. e.g. use RCW_LD then RCW_ST2 or use RCW_LD2 then RCW_ST +// +// Register Cache Word declaration +#define RCW_DEF(RCW) T##_##RCW t##RCW +// Register Cache Word read from I/O +#define RCW_LD(RCW) t##RCW.reg = INW(_REGIOBASE+RCW##_OFS) +// Register Cache Word repeat from I/O for group read +#define RCW_LD2(RCW, grpidx) t##RCW.reg = INW(_REGIOBASE+RCW##_OFS+(grpidx)*_REGGRPOFS) +// Register Cache Word bit reference +#define RCW_OF(RCW) t##RCW.bit +// Register Cache Word reference +#define RCW_VAL(RCW) t##RCW.reg +// Register Cache Word write to I/O +#define RCW_ST(RCW) OUTW(_REGIOBASE+RCW##_OFS, t##RCW.reg) +// Register Cache Word write to I/O for repeat group +#define RCW_ST2(RCW, grpidx) OUTW(_REGIOBASE+RCW##_OFS+(grpidx)*_REGGRPOFS, t##RCW.reg) +// Register Cache Word read and reference to register cache word bit +// !!!need to check for compiler if support for this syntax +#define RCW_LDOF(RCW) ((T##_##RCW)(RCW_LD(RCW))).bit +// Register Cache Word read and reference to register cache word bit for repeat group +// !!!need to check for compiler if support for this syntax +#define RCW_LD2OF(RCW, grpidx) ((T##_##RCW)(RCW_LD2(RCW, grpidx))).bit + +#define rcw_get_phy_addr(addr) ((addr) & 0x1FFFFFFF) + + /** + Macro to generate dummy element for enum type to expand enum size to word (4 bytes) + */ + //@{ + #define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + //@} +//@} + +#endif /* __ASM_ARCH_NVT_IVOT_RCW_MACRO_H */ diff --git a/board/novatek/na51068/loader/Include/Driver/regdef.h b/board/novatek/na51068/loader/Include/Driver/regdef.h new file mode 100755 index 000000000000..4805c4c0d506 --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/regdef.h @@ -0,0 +1,311 @@ +/* + * MIPS register definitions, originally from: + * + * include/asm-mips/regdefs.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License, Version 2. See the file "COPYING" in the main directory of this + * archive for more details. + * + * Copyright (C) 1994, 1995 by Ralf Baechle + */ + +/* + * Symbolic register names for 32 bit ABI + */ + +# define Mode_USR 0x10 /* M[4:0] = 01010 */ +# define Mode_FIQ 0x11 /* M[4:0] = 10001 */ +# define Mode_IRQ 0x12 /* M[4:0] = 10010 */ +# define Mode_SVC 0x13 /* M[4:0] = 10011 */ +# define Mode_MON 0x16 /* M[4:0] = 10110 */ +# define Mode_ABT 0x17 /* M[4:0] = 10111 */ +# define Mode_UNDEF 0x1B /* M[4:0] = 11011 */ +# define Mode_SYS 0x1F /* M[4:0] = 11111 */ +# define Mode_MSK 0x1F /* M[4:0] = 11111 */ +# define I_Bit 0x80 /* 7 6 5 4 3 2 1 0 */ +# define F_Bit 0x40 /* I F T M4 M3 M2 M1 M0 */ + +/* + ************************************************************************ + * Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |W|W|R|W|NumSets |Associativity |L | + * |T|B|A|A| | |S | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CCSIDR_WT 31 +#define M_CCSIDR_WT (0x1 << S_CCSIDR_WT) /* Support write-through */ +#define S_CCSIDR_WB 30 +#define M_CCSIDR_WB (0x1 << S_CCSIDR_WB) /* Support write-back */ +#define S_CCSIDR_RA 29 +#define M_CCSIDR_RA (0x1 << S_CCSIDR_RA) /* Support read-allocation */ +#define S_CCSIDR_WA 28 +#define M_CCSIDR_WA (0x1 << S_CCSIDR_WA) /* Support write-allocation */ +#define S_CCSIDR_SETS 13 +#define M_CCSIDR_SETS (0x7fff << S_CCSIDR_SETS) /* Number of sets */ +#define S_CCSIDR_A 3 +#define M_CCSIDR_A (0x3ff << S_CCSIDR_A) /* Number of associatiovity */ +#define S_CCSIDR_LS 0 +#define M_CCSIDR_LS (0x7 << S_CCSIDR_LS) /* Cache line size */ + +/* + ************************************************************************ + * Cache Level ID Register, CLIDR (cp15, 1, c0, c0, 1) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |0|0|LoUU |LoC |LoUIS|CT7 |CT6 |CT5 |CT4 |CT3 |CT2 |CT1 | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CLIDR_LoUU 27 +#define M_CLIDR_LoUU (0x7 << S_CLIDR_LoUU) +#define S_CLIDR_LoC 24 +#define M_CLIDR_LoC (0x7 << S_CLIDR_LoC) /* Cache cohernecy level */ +#define S_CLIDR_LoUIS 21 +#define M_CLIDR_LoUIS (0x7 << S_CLIDR_LoUIS) +#define S_CLIDR_Ctype7 18 +#define M_CLIDR_Ctype7 (0x7 << S_CLIDR_Ctype7) /* Cache type of level 7 cache */ +#define S_CLIDR_Ctype6 15 +#define M_CLIDR_Ctype6 (0x7 << S_CLIDR_Ctype6) /* Cache type of level 6 cache */ +#define S_CLIDR_Ctype5 12 +#define M_CLIDR_Ctype5 (0x7 << S_CLIDR_Ctype5) /* Cache type of level 5 cache */ +#define S_CLIDR_Ctype4 9 +#define M_CLIDR_Ctype4 (0x7 << S_CLIDR_Ctype4) /* Cache type of level 4 cache */ +#define S_CLIDR_Ctype3 6 +#define M_CLIDR_Ctype3 (0x7 << S_CLIDR_Ctype3) /* Cache type of level 3 cache */ +#define S_CLIDR_Ctype2 3 +#define M_CLIDR_Ctype2 (0x7 << S_CLIDR_Ctype2) /* Cache type of level 2 cache */ +#define S_CLIDR_Ctype1 0 +#define M_CLIDR_Ctype1 (0x7 << S_CLIDR_Ctype1) /* Cache type of level 1 cache */ + +#define K_CLIDR_Ctype_NO 0 /* No cache */ +#define K_CLIDR_Ctype_IC 1 /* Instruction cache only */ +#define K_CLIDR_Ctype_DC 2 /* Data cache only */ +#define K_CLIDR_Ctype_ID 3 /* Seperate instruction and data caches, Harvard cache */ +#define K_CLIDR_Ctype_U 4 /* Unified cache, von Neumann cacge */ + +/* + ************************************************************************ + * Cache Size Selection Register, CCSELR (cp15, 2, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |Reserved |Level|I| + * | | |n| + * | | |D| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CCSELR_Level 1 +#define M_CCSELR_Level (0x7 << S_CCSELR_Level) /* Cache level */ +#define S_CCSELR_InD 0 +#define M_CCSELR_InD (0x1 << S_CCSELR_InD) /* I$ or D$ */ + +/* + ************************************************************************ + * System Control Register, SCTLR (cp15, 0, c1, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |R|T|A|T|N|0|E|V|1|U|F|U|W|1|H|1|0|R|V|I|Z|S|0|0|B|1|B|1|1|C|A|M| + * | |E|F|R|M| |E|E| | |I|W|X| |A| | | | | | |W| | | | |E| | | | | | + * | | |E|E|F| | | | | | |X|N| | | | | | | | | | | | | |N| | | | | | + * | | | | |I| | | | | | |N| | | | | | | | | | | | | | | | | | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_SCTLR_TE 30 +#define M_SCTLR_TE (0x1 << S_SCTLR_TE) /* Thumb exception enable */ +#define S_SCTLR_AFE 29 +#define M_SCTLR_AFE (0x1 << S_SCTLR_AFE) /* Access flag enable */ +#define S_SCTLR_TRE 28 +#define M_SCTLR_TRE (0x1 << S_SCTLR_TRE) /* TXE remap enable */ +#define S_SCTLR_NMFI 27 +#define M_SCTLR_NMFI (0x1 << S_SCTLR_NMFI) /* None-maskable FIQ enbale (RO) */ +#define S_SCTLR_EE 25 +#define M_SCTLR_EE (0x1 << S_SCTLR_EE) /* Exception Endianness: big-endian */ +#define S_SCTLR_VE 24 +#define M_SCTLR_VE (0x1 << S_SCTLR_VE) /* Interrupt Vector Enable */ +#define S_SCTLR_FI 21 +#define M_SCTLR_FI (0x1 << S_SCTLR_FI) /* Fast interrupt configuraiont enable */ +#define S_SCTLR_UWXN 20 +#define M_SCTLR_UWXN (0x1 << S_SCTLR_UWXN) /* */ +#define S_SCTLR_WXN 19 +#define M_SCTLR_WXN (0x1 << S_SCTLR_WXN) +#define S_SCTLR_HA 17 +#define M_SCTLR_HA (0x1 << S_SCTLR_HA) /* Hardware access flag enable */ +#define S_SCTLR_RR 14 +#define M_SCTLR_RR (0x1 << S_SCTLR_RR) /* Round-robin select */ +#define S_SCTLR_V 13 +#define M_SCTLR_V (0x1 << S_SCTLR_V) /* Vector bits */ +#define S_SCTLR_I 12 +#define M_SCTLR_I (0x1 << S_SCTLR_I) /* Instruction cache enable */ +#define S_SCTLR_Z 11 +#define M_SCTLR_Z (0x1 << S_SCTLR_Z) /* Branch prediction enable */ +#define S_SCTLR_SW 10 +#define M_SCTLR_SW (0x1 << S_SCTLR_SW) /* SW and SWP enable */ +#define S_SCTLR_CP15BEN 5 +#define M_SCTLR_CP15BEN (0x1 << S_SCTLR_CP15BEN) /* CP15 barrier support */ +#define S_SCTLR_C 2 +#define M_SCTLR_C (0x1 << S_SCTLR_C) /* Data and Unidied cache enable */ +#define S_SCTLR_A 1 +#define M_SCTLR_A (0x1 << S_SCTLR_A) /* Alignment fault checking enable */ +#define S_SCTLR_M 0 +#define M_SCTLR_M (0x1 << S_SCTLR_M) /* PL1&0 stage MMU enable */ + +/************************************************************************ + * Auxiliary Control Register, ACTLR (cp15, 0, c1, c0, 1) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |UNP/SBZP |P|A|E|S|RAZ|W|L|L|F| + * | |a|l|X|M| | |1|2|W| + * | |r|l|C|P| |f| | | | + * | | |o|L| | |l|p|p| | + * | |o|c| | | | |r|r| | + * | |n| | | | |z|e|e| | + * | | |o| | | |e|f|f| | + * | | |n| | | |r| | | | + * | | |e| | | |o|e|e| | + * | | | | | | |s|n|n| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_ACTLR_PAR_ON 9 +#define M_ACTLR_PAR_ON (0x1 << S_ACTLR_PAR_ON) /* Parity on */ +#define S_ACTLR_ALLOC_ONE 8 +#define M_ACTLR_ALLOC_ONE (0x1 << S_ACTLR_ALLOC_ONE) /* Alloc in one way */ +#define S_ACTLR_EXCL 7 +#define M_ACTLR_EXCL (0x1 << S_ACTLR_EXCL) /* Exclusive cache */ +#define S_ACTLR_SMP 6 +#define M_ACTLR_SMP (0x1 << S_ACTLR_SMP) /* SMP */ +#define S_ACTLR_W_FL_ZEROS 3 +#define M_ACTLR_W_FL_ZEROS (0x1 << S_ACTLR_W_FL_ZEROS) /* Write full line of zeros mode */ +#define S_ACTLR_L1_PERF_EN 2 +#define M_ACTLR_L1_PERF_EN (0x1 << S_ACTLR_L1_PERF_EN) /* Dside prefetch enable */ +#define S_ACTLR_L2_PERF_EN 1 +#define M_ACTLR_L2_PERF_EN (0x1 << S_ACTLR_L2_PERF_EN) /* L2 prefetch enable */ +#define S_ACTLR_FW 0 +#define M_ACTLR_FW (0x1 << S_ACTLR_FW) /* Cache and TLB maintenance boardcast */ + +#if 0 +#define zero $0 /* wired zero */ +#define AT $1 /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ +#define ra $31 /* return address */ + +#define C0_Count $9 +#define C0_Compare $11 +#define C0_Status $12 +#define C0_Cause $13 +#define C0_EPC $14 +#define C0_Config $16 +#define C0_WatchLo $18 +#define C0_WatchHi $19 + +#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ +#define M_ConfigK0 (0x7 << S_ConfigK0) + +#define S_StatusERL 2 /* Denotes error level (R/W) */ +#define M_StatusERL (0x1 << S_StatusERL) + + +#define S_StatusKSU 3 /* Two-bit current mode (R/W) */ +#define M_StatusKSU (0x3 << S_StatusKSU) + +#define S_StatusIE 0 /* Enables interrupts (R/W) */ +#define M_StatusIE (0x1 << S_StatusIE) + +#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ +#define M_StatusBEV (0x1 << S_StatusBEV) + + +/* + * Cache attribute values in the C field of EntryLo and the + * K0 field of Config + */ +#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ +#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ +#define K_CacheAttrU 2 /* Uncached */ +#define K_CacheAttrC 3 /* Cacheable */ +#define K_CacheAttrCN 3 /* Cacheable, non-coherent */ +#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ +#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ +#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ +#define K_CacheAttrUA 7 /* Uncached accelerated */ + +#define S_EntryLo0PFN S_EntryLoPFN +#define M_EntryLo0PFN M_EntryLoPFN + + +#define R_C0_SRSCtl 12 +#define R_C0_SelSRSCtl 2 + +#define S_SRSCtlHSS 26 /* Highest shadow set (R) */ +#define W_SRSCtlHSS 4 +#define M_SRSCtlHSS (0xf << S_SRSCtlHSS) +#define S_SRSCtlEICSS 18 /* Exception shadow set (R/W) */ +#define W_SRSCtlEICSS 4 +#define M_SRSCtlEICSS (0xf << S_SRSCtlEICSS) +#define S_SRSCtlESS 12 /* Exception shadow set (R/W) */ +#define W_SRSCtlESS 4 +#define M_SRSCtlESS (0xf << S_SRSCtlESS) +#define S_SRSCtlPSS 6 /* Previous shadow set (R/W) */ +#define W_SRSCtlPSS 4 +#define M_SRSCtlPSS (0xf << S_SRSCtlPSS) +#define S_SRSCtlCSS 0 +#define W_SRSCtlCSS 4 +#define M_SRSCtlCSS (0xf << S_SRSCtlCSS) /* Current Shadow set (R/W) */ + +#define M_SRSCtl0Fields 0xc3c30c30 +#define M_SRSCtlRFields 0x3c3c000f + + +#define KUSEG_MSK 0x80000000 +#define KSEG_MSK 0xE0000000 +#define KUSEGBASE 0x00000000 +#define KSEG0BASE 0x80000000 +#define KSEG1BASE 0xA0000000 +#define KSSEGBASE 0xC0000000 +#define KSEG3BASE 0xE0000000 +#endif diff --git a/board/novatek/na51068/loader/Include/Driver/top_ctrl.h b/board/novatek/na51068/loader/Include/Driver/top_ctrl.h new file mode 100755 index 000000000000..df2a8c90778b --- /dev/null +++ b/board/novatek/na51068/loader/Include/Driver/top_ctrl.h @@ -0,0 +1,160 @@ +#ifndef __TOP_CTRL_H +#define __TOP_CTRL_H + +#include "board.h" +#define TOP_CTRL_REG_BASE_ADDR REG_TOP_BASE + +#define TOP_CTRL_BOOTSRC (TOP_CTRL_REG_BASE_ADDR + 0x00) + +#define TOP_CTRL_PIN_MUX_CTRL_REG0 (TOP_CTRL_REG_BASE_ADDR + 0x20) +#define TOP_CTRL_PIN_MUX_CTRL_REG1 (TOP_CTRL_REG_BASE_ADDR + 0x24) + +#define TOP_CTRL_PIN_MUX_CTRL_REG2 (TOP_CTRL_REG_BASE_ADDR + 0x08) +#define TOP_CTRL_PIN_MUX_CTRL_REG4 (TOP_CTRL_REG_BASE_ADDR + 0x10) +#define TOP_CTRL_PIN_MUX_CTRL_REG5 (TOP_CTRL_REG_BASE_ADDR + 0x14) +#define TOP_CTRL_PIN_MUX_CTRL_REG8 (TOP_CTRL_REG_BASE_ADDR + 0x20) +#define TOP_CTRL_PIN_MUX_CTRL_REG9 (TOP_CTRL_REG_BASE_ADDR + 0x24) +#define TOP_CTRL_PIN_MUX_CTRL_REG6 (TOP_CTRL_REG_BASE_ADDR + 0x44) + +#define TOP_CTRL_ETH0_MUX_REG0 (TOP_CTRL_REG_BASE_ADDR + 0x70) +#define TOP_CTRL_ETH0_MUX_REG1 (TOP_CTRL_REG_BASE_ADDR + 0x74) +#define TOP_CTRL_ETH_MUX_SEL (TOP_CTRL_REG_BASE_ADDR + 0xC8) + + + +#define TOP_CTRL_CGPIO_MUX_REG0 (TOP_CTRL_REG_BASE_ADDR + 0xA0) +#define TOP_CTRL_CGPIO_MUX_REG1 (TOP_CTRL_REG_BASE_ADDR + 0xA4) +#define TOP_CTRL_PGPIO_MUX_REG0 (TOP_CTRL_REG_BASE_ADDR + 0xA8) +#define TOP_CTRL_PGPIO_MUX_REG1 (TOP_CTRL_REG_BASE_ADDR + 0xAC) +#define TOP_CTRL_SGPIO_MUX_REG0 (TOP_CTRL_REG_BASE_ADDR + 0xB0) +#define TOP_CTRL_LGPIO_MUX_REG0 (TOP_CTRL_REG_BASE_ADDR + 0xB8) +#define TOP_CTRL_DGPIO_MUX_REG0 (TOP_CTRL_REG_BASE_ADDR + 0xD0) +#define TOP_CTRL_VERSION_REG (TOP_CTRL_REG_BASE_ADDR + 0xF0) + + +#define TOP_CTRL_SRAM_RESET_REG0 (TOP_CTRL_REG_BASE_ADDR + 0x1000) + +#define TOP_CTRL_BS_SPI_NAND_2K_PAGE (1<<3) +#define TOP_CTRL_BS_SPI_NAND_4K_PAGE (0) + +#define TOP_BOOTSRC_MSK 0x07 + +#define TOP_GETROMVER() INREG32(0xE0007FFC) +// +// ROM code version number +// +#define TOP_ROMVER_A 0x00000103 +#define TOP_ROMVER_B 0x00000106 + +//#define PINMUX_NAND_ACT (1<<0) +//#define PINMUX_SPI_ACT (1<<1) +//#define PINMUX_NAND_EXIST (1<<12) +//#define PINMUX_SPI_EXIST (1<<13) +#define PINMUX_SDIO_EXIST (1<<14) +#define PINMUX_EXTROM_EXIST (1<<16) +#define PINMUX_SDIO3_EXIST (1<<17) +#define PINMUX_SDIO3_MUX_1 (0) +#define PINMUX_ICE_EXIST (1<<20) +#define PINMUX_SDIO3_MUX_2 (1<<24) +#define PINMUX_SDIO3_4BITS (0) +#define PINMUX_SDIO3_8BITS (1<<31) +#define PINMUX_ROM_SRC (1<<28) + +//need to check (0xF0010018) +#define PINMUX_ETH_RMII (1<<12)//((1<<16) | (1<<8)) SP clk need ?? +#define PINMUX_ETH_REFCLK_INPUT (1<<15) //RMII refclk input mode + +#define PINMUX_ETH_EXTPHY_CLK_EN (1<<28) + + +//Shut down SRAM SDIO1 mask +#define TOP_SRAM_SD_SDIO1 0x20000000 +//Shut down SRAM RSA mask +#define TOP_SRAM_SD_RSA 0x02000000 + +// For storage pinmux +#define TOP_REG0_SDIO_PINMUX (PINMUX_SDIO_EXIST) +#define TOP_REG0_SDIO3_PINMUX (PINMUX_SDIO3_EXIST | PINMUX_SDIO3_MUX_1) +#define TOP_REG0_EMMC_PINMUX (PINMUX_SDIO3_EXIST ) +//#define TOP_REG1_NAND_PINMUX (PINMUX_NAND_EXIST) +#define TOP_REG0_SPI_PINMUX ((2<<28)|(2<<24)|(2<<20)) +#define TOP_REG0_SPI_MASK ((7<<28)|(7<<24)|(7<<20)) +#define TOP_REG0_BMC_PINMUX (PINMUX_EXTROM_EXIST) +#define TOP_REG0_ICE_PINMUX (PINMUX_ICE_EXIST) +#define TOP_REG1_SPI_PINMUX ((2<<12)|(2<<8)|(2<<4)|(2<<0)) +#define TOP_REG1_SPI_MASK ((7<<12)|(7<<8)|(7<<4)|(7<<0)) +#if 0 +#if ((USE_FPGA_EMULATION == 1) || (USE_BMC_EMULATION == 1)) +#define TOP_CGPIO0_SDIO_PINMUX (0xFFFFFFFF & ~((0x3F<<11))) +#define TOP_CGPIO0_SDIO3_PINMUX (0xFFFFFFFF & ~((0xF<<28)|(0xF<<18))) +#define TOP_CGPIO1_SDIO3_PINMUX (0) +#define TOP_CGPIO0_EMMC_PINMUX (0xFFFFFFFF & ~((0xFF<<0)|(1<<8)|(1<<9)|(1<<10))) +#define TOP_CGPIO0_EMMC_4BIT_PINMUX (0xFFFFFFFF & ~((0xF<<0)|(1<<8)|(1<<9)|(1<<10)|(0xF<<18))) +#define TOP_CGPIO0_NAND_PINMUX (0xFFFFFFFF & ~((0xFFFF<<0)|(0xF<<18))) +//#define TOP_CGPIO0_SPI_PINMUX (0xFFFFFFFF & ~((0xF<<0)|(1<<8)|(1<<10))) +#define TOP_SGPIO0_BMC_PINMUX (0xFFFFFFFF & ~((1<<4)|(1<<6)|(1<<7)|(1<<8))) +#else +#define TOP_CGPIO0_SDIO_PINMUX (0xFFFFFFFF & ~(0x3F << 11)) +#define TOP_CGPIO0_SDIO3_PINMUX (0xFFFFFFFF & ~(0xF<<28)) +#define TOP_CGPIO1_SDIO3_PINMUX (0) +#define TOP_CGPIO0_EMMC_PINMUX (0xFFFFFFFF & ~((0xFF<<0)|(1<<8)|(1<<9)|(1<<10))) +#define TOP_CGPIO0_EMMC_4BIT_PINMUX (0xFFFFFFFF & ~((0xF<<0)|(1<<8)|(1<<9)|(1<<10))) +#define TOP_CGPIO0_NAND_PINMUX (0xFFFFFFFF & ~((0xFFFF<<0))) +//#define TOP_CGPIO0_SPI_PINMUX (0xFFFFFFFF & ~((0xF<<0)|(1<<8)|(1<<10))) +#endif +#endif +//Below need to check again +#define TOP_LGPIO0_ETH_MII_PINMUX (0xFFFFFFFF & ~(0xFF7FF)) +#define TOP_LGPIO0_ETH_RMII_PINMUX (0xFFFFFFFF & ~(0x7FF)) +#define TOP_LGPIO0_ETH_EMBED_PINMUX (0xFFFFFFFF & ~((0x1<<19)|(0x3<<9))) +#define TOP_PGPIO0_ETH_PINMUX (0xFFFFFFFF & ~(1<<22)) + +// For eMMC configuration +#define TOP_REG0_EMMC_4BITS (0) +#define TOP_REG0_EMMC_8BITS (1 << 7) +#define TOP_REG0_EMMC_BUSWIDTH_MSK (1 << 7) +#define TOP_REG0_EMMC_BOOT_SDR (0) +#define TOP_REG0_EMMC_BOOT_DDR (1 << 8) +#define TOP_REG0_EMMC_BOOTMODE_MSK (1 << 8) +#define TOP_REG0_EMMC_DDR_ODD_1ST (0) +#define TOP_REG0_EMMC_DDR_EVEN_1ST (1 << 9) +#define TOP_REG0_EMMC_DDREDGE_MSK (1 << 9) + +//Below need to check again +// For ethernet configuration +#define TOP_REG0_ETH_PINMUX_MSK (0x3 << 3) +#define TOP_REG0_ETH_PINMUX_RMII_OUTPUT (0 << 3) +#define TOP_REG0_ETH_PINMUX_RMII_INPUT (1 << 3) +#define TOP_REG0_ETH_PINMUX_RGMII (2 << 3) +#define TOP_REG0_ETH_PINMUX_EMB (3 << 3) + +// ETH LED +#define TOP_REG6_ETH_LED_MSK (0xFF0 ) +#define TOP_REG6_ETH_LED_2 (2 << 13) +#define TOP_REG6_ETH_LED_1 (0x55 << 4) +#define TOP_REG6_ETH_LED_DISABLE (0 << 13) +// WDT +#define TOP_REG0_WDT_PINMUX_MSK (0x01 <<12) + + +#define TOP_DSP_IOP_CH_EN (1 << 17) + +// For UART pinmux +#define UART0_SWITCH (0x01 << 0) + +// For USB pinmux +#define TOP_USB_VBUSI (0x03) // Bit2: device mode, Bit1: VBUSI + +//#define selectUART() SETREG32(TOP_CTRL_PIN_MUX_CTRL_REG9, UART0_SWITCH) +#if 0 +#if ((USE_FPGA_EMULATION == 1) || (USE_BMC_EMULATION == 1)) +#define selectCardType(type) OUTREG32(TOP_CTRL_PIN_MUX_CTRL_REG1, (INREG32(TOP_CTRL_PIN_MUX_CTRL_REG1)&(TOP_REG0_BMC_PINMUX|TOP_REG0_ICE_PINMUX))|(type)) +#else +#define selectCardType(type) OUTREG32(TOP_CTRL_PIN_MUX_CTRL_REG1, (INREG32(TOP_CTRL_PIN_MUX_CTRL_REG1)&(TOP_REG0_BMC_PINMUX|TOP_REG0_ICE_PINMUX))|(type)) +#endif +#endif + +#define selectUART0() CLRREG32(TOP_CTRL_PIN_MUX_CTRL_REG1, ((0x3 << 20) | (0x3 << 24)));\ + SETREG32(TOP_CTRL_PIN_MUX_CTRL_REG1, ((0x1 << 20) | (0x1 << 24))); + +#endif diff --git a/board/novatek/na51068/loader/Include/StorageDef.h b/board/novatek/na51068/loader/Include/StorageDef.h new file mode 100755 index 000000000000..7968627103e4 --- /dev/null +++ b/board/novatek/na51068/loader/Include/StorageDef.h @@ -0,0 +1,524 @@ +/** + Storage module driver. + + This file is the driver of storage module. + + @file StorageDef.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _STORAGE_DEF_ +#define _STORAGE_DEF_ + +#include "board.h" + +#define _STORAGE_OBJ_ 1 +/** + @addtogroup mIDrvStorage +*/ +//@{ + +/** + @name External storage type + +*/ +//@{ +#define EXT_STORAGE_TYPE_NONE (0) +#define EXT_STORAGE_TYPE_SDIO1 (1) +#define EXT_STORAGE_TYPE_SDIO2 (2) +#define EXT_STORAGE_TYPE_USB (3) +#define EXT_STORAGE_TYPE_ETH (4) +//*} + +/** + @name SPI Quad read type + + @note for SPI_IDENTIFY +*/ +//@{ +#define SPI_QUAD_NONE 0 ///< Not support +#define SPI_QUAD_TYPE1 1 ///< Support quad read, QE(Quad Enable) bit is in Status Reigster[bit 6] and 0x6B command requires 8 dummy clocks. +#define SPI_QUAD_TYPE2 2 ///< Support quad read, QE(Quad Enable) bit is in Status Register[bit 9] and 0x6B command requires 8 dummy clocks. +#define SPI_QUAD_TYPE3 3 ///< Support quad read, QE(Quad Enable) NOT exist and 0x6B command requires 8 dummy clocks +#define SPI_QUAD_TYPE4 4 ///< Support quad read, QE(Quad Enable) bit is in Status Register[bit 9] and 0x6B command requires 8 dummy clocks. + ///< But QE CAN'T be modified by 0x31 command. Instead, QE is enabled by 0x01 command 2nd data byte +//@} + +/** + SPI flash identify descriptor + + @note For STRG_IDENTIFY_CB +*/ +typedef struct +{ + BOOL bDualRead; ///< Dual read (0x3B) command capability + ///< - @b TRUE: support dual read comand. (Command value should be 0x3B.) + ///< - @b FALSE: NOT support dual read command + UINT32 uiQuadReadType; ///< Quad read type capability. (ONLY support quad command 0x6B) + ///< - @b SPI_QUAD_NONE: NOT support quad read command + ///< - @b SPI_QUAD_TYPE1: Support quad read command, QE in Status Register bit 6 + ///< - @b SPI_QUAD_TYPE2: Support quad read command, QE in Status Register bit 9 + ///< - @b SPI_QUAD_TYPE3: Support quad read command, QE NOT exist + ///< - @b SPI_QUAD_TYPE4: Support quad read command, QE in Status Register bit 9 (but need 0x31 command) + UINT32 uiFlashSize; ///< Flash total byte size. (unit: byte) +} SPI_IDENTIFY, *PSPI_IDENTIFY; + +/** + @name Storage Access CallBack + + Storage Access CallBack Prototype + + @return void +*/ +//@{ +typedef void (*STRG_ACCESS_CB)(void); ///< Storage access call back prototype +//@} + +/** + @name Storage Identify CallBack + + Storage Identify CallBack Prototype + + @param[in] UINT32 uiMfgID (JEDEC) manufacturer ID read from spi flash + @param[in] UINT32 uiTypeID (JEDEC) type ID read from spi flash + @param[in] UINT32 uiCapacityID (JEDEC) capacity ID read from spi flash + @param[out] PSPI_IDENTIFY flash identification returned to spi flash driver + + @return + - @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information + - @b FALSE: input ID is NOT supported/identified by call back +*/ +//@{ +typedef BOOL (*STRG_IDENTIFY_CB)(UINT32, UINT32, UINT32, PSPI_IDENTIFY); ///< Storage identify call back prototype +//@} + +/** + @name Storage return value + + @note for flash_open(), flash_readSectors(), and flash_writeSectors() +*/ +//@{ +#define E_OK 0 ///< Success +#define E_NAND_IDENTIFY_ERR -1 ///< Read NAND ID (information) error +#define E_NAND_INSUFFICINET_BLK -2 ///< Bad block is too much to write data +#define E_NAND_BLK_NOT_FOUND -3 ///< Logic block number not found in physical block +#define E_NAND_WRITE_PAGEDATA_ERR -4 ///< Logic block number not found in physical block +#define E_NAND_ERASEE_BLK_ERR -5 ///< NAND erase block error +#define E_NAND_READ_PAGE_ERR -6 ///< NAND read page data error +#define E_NAND_READ_BLK_ERR -7 ///< NAND read block data error +#define E_NAND_ID_NOT_SUPPORT -8 ///< Not support NAND ID +#define E_IDENTIFY_ERR -9 ///< SPI IDENTIFY error +#define E_SYS -10 ///< System Error +#define E_NAND_ALIGN_ERR -11 ///< Not block alignment +#define E_NAND_BOUNDARY_ERR -12 ///< boundary < write buffer +#define E_OK_TABLE_FOUND 1 ///< Success & NAND table find +#define E_OK_TABLE_NOT_FOUND 2 ///< Success & NAND table not find +//@} + +/** + @name Internal Storage Update Region + + @note for flash_readSectors(), and flash_writeSectors() +*/ +//@{ +#define NAND_RW_LOADER 0 ///< Update Region is Loader (Update size is assumed 16 KB) +#define NAND_RW_RESERVED 1 ///< Update Region is reserved area (Update size is assumed 16 KB) +#define NAND_RW_FIRMWARE 2 ///< Update Region is FW (Update size is variable) +#define NAND_RW_FIRMWARE_2 3 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_3 4 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_4 5 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_5 6 ///< Update Region is FW from 2-5(Update size is variable) +//@} + +/** + @name Internal Storage Configuration ID + + @note for flash_setConfig() +*/ +//@{ +#define FLASH_CFG_ID_NONE 0 +#define FLASH_CFG_ID_SPI_SUPPORT_4BITS 1 ///< Enable your project to support 4 bit SPI flash. ONLY enable when you ENSURE SPI_D0~SPI_D3 are connected to SPI flash in your PCB!!! +#define FLASH_CFG_ID_EMMC_SUPPORT_8BITS 2 ///< Enable your project to support 8 bit EMMC. ONLY enable when you ENSURE EMMC_D0~SPI_D7 are connected to EMMC flash in your PCB!!! +#define FLASH_CFG_ID_CS_SELECT 3 ///< Select this flash (nand/nor) is connected with CS0 or CS1 +#define FLASH_CFG_ID_SPI_IDENTIFY_CB 4 ///< Install flash identify call back +//@} + +/** + @name Internal Storage Configuration ID + + @note for flash_getConfig() +*/ +//@{ +#define FLASH_CFG_ID_SPI_GET_STATUS_1 0 ///< Get SPI-NOR flash get status 1( S7~S0) +#define FLASH_CFG_ID_SPI_GET_STATUS_2 1 ///< Get SPI-NOR flash get status 2(S15~S8) +#define FLASH_CFG_ID_SPI_GET_STATUS_3 2 ///< Get SPI-NOR flash get status 3(S23~S16) +//@} + +#if (_STORAGE_OBJ_== 1) + + +#define BOOT_SOURCE_SPI 0x00 +#define BOOT_SOURCE_SPI_NAND_2K 0x09 +#define BOOT_SOURCE_SPI_NAND_4K 0x01 + +/** + @name New storage object interface + + For new version storage device driver +*/ +//@{ +typedef struct { + INT32(*flash_open)(void); ///< Flash Open + void(*flash_close)(void); ///< Flash Close + INT32(*flash_readSectors)(UINT32, UINT32, UINT8 *,UINT32); ///< Flash Read Sector + INT32(*flash_writeSectors)(UINT32, UINT32, UINT8 *, UINT32); ///< Flash Write Sector + INT32(*flash_writePartition)(UINT32, UINT32, UINT32, UINT8 *, UINT32); ///< Flash Write Sector, and remain space need erase + UINT32(*flash_getBlockSize)(void); ///< Flash Get Block Size + void(*flash_setReservedBadBlockNumber)(UINT32); ///< Flash Set Reserved Bad Block Number + void(*flash_setReservedAreaMaxBlockNumber)(UINT32); ///< Flash Set Reserved Area Block Number + UINT64(*flash_getTotalSize)(void); + void(*flash_installAccessCB)(STRG_ACCESS_CB); + void(*flash_installIdentifyCB)(STRG_IDENTIFY_CB); + void(*flash_setFrequency)(UINT32); + INT32(*flash_setConfig)(UINT32, UINT32); + INT32(*flash_getConfig)(UINT32, UINT32); +} STORAGE_OBJ, *PSTORAGE_OBJ; + +extern PSTORAGE_OBJ nand_get_storage_object(void); +extern PSTORAGE_OBJ nor_get_storage_object(void); + +//@} +#else +// Internal storage public API ( NAND / SPI flash) +/** + Flash Open + + This function will initialize internal flash driver + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return + - @b E_OK: open success + - @b E_IDENTIFY_ERR: identify fail (SPI path) + - @b E_NAND_IDENTIFY_ERR: identify fail (NAND path) + - @b E_NAND_ID_NOT_SUPPORT: not supported NAND flash +*/ +extern INT32 flash_open(void); +/** + Flash Close + + This function will close internal flash driver + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return void +*/ +extern void flash_close(void); + +/** + Flash Read Sector + + This function will read data from internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] startblk Start block of this read operation (unit: flash block) + @param[in] length Length of read operation (unit: byte) + @param[out] buffer Pointer to DRAM buffer to receive read data (word alignment) + @param[in] updateType Operation Access Region + - @b NAND_RW_LOADER: loader region + - @b NAND_RW_RESERVED: reserved area + - @b NAND_RW_FIRMWARE: f/w region + + @return + - @b E_OK: read success + - @b E_NAND_BLK_NOT_FOUND: can not find available physical block + - @b E_NAND_READ_BLK_ERR: NAND access block error + - @b E_NAND_READ_PAGE_ERR: NAND access page error +*/ +extern INT32 flash_readSectors(UINT32 startblk, UINT32 length, UINT8 * buffer, UINT32 updateType); + +/** + Flash Write Sector + + This function will write data to internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] startblk Start block of this write operation (unit: flash block) + @param[in] length Length of write operation (unit: byte) + @param[in] buffer Pointer to DRAM buffer of written data (word alignment) + @param[in] updateType Operation Access Region + - @b NAND_RW_LOADER: loader region + - @b NAND_RW_RESERVED: reserved area + - @b NAND_RW_FIRMWARE: f/w region + + @return + - @b E_OK: read success + - @b E_NAND_BLK_NOT_FOUND: can not find available physical block + - @b E_NAND_ERASEE_BLK_ERR: erase block error + - @b E_NAND_WRITE_PAGEDATA_ERR: page program error + - @b E_NAND_INSUFFICINET_BLK: insufficient good block +*/ +extern INT32 flash_writeSectors(UINT32 startblk, UINT32 length, UINT8 * buffer, UINT32 updateType); + +/** + Flash Write partition + + This function will write data to internal flash and continue erase flash to partition boundary + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] startblk Start block of this write operation (unit: flash block) + @param[in] length Length of write operation (unit: byte) + @param[in] boundary_length Length of write partition boundary (unit: byte) (limit:block boundary) + @param[in] buffer Pointer to DRAM buffer of written data (word alignment) + @param[in] updateType Operation Access Region + - @b NAND_RW_LOADER: loader region + - @b NAND_RW_RESERVED: reserved area + - @b NAND_RW_FIRMWARE: f/w region + + @return + - @b E_OK: read success + - @b E_NAND_BLK_NOT_FOUND: can not find available physical block + - @b E_NAND_ERASEE_BLK_ERR: erase block error + - @b E_NAND_WRITE_PAGEDATA_ERR: page program error + - @b E_NAND_INSUFFICINET_BLK: insufficient good block +*/ +extern INT32 flash_writePartition(UINT32 startblk, UINT32 length, UINT32 boundary_length, UINT8 * buffer, UINT32 updateType); + +/** + Flash Get Block Size + + This function will return block size of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return block size (unit: byte) +*/ +extern UINT32 flash_getBlockSize(void); + +/** + Flash Mount File system + + Mount file system (FAT) on flash + + @param[in] startblk start LBA of file system on flash. This should point to MBR. + @param[in] uiBuf DRAM address of file system buffer + @param[in] uiSize buffer size of file system buffer (unit: byte) (Recommend size is 0xA0000) + + @note only support by eMMC + + @return + - @b E_OK: mount success + - @b E_SYS: not support or mount fail +*/ +extern INT32 flash_mount_fs(UINT32 startblk, UINT32 uiBuf, UINT32 uiSize); + +/** + Flash Mount Partition + + Mount partition on flash + + @param[in] partition_id partition to be mounted. valid setting: 0 ~ 3 + + @note only support by eMMC + + @return + - @b E_OK: mount success + - @b E_SYS: not support or mount fail +*/ +extern INT32 flash_mount_partition(UINT32 partition_id); + +/** + Flash Open File + + Open File on flash + + @param[in] pfilename file name. It should be 8.3 format + + @note only support by eMMC + + @return + - @b TRUE: open file success + - @b FALSE: not support or open fail +*/ +extern BOOL flash_open_file(UINT8 *pfilename); + +/** + Flash Read File + + Read File on flash + + @param[in] buf_addr buffer address + @param[in] buf_size buffer size + + @note only support by eMMC + + @return + - @b 0: read fail + - @b else: actual read length +*/ +extern UINT32 flash_read_file(UINT8 *buf_addr, UINT32 buf_size); + +/** + Flash Set Reserved Bad Block Number + + This function will set block count reserved to do bad block replacement + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] badBlkNum reserved bad block count (unit: block) + + @return void +*/ +extern void flash_setReservedBadBlockNumber(UINT32 badBlkNum); + +//#NT#2010/04/20#Steven Wang -begin +//#NT#Autumn reserved area from 2 ~ 23 +/** + Flash Set Reserved Area Block Number + + This function will set reserved area max block count + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] RsvMaxBlkNum max reserved area block count (unit: block) + + @return void +*/ +extern void flash_setReservedAreaMaxBlockNumber(UINT32 RsvMaxBlkNum); +//#NT#2010/04/20#Steven Wang -end + +/** + Flash Set Reserved Bad Block Number for loader region + + This function will set block count reserved to do bad block replacement in loader region + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] badBlkNum reserved bad block count (unit: block) + + @return void +*/ +extern void flash_setLoaderReservedBadBlockNumber(UINT32 badBlkNum); + +/** + Flash Get Total Size + + This function will return total size of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return total size (unit: byte) +*/ +extern UINT64 flash_getTotalSize(void); + +/** + Install Flash Access CallBack + + This function will install access callback. + The installed callback will be invoked when one block/page is programmed + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @param[in] accessCB installed callback + + @return void +*/ +extern void flash_installAccessCB(STRG_ACCESS_CB accessCB); + +/** + Install Flash Identify CallBack + + This function will install identification callback. + The installed callback will be invoked when spi flash driver is opened. + + @note NAND driver will NOT invoke the installed call back + + @param[in] identifyCB installed callback + + @return void +*/ +extern void flash_installIdentifyCB(STRG_IDENTIFY_CB identifyCB); + +/** + Flash Set Bus Frequency + + This function will set operating frequency of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] uiFreq Operating frequency (unit: MHz) + + @return void +*/ +extern void flash_setFrequency(UINT32 uiFreq); + +/** + Flash Set Configuration + + This function will set specific configuration for internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] uiConfigId Configuration ID, can be: + - @b FLASH_CFG_ID_SPI_SUPPORT_4BITS: configure to support 4 bit SPI flash + @param[in] uiContext Configuration context for uiConfigId + When uiConfigId == FLASH_CFG_ID_SPI_SUPPORT_4BITS: + - @b TRUE: use 4 bit read when attached SPI flash support 4 bit read + - @b FALSE: won't use 4 bit read + + @return + - @b E_OK: success + - @b Else: fail +*/ +extern INT32 flash_setConfig(UINT32 uiConfigId, UINT32 uiContext); +#endif +// External storage public API ( SDIO/MS/xD ) +/** + Open card driver + + This function will initialize card driver and register it to file system + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return + - @b TRUE: open success + - @b FALSE: open fail +*/ +extern INT32 card_open(void); + +/** + Close card driver + + This function will close card driver + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return void +*/ +extern void card_close(void); + +/** + Get card type + + This function is used to get card storage type + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return void +*/ + +extern UINT32 card_get_type(void); + +//@} + +extern void USBOTGReset(void); +extern INT32 USB3Download(void); +extern void USBSetResult(UINT32 uiResult); +extern INT32 USBStateMachine(void); +#endif diff --git a/board/novatek/na51068/loader/Include/Type.h b/board/novatek/na51068/loader/Include/Type.h new file mode 100755 index 000000000000..74a00059eaaa --- /dev/null +++ b/board/novatek/na51068/loader/Include/Type.h @@ -0,0 +1,9 @@ +#ifndef __TYPE_H +#define __TYPE_H + +#include +//#include + +#define _ALIGNED(x) __attribute__((aligned(x))) + +#endif // __TYPE_H diff --git a/board/novatek/na51068/loader/Include/ahb_dma.h b/board/novatek/na51068/loader/Include/ahb_dma.h new file mode 100755 index 000000000000..5bb1a1203f58 --- /dev/null +++ b/board/novatek/na51068/loader/Include/ahb_dma.h @@ -0,0 +1,98 @@ +#ifndef __AHB_DMA_H + #define __AHB_DMA_H + #include "board.h" + + typedef struct { + INT32U ctrl; + INT32U cfg; + INT32U *src; + INT32U *dst; + INT32U llp; + INT32U size; + INT32U reserved[2]; + } CHANNELx; + + typedef struct { + INT32U ints; // 0x00 + INT32U int_tc; + INT32U int_tc_clr; + INT32U int_err; + INT32U int_err_clr; // 0x10 + INT32U tc; + INT32U err; + INT32U ch_en; + INT32U ch_busy; // 0x20 + INT32U csr; + INT32U sync; //0x28 + INT32U reserved[53]; + CHANNELx ch[8]; //0x100 + } ipDMA; + + typedef struct { + INT32U src_addr; + INT32U dst_addr; + INT32U llp; + INT32U llp_ctrl; + INT32U size; + }DMA_LLPD; + + + #define REQ_NANDTX 0 /* Use CH2 in DMAC */ + #define REQ_NANDRX 0 + #define REQ_SPI020TX 0 /* Use CH8 in DMAC for NOR TX */ + #define REQ_SPI020RX 0 /* Use CH8 in DMAC for NOR RX */ + + // bit[7:0]: dedicated channel no if 0-7 + // any channel no if other + // bit[15: 8]: request no. + /* The following defintions are not hardware relative. The following high byte is just table index to ahbdma_cmd[]. + */ + #define DMA_MEM2MEM ((0UL << 8) | 0) /* index 0 */ + + #define NAND_CHANNEL 0 /* Use CH0 in DMAC */ + /* define at ahb_dma.c ahbdma_cmd[4][2] */ + #define ARRAY_MEM2NAND 0 + #define ARRAY_NAND2MEM 1 + + #define DMA_MEM2NAND ((ARRAY_MEM2NAND << 8) | NAND_CHANNEL) /* index 1 */ + #define DMA_NAND2MEM ((ARRAY_NAND2MEM << 8) | NAND_CHANNEL) /* index 2 */ + + #define SPI020_CHANNEL 0 /* Use CH0 in DMAC */ + /* define at ahb_dma.c ahbdma_cmd[4][2] */ + #define ARRAY_MEM2SPI020 2 + #define ARRAY_SPI0202MEM 3 + + #define DMA_MEM2SPI020 ((ARRAY_MEM2SPI020 << 8) | SPI020_CHANNEL) /* index 1 */ + #define DMA_SPI0202MEM ((ARRAY_SPI0202MEM << 8) | SPI020_CHANNEL) /* index 2 */ + + + #define DMA_MAX 8 + + typedef void (* DMA_FINISH_CALLBACK)(volatile CHANNELx * pch, INT32U dma_st); + + #define AHB_DMA_EXT extern + + AHB_DMA_EXT INT32S Dma_go_trigger(INT32U * src, INT32U *dst, INT32U byte, DMA_LLPD *pllpd,INT32U req, int real); + AHB_DMA_EXT INT32S Dma_wait_timeout(INT32S hw_ch, INT32U timeout); + AHB_DMA_EXT void Dma_init(INT32U sync); + + + //DMA Source size + #define DMA_BURST_1 0x0L + #define DMA_BURST_4 0x1L + #define DMA_BURST_8 0x2L + #define DMA_BURST_16 0x3L + #define DMA_BURST_32 0x4L + #define DMA_BURST_64 0x5L + #define DMA_BURST_128 0x6L + #define DMA_BURST_256 0x7L + + /* req: DMA_MEM2MEM / DMA_MEM2NAND .... + * burst: DMA_BURST_1 ~ DMA_BURST_256 + * return: + * >= 0 for success + */ + AHB_DMA_EXT int Dma_Set_BurstSz(INT32U req, int burst); + +#endif /* __AHB_DMA_H */ + diff --git a/board/novatek/na51068/loader/Include/bdata.h b/board/novatek/na51068/loader/Include/bdata.h new file mode 100755 index 000000000000..b3eaa7031862 --- /dev/null +++ b/board/novatek/na51068/loader/Include/bdata.h @@ -0,0 +1,7 @@ +#ifndef __BDATA_H__ +#define __BDATA_H__ + +#define READ_SYSTEM_DATA 0xf9005100 +unsigned char __attribute__ ((section (".BDATA"))) bdata[] = {0x04, 0xB0, 0x2D, 0xE5, 0x00, 0xB0, 0x8D, 0xE2, 0x34, 0xD0, 0x4D, 0xE2, 0x30, 0x00, 0x0B, 0xE5, 0x34, 0x10, 0x0B, 0xE5, 0x30, 0x30, 0x1B, 0xE5, 0x10, 0x30, 0x43, 0xE2, 0x03, 0x00, 0x53, 0xE3, 0x03, 0xF1, 0x9F, 0x97, 0x1F, 0x00, 0x00, 0xEA, 0x38, 0x56, 0x00, 0xF9, 0x54, 0x56, 0x00, 0xF9, 0x70, 0x56, 0x00, 0xF9, 0x8C, 0x56, 0x00, 0xF9, 0x89, 0x32, 0x00, 0xE3, 0x08, 0x30, 0x0B, 0xE5, 0xF5, 0x32, 0x00, 0xE3, 0x0C, 0x30, 0x0B, 0xE5, 0xF6, 0x32, 0x00, 0xE3, 0x10, 0x30, 0x0B, 0xE5, 0x16, 0x00, 0x00, 0xEA, 0x8F, 0x32, 0x00, 0xE3, 0x08, 0x30, 0x0B, 0xE5, 0xF7, 0x32, 0x00, 0xE3, 0x0C, 0x30, 0x0B, 0xE5, 0xBE, 0x3F, 0xA0, 0xE3, 0x10, 0x30, 0x0B, 0xE5, 0x0F, 0x00, 0x00, 0xEA, 0x95, 0x32, 0x00, 0xE3, 0x08, 0x30, 0x0B, 0xE5, 0xF9, 0x32, 0x00, 0xE3, 0x0C, 0x30, 0x0B, 0xE5, 0xFA, 0x32, 0x00, 0xE3, 0x10, 0x30, 0x0B, 0xE5, 0x08, 0x00, 0x00, 0xEA, 0x9B, 0x32, 0x00, 0xE3, 0x08, 0x30, 0x0B, 0xE5, 0xFB, 0x32, 0x00, 0xE3, 0x0C, 0x30, 0x0B, 0xE5, 0xBF, 0x3F, 0xA0, 0xE3, 0x10, 0x30, 0x0B, 0xE5, 0x01, 0x00, 0x00, 0xEA, 0x00, 0x30, 0xE0, 0xE3, 0x68, 0x00, 0x00, 0xEA, 0x0C, 0x30, 0x1B, 0xE5, 0xA3, 0x31, 0xA0, 0xE1, 0x03, 0x30, 0xC3, 0xE3, 0xFE, 0x34, 0x83, 0xE2, 0x02, 0x38, 0x83, 0xE2, 0x18, 0x30, 0x0B, 0xE5, 0x18, 0x30, 0x1B, 0xE5, 0x00, 0x30, 0x93, 0xE5, 0x14, 0x30, 0x0B, 0xE5, 0x0C, 0x30, 0x1B, 0xE5, 0x1F, 0x30, 0x03, 0xE2, 0x14, 0x20, 0x1B, 0xE5, 0x32, 0x33, 0xA0, 0xE1, 0x01, 0x30, 0x03, 0xE2, 0x1C, 0x30, 0x0B, 0xE5, 0x10, 0x30, 0x1B, 0xE5, 0xA3, 0x31, 0xA0, 0xE1, 0x03, 0x30, 0xC3, 0xE3, 0xFE, 0x34, 0x83, 0xE2, 0x02, 0x38, 0x83, 0xE2, 0x18, 0x30, 0x0B, 0xE5, 0x18, 0x30, 0x1B, 0xE5, 0x00, 0x30, 0x93, 0xE5, 0x14, 0x30, 0x0B, 0xE5, 0x10, 0x30, 0x1B, 0xE5, 0x1F, 0x30, 0x03, 0xE2, 0x14, 0x20, 0x1B, 0xE5, 0x32, 0x33, 0xA0, 0xE1, 0x01, 0x30, 0x03, 0xE2, 0x20, 0x30, 0x0B, 0xE5, 0x20, 0x30, 0x1B, 0xE5, 0x01, 0x00, 0x53, 0xE3, 0x01, 0x00, 0x00, 0x1A, 0x04, 0x30, 0xE0, 0xE3, 0x45, 0x00, 0x00, 0xEA, 0x1C, 0x30, 0x1B, 0xE5, 0x00, 0x00, 0x53, 0xE3, 0x01, 0x00, 0x00, 0x1A, 0x03, 0x30, 0xE0, 0xE3, 0x40, 0x00, 0x00, 0xEA, 0x30, 0x30, 0x1B, 0xE5, 0x10, 0x00, 0x53, 0xE3, 0x30, 0x00, 0x00, 0x3A, 0x12, 0x00, 0x53, 0xE3, 0x02, 0x00, 0x00, 0x9A, 0x13, 0x00, 0x53, 0xE3, 0x10, 0x00, 0x00, 0x0A, 0x2B, 0x00, 0x00, 0xEA, 0x08, 0x30, 0x1B, 0xE5, 0xA3, 0x31, 0xA0, 0xE1, 0x03, 0x30, 0xC3, 0xE3, 0xFE, 0x34, 0x83, 0xE2, 0x02, 0x38, 0x83, 0xE2, 0x18, 0x30, 0x0B, 0xE5, 0x18, 0x30, 0x1B, 0xE5, 0x00, 0x30, 0x93, 0xE5, 0x14, 0x30, 0x0B, 0xE5, 0x08, 0x30, 0x1B, 0xE5, 0x1F, 0x30, 0x03, 0xE2, 0x14, 0x20, 0x1B, 0xE5, 0x32, 0x33, 0xA0, 0xE1, 0x3F, 0x30, 0x03, 0xE2, 0x14, 0x30, 0x0B, 0xE5, 0x1D, 0x00, 0x00, 0xEA, 0x08, 0x30, 0x1B, 0xE5, 0xA3, 0x31, 0xA0, 0xE1, 0x03, 0x30, 0xC3, 0xE3, 0xFE, 0x34, 0x83, 0xE2, 0x02, 0x38, 0x83, 0xE2, 0x18, 0x30, 0x0B, 0xE5, 0x18, 0x30, 0x1B, 0xE5, 0x00, 0x30, 0x93, 0xE5, 0x14, 0x30, 0x0B, 0xE5, 0x08, 0x30, 0x1B, 0xE5, 0x1F, 0x30, 0x03, 0xE2, 0x14, 0x20, 0x1B, 0xE5, 0x32, 0x33, 0xA0, 0xE1, 0x3F, 0x30, 0x03, 0xE2, 0x14, 0x30, 0x0B, 0xE5, 0x18, 0x30, 0x1B, 0xE5, 0x04, 0x30, 0x83, 0xE2, 0x24, 0x30, 0x0B, 0xE5, 0x24, 0x30, 0x1B, 0xE5, 0x00, 0x30, 0x93, 0xE5, 0x01, 0x30, 0x03, 0xE2, 0x28, 0x30, 0x0B, 0xE5, 0x28, 0x30, 0x1B, 0xE5, 0x83, 0x32, 0xA0, 0xE1, 0x14, 0x20, 0x1B, 0xE5, 0x03, 0x30, 0x82, 0xE1, 0x14, 0x30, 0x0B, 0xE5, 0x01, 0x00, 0x00, 0xEA, 0x04, 0x30, 0xA0, 0xE3, 0x0A, 0x00, 0x00, 0xEA, 0x14, 0x30, 0x1B, 0xE5, 0x08, 0x00, 0x53, 0xE3, 0x01, 0x00, 0x00, 0x8A, 0x04, 0x30, 0xE0, 0xE3, 0x05, 0x00, 0x00, 0xEA, 0x34, 0x30, 0x1B, 0xE5, 0x00, 0x30, 0x93, 0xE5, 0x14, 0x20, 0x1B, 0xE5, 0x72, 0x20, 0xEF, 0xE6, 0x00, 0x20, 0xC3, 0xE5, 0x00, 0x30, 0xA0, 0xE3, 0x03, 0x00, 0xA0, 0xE1, 0x00, 0xD0, 0x8B, 0xE2, 0x04, 0xB0, 0x9D, 0xE4, 0x1E, 0xFF, 0x2F, 0xE1}; + +#endif \ No newline at end of file diff --git a/board/novatek/na51068/loader/Include/board.h b/board/novatek/na51068/loader/Include/board.h new file mode 100755 index 000000000000..06cbc879e35f --- /dev/null +++ b/board/novatek/na51068/loader/Include/board.h @@ -0,0 +1,139 @@ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +//#define NULL 0 +#define BIT0 0x00000001L +#define BIT1 0x00000002L +#define BIT2 0x00000004L +#define BIT3 0x00000008L +#define BIT4 0x00000010L +#define BIT5 0x00000020L +#define BIT6 0x00000040L +#define BIT7 0x00000080L +#define BIT8 0x00000100L +#define BIT9 0x00000200L +#define BIT10 0x00000400L +#define BIT11 0x00000800L +#define BIT12 0x00001000L +#define BIT13 0x00002000L +#define BIT14 0x00004000L +#define BIT15 0x00008000L +#define BIT16 0x00010000L +#define BIT17 0x00020000L +#define BIT18 0x00040000L +#define BIT19 0x00080000L +#define BIT20 0x00100000L +#define BIT21 0x00200000L +#define BIT22 0x00400000L +#define BIT23 0x00800000L + +#define IMAGE_ADDR 0x100000 +#if (defined(CONFIG_MT) || defined(CONFIG_RA)) +#define LOAD_ADDR 0x0F000040 +#define LOAD_EP_ADDR 0x1F000000 +#else +#define LOAD_ADDR 0xB00000//0xF9001000 +#endif +#define LOAD_FDT_ADDR 0x01F00000 +#define SYS_CLK 12000000 + +#define SRAM0_BASE 0xf9001640 +#define SRAM0_SIZE 0x6000 /* 24K */ +#define SRAM1_BASE SRAM0_BASE+SRAM0_SIZE//(0xf9001200 + 0x6000) +#define SRAM1_SIZE 0x2000 + +//#define AXIC_REMAP 0x130 + +#define REG_HEAVY_LOAD_BASE 0xfd600000 +#define REG_H2X_BASE 0xfe600000 +#define REG_AXIC_BASE 0xfe700000 + +#define REG_UART0_BASE 0xfe200000 +#define REG_UART1_BASE 0xfe220000 +#define REG_UART2_BASE 0xfe240000 +#define REG_TOP_BASE 0xfe030000 +#define REG_PAD_BASE 0xfe040000 +#define REG_PMU_BASE 0xfe000000 +#define REG_DMA_BASE 0xfca00000 /* dmac030 */ + +#define REG_DDR0_BASE 0xfc400000 +#define REG_DDR1_BASE 0xfc500000 +//#define REG_DDR2_BASE 0xfc600000 +//#define REG_DDR3_BASE 0xfc700000 + +//#define REG_GPIO0_BASE 0xfe400000 +//#define REG_GPIO1_BASE 0xfe420000 +#define REG_GPIO2_BASE 0xfe440000 + +#define REG_WDT_BASE 0xfe8a0000 +#define REG_GIC_BASE 0xf9c00000 +//#define REG_SPI020_BASE 0xfa700000 +#define BASE_SPI 0xFA900000 +//#define REG_DMAC020_BASE 0xFA500000 +#define REG_DMAC030_BASE REG_DMA_BASE +#define REG_TMR010_BASE 0xFE8C0000 +#define REG_SDHCI_BASE 0xFA600000 +#define AXI_PCIE_IC10 0xFE840000 /* S1 for pcie0, S2 for pcie1 */ +#define REG_CRYPTO_BASE 0xFEC60000 +#define REG_HASH_BASE 0xFEC80000 +#define REG_RSA_BASE 0xFECA0000 +#define INTC_OSPREY_BASE 0xF8401000 +#define MP0_BASE 0xFDC00000 +#define REG_PWM_BASE 0xFE6C0000 +#define configARM_TIMER_BASEADDR 0xF9C00200 +#define ARM_TIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ +#define ARM_TIMER_COUNTER_OFFSET 0x04 /**< Timer Counter Register */ +#define ARM_TIMER_CONTROL_OFFSET 0x08 /**< Timer Control Register */ +#define ARM_TIMER_ISR_OFFSET 0x0C /**< Timer Interrupt Status Register */ +#define ARM_TIMER_COUNTER_OFFSET_L 0x00 /**< Timer Counter Register */ +#define ARM_TIMER_COUNTER_OFFSET_H 0x04 /**< Timer Counter Register */ +#define ARM_TIMER_COUNTER_CMP_OFFSET_L 0x10 /**< Timer Counter Register */ +#define ARM_TIMER_COUNTER_CMP_OFFSET_H 0x14 /**< Timer Counter Register */ + +#define CYGHWR_HAL_RTC_PRESCALER 1 +#define ARM_TIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */ +#define ARM_TIMER_CONTROL_PRESCALER_SHIFT 8 +#define ARM_TIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004 /**< Intr enable */ +#define ARM_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */ +#define ARM_TIMER_CONTROL_ENABLE_MASK 0x00000001 /**< Timer enable */ + +#define ARM_TIMER_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */ + + +#define PAD_PUPD_REG0 (REG_PAD_BASE + 0x00) +#define PAD_PUPD_REG1 (REG_PAD_BASE + 0x04) +#define PAD_PUPD_REG8 (REG_PAD_BASE + 0x40) + + +#ifndef __ASSEMBLY__ + +#include "constant.h" + +typedef enum +{ + FLASH_NOR = 0, + FLASH_SPI_NAND, + FLASH_SD +} FLASH_TYPE_T; + +unsigned int read_reg(unsigned int reg); +void write_reg(unsigned int reg, unsigned int value); +void sal_memset(void *pbuf, unsigned char val, int len); +int sal_memcmp(void *sbuf, void *dbuf, int len); +//int sal_memcpy(void *sbuf, void *dbuf, int len); +void *memcpy(void *dst, const void *src, unsigned int n); + + +#ifndef OUTW +#define OUTW(addr,value) (*(UINT32 volatile *)(addr) = (UINT32)(value)) +#endif + +#ifndef INW +#define INW(addr) (*(UINT32 volatile *)(addr)) +#endif +#define _ALIGNED(x) __attribute__((aligned(x))) + +#endif /* __ASSEMBLY__ */ + + +#endif diff --git a/board/novatek/na51068/loader/Include/compiler.h b/board/novatek/na51068/loader/Include/compiler.h new file mode 100755 index 000000000000..7fa9b3831ab4 --- /dev/null +++ b/board/novatek/na51068/loader/Include/compiler.h @@ -0,0 +1,56 @@ +/* + * Keep all the ugly #ifdef for system stuff here + */ + +#ifndef __COMPILER_H__ +#define __COMPILER_H__ + +#ifndef NULL +#define NULL 0 +#endif + +#if 0 +#define uswap_16(x) (x) +#define uswap_32(x) (x) +#define _uswap_64(x, sfx) (x) +#else +#define uswap_16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) +#define uswap_32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) +#define _uswap_64(x, sfx) \ + ((((x) & 0xff00000000000000##sfx) >> 56) | \ + (((x) & 0x00ff000000000000##sfx) >> 40) | \ + (((x) & 0x0000ff0000000000##sfx) >> 24) | \ + (((x) & 0x000000ff00000000##sfx) >> 8) | \ + (((x) & 0x00000000ff000000##sfx) << 8) | \ + (((x) & 0x0000000000ff0000##sfx) << 24) | \ + (((x) & 0x000000000000ff00##sfx) << 40) | \ + (((x) & 0x00000000000000ff##sfx) << 56)) +#endif +#if defined(__GNUC__) +#define uswap_64(x) _uswap_64(x, ull) +#else +#define uswap_64(x) _uswap_64(x, ) +#endif +#define cpu_to_le16(x) (x) +#define cpu_to_le32(x) (x) +#define cpu_to_le64(x) (x) +#define le16_to_cpu(x) (x) +#define le32_to_cpu(x) (x) +#define le64_to_cpu(x) (x) +#define cpu_to_be16(x) uswap_16(x) +#define cpu_to_be32(x) uswap_32(x) +#define cpu_to_be64(x) uswap_64(x) +#define be16_to_cpu(x) uswap_16(x) +#define be32_to_cpu(x) uswap_32(x) +#define be64_to_cpu(x) uswap_64(x) + +/* Type for `void *' pointers. */ +typedef unsigned long int uintptr_t; + +#endif diff --git a/board/novatek/na51068/loader/Include/constant.h b/board/novatek/na51068/loader/Include/constant.h new file mode 100755 index 000000000000..bf38c0a333b8 --- /dev/null +++ b/board/novatek/na51068/loader/Include/constant.h @@ -0,0 +1,118 @@ +#ifndef _CONSTANT_H +#define _CONSTANT_H + +//Size MNEMONIC + +#define SZ_1 (1 << 0) /* 0x00000001 */ +#define SZ_2 (1 << 1) /* 0x00000002 */ +#define SZ_4 (1 << 2) /* 0x00000004 */ +#define SZ_8 (1 << 3) /* 0x00000008 */ +#define SZ_16 (1 << 4) /* 0x00000010 */ +#define SZ_32 (1 << 5) /* 0x00000020 */ +#define SZ_64 (1 << 6) /* 0x00000040 */ +#define SZ_128 (1 << 7) /* 0x00000080 */ +#define SZ_256 (1 << 8) /* 0x00000100 */ +#define SZ_512 (1 << 9) /* 0x00000200 */ + +#define SZ_1K (1 << 10) /* 0x00000400 */ +#define SZ_2K (1 << 11) /* 0x00000800 */ +#define SZ_4K (1 << 12) /* 0x00001000 */ +#define SZ_8K (1 << 13) /* 0x00002000 */ +#define SZ_16K (1 << 14) /* 0x00004000 */ +#define SZ_32K (1 << 15) /* 0x00008000 */ +#define SZ_64K (1 << 16) /* 0x00010000 */ +#define SZ_128K (1 << 17) /* 0x00020000 */ +#define SZ_256K (1 << 18) /* 0x00040000 */ +#define SZ_512K (1 << 19) /* 0x00080000 */ + +#define SZ_1M (1 << 20) /* 0x00100000 */ +#define SZ_2M (1 << 21) /* 0x00200000 */ +#define SZ_4M (1 << 22) /* 0x00400000 */ +#define SZ_8M (1 << 23) /* 0x00800000 */ +#define SZ_16M (1 << 24) /* 0x01000000 */ +#define SZ_32M (1 << 25) /* 0x02000000 */ +#define SZ_64M (1 << 26) /* 0x04000000 */ +#define SZ_128M (1 << 27) /* 0x08000000 */ +#define SZ_256M (1 << 28) /* 0x10000000 */ +#define SZ_512M (1 << 29) /* 0x20000000 */ + +#define SZ_1G (1 << 30) /* 0x40000000 */ +#define SZ_2G (1 << 31) /* 0x80000000 */ + +#define SZ_30M (SZ_32M - SZ_2M) + +// ASCII code + +#define CR 0x0D +#define LF 0x0A +#define BS 0x08 +#define ESC 27 + +// Boolean constant definition + +#if 0 +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef ON +#define ON 1 +#endif + +#ifndef OFF +#define OFF 0 +#endif + +#ifndef ENABLE +#define ENABLE 1 +#endif + +#ifndef DISABLE +#define DISABLE 0 +#endif + +#ifndef DISK_FULL +#define DISK_FULL (-1) +#endif + +// type declaration +typedef unsigned int UINT32; +typedef unsigned int INT32U; +typedef int INT32; +typedef int INT32S; +typedef unsigned short UINT16; +typedef unsigned short INT16U; +typedef short INT16; +typedef unsigned char UINT8; +typedef unsigned char INT8U; +typedef char INT8; +typedef char INT8S; +typedef unsigned int BOOL; +typedef unsigned long long u64; +typedef unsigned int u32; +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int uint; +typedef unsigned short ushort; +typedef unsigned char uchar; +typedef int BOOLEAN; +typedef unsigned long long UINT64; +typedef long long INT64; +typedef unsigned int UINT; +typedef int INT; +typedef long ER; + +enum {FALSE=0, TRUE=1}; + +// error codes +typedef long ER; + +#endif diff --git a/board/novatek/na51068/loader/Include/ctype.h b/board/novatek/na51068/loader/Include/ctype.h new file mode 100755 index 000000000000..dbbc7cf7dd9c --- /dev/null +++ b/board/novatek/na51068/loader/Include/ctype.h @@ -0,0 +1,36 @@ + + +#ifndef NVT_CTYPES_H__ +#define NVT_CTYPES_H__ + + +#define _U 0x01 /* upper */ +#define _L 0x02 /* lower */ +#define _D 0x04 /* digit */ +#define _C 0x08 /* cntrl */ +#define _P 0x10 /* punct */ +#define _S 0x20 /* white space (space/lf/tab) */ +#define _X 0x40 /* hex digit */ +#define _SP 0x80 /* hard space (0x20) */ + +extern unsigned char _ctype[]; + +#define __ismask(x) (_ctype[(int)(unsigned char)(x)]) + +#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) +#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) +#define iscntrl(c) ((__ismask(c)&(_C)) != 0) +#define isdigit(c) ((__ismask(c)&(_D)) != 0) +#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) +#define islower(c) ((__ismask(c)&(_L)) != 0) +#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) +#define ispunct(c) ((__ismask(c)&(_P)) != 0) +#define isspace(c) ((__ismask(c)&(_S)) != 0) +#define isupper(c) ((__ismask(c)&(_U)) != 0) +#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) + +#define isascii(c) (((unsigned char)(c))<=0x7f) +#define toascii(c) (((unsigned char)(c))&0x7f) + + +#endif diff --git a/board/novatek/na51068/loader/Include/data_keeper.h b/board/novatek/na51068/loader/Include/data_keeper.h new file mode 100755 index 000000000000..3a32e8f47db1 --- /dev/null +++ b/board/novatek/na51068/loader/Include/data_keeper.h @@ -0,0 +1,17 @@ +#ifndef __DATA_KEEPER_H__ +#define __DATA_KEEPER_H__ + +struct buffer_info_t { + unsigned char *data; + unsigned int size; + unsigned int read_which_chip; +}; + +typedef enum { + READ_FROM_RC = 0, + READ_FROM_EP0 = 1 +} READ_FROM_CHIP_TYPE; + +int read_system_data(unsigned int data_id, struct buffer_info_t *buffer); + +#endif diff --git a/board/novatek/na51068/loader/Include/debug.h b/board/novatek/na51068/loader/Include/debug.h new file mode 100755 index 000000000000..5cf99e50bdcb --- /dev/null +++ b/board/novatek/na51068/loader/Include/debug.h @@ -0,0 +1,31 @@ +/** + string header + + string header + + @file string.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_DEBUG_H__ +#define __NVT_DEBUG_H__ + +#include "fuart.h" +/** \addtogroup mISYSClib */ +//@{ + +extern void debug_set_console(CONSOLE_OBJ *p_obj); +extern void debug_err(char *str); +extern void debug_err_var(char *str, int var); +extern void debug_msg(char *str); +extern void debug_msg_var(char *str, int var); +extern void debug_dump_addr(UINT32 addr, UINT32 size); + + +//@} + +#endif + diff --git a/board/novatek/na51068/loader/Include/fat.h b/board/novatek/na51068/loader/Include/fat.h new file mode 100755 index 000000000000..618767a91580 --- /dev/null +++ b/board/novatek/na51068/loader/Include/fat.h @@ -0,0 +1,48 @@ +/** + File system library + + This file is the library of file system + + @file fat.h + @ingroup mISYSFile + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _FAT_H +#define _FAT_H + +#include "board.h" +#include "StorageDef.h" +#include "compiler.h" +/** + @addtogroup mISYSFile +*/ +//@{ + +#define FAT_READ_TOTAL_FILE_LENGTH 0 + +typedef void (*TOGGLE_LED)(UINT8 WithCount); + +extern BOOL fat_initFAT(UINT32 uiBuf, UINT32 uiSize); +extern UINT32 fat_getPartitionCount(void); +extern BOOL fat_mountPartition(UINT32 partition_id); +extern void fat_closeFAT(void); +extern BOOL fat_open_rootfile(UINT8 *pfilename); +extern UINT32 fat_read_rootfile(UINT8 *pbuf, UINT32 uiRdLen); +extern UINT32 fat_getRootfileSize(void); +extern void fat_close_rootfile(void); +extern void fat_regToggleLED(TOGGLE_LED pToggleLED); +extern void fat_installAccessCB(STRG_ACCESS_CB accessCB); + +// For SD registration +extern BOOL fat_internal_initFAT(UINT32 uiBuf, UINT32 uiSize); +extern BOOL fat_internal_open_rootfile(UINT8 *pfilename); +extern UINT32 fat_internal_read_rootfile(UINT8 *pbuf, UINT32 uiRdLen); +extern void fat_internal_close_rootfile(void); + +//@} + +#endif + diff --git a/board/novatek/na51068/loader/Include/fdt.h b/board/novatek/na51068/loader/Include/fdt.h new file mode 100755 index 000000000000..0187749f19b6 --- /dev/null +++ b/board/novatek/na51068/loader/Include/fdt.h @@ -0,0 +1,111 @@ +#ifndef _FDT_H +#define _FDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ASSEMBLY__ + +struct fdt_header { + fdt32_t magic; /* magic word FDT_MAGIC */ + fdt32_t totalsize; /* total size of DT block */ + fdt32_t off_dt_struct; /* offset to structure */ + fdt32_t off_dt_strings; /* offset to strings */ + fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ + fdt32_t version; /* format version */ + fdt32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + fdt32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + fdt32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + fdt32_t size_dt_struct; /* size of the structure block */ +}; + +struct fdt_reserve_entry { + fdt64_t address; + fdt64_t size; +}; + +struct fdt_node_header { + fdt32_t tag; + char name[0]; +}; + +struct fdt_property { + fdt32_t tag; + fdt32_t len; + fdt32_t nameoff; + char data[0]; +}; + +#endif /* !__ASSEMBLY */ + +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_TAGSIZE sizeof(fdt32_t) + +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, + size, content */ +#define FDT_NOP 0x4 /* nop */ +#define FDT_END 0x9 + +#define FDT_V1_SIZE (7*sizeof(fdt32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) +#define FDT_V16_SIZE FDT_V3_SIZE +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) + +#endif /* _FDT_H */ diff --git a/board/novatek/na51068/loader/Include/fdt/compiler.h b/board/novatek/na51068/loader/Include/fdt/compiler.h new file mode 100755 index 000000000000..7fa9b3831ab4 --- /dev/null +++ b/board/novatek/na51068/loader/Include/fdt/compiler.h @@ -0,0 +1,56 @@ +/* + * Keep all the ugly #ifdef for system stuff here + */ + +#ifndef __COMPILER_H__ +#define __COMPILER_H__ + +#ifndef NULL +#define NULL 0 +#endif + +#if 0 +#define uswap_16(x) (x) +#define uswap_32(x) (x) +#define _uswap_64(x, sfx) (x) +#else +#define uswap_16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) +#define uswap_32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) +#define _uswap_64(x, sfx) \ + ((((x) & 0xff00000000000000##sfx) >> 56) | \ + (((x) & 0x00ff000000000000##sfx) >> 40) | \ + (((x) & 0x0000ff0000000000##sfx) >> 24) | \ + (((x) & 0x000000ff00000000##sfx) >> 8) | \ + (((x) & 0x00000000ff000000##sfx) << 8) | \ + (((x) & 0x0000000000ff0000##sfx) << 24) | \ + (((x) & 0x000000000000ff00##sfx) << 40) | \ + (((x) & 0x00000000000000ff##sfx) << 56)) +#endif +#if defined(__GNUC__) +#define uswap_64(x) _uswap_64(x, ull) +#else +#define uswap_64(x) _uswap_64(x, ) +#endif +#define cpu_to_le16(x) (x) +#define cpu_to_le32(x) (x) +#define cpu_to_le64(x) (x) +#define le16_to_cpu(x) (x) +#define le32_to_cpu(x) (x) +#define le64_to_cpu(x) (x) +#define cpu_to_be16(x) uswap_16(x) +#define cpu_to_be32(x) uswap_32(x) +#define cpu_to_be64(x) uswap_64(x) +#define be16_to_cpu(x) uswap_16(x) +#define be32_to_cpu(x) uswap_32(x) +#define be64_to_cpu(x) uswap_64(x) + +/* Type for `void *' pointers. */ +typedef unsigned long int uintptr_t; + +#endif diff --git a/board/novatek/na51068/loader/Include/fdt/fdt.h b/board/novatek/na51068/loader/Include/fdt/fdt.h new file mode 100755 index 000000000000..0187749f19b6 --- /dev/null +++ b/board/novatek/na51068/loader/Include/fdt/fdt.h @@ -0,0 +1,111 @@ +#ifndef _FDT_H +#define _FDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ASSEMBLY__ + +struct fdt_header { + fdt32_t magic; /* magic word FDT_MAGIC */ + fdt32_t totalsize; /* total size of DT block */ + fdt32_t off_dt_struct; /* offset to structure */ + fdt32_t off_dt_strings; /* offset to strings */ + fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ + fdt32_t version; /* format version */ + fdt32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + fdt32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + fdt32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + fdt32_t size_dt_struct; /* size of the structure block */ +}; + +struct fdt_reserve_entry { + fdt64_t address; + fdt64_t size; +}; + +struct fdt_node_header { + fdt32_t tag; + char name[0]; +}; + +struct fdt_property { + fdt32_t tag; + fdt32_t len; + fdt32_t nameoff; + char data[0]; +}; + +#endif /* !__ASSEMBLY */ + +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_TAGSIZE sizeof(fdt32_t) + +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, + size, content */ +#define FDT_NOP 0x4 /* nop */ +#define FDT_END 0x9 + +#define FDT_V1_SIZE (7*sizeof(fdt32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) +#define FDT_V16_SIZE FDT_V3_SIZE +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) + +#endif /* _FDT_H */ diff --git a/board/novatek/na51068/loader/Include/fdt/libfdt.h b/board/novatek/na51068/loader/Include/fdt/libfdt.h new file mode 100755 index 000000000000..9cade83bb638 --- /dev/null +++ b/board/novatek/na51068/loader/Include/fdt/libfdt.h @@ -0,0 +1,1578 @@ +#ifndef _LIBFDT_H +#define _LIBFDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "libfdt_env.h" +#include "fdt.h" + +#define FDT_FIRST_SUPPORTED_VERSION 0x10 +#define FDT_LAST_SUPPORTED_VERSION 0x11 + +/* Error codes: informative error codes */ +#define FDT_ERR_NOTFOUND 1 + /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ +#define FDT_ERR_EXISTS 2 + /* FDT_ERR_EXISTS: Attemped to create a node or property which + * already exists */ +#define FDT_ERR_NOSPACE 3 + /* FDT_ERR_NOSPACE: Operation needed to expand the device + * tree, but its buffer did not have sufficient space to + * contain the expanded tree. Use fdt_open_into() to move the + * device tree to a buffer with more space. */ + +/* Error codes: codes for bad parameters */ +#define FDT_ERR_BADOFFSET 4 + /* FDT_ERR_BADOFFSET: Function was passed a structure block + * offset which is out-of-bounds, or which points to an + * unsuitable part of the structure for the operation. */ +#define FDT_ERR_BADPATH 5 + /* FDT_ERR_BADPATH: Function was passed a badly formatted path + * (e.g. missing a leading / for a function which requires an + * absolute path) */ +#define FDT_ERR_BADPHANDLE 6 + /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle + * value. phandle values of 0 and -1 are not permitted. */ +#define FDT_ERR_BADSTATE 7 + /* FDT_ERR_BADSTATE: Function was passed an incomplete device + * tree created by the sequential-write functions, which is + * not sufficiently complete for the requested operation. */ + +/* Error codes: codes for bad device tree blobs */ +#define FDT_ERR_TRUNCATED 8 + /* FDT_ERR_TRUNCATED: Structure block of the given device tree + * ends without an FDT_END tag. */ +#define FDT_ERR_BADMAGIC 9 + /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a + * device tree at all - it is missing the flattened device + * tree magic number. */ +#define FDT_ERR_BADVERSION 10 + /* FDT_ERR_BADVERSION: Given device tree has a version which + * can't be handled by the requested operation. For + * read-write functions, this may mean that fdt_open_into() is + * required to convert the tree to the expected version. */ +#define FDT_ERR_BADSTRUCTURE 11 + /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt + * structure block or other serious error (e.g. misnested + * nodes, or subnodes preceding properties). */ +#define FDT_ERR_BADLAYOUT 12 + /* FDT_ERR_BADLAYOUT: For read-write functions, the given + * device tree has it's sub-blocks in an order that the + * function can't handle (memory reserve map, then structure, + * then strings). Use fdt_open_into() to reorganize the tree + * into a form suitable for the read-write operations. */ + +/* "Can't happen" error indicating a bug in libfdt */ +#define FDT_ERR_INTERNAL 13 + /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. + * Should never be returned, if it is, it indicates a bug in + * libfdt itself. */ + +#define FDT_ERR_MAX 13 + +/**********************************************************************/ +/* Low-level functions (you probably don't need these) */ +/**********************************************************************/ + +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); +static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) +{ + return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); +} + +uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); + +/**********************************************************************/ +/* Traversal functions */ +/**********************************************************************/ + +int fdt_next_node(const void *fdt, int offset, int *depth); + +/** + * fdt_first_subnode() - get offset of first direct subnode + * + * @fdt: FDT blob + * @offset: Offset of node to check + * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + */ +int fdt_first_subnode(const void *fdt, int offset); + +/** + * fdt_next_subnode() - get offset of next direct subnode + * + * After first calling fdt_first_subnode(), call this function repeatedly to + * get direct subnodes of a parent node. + * + * @fdt: FDT blob + * @offset: Offset of previous subnode + * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes + */ +int fdt_next_subnode(const void *fdt, int offset); + +/**********************************************************************/ +/* General functions */ +/**********************************************************************/ + +#define fdt_get_header(fdt, field) \ + (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) +#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) +#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) +#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) +#define fdt_version(fdt) (fdt_get_header(fdt, version)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) + +#define __fdt_set_hdr(name) \ + static inline void fdt_set_##name(void *fdt, uint32_t val) \ + { \ + struct fdt_header *fdth = (struct fdt_header*)fdt; \ + fdth->name = cpu_to_fdt32(val); \ + } +__fdt_set_hdr(magic); +__fdt_set_hdr(totalsize); +__fdt_set_hdr(off_dt_struct); +__fdt_set_hdr(off_dt_strings); +__fdt_set_hdr(off_mem_rsvmap); +__fdt_set_hdr(version); +__fdt_set_hdr(last_comp_version); +__fdt_set_hdr(boot_cpuid_phys); +__fdt_set_hdr(size_dt_strings); +__fdt_set_hdr(size_dt_struct); +#undef __fdt_set_hdr + +/** + * fdt_check_header - sanity check a device tree or possible device tree + * @fdt: pointer to data which might be a flattened device tree + * + * fdt_check_header() checks that the given buffer contains what + * appears to be a flattened device tree with sane information in its + * header. + * + * returns: + * 0, if the buffer appears to contain a valid device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings, as above + */ +int fdt_check_header(const void *fdt); + +/** + * fdt_move - move a device tree around in memory + * @fdt: pointer to the device tree to move + * @buf: pointer to memory where the device is to be moved + * @bufsize: size of the memory space at buf + * + * fdt_move() relocates, if possible, the device tree blob located at + * fdt to the buffer at buf of size bufsize. The buffer may overlap + * with the existing device tree blob at fdt. Therefore, + * fdt_move(fdt, fdt, fdt_totalsize(fdt)) + * should always succeed. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_move(const void *fdt, void *buf, int bufsize); + +/**********************************************************************/ +/* Read-only functions */ +/**********************************************************************/ + +/** + * fdt_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * + * fdt_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds + */ +const char *fdt_string(const void *fdt, int stroffset); + +/** + * fdt_num_mem_rsv - retrieve the number of memory reserve map entries + * @fdt: pointer to the device tree blob + * + * Returns the number of entries in the device tree blob's memory + * reservation map. This does not include the terminating 0,0 entry + * or any other (0,0) entries reserved for expansion. + * + * returns: + * the number of entries + */ +int fdt_num_mem_rsv(const void *fdt); + +/** + * fdt_get_mem_rsv - retrieve one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: pointers to 64-bit variables + * + * On success, *address and *size will contain the address and size of + * the n-th reserve map entry from the device tree blob, in + * native-endian format. + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); + +/** + * fdt_subnode_offset_namelen - find a subnode based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_subnode_offset(), but only examine the first + * namelen characters of name for matching the subnode name. This is + * useful for finding subnodes based on a portion of a larger string, + * such as a full path. + */ +int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, + const char *name, int namelen); +/** + * fdt_subnode_offset - find a subnode of a given node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node at structure block + * offset parentoffset with the given name. name may include a unit + * address, in which case fdt_subnode_offset() will find the subnode + * with that unit address, or the unit address may be omitted, in + * which case fdt_subnode_offset() will find an arbitrary subnode + * whose name excluding unit address matches the given name. + * + * returns: + * structure block offset of the requested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); + +/** + * fdt_path_offset - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * + * fdt_path_offset() finds a node of a given path in the device tree. + * Each path component may omit the unit address portion, but the + * results of this are undefined if any such path component is + * ambiguous (that is if there are multiple nodes at the relevant + * level matching the given component, differentiated only by unit + * address). + * + * returns: + * structure block offset of the node with the requested path (>=0), on success + * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_NOTFOUND, if the requested node does not exist + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_path_offset(const void *fdt, const char *path); + +/** + * fdt_get_name - retrieve the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the starting node + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_name() retrieves the name (including unit address) of the + * device tree node at structure block offset nodeoffset. If lenp is + * non-NULL, the length of this name is also returned, in the integer + * pointed to by lenp. + * + * returns: + * pointer to the node's name, on success + * If lenp is non-NULL, *lenp contains the length of that name (>=0) + * NULL, on error + * if lenp is non-NULL *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); + +/** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** + * fdt_get_property_namelen - find a property based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_get_property_namelen(), but only examine the first + * namelen characters of name for matching the property name. + */ +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int nodeoffset, + const char *name, + int namelen, int *lenp); + +/** + * fdt_get_property - find a given property in a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property() retrieves a pointer to the fdt_property + * structure within the device tree blob corresponding to the property + * named 'name' of the node at offset nodeoffset. If lenp is + * non-NULL, the length of the property value is also returned, in the + * integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, + const char *name, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @ffset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); + +/** + * fdt_getprop_namelen - get property value based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_getprop(), but only examine the first namelen + * characters of name for matching the property name. + */ +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp); + +/** + * fdt_getprop - retrieve the value of a given property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline void *fdt_getprop_w(void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_get_phandle - retrieve the phandle of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the node + * + * fdt_get_phandle() retrieves the phandle of the device tree node at + * structure block offset nodeoffset. + * + * returns: + * the phandle of the node at nodeoffset, on success (!= 0, != -1) + * 0, if the node has no phandle, or another error occurs + */ +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); + +/** + * fdt_get_alias_namelen - get alias based on substring + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * @namelen: number of characters of name to consider + * + * Identical to fdt_get_alias(), but only examine the first namelen + * characters of name for matching the alias name. + */ +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen); + +/** + * fdt_get_alias - retrieve the path referenced by a given alias + * @fdt: pointer to the device tree blob + * @name: name of the alias to look up + * + * fdt_get_alias() retrieves the value of a given alias. That is, the + * value of the property named 'name' in the node /aliases. + * + * returns: + * a pointer to the expansion of the alias named 'name', if it exists + * NULL, if the given alias or the /aliases node does not exist + */ +const char *fdt_get_alias(const void *fdt, const char *name); + +/** + * fdt_get_path - determine the full path of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose path to find + * @buf: character buffer to contain the returned path (will be overwritten) + * @buflen: size of the character buffer at buf + * + * fdt_get_path() computes the full path of the node at offset + * nodeoffset, and records that path in the buffer at buf. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * 0, on success + * buf contains the absolute path of the node at + * nodeoffset, as a NUL-terminated string. + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) + * characters and will not fit in the given buffer. + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); + +/** + * fdt_supernode_atdepth_offset - find a specific ancestor of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * @supernodedepth: depth of the ancestor to find + * @nodedepth: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_supernode_atdepth_offset() finds an ancestor of the given node + * at a specific depth from the root (where the root itself has depth + * 0, its immediate subnodes depth 1 and so forth). So + * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); + * will always return 0, the offset of the root node. If the node at + * nodeoffset has depth D, then: + * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); + * will return nodeoffset itself. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + + * structure block offset of the node at node offset's ancestor + * of depth supernodedepth (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag +* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth); + +/** + * fdt_node_depth - find the depth of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_node_depth() finds the depth of a given node. The root node + * has depth 0, its immediate subnodes depth 1 and so forth. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * depth of the node at nodeoffset (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_depth(const void *fdt, int nodeoffset); + +/** + * fdt_parent_offset - find the parent of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_parent_offset() locates the parent node of a given node (that + * is, it finds the offset of the node which contains the node at + * nodeoffset as a subnode). + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset, *twice*. + * + * returns: + * structure block offset of the parent of the node at nodeoffset + * (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_parent_offset(const void *fdt, int nodeoffset); + +/** + * fdt_node_offset_by_prop_value - find nodes with a given property value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * + * fdt_node_offset_by_prop_value() returns the offset of the first + * node after startoffset, which has a property named propname whose + * value is of length proplen and has value equal to propval; or if + * startoffset is -1, the very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, + * propval, proplen); + * while (offset != -FDT_ERR_NOTFOUND) { + * ... other code here ... + * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, + * propval, proplen); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen); + +/** + * fdt_node_offset_by_phandle - find the node with a given phandle + * @fdt: pointer to the device tree blob + * @phandle: phandle value + * + * fdt_node_offset_by_phandle() returns the offset of the node + * which has the given phandle value. If there is more than one node + * in the tree with the given phandle (an invalid tree), results are + * undefined. + * + * returns: + * structure block offset of the located node (>= 0), on success + * -FDT_ERR_NOTFOUND, no node with that phandle exists + * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); + +/** + * fdt_node_check_compatible: check a node's compatible property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @compatible: string to match against + * + * + * fdt_node_check_compatible() returns 0 if the given node contains a + * 'compatible' property with the given string as one of its elements, + * it returns non-zero otherwise, or on error. + * + * returns: + * 0, if the node has a 'compatible' property listing the given string + * 1, if the node has a 'compatible' property, but it does not list + * the given string + * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property + * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible); + +/** + * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @compatible: 'compatible' string to match against + * + * fdt_node_offset_by_compatible() returns the offset of the first + * node after startoffset, which has a 'compatible' property which + * lists the given compatible string; or if startoffset is -1, the + * very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); + * while (offset != -FDT_ERR_NOTFOUND) { + * ... other code here ... + * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible); + +/** + * fdt_stringlist_contains - check a string list property for a string + * @strlist: Property containing a list of strings to check + * @listlen: Length of property + * @str: String to search for + * + * This is a utility function provided for convenience. The list contains + * one or more strings, each terminated by \0, as is found in a device tree + * "compatible" property. + * + * @return: 1 if the string is found in the list, 0 not found, or invalid list + */ +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); + +/**********************************************************************/ +/* Write-in-place functions */ +/**********************************************************************/ + +/** + * fdt_setprop_inplace - change a property's value, but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * fdt_setprop_inplace() replaces the value of a given property with + * the data in val, of length len. This function cannot change the + * size of a property, and so will only work if len is equal to the + * current length of the property. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if len is not equal to the property's current length + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to replace the property with + * + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_nop_property - replace a property with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_nop_property() will replace a given property's representation + * in the blob with FDT_NOP tags, effectively removing it from the + * tree. + * + * This function will alter only the bytes in the blob which contain + * the property, and will not alter or move any other part of the + * tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_property(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_nop_node - replace a node (subtree) with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_nop_node() will replace a given node's representation in the + * blob, including all its subnodes, if any, with FDT_NOP tags, + * effectively removing it from the tree. + * + * This function will alter only the bytes in the blob which contain + * the node and its properties and subnodes, and will not alter or + * move any other part of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Sequential write functions */ +/**********************************************************************/ + +int fdt_create(void *buf, int bufsize); +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); +int fdt_finish_reservemap(void *fdt); +int fdt_begin_node(void *fdt, const char *name); +int fdt_property(void *fdt, const char *name, const void *val, int len); +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} +#define fdt_property_string(fdt, name, str) \ + fdt_property(fdt, name, str, strlen(str)+1) +int fdt_end_node(void *fdt); +int fdt_finish(void *fdt); + +/**********************************************************************/ +/* Read-write functions */ +/**********************************************************************/ + +int fdt_create_empty_tree(void *buf, int bufsize); +int fdt_open_into(const void *fdt, void *buf, int bufsize); +int fdt_pack(void *fdt); + +/** + * fdt_add_mem_rsv - add one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: 64-bit values (native endian) + * + * Adds a reserve map entry to the given blob reserving a region at + * address address of length size. + * + * This function will insert data into the reserve map and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new reservation entry + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); + +/** + * fdt_del_mem_rsv - remove a memory reserve map entry + * @fdt: pointer to the device tree blob + * @n: entry to remove + * + * fdt_del_mem_rsv() removes the n-th memory reserve map entry from + * the blob. + * + * This function will delete data from the reservation table and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there + * are less than n+1 reserve map entries) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_mem_rsv(void *fdt, int n); + +/** + * fdt_set_name - change the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * @name: name to give the node + * + * fdt_set_name() replaces the name (including unit address, if any) + * of the given node with the given string. NOTE: this function can't + * efficiently check if the new name is unique amongst the given + * node's siblings; results are undefined if this function is invoked + * with a name equal to one of the given node's siblings. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob + * to contain the new name + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_set_name(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_setprop - create or change a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_setprop() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_u32 - set a property to a 32-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) + * + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_setprop_string - set a property to a string value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value for the property + * + * fdt_setprop_string() sets the value of the named property in the + * given node to the given string value (using the length of the + * string to determine the new length of the property), or creates a + * new property with that value if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_string(fdt, nodeoffset, name, str) \ + fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_u32 - append a 32-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_delprop - delete a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_del_property() will delete the given property. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_delprop(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_add_subnode_namelen - creates a new node based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_add_subnode(), but use only the first namelen + * characters of name as the name of the new node. This is useful for + * creating subnodes based on a portion of a larger string, such as a + * full path. + */ +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen); + +/** + * fdt_add_subnode - creates a new node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_add_subnode() creates a new node as a subnode of the node at + * structure block offset parentoffset, with the given name (which + * should include the unit address, if any). + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + + * returns: + * structure block offset of the created nodeequested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * fdt_del_node - delete a node (subtree) + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_del_node() will remove the given node, including all its + * subnodes if any, from the blob. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Debugging / informational functions */ +/**********************************************************************/ + +const char *fdt_strerror(int errval); + +struct fdt_region { + int offset; + int size; +}; + +/** + * fdt_find_regions() - find regions in device tree + * + * Given a list of nodes to include and properties to exclude, find + * the regions of the device tree which describe those included parts. + * + * The intent is to get a list of regions which will be invariant provided + * those parts are invariant. For example, if you request a list of regions + * for all nodes but exclude the property "data", then you will get the + * same region contents regardless of any change to "data" properties. + * + * This function can be used to produce a byte-stream to send to a hashing + * function to verify that critical parts of the FDT have not changed. + * + * Nodes which are given in 'inc' are included in the region list, as + * are the names of the immediate subnodes nodes (but not the properties + * or subnodes of those subnodes). + * + * For eaxample "/" means to include the root node, all root properties + * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter + * ensures that we capture the names of the subnodes. In a hashing situation + * it prevents the root node from changing at all Any change to non-excluded + * properties, names of subnodes or number of subnodes would be detected. + * + * When used with FITs this provides the ability to hash and sign parts of + * the FIT based on different configurations in the FIT. Then it is + * impossible to change anything about that configuration (include images + * attached to the configuration), but it may be possible to add new + * configurations, new images or new signatures within the existing + * framework. + * + * Adding new properties to a device tree may result in the string table + * being extended (if the new property names are different from those + * already added). This function can optionally include a region for + * the string table so that this can be part of the hash too. + * + * The device tree header is not included in the list. + * + * @fdt: Device tree to check + * @inc: List of node paths to included + * @inc_count: Number of node paths in list + * @exc_prop: List of properties names to exclude + * @exc_prop_count: Number of properties in exclude list + * @region: Returns list of regions + * @max_region: Maximum length of region list + * @path: Pointer to a temporary string for the function to use for + * building path names + * @path_len: Length of path, must be large enough to hold the longest + * path in the tree + * @add_string_tab: 1 to add a region for the string table + * @return number of regions in list. If this is >max_regions then the + * region array was exhausted. You should increase max_regions and try + * the call again. + */ +int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, + char * const exc_prop[], int exc_prop_count, + struct fdt_region region[], int max_regions, + char *path, int path_len, int add_string_tab); + +#endif /* _LIBFDT_H */ diff --git a/board/novatek/na51068/loader/Include/fdt/libfdt_env.h b/board/novatek/na51068/loader/Include/fdt/libfdt_env.h new file mode 100755 index 000000000000..5573b3f8c523 --- /dev/null +++ b/board/novatek/na51068/loader/Include/fdt/libfdt_env.h @@ -0,0 +1,63 @@ +/* + * libfdt - Flat Device Tree manipulation (build/run environment adaptation) + * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * Original version written by David Gibson, IBM Corporation. + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef _LIBFDT_ENV_H +#define _LIBFDT_ENV_H + +#include "compiler.h" + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +typedef __u8 uint8_t; +typedef __u16 uint16_t; +typedef __u32 uint32_t; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __u64 uint64_t; +typedef __u64 u_int64_t; +typedef __s64 int64_t; +#endif + +#define __bitwise + +typedef __u16 __bitwise __le16; +typedef __u16 __bitwise __be16; +typedef __u32 __bitwise __le32; +typedef __u32 __bitwise __be32; +#if defined(__GNUC__) +typedef __u64 __bitwise __le64; +typedef __u64 __bitwise __be64; +#endif + +extern struct fdt_header *working_fdt; /* Pointer to the working fdt */ + +typedef __be16 fdt16_t; +typedef __be32 fdt32_t; +typedef __be64 fdt64_t; + +#define fdt32_to_cpu(x) be32_to_cpu(x) +#define cpu_to_fdt32(x) cpu_to_be32(x) +#define fdt64_to_cpu(x) be64_to_cpu(x) +#define cpu_to_fdt64(x) cpu_to_be64(x) + +/* adding a ramdisk needs 0x44 bytes in version 2008.10 */ +#define FDT_RAMDISK_OVERHEAD 0x80 + +#endif /* _LIBFDT_ENV_H */ diff --git a/board/novatek/na51068/loader/Include/fuart.h b/board/novatek/na51068/loader/Include/fuart.h new file mode 100755 index 000000000000..50584e8a43b0 --- /dev/null +++ b/board/novatek/na51068/loader/Include/fuart.h @@ -0,0 +1,81 @@ +/** + Header file for UART + + This file is the header file for UART driver + + @file fuart.h + @ingroup mIIOUART + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + + +#ifndef _FUART_H +#define _FUART_H + +#include "board.h" + +/** + @addtogroup mIIOUART +*/ + /** + Macro to generate dummy element for enum type to expand enum size to word (4 bytes) + */ + //@{ + #ifndef ENUM_DUMMY4WORD + #define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + #endif + //@} +//@} +//@{ +typedef enum { + CONSOLE_UART0, + CONSOLE_UART1, + + ENUM_DUMMY4WORD(UART_CONSOLE_CH) +} UART_CONSOLE_CH; + + +typedef struct _CONSOLE { + void (*hook)(void); ///< start this object + void (*putc)(char c); ///< console input funciton pointer + unsigned char (*getc)(void); ///< console output function point +} CONSOLE_OBJ, *PCONSOLE_OBJ; + +/** + @name Put system UART string + + Print string to UART + + @param[in] m printed string +*/ +//@{ +//#define uart_putSystemUARTStr(m) fLib_PutSerialStr(m) ///< Print string MACRO +//@} + +/** + @name Put system UART character + + Print character to UART + + @param[in] m printed character +*/ +//@{ +#define fLib_PutSerialChar(m) serial_putc(m) +#define uart_putSystemUARTChar(m) fLib_PutSerialChar(m) ///< Print character MACRO +//@} + + + + +void serial_init(void); +unsigned char serial_getc(void); +void serial_putc(char c); +void uart_putSystemUARTStr(char *str); +PCONSOLE_OBJ get_uart_object(UART_CONSOLE_CH uart_ch); + + +//@} + +#endif diff --git a/board/novatek/na51068/loader/Include/global.h b/board/novatek/na51068/loader/Include/global.h new file mode 100755 index 000000000000..873bda2d176e --- /dev/null +++ b/board/novatek/na51068/loader/Include/global.h @@ -0,0 +1,67 @@ +/** + Global utility header file + + Global utility header file + + @file global.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef _GLOBAL_H +#define _GLOBAL_H + +#include "board.h" + + +#define BOOT_SOURCE_SPI 0x00 +#define BOOT_SOURCE_SPI_NAND 0x01 +#define BOOT_SOURCE_USB 0x02 +#define BOOT_SOURCE_ETHERNET 0x03 +#define BOOT_SOURCE_UART 0x04 +#define BOOT_SOURCE_CARD 0x05 + +#define BOOT_SOURCE_MSK 0x07 + +#define CHIPVER_A 0x0 +#define CHIPVER_B 0x1 + +/** + @addtogroup mISYSUtil +*/ +//@{ +extern char* Dec2HexStr(UINT32 data); +extern void PrintDec2Hex(UINT32 data) __attribute__ ((section (".part1"))); +extern char* Dec2HexStr2Bytes(UINT32 data); +extern void PrintDec2HexStr2Bytes(UINT32 data) __attribute__ ((section (".part1"))); +extern UINT32 DecStr2Int(char* str); +extern UINT32 bitCount(UINT32 data); +extern void exit(int num); + +extern int printf(char const *, ...) __attribute__ ((section (".part1")));; +extern BOOL utl_is_sram_fw(UINT32 fw_addr); +extern UINT32 utl_get_bootsrc(void); +extern UINT32 utl_get_chipversion(void); +extern void UTL_setDrvTmpBufferAddress(UINT32 addr); +extern UINT32 UTL_getDrvTmpBufferAddress(void); + +#if 0 +extern BOOL UTL_canUpdateSecKey(void); +extern BOOL utl_is_sram_fw(UINT32 fw_addr); +extern void utl_test_checksum(UINT32 addr, UINT32 size); +extern void utl_dram_protect_enable(UINT32 addr, UINT32 size); +extern void utl_dram_protect_disable(void); +extern UINT32 utl_dram_protect_check(void); +extern UINT32 utl_dram_get_size(void); + +extern void load_dram_scan(UINT32 addr, UINT32 size) __attribute__ ((section (".dram_text"))); + +extern UINT32 dma_get_capacity(void); +#endif +extern __attribute__((target("thumb"))) void udelay(UINT32 US) __attribute__ ((section (".part1"))); +extern __attribute__((target("thumb"))) void timer0_tm1_init(void) __attribute__ ((section (".part1"))); + +#define timer_getSysTick() ((*(UINT32 volatile *)(REG_TMR010_BASE + 0x10)) / 16) +//@} + +#endif diff --git a/board/novatek/na51068/loader/Include/kprint.h b/board/novatek/na51068/loader/Include/kprint.h new file mode 100755 index 000000000000..4f1aa6653899 --- /dev/null +++ b/board/novatek/na51068/loader/Include/kprint.h @@ -0,0 +1,29 @@ +#ifndef __KPRINT_H__ +#define __KPRINT_H__ + +extern void KPrint(char const *, ...); +extern void putc(const char c); +extern void puts(const char *s); + +/* +#ifndef _VALIST +#define _VALIST +typedef char *va_list; +#endif*/ + +/* + * Storage alignment properties + */ +#define _AUPBND (sizeof(int) - 1) +#define _ADNBND (sizeof(int) - 1) + +/* + * Variable argument list macro definitions + */ +#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd))) +#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND)))) +#define va_end(ap) (void) 0 +#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND)))) + +#endif /* __KPRINT_H__ */ + diff --git a/board/novatek/na51068/loader/Include/libfdt.h b/board/novatek/na51068/loader/Include/libfdt.h new file mode 100755 index 000000000000..9cade83bb638 --- /dev/null +++ b/board/novatek/na51068/loader/Include/libfdt.h @@ -0,0 +1,1578 @@ +#ifndef _LIBFDT_H +#define _LIBFDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "libfdt_env.h" +#include "fdt.h" + +#define FDT_FIRST_SUPPORTED_VERSION 0x10 +#define FDT_LAST_SUPPORTED_VERSION 0x11 + +/* Error codes: informative error codes */ +#define FDT_ERR_NOTFOUND 1 + /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ +#define FDT_ERR_EXISTS 2 + /* FDT_ERR_EXISTS: Attemped to create a node or property which + * already exists */ +#define FDT_ERR_NOSPACE 3 + /* FDT_ERR_NOSPACE: Operation needed to expand the device + * tree, but its buffer did not have sufficient space to + * contain the expanded tree. Use fdt_open_into() to move the + * device tree to a buffer with more space. */ + +/* Error codes: codes for bad parameters */ +#define FDT_ERR_BADOFFSET 4 + /* FDT_ERR_BADOFFSET: Function was passed a structure block + * offset which is out-of-bounds, or which points to an + * unsuitable part of the structure for the operation. */ +#define FDT_ERR_BADPATH 5 + /* FDT_ERR_BADPATH: Function was passed a badly formatted path + * (e.g. missing a leading / for a function which requires an + * absolute path) */ +#define FDT_ERR_BADPHANDLE 6 + /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle + * value. phandle values of 0 and -1 are not permitted. */ +#define FDT_ERR_BADSTATE 7 + /* FDT_ERR_BADSTATE: Function was passed an incomplete device + * tree created by the sequential-write functions, which is + * not sufficiently complete for the requested operation. */ + +/* Error codes: codes for bad device tree blobs */ +#define FDT_ERR_TRUNCATED 8 + /* FDT_ERR_TRUNCATED: Structure block of the given device tree + * ends without an FDT_END tag. */ +#define FDT_ERR_BADMAGIC 9 + /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a + * device tree at all - it is missing the flattened device + * tree magic number. */ +#define FDT_ERR_BADVERSION 10 + /* FDT_ERR_BADVERSION: Given device tree has a version which + * can't be handled by the requested operation. For + * read-write functions, this may mean that fdt_open_into() is + * required to convert the tree to the expected version. */ +#define FDT_ERR_BADSTRUCTURE 11 + /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt + * structure block or other serious error (e.g. misnested + * nodes, or subnodes preceding properties). */ +#define FDT_ERR_BADLAYOUT 12 + /* FDT_ERR_BADLAYOUT: For read-write functions, the given + * device tree has it's sub-blocks in an order that the + * function can't handle (memory reserve map, then structure, + * then strings). Use fdt_open_into() to reorganize the tree + * into a form suitable for the read-write operations. */ + +/* "Can't happen" error indicating a bug in libfdt */ +#define FDT_ERR_INTERNAL 13 + /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. + * Should never be returned, if it is, it indicates a bug in + * libfdt itself. */ + +#define FDT_ERR_MAX 13 + +/**********************************************************************/ +/* Low-level functions (you probably don't need these) */ +/**********************************************************************/ + +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); +static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) +{ + return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); +} + +uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); + +/**********************************************************************/ +/* Traversal functions */ +/**********************************************************************/ + +int fdt_next_node(const void *fdt, int offset, int *depth); + +/** + * fdt_first_subnode() - get offset of first direct subnode + * + * @fdt: FDT blob + * @offset: Offset of node to check + * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + */ +int fdt_first_subnode(const void *fdt, int offset); + +/** + * fdt_next_subnode() - get offset of next direct subnode + * + * After first calling fdt_first_subnode(), call this function repeatedly to + * get direct subnodes of a parent node. + * + * @fdt: FDT blob + * @offset: Offset of previous subnode + * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes + */ +int fdt_next_subnode(const void *fdt, int offset); + +/**********************************************************************/ +/* General functions */ +/**********************************************************************/ + +#define fdt_get_header(fdt, field) \ + (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) +#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) +#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) +#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) +#define fdt_version(fdt) (fdt_get_header(fdt, version)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) + +#define __fdt_set_hdr(name) \ + static inline void fdt_set_##name(void *fdt, uint32_t val) \ + { \ + struct fdt_header *fdth = (struct fdt_header*)fdt; \ + fdth->name = cpu_to_fdt32(val); \ + } +__fdt_set_hdr(magic); +__fdt_set_hdr(totalsize); +__fdt_set_hdr(off_dt_struct); +__fdt_set_hdr(off_dt_strings); +__fdt_set_hdr(off_mem_rsvmap); +__fdt_set_hdr(version); +__fdt_set_hdr(last_comp_version); +__fdt_set_hdr(boot_cpuid_phys); +__fdt_set_hdr(size_dt_strings); +__fdt_set_hdr(size_dt_struct); +#undef __fdt_set_hdr + +/** + * fdt_check_header - sanity check a device tree or possible device tree + * @fdt: pointer to data which might be a flattened device tree + * + * fdt_check_header() checks that the given buffer contains what + * appears to be a flattened device tree with sane information in its + * header. + * + * returns: + * 0, if the buffer appears to contain a valid device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings, as above + */ +int fdt_check_header(const void *fdt); + +/** + * fdt_move - move a device tree around in memory + * @fdt: pointer to the device tree to move + * @buf: pointer to memory where the device is to be moved + * @bufsize: size of the memory space at buf + * + * fdt_move() relocates, if possible, the device tree blob located at + * fdt to the buffer at buf of size bufsize. The buffer may overlap + * with the existing device tree blob at fdt. Therefore, + * fdt_move(fdt, fdt, fdt_totalsize(fdt)) + * should always succeed. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_move(const void *fdt, void *buf, int bufsize); + +/**********************************************************************/ +/* Read-only functions */ +/**********************************************************************/ + +/** + * fdt_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * + * fdt_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds + */ +const char *fdt_string(const void *fdt, int stroffset); + +/** + * fdt_num_mem_rsv - retrieve the number of memory reserve map entries + * @fdt: pointer to the device tree blob + * + * Returns the number of entries in the device tree blob's memory + * reservation map. This does not include the terminating 0,0 entry + * or any other (0,0) entries reserved for expansion. + * + * returns: + * the number of entries + */ +int fdt_num_mem_rsv(const void *fdt); + +/** + * fdt_get_mem_rsv - retrieve one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: pointers to 64-bit variables + * + * On success, *address and *size will contain the address and size of + * the n-th reserve map entry from the device tree blob, in + * native-endian format. + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); + +/** + * fdt_subnode_offset_namelen - find a subnode based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_subnode_offset(), but only examine the first + * namelen characters of name for matching the subnode name. This is + * useful for finding subnodes based on a portion of a larger string, + * such as a full path. + */ +int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, + const char *name, int namelen); +/** + * fdt_subnode_offset - find a subnode of a given node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node at structure block + * offset parentoffset with the given name. name may include a unit + * address, in which case fdt_subnode_offset() will find the subnode + * with that unit address, or the unit address may be omitted, in + * which case fdt_subnode_offset() will find an arbitrary subnode + * whose name excluding unit address matches the given name. + * + * returns: + * structure block offset of the requested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); + +/** + * fdt_path_offset - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * + * fdt_path_offset() finds a node of a given path in the device tree. + * Each path component may omit the unit address portion, but the + * results of this are undefined if any such path component is + * ambiguous (that is if there are multiple nodes at the relevant + * level matching the given component, differentiated only by unit + * address). + * + * returns: + * structure block offset of the node with the requested path (>=0), on success + * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_NOTFOUND, if the requested node does not exist + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_path_offset(const void *fdt, const char *path); + +/** + * fdt_get_name - retrieve the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the starting node + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_name() retrieves the name (including unit address) of the + * device tree node at structure block offset nodeoffset. If lenp is + * non-NULL, the length of this name is also returned, in the integer + * pointed to by lenp. + * + * returns: + * pointer to the node's name, on success + * If lenp is non-NULL, *lenp contains the length of that name (>=0) + * NULL, on error + * if lenp is non-NULL *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); + +/** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** + * fdt_get_property_namelen - find a property based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_get_property_namelen(), but only examine the first + * namelen characters of name for matching the property name. + */ +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int nodeoffset, + const char *name, + int namelen, int *lenp); + +/** + * fdt_get_property - find a given property in a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property() retrieves a pointer to the fdt_property + * structure within the device tree blob corresponding to the property + * named 'name' of the node at offset nodeoffset. If lenp is + * non-NULL, the length of the property value is also returned, in the + * integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, + const char *name, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @ffset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); + +/** + * fdt_getprop_namelen - get property value based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_getprop(), but only examine the first namelen + * characters of name for matching the property name. + */ +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp); + +/** + * fdt_getprop - retrieve the value of a given property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline void *fdt_getprop_w(void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_get_phandle - retrieve the phandle of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the node + * + * fdt_get_phandle() retrieves the phandle of the device tree node at + * structure block offset nodeoffset. + * + * returns: + * the phandle of the node at nodeoffset, on success (!= 0, != -1) + * 0, if the node has no phandle, or another error occurs + */ +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); + +/** + * fdt_get_alias_namelen - get alias based on substring + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * @namelen: number of characters of name to consider + * + * Identical to fdt_get_alias(), but only examine the first namelen + * characters of name for matching the alias name. + */ +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen); + +/** + * fdt_get_alias - retrieve the path referenced by a given alias + * @fdt: pointer to the device tree blob + * @name: name of the alias to look up + * + * fdt_get_alias() retrieves the value of a given alias. That is, the + * value of the property named 'name' in the node /aliases. + * + * returns: + * a pointer to the expansion of the alias named 'name', if it exists + * NULL, if the given alias or the /aliases node does not exist + */ +const char *fdt_get_alias(const void *fdt, const char *name); + +/** + * fdt_get_path - determine the full path of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose path to find + * @buf: character buffer to contain the returned path (will be overwritten) + * @buflen: size of the character buffer at buf + * + * fdt_get_path() computes the full path of the node at offset + * nodeoffset, and records that path in the buffer at buf. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * 0, on success + * buf contains the absolute path of the node at + * nodeoffset, as a NUL-terminated string. + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) + * characters and will not fit in the given buffer. + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); + +/** + * fdt_supernode_atdepth_offset - find a specific ancestor of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * @supernodedepth: depth of the ancestor to find + * @nodedepth: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_supernode_atdepth_offset() finds an ancestor of the given node + * at a specific depth from the root (where the root itself has depth + * 0, its immediate subnodes depth 1 and so forth). So + * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); + * will always return 0, the offset of the root node. If the node at + * nodeoffset has depth D, then: + * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); + * will return nodeoffset itself. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + + * structure block offset of the node at node offset's ancestor + * of depth supernodedepth (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag +* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth); + +/** + * fdt_node_depth - find the depth of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_node_depth() finds the depth of a given node. The root node + * has depth 0, its immediate subnodes depth 1 and so forth. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * depth of the node at nodeoffset (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_depth(const void *fdt, int nodeoffset); + +/** + * fdt_parent_offset - find the parent of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_parent_offset() locates the parent node of a given node (that + * is, it finds the offset of the node which contains the node at + * nodeoffset as a subnode). + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset, *twice*. + * + * returns: + * structure block offset of the parent of the node at nodeoffset + * (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_parent_offset(const void *fdt, int nodeoffset); + +/** + * fdt_node_offset_by_prop_value - find nodes with a given property value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * + * fdt_node_offset_by_prop_value() returns the offset of the first + * node after startoffset, which has a property named propname whose + * value is of length proplen and has value equal to propval; or if + * startoffset is -1, the very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, + * propval, proplen); + * while (offset != -FDT_ERR_NOTFOUND) { + * ... other code here ... + * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, + * propval, proplen); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen); + +/** + * fdt_node_offset_by_phandle - find the node with a given phandle + * @fdt: pointer to the device tree blob + * @phandle: phandle value + * + * fdt_node_offset_by_phandle() returns the offset of the node + * which has the given phandle value. If there is more than one node + * in the tree with the given phandle (an invalid tree), results are + * undefined. + * + * returns: + * structure block offset of the located node (>= 0), on success + * -FDT_ERR_NOTFOUND, no node with that phandle exists + * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); + +/** + * fdt_node_check_compatible: check a node's compatible property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @compatible: string to match against + * + * + * fdt_node_check_compatible() returns 0 if the given node contains a + * 'compatible' property with the given string as one of its elements, + * it returns non-zero otherwise, or on error. + * + * returns: + * 0, if the node has a 'compatible' property listing the given string + * 1, if the node has a 'compatible' property, but it does not list + * the given string + * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property + * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible); + +/** + * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @compatible: 'compatible' string to match against + * + * fdt_node_offset_by_compatible() returns the offset of the first + * node after startoffset, which has a 'compatible' property which + * lists the given compatible string; or if startoffset is -1, the + * very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); + * while (offset != -FDT_ERR_NOTFOUND) { + * ... other code here ... + * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible); + +/** + * fdt_stringlist_contains - check a string list property for a string + * @strlist: Property containing a list of strings to check + * @listlen: Length of property + * @str: String to search for + * + * This is a utility function provided for convenience. The list contains + * one or more strings, each terminated by \0, as is found in a device tree + * "compatible" property. + * + * @return: 1 if the string is found in the list, 0 not found, or invalid list + */ +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); + +/**********************************************************************/ +/* Write-in-place functions */ +/**********************************************************************/ + +/** + * fdt_setprop_inplace - change a property's value, but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * fdt_setprop_inplace() replaces the value of a given property with + * the data in val, of length len. This function cannot change the + * size of a property, and so will only work if len is equal to the + * current length of the property. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if len is not equal to the property's current length + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to replace the property with + * + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_nop_property - replace a property with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_nop_property() will replace a given property's representation + * in the blob with FDT_NOP tags, effectively removing it from the + * tree. + * + * This function will alter only the bytes in the blob which contain + * the property, and will not alter or move any other part of the + * tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_property(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_nop_node - replace a node (subtree) with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_nop_node() will replace a given node's representation in the + * blob, including all its subnodes, if any, with FDT_NOP tags, + * effectively removing it from the tree. + * + * This function will alter only the bytes in the blob which contain + * the node and its properties and subnodes, and will not alter or + * move any other part of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Sequential write functions */ +/**********************************************************************/ + +int fdt_create(void *buf, int bufsize); +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); +int fdt_finish_reservemap(void *fdt); +int fdt_begin_node(void *fdt, const char *name); +int fdt_property(void *fdt, const char *name, const void *val, int len); +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} +#define fdt_property_string(fdt, name, str) \ + fdt_property(fdt, name, str, strlen(str)+1) +int fdt_end_node(void *fdt); +int fdt_finish(void *fdt); + +/**********************************************************************/ +/* Read-write functions */ +/**********************************************************************/ + +int fdt_create_empty_tree(void *buf, int bufsize); +int fdt_open_into(const void *fdt, void *buf, int bufsize); +int fdt_pack(void *fdt); + +/** + * fdt_add_mem_rsv - add one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: 64-bit values (native endian) + * + * Adds a reserve map entry to the given blob reserving a region at + * address address of length size. + * + * This function will insert data into the reserve map and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new reservation entry + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); + +/** + * fdt_del_mem_rsv - remove a memory reserve map entry + * @fdt: pointer to the device tree blob + * @n: entry to remove + * + * fdt_del_mem_rsv() removes the n-th memory reserve map entry from + * the blob. + * + * This function will delete data from the reservation table and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there + * are less than n+1 reserve map entries) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_mem_rsv(void *fdt, int n); + +/** + * fdt_set_name - change the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * @name: name to give the node + * + * fdt_set_name() replaces the name (including unit address, if any) + * of the given node with the given string. NOTE: this function can't + * efficiently check if the new name is unique amongst the given + * node's siblings; results are undefined if this function is invoked + * with a name equal to one of the given node's siblings. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob + * to contain the new name + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_set_name(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_setprop - create or change a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_setprop() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_u32 - set a property to a 32-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) + * + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_setprop_string - set a property to a string value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value for the property + * + * fdt_setprop_string() sets the value of the named property in the + * given node to the given string value (using the length of the + * string to determine the new length of the property), or creates a + * new property with that value if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_string(fdt, nodeoffset, name, str) \ + fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_u32 - append a 32-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_delprop - delete a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_del_property() will delete the given property. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_delprop(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_add_subnode_namelen - creates a new node based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_add_subnode(), but use only the first namelen + * characters of name as the name of the new node. This is useful for + * creating subnodes based on a portion of a larger string, such as a + * full path. + */ +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen); + +/** + * fdt_add_subnode - creates a new node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_add_subnode() creates a new node as a subnode of the node at + * structure block offset parentoffset, with the given name (which + * should include the unit address, if any). + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + + * returns: + * structure block offset of the created nodeequested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * fdt_del_node - delete a node (subtree) + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_del_node() will remove the given node, including all its + * subnodes if any, from the blob. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Debugging / informational functions */ +/**********************************************************************/ + +const char *fdt_strerror(int errval); + +struct fdt_region { + int offset; + int size; +}; + +/** + * fdt_find_regions() - find regions in device tree + * + * Given a list of nodes to include and properties to exclude, find + * the regions of the device tree which describe those included parts. + * + * The intent is to get a list of regions which will be invariant provided + * those parts are invariant. For example, if you request a list of regions + * for all nodes but exclude the property "data", then you will get the + * same region contents regardless of any change to "data" properties. + * + * This function can be used to produce a byte-stream to send to a hashing + * function to verify that critical parts of the FDT have not changed. + * + * Nodes which are given in 'inc' are included in the region list, as + * are the names of the immediate subnodes nodes (but not the properties + * or subnodes of those subnodes). + * + * For eaxample "/" means to include the root node, all root properties + * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter + * ensures that we capture the names of the subnodes. In a hashing situation + * it prevents the root node from changing at all Any change to non-excluded + * properties, names of subnodes or number of subnodes would be detected. + * + * When used with FITs this provides the ability to hash and sign parts of + * the FIT based on different configurations in the FIT. Then it is + * impossible to change anything about that configuration (include images + * attached to the configuration), but it may be possible to add new + * configurations, new images or new signatures within the existing + * framework. + * + * Adding new properties to a device tree may result in the string table + * being extended (if the new property names are different from those + * already added). This function can optionally include a region for + * the string table so that this can be part of the hash too. + * + * The device tree header is not included in the list. + * + * @fdt: Device tree to check + * @inc: List of node paths to included + * @inc_count: Number of node paths in list + * @exc_prop: List of properties names to exclude + * @exc_prop_count: Number of properties in exclude list + * @region: Returns list of regions + * @max_region: Maximum length of region list + * @path: Pointer to a temporary string for the function to use for + * building path names + * @path_len: Length of path, must be large enough to hold the longest + * path in the tree + * @add_string_tab: 1 to add a region for the string table + * @return number of regions in list. If this is >max_regions then the + * region array was exhausted. You should increase max_regions and try + * the call again. + */ +int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, + char * const exc_prop[], int exc_prop_count, + struct fdt_region region[], int max_regions, + char *path, int path_len, int add_string_tab); + +#endif /* _LIBFDT_H */ diff --git a/board/novatek/na51068/loader/Include/libfdt_env.h b/board/novatek/na51068/loader/Include/libfdt_env.h new file mode 100755 index 000000000000..5573b3f8c523 --- /dev/null +++ b/board/novatek/na51068/loader/Include/libfdt_env.h @@ -0,0 +1,63 @@ +/* + * libfdt - Flat Device Tree manipulation (build/run environment adaptation) + * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * Original version written by David Gibson, IBM Corporation. + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef _LIBFDT_ENV_H +#define _LIBFDT_ENV_H + +#include "compiler.h" + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +typedef __u8 uint8_t; +typedef __u16 uint16_t; +typedef __u32 uint32_t; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __u64 uint64_t; +typedef __u64 u_int64_t; +typedef __s64 int64_t; +#endif + +#define __bitwise + +typedef __u16 __bitwise __le16; +typedef __u16 __bitwise __be16; +typedef __u32 __bitwise __le32; +typedef __u32 __bitwise __be32; +#if defined(__GNUC__) +typedef __u64 __bitwise __le64; +typedef __u64 __bitwise __be64; +#endif + +extern struct fdt_header *working_fdt; /* Pointer to the working fdt */ + +typedef __be16 fdt16_t; +typedef __be32 fdt32_t; +typedef __be64 fdt64_t; + +#define fdt32_to_cpu(x) be32_to_cpu(x) +#define cpu_to_fdt32(x) cpu_to_be32(x) +#define fdt64_to_cpu(x) be64_to_cpu(x) +#define cpu_to_fdt64(x) cpu_to_be64(x) + +/* adding a ramdisk needs 0x44 bytes in version 2008.10 */ +#define FDT_RAMDISK_OVERHEAD 0x80 + +#endif /* _LIBFDT_ENV_H */ diff --git a/board/novatek/na51068/loader/Include/libfdt_internal.h b/board/novatek/na51068/loader/Include/libfdt_internal.h new file mode 100755 index 000000000000..4e9e43437786 --- /dev/null +++ b/board/novatek/na51068/loader/Include/libfdt_internal.h @@ -0,0 +1,56 @@ +#ifndef _LIBFDT_INTERNAL_H +#define _LIBFDT_INTERNAL_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause + */ +#include + +#define FDT_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) +#define FDT_TAGALIGN(x) (FDT_ALIGN((x), FDT_TAGSIZE)) + +#define FDT_CHECK_HEADER(fdt) \ + { \ + int err; \ + if ((err = fdt_check_header(fdt)) != 0) \ + return err; \ + } + +int _fdt_check_node_offset(const void *fdt, int offset); +int _fdt_check_prop_offset(const void *fdt, int offset); +const char *_fdt_find_string(const char *strtab, int tabsize, const char *s); +int _fdt_node_end_offset(void *fdt, int nodeoffset); + +static inline const void *_fdt_offset_ptr(const void *fdt, int offset) +{ + return (const char *)fdt + fdt_off_dt_struct(fdt) + offset; + //return (const char *)fdt + fdt_off_dt_struct(fdt) + offset; +} + +static inline void *_fdt_offset_ptr_w(void *fdt, int offset) +{ + //return (void *)(uintptr_t)_fdt_offset_ptr(fdt, offset); + return 0; +} + +static inline const struct fdt_reserve_entry *_fdt_mem_rsv(const void *fdt, int n) +{ + return 0; +#if 0 + const struct fdt_reserve_entry *rsv_table = + (const struct fdt_reserve_entry *) + ((const char *)fdt + fdt_off_mem_rsvmap(fdt)); + + return rsv_table + n; +#endif +} +static inline struct fdt_reserve_entry *_fdt_mem_rsv_w(void *fdt, int n) +{ + //return (void *)(uintptr_t)_fdt_mem_rsv(fdt, n); + return 0; +} + +#define FDT_SW_MAGIC (~FDT_MAGIC) + +#endif /* _LIBFDT_INTERNAL_H */ diff --git a/board/novatek/na51068/loader/Include/loader.h b/board/novatek/na51068/loader/Include/loader.h new file mode 100755 index 000000000000..8fd11b4a3b8c --- /dev/null +++ b/board/novatek/na51068/loader/Include/loader.h @@ -0,0 +1,83 @@ +/** + Global loader header file + + Global loader header file + + @file loader.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef _LOADER_H +#define _LOADER_H + +#include "constant.h" +#include "StorageDef.h" + +/** + @name Special key detect CallBack + + Special key detect Prototype + + Project layer can detect special key in this callback. + If callback returns TRUE, loader will try to find files on SD card. + + @return + - @b TRUE: special key is pressed + - @b FALSE: special key is NOT pressed +*/ +//@{ +typedef BOOL (*LDR_SPECIAL_KEY_CB)(void); +//@} + +/** + @name Card detect CallBack + + Card detect Prototype + + Project layer can detect SD card existence in this callback. + If callback returns TRUE, loader will consider SD is plugged + + @return + - @b TRUE: SD exist + - @b FALSE: SD NOT exist +*/ +//@{ +typedef BOOL (*LDR_CARD_DETECT_CB)(void); +//@} +/** + @name Recovery Trigger CallBack + + Recovery trigger Prototype + + Project layer can detect if the recovery flow should started. + If callback returns TRUE, recovery flow will start. + + @return + - @b TRUE: Recovery flow is triggered. + - @b FALSE: Recovery flow is NOT triggered. +*/ +//@{ +typedef BOOL (*LDR_RECOVERY_TRIGGER_CB)(void); +//@} + +typedef enum _STORAGEINT { + STORAGEINT_UNOKNOWN, + STORAGEINT_SPI_NAND, + STORAGEINT_SPI_NOR, +} STORAGEINT; + +extern void loader_setUpdateFwName(char* fileName); +extern void loader_setUpdateLdrName(char* fileName); +extern void loader_setRunFwName(char* fileName); +extern void loader_setRecoveryFwName(char *fileName); +extern void loader_setRecoveryPartitionID(UINT32 partition_id); +extern void loader_setVersion(UINT32 version); +extern void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj); +//extern void loader_installSpecialKeyCB(LDR_SPECIAL_KEY_CB callback); +//extern void loader_installCardDetectCB(LDR_CARD_DETECT_CB callback); +//extern void loader_installRecoveryTriggerCB(LDR_RECOVERY_TRIGGER_CB callback); + +#endif + + diff --git a/board/novatek/na51068/loader/Include/lz.h b/board/novatek/na51068/loader/Include/lz.h new file mode 100755 index 000000000000..738f1607037d --- /dev/null +++ b/board/novatek/na51068/loader/Include/lz.h @@ -0,0 +1,26 @@ +/** + Decompress library header file + + Decompress library header file + + @file lz.h + @ingroup mISYSUtil + @note Nothing +*/ +#ifndef __NVT_LZ_DEF__ +#define __NVT_LZ_DEF__ + +#include "constant.h" + +/** + @addtogroup mISYSUtil +*/ +//@{ + +extern unsigned int LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize) __attribute__ ((section (".part1"))); +//extern void LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize) __attribute__ ((section (".part1"), far)); +extern int lzma_inflate(UINT8 *in_ptr, UINT32 in_size, UINT8 *out_ptr, UINT32 out_size, UINT8 *p_tmp, UINT32 tmp_size); + +//@} + +#endif diff --git a/board/novatek/na51068/loader/Include/modelext/bin_info.h b/board/novatek/na51068/loader/Include/modelext/bin_info.h new file mode 100755 index 000000000000..a3efa2ca6199 --- /dev/null +++ b/board/novatek/na51068/loader/Include/modelext/bin_info.h @@ -0,0 +1,143 @@ +/** + Bin File Information + + Bin file layout + + ----------------------------------------------------- + HEADINFO 0x00 ~ 0x80 = 128 bytes = 32 WORDS + ----------------------------------------------------- + + EXCEPTION_TABLE: 0x180 ~ 0x200 = 128 bytes = 32 WORDS (see exception_MIPS.s) + + ----------------------------------------------------- + + VECTOR_TABLE: 0x200 ~ 0x2f0 = 240 bytes = 60 WORDS (see isr_MIPS.s) + + ----------------------------------------------------- + + Code Info: 0x2f0 ~ 0x400 = 272 bytes = 68 WORDS (see CodeInfo_MIPS.s) + + ----------------------------------------------------- + + Code Entry: 0x400 (see Loader_MIPS.s) + + : + + PART-1 + PART-2 + PART-3 + : + PART-N + + ----------------------------------------------------- + + @file bin_info.h + @ingroup mMODELEXT + @note THESE STRUCTS ARE VERY VERY IMPORTANT FORMAT DEFINITION OF SYSTEM, + DO NOT MODIFY ANY ITEM OR INSERT/REMOVE ANY ITEM OF THESE STRUCTS!!! + + Copyright Novatek Microelectronics Corp. 2011. All rights reserved. +*/ +#ifndef _BINI_NFO_H +#define _BINI_NFO_H + +#define BIN_INFO_VER 0x19062115 ///< YYYY/MM/DD HH + +#define BIN_INFO_OFFSET_RTOS 0x00000200 ///< uITRON HEADINFO.o attached to this offset +#define BIN_INFO_OFFSET_UBOOT 0x00000300 ///< uboot HEADINFO.o attached to this +#define BIN_INFO_OFFSET_NUTTX 0x00000100 ///< nuttx + +//Ep: Encryption Program (CheckSum version) +//Epcrc: Encryption Program (CRC version) +//Bfc: Bin File Compress +//Ld: Loader +//Fw: Firmware + +//Head control flag for HEADINFO.BinCtrl +#define HDCF_LZCOMPRESS_EN 0x0000001 ///< BIT 0.compressed enable (0=no,1=yes) + +/** + @name Ld control flag for LDINFO.LdCtrl +*/ +//@{ +#define BOOT_FLAG_PARTLOAD_EN 0x0000001 ///< BIT 0.PARTLOAD_EN (0=no,1=yes) +//@} + +//HEADINFO::Resv field definition +typedef enum _HEADINFO_RESV_IDX_{ + HEADINFO_RESV_IDX_FDT_ADDR = 0, + HEADINFO_RESV_IDX_SHM_ADDR = 1, + HEADINFO_RESV_IDX_BOOT_FLAG = 2, + HEADINFO_RESV_IDX_COUNTS = 19, +} HEADINFO_RESV_IDX; + +/** + Header information + + 0x00 ~ 0x80 = 128 bytes = 32 WORDS +*/ +typedef struct HEADINFO { + unsigned int CodeEntry; ///< [0x00] fw CODE entry (4) ----- r by Ld + unsigned int Resv1[HEADINFO_RESV_IDX_COUNTS]; + ///< [0x04~0x50] reserved (4*19) -- reserved, its mem value will filled by Ld + ///< Resv1[HEADINFO_RESV_IDX_FDT_ADDR]: store fdt addr for rtos + ///< Resv1[HEADINFO_RESV_IDX_SHM_ADDR]: store shm addr for rtos + ///< Resv1[HEADINFO_RESV_IDX_BOOT_FLAG]: boot flag for rtos + char BinInfo_1[8]; ///< [0x50~0x58] CHIP-NAME (8) ---- r by Ep + char BinInfo_2[8]; ///< [0x58~0x60] SDK version (8) + char BinInfo_3[8]; ///< [0x60~0x68] SDK releasedate (8) + unsigned int BinLength; ///< [0x68] Bin File Length (4) --- w by Ep/bfc + unsigned int Checksum; ///< [0x6c] Check Sum or CRC (4) ----- w by Ep/Epcrc + unsigned int CRCLenCheck; ///< [0x70~0x74] Length check for CRC (4) ----- w by Epcrc (total len ^ 0xAA55) + unsigned int ModelextAddr;///< [0x74~0x78] where modelext data is. w by Ld / u-boot + unsigned int BinCtrl; ///< [0x78~0x7C] Bin flag (4) --- w by bfc + ///< BIT 0.compressed enable (w by bfc) + ///< BIT 1.Linux SMP enable (1: SMP/VOS, 0: Dual OS) + unsigned int CRCBinaryTag;///< [0x7C~0x80] Binary Tag for CRC (4) ----- w by Epcrc (0xAA55 + "NT") +} +HEADINFO; + +STATIC_ASSERT(sizeof(HEADINFO) == 128); + + +/** + Binary file information + + 0x00 ~ 0x180 = 384 bytes = 96 WORDS +*/ +typedef struct _BININFO { + HEADINFO head; ///< 0x00 ~ 0x80 = 128 bytes = 32 WORDS, header information + unsigned int Resv[64]; ///< 0x80 ~ 0x180 = 384 bytes = 64 WORDS, reserved information +} +BININFO; + +STATIC_ASSERT(sizeof(BININFO) == 384); + +/////////////////////////////////////////////////////////////////////////////// +//Code Info: 0x2f0 ~ 0x400 + +#define ZI_SECTION_OFFSET (0x3f0+0x10) ///< ZI area information of starting offset +#define CODE_SECTION_OFFSET (0x3f0+0x18) ///< code section information of starting offset + +/* +bfc syntex + +bfc.exe p1 p2 p3 p4 p5 p6 p7 p8 p9 + +p1: compress/decompress +p2: compress method +p3: input file name +p4: output file name +p5: partial load flag ('1' means partial load) +p6: partial load file start [locate offset of bin file] +p7: output binary file length [locate offset of bin file] +p8: partial compress flag [locate offset of bin file] +p9: NAND block size (option) + +NOTE: p6~p9 must be hex format (0x****) + +@$(BFC) c lz $(BIN_R) tmp 1 0x310 0x68 0x78 $(EMBMEM_BLK_SIZE) +*/ + +#endif + diff --git a/board/novatek/na51068/loader/Include/modelext/dram_partition_info.h b/board/novatek/na51068/loader/Include/modelext/dram_partition_info.h new file mode 100755 index 000000000000..b1f14a322274 --- /dev/null +++ b/board/novatek/na51068/loader/Include/modelext/dram_partition_info.h @@ -0,0 +1,48 @@ +#ifndef _DRAM_PARTITION_INFO_H +#define _DRAM_PARTITION_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#else +#include "nvt_type.h" +#endif + +/** + DRAM Partition + + This is common header used between firmware of uITRON, eCos, Linux, DSP + so !!!!!! DO NOT modify it !!!!!! +*/ + +#define DRAM_PARTITION_INFO_VER 0x17032309 ///< YYYY/MM/DD HH + +typedef struct _DRAM_PARTITION { + unsigned int fourcc; ///< FourCC DRAM + unsigned int info_size; ///< sizeof(CORE_INFO) + unsigned int dram_addr; ///< whole dram starting address + unsigned int dram_size; ///< whole dram size + unsigned int rev_addr; ///< reversed starting address + unsigned int rev_size; ///< reversed size + unsigned int fdt_addr; ///< ipc starting address + unsigned int fdt_size; ///< ipc size + unsigned int linux_addr;///< linux-kernel starting address + unsigned int linux_size;///< linux-kernel size + unsigned int uboot_addr;///< u-boot starting address + unsigned int uboot_size;///< u-boot size + unsigned int rtos_addr; ///< rtos starting address + unsigned int rtos_size; ///< rtos size + unsigned int dsp1_addr; ///< DSP1 starting address + unsigned int dsp1_size; ///< DSP1 size + unsigned int dsp2_addr; ///< ecos(na51023) / DSP2(na51000) starting address + unsigned int dsp2_size; ///< ecos(na51023) / DSP2(na51000) size + unsigned int loader_addr; ///< loader starting address + unsigned int loader_size; ///< loader size + unsigned int nuttx_addr; ///< nuttx starting address + unsigned int nuttx_size; ///< nuttx size + unsigned int core2_entry1_addr; ///< for smp boot, cpu2 start at 0 then jump to core2_entry2 for addr 0 can be reuse. + unsigned int core2_entry1_size; ///< for smp boot, cpu2 start at 0 then jump to core2_entry2 for addr 0 can be reuse. + unsigned int core2_entry2_addr; ///< asm code to start smp + unsigned int core2_entry2_size; ///< asm code to start smp +}DRAM_PARTITION; + +#endif \ No newline at end of file diff --git a/board/novatek/na51068/loader/Include/modelext/emb_partition_info.h b/board/novatek/na51068/loader/Include/modelext/emb_partition_info.h new file mode 100755 index 000000000000..aa4e1f95c1a6 --- /dev/null +++ b/board/novatek/na51068/loader/Include/modelext/emb_partition_info.h @@ -0,0 +1,55 @@ +#ifndef _EMB_PARTITION_INFO_H +#define _EMB_PARTITION_INFO_H + +#define EMB_PARTITION_INFO_VER 0x16072117 ///< YYYY/MM/DD HH + +/** + Partition Infomation + This is common header used between firmware of uITRON, eCos, Linux, DSP + so !!!!!! DO NOT modify it !!!!!! +*/ + +#define EMB_PARTITION_INFO_COUNT 16 + +#define EMBTYPE_UNKNOWN 0x00 +#define EMBTYPE_LOADER 0x01 /* loader must always put in partition[0] */ +#define EMBTYPE_MODELEXT 0x02 /* modelext must always put in partition[1] */ +#define EMBTYPE_UITRON 0x03 +#define EMBTYPE_ECOS 0x04 +#define EMBTYPE_UBOOT 0x05 +#define EMBTYPE_LINUX 0x06 +#define EMBTYPE_DSP 0x07 +#define EMBTYPE_PSTORE 0x08 +#define EMBTYPE_FAT 0x09 +#define EMBTYPE_EXFAT 0x0A +#define EMBTYPE_ROOTFS 0x0B +#define EMBTYPE_RAMFS 0x0C +#define EMBTYPE_UENV 0x0D /* u-boot environment data */ +#define EMBTYPE_MBR 0x0E /* for emmc partition, mbr always put in partition[0] instead of loader */ +#define EMBTYPE_NUTTX 0x0F +#define EMBTYPE_RTOS 0x10 + +/** + customer defined data partition format +*/ +#define EMBTYPE_USER0 0x80 +#define EMBTYPE_USER1 0x81 +#define EMBTYPE_USER2 0x82 +#define EMBTYPE_USER3 0x83 +#define EMBTYPE_USER4 0x84 +#define EMBTYPE_USER5 0x85 +#define EMBTYPE_USER6 0x86 +#define EMBTYPE_USER7 0x87 + + +/* for reason of compatiable linux, we use original type to decalre */ + +typedef struct _EMB_PARTITION { + unsigned short EmbType; /* EMBTYPE_ */ + unsigned short OrderIdx; /* Order index of the same EmbType based on '0' */ + unsigned long long PartitionOffset; /* Phyical offset of partition */ + unsigned long long PartitionSize; /* Size of this partition */ + unsigned long long ReversedSize; /* Reserved size for bad block */ +} EMB_PARTITION, *PEMB_PARTITION; + +#endif diff --git a/board/novatek/na51068/loader/Include/modelext/modelext_info.h b/board/novatek/na51068/loader/Include/modelext/modelext_info.h new file mode 100755 index 000000000000..a06cbf05e796 --- /dev/null +++ b/board/novatek/na51068/loader/Include/modelext/modelext_info.h @@ -0,0 +1,16 @@ +#ifndef _MODELEXT_INFO_H +#define _MODELEXT_INFO_H + +#define MODELEXT_INFO_VER 0x19071014 ///< YYYY/MM/DD HH + +typedef enum _MODELEXT_TYPE { + MODELEXT_TYPE_DUMMY = 0, + MODELEXT_TYPE_INFO , + MODELEXT_TYPE_BIN_INFO , + MODELEXT_TYPE_EMB_PARTITION, + MODELEXT_TYPE_DRAM_PARTITION, + MODELEXT_TYPE_MAX, +} MODELEXT_TYPE; + + +#endif diff --git a/board/novatek/na51068/loader/Include/modelext/shm_info.h b/board/novatek/na51068/loader/Include/modelext/shm_info.h new file mode 100755 index 000000000000..4ffaeaa3e637 --- /dev/null +++ b/board/novatek/na51068/loader/Include/modelext/shm_info.h @@ -0,0 +1,131 @@ +/** + @file shm_info.h + @ingroup + @note THESE STRUCTS ARE VERY VERY IMPORTANT FORMAT DEFINITION OF SYSTEM, + DO NOT MODIFY ANY ITEM OR INSERT/REMOVE ANY ITEM OF THESE STRUCTS!!! + + Copyright Novatek Microelectronics Corp. 2018. All rights reserved. +*/ +#ifndef __ARCH_COMMON_SHM_INFO_H +#define __ARCH_COMMON_SHM_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#elif defined(_NVT_LINUX_) +#include +#else +#include +#endif + +#define SHM_INFO_VER 0x18060815 ///< YYYY/MM/DD HH + +/** + @name Ld control flag for LDINFO.LdCtrl +*/ +//@{ +#define LDCF_PARTLOAD_EN 0x0000001 ///< BIT 0.PARTLOAD_EN (0=no,1=yes) +//@} + +/** + @name Ld control flag for LDINFO.LdCtrl2 +*/ +//@{ +#define LDCF_UPDATE_FW 0x0000001 ///< BIT 0.UPDATE_FW (0=no,1=yes) +#define LDCF_UPDATE_LD 0x0000002 ///< BIT 1.UPDATE_LD (0=no,1=yes) +#define LDCF_BOOT_CARD 0x0000004 ///< BIT 2.BOOT_CARD (0=no,1=yes) +#define LDCF_BOOT_FLASH 0x0000008 ///< BIT 3.BOOT_FLASH (0=no,1=yes) +#define LDCF_UPDATE_CAL 0x0000010 ///< BIT 4.UPDATE_CAL (0=no,1=yes) +#define LDCF_UPDATE_FW_DONE 0x0000100 ///< BIT 8.UPDATE_FW_DONE (0=no,1=yes) +#define LDCF_S3_BOOT 0x0000200 ///< BIT 9.BOOT FROM S3 STATE (0=no,1=yes) +//@} + +/** + Loader information + + MUST 28 WORDS +*/ +typedef struct _BOOTINFO { + char LdInfo_1[16]; ///< LD-NAME(16) ------ w by Ld + UINT32 LdCtrl; ///< Fw flag (4) ----------- r by Ld + ///< BIT 0.enable part-load (0=full load,1=part load) + UINT32 LdCtrl2; ///< Ld flag (4) ----------- w by Ld + ///< BIT 0.UPDATE_FW (0=no,1=yes) + ///< BIT 1.UPDATE_LOADER (0=no,1=yes) + ///< BIT 2.BOOT_CARD (0=no,1=yes) + ///< BIT 3.BOOT_FLASH (0=no,1=yes) + ///< BIT 4.UPDATE_CAL (0=no,1=yes) + ///< BIT 8.UPDATE_FW_DONE (0=no,1=yes) + //< BIT 9.BOOT FROM S3 STATE (0=no,1=yes) + UINT32 LdLoadSize; ///< Ld load size (4) ------ w by Ld (NOTE: this value must be block size align) + UINT32 LdLoadTime; ///< Ld exec time(us) (4) -- w by Ld + UINT32 LdResvSize; ///< Ld size (by bytes, reserved size in partition) (4) ------ w by Ld + UINT32 FWResvSize; ///< FW reserved size (4) ------ w by Ld + UINT16 LdPackage; ///< IC package expected by Ld (0xFF: ES, 0: 660, 3: 663, 5: 665, etc...) + UINT16 LdStorage; ///< Internal storage expected by Ld (0: unkown, 1: nand, 2: spi nand, 3: spi nor) + UINT32 fdt_addr; + UINT32 Resv[16]; ///< (4*5) ------------ reserved for project Ld +} BOOTINFO; + +STATIC_ASSERT(sizeof(BOOTINFO) == 112); + +/** + communication information + + MUST 54 WORDS +*/ +//BOOT_REASON +#define BOOT_REASON_NORMAL 0 // normal or from sd +#define BOOT_REASON_FWUPDFW 1 // Firmware update Firmware +#define BOOT_REASON_FROM_USB 2 // Update from USB +#define BOOT_REASON_FROM_ETH 3 // Update from ethernet +#define BOOT_REASON_FORMAT_ROOTFS 4 // Format rootfs because rootfs broken is detected +#define BOOT_REASON_RECOVERY_SYS 5 // System recovery from eMMC +#define BOOT_REASON_FROM_UART 6 // Update from uart + +//COMMINFO::Resv field definition +typedef enum _COMM_RESV_IDX_{ + COMM_RESV_IDX_BOOT_REASON = 0, + COMM_RESV_IDX_CORE1_START = 1, + COMM_RESV_IDX_CORE2_START = 2, + COMM_RESV_IDX_UITRON_COMP_ADDR = 3, + COMM_RESV_IDX_UITRON_COMP_LEN = 4, + COMM_RESV_IDX_FW_UPD_ADDR = 5, + COMM_RESV_IDX_FW_UPD_LEN = 6, + COMM_RESV_IDX_OTA_NAME_ADDR = 7, + COMM_RESV_IDX_S3_APB_ADDR = 8, + COMM_RESV_IDX_S3_APB_LEN = 9, +} COMM_RESV_IDX; + +typedef struct _COMMINFO { + char CommInfo_1[16];///< COMMINFO (16) + UINT32 Resv[45];///< reversed data for communication between loader, uboot, uitron, linux + // Resv[0]: COMM_RESV_IDX_BOOT_REASON, + // BYTE[0]: BOOT_REASON: use #define COMM_BOOT_REASON_ + // BYTE[1]: BOOT_DONE: 0:Not yet, 1:Done 2:NG + // BYTE[2]: DSP_DONE: 0:Not yet, 1:Done 2:NG + // Resv[1]: COMM_CORE1_START (used on uboot trigger loader to start uitron) + // Resv[2]: COMM_CORE2_START (used on uitron trigger linux resume) + // Resv[3]: COMM_UITRON_COMP_ADDR + // Resv[4]: COMM_UITRON_COMP_LEN + // Resv[5]: COMM_FW_UPD_ADDR + // Resv[6]: COMM_FW_UPD_LEN + // Resv[7]: COMM_OTA_NAME_ADDR : OTA name + // Resv[8]: COMM_S3_APB_ADDR : S3-resume's apb register info addr + // Resv[9]: COMM_S3_APB_LEN : S3-resume's apb register info len + UINT32 UserDef[5]; ///< can be used for customer +} COMMINFO; + +STATIC_ASSERT(sizeof(COMMINFO) == 216); + +/** + Binary file information + + MUST 82 WORDS +*/ +typedef struct _SHMINFO { + BOOTINFO boot; + COMMINFO comm; +} SHMINFO; + +STATIC_ASSERT(sizeof(SHMINFO) == 328); +#endif /* __ARCH_COMMON_SHM_INFO_H */ diff --git a/board/novatek/na51068/loader/Include/nvt_crypto.h b/board/novatek/na51068/loader/Include/nvt_crypto.h new file mode 100755 index 000000000000..fed9c24fb035 --- /dev/null +++ b/board/novatek/na51068/loader/Include/nvt_crypto.h @@ -0,0 +1,50 @@ +#ifndef _NVT_CRYPTO_H_ +#define _NVT_CRYPTO_H_ + +#define NVT_CRYPTO_AES_BLOCK_SIZE 16 ///< bytes +#define NVT_CRYPTO_AES_128_KEY_SIZE 16 ///< bytes +#define NVT_CRYPTO_AES_256_KEY_SIZE 32 ///< bytes + +typedef enum { + NVT_CRYPTO_MODE_DES = 0, ///< Block Size => 64 bits, Key Size => 64 bits, Single Block Cipher + NVT_CRYPTO_MODE_3DES, ///< Block Size => 64 bits, Key Size => 192 bits, Single Block Cipher + NVT_CRYPTO_MODE_AES_128, ///< Block Size => 128 bits, Key Size => 128 bits, Single Block Cipher + NVT_CRYPTO_MODE_AES_256, ///< Block Size => 128 bits, Key Size => 256 bits, Single Block Cipher + NVT_CRYPTO_MODE_MAX +} NVT_CRYPTO_MODE_T; + +typedef enum { + NVT_CRYPTO_OPMODE_ECB = 0, ///< ECB mode + NVT_CRYPTO_OPMODE_CBC, ///< CBC mode, need IV + NVT_CRYPTO_OPMODE_MAX +} NVT_CRYPTO_OPMODE_T; + +typedef enum { + NVT_CRYPTO_KEY_SRC_EFUSE = 0, ///< key from efuse + NVT_CRYPTO_KEY_SRC_DATA, ///< key from user key data + NVT_CRYPTO_KEY_SRC_MAX +} NVT_CRYPTO_KEY_SRC_T; + +struct nvt_crypto_pio_t { + u32 encrypt; ///< 0:decrypt 1:encrypt + NVT_CRYPTO_OPMODE_T opmode; ///< 0:ecb 1:cbc + u8 *src; ///< input data buffer + u8 *dst; ///< output data buffer + u8 *key; ///< key data buffer, key => NULL means from efuse secure boot key + u8 *iv; ///< initial vector data buffer + NVT_CRYPTO_KEY_SRC_T key_src; ///< key from efuse or key buffer, 0:from efuse 1:frome key buffer + u32 key_ofs; ///< key offset from efuse, word(4bytes) unit, used if key source from efuse + u32 src_size; ///< input data buffer length, bytes + u32 dst_size; ///< output data buffer length, bytes + u32 key_size; ///< key data buffer length, bytes, 16=>AES-128, 32=>AES-256 + u32 iv_size; ///< initial vector data buffer length, bytes +}; + +/************************************************************************************* + * Public Function Prototype + *************************************************************************************/ +void nvt_crypto_close(void); +int nvt_crypto_open(void); +int nvt_crypto_pio_aes(struct nvt_crypto_pio_t *p_crypto); + +#endif /* _NVT_CRYPTO_H_ */ diff --git a/board/novatek/na51068/loader/Include/nvt_hash.h b/board/novatek/na51068/loader/Include/nvt_hash.h new file mode 100755 index 000000000000..c7324ad1ef48 --- /dev/null +++ b/board/novatek/na51068/loader/Include/nvt_hash.h @@ -0,0 +1,30 @@ +#ifndef _NVT_HASH_H_ +#define _NVT_HASH_H_ + +typedef enum { + NVT_HASH_MODE_SHA1 = 0, ///< block size=> 64 bytes, digest size 20 bytes + NVT_HASH_MODE_SHA256, ///< block size=> 64 bytes, digest size 32 bytes + NVT_HASH_MODE_MAX +} NVT_HASH_MODE_T; + +#define NVT_HASH_SHA1_DIGEST_SIZE 20 +#define NVT_HASH_SHA1_BLOCK_SIZE 64 +#define NVT_HASH_SHA256_DIGEST_SIZE 32 +#define NVT_HASH_SHA256_BLOCK_SIZE 64 + +struct nvt_hash_pio_t { + u32 mode; ///< hash mode + u8 *src; ///< input data buffer + u8 *digest; ///< digest data buffer + u32 src_size; ///< input data buffer length + u32 digest_size; ///< digest data buffer length +}; + +/************************************************************************************* + * Public Function Prototype + *************************************************************************************/ +void nvt_hash_close(void); +int nvt_hash_open(void); +int nvt_hash_pio_sha(struct nvt_hash_pio_t *p_hash); + +#endif /* _NVT_HASH_H_ */ diff --git a/board/novatek/na51068/loader/Include/nvt_rdata_sys.h b/board/novatek/na51068/loader/Include/nvt_rdata_sys.h new file mode 100755 index 000000000000..676e734089a9 --- /dev/null +++ b/board/novatek/na51068/loader/Include/nvt_rdata_sys.h @@ -0,0 +1,49 @@ +#ifndef __SYSTEM_H__ +#define __SYSTEM_H__ + +typedef enum { + SYS_SECURE_MODE = 0, + SYS_SECURE_INVISIBLE, + SYS_SECURE_BOOT_EN, + SYS_CHIP_UNIQE_ID, + SYS_HDMI0_PHY_TRIM, + SYS_THREMAL_SENSOR_PHY_TRIM, + SYS_CHIP_PACKAGE_ID, + SYS_CHIP_CUSTOMER_ID, + SYS_CHIP_VER, + SYS_CHIP_DIE_ID, + SYS_CORE_POWER_CTRL, /* 10 */ + SYS_EFUSE_READ_ONLY, + SYS_VDAC_R, + SYS_VDAC_G, + SYS_VDAC_B, + SYS_VDAC_CVBS, + SYS_DDR_PHY_32BIT_PLEG, + SYS_DDR_PHY_32BIT_NLEG, + SYS_DDR_PHY_16BIT_PLEG, + SYS_DDR_PHY_16BIT_NLEG, /* 19 */ + SYS_MAX_DATA_ID = SYS_DDR_PHY_16BIT_NLEG + } PUBLIC_SYS_DATA; + +enum CHIP_VER { + VERSION_UNKNOW = 0, + VERSION_A, + VERSION_B, + VERSION_C, + VERSION_D, + VERSION_E, + VERSION_F, + VERSION_G +}; + +enum CHIP_PACKAGE { + CHIP_UNKNOW = 0, + NT98310, + NT98311, + NT98312, + NT98313, + NT98314, + NT98315, + NT98316 +}; +#endif diff --git a/board/novatek/na51068/loader/Include/nvt_rsa.h b/board/novatek/na51068/loader/Include/nvt_rsa.h new file mode 100755 index 000000000000..1dc342a25443 --- /dev/null +++ b/board/novatek/na51068/loader/Include/nvt_rsa.h @@ -0,0 +1,49 @@ +#ifndef _NVT_RSA_H_ +#define _NVT_RSA_H_ + +typedef enum { + NVT_RSA_MODE_NORMAL = 0, ///< normal mode, encryption or decryption + NVT_RSA_MODE_MAX +} NVT_RSA_MODE_T; + +typedef enum { + NVT_RSA_KEY_WIDTH_256 = 0, ///< key width 256 bits + NVT_RSA_KEY_WIDTH_512, ///< key width 512 bits + NVT_RSA_KEY_WIDTH_1024, ///< key width 1024 bits + NVT_RSA_KEY_WIDTH_2048, ///< key width 2048 bits + NVT_RSA_KEY_WIDTH_4096, ///< key width 4096 bits + NVT_RSA_KEY_WIDTH_MAX +} NVT_RSA_KEY_WIDTH_T; + +#define NVT_RSA_256_KEY_SIZE 32 ///< bytes +#define NVT_RSA_512_KEY_SIZE 64 ///< bytes +#define NVT_RSA_1024_KEY_SIZE 128 ///< bytes +#define NVT_RSA_2048_KEY_SIZE 256 ///< bytes +#define NVT_RSA_4096_KEY_SIZE 512 ///< bytes + +#define NVT_RSA_256_OUT_SIZE NVT_RSA_256_KEY_SIZE ///< bytes +#define NVT_RSA_512_OUT_SIZE NVT_RSA_512_KEY_SIZE ///< bytes +#define NVT_RSA_1024_OUT_SIZE NVT_RSA_1024_KEY_SIZE ///< bytes +#define NVT_RSA_2048_OUT_SIZE NVT_RSA_2048_KEY_SIZE ///< bytes +#define NVT_RSA_4096_OUT_SIZE NVT_RSA_4096_KEY_SIZE ///< bytes + +struct nvt_rsa_pio_t { + NVT_RSA_KEY_WIDTH_T key_w; ///< key width + u8 *src; ///< input data buffer + u8 *dst; ///< output data buffer + u8 *key_n; ///< key_n data buffer + u8 *key_ed; ///< key_ed data buffer, (N, e) as public key, (N, d) as private key + u32 src_size; ///< input data buffer length + u32 dst_size; ///< output data buffer length + u32 key_n_size; ///< key_n data buffer length + u32 key_ed_size; ///< key_ed data buffer length +}; + +/************************************************************************************* + * Public Function Prototype + *************************************************************************************/ +void nvt_rsa_close(void); +int nvt_rsa_open(void); +int nvt_rsa_pio_normal(struct nvt_rsa_pio_t *p_rsa); + +#endif /* _NVT_RSA_H_ */ diff --git a/board/novatek/na51068/loader/Include/nvtpack/nvtpack.h b/board/novatek/na51068/loader/Include/nvtpack/nvtpack.h new file mode 100755 index 000000000000..ab5ef6f289ea --- /dev/null +++ b/board/novatek/na51068/loader/Include/nvtpack/nvtpack.h @@ -0,0 +1,195 @@ +#ifndef _NVTPACK_H +#define _NVTPACK_H + +#define CHECKSUM_EN 0 + +#define NVTPACK_CHKSUM_HDR_VERSION 0x16040719U +#define NVTPACK_FW_HDR2_VERSION 0x16071515U + +typedef enum _NVTPACK_ER { + NVTPACK_ER_SUCCESS = 0, + NVTPACK_ER_FAILED = -1, + NVTPACK_ER_UNKNOWN_FORMAT = -2, + NVTPACK_ER_CHECK_SUM = -3, + NVTPACK_ER_NOT_FOUND = -4, + NVTPACK_ER_USER_BREAK = -5, + NVTPACK_ER_PARAM = -6, + NVTPACK_ER_MEM_NOT_ENOUGH = -7, + NVTPACK_ER_UITRON_SIZE_ALIGN4 = -8, ///< uITRON size must align by 4 + NVTPACK_ER_INVALID_WHOLE_SIZE = -9, ///< after nvtpack, whole size must align by 4 + NVTPACK_ER_SRC_NAME_BLANK = -10, ///< resource's SrcName cannot be NULL or blank + NVTPACK_ER_SRC_NAME_EXCEED = -11, ///< resource's SrcName cannot exceed 12 bytes + NVTPACK_ER_SRC_NAME_INVALID = -12, ///< resource's SrcName include invalid character + NVTPACK_ER_SRC_NAME_ALIKE = -13, ///< there resource's SrcName are alike. +} NVTPACK_ER; + +typedef enum _NVTPACK_VER { + NVTPACK_VER_UNKNOWN, ///< UNKNOWN + NVTPACK_VER_13012816, ///< NT9666X, NT9850X + NVTPACK_VER_16072017, ///< NT9668X +} NVTPACK_VER; + +#if !defined(_WIN32) +typedef struct _GUID { + unsigned int Data1; + unsigned short Data2; + unsigned short Data3; + unsigned char Data4[8]; +} GUID; +#endif + +typedef struct _NVTPACK_RES_HDR { + GUID guid; ///< {B5CB64AE-05DD-46FA-B906-0C62D22958D6} + unsigned int TotalSize; + unsigned int CheckSum; + unsigned int ContentSize; + char SrcName[16]; ///< original packed bin file name + char DstName[16]; ///< target file name +} NVTPACK_RES_HDR; + +typedef struct _NVTPACK_FW_HDR { + GUID guid; ///< {8827BE90-36CD-4FC2-A987-73A8484E84B1} + unsigned int TotalSize; ///< sizeof(NVTPACK_FW_HDR) + n*sizeof(NVTPACK_PARTITION_HDR) + unsigned int CheckSum; ///< check sum of sizeof(NVTPACK_FW_HDR) + n*sizeof(NVTPACK_PARTITION_HDR) + unsigned int TotalRes; ///< total partitions +} NVTPACK_FW_HDR; + +typedef struct _NVTPACK_FW_HDR2 { + GUID guid; ///< {D6012E07-10BC-4F91-B28A-352F82261A50} + unsigned int uiVersion; ///< NVTPACK_FW_HDR2_VERSION + unsigned int uiHdrSize; ///< sizeof(NVTPACK_FW_HDR2); + unsigned int TotalRes; ///< total resource counts + unsigned int TotalSize; ///< whole bin size + unsigned int uiChkMethod; ///< 0: CheckSum + unsigned int uiChkValue; ///< check sum value or crc value within NVTPACK_FW_HDR2 + unsigned int uiUserData[4]; ///< user defined data that may be used in future + unsigned int uiReversed[18];///< align to 128 bytes +} NVTPACK_FW_HDR2; + +typedef struct _NVTPACK_PARTITION_HDR { + unsigned int Offset; + unsigned int Size; + unsigned int PartitionID; +} NVTPACK_PARTITION_HDR; + +typedef struct _NVTPACK_CHKSUM_HDR { + unsigned int uiFourCC ; ///< 'C','K','S','M' + unsigned int uiVersion; ///< NVTPACK_CHKSUM_HDR header version + unsigned int uiChkMethod; ///< 0: CheckSum + unsigned int uiChkValue; ///< check sum value or crc value within NVTPACK_CHKSUM_HDR + unsigned int uiDataOffset; ///< real data starting offset without NVTPACK_CHKSUM_HDR + unsigned int uiDataSize; ///< real data size without NVTPACK_CHKSUM_HDR + unsigned int uiPaddingSize; ///< padding bytes for check sum + unsigned int uiEmbType; ///< relate to EMBTYPE_????? + unsigned int uiReversed[8]; ///< align to 64 bytes +} NVTPACK_CHKSUM_HDR; + +typedef struct _NVTPACK_BFC_HDR { + unsigned int uiFourCC; ///< FourCC = BCL1 + unsigned int uiAlgorithm; ///< algorithm always is 9 + unsigned int uiSizeUnComp;///< big endian uncompressed size + unsigned int uiSizeComp; ///< big endian compressed size +} NVTPACK_BFC_HDR; + +typedef struct _NVTPACK_BININFO_HDR { + unsigned int CodeEntry; ///< [0x00] fw CODE entry (4) ----- r by Ld + unsigned int Resv1[19]; ///< [0x04~0x50] reserved (4*19) -- reserved, its mem value will filled by Ld + char BinInfo_1[8]; ///< [0x50~0x58] CHIP-NAME (8) ---- r by Ep + char BinInfo_2[8]; ///< [0x58~0x60] SDK version (8) + char BinInfo_3[8]; ///< [0x60~0x68] SDK release-date (8) + unsigned int BinLength; ///< [0x68] Bin File Length (4) --- w by Ep/bfc + unsigned int Checksum; ///< [0x6c] Check Sum or CRC (4) ----- w by Ep/Epcrc + unsigned int CRCLenCheck; ///< [0x70~0x74] Length check for CRC (4) ----- w by Epcrc (total len ^ 0xAA55) + unsigned int Resv2; ///< [0x74~0x78] reserved (4) --- reserved for other bin tools + unsigned int BinCtrl; ///< [0x78~0x7C] Bin flag (4) --- w by bfc + ///< BIT 0.compressed enable (w by bfc) + unsigned int CRCBinaryTag; ///< [0x7C~0x80] Binary Tag for CRC (4) ----- w by Epcrc (0xAA55 + "NT") +} NVTPACK_BININFO_HDR; + +typedef struct _NVTPACK_MEM { + void *p_data; + unsigned int len; +} NVTPACK_MEM; + +typedef struct _NVTPACK_VERIFY_OUTPUT { + NVTPACK_VER ver; ///< indicate package type + unsigned int partition_cnt; ///< total partition counts +} NVTPACK_VERIFY_OUTPUT; + +typedef struct _NVTPACK_GET_PARTITION_INPUT { + unsigned int id; + NVTPACK_MEM mem; +} NVTPACK_GET_PARTITION_INPUT; + +typedef struct _NVTPACK_GET_RESOURCE_INPUT { + const char *filename; + NVTPACK_MEM mem; +} NVTPACK_GET_RESOURCE_INPUT; + +typedef struct _NVTPACK_ENUM_PARTITION_INPUT { + NVTPACK_MEM mem; + void *p_user_data; ///< [Optional] e.g. if use c class, you can pass that class point to your static callback. + int (*fp_enum)(unsigned int id, NVTPACK_MEM *p_mem, void *p_user_data); +} NVTPACK_ENUM_PARTITION_INPUT; + +typedef struct _NVTPACK_ENUM_RESOURCE_INPUT { + NVTPACK_MEM mem; + void *p_user_data; ///< [Optional] e.g. if use c class, you can pass that class point to your static callback. + int (*fp_enum)(NVTPACK_RES_HDR *p_hdr, NVTPACK_MEM *p_mem, void *p_user_data); +} NVTPACK_ENUM_RESOURCE_INPUT; + +typedef struct _NVTPACK_PARTITION_ITEM { + unsigned int id; + NVTPACK_MEM mem; +} NVTPACK_PARTITION_ITEM; + +typedef struct _NVTPACK_MAKE_PARTITION_INPUT { + NVTPACK_VER ver; ///< package version + NVTPACK_PARTITION_ITEM *p_list; ///< data list + int num; ///< data counts + NVTPACK_MEM mem_work; ///< working buffer +} NVTPACK_MAKE_PARTITION_INPUT; + +typedef struct _NVTPACK_RESOURCE_ITEM { + char SrcName[16]; ///< original name + char DstName[16]; ///< target file name + NVTPACK_MEM mem; +} NVTPACK_RESOURCE_ITEM; + +typedef struct _NVTPACK_MAKE_RESOURCE_INPUT { + NVTPACK_RESOURCE_ITEM *p_list; + int num; + NVTPACK_MEM mem_work; +} NVTPACK_MAKE_RESOURCE_INPUT; + +#ifndef IsEqualGUID +#define IsEqualGUID(rguid1, rguid2) (!memcmp(rguid1, rguid2, sizeof(GUID))) +#endif + +#ifndef MAKEFOURCC +#define MAKEFOURCC(ch0, ch1, ch2, ch3) ((unsigned int)(unsigned char)(ch0) | ((unsigned int)(unsigned char)(ch1) << 8) | ((unsigned int)(unsigned char)(ch2) << 16) | ((unsigned int)(unsigned char)(ch3) << 24 )) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +extern unsigned int nvtpack_calc_nvt_sum(NVTPACK_MEM *p_mem); +extern NVTPACK_ER nvtpack_getver(NVTPACK_MEM *p_mem, NVTPACK_VER *p_ver); +extern NVTPACK_ER nvtpack_verify(NVTPACK_MEM *p_mem, NVTPACK_VERIFY_OUTPUT *p_output); +extern NVTPACK_ER nvtpack_get_partition(NVTPACK_GET_PARTITION_INPUT *p_input, NVTPACK_MEM *p_out); +extern NVTPACK_ER nvtpack_enum_partition(NVTPACK_ENUM_PARTITION_INPUT *p_input); +//NVTPACK_VER_13012816: need sizeof(NVTPACK_FW_HDR) +n*(sizeof(NVTPACK_PARTITION_HDR) + 4) + whole_data_size +//NVTPACK_VER_16072017: need sizeof(NVTPACK_FW_HDR2) +n*(sizeof(NVTPACK_PARTITION_HDR) + 4) + whole_data_size +extern NVTPACK_ER nvtpack_make_parition_pkg(NVTPACK_MAKE_PARTITION_INPUT *p_input, NVTPACK_MEM *p_out); + +extern NVTPACK_ER nvtpack_get_resource(NVTPACK_GET_RESOURCE_INPUT *p_input, NVTPACK_MEM *p_out); +extern NVTPACK_ER nvtpack_enum_resource(NVTPACK_ENUM_RESOURCE_INPUT *p_input); +//buf need n*(sizeof(NVTPACK_RES_HDR)+32)+ whole_data_size +extern NVTPACK_ER nvtpack_make_resource_pkg(NVTPACK_MAKE_RESOURCE_INPUT *p_input, NVTPACK_MEM *p_out); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/novatek/na51068/loader/Include/scsi_op.h b/board/novatek/na51068/loader/Include/scsi_op.h new file mode 100755 index 000000000000..bda03aa4f419 --- /dev/null +++ b/board/novatek/na51068/loader/Include/scsi_op.h @@ -0,0 +1,205 @@ +#ifndef _SCSI_OP_H +#define _SCSI_OP_H + +/** +Only Support MSDC Vendor command code 0xF0/0xE0/0xC0. +Others vendor code would STALL OUT EP. Sense data would return illegal request sense code. +*/ +#define SCSI_OP_SET0 0xF0 +#define SCSI_OP_SET1 0xE0 +#define SCSI_OP_SET2 0xC0 + + +/////////////////////////////////////////////////////////////////////////////// +// Uart's return status: CDB[13] +// Uart's extra data len: CDB[6] ~ CDB[9] except SCSIOP_OUT_ADDR_WRITE +// Checksum rule: The CDB[0] ~ CDB[15]'s sum LSB 8bits shall be 0x00 +// Checksum is fixed CDB[14] ~ CDB[15] +// When Checksum failed. CSW Status 0x1 means command failed. +/////////////////////////////////////////////////////////////////////////////// +#define IDX_CDB_UART_DATA_LEN_LWLB 6 ///< uart's data len low word low byte +#define IDX_CDB_UART_DATA_LEN_LWHB 7 ///< uart's data len low word high byte +#define IDX_CDB_UART_DATA_LEN_HWLB 8 ///< uart's data len high word low byte +#define IDX_CDB_UART_DATA_LEN_HWHB 9 ///< uart's data len high word low byte +#define IDX_CDB_UART_STATUS_ER 13 ///< uart's csw status +#define IDX_CDB_CHKSUM_LB 14 ///< check sum low bytes +#define IDX_CDB_CHKSUM_HB 15 ///< check sum high bytes + +/////////////////////////////////////////////////////////////////////////////// +// SCSI CBW +/////////////////////////////////////////////////////////////////////////////// +typedef struct _NVT_SCSI_CBW { + unsigned int dCBWSignature; + unsigned int dCBWTag; + unsigned int dCBWDataTransferLength; + unsigned char bmCBWFlags; + unsigned char bCBWLUN; + unsigned char bCBWCBLength; + unsigned char CBWCB[16]; +} NVT_SCSI_CBW; + +/** +Open NVT Device + +The commands except SCSIOP_IN_IS_NVT can be run if open device success. +If not open first, the operation commands got CSW Status 0x1 means command failed. + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_OPEN_DEVICE 0x01 + + +/** +Send Write Loader + +The Write Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_WRLOADER 0x02 + +/** +Address WRITE WORD (DRAM/REG/SRAM dont care) + +The Write Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +The Write DATA @ CDB[6]~[9]. +For example address 0x12345678 shall fill CDB[6]=0x78 CDB[7]=0x56 CDB[8]=0x34 CDB[9]=0x12 +CDB[10]~[15] shall follow checksum rule. Content is dont care. + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_ADDR_WRITE 0x03 + +/** +Write Memory + +The Write Starting Address @ CDB[2]~[5]; +For example offset 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_MEM_WRITE 0x04 + +/** +Read / Write flash + +send SCSIOP_FLASH_OP to loader +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. except CDB[10] +UART: CDB[6]~[9] is SCSIOP_FLASH_OP size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define FLASH_ACCESS_TYPE_AUTO 0 +#define FLASH_ACCESS_TYPE_NAND 1 +#define FLASH_ACCESS_TYPE_NOR 2 +#define FLASH_ACCESS_TYPE_EMMC 3 +typedef struct _SCSIOP_FLASH_OP { + unsigned int type; //FLASH_ACCESS_TYPE + unsigned int is_write; //indicate write + unsigned long long offset; //flash r/w offset + unsigned long long size; //flash r/w size + unsigned long long partition_size; //flash partition size +} SCSIOP_FLASH_OP; +#define SCSIOP_OUT_FLASH_ACCESS 0x05 + + +/** +Ask if NVT Device + +No need to SCSIOP_IN_OPEN_DEVICE +CDB[2]~[15] shall follow checksum rule + +@DATA_PHASE: IN 4 bytes return; The value 0x81200000 woule be return for 98321. <8321 = 0x2081> If checksum fail, the 0x0 would be returned. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. + +*/ +#define SCSIOP_IN_IS_NVT 0x81 + + +/** +End USB ROM CODE. + +Exit USB ROM code after receiving this command. The checksum must be correct. +After SCSIOP_IN_WRLOADER is invoked, PC invoked this to confirm write loader is ok. + +CDB[2]~[15] shall follow checksum rule + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success and end usb rom. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_WAIT_DONE 0x82 + + +/** +Address READ WORD (DRAM/REG/SRAM dont care) + +The READ Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +CDB[6]~[15] shall follow checksum rule. Content is dont care. + +@DATA_PHASE: IN 8 bytes return. DATA[0]~[3] is repeat CDB address. Read out DATA is [4] ~[7]. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_ADDR_READ 0x83 + + +/** +The Read Starting Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +CDB[6]~[9] is read data size +CDB[10]~[15] shall follow checksum rule. Content is dont care. + +@DATA_PHASE: IN 8 bytes return. DATA[0]~[3] is repeat CDB address. Read out DATA is [3] ~[7]. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. + +*/ +#define SCSIOP_IN_MEM_READ 0x84 + + +/** +Get Temp Buffer Address + +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: Read out DATA is [3] ~[7]. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_GET_TMP_ADDR 0x85 + +/** +Notify fdt has send + +The fdt has sent into loader's temp buffer. notify loader to check its sanity. +CDB[2]~[5] is status result in word. +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_FDT 0x86 + + +/** +Notify uboot or nvtpack has send + +The uboot or nvtpack has sent into loader's temp buffer. notify loader to check its sanity. +CDB[2]~[5] is status result in word. +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) +*/ +#define SCSIOP_IN_UBOOT 0x87 + +#endif \ No newline at end of file diff --git a/board/novatek/na51068/loader/Include/sdhci.h b/board/novatek/na51068/loader/Include/sdhci.h new file mode 100755 index 000000000000..c14d3af67e51 --- /dev/null +++ b/board/novatek/na51068/loader/Include/sdhci.h @@ -0,0 +1,218 @@ +#ifndef __SDHCI_H__ +#define __SDHCI_H__ + +#define SDHCI_SPEC_300 2 +/* SDHCI_BLOCK_SIZE 0x04 */ +#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) + +/* SDHCI_TRANSFER_MODE 0x0C */ +#define SDHCI_TRNS_DMA 0x01 +#define SDHCI_TRNS_BLK_CNT_EN 0x02 +#define SDHCI_TRNS_ACMD12 0x04 +#define SDHCI_TRNS_READ 0x10 +#define SDHCI_TRNS_MULTI 0x20 + +/* SDHCI_COMMAND 0x0E */ +#define SDHCI_CMD_RESP_MASK 0x03 +#define SDHCI_CMD_CRC 0x08 +#define SDHCI_CMD_INDEX 0x10 +#define SDHCI_CMD_DATA 0x20 +#define SDHCI_CMD_ABORTCMD 0xC0 + +#define SDHCI_CMD_RESP_NONE 0x00 +#define SDHCI_CMD_RESP_LONG 0x01 +#define SDHCI_CMD_RESP_SHORT 0x02 +#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 + +#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) +#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) + +/* SDHCI_PRESENT_STATE 0x24 */ +#define SDHCI_CMD_INHIBIT 0x00000001 +#define SDHCI_DATA_INHIBIT 0x00000002 +#define SDHCI_DOING_WRITE 0x00000100 +#define SDHCI_DOING_READ 0x00000200 +#define SDHCI_SPACE_AVAILABLE 0x00000400 +#define SDHCI_DATA_AVAILABLE 0x00000800 +#define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_CARD_STATE_STABLE 0x00020000 +#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000 +#define SDHCI_WRITE_PROTECT 0x00080000 + +/* SDHCI_HOST_CONTROL 0x28 */ +//#define SDHCI_CTRL_LED 0x01 +#define SDHCI_CTRL_4BITBUS 0x02 +#define SDHCI_CTRL_HISPD 0x04 +#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_CD_TEST_INS 0x40 +#define SDHCI_CTRL_CD_TEST 0x80 + +/* SDHCI_POWER_CONTROL 0x29 */ +#define SDHCI_POWER_ON 0x01 +//#define SDHCI_POWER_180 0x0A +//#define SDHCI_POWER_300 0x0C +#define SDHCI_POWER_330 0x0E + +/* SDHCI_CLOCK_CONTROL 0x2C */ +#define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_DIVIDER_HI_SHIFT 6 +#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK_LEN 8 +#define SDHCI_DIV_HI_MASK 0x300 +#define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_INT_STABLE 0x0002 +#define SDHCI_CLOCK_INT_EN 0x0001 + +/* SDHCI_SOFTWARE_RESET 0x2F */ +#define SDHCI_RESET_ALL 0x01 +#define SDHCI_RESET_CMD 0x02 +#define SDHCI_RESET_DATA 0x04 + +/* SDHCI_INT_STATUS 0x30 */ +/* SDHCI_INT_ENABLE 0x34 */ +/* SDHCI_SIGNAL_ENABLE 0x38 */ +#define SDHCI_INT_RESPONSE 0x00000001 +#define SDHCI_INT_DATA_END 0x00000002 +#define SDHCI_INT_DMA_END 0x00000008 +#define SDHCI_INT_SPACE_AVAIL 0x00000010 +#define SDHCI_INT_DATA_AVAIL 0x00000020 +#define SDHCI_INT_CARD_INSERT 0x00000040 +#define SDHCI_INT_CARD_REMOVE 0x00000080 +#define SDHCI_INT_CARD_INT 0x00000100 +#define SDHCI_INT_ERROR 0x00008000 +#define SDHCI_INT_TIMEOUT 0x00010000 +#define SDHCI_INT_CRC 0x00020000 +#define SDHCI_INT_END_BIT 0x00040000 +#define SDHCI_INT_INDEX 0x00080000 +#define SDHCI_INT_DATA_TIMEOUT 0x00100000 +#define SDHCI_INT_DATA_CRC 0x00200000 +#define SDHCI_INT_DATA_END_BIT 0x00400000 +#define SDHCI_INT_BUS_POWER 0x00800000 +#define SDHCI_INT_ACMD12ERR 0x01000000 +#define SDHCI_INT_ADMA_ERROR 0x02000000 + +#define SDHCI_INT_NORMAL_MASK 0x00007FFF +#define SDHCI_INT_ERROR_MASK 0xFFFF8000 + +#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ + SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) +#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ + SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ + SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) +#define SDHCI_INT_ALL_MASK ((unsigned int)-1) & ~0x100 + +typedef enum sdhci_reg +{ + SDHCI_DMA_ADDRESS = 0x00, + SDHCI_BLOCK_SIZE = 0x04, + SDHCI_BLOCK_COUNT = 0x06, + SDHCI_ARGUMENT = 0x08, + SDHCI_TRANSFER_MODE = 0x0c, + SDHCI_COMMAND = 0x0E, + SDHCI_RESPONSE = 0x10, + SDHCI_RESPONSE1 = 0x14, + SDHCI_RESPONSE2 = 0x18, + SDHCI_RESPONSE3 = 0x1c, + SDHCI_BUFFER = 0x20, + SDHCI_PRESENT_STATE = 0x24, + SDHCI_HOST_CONTROL = 0x28, + SDHCI_POWER_CONTROL = 0x29, + SDHCI_BLOCK_GAP_CONTROL = 0x2a, + SDHCI_WAKE_UP_CONTROL = 0x2b, + SDHCI_CLOCK_CONTROL = 0x2c, + SDHCI_TIMEOUT_CONTROL = 0x2e, + SDHCI_SOFTWARE_RESET = 0x2f, + SDHCI_INT_STATUS = 0x30, + SDHCI_ERRINT_STATUS = 0x32, + SDHCI_INT_ENABLE = 0x34, + SDHCI_ERRINT_ENABLE = 0x36, + SDHCI_SIGNAL_ENABLE = 0x38, + SDHCI_ERRSIGNAL_ENABLE = 0x3a, + SDHCI_ACMD12_ERR = 0x3c, + SDHCI_HOST_CONTROL2 = 0x3e, + SDHCI_CAPABILITIES = 0x40, + SDHCI_CAPABILITIES_1 = 0x44, + SDHCI_MAX_CURRENT = 0x48, + SDHCI_SET_ACMD12_ERROR = 0x50, + SDHCI_SET_INT_ERROR = 0x52, + SDHCI_ADMA_ERROR = 0x54, + SDHCI_ADMA_ADDRESS = 0x58, + SDHCI_ADMA_ADDRESS_HI = 0x5c, + SDHCI_PRESET_FOR_SDR12 = 0x66, + SDHCI_PRESET_FOR_SDR25 = 0x68, + SDHCI_PRESET_FOR_SDR50 = 0x6a, + SDHCI_PRESET_FOR_SDR104 = 0x6c, + SDHCI_PRESET_FOR_DDR50 = 0x6e, + SDHCI_PRESET_FOR_HS400 = 0x74, + + SPEC_VERSION_NUMBER = 0xfe, + VENDOR_DEFINE_REG0 = 0x100, + VENDOR_DEFINE_REG1 = 0x104, + VENDOR_DEFINE_REG2 = 0x108, + VENDOR_DEFINE_REG3 = 0x10c, + VENDOR_DEFINE_REG4 = 0x110, + VENDOR_DEFINE_REG5 = 0x114, + VENDOR_DEFINE_REG6 = 0x118, + VENDOR_DEFINE_REG7 = 0x11c, + VENDOR_DEFINE_REG8 = 0x120, + VENDOR_DEFINE_REG9 = 0x124, + DMA_HANDSHAKE_EN_REG = 0x128, + HW_ATTRIBUTES_REG = 0x178, + IP_REVISION_REG = 0x17C, + SDHCI_REG_MAX = 0xFFFF +} SDHCI_REG_T; +/* + * End of controller registers. + */ +//#define SDHCI_MAX_DIV_SPEC_200 256 +#define SDHCI_MAX_DIV_SPEC_300 2046 +/* + * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. + */ +#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) +#define SDHCI_DEFAULT_BOUNDARY_ARG (7) + +struct sdhci_host { + u32 ioaddr; + u32 quirks; + u32 host_caps; + u32 version; + u32 clock; + u32 voltages; + int index; + struct mmc *mmc; +}; + +static __inline void sdhci_writel(struct sdhci_host *host, u32 val, SDHCI_REG_T reg) +{ + (*((volatile unsigned int *)(host->ioaddr + reg)) = (unsigned int)(val)); +} + +static __inline void sdhci_writew(struct sdhci_host *host, u16 val, SDHCI_REG_T reg) +{ + (*((volatile unsigned short *)(host->ioaddr + reg)) = (unsigned short)(val)); +} + +static __inline void sdhci_writeb(struct sdhci_host *host, u8 val, SDHCI_REG_T reg) +{ + (*((volatile unsigned char *)(host->ioaddr + reg)) = (unsigned char)(val)); +} + +static __inline u32 sdhci_readl(struct sdhci_host *host, SDHCI_REG_T reg) +{ + return *((volatile unsigned int *)(host->ioaddr + reg)); +} + +static __inline u16 sdhci_readw(struct sdhci_host *host, SDHCI_REG_T reg) +{ + return *((volatile unsigned short *)(host->ioaddr + reg)); +} + +static __inline u8 sdhci_readb(struct sdhci_host *host, SDHCI_REG_T reg) +{ + return *((volatile unsigned char *)(host->ioaddr + reg)); +} + + +#endif /* __SDHCI_H__ */ diff --git a/board/novatek/na51068/loader/Include/signal.h b/board/novatek/na51068/loader/Include/signal.h new file mode 100755 index 000000000000..5a2a7078c80c --- /dev/null +++ b/board/novatek/na51068/loader/Include/signal.h @@ -0,0 +1,4 @@ +#ifndef _NVT_LIBC_SIGNAL_H__ +#define _NVT_LIBC_SIGNAL_H__ +int raise(int sig); +#endif diff --git a/board/novatek/na51068/loader/Include/spi020.h b/board/novatek/na51068/loader/Include/spi020.h new file mode 100755 index 000000000000..ea07e949ef28 --- /dev/null +++ b/board/novatek/na51068/loader/Include/spi020.h @@ -0,0 +1,281 @@ +#ifndef _SPI020_H_ +#define _SPI020_H_ + +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "spi_flash.h" + +#define FTSPI020_DMA_TX_CH 0 +#define FTSPI020_DMA_RX_CH 1 + +//#define CONFIG_SPI_DMA +//#define CONFIG_SPI_QUAD +//============================================================================= +// System Header, size = 256 bytes +//============================================================================= + +#define NORMAL_MODE 0 +#define HW_HANDSHAKE_MODE 1 + +#define FTSPI020_32BIT(offset) *((volatile unsigned int *)(REG_SPI020_BASE + offset)) +#define FTSPI020_16BIT(offset) *((volatile UINT16 *)(REG_SPI020_BASE + offset)) +#define FTSPI020_8BIT(offset) *((volatile unsigned char *)(REG_SPI020_BASE + offset)) +#define READ_REG32(_register_) *((volatile unsigned int *)(_register_)) +#define WRITE_REG32(_register_, _value_) (*((volatile unsigned int *)(_register_)) = (unsigned int)(_value_)) + +#define SPI_FLASH_ADDR 0x0000 +#define SPI_CMD_FEATURE1 0x0004 + #define no_addr_state 0 // bit[2:0] + #define addr_1byte 1 + #define addr_2byte 2 + #define addr_3byte 3 + #define addr_4byte 4 + #define no_dummy_cycle_2nd 0 // bit[23:16] + #define dummy_1cycle_2nd 1 + #define dummy_2cycle_2nd 2 + #define dummy_3cycle_2nd 3 + #define no_instr_state 0 // bit[25:24] + #define instr_1byte 1 + #define instr_2byte 2 + // bit[27:26] + #define no_enable_dummy_cycle 0 + +#define SPI_DATA_CNT 0x0008 +#define SPI_CMD_FEATURE2 0x000C + // bit0 + #define cmd_complete_intr_enable 1 + // bit1 + #define spi_read 0 + #define spi_write 1 + // bit2 + #define read_status_disable 0 + #define read_status_enable 1 + // bit3 + #define read_status_by_hw 0 + #define read_status_by_sw 1 + // bit4 + #define dtr_disable 0 + #define dtr_enable 1 + // bit[7:5] + #define spi_operate_serial_mode 0 + #define spi_operate_dual_mode 1 + #define spi_operate_quad_mode 2 + #define spi_operate_dualio_mode 3 + #define spi_operate_quadio_mode 4 + // bit[9:8] + #define start_ce0 0 + // bit[23:16] op_code info + + // bit[31:24] instr index + +#define CONTROL_REG 0x0010 + // bit[1:0] divider + #define divider_2 0 + #define divider_4 1 + #define divider_6 2 + #define divider_8 3 + // bit 4 mode + #define mode0 0 + #define mode3 1 + // bit 8 abort + // bit 9 wp_en + // bit[18:16] busy_loc + #define BUSY_BIT0 0 + +#define AC_TIMING 0x0014 +// bit[3:0] CS timing +// bit[7:4] Trace delay + +#define STATUS_REG 0x0018 +// bit0 Tx Empty +// bit1 Rx Full + #define tx_ready 0 + #define rx_ready 1 +// bit2 Cmd Queue Full + +#define INTR_CONTROL_REG 0x0020 + +#define INTR_STATUS_REG 0x0024 +#define cmd_complete (0x1 << 0) + +#define SPI_READ_STATUS 0x0028 +#define TX_DATA_CNT 0x0030 +#define RX_DATA_CNT 0x0034 +#define REVISION 0x0050 +#define FEATURE 0x0054 +#define support_dtr_mode (0x1 << 24) +#define SPI020_DATA_PORT 0x0100 + +// ===================================== Common commands ===================================== +#define CMD_READ_ID 0x9F +#define CMD_RESET 0xFF + +// Command +#define COMMAND_WRITE_ENABLE 0x06 +#define COMMAND_WRITE_DISABLE 0x04 +#define COMMAND_ERASE_SECTOR 0x20 +#define COMMAND_ERASE_32K_BLOCK 0x52 +#define COMMAND_ERASE_64K_BLOCK 0xD8 +#define COMMAND_ERASE_CHIP 0xC7 +#define COMMAND_READ_STATUS1 0x05 +#define COMMAND_READ_STATUS2 0x35 +#define COMMAND_WRITE_STATUS 0x01 +#define COMMAND_WRITE_PAGE 0x02 +#define COMMAND_WINBOND_QUAD_WRITE_PAGE 0x32 +#define COMMAND_QUAD_WRITE_PAGE 0x38 +#define COMMAND_READ_DATA 0x03 +#define COMMAND_FAST_READ 0x0B +#define COMMAND_FAST_READ_DUAL 0x3B +#define COMMAND_FAST_READ_DUAL_IO 0xBB +#define COMMAND_FAST_READ_QUAD 0x6B +#define COMMAND_FAST_READ_QUAD_IO 0xEB +#define COMMAND_FAST_READ_DTR_QUAD_IO 0xED +#define COMMAND_WORD_READ_QUAD_IO 0xE7 +#define COMMAND_READ_UNIQUE_ID 0x4B +#define COMMAND_EN4B 0xB7 //enter 4 byte mode +#define COMMAND_EX4B 0xE9 //exit 4 byte mode + +/* Additional command for SPI NAND */ +#define COMMAND_GET_FEATURES 0x0F +#define COMMAND_SET_FEATURES 0x1F +#define COMMAND_PAGE_READ 0x13 +#define COMMAND_PROGRAM_LOAD 0x02 +#define COMMAND_PROGRAM_EXECUTE 0x10 +#define COMMAND_BLOCK_ERASE 0xD8 + +#define SPI_XFER_CMD_STATE 0x00000002 +#define SPI_XFER_DATA_STATE 0x00000004 +#define SPI_XFER_CHECK_CMD_COMPLETE 0x00000008 + +/* Status register 1 bits */ +#define FLASH_STS_BUSY (0x1 << 0) +// ===================================== Variable and Struct ===================================== + +/* default flash parameters */ + +typedef enum { + READ_DATA = 0, + FAST_READ, + FAST_READ_QUAD_IO +} read_type_t; + +typedef enum { + SECTOR_ERASE = 0, //4K + BLOCK_32K_ERASE, + BLOCK_64K_ERASE +} erase_type_t; + +// Cmd Type for choosing +typedef enum { + PAGE_PROGRAM = 0, + QUAD_PROGRAM +} write_type_t; + +struct spi_flash { + unsigned int ce; + unsigned int erase_sector_size; + unsigned int page_size; + unsigned int nr_pages; + unsigned int size; //chip size + unsigned int mode_3_4; //addres length = 3 or 4 bytes + unsigned int read_command; + int (*spi_xfer)(struct spi_flash * flash, unsigned int len, const void *dout, void *din, unsigned long flags, int sts_hw); + int (*read) (struct spi_flash * flash, read_type_t type, unsigned int offset, unsigned int len, void *buf); + int (*write) (struct spi_flash * flash, write_type_t type, unsigned int offset, unsigned int len, void *buf); + int (*erase) (struct spi_flash * flash, erase_type_t type, unsigned int offset, unsigned int len); + int (*erase_all) (struct spi_flash * flash); + struct { + UINT32 chip_block; + UINT32 block_pg; + UINT32 page_size; + UINT32 spare_size; + UINT32 block_size; + } nand_parm; +}; + +typedef struct ftspi020_cmd { + // offset 0x00 + unsigned int spi_addr; + // offset 0x04 + unsigned char addr_len; + unsigned char dum_2nd_cyc; + unsigned char ins_len; /* instruction length */ + unsigned char conti_read_mode_en; + // offset 0x08 + unsigned int data_cnt; + // offset 0x0C + unsigned char intr_en; + unsigned char write_en; + unsigned char read_status_en; + unsigned char read_status; + unsigned char dtr_mode; + unsigned char spi_mode; + unsigned char start_ce; + unsigned char conti_read_mode_code; + unsigned char ins_code; +} ftspi020_cmd_t; + +/* Init function, 0 for success, otherwise for fail + */ +struct spi_flash *FTSPI020_Init(void); + +/* Flash Read function, + * start_pg: start page + * len: how many bytes + * 0 for success, otherwise for fail + */ +int FTSPI020_PgRd(unsigned int start_pg, unsigned char *rx_buf, unsigned int len); + +/* Flash Write function, + * start_pg: start page + * 0 for success, otherwise for fail + */ +int FTSPI020_PgWr(unsigned int start_pg, unsigned char *tx_buf); + +/* Flash sector erase, + * sector: sector no. + * sector_cnt: how many sectors + * 0 for success, otherwise for fail + */ +int FTSPI020_Erase_Sector(unsigned int sector, unsigned int sector_cnt); + +/* Flash chip erase + * 0 for success, otherwise for fail + */ +int FTSPI020_Erase_Chip(void); + +/* Update the flash config + */ +int FTSPI020_Update_Param(unsigned int divisor, unsigned int pagesz_log2, unsigned int secsz_log2, unsigned int chipsz_log2); + +/* load the code and execute it. */ +unsigned int fLib_NOR_Copy_Image(unsigned int addr, unsigned int fdt_addr); +unsigned int fLib_SPI_NAND_Copy_Image(unsigned int addr, unsigned int fdt_addr); + +/* Get the current config of FLASH. + */ +struct spi_flash *FTSPI020_Get_Param(void); + +/* Get FLASH status-1 and -2 register + */ +unsigned int FTSPI020_Get_Status(void); +int flash_set_quad_enable(struct spi_flash *flash, int en); +/* + * API backward compatiable + */ +#define spi_init FTSPI020_Init +#define spi_load_para FTSPI020_Update_Param +#define spi_pgrd FTSPI020_PgRd +#define spi_pgwr FTSPI020_PgWr +#define spi_get_satus FTSPI020_Get_Status +#define spi_erase_sect FTSPI020_Erase_Sector +#define spi_erase_chip FTSPI020_Erase_Chip +/* + * The following functions are used internal only. + */ +void ftspi020_read_status(unsigned char * status); +unsigned char ftspi020_issue_cmd(struct ftspi020_cmd *command); +void ftspi020_data_access(unsigned char *dout, unsigned char *din, unsigned int len); +void ftspi020_wait_cmd_complete(void); +#endif /* _SPI020_H_ */ \ No newline at end of file diff --git a/board/novatek/na51068/loader/Include/spi_flash.h b/board/novatek/na51068/loader/Include/spi_flash.h new file mode 100755 index 000000000000..2bef2975df8d --- /dev/null +++ b/board/novatek/na51068/loader/Include/spi_flash.h @@ -0,0 +1,111 @@ +//***************************************************************************** +// Copyright Faraday Technology Corp 2002-2003. All rights reserved. * +//----------------------------------------------------------------------------* +// Name: spi_flash.h * +// Description: SPI flash access functions * +//***************************************************************************** +#ifndef _SPI_FALSH_H_ +#define _SPI_FALSH_H_ + +#include "board.h" + +#define READ_REG32(_register_) *((volatile unsigned int *)(_register_)) +#define WRITE_REG32(_register_, _value_) (*((volatile unsigned int *)(_register_)) = (unsigned int)(_value_)) + +#define SS_SIGNATURE "NT8313" + +//============================================================================= +// System Header, size = 256 bytes +//============================================================================= +typedef struct +{ + char signature[8]; /* Signature is "GM8xxx" */ + struct { + unsigned int addr; /* partition address */ + unsigned int size; /* partition size */ + unsigned char name[8]; /* partition name */ + unsigned int img_size; /* image size */ + } image[12]; + + struct { + unsigned char pagesz_log2; // page size with bytes in log2 + unsigned char secsz_log2; // sector size with bytes in log2 + unsigned char chipsz_log2; // chip size with bytes in log2 + unsigned char clk_div; // 2/4/6/8 + } norfixup; + unsigned char reserved[2]; // Reserved for future + unsigned char last_256[2]; // byte254:0x55, byte255:0xAA +} NOR_SYSHDR; + +#if 0//def CONFIG_FPGA + +typedef struct +{ + char signature[8]; /* Signature is "GM8xxx" */ + struct { + unsigned int addr; /* partition address */ + unsigned int size; /* partition size */ + unsigned char name[8]; /* partition name */ + unsigned int img_size; /* image size */ + } image[23]; + + struct { + unsigned int nand_numblks; //number of blocks in chip + unsigned int nand_numpgs_blk; //how many pages in a block + unsigned int nand_pagesz; //real size in bytes + unsigned int nand_sparesz_inpage; //64bytes for 2k, ...... needed for NANDC023 + unsigned int nand_numce; //how many CE in chip + unsigned int nand_clkdiv; // 2/4/6/8 + unsigned int nand_ecc_capability; + unsigned int nand_sparesz_insect; + } nandfixup; + unsigned int reserved[2]; // unused + unsigned char last_511[4]; // byte510:0x55, byte511:0xAA +} SPI_NAND_SYSHDR; + +#else + +typedef struct +{ + char signature[8]; /* Signature is "GM8xxx" */ + struct { + unsigned int addr; /* partition address */ + unsigned int size; /* partition size */ + unsigned char name[8]; /* partition name */ + unsigned int img_size; /* image size */ + } image[20]; + + unsigned int arg[10][2]; + unsigned char reserved_0[4]; + + struct { + unsigned int nand_numblks; //number of blocks in chip + unsigned int nand_numpgs_blk; //how many pages in a block + unsigned short nand_pagesz; //real size in bytes + unsigned short nand_sparesz_inpage; //64bytes for 2k, ...... needed for NANDC023 + unsigned short nand_numce; //how many CE in chip + unsigned char nand_clkdiv; // 2/4/6/8 + unsigned char function; + //unsigned int nand_ecc_capability; + //unsigned int nand_sparesz_insect; + } nandfixup; + unsigned char reserved[2]; // unused + unsigned char last_511[2]; // byte510:0x55, byte511:0xAA +} SPI_NAND_SYSHDR; +#endif + +//============================================================================= +// SPI flash access functions +//============================================================================= +void spi_load_para(INT32U dividor, INT32U pagesz_log2, + INT32U secsz_log2, INT32U chipsz_log2); +INT32U spi_get_satus(void); +void spi_erase_sect(INT32U sector, INT32U sector_cnt); +void spi_erase_chip(void); +int spi_pgrd(INT32U page, INT32U *buf, INT32U len); +int spi_pgwr(INT32U page, INT32U *buf); + +#endif //_SPI_FALSH_H_ + +//----------------------------------------------------------------------------- +// EOF spi_flash.h diff --git a/board/novatek/na51068/loader/Include/stdarg.h b/board/novatek/na51068/loader/Include/stdarg.h new file mode 100755 index 000000000000..f9af3123244d --- /dev/null +++ b/board/novatek/na51068/loader/Include/stdarg.h @@ -0,0 +1,19 @@ +#ifndef __NVT_STDARG_H__ +#define __NVT_STDARG_H__ + +typedef char *va_list; + +/* + * Storage alignment properties + */ +#define _AUPBND (sizeof (int) - 1) +#define _ADNBND (sizeof (int) - 1) + +/* + * Variable argument list macro definitions + */ +#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd))) +#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND)))) +#define va_end(ap) (void) 0 +#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND)))) +#endif diff --git a/board/novatek/na51068/loader/Include/stdio.h b/board/novatek/na51068/loader/Include/stdio.h new file mode 100755 index 000000000000..ec8eff4318d4 --- /dev/null +++ b/board/novatek/na51068/loader/Include/stdio.h @@ -0,0 +1,23 @@ +/** + STDIO header + + STDIO header + + @file stdio.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_STDIO_H__ +#define __NVT_STDIO_H__ + +/** \addtogroup mISYSClib */ +//@{ + +int sprintf(char * buf, const char *fmt, ...); +int sscanf(const char * buf, const char * fmt, ...); + +//@} +#endif diff --git a/board/novatek/na51068/loader/Include/stdlib.h b/board/novatek/na51068/loader/Include/stdlib.h new file mode 100755 index 000000000000..9f8540807eb6 --- /dev/null +++ b/board/novatek/na51068/loader/Include/stdlib.h @@ -0,0 +1,4 @@ +#ifndef __NVT_LIBC_STDLIB_H__ +#define __NVT_LIBC_STDLIB_H__ +int atoi(const char *nptr); +#endif diff --git a/board/novatek/na51068/loader/Include/string.h b/board/novatek/na51068/loader/Include/string.h new file mode 100755 index 000000000000..5895db6eba7e --- /dev/null +++ b/board/novatek/na51068/loader/Include/string.h @@ -0,0 +1,47 @@ +/** + string header + + string header + + @file string.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_LIBC_STRING_H__ +#define __NVT_LIBC_STRING_H__ + +/** \addtogroup mISYSClib */ +//@{ + +/** + size_t data type + + data type to store value return by sizeof keyword +*/ +typedef unsigned int size_t; + +extern size_t strlen(const char *s) __attribute__ ((section (".part1"))); +extern size_t strnlen(const char *s, size_t count); +extern char *strncpy(char *dest, const char *src, size_t count); +extern char *strncat(char *dest, const char *src, size_t count); +extern char *strstr(const char *s1, const char *s2); +extern int strncmp(const char *cs, const char *ct, size_t count); +extern char *strrchr(const char *s, int c); +extern char *strcpy(char *dest, const char *src); +extern char *strcat(char *dest, const char *src); +extern char *strchr(const char *s, int c); +extern char* strtok(char *s, const char *delim); +extern int strcmp(const char *cs, const char *ct); + +extern void *utl_memset(void *s, int c, size_t count); +extern void *utl_memcpy(void *dest, const void *src, size_t count); +extern int memcmp(const void *cs, const void *ct, size_t count); +extern void *memmove(void *dest, const void *src, size_t count); +extern void *memchr(const void *ptr, int value, size_t count); +//@} + +#endif + diff --git a/board/novatek/na51068/loader/Include/timer.h b/board/novatek/na51068/loader/Include/timer.h new file mode 100755 index 000000000000..8f829f0f0410 --- /dev/null +++ b/board/novatek/na51068/loader/Include/timer.h @@ -0,0 +1,9 @@ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +void udelay(unsigned int usec); +void mdelay(unsigned int msec); +void delay(unsigned int sec); + + +#endif /* __TIMER_H__ */ diff --git a/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile new file mode 100644 index 000000000000..96063aba60a6 --- /dev/null +++ b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile @@ -0,0 +1,57 @@ +#---------------------------------------------------------------------- +# include make config file +#---------------------------------------------------------------------- +include ../../../Project/Model/ModelConfig.txt +include ../../../Project/Model/ModelConfig_$(MODEL).txt +include ../../../Project/Model/MakeConfig.txt + +#---------------------------------------------------------------------- +# set the library name here +#---------------------------------------------------------------------- +PRJ_NAME = Ctrl_Flow + + +#---------------------------------------------------------------------- +# add/delete source files here +#---------------------------------------------------------------------- +SRC = \ + main.c \ + bl_func.c \ + bl_u2.c \ + nand_ids.c\ + spi_nor_ids.c\ + +ASM = + +#---------------------------------------------------------------------- +# set the include directory here +#---------------------------------------------------------------------- +INC_DIR = . \ + ../../../Include + +#---------------------------------------------------------------------- +# set the image output directory here +#---------------------------------------------------------------------- +IMG_BASE_DIR = ../../../ARC/Lib + +#---------------------------------------------------------------------- +# add additional C and assembly flags here +#---------------------------------------------------------------------- +CFLAGS_D = -O2 +ASMFLAGS_D = + +CFLAGS_R = -O2 +ASMFLAGS_R = + +C_DEFINE_EXT = \ + $(EXTSTRG_PARAM) \ + $(SECURE_DECRYPT_UBOOT_PARAM) \ + $(UBOOT_BIND_PARAM) + +CFLAGS_R = $(C_DEFINE_EXT) + +#---------------------------------------------------------------------- +# include common parts of the makefile +#---------------------------------------------------------------------- +MAKE_COMMON_DIR = ../../../MakeCommon +include $(MAKE_COMMON_DIR)/OutputLib.txt diff --git a/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c new file mode 100755 index 000000000000..fd59a6aa4b11 --- /dev/null +++ b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c @@ -0,0 +1,2137 @@ +/* + Main control function + + This file is implement by user mode + + @file bl_func.c + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ + +#include "constant.h" +#include "fuart.h" +#include "fat.h" +#include "StorageDef.h" +#include "global.h" +#include "bl_func.h" +#include "string.h" +#include "lz.h" +#include "debug.h" +#include "loader.h" +#include "emb_partition_info.h" +#include "modelext_info.h" +#include "bin_info.h" +#include "shm_info.h" +#include "libfdt.h" +#include +#include "mmc_api.h" +#include "cache.h" +#include "Memory.h" +#include "bl_u2.h" +#include "crypto.h" +#include "nand.h" +#include "nor.h" + +PSTORAGE_OBJ int_strg_obj = NULL; +#define _THUMB2 __attribute__((target("thumb"))) +#define FW_PART1_SIZE_OFFSET (CODE_SECTION_OFFSET + 0x04) //ref to CodeInfo.S on rtos (addr of _section_01_size) +static uint32_t global_timer_freq = 3000000; //3MHz = 3000000 Hz + +static UINT8 UPDATE_FW_NAME[] = {"FW98321A.BIN"}; +static UINT8 UPDATE_LOADER_NAME[] = {"LD98321A.BIN"}; +static UINT8 RUN_FW_NAME[] = {"FW98321T.BIN"}; +static UINT8 *LOADER_START_STR = {(UINT8 *)"\r\nLoader Start ..."}; +static UINT8 RECOVERY_FW_NAME[] = {"FW98321R.BIN"}; +static UINT32 g_uiPartitionID = 2; +static UINT32 g_uiVersion = 0; + +#define _TODO 0 + +#define bl_memcpy utl_memcpy +#define bl_memset utl_memset +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#define SIZE_PRELOAD 0x400 +#define SIZE_PRESERVE_USB 0x2000 + +static UINT32 g_rtos_load_addr = 0; +static UINT32 g_rtos_target_addr = 0; +static UINT32 g_rtos_size = 0; + + +extern char _loader_heap_base[]; +static BOOL g_is_flash_open = FALSE; // indicate flash is open for updating non-fully all-in-one bin. +static UINT32 g_uiStartBlkUpdateFW = StartNandBlkUpdateFW; +static STORAGEINT gStorageIntType = STORAGEINT_UNOKNOWN; +static UINT32 g_uiNandBlkSize = 0; + +extern void uart_upgrade_procedure(void); +#if !(USB_WRITELOADER) +extern void set_usb_suspend(void); +#endif + +#if (FDT_SUPPORT) +#define PATH_MEM_DRAM "/nvt_memory_cfg/dram" +#define PATH_MEM_LOADER "/nvt_memory_cfg/loader" +#define PATH_MEM_UBOOT "/nvt_memory_cfg/uboot" +#define PATH_MEM_FDT "/nvt_memory_cfg/fdt" +#define PATH_MEM_SHMEM "/nvt_memory_cfg/shmem" +#define PATH_MEM_RTOS "/nvt_memory_cfg/rtos" +#define PATH_MEM_NUTTX "/nvt_memory_cfg/nuttx" +#define PATH_MEM_CORE2_ENTRY1 "/nvt_memory_cfg/core2entry1" +#define PATH_MEM_CORE2_ENTRY2 "/nvt_memory_cfg/core2entry2" +#define PATH_NVTPACK_INDEX "nvtpack/index" +#define PATH_PARTITION_LOADER "partition_loader" +#define PATH_PARTITION_FDT "partition_fdt" +#define PATH_PARTITION_UBOOT "partition_uboot" +#define PATH_PARTITION_NUTTX "partition_nuttx" +#define PATH_PARTITION_RTOS "partition_rtos" +#define PROPERTY_REG "reg" +#define PROPERTY_LABEL "label" +#define PROPERTY_PARTITION_NAME "partition_name" +static DRAM_PARTITION g_dram_partition = {0}; +static EMB_PARTITION g_emb_uboot = {0}; +static EMB_PARTITION g_emb_loader = {0}; +static EMB_PARTITION g_emb_rtos = {0}; +#else // NO FDT_SUPPORT +// refer to met-tbl.dtsi /nvt_memory_cfg +static DRAM_PARTITION g_dram_partition = { + .dram_addr = 0x00000000, + .dram_size = 0x20000000, + .rev_addr = 0x00200000, ///< shmem + .rev_size = 0x00000200, ///< shmem + .loader_addr = 0x01000000, + .loader_size = 0x00800000, + .fdt_addr = 0x00100000, + .fdt_size = 0x00040000, + .uboot_addr = 0x1E000000, + .uboot_size = 0x01FC0000, + .rtos_addr = 0x01840000, ///< optional, only for fast-boot, + .rtos_size = 0x00780000, ///< optional, only for fast-boot + .core2_entry1_addr = 0x00000000, ///< optional, only for dual core IC (fixed here, and must be) + .core2_entry1_size = 0x00004000, ///< optional, only for dual core IC + .core2_entry2_addr = 0x1FFC0000, ///< optional, only for dual core IC (address better in the bottom of dram to avoid memory space overlap) + .core2_entry2_size = 0x00040000, ///< optional, only for dual core IC +}; +// refer to storage-partition.dtsi +static EMB_PARTITION g_emb_loader = { + .PartitionOffset = 0x00000, + .PartitionSize = 0x40000, +}; +static EMB_PARTITION g_emb_uboot = { + .PartitionOffset = 0xC0000, + .PartitionSize = 0x200000, +}; +static EMB_PARTITION g_emb_rtos = { ///< optional, only for fast-boot, + .PartitionOffset = 0x2B40000, + .PartitionSize = 0xA00000, +}; +//following just for processing all-in-one bin (nvtpack) +//refer to nvtpack.dtsi +#define NVTPACK_IDX_LOADER 0 +#define NVTPACK_IDX_UBOOT 3 +#define NVTPACK_IDX_RTOS 10 +#endif + +//#if CHECKSUM_EN +// Error message +static char FWErrorMsg[] = "\r\nFW check fail\r\n"; +//#endif + +// Error message +static char RWErrorMsg[] = "\r\nR/W error\r\n"; +static char LoaderErrorMsg[] = "\r\nLoader check fail\r\n"; + +//--------------------------------------------------------------------------- +// Static function +//--------------------------------------------------------------------------- +/** + Display error message. + + Display error message. + CPU loop forever and LED is red. + + @param Msg: Message to display + @return void +*/ +_THUMB2 static void bl_displayErrMsg(char *Msg) +{ + // Display error message to UART + debug_msg(Msg); + // Loop forever + while (1) { + ; + } +} + + +/** + Invert endianess of input word + + + @param[in] a input word + + @return translated word +*/ +_THUMB2 static UINT32 invertEndian(UINT32 a) +{ + return __builtin_bswap32(a); +} + + +/** + Check FW code. + + Check FW code and file length. + The FW binary file must be post-proecessd by encrypt_bin.exe. + This function must sync to encrypt_bin.exe. + If FW checking is fail, the CPU will loop forever and LED is red. + + @param[in] uiAddress FW code in DRAM starting address + @param[in] uiFileLen FW code length + @return void +*/ +_THUMB2 static void bl_checkFW(UINT32 uiAddress, UINT32 uiFileLen) +{ + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)uiAddress; + mem.len = uiFileLen; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + bl_displayErrMsg(FWErrorMsg); + } +} + +/** + Check boot loader code. + + Check boot loader code. + + @return void +*/ +_THUMB2 static void bl_checkLoader(UINT32 uiAddr, UINT32 uiSize) +{ + UINT16 *puiValue, uiSum; + UINT32 i; + + puiValue = (UINT16 *)uiAddr; + uiSum = 0; + + for (i = 0; i < (uiSize >> 1); i++) { + uiSum += (*puiValue + i); + puiValue++; + } + + if ((*(UINT16 *)(uiAddr + LOADER_TAG_OFFSET) != LOADER_TAG_VALUE) || + (uiSum != 0)) { + bl_displayErrMsg(LoaderErrorMsg); + } +} +#if (SECURE_DECRYPT_UBOOT) + +_THUMB2 static void get_bininfo_size_offset(unsigned char* bininfo,unsigned int* size,unsigned int *offset) +{ + /****this headinfo is for encrypt header + BinInfo will set partition offset and size + BinInfo_1[0~3] public key offset + BinInfo_1[4~7] public key length + BinInfo_2[0~3] signature offset + BinInfo_2[4~7] signature length + BinInfo_3[0~3] encrypted offset + BinInfo_3[4~7] encrypted size + BinLength total bin size + Checksum total bin checksum + others parameters set 0 + */ + *size = bininfo[4] | bininfo[5]<<8 | bininfo[6] << 16 | bininfo[7] << 24; + *offset = bininfo[0] | bininfo[1] << 8 | bininfo[2] << 16 | bininfo[3] <<24; +} + +_THUMB2 static int decrypt_aes_cbc(unsigned int input, unsigned int output, unsigned len) +{ + + CRYPT_OP crypt_op_param; + if(len &0x0f) + { + debug_msg_var("enc size", len); + debug_err("not align 16\r\n"); + return -21; + } + if((input & 0x03) || (output & 0x03) || (len & 0x03) ){ //check word alignment + //debug_msg_var("input", input); + //debug_msg_var("output", output); + //debug_msg_var("len", len); + //debug_err("not word align\r\n"); + return -22; + } + crypt_op_param.op_mode = CRYPTO_CBC; + crypt_op_param.en_de_crypt = CRYPTO_DECRYPT; + crypt_op_param.src_addr = input; + crypt_op_param.dst_addr = output; + crypt_op_param.length = len; //Need align to 16bytes align + //debug_msg_var("src",(unsigned int)crypt_op_param.src_addr); + //debug_msg_var("dst",(unsigned int)crypt_op_param.dst_addr); + + #if 0 + debug_msg_var("input",input); + debug_msg_var("output",output); + debug_msg_var("len",len); + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i=0; + debug_msg_var("encryped buf addr",(unsigned int)tmp); + for(i=0;i<16;i++){ + debug_msg_var("encryped buf",(unsigned int)tmp[i]); + } + #endif + if(crypto_data_operation(EFUSE_OTP_1ST_KEY_SET_FIELD, crypt_op_param) != 0) + { + //debug_err("aes dec fail\r\n"); + return -23; + } + #if 0 + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i=0; + tmp = (unsigned char *) crypt_op_param.dst_addr; + debug_msg_var("decryped addr",(unsigned int)&tmp[0]); + for(i=0;i<16;i++){ + debug_msg_var("decryped buf",(unsigned int)tmp[i]); + } + + #endif + return 0; + +} + +_THUMB2 static void data_reverse(unsigned char* input_data, unsigned int size) +{ + unsigned int i=0; + unsigned char tmp=0; + for(i=0;i< (size/2);i++) + { + tmp = input_data[size - 1 - i]; + input_data[size - 1 - i] = input_data[i]; + input_data[i] = tmp; + } + +} + +_THUMB2 static int do_decrypt_aes(unsigned int input_data, unsigned int output_data, unsigned int* output_size,unsigned int partition_size) +{ + + unsigned int encrypt_offset =0; + unsigned int encrypt_size =0; + unsigned int data_size = 0; + HEADINFO *p_headinfo = (HEADINFO *)input_data; + int er=0; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_3, &encrypt_size, &encrypt_offset); + data_size = p_headinfo->BinLength - encrypt_offset; +#if 1 //for signature check + unsigned int key_offset =0; + unsigned int key_size =0; + unsigned int signature_offset =0; + unsigned int signature_size = 0; + UINT32 hash_buf[8]; + unsigned int n_size=0; + unsigned int e_size=0; + unsigned int sha256_align_size =0; + UINT32 rsa_output[64]; + UINT32 * signature_buff = NULL; + UINT32 *key_n = NULL; + UINT32 *key_e = NULL; + UINT32 *signature_addr = NULL; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_1, &key_size, &key_offset); + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_2, &signature_size, &signature_offset); + n_size = signature_size;// if rsa 2048 , signature_size should be 256 bytes + e_size = key_size - n_size; + key_n = (UINT32 *)(input_data + key_offset); + // now only support rsa 2048 + key_e = (UINT32 *)(input_data + key_offset + signature_size); // signature_size should be 256 bytes, n key should be 256 + data_reverse((unsigned char *)(key_n),n_size); + data_reverse((unsigned char *)(key_e),e_size); + + er = rsa_keycheck(key_n, 1);// check rsa n key in efuse 1 and 2 field, 0 field for aes key + if(er == 0) + { + debug_err("key fail\r\n"); + return -20; + } + signature_addr = (UINT32 *)(input_data + signature_offset); + data_reverse((unsigned char *)signature_addr, signature_size); + + //decrypt signature + rsa_decrypt(signature_addr, signature_size, key_n, n_size, key_e, e_size,rsa_output); + + data_reverse((unsigned char *)rsa_output, signature_size); + + //remove pending data 0, the last 32 bytes will be signature data + signature_buff = (UINT32 *)&rsa_output[(sizeof(rsa_output)/4 ) - (32/4 )];// offset need devided by 4, because of UINT32 type + //hash encrypt data + #if 0 + debug_msg_var("partition_size:",partition_size); + debug_msg_var("partition last addr:",input_data); + debug_msg_var("partition last addr:",input_data + partition_size); + debug_msg_var("input_data + encrypt_offset:",input_data + encrypt_offset); + debug_msg_var("input_data + encrypt_offset + data_size:",input_data + encrypt_offset + data_size); + debug_msg_var("data_size:",data_size); + debug_msg_var("hash buf addr:",(unsigned int)hash_buf); + #endif + + if((data_size & 0x3f) != 0) + { + // hardware sha256 need align 64, need set pending 0 + sha256_align_size = ((data_size/0x40) + 1)*0x40; + bl_memset((unsigned char *)(input_data + encrypt_offset + data_size),0, sha256_align_size - data_size); + } + else + { + sha256_align_size = data_size; + } + + shahw((unsigned char *)(input_data + encrypt_offset), sha256_align_size, hash_buf); + + //compare signature and current hash + if(memcmp((void *)hash_buf, (void *)signature_buff, sizeof(hash_buf)) != 0) + { + debug_err("sig fail\r\n"); + return -20; + } +#endif +//decrypt data + //dma addr should 4 alignment, input_data address is 4 alignment + if((input_data + encrypt_offset) & 0x03) + { + utl_memcpy((void *)input_data,(unsigned char*)(input_data + encrypt_offset), data_size); + er = decrypt_aes_cbc(input_data, output_data, encrypt_size); + } + else + { + er = decrypt_aes_cbc(input_data + encrypt_offset, output_data, encrypt_size); + } + if(er != 0) + { + debug_err("aes fail\r\n"); + return er; + } + + *output_size = data_size; + + //add plaintext data to output buf--> aes should 16 alignment, if data not alignment, the last bytes we will not encrypt data + int plaintext_size = data_size - encrypt_size; + unsigned char *p_output = (unsigned char *)output_data; + if( plaintext_size > 0) + { + utl_memcpy(&p_output[encrypt_size], (unsigned char*)(input_data + encrypt_offset+ encrypt_size),plaintext_size); + } + return 0; + +} +#endif + + + +_THUMB2 static void bl_cpu_timer_init(UINT32 value) +{ + UINT32 dwVal; + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_LOAD_OFFSET, value); + + dwVal = INW(configARM_TIMER_BASEADDR + ARM_TIMER_CONTROL_OFFSET); + /* Enable Auto reload mode. */ + dwVal |= ARM_TIMER_CONTROL_AUTO_RELOAD_MASK; + /* Clear prescaler control bits */ + dwVal &= ~ARM_TIMER_CONTROL_PRESCALER_MASK; + /* Set prescaler value */ + dwVal |= ((CYGHWR_HAL_RTC_PRESCALER - 1) << ARM_TIMER_CONTROL_PRESCALER_SHIFT); + /* Enable the decrementer */ + //dwVal |= ARM_TIMER_CONTROL_ENABLE_MASK; + /* Enable the interrupt */ + dwVal |= ARM_TIMER_CONTROL_IRQ_ENABLE_MASK; + + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_CONTROL_OFFSET, dwVal); + + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_ISR_OFFSET, + ARM_TIMER_ISR_EVENT_FLAG_MASK); + +} + +_THUMB2 int bl_flash_open(void) +{ + int er; + //UINT32 uiStorageVersion = (UINT32)&_load_nand_table_start_base; + + if (g_is_flash_open) { + return 0; + } +// User define SPI-NAND id table sample code +// int_strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_IDENTIFY_CB, (UINT32)nand_identify); + +// User define SPI-NOR id table sample code +// int_strg_obj->flash_installIdentifyCB(nor_identify); + er = int_strg_obj->flash_open(); + + if (er < 0) { + debug_err_var("flash open fail", er); + return -1; + } + + //OUTREG32(NAND_TABLE_VERSION_ADDR, INREG32(uiStorageVersion)); + + //if (er == E_OK) { + // OUTREG32(NAND_TABLE_FLAG_ADDR, 0x46495053); //'S''P''I''F' + //} else { // E_OK_TABLE_FOUND(1) or E_OK_TABLE_NOT_FOUND(2) + // OUTREG32(NAND_TABLE_FLAG_ADDR, er); + //} + g_uiNandBlkSize = int_strg_obj->flash_getBlockSize(); + if (g_uiNandBlkSize == 0x10000) { + debug_msg("SPI NOR\r\n"); + g_uiStartBlkUpdateFW = 1; + } else if (g_uiNandBlkSize == EMMC_BLOCK_SIZE) { + debug_msg("EMMC\r\n"); + g_uiStartBlkUpdateFW = FDT_OFFSET / EMMC_BLOCK_SIZE; + } else { + g_uiStartBlkUpdateFW = StartNandBlkUpdateFW; + } + + g_is_flash_open = TRUE; + return 0; +} + + + +#if (FDT_SUPPORT) +_THUMB2 static const void *bl_get_fdt_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + int nodeoffset; /* next node offset from libfdt */ + const void *nodep; /* property node pointer */ + + nodeoffset = fdt_path_offset(p_dtb, p_path); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} +#endif + + +_THUMB2 static unsigned char *bl_get_fdt_cfg(const void *p_dtb, MODELEXT_TYPE type) +{ +#if (FDT_SUPPORT) + int len; + const int *nodep; + + UINT8 *p_rt = NULL; + + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_DRAM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get dram fail\r\n"); + return NULL; + } + g_dram_partition.dram_addr = be32_to_cpu(nodep[0]); + g_dram_partition.dram_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_LOADER, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get loader fail\r\n"); + return NULL; + } + g_dram_partition.loader_addr = be32_to_cpu(nodep[0]); + g_dram_partition.loader_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_UBOOT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get uboot fail\r\n"); + return NULL; + } + g_dram_partition.uboot_addr = be32_to_cpu(nodep[0]); + g_dram_partition.uboot_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_FDT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get fdt fail\r\n"); + return NULL; + } + g_dram_partition.fdt_addr = be32_to_cpu(nodep[0]); + g_dram_partition.fdt_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_RTOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.rtos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.rtos_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_NUTTX, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.nuttx_addr = be32_to_cpu(nodep[0]); + g_dram_partition.nuttx_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_CORE2_ENTRY1, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("get CORE2_ENTRY1 dtb fail\r\n"); +// return NULL; + } + + g_dram_partition.core2_entry1_addr = be32_to_cpu(nodep[0]); + g_dram_partition.core2_entry1_size = be32_to_cpu(nodep[1]); + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_CORE2_ENTRY2, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("get CORE2_ENTRY2 dtb fail\r\n"); +// return NULL; + } + g_dram_partition.core2_entry2_addr = be32_to_cpu(nodep[0]); + g_dram_partition.core2_entry2_size = be32_to_cpu(nodep[1]); + + p_rt = (UINT8 *)&g_dram_partition; + + break; + + case MODELEXT_TYPE_BIN_INFO: + nodep = (const int *)bl_get_fdt_property(p_dtb, PATH_MEM_SHMEM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get shmem fail\r\n"); + return NULL; + } + + if (sizeof(SHMINFO) > be32_to_cpu(nodep[1])) { + debug_err("shmem size mismatch\r\n"); + return NULL; + } + + p_rt = (UINT8 *)be32_to_cpu(nodep[0]); + break; + + default: + debug_err_var("not handle type\r\n", type); + return NULL; + } + return p_rt; +#else // NO FDT_SUPPORT + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + return (UINT8 *)&g_dram_partition; + case MODELEXT_TYPE_BIN_INFO: + return (UINT8 *)g_dram_partition.rev_addr; + default: + return NULL; + } +#endif +} + +_THUMB2 int bl_chk_valid_all_in_one(NVTPACK_MEM *p_mem_all_in_one) +{ + NVTPACK_ER er; + NVTPACK_VER ver; + + er = nvtpack_getver(p_mem_all_in_one, &ver); + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + if (ver == NVTPACK_VER_16072017) { + return 0; + } + + return -1; +} + +_THUMB2 int bl_chk_fdt(unsigned int addr, unsigned int size) +{ + DRAM_PARTITION *p_dram_partition = NULL; + + if (fdt_check_header((void *)addr) != 0) { + debug_err("invalid dtb\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)addr, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("invalid dram_partition\r\n"); + return -1; + } + + // check tmp memory (file load) cannot overlap with uboot + // we allow to overlap with linux, root-fs because uboot will reload bin file later + debug_msg_var("tmp_addr", SDRAM_Start_FW); + + if ((addr < p_dram_partition->uboot_addr && addr + size > p_dram_partition->uboot_addr) || + (addr > p_dram_partition->uboot_addr && addr + size < p_dram_partition->uboot_addr + p_dram_partition->uboot_size)) { + debug_err_var("addr", addr); + debug_err_var("size", size); + debug_err("uboot & tmp_addr are overlapped\r\n"); + return -1; + } + return 0; +} + +_THUMB2 int bl_chk_uboot(unsigned int addr, unsigned int size) +{ + #if CHECKSUM_EN + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)addr; + mem.len = size; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + debug_err("uboot check sum fail"); + return -1; + } + #endif + return 0; +} + +_THUMB2 static void bl_core2_reset(void) +{ + UINT32 core_reg; + //cc_startCore(CC_CORE_CA53_CORE2); + //0xF8400000 + core_reg = *(volatile UINT32 *)0xF84000F0; + core_reg &= ~(1<<3); + core_reg &= ~(1<<11); + *(volatile UINT32 *)0xF84000F0 = core_reg; + core_reg |= (1<<2)|(1<<10) | (1<<21); + core_reg |= (1<<17); + *(volatile UINT32 *)0xF84000F0 = core_reg; + +} + +_THUMB2 static int bl_smp_start(unsigned char *p_modelext, UINT32 uboot_entry) +{ + extern char _load_core2_jump_program_start_base[]; + extern char _load_core2_jump_program_end_base[]; + extern char _load_core2_entry_program_start_base[]; + extern char _load_core2_entry_program_end_base[]; + UINT32 code2JumpCodelen, code2EntryCodelen; + + + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_modelext, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_modelext, MODELEXT_TYPE_DRAM_PARTITION); + if (p_bininfo == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + debug_msg_var("fdt", (UINT32)p_modelext); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_modelext; + debug_msg_var("p_bininfo->boot.fdt_addr", p_bininfo->boot.fdt_addr); + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + // clear cc_core1_addr, cc_core2_addr +#if USB_WRITELOADER + if(utl_get_bootsrc() == BOOT_SOURCE_UART) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_UART; + } else if(USB_WRITELOADER || utl_get_bootsrc() == BOOT_SOURCE_USB) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; + } else { + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; + } +#else +// if (card_get_type() == EXT_STORAGE_TYPE_ETH) +// p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +// else if (g_is_recovery_triggered) +// p_bininfo->comm.Resv[0] = BOOT_REASON_RECOVERY_SYS; +// else +#if (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +#else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif +#endif + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + + debug_msg("bl_smp_start\r\n"); + + debug_msg_var("uboot_entry", uboot_entry); + + //check core2_entry1 must at addr 0 + if (p_dram_partition->core2_entry1_addr != CORE2_JUMP_ADDR) { + bl_displayErrMsg("core2entry1 != 0"); + } + + // copy core2 jump code to dram 0x0 + code2JumpCodelen = _load_core2_jump_program_end_base - _load_core2_jump_program_start_base; + utl_memcpy((void *)p_dram_partition->core2_entry1_addr, _load_core2_jump_program_start_base, code2JumpCodelen); + CPUflushWriteCache(p_dram_partition->core2_entry1_addr, code2JumpCodelen); + //CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + debug_msg_var("core2_jump_program", (int)_load_core2_jump_program_start_base); + debug_msg_var("code2JumpCodelen", (int)code2JumpCodelen); + debug_msg_var("core2_entry2_addr", (int)p_dram_partition->core2_entry2_addr); + + // copy core2 entry code to dram specified by fdt + *(volatile UINT32 *)(NVT_CORE2_START) = p_dram_partition->core2_entry2_addr; + code2EntryCodelen = _load_core2_entry_program_end_base - _load_core2_entry_program_start_base; + utl_memcpy((void *)p_dram_partition->core2_entry2_addr, _load_core2_entry_program_start_base, code2EntryCodelen); + CPUflushWriteCache(p_dram_partition->core2_entry2_addr, code2EntryCodelen); + //CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + debug_msg_var("core2_entry_program", (int)_load_core2_entry_program_start_base); + debug_msg_var("code2EntryCodelen", (int)code2EntryCodelen); + *(volatile UINT32 *)0xFE0B9000 = 0; + debug_msg_var("0xFE0B9000=", (int)*(volatile UINT32 *)0xFE0B9000); + + //reset core2 + debug_msg("reset core2\r\n"); + bl_core2_reset(); + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)uboot_entry; + p_func(); + } + + return 0; +} + + + +_THUMB2 static int bl_entry_boot(unsigned char *p_fdt, UINT32 uboot_entry) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + debug_msg_var("fdt", (UINT32)p_fdt); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_fdt; + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + // clear cc_core1_addr, cc_core2_addr +#if USB_WRITELOADER + CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; +#else +#if _TODO + if (card_get_type() == EXT_STORAGE_TYPE_ETH) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; + } else if (g_is_recovery_triggered) { + p_bininfo->comm.Resv[0] = BOOT_REASON_RECOVERY_SYS; + } else { + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; + } +#else +#if (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +#else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif +#endif +#endif + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + + debug_msg_var("jump", uboot_entry); + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)uboot_entry; + p_func(); + } + + return 0; +} + +_THUMB2 int bl_boot_uboot(unsigned char *p_fdt) +{ + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + UINT32 No_CPU; + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->uboot_addr + BIN_INFO_OFFSET_UBOOT); + + if (bl_chk_uboot(p_dram_partition->uboot_addr, p_headinfo->BinLength) != 0) { + return -1; + } + // start cpu2 + if (p_dram_partition->uboot_addr != p_headinfo->CodeEntry) { + debug_err_var("drampat-uboot_addr ", (int)p_dram_partition->uboot_addr); + debug_err_var("bin-uboot_addr ", (int)p_headinfo->CodeEntry); + return -1; + } + // for uboot to indicate this boot is all-in-one fw or non-all-in-one boot from uart or usb + // if boot from uart or usb with non-all-in-one fw, the uboot's ModelextAddr will be zero + p_headinfo->ModelextAddr = p_dram_partition->fdt_addr; + + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + + UINT32 isSMP = (p_headinfo->BinCtrl & 0x00000002); + No_CPU = *(UINT32 *)0xF9C00004; + debug_msg_var("core No.", No_CPU); + No_CPU &= 0x3; + + if (!isSMP || !No_CPU) { + debug_msg("Single core\r\n"); + // init cpu timer + //bl_cpu_timer_init(CPU_TIMER_SETTING); + + // init uart2 + //uart_openSystemUART2(); + + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + // boot u-boot and never return back to loader + } else { + // init cpu timer + bl_cpu_timer_init(global_timer_freq); + + // init uart2 +// uart_openSystemUART2(); + + bl_smp_start(p_fdt, p_headinfo->CodeEntry); + // boot u-boot and never return back to loader + } + + return 0; +} + +_THUMB2 static int bl_update_loader_flag(unsigned char *p_fdt, UINT32 uiLoaderFunc) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + + p_bininfo->boot.LdCtrl2 = 0; + if (uiLoaderFunc & FUNC_UPDATE_FW) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_FW; + } + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_LD; + } + if (uiLoaderFunc & FUNC_RUN_CARD) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_CARD; + } + if (uiLoaderFunc & FUNC_RUN_FLASH) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_FLASH; + } + //CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + debug_msg_var("LdCtrl2", p_bininfo->boot.LdCtrl2); + + return 0; +} + +_THUMB2 int bl_copy_fdt_to_fdt_addr(unsigned char *p_fdt /*IN*/, unsigned char **pp_fdt /*OUT*/) +{ + DRAM_PARTITION *p_dram_partition; + + if (fdt_check_header((const void *)p_fdt) != 0) { + debug_err("invalid dtb\r\n"); + return -1; + } + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("bl_copy_fdt_to_fdt_addr failed.\r\n"); + return -1; + } + + // load fdt to fdt buffer + utl_memcpy((void *)p_dram_partition->fdt_addr, p_fdt, fdt_totalsize(p_fdt)); + *pp_fdt = (unsigned char *)p_dram_partition->fdt_addr; + + //reset shminfo + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + bl_memset(p_bininfo, 0, sizeof(SHMINFO)); + return 0; +} + +_THUMB2 static int bl_load_fdt_from_flash(unsigned char *p_tmp, unsigned int tmp_size, unsigned char **pp_fdt /*OUT*/) +{ + int blk_size = (int)int_strg_obj->flash_getBlockSize(); + // read first block to get dtb size + int er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, blk_size, p_tmp, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash"); + return -1; + } + + int total_size = ALIGN_CEIL(fdt_totalsize(p_tmp), blk_size); + if ((int)tmp_size < total_size) { + debug_err_var("tmp_size too small, require:", fdt_totalsize(p_tmp)); + return -1; + } + + total_size -= blk_size; + if (total_size > 0) { + // read remain to get uboot starting addr on dram and offset in flash + er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW+1, total_size, p_tmp+blk_size, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash"); + return -1; + } + } + + if (bl_chk_fdt((unsigned int)p_tmp, fdt_totalsize(p_tmp)) == 0) { + return bl_copy_fdt_to_fdt_addr(p_tmp, pp_fdt); + } + + return -1; +} + +#if (FDT_SUPPORT) +_THUMB2 static char *bl_get_partition_name(unsigned char *p_fdt) +{ + int i; + const static char *p_name[3] = { + "/nand", + "/nor", + "/mmc@fa600000" + }; + const static char *p_uboot[3] = { + "/nand/partition_uboot", + "/nor/partition_uboot", + "/mmc@fa600000/partition_uboot" + }; + + for (i = 0; i < 3; i++) { + int nodeoffset = fdt_path_offset(p_fdt, p_uboot[i]); + if (nodeoffset > 0) { + return (char *)p_name[i]; + } + } + + debug_err("E:bl_get_partition_name\r\n"); + return NULL; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static char *bl_make_fdt_path(char *root, char *name) +{ + //for fdt to combine the full path of node + static char g_tmp_path[64] = {0}; + g_tmp_path[0] = 0; + strcat(g_tmp_path, "/"); + strcat(g_tmp_path, root); + strcat(g_tmp_path, "/"); + strcat(g_tmp_path, name); + return g_tmp_path; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static int bl_get_partition(unsigned char *p_fdt /*IN*/, char *p_emb_name /*IN*/, EMB_PARTITION *p_emb/*OUT*/, int *p_id) +{ + int len; + const unsigned long long *nodep; + char *p_name = bl_get_partition_name(p_fdt); + char *p_path = NULL; + + if (p_name == NULL) { + return -1; + } + + p_path = bl_make_fdt_path(p_name, p_emb_name); + + // get partition offset and size + nodep = (const unsigned long long *)bl_get_fdt_property(p_fdt, p_path, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("bl_get_partition-1\r\n"); + return -1; + } + + p_emb->PartitionOffset = be64_to_cpu(nodep[0]); + p_emb->PartitionSize = be64_to_cpu(nodep[1]); + + // get partition label + char *p_label_name = (char *)bl_get_fdt_property(p_fdt, p_path, PROPERTY_LABEL, &len); + if (p_label_name == NULL) { + debug_err("bl_get_partition-2\r\n"); + return -1; + } + + // get id + p_path = bl_make_fdt_path(p_name, PATH_NVTPACK_INDEX); + int nodeoffset = fdt_path_offset(p_fdt, p_path); + + for (nodeoffset = fdt_first_subnode(p_fdt, nodeoffset); + (nodeoffset >= 0); + (nodeoffset = fdt_next_subnode(p_fdt, nodeoffset))) { + const struct fdt_property *prop; + + if (!(prop = fdt_get_property(p_fdt, nodeoffset, PROPERTY_PARTITION_NAME, &len))) { + break; + } + const char *p_id_name = fdt_get_name(p_fdt, nodeoffset, &len); + + if (strcmp(p_label_name, (char *)prop->data) == 0) { + *p_id = atoi(p_id_name + strlen("id")); + return 0; + } + } + + return -1; +} +#endif + +_THUMB2 static void *bl_get_uboot_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_UBOOT, &g_emb_uboot, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_UBOOT; +#endif + g_emb_uboot.EmbType = EMBTYPE_UBOOT; + return &g_emb_uboot; +} + +_THUMB2 static int bl_load_fdt_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char **pp_fdt /*OUT*/) +{ + NVTPACK_ER er; + NVTPACK_MEM emb_fdt; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + debug_err("packbin verify failed.\r\n"); + return -1; + } + + np_get_input.id = 1; // fdt must always put in partition[1] + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt); + + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } else if (er == NVTPACK_ER_SUCCESS) { + debug_msg_var("fdt addr", (int)emb_fdt.p_data); + debug_msg_var("fdt size", (int)emb_fdt.len); + if (bl_chk_fdt((unsigned int)emb_fdt.p_data, emb_fdt.len) == 0) { + return bl_copy_fdt_to_fdt_addr(emb_fdt.p_data, pp_fdt); + } + } + return -1; +} + +_THUMB2 static void *bl_get_rtos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_RTOS, &g_emb_rtos, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_RTOS; +#endif + g_emb_rtos.EmbType = EMBTYPE_RTOS; + return &g_emb_rtos; +} + +_THUMB2 static void *bl_get_loader_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_LOADER, &g_emb_loader, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_LOADER; +#endif + g_emb_loader.EmbType = EMBTYPE_LOADER; + return &g_emb_loader; +} + +// return decompress_fw_size +_THUMB2 static unsigned int bl_decompress_rtos(UINT32 compress_addr, UINT32 compress_size, UINT32 fw_base_addr) +{ + UINT32 decoded_size; + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)compress_addr; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + + size_comp_le = (compress_size < size_comp_le) ? compress_size : size_comp_le; + decoded_size = LZ_Uncompress((UINT8 *)compress_addr + sizeof(NVTPACK_BFC_HDR), (UINT8 *)fw_base_addr, size_comp_le); + + //because some padding bytes are decoded, we must return real rtos size + return (decoded_size < size_uncomp_le) ? decoded_size : size_uncomp_le; +} + +static _THUMB2 int bl_load_uboot_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int uboot_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // load 1st block of u-boot to tmp dram (to detect compressed u-boot) + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, ALIGN_CEIL(BIN_INFO_OFFSET_UBOOT + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_uboot_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read uboot failed + } + + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + debug_msg_var("uboot_size", p_dram_partition->uboot_size); +#if 0 + if(0){ +#else + if(is_secure_enable() == 0) { +#endif + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) + { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(size_comp_le, blk_size),p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash_comp,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + /* + * OpenIPC: algorithm 11, LZMA, through the decoder + * Compress.a has for the bound U-Boot + * (bl_boot_bind_uboot()), as NA51089's loader takes it + * to its mask ROM + */ + if ((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF) == 11) { + extern char _lzma_tmp_start[]; + extern char _lzma_tmp_end[]; + + if (invertEndian(pBfc->uiSizeUnComp) > p_dram_partition->uboot_size) { + debug_err_var("uboot_size", invertEndian(pBfc->uiSizeUnComp)); + return -1; + } + if (lzma_inflate(p_tmp + sizeof(NVTPACK_BFC_HDR), size_comp_le, + (UINT8 *)p_dram_partition->uboot_addr, + invertEndian(pBfc->uiSizeUnComp), + (UINT8 *)_lzma_tmp_start, + (UINT32)(_lzma_tmp_end - _lzma_tmp_start)) < 0) { + debug_err("lzma\r\n"); + return -1; + } + } else + LZ_Uncompress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->uboot_addr, size_comp_le); + } + else + { + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + } + else + { +#if (SECURE_DECRYPT_UBOOT) + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); // describe uncompressed u-boot + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + unsigned int plaintext_size=0; + if((er =do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size))!= 0) + { + debug_err("aes fail\r\n"); + return er; + } +#else + debug_msg("plase enable SECURE_DECRYPT_UBOOT config\r\n"); + return -1; +#endif + } + return 0; +} + +_THUMB2 static int bl_load_rtos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int rtos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_rtos = bl_get_rtos_partition(p_fdt, &rtos_partition_id); + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + if (p_emb_partition_rtos == NULL) { + debug_err("null p_emb_partition_rtos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // load 1st block of u-boot to tmp dram (to detect compressed u-boot) + unsigned int bininfo_preload_size = ALIGN_CEIL(BIN_INFO_OFFSET_RTOS + sizeof(HEADINFO), blk_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, bininfo_preload_size, p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read rtos failed + } + + // flow to handle compressed u-boot and uncompressed one. + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + // load rtos bin to dram partiton location + //debug_msg_var("rtos_addr", p_dram_partition->rtos_addr); + //debug_msg_var("rtos_size", p_dram_partition->rtos_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) + { + /* lzma compressed image*/ + debug_msg("lzma, use uboot\r\n"); + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, ALIGN_CEIL(size_comp_le, blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_comp,er=", er); // read bfc-rtos failed + bl_displayErrMsg(RWErrorMsg); + } + LZ_Uncompress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->rtos_addr, size_comp_le); + } + } else { + BININFO *p_bininfo = (BININFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); // describe uncompressed u-boot + if (p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN) { + // copy bininfo_preload to rtos_addr + bl_memcpy((UINT8 *)p_dram_partition->rtos_addr, p_tmp, bininfo_preload_size); + // preload some to get part-1 size for partial load and partial compressed load + UINT32 preload_size = ALIGN_CEIL(FW_PART1_SIZE_OFFSET, blk_size) - bininfo_preload_size; + + if (preload_size!= 0) { + er = int_strg_obj->flash_readSectors( + (p_emb_partition_rtos->PartitionOffset + bininfo_preload_size) / blk_size, + preload_size, + (UINT8 *)(p_dram_partition->rtos_addr + bininfo_preload_size), NAND_RW_FIRMWARE + ); + + if (er < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + UINT32 part1_size = *(UINT32 *)(p_dram_partition->rtos_addr + FW_PART1_SIZE_OFFSET); + debug_msg_var("part1_size",part1_size); + part1_size = ALIGN_CEIL(part1_size, blk_size); + //debug_msg_var("part1_size_aligned",part1_size); + if ((er =int_strg_obj-> flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, part1_size, (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = part1_size; + } else { + // full load + debug_msg_var("rtos_size", p_bininfo->head.BinLength); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset /blk_size, ALIGN_CEIL(p_bininfo->head.BinLength, blk_size), (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = p_bininfo->head.BinLength; + } + } + return 0; +} +_THUMB2 static void bl_update_uItron_headInfo(UINT32 fw_base_addr, DRAM_PARTITION *p_dram_partition) +{ + HEADINFO *pHeadInfo; + + pHeadInfo = (HEADINFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + if (p_dram_partition) { + pHeadInfo->ModelextAddr = p_dram_partition->fdt_addr; + } else { + pHeadInfo->ModelextAddr = 0; + } +} + +_THUMB2 static int bl_update_loader_bininfo(unsigned char *p_fdt, unsigned int ld_flag, unsigned int rtos_loaded_size) +{ + unsigned int ver; + unsigned int *p_param; + BOOTINFO *p_ld; + int id; + + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + EMB_PARTITION *p_emb_partition = bl_get_loader_partition(p_fdt, &id); + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + BININFO *p_bininfo = (BININFO *)(p_dram_partition->rtos_addr + BIN_INFO_OFFSET_RTOS); + + if (p_emb_partition == NULL) { + return -1; + } + + p_ld = &p_shminfo->boot; + + utl_memset(p_ld->LdInfo_1, 0, sizeof(p_ld->LdInfo_1)); + utl_memcpy(p_ld->LdInfo_1, "LD_NVT", 6); + + ver = (((LoaderInternalInfo[1] >> 28) & 0xF) << 24) | + (((LoaderInternalInfo[1] >> 24) & 0xF) << 16) | + ((LoaderInternalInfo[1] >> 16) & 0xFF); + + if (g_uiVersion == 0) { + g_uiVersion = ver; + } + + utl_memcpy(&p_ld->LdInfo_1[8], &g_uiVersion, sizeof(g_uiVersion)); + p_ld->LdCtrl2 = ld_flag; + if (!(p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN)) { + // LdLoadSize updated on uboot or bl_load_rtos_from_flash(), if BOOT_FLAG_PARTLOAD_EN + p_ld->LdLoadSize = rtos_loaded_size; + } + p_ld->LdLoadTime = timer_getSysTick();//timer_getLdrElapse(); + p_ld->LdResvSize = p_emb_partition->PartitionSize; + p_ld->FWResvSize = 0; //unused + + p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_ld->LdPackage = p_param[3] & 0xFFFF; + p_ld->LdStorage = (p_param[3] >> 16) & 0xFF; + return 0; +} + +_THUMB2 static int bl_load_uboot_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_uboot; + int uboot_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)uboot_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_uboot); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + debug_msg_var("uboot_size", p_dram_partition->uboot_size); +# if 0 + if(0) { +#else + if(is_secure_enable() == 0) { +#endif + if (bl_chk_uboot((unsigned int)mem_uboot.p_data, mem_uboot.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_uboot.p_data + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_uboot.p_data; // describe compressed u-boot + + // load uboot bin to dram partiton location + //debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + //debug_msg_var("uboot_size", p_dram_partition->uboot_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Uncompress(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->uboot_addr, size_comp_le); + } else { + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, p_headinfo->BinLength); + } + } else { +#if (SECURE_DECRYPT_UBOOT) + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, mem_uboot.len); + unsigned int plaintext_size =0; + + if((er = do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size))!= 0 ) + { + debug_err("aes fail\r\n"); + return er; + } + if (bl_chk_uboot((unsigned int)p_dram_partition->uboot_addr, plaintext_size) != 0) { + return -1; + } +#else + debug_msg("please enable SECURE_DECRYPT_UBOOT\r\n"); + return -1; +#endif + } + + return 0; +} + +_THUMB2 static unsigned int bl_load_rtos_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char **pp_fdt /*OUT*/) +{ + UINT32 uItron_fw_addr= 0; + NVTPACK_ER er; + NVTPACK_MEM emb_fdt; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + HEADINFO *p_headinfo; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + debug_err("packbin verify failed.\r\n"); + return 0; + } + + np_get_input.id = 5; // rtos must always put in partition[5] for now + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt);//&np_get_input, &emb_fdt); + + if (er == NVTPACK_ER_NOT_FOUND) { + return 0; + } else if (er == NVTPACK_ER_SUCCESS) { + debug_msg("get rtos partition ok\r\n"); + + p_headinfo = (HEADINFO *)(emb_fdt.p_data + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry; + + utl_memcpy((void *)uItron_fw_addr, emb_fdt.p_data, emb_fdt.len); + //CPUflushWriteCache(uItron_fw_addr, emb_fdt.len); + } + debug_msg_var("uItron_fw_addr=", uItron_fw_addr); + return uItron_fw_addr; +} + +#if !(USB_WRITELOADER || UART_UPDATE) +_THUMB2 static int bl_load_rtos_from_non_nvtpack(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + HEADINFO *p_headinfo = (HEADINFO *)(src_addr + BIN_INFO_OFFSET_RTOS); + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + // to avoid rtos_addr is overlapped by src_addr, we need extract some bits to get real rtos addr. + // compressed firmware + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr + SIZE_PRELOAD); + p_headinfo = (HEADINFO *)(src_addr + SIZE_PRELOAD + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = fat_read_rootfile((UINT8 *)src_addr, compress_size); + } else { + return -1; + } + } else if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + // uncompressed firmware + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + + src_size = fat_read_rootfile((UINT8 *)src_addr, uncompress_size); + src_addr = uncompress_addr; + src_size = uncompress_size; + debug_msg("uncompressed t.bin\r\n"); +#if (DRAM_RANGE_SCAN_EN == ENABLE) + } else if (utl_is_sram_fw(src_addr) == TRUE) { + debug_msg("detected as SRAM fw\r\n"); + src_size = fat_read_rootfile((UINT8 *)src_addr, FAT_READ_TOTAL_FILE_LENGTH); +#endif + } else { + return -1; + } + + *p_dst_addr = src_addr; + *p_dst_size = src_size; + return 0; +} +#endif + +#if !UPDATE_EMU_CODE && !REMOVED_FLASH +_THUMB2 static unsigned int bl_process_flash_boot(unsigned char *p_tmp, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // load fdt + er = bl_load_fdt_from_flash(p_tmp, SDRAM_Start_FW, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition->rtos_addr == 0) { + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { + // load rtos + er = bl_load_rtos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load rtos failed\r\n"); + } + } + + // update compressed rtos information + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((unsigned char *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + *p_comp_addr = p_bininfo->comm.Resv[3]; // COMM_UITRON_COMP_ADDR + *p_comp_size = p_bininfo->comm.Resv[4]; // COMM_UITRON_COMP_LEN + + *pOut_dram_partition = p_dram_partition; + return p_dram_partition->rtos_addr; +} +#endif + +static _THUMB2 int bl_process_update_loader(unsigned int loader_addr, unsigned int loader_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card + if(is_data_area_encrypted() == 0){ + bl_checkLoader(loader_addr, loader_size); + } + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // Program loader + if (int_strg_obj->flash_writeSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)loader_addr, NAND_RW_LOADER) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = loader_addr + loader_size; + if (int_strg_obj->flash_readSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)reload_addr, NAND_RW_LOADER) < 0) { + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)loader_addr, (void *)reload_addr, loader_size) != 0) { + bl_displayErrMsg("verify fail\r\n"); + } + return 0; +} + + +// return uItron_fw_addr +unsigned _THUMB2 int bl_process_all_in_one(UINT32 uiFwBuf, UINT32 uiFwBufSize, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + + // load fdt + er = bl_load_fdt_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, &p_fdt); + if (er == -2) { // try to load from nand + debug_msg("fdt from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + er = bl_load_fdt_from_flash(p_tmp, 0x2000000, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + if (uiLoaderFunc & FUNC_UPDATE_FW) { + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + p_bininfo->comm.Resv[5] = uiFwBuf; // COMM_FW_UPD_ADDR + p_bininfo->comm.Resv[6] = uiFwBufSize; // COMM_FW_UPD_LEN + debug_msg_var("upd_src_addr=", uiFwBuf); + debug_msg_var("upd_src_size=", uiFwBufSize); + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + //check loader addr is matched with loader self. + extern char _loader_exec_compres_start[]; + if (p_dram_partition->loader_addr != (UINT32)_loader_exec_compres_start) { + debug_msg_var("p_dram_partition->loader_addr", p_dram_partition->loader_addr); + debug_msg_var("_loader_exec_compres_start", (UINT32)_loader_exec_compres_start); + bl_displayErrMsg("loader addr is not match."); + } + //when rtos boot from flash, the boot from loader directly, + //but when rtos need to burn image, the uboot is still required. + //so, any one need to burn image, uboot is always needed to boot. + if ((uiLoaderFunc & FUNC_UPDATE_FW) || p_dram_partition->rtos_addr == 0) { + // always use uboot to handle all-in-one bin + if (p_dram_partition->nuttx_size == 0) { + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er == -2) { // try to load from nand + debug_msg("uboot from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + } + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { +#if _TODO + // load nuttx + er = bl_load_nuttx_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load nuttx failed\r\n"); + } + er = bl_boot_nuttx((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot nuttx failed\r\n"); + } +#else + bl_displayErrMsg("not support nuttx\r\n"); +#endif + } + return er; + } else { + // update rtos information + // the following is for uncompressed-rtos only, others needing uboot + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + *p_comp_addr = p_bininfo->comm.Resv[3]; // COMM_UITRON_COMP_ADDR + *p_comp_size = p_bininfo->comm.Resv[4]; // COMM_UITRON_COMP_LEN + + *pOut_dram_partition = p_dram_partition; + return bl_load_rtos_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, &p_fdt); + } +} + + +/** + main flow code + + If there is Calibration Firmware code store in NAND, running flow as follow + O's work flow + + @return fw base addr +*/ + + +_THUMB2 UINT32 bl_mainFlow(void) +{ + UINT32 uiUpdateFileLen = 0; + UINT32 uiLoaderFunc = 0; + UINT32 uiLoaderSize = 64 * 1024; // pre-assume 32KB, actual size is parsed from loader + UINT32 uiFwBaseAddr = SDRAM_Start_FW; // FW base address + DRAM_PARTITION *p_dram_partition = NULL; + + // BaseOfStack is initialized at doRemapLZ.s + UINT32 uiheapBufferAddr = (UINT32)_loader_heap_base; + UINT32 uiTmpBufferAddr = uiheapBufferAddr + FAT_HEAP_BUFFER_SIZE; + UINT32 uiUpdateBootloaderBufAddr = uiTmpBufferAddr + 0x4000; + UINT32 uiUpdateMainBinBufAddr = SDRAM_Start_FW; + +#if !(USB_WRITELOADER || UART_UPDATE) + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; +#endif + + serial_init(); + debug_msg((char *)LOADER_START_STR); + UTL_setDrvTmpBufferAddress(uiTmpBufferAddr); + + prj_main(); + +#if !(USB_WRITELOADER) + set_usb_suspend(); +#endif + + if(utl_get_bootsrc() == BOOT_SOURCE_UART) + { +#if UART_UPDATE + debug_msg("Boot from UART ...\r\n"); + bl_uart();//never returned. +#else + bl_displayErrMsg("UART_UPDATE must enable on loader\r\n"); +#endif + } + + if(USB_WRITELOADER || utl_get_bootsrc() == BOOT_SOURCE_USB) + { +#if USB_WRITELOADER + debug_msg("Boot from USB ...\r\n"); + bl_usb(); //never returned. +#else + bl_displayErrMsg("USB_WRITELOADER must enable on loader\r\n"); +#endif + } + + + +#if !(USB_WRITELOADER || UART_UPDATE) + if (card_open() == TRUE && fat_initFAT(uiheapBufferAddr, FAT_HEAP_BUFFER_SIZE) == TRUE) { + if (fat_open_rootfile(UPDATE_LOADER_NAME) == TRUE) { + // Read byte count specified in file directory entry + fat_read_rootfile((UINT8 *)uiUpdateBootloaderBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_UPDATE_LOADER; + uiLoaderSize = *((UINT32 *)(uiUpdateBootloaderBufAddr + 0x24)); + } + + if (fat_open_rootfile(UPDATE_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + } else { + // only rtos + debug_msg("not all-in-one, force behavior as T bin.\r\n"); + adjusted_addr = 0; + adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) == 0) { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } else { + bl_displayErrMsg("invalid firmware"); + } +#if UPDATE_EMU_CODE + uiLoaderFunc |= FUNC_UPDATE_FW; +#else + uiLoaderFunc |= FUNC_RUN_CARD; +#endif + + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + } + // Run FW has lower priority + else if (fat_open_rootfile(RUN_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + } else { + // Read rtos + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) != 0) { + bl_displayErrMsg("invalid firmware"); + } else { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } + uiLoaderFunc |= FUNC_RUN_CARD; + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_CARD; + } + card_close(); + } else { + debug_msg("card open fail\r\n"); +// while (1); + } +#endif + + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + bl_process_update_loader(uiUpdateBootloaderBufAddr, uiLoaderSize); + } + // Run FW + UINT32 comp_addr = 0; + UINT32 comp_size = 0; + if (uiLoaderFunc & (FUNC_RUN_CARD | FUNC_UPDATE_FW)) { + debug_msg("RC\r\n"); + NVTPACK_MEM mem_in ; + int chk_valid_all_in_one; +#if (DRAM_RANGE_SCAN_EN == ENABLE) + // First word is code entry point address, once if entry address is 0xC000XXXX + // represent code is running on sram. + debug_msg("Check SRAM fw\r\n"); + if (bl_checkDramScanFW(uiUpdateMainBinBufAddr) == TRUE) { + + debug_msg("This fw is on SRAM\r\n"); + // Enable sram usage + SETREG32(0xF0900128, 0x00000002); + SETREG32(0xF0800128, 0x00000006); + SETREG32(0xF0020060, 0x00030002); + + debug_msg(Dec2HexStr(*((UINT32 *)SRAM_Start_FW))); + debug_msg("before jump\r\n"); +// while (b_debug_go == FALSE); + load_dram_scan(uiUpdateMainBinBufAddr, uiUpdateFileLen); + return *((UINT32 *)SRAM_Start_FW); + } +#endif + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + chk_valid_all_in_one = bl_chk_valid_all_in_one(&mem_in); + if (chk_valid_all_in_one == 0) { + // all-in-one flow + // File len got from fat_read_rootfile() may exceed actual file size. + // In such condition, we should use info in NVTPACK_FW_HDR2 + if (((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize < uiUpdateFileLen) { + uiUpdateFileLen = ((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize; + mem_in.len = uiUpdateFileLen; + } +//#if (REMOVED_FLASH == ENABLE) +// bl_displayErrMsg("cannot process all-in-one fw"); +//#else + uiFwBaseAddr = bl_process_all_in_one(uiUpdateMainBinBufAddr, uiUpdateFileLen, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); +//#endif + } else { +//#if UPDATE_EMU_CODE +// bl_process_update_emu_firmware(uiUpdateMainBinBufAddr, uiUpdateFileLen); +//#else + bl_displayErrMsg("cannot process non-all-in-one fw"); +//#endif + } +// uiFwBaseAddr = bl_process_rtos_only(uiUpdateMainBinBufAddr, mem_in.len, uiLoaderFunc, &comp_addr, &comp_size); + + + // here uiFwBaseAddr is ready to use. + if (comp_addr == 0) { + HEADINFO *p_headinfo = (HEADINFO *)(uiFwBaseAddr + BIN_INFO_OFFSET_RTOS); + debug_msg("Nrml\r\n"); + if (chk_valid_all_in_one == 0) { + uiUpdateFileLen = p_headinfo->BinLength; + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + // uiUpdateFileLen is already set when file is loaded + } + } else { + debug_msg("Fcompress\r\n"); + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + debug_msg_var("uiUpdateFileLen", uiUpdateFileLen); + //boot from flash or update fw is no need to check sanity because of ecc, turn on it just for debug + if (uiLoaderFunc & FUNC_RUN_CARD) { + bl_checkFW(uiUpdateMainBinBufAddr, uiUpdateFileLen); + } + if (chk_valid_all_in_one == 0) { + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); + } else { + debug_msg_var("fw load addr", uiUpdateMainBinBufAddr); + bl_update_uItron_headInfo(uiUpdateMainBinBufAddr, p_dram_partition); + } + } else { //boot from flash +#if (REMOVED_FLASH == DISABLE) +#if UPDATE_EMU_CODE +// UINT32 uiNandBlkSize; + // open flash +/* + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + debug_msg("RFlash\r\n"); + if (flash_readSectors(g_uiStartBlkUpdateFW, g_uiNandBlkSize, (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiUpdateFileLen = *(volatile UINT32 *)(SDRAM_Start_FW + 0x168); + + if (flash_readSectors(g_uiStartBlkUpdateFW + 1, uiUpdateFileLen - g_uiNandBlkSize, (UINT8 *)(SDRAM_Start_FW + g_uiNandBlkSize), NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiFwBaseAddr = bl_process_rtos_only(SDRAM_Start_FW, uiUpdateFileLen, uiLoaderFunc, &comp_addr, &comp_size); + bl_checkFW(SDRAM_Start_FW, uiUpdateFileLen); + uiUpdateMainBinBufAddr = SDRAM_Start_FW; + if (comp_addr == 0) { + debug_msg("Nrml\r\n"); + } else { + debug_msg("Fcompress not support\r\n"); + } +*/ +#else + uiFwBaseAddr = bl_process_flash_boot((UINT8 *)SDRAM_Start_FW, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); + if (comp_addr == 0) { + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + // no need to bl_checkFW, because check sanity in flash_read + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); +#endif +#endif + } + + if (p_dram_partition) { + bl_update_loader_bininfo((unsigned char *)p_dram_partition->fdt_addr, uiLoaderFunc, uiUpdateFileLen); + } + +//#if UPDATE_EMU_CODE +// debug_msg_var("emu fw len", uiUpdateFileLen); +//#endif + g_rtos_load_addr = uiUpdateMainBinBufAddr; + g_rtos_target_addr = uiFwBaseAddr; + g_rtos_size = uiUpdateFileLen; + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + debug_msg_var("rtos start", uiFwBaseAddr); + return uiFwBaseAddr; + + + + + +/* + uiUpdateFileLen = mmc_loader(uiFwBaseAddr, RUN_FW_NAME, UPDATE_FW_NAME); + + if(uiUpdateFileLen > 0) { + uiLoaderFunc = FUNC_RUN_CARD; +#if CHECKSUM_EN + NVTPACK_MEM mem_in; + mem_in.p_data = (void *)uiFwBaseAddr; + mem_in.len = uiUpdateFileLen; + + debug_msg("checksum "); + if (nvtpack_calc_nvt_sum(&mem_in)!= 0) { + bl_displayErrMsg(FWErrorMsg); + } + debug_msg("done\r\n"); +#endif + } else { + + } +*/ + //return bl_process_all_in_one(uiFwBaseAddr, uiUpdateFileLen, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); +} + +_THUMB2 void loader_setUpdateFwName(char *fileName) +{ + strncpy((char *)UPDATE_FW_NAME, fileName, sizeof(UPDATE_FW_NAME)); +} + +_THUMB2 void loader_setUpdateLdrName(char *fileName) +{ + strncpy((char *)UPDATE_LOADER_NAME, fileName, sizeof(UPDATE_LOADER_NAME)); +} + +_THUMB2 void loader_setRunFwName(char *fileName) +{ + strncpy((char *)RUN_FW_NAME, fileName, sizeof(RUN_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryFwName(char *fileName) +{ + strncpy((char *)RECOVERY_FW_NAME, fileName, sizeof(RECOVERY_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryPartitionID(UINT32 partition_id) +{ + g_uiPartitionID = partition_id; +} + +_THUMB2 void loader_setVersion(UINT32 version) +{ + g_uiVersion = version; +} +_THUMB2 void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj) +{ + gStorageIntType = type; + int_strg_obj = strg_obj; +} diff --git a/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h new file mode 100644 index 000000000000..f6e05b459d32 --- /dev/null +++ b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h @@ -0,0 +1,282 @@ +/** + @file bl_func.h + @brief Header file for main function + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ +#ifndef _BL_MAIN_H +#define _BL_MAIN_H + +#include "main.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "loader.h" +//------------------------------------------------------------------------------ +// Compiler option +// +// These compiler option are define in MakeConfig.txt +//!!!!!!!!!!!!!!!!!!! DO NOT MODIFY COMPILER OPTION HERE !!!!!!!!!!!!!!!!!!!! +//------------------------------------------------------------------------------ +#ifndef SECURE_DECRYPT_UBOOT +#define SECURE_DECRYPT_UBOOT 0 //Decrypt uboot sample code +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt + +#if (SECURE_DECRYPT_UBOOT) +#define SECURE_OFFSET 1024 //Decrypt uboot from which offset +#endif + +// Define LED_FUNCTION == ENABLE will enable LED on/off in boot loader +#define LED_FUNCTION ENABLE//DISABLE + +// FW checking method, support checksum & CRC now +//#define FW_CHECK_NOCHECK 0 +//#define FW_CHECK_CHECKSUM 1 +//#define FW_CHECK_CRC 2 +#ifndef FW_CHECK_METHOD +#define FW_CHECK_METHOD FW_CHECK_CHECKSUM +#endif + +///#define FW_CHECK_INSTRUCTION0 0xE59FF018 + +// Optional pseudo string for checksum & CRC checking +#define FW_CHECK_PSEUDO_STR_EN DISABLE +#if (FW_CHECK_PSEUDO_STR_EN == ENABLE) + // Must sync to MakeConfig.txt + #define FW_CHECK_PSEUDO_STR "DSC_FW" +#endif + +// Determine if need to support compressable main code +#ifndef _MAINCODE_COMPRESS_ +#define _MAINCODE_COMPRESS_ 0 +#endif + +#ifndef STORAGEINT_SPI +#define STORAGEINT_SPI 0 +#endif + +#define FW_EXCEED_16MB_TEST DISABLE + +//------------------------------------------------------------------------------ +// Global definition +//------------------------------------------------------------------------------ +#define LOADER_CODE_SIZE 0x8000 // Reserve 32 KB + +#define RESERVED_DATA_SIZE 0x4000 // Fixed to 16 KB + +#define SDRAM_Start_FW 0x02000000 // DRAM uITRON starting address + +#define SRAM_Start_FW 0xF07c0000 // SRAM FW starting address + +#define SRAM_TAG 0xF0000000 // SRAM tag + +#define CORE2_JUMP_ADDR 0x00000000 // Core2 entry code should put on 0, because when core2 reset is released, core2 will jump to 0 and run + +#define CPU_TIMER_SETTING 0x00B71B00 //0x016E3600 + +#define _BOARD_IPC_ADDR_ 0x00002000 // must be the same with BOARD_IPC_ADDR on ModelConfig. + + + +#define UPDATE_CFG_BUFADDR 0x06000000 +#define UPDATE_CFG_TAGCODE 0xABCD0043 +#define UPDATE_CFG_LOADER_OFS 0x00 +#define UPDATE_CFG_FW_OFS 0x10 + +#define UPDATE_CFG_ITEM_LD 0xABCD0001 +#define UPDATE_CFG_ITEM_FW 0xABCD0002 + +#define UPDATE_CFG_TAG 0 +#define UPDATE_CFG_ITEM 1 +#define UPDATE_CFG_ADDR 2 +#define UPDATE_CFG_LEN 3 + +#define USB_RESULT_LOADER_INVALID_FW_INVALID (0) +#define USB_RESULT_LOADER_INVALID_FW_OK (1) +#define USB_RESULT_LOADER_INVALIE_FW_FAIL (2) +#define USB_RESULT_LOADER_OK_FW_INVALID (3) +#define USB_RESULT_LOADER_FAIL_FW_INVALID (4) +#define USB_RESULT_LOADER_OK_FW_OK (5) +#define USB_RESULT_LOADER_FAIL_FW_OK (6) +#define USB_RESULT_LOADER_OK_FW_FAIL (7) +#define USB_RESULT_LOADER_FAIL_FW_FAIL (8) +#define USB_RESULT_OTHER (9) + +// Loader checking +#define LOADER_TAG_OFFSET 0x30 +#define LOADER_TAG_VALUE 0xAA55 + +//#NT#2011/06/30#Steven Wang -begin +//#NT#Checksum offset +///#define CHECKSUM_OFFSET 0x1C +#define CHECKSUM_TAG 0xAA55 +//#NT#2011/06/30#Steven Wang -end + +// Config table tag value (for USB flow) +#define CFG_TABLE_TAG (0x4B54564E) // 'N' 'V' 'T' 'K' + +#define COMPRESS_TAG_VALUE (0x314C4342) // use to distinguish full compressed main code + +#define SPI_FLASH_IDENTIFY (0x46495053) //'S''P''I''F' + +#define BOOTVER_SET(OutMaj,OutMin,InnMaj,InnMin) (((OutMaj)<<24)|((OutMin)<<16)|((InnMaj)<<8)|((InnMin))) + +#define BOOTVER_GETOuterMajor(Ver) (((Ver)&0xFF000000)>>24) +#define BOOTVER_GETOuterMinor(Ver) (((Ver)&0x00FF0000)>>16) +#define BOOTVER_GETInnerMajor(Ver) (((Ver)&0x0000FF00)>>8) +#define BOOTVER_GETInnerMinor(Ver) (((Ver)&0x000000FF)) + +// Define loader version (_LDR_VER_) in MakeConfig.txt +#define BOOTLOADER_OUTERMAJOR (((_LDR_VER_)&0xFF000000)>>24) +#define BOOTLOADER_OUTERMINOR (((_LDR_VER_)&0x00FF0000)>>16) +#define BOOTLOADER_INNERMAJOR (((_LDR_VER_)&0x0000FF00)>>8) +#define BOOTLOADER_INNERMINOR (((_LDR_VER_)&0x000000FF)) + +// Binary tag value +#define FW_BINARY_TAG 0xAA55544E // 'N' 'T' 0x55 0xAA + +// CAL FW size exit tag +#define CAL_SIZE_TAG 0x5A534C43 // CLSZ +// FW size exit tag +#define FW_SIZE_TAG 0x5A535746 // FWSZ + +// Reserved area FW size offset +#define RESERVED_AREA_FW_SIZE_OFFSET 0x00 +// Reserved area CAL size offset +#define RESERVED_AREA_CAL_SIZE_OFFSET 0x04 +// Reserved area FW size tag offset +#define RESERVED_AREA_FW_TAG_OFFSET 0x08 +// Reserved area CAL size tag offset +#define RESERVED_AREA_CAL_TAG_OFFSET 0x0C + +// Operation of boot loader +#define FUNC_UPDATE_FW 0x01 // Read FW code from card and update to NAND and run +#define FUNC_UPDATE_LOADER 0x02 // Read boot loader code from card and update to NAND +#define FUNC_RUN_CARD 0x04 // Read FW code from card and run +#define FUNC_RUN_FLASH 0x08 // Read FW code from internal flash and run +#define FUNC_UPDATE_CAL 0X10 // Update CAL data +#define FUNC_RUN_WRBIN 0X20 // RUN wrkey data +#define FUNC_RUN_UBOOT 0X40 // Read Uboot from card and run +#define FUNC_UPDATE_FW_DONE 0x0100 // update f/w to NAND/SPI done + +// API to turn on / off LED +#if (LED_FUNCTION == ENABLE) +// Red LED (DGPIO 6) +// Green LED (DGPIO 9) +#define TurnOff_RedLED() OUTREG32(CPE_GPIO_BASE + 0x4C, 0x00000040) +#define TurnOn_RedLED() OUTREG32(CPE_GPIO_BASE + 0x38, 0x00000040) +#define TurnOff_GreenLED() OUTREG32(CPE_GPIO_BASE + 0x4C, 0x00000200) +#define TurnOn_GreenLED() OUTREG32(CPE_GPIO_BASE + 0x38, 0x00000200) +#else +#define TurnOff_RedLED() +#define TurnOn_RedLED() +#define TurnOff_GreenLED() +#define TurnOn_GreenLED() +#endif + +//Configure build as USB write loader @ ModelConfig_EMU_EVB.txt +//UART & USB can enable at the same time. +#if (STORAGE_EXT_TYPE == STORAGE_EXT_USB) || (STORAGE_EXT_TYPE == STORAGE_EXT_UART) +#define USB_WRITELOADER ENABLE +#define UART_UPDATE ENABLE +#else +#define USB_WRITELOADER DISABLE +#define UART_UPDATE DISABLE +#endif + + + +#define UPDATE_EMU_CODE DISABLE +#define REMOVED_FLASH DISABLE +#define FDT_SUPPORT ENABLE + +#define EMUKIT 0 +#define DEMOKIT 0x1800000 +#define RESUME_ADDR DEMOKIT + +//#NT#2018/03/07#Ben Wang -begin +//#NT#Support EMMC boot flow +#define EMMC_BLOCK_SIZE 0x200 +#define FDT_OFFSET 0x40000 +//#NT#2018/03/07#Ben Wang -end + +#if (STORAGEINT_SPI == 1) + #define StartNandBlkUpdateLoader 0 + #define StartNandBlkReserved 0 + //#NT#2012/12/17#HH Chuang -begin + //#NT#Sync spi erase unit to best access size of f/w storage object + #define StartNandBlkUpdateFW 16 + //#NT#2012/12/17#HH Chuang -end +#else + #define StartNandBlkUpdateLoader 0 + #define StartNandBlkUpdateFW 2 +#endif + +#if (FW_CHECK_METHOD == FW_CHECK_CRC) +static UINT32 g_uiCRCTable[256]; +#endif + +// Card detect GPIO offset +#define DGPIO_CARD_DETECT (0 | GPIO_IS_DGPIO) + + +#define CHECK_CARD_EXIST (ENABLE) +#if (CHECK_CARD_EXIST == ENABLE) +// MC16 default is config as input and pull up +#define bl_checkCardExist() (gpio_getPin(DGPIO_CARD_DETECT) == 0 ? TRUE : FALSE) +#else +#define bl_checkCardExist() TRUE +#endif + +/** + @name Assert macros +*/ +//@{ +#define ASSERT_CONCAT_(a, b) a##b +#define ASSERT_CONCAT(a, b) ASSERT_CONCAT_(a, b) + +#if defined(__COUNTER__) + +#define STATIC_ASSERT(expr) \ +enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __COUNTER__) = 1/(expr) } + +#else + +// This might cause compile error when writing STATIC_ASSERT at the same line +// in two (or more) files and one file include another one. +#define STATIC_ASSERT(expr) \ +enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __LINE__) = 1/(expr) } + +#endif +//@} + +//#NT#2010/05/21#Steven Wang -begin +//#NT#Check if FW size > EXEC base address +extern UINT32 _load_BOOT_EXEC_start_base; +//#NT#2010/05/21#Steven Wang -end + +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[]; + +extern UINT32 LoaderInternalInfo[]; + +extern PSTORAGE_OBJ int_strg_obj; + +//------------------------------------------------------------------------------ +// internal functions +//------------------------------------------------------------------------------ +extern int bl_chk_valid_all_in_one(NVTPACK_MEM *p_mem_all_in_one); +extern int bl_chk_uboot(unsigned int addr, unsigned int size); +extern unsigned int bl_process_all_in_one(UINT32 uiFwBuf, UINT32 uiFwBufSize, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size); +extern int bl_boot_uboot(unsigned char *p_fdt); +extern int bl_chk_fdt(unsigned int addr, unsigned int size); +extern int bl_copy_fdt_to_fdt_addr(unsigned char *p_fdt /*IN*/, unsigned char **pp_fdt /*OUT*/); +extern int bl_flash_open(void); + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern UINT32 bl_mainFlow(void); + +// project(customer) main function +extern void prj_main(void); +extern void bl_read_rtos_addr(UINT32* pLoadAddr, UINT32* pTargetAddr, UINT32* pSize); +#endif diff --git a/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.c b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.c new file mode 100755 index 000000000000..c01e4330710e --- /dev/null +++ b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.c @@ -0,0 +1,372 @@ +#include "constant.h" +#include "fuart.h" +#include "fat.h" +#include "StorageDef.h" +#include "global.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "bl_func.h" +#include "string.h" +#include "lz.h" +#include "debug.h" +#include "loader.h" +#include "emb_partition_info.h" +#include "modelext_info.h" +#include "bin_info.h" +#include "shm_info.h" +#include "libfdt.h" +#include +#include "mmc_api.h" +#include "cache.h" +#include "Memory.h" +#include "timer.h" +#include "lz.h" +#include "bl_u2.h" +#include "nand.h" +#include "nor.h" + +#ifndef ALIGN_FLOOR +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#endif +#ifndef ALIGN_CEIL +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#endif + +#if (USB_WRITELOADER || UART_UPDATE) + +//u2: means usb and uart +#include "scsi_op.h" + +typedef enum _U2_FW_TYPE { + U2_FW_TYPE_UNKNOWN, + U2_FW_TYPE_NVTPACK, + U2_FW_TYPE_UBOOT, +} U2_FW_TYPE; + +#define MAKEUINT32(a, b, c, d) ((UINT32)((a)&0xFF)) | (((UINT32)((b)&0xFF)) << 8) | (((UINT32)((c)&0xFF)) << 16) | (((UINT32)((d)&0xFF)) << 24) + +static U2_FW_TYPE m_u2_fw_type = U2_FW_TYPE_UNKNOWN; +static unsigned int m_u2_fw_size = 0; +static unsigned char *m_fdt = NULL; +UINT32 m_tmp_addr = SDRAM_Start_FW; +static int m_uboot_status = -2; +static int m_fdt_status = -1; +static SCSIOP_FLASH_OP m_flash_op = {0}; + +__attribute__((target("thumb"))) static int u2_check_firmware(unsigned int addr) +{ + NVTPACK_FW_HDR2 *p_hdr = (NVTPACK_FW_HDR2 *)addr; + unsigned int size = p_hdr->TotalSize; + NVTPACK_MEM mem_in ; + mem_in.p_data = (void *)addr; + mem_in.len = size; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + m_u2_fw_type = U2_FW_TYPE_NVTPACK; + m_u2_fw_size = size; + return 0; + } + // uboot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)addr; // describe compressed u-boot + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = __builtin_bswap32(pBfc->uiSizeComp); + UINT32 addr_uncomp = ALIGN_CEIL(addr + size_comp_le, 4); + LZ_Uncompress((UINT8 *)addr + sizeof(NVTPACK_BFC_HDR), (unsigned char *)addr_uncomp, 1024); + addr = addr_uncomp; + } + HEADINFO *p_headinfo = (HEADINFO *)(addr + BIN_INFO_OFFSET_UBOOT); + if (p_headinfo->BinLength < 0x1000000 && bl_chk_uboot(addr, p_headinfo->BinLength) == 0) { + m_u2_fw_type = U2_FW_TYPE_UBOOT; + m_u2_fw_size = p_headinfo->BinLength; + return 0; + } + + return -1; +} + +__attribute__((target("thumb"))) static int u2_boot_uboot(unsigned int addr, unsigned int size, U2_FW_TYPE fw_type) +{ + if (fw_type == U2_FW_TYPE_NVTPACK) { + UINT32 comp_addr = 0; + UINT32 comp_size = 0; + DRAM_PARTITION *p_dram_partition = NULL; + return bl_process_all_in_one(addr, size, &p_dram_partition, FUNC_UPDATE_FW, &comp_addr, &comp_size); + } else { + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(addr + BIN_INFO_OFFSET_UBOOT); + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)addr; // describe compressed u-boot + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = __builtin_bswap32(pBfc->uiSizeComp); + UINT32 addr_uncomp = ALIGN_CEIL(addr + size_comp_le, 4); + LZ_Uncompress((UINT8 *)addr + sizeof(NVTPACK_BFC_HDR), (unsigned char *)addr_uncomp, 1024); + p_headinfo = (HEADINFO *)(addr_uncomp + BIN_INFO_OFFSET_UBOOT); + } + // check tmp memory (file load) cannot overlap with uboot + if ((addr < p_headinfo->CodeEntry && addr + size > p_headinfo->CodeEntry) || + (addr > p_headinfo->CodeEntry && addr + size < p_headinfo->CodeEntry + size)) { + debug_err_var("addr", addr); + debug_err_var("size", size); + debug_err_var("CodeEntry", p_headinfo->CodeEntry); + debug_err("uboot & tmp_addr are overlapped\r\n"); + return -1; + } + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = __builtin_bswap32(pBfc->uiSizeComp); + LZ_Uncompress((UINT8 *)addr + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_headinfo->CodeEntry, size_comp_le); + } else { + utl_memcpy((void *)p_headinfo->CodeEntry, (void *)addr, size); + } + + if (m_fdt != NULL) { + bl_boot_uboot(m_fdt); + } else { + //check fdt followed uboot + unsigned char *fdt = (unsigned char *)(addr + size); + if (fdt_check_header(fdt) != 0) { + debug_err("no fdt behind uboot\r\n"); + return -1; + } + utl_memcpy((void *)(p_headinfo->CodeEntry + size), fdt, fdt_totalsize(fdt)); + debug_msg_var("jump", p_headinfo->CodeEntry); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)p_headinfo->CodeEntry; + p_func(); + } + } + } + return 0; +} + +__attribute__((target("thumb"))) static int u2_on_verify(unsigned int p_cmd, unsigned int *p_data, unsigned int *in_size) +{ + NVT_SCSI_CBW *p_cbw = (NVT_SCSI_CBW *)p_cmd; + int cmd_id = p_cbw->CBWCB[1]; + + switch (cmd_id) { + case SCSIOP_OUT_MEM_WRITE: + *p_data = MAKEUINT32(p_cbw->CBWCB[2], p_cbw->CBWCB[3], p_cbw->CBWCB[4], p_cbw->CBWCB[5]); + *in_size = p_cbw->dCBWDataTransferLength; + break; + case SCSIOP_OUT_FLASH_ACCESS: + if (p_cbw->dCBWDataTransferLength != sizeof(m_flash_op)) { + debug_err_var("m_flash_op size not matched", *in_size); + return -1; + } + *p_data = (UINT32)&m_flash_op; + *in_size = p_cbw->dCBWDataTransferLength; + break; + case SCSIOP_IN_MEM_READ: + *p_data = MAKEUINT32(p_cbw->CBWCB[2], p_cbw->CBWCB[3], p_cbw->CBWCB[4], p_cbw->CBWCB[5]); + *in_size = p_cbw->dCBWDataTransferLength; + //debug_msg_var("p_data:", MAKEUINT32(p_cbw->CBWCB[2], p_cbw->CBWCB[3], p_cbw->CBWCB[4], p_cbw->CBWCB[5])); + break; + case SCSIOP_IN_GET_TMP_ADDR: + *p_data = (unsigned int)&m_tmp_addr; + *in_size = sizeof(m_tmp_addr); + break; + case SCSIOP_IN_FDT: + *p_data = (unsigned int)&m_fdt_status; + *in_size = sizeof(m_fdt_status); + if (bl_chk_fdt((unsigned int)SDRAM_Start_FW, p_cbw->dCBWDataTransferLength) == 0) { + m_fdt_status = bl_copy_fdt_to_fdt_addr((unsigned char *)SDRAM_Start_FW, &m_fdt); + } else { + m_fdt_status = -1; + } + break; + case SCSIOP_IN_UBOOT: + *p_data = (unsigned int)&m_uboot_status; + *in_size = sizeof(m_uboot_status); + if (u2_check_firmware(SDRAM_Start_FW) == 0) { + m_uboot_status = 0; + } else { + m_uboot_status = -1; + } + break; + default: + debug_err_var("unknown_cmd_id", cmd_id); + break; + } + return 0; +} + +__attribute__((target("thumb"))) static int u2_flash_open(unsigned int flash_type) +{ + static int is_opened[4] = {0}; + + if (flash_type >= 4) { + debug_err_var("flash_type", flash_type); + return -1; + } + + // open default and its related to + if (is_opened[0] == 0) { + if (bl_flash_open() != 0) { + return -1; + } + is_opened[0] = 1; + if (int_strg_obj == nand_get_storage_object()) { + is_opened[FLASH_ACCESS_TYPE_NAND] = 1; + } + if (int_strg_obj == nor_get_storage_object()) { + is_opened[FLASH_ACCESS_TYPE_NOR] = 1; + } + } + + if (is_opened[flash_type]) { + return 0; + } + + switch(flash_type) { + case FLASH_ACCESS_TYPE_NAND: +#if 0 + nand_get_storage_object()->flash_setConfig(FLASH_CFG_ID_SPI_IDENTIFY_CB, (UINT32)nand_identify); +#endif + nand_get_storage_object()->flash_open(); + is_opened[FLASH_ACCESS_TYPE_NAND] = 1; + break; + case FLASH_ACCESS_TYPE_NOR: +#if 0 + nor_get_storage_object()->flash_installIdentifyCB(nor_identify); +#endif + nor_get_storage_object()->flash_open(); + is_opened[FLASH_ACCESS_TYPE_NOR] = 1; + break; + default: + debug_err_var("unsupport flash_type", flash_type); + return -1; + } + return 0; +} + +__attribute__((target("thumb"))) static int u2_on_vendor(unsigned int p_cmd) +{ + int er; + PSTORAGE_OBJ p_strg = NULL; + NVT_SCSI_CBW *p_cbw = (NVT_SCSI_CBW *)p_cmd; + int cmd_id = p_cbw->CBWCB[1]; + + switch (cmd_id) { + case SCSIOP_OUT_MEM_WRITE: + break; + case SCSIOP_OUT_FLASH_ACCESS: + if (u2_flash_open(m_flash_op.type) != 0) { + return -1; + } + switch(m_flash_op.type) { + case FLASH_ACCESS_TYPE_AUTO: + p_strg = int_strg_obj; + break; + case FLASH_ACCESS_TYPE_NAND: + p_strg = nand_get_storage_object(); + break; + case FLASH_ACCESS_TYPE_NOR: + p_strg = nor_get_storage_object(); + break; + default: + debug_err_var("unsupport flash_type", m_flash_op.type); + return -1; + } + // If use USB write loader & nand user define table => should add this + // User define SPI-NAND id table sample code(you can remove // by your self) + //p_strg->flash_setConfig(FLASH_CFG_ID_SPI_IDENTIFY_CB, (UINT32)nand_identify); + + if (m_flash_op.is_write) { + //write + unsigned int block_size = p_strg->flash_getBlockSize(); + unsigned int startblk = (unsigned int)(m_flash_op.offset / block_size); + unsigned int write_size = ALIGN_CEIL(m_flash_op.size, block_size); + if ((er = p_strg->flash_writePartition(startblk, write_size, (unsigned int)(m_flash_op.partition_size), (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE)) != 0) { + debug_err_var("wr failed", er); + return -1; + } + //Once write loader something wrong happen.. + //Can enable code bellow make sure data were program into SPI-NOR/NAND +#if 0 + else { //Read back and make checksum + unsigned int reload_addr; + UINT32 status = 0; + reload_addr = SDRAM_Start_FW + write_size; + + int_strg_obj->flash_getConfig(FLASH_CFG_ID_SPI_GET_STATUS_1,(UINT32)&status); + debug_msg_var( +"status1", status); + + if (int_strg_obj->flash_readSectors(startblk, write_size, (UINT8 *)reload_addr, NAND_RW_LOADER) < 0) { + debug_err("rd fail\r\n"); + } else { + debug_err("rd success\r\n"); + } + // Verify + if (memcmp((void *)SDRAM_Start_FW, (void *)reload_addr, write_size) != 0) { + debug_err("verify fail\r\n"); + } else { + debug_msg_var("read back 0x0",*(UINT32 *)(reload_addr+0x0)); + debug_msg_var("read back 0x4",*(UINT32 *)(reload_addr+0x4)); + debug_msg_var("read back 0x8",*(UINT32 *)(reload_addr+0x8)); + debug_msg_var("read back 0xc",*(UINT32 *)(reload_addr+0xc)); + } + + } +#endif + } else { + //read + unsigned int block_size = p_strg->flash_getBlockSize(); + unsigned int startblk = (unsigned int)(m_flash_op.offset / block_size); + unsigned int read_size = ALIGN_CEIL(m_flash_op.size, block_size); + if ((er = p_strg->flash_readSectors(startblk, read_size, (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE)) != 0) { + debug_err_var("rd failed", er); + return -1; + } + } + break; + case SCSIOP_IN_MEM_READ: + case SCSIOP_IN_GET_TMP_ADDR: + break; + case SCSIOP_IN_FDT: + break; + case SCSIOP_IN_UBOOT: + break; + default: + debug_err_var("unknown_cmd_id", cmd_id); + break; + } + return 0; +} + +__attribute__((target("thumb"))) int bl_usb(void) +{ + + typedef int (*MSDC_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); + typedef int (*MSDC_VenDone_CB)(unsigned int pCmdBuf); + extern void fLib_USB_Update_FW(void); + extern MSDC_Verify_CB guiU2MsdcCheck_cb; + extern MSDC_VenDone_CB guiU2MsdcVendorDone_cb; + guiU2MsdcCheck_cb = u2_on_verify; + guiU2MsdcVendorDone_cb = u2_on_vendor; + fLib_USB_Update_FW(); + u2_boot_uboot(SDRAM_Start_FW, m_u2_fw_size, m_u2_fw_type); + return 0; +} + +__attribute__((target("thumb"))) int bl_uart(void) +{ + + typedef int (*UART_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); + typedef int (*UART_Vendor_CB)(unsigned int pCmdBuf); + extern void uart_upgrade_procedure(void); + extern UART_Verify_CB guiUARTCheck_cb; + extern UART_Vendor_CB guiUARTVendor_cb; + guiUARTCheck_cb = u2_on_verify; + guiUARTVendor_cb = u2_on_vendor; + uart_upgrade_procedure(); + u2_boot_uboot(SDRAM_Start_FW, m_u2_fw_size, m_u2_fw_type); + return 0; +} + +#endif //USB_WRITELOADER diff --git a/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.h b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.h new file mode 100755 index 000000000000..28ae6ee7c714 --- /dev/null +++ b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.h @@ -0,0 +1,7 @@ +#ifndef _BL_USB_H +#define _BL_USB_H + +extern int bl_usb(void); +extern int bl_uart(void); + +#endif \ No newline at end of file diff --git a/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c new file mode 100755 index 000000000000..93dd5ee91681 --- /dev/null +++ b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c @@ -0,0 +1,1168 @@ +/* + * main.c + * + * Entry point for nsboot + * + * Copyright (c) 2018 Novatek, ALL Rights Reserve + */ +#include "main.h" +#include "board.h" +#include "constant.h" +#include "compiler.h" +#include "mmc_api.h" +#include "spi020.h" +#include "fuart.h" +#include "timer.h" +#include "ahb_dma.h" +#include "bus.h" +#include "pll.h" +//#include "ddr.h" +#include "debug.h" +#include "bdata.h" +#include "nvt_rdata_sys.h" +#include "data_keeper.h" +#include "bl_func.h" +#include "cache.h" +#include "global.h" +#include "nvtpack.h" +#include "bin_info.h" +#include "Memory.h" + +//#define MEM_TEST +//#define CONFIG_FIX_ADDR 1 +//#define DO_DEBUG +//#define USE_SCP /* use ice scp file set ddr and remap */ + +//int __attribute__ ((section (".READ_CUSTOM_DATA"))) read_custom_data_if(unsigned int, struct buffer_info_t*, int, int); + +FLASH_TYPE_T flash_type = FLASH_SD; +#define _THUMB2 __attribute__((target("thumb"))) +#define VERSION "Version 1.0.00" + +// Specific test +#define DRAM_TEST (0) +#define HVYLOAD_TEST (0) +#define WDT_TEST_ENABLE (0) + +#define WDT_CASE_INTRESET (0) +#define WDT_CASE_EXTRESET (1) +#define WDT_CASE_NORMAL (2) +#define WDT_TEST_CASE (WDT_CASE_EXTRESET) + +#ifndef ALIGN_FLOOR +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#endif +#ifndef ALIGN_CEIL +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#endif + +extern char _loader_exec_compres_start[]; +extern char _loader_exec_compress_load_cpu_addr[]; + +extern char _loader_data_cpu_addr[]; +extern char _loader_exec_end_base[]; +extern char _loader_data_start_base[]; +extern char _loader_data_size[]; + +extern int decompress(unsigned char *buf, int in_len, unsigned char *output); +extern void reset_cpu(unsigned int base, unsigned int count); +extern void wait_delay(unsigned int loop); +extern void jmpcore1(void); +extern void fLib_USB_Update_FW(void); + +extern void serial_init(void); + + +extern unsigned int read_reg(unsigned int reg); +extern void write_reg(unsigned int reg, unsigned int value); + +#define write_reg(m,n) OUTW(m,n) +#define read_reg(m) INW(m) + +void hang(void); +void __div0(void); +void check_storage_type(void); +void u32PMU_WritePLL(unsigned int base, uint num, uint offset, uint value); +void set_bus(unsigned int base); +void set_ddr0(unsigned int base); +#if (defined(DDR1_1800_SZ_1Gb) || defined(DDR1_1800_SZ_2Gb) || defined(DDR1_1800_SZ_4Gb) || defined(DDR1_1600_SZ_4Gb)) +/* RC DDRC1 */ +void set_ddr1(unsigned int base); +#endif +void set_fire(unsigned int base); +void cpu_change_armpll(void); +void show_evb_message(void); +void reset_EP(void); +#if HVYLOAD_TEST +void heavy_load_test(void); +#endif +//void entry(void); +void entry(void) __attribute__ ((section (".part1"))); + +#define KPrint +void hang(void) +{ + debug_msg("### ERROR ### Please RESET the board ###\n"); + for (;;) ; +} + +void __div0(void) +{ + hang(); +} + +#ifdef DO_DEBUG + +_THUMB2 static void hexdump(unsigned char *data, int len) +{ + int i, j; + + for (i = 0; i < len; i += 16) { + KPrint("\n%04xh:", i); + for (j = 0; j < 16; j++) + KPrint(" %02X", data[i + j]); + KPrint(" "); + for (j = 0; j < 16; j++) { + int c = data[i + j]; + if (c < 0x20) + KPrint("."); + else + KPrint("%c", c); + } + } + KPrint("\n"); +} + +_THUMB2 void syshdrdump(SYSHDR * hdr) +{ + KPrint("\n"); + KPrint(" signature: %s\n", hdr->signature); + KPrint(" bootm_addr: 0x%x\n", hdr->bootm_addr); + KPrint(" stsize: %d\n", hdr->stsize); + KPrint(" st_0: 0x%x\n", hdr->st.setting[0]); + KPrint(" st_1: 0x%x\n", hdr->st.setting[1]); + KPrint(" st_2: 0x%x\n", hdr->st.setting[2]); +} + +#endif //DO_DEBUG + +_THUMB2 void u32PMU_WritePLL(unsigned int base, uint num, uint offset, uint value) +{ + unsigned int data; + + if(num == 2) { + /* CPU switch to 12M */ + write_reg(base + 0x1340, 0x02); + } + + if(offset == 0x7C0) {/* CPU */ + data = (value * (1 << 17) / 80) / 12; + } else if((offset == 0x4C0) || (offset == 0x500)) {/* DDR */ + data = (value * 68266) / 1000;/* 131072 / (12 * 160) *///0x01F111; + //KPrint("data = 0x%x\n", data); + } else { + data = (value * (1 << 17)) / 12; + } + + write_reg(base + 0x10000 + offset + 0x20, data & 0xFF); + write_reg(base + 0x10000 + offset + 0x24, (data >> 8) & 0xFF); + write_reg(base + 0x10000 + offset + 0x28, (data >> 16) & 0xFF); + + /* ddr0 & ddr1 set at the same time */ + if(num == 3) + return; + + /* hit cache & wait clock stable */ + if((num < 2) || (num > 4)) { + /* delay 30 us */ + wait_delay(3000); + } else if(num == 2) { + /* cpu delay 300 us */ + wait_delay(30000); + write_reg(base + 0x1340, 0x03); + } else if(num == 4) { + /* ddr delay 30 us */ + wait_delay(3000); + write_reg(base + 0x20, 0x0000A001); + /* ddr delay 300 us */ + wait_delay(30000); + write_reg(base + 0x20, 0x0000E001); + } +} + +_THUMB2 void check_storage_type(void) +{ + unsigned int value; + + value = read_reg(REG_PMU_BASE + 0x04) & (1 << 2); + if (value) + flash_type = FLASH_NOR; + else + flash_type = FLASH_SPI_NAND; + //else + // flash_type = FLASH_SD; +} + +#if HVYLOAD_TEST +__attribute__((target("thumb"))) void heavy_load_test(void) +{ + //volatile int tt = 0; + unsigned int test_addr1 = 0x30001000, test_addr2 = 0x30101000, test_addr3 = 0x30202000; + unsigned int test_size = 0x100000; + unsigned int value; + + //value = read_reg(REG_PMU_BASE + 0x50); + //value |= (1 << 25); + //write_reg(REG_PMU_BASE + 0x50, value); + + // set heavy load pattern + write_reg(REG_HEAVY_LOAD_BASE + 0x8090, 0xaaaaaaaa); + write_reg(REG_HEAVY_LOAD_BASE + 0x8094, 0x55555555); + write_reg(REG_HEAVY_LOAD_BASE + 0x8098, 0x00000000); + write_reg(REG_HEAVY_LOAD_BASE + 0x809C, 0xffffffff); + + // set heavy load region + write_reg(REG_HEAVY_LOAD_BASE + 0x8064, test_addr1); + write_reg(REG_HEAVY_LOAD_BASE + 0x8068, test_size); + write_reg(REG_HEAVY_LOAD_BASE + 0x8074, test_addr2); + write_reg(REG_HEAVY_LOAD_BASE + 0x8078, test_size); + write_reg(REG_HEAVY_LOAD_BASE + 0x8084, test_addr3); + write_reg(REG_HEAVY_LOAD_BASE + 0x8088, test_size); + + // trigger heavy load + + write_reg(REG_HEAVY_LOAD_BASE + 0x8060, 0x00103fc1); + write_reg(REG_HEAVY_LOAD_BASE + 0x8070, 0x00103fc1); + write_reg(REG_HEAVY_LOAD_BASE + 0x8080, 0x00103fc1); + write_reg(REG_HEAVY_LOAD_BASE + 0x805c, 0x7); + + value = read_reg(REG_HEAVY_LOAD_BASE + 0x80A0); + value &= 0x03; + + while(value == 0) { + value = read_reg(REG_HEAVY_LOAD_BASE + 0x80A0); + //KPrint("data = 0x%x\n", value); + value &= 0x03; + if(value) + break; + } + + //KPrint("0x80A0 data = 0x%x\n", value); + if(read_reg(REG_HEAVY_LOAD_BASE + 0x80A0) & 0x2){ + //KPrint("HEAVY LOAD fail, ERROR_DATA = 0x%x, CORRECT_DATA = 0x%x, ADDR = 0x%x\n", + // read_reg(REG_HEAVY_LOAD_BASE + 0x80A4), read_reg(REG_HEAVY_LOAD_BASE + 0x80A8), read_reg(REG_HEAVY_LOAD_BASE + 0x80AC)); + debug_msg("HEAVY LOAD NG\n"); + while(1); + } + else + debug_msg("HEAVY LOAD pass\n"); + + // write 1 clear + write_reg(REG_HEAVY_LOAD_BASE + 0x80A0, 0x03); + + //tt++; + //while(tt > 0); +} +#endif + +void set_bus(unsigned int base) +{ + volatile unsigned int i; + + //KPrint("set_bus\n"); + + for(i = 0; i < sizeof(bus_arg) / 8; i++) { + write_reg(base + bus_arg[i][0], bus_arg[i][1]); + } + + for(i = 0; i < 60000; i++); + +} + +/* RC DDRC0 */ +void set_ddr0(unsigned int base) +{ +#if 0 + volatile unsigned int i; + + //KPrint("set ddr0 arg\n"); + + while(!(read_reg(base + 0x1000) & 0x10)); + + for(i = 0; i < sizeof(DDR0_arg) / 8; i++) { + write_reg(base + DDR0_arg[i][0], DDR0_arg[i][1]); + } + + write_reg(base + 0x04, 0x00000001); + while(!(read_reg(base + 0x04) & 0x100)); + + //for(i = 0; i < 60000; i++); +#endif +} + +#if (defined(DDR1_1800_SZ_1Gb) || defined(DDR1_1800_SZ_2Gb) || defined(DDR1_1800_SZ_4Gb) || defined(DDR1_1600_SZ_4Gb)) +/* RC DDRC1 */ +void set_ddr1(unsigned int base) +{ + volatile unsigned int i; + + //KPrint("set ddr1 arg\n"); + + while(!(read_reg(base + 0x1000) & 0x10)); + + for(i = 0; i < sizeof(DDR1_arg) / 8; i++) { + write_reg(base + DDR1_arg[i][0], DDR1_arg[i][1]); + } + + write_reg(base + 0x04, 0x00000001); + while(!(read_reg(base + 0x04) & 0x100)); + + //for(i = 0; i < 60000; i++); +} +#endif //(defined(DDR1_1800_SZ_1Gb) || defined(DDR1_1800_SZ_2Gb) || defined(DDR1_1800_SZ_4Gb)) + +static void platform_setup(unsigned int pmu_base, unsigned int h2x_base, unsigned int dmac030_base, unsigned int tmr010_base) +{ +#if 0 + unsigned int value; + + /* Enable gating clock */ + /* release tmr & wdt */ + value = read_reg(pmu_base + 0x78); + value = value & ~((0x1 << 7) | (0x1 << 15)); + write_reg(pmu_base + 0x78, value); + + /* disable DSP */ + write_reg(pmu_base + 0x104, 0x00060000); + + /* Set H2X R/W prottype */ + write_reg(h2x_base + 0x20000, 0x5 << 2); + //write_reg(h2x_base + 0x40000, 0x5 << 2); + //write_reg(h2x_base + 0x60000, 0x14); + write_reg(h2x_base + 0x80000, 0x14); + //write_reg(h2x_base + 0xA0000, 0x5 << 2); + write_reg(h2x_base + 0xC0000, 0x5 << 2); + + /* Set VGA & CVBS */ + value = read_reg(pmu_base + 0xFC) & 0xFE1FFE1F; + value = value | (0x7 << 21) | (0x7 << 5); + write_reg(pmu_base + 0xFC, value); + + /* WDT exit reset */ + value = read_reg(pmu_base + 0x5C); + value |= (0x1 << 28); + write_reg(pmu_base + 0x5C, value); + + /* DMAC030 exit reset */ + value = read_reg(pmu_base + 0x50); + value |= (0x1 << 16); + write_reg(pmu_base + 0x50, value); + + /* Turn on u_FTDMAC030 PClk */ + value = read_reg(pmu_base + 0x70); + value &= ~(0x1 << 23); + write_reg(pmu_base + 0x70, value); + + /* Disable debug uart */ + value = read_reg(0xfe4e0010); + value &= ~(0x1 << 7); + write_reg(0xfe4e0010, value); + /* The following IP is used by ROM CODE, we need to clear its interrupt + */ + /* clear DMAC030 pending interrupts */ + write_reg(dmac030_base + 0x8, 0xff); + /* clear DMAC030 Error/Abort interrupts */ + write_reg(dmac030_base + 0x10, 0xff); + /* synchronize the corresponding dma_req */ + write_reg(dmac030_base + 0x20, 0xffff); + + write_reg(tmr010_base + 0x38, 0xff); + + /* UART pin mux */ + /* UART clock source */ + /* UART from PLL4, calc clock div to uart */ + //reg = read_reg(REG_PMU_BASE + 0x194) & 0xFFFFFFC0; + //value = u32PMU_ReadPLL4CLK() / 6; + //value = (value / (2*16*115200)) - 1; + value = read_reg(pmu_base + 0x194); + value &= ~0xFF; + write_reg(pmu_base + 0x194, value | 0x1); + + if(pmu_base == REG_PMU_BASE) + serial_init(); +#endif +} + +void set_fire(unsigned int base) +{ +#if 0 +#if (defined(DDR0_1200_SZ_4Gbx2) || defined(DDR0_1200_SZ_2Gbx2)) + unsigned int i, PLL[6][2] = {}; + KPrint("clock no change...\n"); + return; +#else + #if (defined(DDR0_1600_SZ_4Gbx2) || defined(DDR0_1600_SZ_2Gbx2)) + /* codec, axi0, CPU, ddr0, ddr1 7.5~11.5, cnn */ + unsigned int i, PLL[6][2] = {{0x740, 380}, {0x400, 467}, {0x7C0, 1100}, {0x4C0, 1600}, {0x500, 1600}, {0x480, 600}}; + #else + #if (defined(DDR0_1800_SZ_4Gb) || defined(DDR0_1800_SZ_4Gbx2) || defined(DDR0_1800_SZ_2Gbx2) || defined(DDR0_1800_SZ_1Gbx2)) + unsigned int i, PLL[6][2] = {{0x740, 380}, {0x400, 467}, {0x7C0, 1100}, {0x4C0, 1866}, {0x500, 1866}, {0x480, 600}}; + #else + KPrint("not define this type ddr setting...\n"); + return; + #endif + #endif +#endif + debug_msg("clock change..."); + for(i = 0; i < 6; i++) { + //KPrint("offset = 0x%08x, data = 0x%08x\n", PLL[i][0], PLL[i][1]); + u32PMU_WritePLL(base, i, PLL[i][0], PLL[i][1]); + } + + debug_msg("done\n"); +#endif +} + +#ifdef MEM_TEST +int memtest(void); + +_THUMB2 int memtest(void) +{ + unsigned int *bg; + int i = 0, j = 0, fail = 0; + unsigned int pattern[2] = {0x5a5a5a5a, 0xa5a5a5a5}; + int TEST_LENGTH = 0x100000; /* 1MB */ + unsigned int addr = 0x1000000; + + //KPrint("Test addr: 0x%x, len = 0x%x\n", addr, TEST_LENGTH); + debug_msg("Test addr: 0x%x, len =\n"); + bg = (unsigned int *)addr; + + for (j = 0; j < (TEST_LENGTH / 4); j += 2) { + *bg++ = pattern[0]; + *bg++ = pattern[1]; + } + + bg = (unsigned int *)addr; + for (j = 0; j < (TEST_LENGTH / 4); j += 2) { + if (*bg != pattern[i] || (*(bg + 1) != pattern[i + 1])){ + fail++; +#if 1 + if (*bg != pattern[i]) + debug_msg("addr: 0x%x correct data: 0x%x, err = 0x%x\n"); + if (*(bg + 1) != pattern[i + 1]) + debug_msg("addr: 0x%x correct data: 0x%x, err = 0x%x\n"); +#endif + } + bg += 2; + } + + if (fail) + debug_msg("error number %d: "); + else + debug_msg("Test pass, pattern 0x%x, 0x%x\n"); + + if(fail > 0) + while(1); + + return 0; +} +#endif + +_THUMB2 void cpu_change_armpll(void) +{ + //spare pll power down + write_reg(REG_PMU_BASE + 0x10000 + (0x210), 0x01); + + #if 0 + debug_msg("CPU1400 "); + //CPU 1400 MHz -> CPU-MPLL-175Mhz = 0x1D2AAA + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x20), 0xAA); // B0 + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x24), 0x2A); // B1 + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x28), 0x1D); // B2 + #elif 1 + debug_msg("CPU1200 "); + //CPU 1200 MHz -> CPU-MPLL-150Mhz = 0x190000 + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x20), 0x00); // B0 + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x24), 0x00); // B1 + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x28), 0x19); // B2 + #elif 0 + debug_msg("CPU1000 "); + //CPU 1000 MHz -> CPU-MPLL-125Mhz = 0x14D555 + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x20), 0x55); // B0 + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x24), 0xD5); // B1 + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x28), 0x14); // B2 + #else + debug_msg("CPU800"); + //CPU 800 MHz -> CPU-MPLL-100Mhz = 0x10AAAA + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x20), 0xAA); // B0 + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x24), 0xAA); // B1 + write_reg(REG_PMU_BASE + 0x10000 + (0x7C0+0x28), 0x10); // B2 + #endif + + // wait 300us for synthesizer stable + udelay(300); + + // de-assert resetb_armpll to 1: Write 0xD1 = 0x10 + write_reg(REG_PMU_BASE + 0x10000 + (0xD1<<2), 0x10); + + // wait 300us for ARMPLL stable + udelay(500); + + // Set ARMPLL output. Write 0xD0 = 0x03 + write_reg(REG_PMU_BASE + 0x10000 + (0xD0<<2), 0x03); + + // Change CPU to APLL + write_reg(REG_PMU_BASE + 0x100, read_reg(REG_PMU_BASE + 0x100)|(0x1<<31)); + + debug_msg("DONE\r\n"); +} + + +_THUMB2 void show_evb_message(void) +{ + + debug_msg("NA51068 "); + debug_msg(Dec2HexStr2Bytes((LoaderInternalInfo[1] >> 28) & 0xF)); + debug_msg("."); + debug_msg(Dec2HexStr2Bytes((LoaderInternalInfo[1] >> 24) & 0xF)); + debug_msg("."); + debug_msg(Dec2HexStr2Bytes((LoaderInternalInfo[1] >> 16) & 0xFF)); + debug_msg("\r\n"); + +#ifdef DDR0_1200_SZ_4Gbx2 + KPrint("DDR0 1200 4Gbx2\r\n"); +#endif + +#ifdef DDR0_1600_SZ_2Gbx1 + KPrint("DDR0 1600 2Gbx1\r\n"); +#endif + +#ifdef DDR0_1600_SZ_4Gbx1 + KPrint("DDR0 1600 4Gbx1\r\n"); +#endif + +#ifdef DDR0_1600_SZ_2Gbx2 + KPrint("DDR0 1600 2Gbx2\r\n"); +#endif + +#ifdef DDR0_1600_SZ_4Gbx2 + KPrint("DDR0 1600 4Gbx2\r\n"); +#endif + +#ifdef DDR0_1800_SZ_4Gb + KPrint("DDR0 1800 4Gb\r\n"); +#endif + +#ifdef DDR0_1800_SZ_1Gbx2 + KPrint("DDR0 1800 1Gbx2\r\n"); +#endif + +#ifdef DDR0_1800_SZ_4Gbx2 + KPrint("DDR0 1800 4Gbx2\r\n"); +#endif + +#ifdef DDR0_FPGA + debug_msg("FPGA EMULATION Loader\r\n"); +#endif + +#ifdef MODE0 + KPrint("CPU800, DSP 600, codec 350, ddr 1600\n"); +#endif + + +} + +/* set ep 12MHz */ +_THUMB2 void reset_EP(void) +{ + unsigned int reg; + /* set ext clk */ + reg = read_reg(REG_PMU_BASE + 0x1a4); + reg &= ~0x3; + reg |= 0x1; + write_reg(REG_PMU_BASE + 0x1a4, reg); + + /* set clk 12MHz */ + reg = read_reg(REG_PMU_BASE + 0x170); + reg &= ~0xFF; + reg |= 0x6; + write_reg(REG_PMU_BASE + 0x170, reg); + + /* enable gpio2 */ + reg = read_reg(REG_PMU_BASE + 0x58); + reg |= (0x1 << 29); + write_reg(REG_PMU_BASE + 0x58, reg); + + reg = read_reg(REG_PMU_BASE + 0x74); + reg &= ~(0x1 << 5); + write_reg(REG_PMU_BASE + 0x74, reg); + + /* set gpio2 pulse */ + reg = read_reg(REG_GPIO2_BASE + 0x08); + reg |= (0x1 << 27); + write_reg(REG_GPIO2_BASE + 0x08, reg); + + reg = read_reg(REG_GPIO2_BASE + 0x14); + reg |= (0x1 << 27); + write_reg(REG_GPIO2_BASE + 0x14, reg); + + wait_delay(0x10000); + + reg = read_reg(REG_GPIO2_BASE + 0x10); + reg |= (0x1 << 27); + write_reg(REG_GPIO2_BASE + 0x10, reg); +} + +#if (_FPGA_EMULATION_ == 1) +static inline unsigned long read_periphbase(void) +{ + unsigned long val; + __asm__ __volatile__( + "mrc p15, 4, %0, c15, c0, 0\n\t" + : "=r"(val) + ); + return val; +} +#endif + + +#if (_LOADER_COMPRESSED_ == ENABLE) && defined(_UBOOT_BIND_ON_) +_THUMB2 static void bl_core2_reset(void) +{ + UINT32 core_reg; + core_reg = *(volatile UINT32 *)0xF84000F0; + core_reg &= ~(1<<3); + core_reg &= ~(1<<11); + *(volatile UINT32 *)0xF84000F0 = core_reg; + core_reg |= (1<<2)|(1<<10) | (1<<21); + core_reg |= (1<<17); + *(volatile UINT32 *)0xF84000F0 = core_reg; + +} + +_THUMB2 static UINT32 bl_boot_bind_uboot(void) +{ + extern char _lzma_tmp_start[]; + extern char _lzma_tmp_end[]; + _ALIGNED(4) static char uboot_pre_deocde[BIN_INFO_OFFSET_UBOOT+sizeof(HEADINFO)]; + int loader_size, padding_bytes; + NVTPACK_BFC_HDR *p_loader, *p_uboot; + + p_loader = (NVTPACK_BFC_HDR *)(_loader_exec_compress_load_cpu_addr); + padding_bytes = 4 - (__builtin_bswap32(p_loader->uiSizeComp)&0x3); + loader_size = __builtin_bswap32(p_loader->uiSizeComp) + LDC_HEADER_SIZE + padding_bytes; + p_uboot = (NVTPACK_BFC_HDR *)(_loader_exec_compress_load_cpu_addr + loader_size); + + lzma_inflate( + (UINT8 *)&p_uboot[1], + __builtin_bswap32(p_uboot->uiSizeComp), + (UINT8 *)uboot_pre_deocde, + sizeof(uboot_pre_deocde), + (UINT8 *)_lzma_tmp_start, + (UINT32)(_lzma_tmp_end - _lzma_tmp_start) + ); + + HEADINFO *p_head = (HEADINFO *)&uboot_pre_deocde[BIN_INFO_OFFSET_UBOOT]; + + lzma_inflate( + (UINT8 *)&p_uboot[1], + __builtin_bswap32(p_uboot->uiSizeComp), + (UINT8 *)p_head->CodeEntry, + __builtin_bswap32(p_uboot->uiSizeUnComp), + (UINT8 *)_lzma_tmp_start, + (UINT32)(_lzma_tmp_end - _lzma_tmp_start) + ); + + UINT32 No_CPU; + No_CPU = *(UINT32 *)0xF9C00004; + No_CPU &= 0x3; + + if (No_CPU) { + extern char _load_core2_jump_program_start_base[]; + extern char _load_core2_jump_program_end_base[]; + extern char _load_core2_entry_program_start_base[]; + extern char _load_core2_entry_program_end_base[]; + UINT32 code2JumpCodelen = _load_core2_jump_program_end_base - _load_core2_jump_program_start_base; + UINT32 code2EntryCodelen = _load_core2_entry_program_end_base - _load_core2_entry_program_start_base; + UINT32 core2_entry1_addr = 0x00000000; + //UINT32 core2_entry2_addr = 0x1FFC0000; + UINT32 core2_entry2_addr = (_SDRAM_SIZE_ / 8) * 1024 * 1024 - ALIGN_CEIL(code2EntryCodelen, 0x10000); + // copy core2 jump code to dram 0x0 + utl_memcpy((void *)core2_entry1_addr, _load_core2_jump_program_start_base, code2JumpCodelen); + CPUflushWriteCache(core2_entry1_addr, code2JumpCodelen);; + //debug_msg_var("core2_jump_program", (int)_load_core2_jump_program_start_base); + //debug_msg_var("code2JumpCodelen", (int)code2JumpCodelen); + debug_msg_var("core2_entry2_addr", (int)core2_entry2_addr); + + // copy core2 entry code into the bottom of memory + *(volatile UINT32 *)(NVT_CORE2_START) = core2_entry2_addr; + utl_memcpy((void *)core2_entry2_addr, _load_core2_entry_program_start_base, code2EntryCodelen); + CPUflushWriteCache(core2_entry2_addr, code2EntryCodelen); + //debug_msg_var("core2_entry_program", (int)_load_core2_entry_program_start_base); + //debug_msg_var("code2EntryCodelen", (int)code2EntryCodelen); + *(volatile UINT32 *)0xFE0B9000 = 0; + //debug_msg_var("0xFE0B9000=", (int)*(volatile UINT32 *)0xFE0B9000); + //reset core2 + //debug_msg("reset core2\r\n"); + bl_core2_reset(); + } + + debug_msg_var("j", p_head->CodeEntry); + + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)p_head->CodeEntry; + p_func(); + } + + return p_head->CodeEntry; +} +#endif +//--------------------------------------------------------------------------- +// Static function +//--------------------------------------------------------------------------- +/* + BL_RunPartOne + + Expend loader if use compress + + @return void +*/ +_THUMB2 static void BL_RunPartOne(void) +{ +#if (_LOADER_COMPRESSED_ == ENABLE) + UINT8 *in_addr = (UINT8 *)(_loader_exec_compress_load_cpu_addr); + UINT8 *out_addr = (UINT8 *)(_loader_exec_compres_start); + UINT32 uiCompressedOutSize; + unsigned int out_size; + + // Get decompress size within specific header + uiCompressedOutSize = (((UINT32)*(in_addr + 12)) << 24) + + (((UINT32)*(in_addr + 13)) << 16) + + (((UINT32)*(in_addr + 14)) << 8) + + ((UINT32)*(in_addr + 15)); + + // Decompress loader image + out_size = LZ_Uncompress((unsigned char *)(in_addr + LDC_HEADER_SIZE), (unsigned char *)(out_addr), uiCompressedOutSize); + + // Need to clean data cache + CPUInvalidateICacheAll(); + CPUCleanInvalidateDCacheAll(); + + // Copy data to its execution address + in_addr = (UINT8 *)((UINT32)_loader_exec_compres_start+(UINT32)_loader_data_cpu_addr - (UINT32)_loader_exec_end_base); + out_addr = (UINT8 *)(_loader_data_start_base); + out_size =(UINT32) _loader_data_size; + + //PrintDec2Hex((UINT32)in_addr); + //PrintDec2Hex((UINT32)out_addr); + //PrintDec2Hex((UINT32)out_size); + utl_memcpy((void *)out_addr, in_addr, out_size); + + debug_msg("\r\nUNZOK!"); +#else + debug_msg("\r\nOK!"); +#endif +} + + +_THUMB2 void entry(void) +{ + UINT32 reg; +#if HVYLOAD_TEST +// UINT32 src; +// UINT32 i; +// UINT32 reg; +#endif + void (*image_entry)(void) = (void *)LOAD_ADDR; + +#ifndef HEAVY_LOAD + //struct spi_flash *spi_chip = NULL; + //unsigned int reg;//, i; + +#ifdef COMPRESS + unsigned char *in_ptr = (unsigned char *)IMAGE_ADDR; + unsigned char *out_ptr = (unsigned char *)LOAD_ADDR; + unsigned int img_addr = IMAGE_ADDR; +#else + unsigned int img_addr = LOAD_ADDR; +#endif +#endif //HEAVY_LOAD + + + // Run part one loader + // If using compressed loader, just decompress the loader image at first! + BL_RunPartOne(); + + platform_setup(REG_PMU_BASE, REG_H2X_BASE, REG_DMAC030_BASE, REG_TMR010_BASE); +#if (_FPGA_EMULATION_ == 1 ) + debug_msg_var("\r\nperiphbase=", read_periphbase()); +#endif +#ifndef USE_SCP +/* +#ifdef CONFIG_MT + debug_msg("MT test\r\n"); +#else +#ifdef CONFIG_RA + reset_cpu(REG_WDT_BASE, 0xffffffff); +#else + reset_cpu(REG_WDT_BASE, SYS_CLK * 160); +#endif //CONFIG_RA +#endif //CONFIG_MT +*/ + + show_evb_message(); + + #if (_FPGA_EMULATION_ == 0) + cpu_change_armpll(); + #endif + + #if 0 + fLib_USB_Update_FW(); + #endif + + +#if (_FPGA_EMULATION_ == 0) + //set_fire(REG_PMU_BASE); +#endif + + +#if (_FPGA_EMULATION_ == 0) + //write_reg(REG_PMU_BASE + 0x20, 0x0000A001); /* DDR0 + DDR1 phy reset */ + //write_reg(REG_PMU_BASE + 0x20, 0x0000E001); + //set_ddr0(REG_DDR0_BASE); +#endif + + //debug_msg("0xFE030000 = 0x"); + //debug_msg(Dec2HexStr(*(UINT32 *)0xFE030000)); + //debug_msg("\r\n"); + reg = *(UINT32 *)0xFE030000; + reg = reg&0xFFFFFF3F; + *(UINT32 *)0xFE030000 = reg; + //debug_msg("Force bit6/7 to 0\r\n"); + //debug_msg("0xFE030000 = 0x"); + //debug_msg(Dec2HexStr(*(UINT32 *)0xFE030000)); + //debug_msg("\r\n"); + + +#ifdef DDR1_1200_SZ_4Gb +#ifndef CONFIG_FPGA + debug_msg("DDR1 1200 4Gb\r\n"); + set_ddr1(REG_DDR1_BASE); +#endif +#endif //DDR1_1200_SZ_4Gb + +#ifdef DDR1_1600_SZ_4Gb +#ifndef CONFIG_FPGA + debug_msg("DDR1 1600 4Gb\r\n"); + set_ddr1(REG_DDR1_BASE); +#endif +#endif //DDR1_1600_SZ_4Gb + +#ifdef DDR1_1800_SZ_1Gb + debug_msg("DDR1 1800 1Gb\r\n"); + set_ddr1(REG_DDR1_BASE); +#endif //DDR1_1800_SZ_1Gb + +#ifdef DDR1_1800_SZ_2Gb + debug_msg("DDR1 1800 2Gb\r\n"); + set_ddr1(REG_DDR1_BASE); +#endif //DDR1_1800_SZ_2Gb + +#ifdef DDR1_1800_SZ_4Gb +#if (_FPGA_EMULATION_ == 0) + debug_msg("DDR1 1800 4Gb\n"); + set_ddr1(REG_DDR1_BASE); +#endif +#endif //DDR1_1800_SZ_4Gb + + + //write_reg(REG_PMU_BASE + 0x198, 0x10); //remap + + /* modify DDR base address if user update DDR size */ + //set_bus(REG_AXIC_BASE); +#else + heavy_load_test(); +#endif //USE_SCP + +#if HVYLOAD_TEST +heavy_load_test(); +#endif + +#if DRAM_TEST +printf("mem r/w test ~~ \r\n"); + +for(i=0;i<0x100000;i=i+4) +{ + write_reg( i, i); +} + +for(i=0;i<0x100000;i=i+4) +{ + src = read_reg(i); + if(src !=i) + { + printf("mem r/w failed ~~ \r\n"); + while(1); + } +} +printf("mem r/w pass \r\n"); +#endif + +#if WDT_TEST_ENABLE + //UINT32 reg; + //if ((INREG32(0xF0020010) & 0x3) != 1) + //debug_msg(("CPU CLKSEL != PLL8 !!\r\n")); + +#if (WDT_TEST_CASE == WDT_CASE_NORMAL) + //gpio_setDir(Y_GPIO_Y, GPIO_DIR_OUTPUT); + *(UINT32 *)(0xF0070024) = 1; + //gpio_setPin(Y_GPIO_Y); + *(UINT32 *)(0xF0070004) = 1; + debug_msg(("Set PGPIO0 ~ \r\n")); + +#elif (WDT_TEST_CASE == WDT_CASE_INTRESET) + reg = (*(UINT32 *)(WDT_REG_BASE_ADDR+0x80))&0xFF; + + if(reg) + debug_msg("count >0\r\n"); + else + debug_msg("count = 0\r\n"); + + enableWdtClock(); + reg = WDT_RESET_NUM0_EN |WDT_MODE_RESET | WDT_EN_MSK|WDT_KEYCTRL(WDT_KEY_VALUE); + write_reg(WDT_CTRL_REG, reg); + debug_msg("Wait WDT int reset\r\n"); + +#elif (WDT_TEST_CASE == WDT_CASE_EXTRESET) + reg = (*(UINT32 *)(0xfe8a0000+0x80))&0xFF; + if(reg) + debug_msg("count >0\r\n"); + else + debug_msg("count = 0\r\n"); + + //enableWdtPCLK + write_reg (0xFE00005C ,0xFFFFFFFF); + + reg =*(UINT32 *)(0xfe000078); + write_reg (0xFE000078 ,reg&0xFFFF7FFF); + + //reg = 0x33|WDT_KEYCTRL(0x5A96); + reg = 0x5A960033; + write_reg(0xFE8A0000, reg); + debug_msg("Wait WDT ext reset\r\n"); + while(1); +#endif + while(1); + return; +#endif + + + +#ifdef MEM_TEST + debug_msg("memtest after FCS\r\n"); + memtest(); + #ifdef FCS_TEST + { + unsigned int i = 0; + while(1) { + //KPrint("Test loop %d, ", i++); + memtest(); + } + } + #endif +#endif //MEM_TEST + + + +#ifdef HEAVY_LOAD + heavy_load_test(); +#endif + + //check_storage_type(); + + /* Release SPI */ + //reg = read_reg(REG_PMU_BASE + 0x54); + //reg |= (0x1 << 11); + //write_reg(REG_PMU_BASE + 0x54, reg); + + /* Turn on SPI gating clock */ + //reg = read_reg(REG_PMU_BASE + 0x1A0); + //#if (defined(CONFIG_MT) || defined(CONFIG_RA)) + //reg = (reg & 0xCC003FFF) | 0x22AA8000; + //#else + //reg = (reg & 0xCFC03FFF) | 0x202A8000; + //#endif + //write_reg(REG_PMU_BASE + 0x1A0, reg); + + //#ifdef CONFIG_SPI_DMA + //Dma_init((1 << REQ_SPI020RX) | (1 << REQ_SPI020TX)); + //#endif + +#if 1 + + //if (flash_type == FLASH_SD) { + debug_msg("mmc bootstrap\r\n"); + + #if 0 // load rtos bin directly + /* sdhci init */ + //extern int mmc_loader(unsigned int load_addr); + debug_msg_var("loader_addr=",img_addr); + unsigned int image_size = prj_main(img_addr); + if(image_size > 0) { + goto img_boot; + } + else { + debug_msg("no mmc\n"); + } + //} else { + #else // load all-in-one firmware +#if defined(_UBOOT_BIND_ON_) + img_addr = bl_boot_bind_uboot(); +#else + debug_msg("load all-in-one fw\r\n"); + img_addr = bl_mainFlow(); +#endif + debug_msg_var("loader_addr=",img_addr); + if(img_addr > 0) { + goto img_boot; + } + else { + debug_msg("no mmc\n"); + } + #endif + #endif + + /* SPI init */ + //FTSPI020_Init(); //------------->TODO + //spi_chip = 0; + //if (!spi_chip) { + // debug_msg("SPI init fail! \n"); + // goto exit_nsboot; + //} + //} + + //if (flash_type == FLASH_NOR) { + // debug_msg("FLASH_NOR TODO\n"); + /* + image_size = fLib_NOR_Copy_Image(img_addr, LOAD_FDT_ADDR); + if (image_size < 0) { + debug_msg("image_size < 0\n"); + goto exit_nsboot; + } + */ + //} + + //if (flash_type == FLASH_SPI_NAND) { + // debug_msg("FLASH_SPI_NAND TODO\n"); + /* + image_size = fLib_SPI_NAND_Copy_Image(img_addr, LOAD_FDT_ADDR); + if (image_size < 0) { + debug_msg("image_size < 0\n"); + goto exit_nsboot; + } + */ + //} + +img_boot: + +#if 0 +#if (defined(CONFIG_MT) || defined(CONFIG_RA)) + //reset_EP(); + + #if 0 + #ifdef CONFIG_MT + /* Release UART1 */ + reg = read_reg(REG_PMU_BASE + 0x5C); + reg |= (0x1 << 23); + write_reg(REG_PMU_BASE + 0x5C, reg); + + reg = read_reg(REG_PMU_BASE + 0x78); + reg &= ~(0x1 << 10); + write_reg(REG_PMU_BASE + 0x78, reg); + + write_reg(REG_UART1_BASE + 0x8, 0x00000035); + write_reg(REG_UART1_BASE + 0xC, 0x00000083); + write_reg(REG_UART1_BASE + 0x0, 0x00000045); + write_reg(REG_UART1_BASE + 0x4, 0x00000000); + write_reg(REG_UART1_BASE + 0xC, 0x00000003); + write_reg(REG_UART1_BASE + 0x0, 0x00000030); + write_reg(REG_UART1_BASE + 0x0, 0x00000024); + #endif + #endif + + #if 0 + #ifdef CONFIG_RA + /* Release UART2 */ + reg = read_reg(REG_PMU_BASE + 0x5C); + reg |= (0x1 << 24); + write_reg(REG_PMU_BASE + 0x5C, reg); + + reg = read_reg(REG_PMU_BASE + 0x78); + reg &= ~(0x1 << 11); + write_reg(REG_PMU_BASE + 0x78, reg); + + write_reg(REG_UART2_BASE + 0x8, 0x00000035); + write_reg(REG_UART2_BASE + 0xC, 0x00000083); + write_reg(REG_UART2_BASE + 0x0, 0x00000045); + write_reg(REG_UART2_BASE + 0x4, 0x00000000); + write_reg(REG_UART2_BASE + 0xC, 0x00000003); + write_reg(REG_UART2_BASE + 0x0, 0x00000030); + write_reg(REG_UART2_BASE + 0x0, 0x00000024); + #endif + #endif + + /* jump */ + write_reg(0x0, 0xe59ff014); + write_reg(0x1C, LOAD_EP_ADDR); + //write_reg(LOAD_EP_ADDR, 0xEAFFFFFE); /* loop */ + + /* Reset secondary CPU */ + reg = read_reg(INTC_OSPREY_BASE + 0x4); + reg |= (1 << 10) | (1 << 2); + write_reg(INTC_OSPREY_BASE + 0x4, reg); + //KPrint("addr 0x%x, data 0x%x\n", INTC_OSPREY_BASE + 0x4, reg); + + //KPrint("Jump to 0x%x\n", LOAD_ADDR); + + jmpcore1();/* LOAD_ADDR 0x0f000040 */ + //image_entry(); +#endif +#endif + + //reset_EP(); + + /*KPrint("write pattern\n"); + for(i = 0; i < 0x10000000; i += 4){ + write_reg(i, i); + } + KPrint("read compare\n"); + for(i = 0; i < 0x10000000; i += 4){ + if(i != read_reg(i)) { + KPrint("compare fail\n"); + while(1); + } + }*/ + //KPrint("Boot image offset: 0x%x. Booting Image .....\n", image_size); + //write_reg(0xF9000FF8, 0x7e9f05a3); + //write_reg(0xF9000FFC, 0x1fe38ae7); + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); +// __asm__ __volatile__("mcr p15, 0, r0, c7, c1, 0"); //invalidate I-cache inner shareable +// __asm__ __volatile__("mcr p15, 0, r0, c7, c5, 0"); //I+BTB cache invalidate + +#ifdef COMPRESS + KPrint("Uncompress from 0x%x to 0x%x, size %d\n", in_ptr, out_ptr, image_size); + if(decompress(in_ptr, image_size, out_ptr) < 0) + KPrint("Uncompress fail\n"); +#endif + + image_entry(); + +//exit_nsboot: +// return; +} diff --git a/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/main.h b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/main.h new file mode 100755 index 000000000000..e54a5c09102a --- /dev/null +++ b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/main.h @@ -0,0 +1,36 @@ +/** + @file main.h + @brief Header file for main function + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ +#ifndef _MAIN_H +#define _MAIN_H + +#include "constant.h" + +// FW checking method, support checksum & CRC now +#define FW_CHECK_NOCHECK 0 +#define FW_CHECK_CHECKSUM 1 +#define FW_CHECK_CRC 2 +#define DRAM_RANGE_SCAN_EN (DISABLE) +#define _LOADER_COMPRESSED_ (ENABLE) +#define _LOADER_DUTY_CALIBRATION_ (DISABLE) +#define _LOADER_DUTY_CALIBRATION_LOG_ (DISABLE) +#define FW_CHECK_METHOD (FW_CHECK_CHECKSUM) + + + + +#define LDC_HEADER_SIZE 16 +#if (_LOADER_COMPRESSED_ == ENABLE) +// header size for compressed loader (16 bytes) +//#define LDC_HEADER_SIZE 16 + +#include "lz.h" +#endif + +extern UINT32 main(void) __attribute__ ((section (".part1"))); + + +#endif diff --git a/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/nand_ids.c b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/nand_ids.c new file mode 100755 index 000000000000..c0a27da5b555 --- /dev/null +++ b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/nand_ids.c @@ -0,0 +1,49 @@ +/* + * nand_ids.c + * + * nand id table + * + * Copyright (c) 2018 Novatek, ALL Rights Reserve + */ +#include "main.h" +#include "nand.h" +#include "constant.h" +#include "compiler.h" +#include "mmc_api.h" +#include "spi020.h" +#include "fuart.h" +#include "timer.h" +#include "debug.h" +#include "pll.h" + +#define _THUMB2 __attribute__((target("thumb"))) + + +NAND_FLASH_DEV nvt_nand_ids[] = { + // manufactor ID device id page size(unit:bytes) erase unit(block size, unit:bytes) QE type plane type + SPI_ID_NAND(_SNAND_MXIC_ID, _MXIC_SPI_NAND_1Gb, 2048, 0x20000, SPINAND_QE_FEATURE2_B0H_BIT0_TYPE1, SPINAND_2_PLANE_NONE), + SPI_ID_NAND(_SNAND_TOSHIBA_ID, 0xCD, 4096, 0x40000, SPINAND_QE_NONE, SPINAND_2_PLANE_NONE), + //DS35Q2GAxxx + SPI_ID_NAND(0xE5, 0x72, 2048, 0x20000, SPINAND_QE_NONE, SPINAND_2_PLANE_COLUMN_ADDR_BIT_12_AS_PLANE_SEL), + //MX35LFxGE4AB + SPI_ID_NAND(_SNAND_MXIC_ID, 0x22, 2048, 0x20000, SPINAND_QE_NONE, SPINAND_2_PLANE_COLUMN_ADDR_BIT_12_AS_PLANE_SEL), + +}; + +_THUMB2 BOOL nand_identify(UINT32 uiMfgID, UINT32 uiTypeID, PSPINAND_IDENTIFY pIdentify) +{ + UINT32 ui_nand_ids; + BOOL nand_ids_found = FALSE; + for (ui_nand_ids = 0; ui_nand_ids < (sizeof(nvt_nand_ids) / sizeof(NAND_FLASH_DEV)); ui_nand_ids++) { + if (uiMfgID == nvt_nand_ids[ui_nand_ids].mfr_id && uiTypeID == nvt_nand_ids[ui_nand_ids].dev_id) { + // For SPI Nor flash only + pIdentify->pagesize = nvt_nand_ids[ui_nand_ids].pagesize; + pIdentify->erasesize= nvt_nand_ids[ui_nand_ids].erasesize; + pIdentify->qe_opt = nvt_nand_ids[ui_nand_ids].qe_opt; + pIdentify->plane_opt= nvt_nand_ids[ui_nand_ids].plane_opt; + nand_ids_found = TRUE; + break; + } + } + return nand_ids_found; +} diff --git a/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c new file mode 100755 index 000000000000..6436d4fb888c --- /dev/null +++ b/board/novatek/na51068/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c @@ -0,0 +1,43 @@ +/* + * nand_ids.c + * + * nand id table + * + * Copyright (c) 2018 Novatek, ALL Rights Reserve + */ +#include "main.h" +#include "nor.h" +#include "constant.h" +#include "compiler.h" +#include "mmc_api.h" +#include "spi020.h" +#include "fuart.h" +#include "timer.h" +#include "debug.h" +#include "pll.h" + +#define _THUMB2 __attribute__((target("thumb"))) + + +NOR_FLASH_DEV nvt_nor_ids[] = { + // manufactor ID device id capacity id, dual read quad type flash size + SPI_ID_NOR(0xEF, 0x40, 0x18, TRUE, SPI_QUAD_TYPE2, (16<<20)), +}; + +_THUMB2 BOOL nor_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + BOOL nor_ids_found = FALSE; + UINT32 ui_nor_ids; + for (ui_nor_ids = 0; ui_nor_ids < (sizeof(nvt_nor_ids) / sizeof(NOR_FLASH_DEV)); ui_nor_ids++) { + if (uiMfgID == nvt_nor_ids[ui_nor_ids].mfr_id && uiTypeID == nvt_nor_ids[ui_nor_ids].dev_id && uiCapacityID == nvt_nor_ids[ui_nor_ids].capacity_id) { + // For SPI Nor flash only + pIdentify->bDualRead = nvt_nor_ids[ui_nor_ids].bDualRead; + pIdentify->uiQuadReadType = nvt_nor_ids[ui_nor_ids].uiQuadReadType; + pIdentify->uiFlashSize = nvt_nor_ids[ui_nor_ids].uiFlashSize; + nor_ids_found = TRUE; + break; + } + } + + return nor_ids_found; +} diff --git a/board/novatek/na51068/loader/LibExt/Makefile b/board/novatek/na51068/loader/LibExt/Makefile new file mode 100755 index 000000000000..c37cab5becbe --- /dev/null +++ b/board/novatek/na51068/loader/LibExt/Makefile @@ -0,0 +1,62 @@ +include ../MakeCommon/MakeOption.txt + +ifeq "$(shell uname)" "Linux" +MAKEFILE_SEARCH := $(sort $(dir $(shell find . -name 'Makefile'))) +else +MAKEFILE_SEARCH := $(sort $(dir $(shell find . -name \'Makefile\'))) +endif +mk_all := $(filter-out ./, $(MAKEFILE_SEARCH)) + +ifeq "$(ISOLATE_DEP)" "ON" +.PHONY: all $(mk_all) clean rebuild debug release dep + +all: + @make dep + @make debug + @make release +else +.PHONY: all $(mk_all) clean rebuild debug release + +all: rm_log $(mk_all) +endif + +$(mk_all): + @$(MAKE) --directory=$@ $(MAKECMDGOALS) + +rm_log: +ifeq "$(CLEAN_LOG)" "ON" + @-rm -f log*.txt +endif + +PRJ_NAME_ALL = $(shell find -name 'Makefile' -not -path "./Makefile" -print | xargs grep "PRJ_NAME" | sed 's/[[:digit:][:alpha:][:punct:]]*:PRJ_NAME[ ]*=[ ]*//g') +LIB_R = $(addprefix "../ARC/Lib/Release/", $(addsuffix ".a", $(PRJ_NAME_ALL))) +LIB_D = $(addprefix "../ARC/Lib/Debug/", $(addsuffix "_D.a", $(PRJ_NAME_ALL))) + +clean: + @-echo Clean LibExt ... \ + && find ./ -type d -name '*_Data' | xargs rm -rf --no-preserve-root $(LIB_D) $(LIB_R) log*.txt lint*.txt + +ifeq "$(ISOLATE_DEP)" "ON" +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: rm_log $(mk_all) +else +rebuild: rm_log $(mk_all) +endif + +debug: rm_log $(mk_all) + +release: rm_log $(mk_all) + +rm_lint_log: + @-rm -f lint*.txt + +lint: rm_lint_log $(mk_all) + +lintclean: + @-echo Clean LibExt lint data ... \ + && find ./ -type d -name 'CheckData' | xargs rm -rf --no-preserve-root lint*.txt \ No newline at end of file diff --git a/board/novatek/na51068/loader/MakeCommon/InputSource.txt b/board/novatek/na51068/loader/MakeCommon/InputSource.txt new file mode 100755 index 000000000000..631265678903 --- /dev/null +++ b/board/novatek/na51068/loader/MakeCommon/InputSource.txt @@ -0,0 +1,177 @@ +#---------------------------------------------------------------------- +# get the source full path, convert upper case extension to lower case +#---------------------------------------------------------------------- +ifeq "$(shell uname)" "Linux" +SRC := $(addprefix $(shell pwd)/, $(SRC:.C=.c)) +ASM := $(addprefix $(shell pwd)/, $(ASM:.s=.S)) +CPP_SRC := $(addprefix $(shell pwd)/, $(CPP_SRC:.CPP=.cpp)) +else +SRC := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(SRC:.C=.c)) +ASM := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(ASM:.s=.S)) +CPP_SRC := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(CPP_SRC:.CPP=.cpp)) +endif + +#---------------------------------------------------------------------- +# set the basic include directories +#---------------------------------------------------------------------- +# Get working directory +MYPWD := $(shell pwd) +ALG_PATH := $(findstring /Alg/, $(MYPWD)) +APP_PATH := $(findstring /App/, $(MYPWD)) +APPEXT_PATH := $(findstring /AppExt/, $(MYPWD)) +LIB_PATH := $(findstring /Lib/, $(MYPWD)) +LIBEXT_PATH := $(findstring /LibExt/, $(MYPWD)) +DRV_PATH := $(findstring /Drv/, $(MYPWD)) +DRVEXT_PATH := $(findstring /DrvExt/, $(MYPWD)) +COM_PATH := $(findstring /Common/, $(MYPWD)) +UTIL_PATH := $(findstring /Common/Common_src/Utility, $(MYPWD)) +PRJ_PATH := $(shell find ./ -maxdepth 1 -name MakeConfig.txt) + +BASE_INC_DIR := $(filter %../../Include, $(INC_DIR)) +APPEXT_INC_DIR := -I$(BASE_INC_DIR)/AppExt +APP_INC_DIR := -I$(BASE_INC_DIR)/App +LIBEXT_INC_DIR := -I$(BASE_INC_DIR)/LibExt +LIB_INC_DIR := -I$(BASE_INC_DIR)/Lib +DRVEXT_INC_DIR := -I$(BASE_INC_DIR)/DrvExt +DRV_INC_DIR := -I$(BASE_INC_DIR)/Drv +LIBC_INC_DIR := -I$(BASE_INC_DIR)/Common/LibC + +#BASE_INC_ALG_DIR := $(BASE_INC_DIR)/../Alg/Include +#BASE_INC_PROTECT_DIR := $(subst Include,IncludeProtected,$(BASE_INC_DIR)) + +#change replace /Include/ to /IncludeProtected/ +define protected +$(subst ../../Include/,../../IncludeProtected/,$1) +endef + + +ifeq "$(USE_ECOS_KERNEL)" "ON" +#eCos include path like ThirdParty/eCos/Include ThirdParty/live555/Include +ECOS_INC_DIR := $(addprefix -I,$(addsuffix /include, $(shell find $(BASE_INC_DIR)/../ThirdParty/ -maxdepth 1 -mindepth 1 -type d))) +endif + +ifeq "$(shell uname)" "Linux" +INC_DIR := $(addprefix -I, $(sort $(dir $(shell find $(INC_DIR) -name '*.h')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_PROTECT_DIR) -name '*.h')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_ALG_DIR) -name '*.h')))) +else +INC_DIR := $(addprefix -I, $(sort $(dir $(shell find $(INC_DIR) -name \'\*\.h\')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_PROTECT_DIR) -name \'\*\.h\')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_ALG_DIR) -name \'\*\.h\')))) +endif + +# For uITRON (MIPS) platform, we use proprietary standard C library. +# We must filter out proprietary header file if we are in others platform (ARM or eCos...) +# Filter out standard C library header file +# ifeq "$(ARCH)" "ARM" +# INC_DIR := $(filter-out $(LIBC_INC_DIR)/%, $(INC_DIR)) +# endif + +ifeq "$(USE_ECOS_KERNEL)" "ON" + INC_DIR := $(filter-out $(LIBC_INC_DIR)/%, $(INC_DIR)) + INC_DIR += $(ECOS_INC_DIR) +endif + +ifeq "$(INCLUDE_RULE)" "ON" + +#---------------------------------------------------------------------- +# Filter out upper layer's include path +#---------------------------------------------------------------------- + + +# /Common can't access /App or /AppExt or /Lib or /LibExt or /Drv or /DrvExt +# except: /Common/Common_src/Utility can access /Drv +ifneq "$(COM_PATH)" "" +ifneq "$(UTIL_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)% $(DRVEXT_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%) $(call protected,$(DRVEXT_INC_DIR)%),$(INC_DIR)) +else +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)% $(DRVEXT_INC_DIR)% $(DRV_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%) $(call protected,$(DRVEXT_INC_DIR)%) $(call protected,$(DRV_INC_DIR)%),$(INC_DIR)) +endif +endif + +# /Drv can't access /App or /AppExt or /Lib or /LibExt +ifneq "$(DRV_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%),$(INC_DIR)) +endif + +# /DrvExt can't access /App or /AppExt or /Lib or /LibExt +ifneq "$(DRVEXT_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%), $(INC_DIR)) +endif + +# /Lib can't access /App or /AppExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%), $(INC_DIR)) +endif + +# /LibExt can't access /App or /AppExt +ifneq "$(LIBEXT_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%), $(INC_DIR)) +endif + +#---------------------------------------------------------------------- +# Filter out under layer's include path +#---------------------------------------------------------------------- + +# /App can't access /Drv +#ifneq "$(APP_PATH)" "" +#INC_DIR := $(filter-out $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +# /App can't access /DrvExt or /LibExt +ifneq "$(APP_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)% $(LIBEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /AppExt can't access /Drv +#ifneq "$(APPEXT_PATH)" "" +#INC_DIR := $(filter-out $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +# /Lib can't access /DrvExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /Prj can't access /Drv or /DrvExt +#ifneq "$(PRJ_PATH)" "" +#INC_DIR := $(filter-out $(DRVEXT_INC_DIR)% $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +ifneq "$(UI_STYLE)" "" +ifeq ($(filter $(UI_STYLE), $(UI_STYLE_ALL)),) +$(error add your style into $$UI_STYLE_ALL in MakeConfig.txt) +else +PRJ_FILT_OUT := $(filter-out $(UI_STYLE), $(UI_STYLE_ALL)) +endif +PRJ_FILT_OUT_DIR := $(addsuffix %,$(addprefix -I./SrcCode/UIWnd/, $(subst UI_STYLE_,,$(PRJ_FILT_OUT)))) +#INC_DIR := $(shell echo $(INC_DIR)|tr a-z A-Z) +INC_DIR := $(filter-out $(PRJ_FILT_OUT_DIR) , $(INC_DIR)) +endif + +#---------------------------------------------------------------------- +# Filter out external layer's include path +#---------------------------------------------------------------------- + +# /Drv can't access /DrvExt +ifneq "$(DRV_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /Lib can't access /LibExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(LIBEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /App can't access /AppExt +ifneq "$(APP_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)%, $(INC_DIR)) +endif + +endif \ No newline at end of file diff --git a/board/novatek/na51068/loader/MakeCommon/MakeCommon.txt b/board/novatek/na51068/loader/MakeCommon/MakeCommon.txt new file mode 100755 index 000000000000..29b5304dad2e --- /dev/null +++ b/board/novatek/na51068/loader/MakeCommon/MakeCommon.txt @@ -0,0 +1,651 @@ +#---------------------------------------------------------------------- +# Get the source full path, include directories +#---------------------------------------------------------------------- +# query SRC, ASM, INC_DIR +include $(MAKE_COMMON_DIR)/InputSource.txt + +#---------------------------------------------------------------------- +# set the basic ASM flags +# PLATFORM_AFLAGS := -march=armv7-a -mcpu=cortex-a9 -mabi=aapcs -msoft-float +# -mfloat-abi=softfp <==> -mfloat-abi=hard +#---------------------------------------------------------------------- +ifeq "$(FPU)" "hard" +PLATFORM_AFLAGS := -mcpu=$(CPU) -mfpu=neon -mfloat-abi=$(FPU) +else +PLATFORM_AFLAGS := -mcpu=$(CPU) -mfloat-abi=$(FPU) +endif + + + +#---------------------------------------------------------------------- +# set the basic C flags +# Reference +# http://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/ +# http://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/Option-Summary.html#Option-Summary +#---------------------------------------------------------------------- +#---------------------------------------------------------------------- +# Overall Options +#---------------------------------------------------------------------- +# -c : Compile the source files, but do not link +# -pipe : Use pipes rather than temporary files for communication between the various stages of compilation +PLATFORM_CFLAGS := -c -pipe + +#---------------------------------------------------------------------- +# Machine Dependent Options +#---------------------------------------------------------------------- +# -march=24kec : Generate code that will run on MIPS 24KEc +# -mtune=24kec : Optimize for MIPS 24KEc +# -mdsp : Use revision 1 of the MIPS DSP ASE +# -EL : Generate little-endian code +# -msoft-float : Do not use floating-point coprocessor instructions +# -marm : Tell compiler do not build c code as thumb2 instruction +#---------------------------------------------------------------------- +ifeq "$(USE_NEON)" "on" +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=softfp -mfpu=neon-fp-armv8 -ftree-vectorize +else +ifeq "$(FPU)" "hard" +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=$(FPU) -mfpu=neon -ftree-vectorize +else +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=$(FPU) +endif +endif +# PLATFORM_CFLAGS += -mtune=$(CPU) -march=armv7-a -marm -mhard-float -mfpu=neon-vfpv4 -mno-thumb-interwork -mno-sched-prolog +# PLATFORM_CFLAGS += -mtune=$(CPU) -march=armv7-a -marm -msoft-float -mno-thumb-interwork -mno-sched-prolog + +#---------------------------------------------------------------------- +# Warning Options +#---------------------------------------------------------------------- +# -Wall : This enables all the warnings about constructions that some users consider questionable, +# and that are easy to avoid (or modify to prevent the warning), even in conjunction with macros. +# NOTE: -Wall turns on the following warning flags: +# -Waddress +# -Warray-bounds (only with -O2) +# -Wc++11-compat +# -Wchar-subscripts +# -Wenum-compare (in C/ObjC; this is on by default in C++) +# -Wimplicit-int (C and Objective-C only) +# -Wimplicit-function-declaration (C and Objective-C only) +# -Wcomment +# -Wformat +# -Wmain (only for C/ObjC and unless -ffreestanding) +# -Wmaybe-uninitialized +# -Wmissing-braces (only for C/ObjC) +# -Wnonnull +# -Wparentheses +# -Wpointer-sign +# -Wreorder +# -Wreturn-type +# -Wsequence-point +# -Wsign-compare (only in C++) +# -Wstrict-aliasing +# -Wstrict-overflow=1 +# -Wswitch +# -Wtrigraphs +# -Wuninitialized +# -Wunknown-pragmas +# -Wunused-function +# -Wunused-label +# -Wunused-value +# -Wunused-variable +# -Wvolatile-register-var +# -Wundef : Warn if an undefined identifier is evaluated in an `#if' directive +# -Wsign-compare : Warn when a comparison between signed and unsigned values could produce an incorrect result when the signed value is converted to unsigned +# -Wno-missing-braces : Trun off "Warn if an aggregate or union initializer is not fully bracketed". For XXX = {0}; statement. +# -Wstrict-prototypes : Warn if a function is declared or defined without specifying the argument types +# -Wimplicit-function-declaration : Warn when a function is used before being declared +# -Wmissing-prototypes : Warn about global funcs without prototypes +# -Wmissing-declarations: Warn about global funcs without previous declarations +# -Werror : Warnning as error +#---------------------------------------------------------------------- +PLATFORM_CFLAGS += -Wall -Wundef -Wsign-compare -Wno-missing-braces -Wstrict-prototypes -Wno-unused-const-variable -Wno-misleading-indentation +ifeq "$(OUTPUT_FILE)" "BIN" +else +ifeq "$(INCLUDE_RULE)" "ON" +# PLATFORM_CFLAGS += -Werror=implicit-function-declaration -Werror=missing-prototypes -Werror=missing-declarations + PLATFORM_CFLAGS += -Wimplicit-function-declaration -Wmissing-prototypes -Wmissing-declarations +endif +endif + +ifeq "$(shell uname)" "Linux" +PLATFORM_CFLAGS += -Werror +endif + +#---------------------------------------------------------------------- +# C Language Options +#---------------------------------------------------------------------- +# -fno-builtin : Don't recognize built-in functions that do not begin with `__builtin_' as prefix +# -ffreestanding: Assert that compilation takes place in a freestanding environment +#---------------------------------------------------------------------- +# Code Generation Options +#---------------------------------------------------------------------- +# -fno-common : The compiler should place uninitialized global variables in the data section of the object file, rather than generating them as common blocks +# -fshort-wchar : Override the underlying type for `wchar_t' to be `short unsigned int' instead of the default for the target. +#---------------------------------------------------------------------- +# Optimization Options +#---------------------------------------------------------------------- +# -fno-strict-aliasing : Do not warn about code that breaks strict aliasing rules +# -fno-optimize-sibling-calls : Don't optimize sibling and tail recursive calls +# -fno-omit-frame-pointer : Keep the frame pointer in a register for functions that don't need one +#---------------------------------------------------------------------- +PLATFORM_CFLAGS += -fno-builtin -ffreestanding -fno-common -fshort-enums -fshort-wchar -fno-strict-aliasing -fno-optimize-sibling-calls -fno-omit-frame-pointer + +# C Language Options for eCos system +ifeq "$(USE_ECOS_KERNEL)" "ON" + PLATFORM_CFLAGS += -D__ECOS +else + PLATFORM_CFLAGS += -nostdinc -D__UITRON +# For make dep + GCCFLAGS +=-D__UITRON +endif + +#8313 +MFLAGS = -DPLATFORM_8321 +#MFLAGS = -DDDR0_1800_SZ_4Gbx2 -DDDR1_1800_SZ_4Gb -DPLATFORM_8313 +#MFLAGS = -DDDR0_1800_SZ_4Gbx2 -DDDR1_1800_SZ_2Gb -DPLATFORM_8313 +#MFLAGS = -DDDR0_1800_SZ_4Gbx2 -DDDR1_1800_SZ_1Gb -DPLATFORM_8313 + +# Remove -Otime (There is no such option in GCC, GCC default is optimize for time) +# Replace -OSpace (-Os in GCC) +CFLAGS_D := $(filter-out -Otime, $(CFLAGS_D)) +CFLAGS_D := $(CFLAGS_D:-Ospace=-Os) +CFLAGS_R := $(filter-out -Otime, $(CFLAGS_R)) +CFLAGS_R := $(CFLAGS_R:-Ospace=-Os) + +# Slove sub-folder cannot include parent folder header file +INC_DIR += -I$(CURDIR) + +# For Debug target +CFLAGS_D += $(INC_DIR) -g -ggdb -O0 $(PLATFORM_CFLAGS) $(MFLAGS) +ASMFLAGS_D += -g $(INC_DIR) $(PLATFORM_AFLAGS) -D__ASSEMBLY__ $(MFLAGS) + +# For Release target (use -Os instead of -O2, because loader is size dominant) +CFLAGS_R += $(INC_DIR) -Os $(PLATFORM_CFLAGS) $(MFLAGS) +ASMFLAGS_R += $(INC_DIR) $(PLATFORM_AFLAGS) -D__ASSEMBLY__ $(MFLAGS) + +# Generate debug symbol in release target +ifeq "$(RELEASE_SYMBOL)" "ON" + CFLAGS_R += -g -ggdb + ASMFLAGS_R += -L -g +endif + +# Generate debug callback of entry and exit to functions +ifeq "$(INSTRUMENT_FUNCTION)" "ON" + CFLAGS_R += -finstrument-functions -finstrument-functions-exclude-file-list=Common_src/LibC,Common_src/Kernel,Common_src/Debug,Common_src/OS,Include/Common/LibC,Include/Common/Kernel,Include/Common/Debug,Include/Common/OS,Drv_src/Driver,Include/Drv/Driver + CFLAGS_D += -finstrument-functions -finstrument-functions-exclude-file-list=Common_src/LibC,Common_src/Kernel,Common_src/Debug,Common_src/OS,Include/Common/LibC,Include/Common/Kernel,Include/Common/Debug,Include/Common/OS,Drv_src/Driver,Include/Drv/Driver + CFLAGS_R += -D_INSTRUMENT_FUNCTION_=1 + CFLAGS_D += -D_INSTRUMENT_FUNCTION_=1 +else + CFLAGS_R += -D_INSTRUMENT_FUNCTION_=0 + CFLAGS_D += -D_INSTRUMENT_FUNCTION_=0 +endif + +#---------------------------------------------------------------------- +# Generate one ELF section for each function +# Only apply to release target +# Note: -fdata-sections will generate larger code size +#---------------------------------------------------------------------- +ifeq "$(SECTION_BY_FUNC)" "ON" +# CFLAGS_R += -ffunction-sections -fdata-sections + CFLAGS_R += -ffunction-sections +endif + +#---------------------------------------------------------------------- +# Definition for source code check build debug or release +#---------------------------------------------------------------------- +CFLAGS_R += -DNDEBUG +CFLAGS_D += -D_DEBUG + +#---------------------------------------------------------------------- +# FPGA notification for drivers +#---------------------------------------------------------------------- +ifeq "$(EMULATION)" "ON" + ifeq "$(FPGA_EMULATION)" "ON" + CFLAGS_R += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + CFLAGS_D += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + GCCFLAGS += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + else + CFLAGS_R += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + CFLAGS_D += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + GCCFLAGS += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + endif +else + CFLAGS_R += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 + CFLAGS_D += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 + GCCFLAGS += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 +endif + +#---------------------------------------------------------------------- +# PM demo based on customized building way +#---------------------------------------------------------------------- +ifeq "$(PM_DEMO)" "ON" + CFLAGS_R += -D_PM_DEMO_=1 + CFLAGS_D += -D_PM_DEMO_=1 +else + CFLAGS_R += -D_PM_DEMO_=0 + CFLAGS_D += -D_PM_DEMO_=0 +endif + +#---------------------------------------------------------------------- +# GIC usage ON/OFF +#---------------------------------------------------------------------- +ifeq "$(ARM_GIC_400)" "ON" + CFLAGS_R += -D_ARM_GIC_USAGE_=1 + CFLAGS_D += -D_ARM_GIC_USAGE_=1 + ASMFLAGS_R += -D_ARM_GIC_USAGE_=1 + ASMFLAGS_D += -D_ARM_GIC_USAGE_=1 +else + CFLAGS_R += -D_ARM_GIC_USAGE_=0 + CFLAGS_D += -D_ARM_GIC_USAGE_=0 + ASMFLAGS_R += -D_ARM_GIC_USAGE_=0 + ASMFLAGS_D += -D_ARM_GIC_USAGE_=0 +endif + +#---------------------------------------------------------------------- +# Architecture definition +#---------------------------------------------------------------------- +CFLAGS_R += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 +CFLAGS_D += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 +GCCFLAGS += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 + +ifeq "$(ARCH)" "ARM" + CFLAGS_R += -D_ARCH_=_ARCH_ARM_ + CFLAGS_D += -D_ARCH_=_ARCH_ARM_ + GCCFLAGS += -D_ARCH_=_ARCH_ARM_ +else ifeq "$(ARCH)" "MIPS" + CFLAGS_R += -D_ARCH_=_ARCH_MIPS_ + CFLAGS_D += -D_ARCH_=_ARCH_MIPS_ + GCCFLAGS += -D_ARCH_=_ARCH_MIPS_ +endif + +ifeq "$(FPU)" "hard" +ASMFLAGS_D += -D_NEON_ON_=1 +ASMFLAGS_R += -D_NEON_ON_=1 +else +ASMFLAGS_D += -D_NEON_ON_=0 +ASMFLAGS_R += -D_NEON_ON_=0 +endif + +ifeq "$(CPU)" "cortex-a9" +CFLAGS_R += -D_ARM_V8_=0 +CFLAGS_D += -D_ARM_V8_=0 +ASMFLAGS_R += -D_ARM_V8_=0 +ASMFLAGS_D += -D_ARM_V8_=0 +else +CFLAGS_R += -D_ARM_V8_=1 +CFLAGS_D += -D_ARM_V8_=1 +ASMFLAGS_R += -D_ARM_V8_=1 +ASMFLAGS_D += -D_ARM_V8_=1 +endif + + +#---------------------------------------------------------------------- +# Definition from environment +#---------------------------------------------------------------------- +ifeq "$(NMAKE_DEF)" "" +CFLAGS_R += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +CFLAGS_D += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +else +CFLAGS_R += $(NMAKE_DEF) +CFLAGS_D += $(NMAKE_DEF) +endif +ifeq "$(NMAKE_DEF_ASM)" "" +ASMFLAGS_R += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +ASMFLAGS_D += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +else +ASMFLAGS_R += $(NMAKE_DEF_ASM) +ASMFLAGS_D += $(NMAKE_DEF_ASM) +endif +#---------------------------------------------------------------------- +# Set image base directory according to kernel type +# eCos : /ARC +# uITRON : /ARC_eCos +#---------------------------------------------------------------------- +ifeq "$(USE_ECOS_KERNEL)" "ON" + ifeq "$(OUTPUT_FILE)" "LIB" + # This is for library, project's image base directory is $(PRJ_NAME)_Data + # IMG_BASE_DIR looks like ../../ARC/Common (There is backslash succeeding to /ARC) + IMG_BASE_DIR := $(subst /ARC/,/ARC_eCos/,$(IMG_BASE_DIR)) + endif + ifeq "$(OUTPUT_FILE)" "BIN" + # This is for project, library doesn't have this variable + # ARC_BASE_DIR looks like ../../ARC (There is No backslash succeeding to /ARC) + ARC_BASE_DIR := $(subst /ARC,/ARC_eCos,$(ARC_BASE_DIR)) + endif + KERNEL_STR := eCos +else + KERNEL_STR := uITRON +endif + +#---------------------------------------------------------------------- +# Set branched project name +#---------------------------------------------------------------------- +ifneq "$(_BRANCH_PROJECT_)" "" + CFLAGS_R += -D_PROJECT_CODE_=$(_BRANCH_PROJECT_) + CFLAGS_D += -D_PROJECT_CODE_=$(_BRANCH_PROJECT_) +endif + +#---------------------------------------------------------------------- +# Set the directory for debug/release objects and images here +#---------------------------------------------------------------------- +OBJ_DEBUG = $(PRJ_NAME)_Data/Debug/ObjectCode +OBJ_RELEASE = $(PRJ_NAME)_Data/Release/ObjectCode +IMG_DEBUG = $(IMG_BASE_DIR)/Debug +IMG_RELEASE = $(IMG_BASE_DIR)/Release + + +#---------------------------------------------------------------------- +# Filter the GCC Command Options for debug/release mode +#---------------------------------------------------------------------- +FILTER_GCC_D = $(foreach v, $(CFLAGS_D), $(if $(findstring -D, $(v)), , $(v))) +GCC_OPT_D = $(filter-out $(INC_DIR), $(FILTER_GCC_D)) +FILTER_GCC_R = $(foreach v, $(CFLAGS_R), $(if $(findstring -D, $(v)), , $(v))) +GCC_OPT_R = $(filter-out $(INC_DIR), $(FILTER_GCC_R)) + + +#---------------------------------------------------------------------- +# Set the make outputs +#---------------------------------------------------------------------- +SRC_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(SRC:.c=.o))) +ASM_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(ASM:.S=.o))) +CPP_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(CPP_SRC:.cpp=.o))) +ALL_OBJ_D := $(ASM_OBJ_D) $(SRC_OBJ_D) $(CPP_OBJ_D) +DEPFILE_D := $(subst .o,.d,$(ALL_OBJ_D)) + +SRC_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(SRC:.c=.o))) +ASM_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(ASM:.S=.o))) +CPP_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(CPP_SRC:.cpp=.o))) +ALL_OBJ_R := $(ASM_OBJ_R) $(SRC_OBJ_R) $(CPP_OBJ_R) +DEPFILE_R := $(subst .o,.d,$(ALL_OBJ_R)) + +ifeq "$(ISOLATE_DEP)" "ON" + ALL_DEP := $(DEPFILE_D) $(DEPFILE_R) +endif + +LINT_ROOTDIR = $(PRJ_NAME)_Lint +LINT_DIR = $(PRJ_NAME)_Lint/LintData +LINT_FILE := $(addprefix $(LINT_DIR)/, $(notdir $(SRC:.c=.lob))) + +#---------------------------------------------------------------------- +# For dependency +#---------------------------------------------------------------------- +GCCFLAGS += $(INC_DIR) -c -w + +#---------------------------------------------------------------------- +# For coding rule +#---------------------------------------------------------------------- +PCLINTFLAGS = $(PCLINT_PARAMETER) $(C_DEFINE_EXT) $(INC_DIR) -i$(MAKE_COMMON_DIR)/LintRule std.lnt options.lnt $$(lintopt_file) + +#---------------------------------------------------------------------- +# define host environment is linux if we build on linux server +#---------------------------------------------------------------------- +ifeq ($(OS),Linux) +CFLAGS_R += -D_HOST_ENV_LINUX_ +CFLAGS_D += -D_HOST_ENV_LINUX_ +GCCFLAGS += -D_HOST_ENV_LINUX_ +endif + +#---------------------------------------------------------------------- +# CPP FLAGS derived from CFLAGS_R / CFLAGS_D +#---------------------------------------------------------------------- +CPPFLAGS_R = $(filter-out -Wstrict-prototypes -Wimplicit-function-declaration -Wmissing-prototypes, $(CFLAGS_R)) +CPPFLAGS_D = $(filter-out -Wstrict-prototypes -Wimplicit-function-declaration -Wmissing-prototypes, $(CFLAGS_D)) + +#---------------------------------------------------------------------- +# Set the make targets +#---------------------------------------------------------------------- +build_all: rm_log build_D build_R + +make_debug_begin: + @-echo \ + && echo Checking $(KERNEL_STR) - $(basename $(notdir $(IMAGE_D))) debug target ... \ + && mkdir -p $(IMG_DEBUG) $(OBJ_DEBUG) + +make_release_begin: + @-echo \ + && echo Checking $(KERNEL_STR) - $(basename $(notdir $(IMAGE_R))) release target ... \ + && mkdir -p $(IMG_RELEASE) $(OBJ_RELEASE) + +make_dep_begin: + @-echo Checking $(basename $(notdir $(IMAGE_R))) dependency ... \ + && mkdir -p $(OBJ_DEBUG) $(OBJ_RELEASE) + +make_lint_begin: + @-echo Checking \"$(basename $(notdir $(IMAGE_R)))\" with coding rules ... \ + && mkdir -p $(LINT_DIR) + +make_option_begin: + @-echo [GCC Command Options - Release] + @-echo $(GCC_OPT_R) + @-echo + @-echo [GCC Command Options - Debug ] + @-echo $(GCC_OPT_D) + +#---------------------------------------------------------------------- +# Compile rule functions +#---------------------------------------------------------------------- +BUILD_DATE = 20`date +'%y%m%d'` +ifeq "$(ISOLATE_DEP)" "ON" + + # $(call compile_rule,object,source,cflags) + define compile_rule + $1: $2 + @echo Compiling $(notdir $2)\ + && $(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_asm,object,source,asmflags) + define compile_rule_asm + $1: $2 + @echo Compiling $(notdir $2) \ + && $(CC) $(PLATFORM_AFLAGS) -c $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_cpp,object,source,cflags) + define compile_rule_cpp + $1: $2 + @echo Compiling $(notdir $2) \ + && $(CXX) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + +else + + # $(call compile_rule,object,source,cflags) + define compile_rule + $1: $2 + @-$(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_asm,object,source,asmflags) + define compile_rule_asm + $1: $2 + @-$(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_cpp,object,source,cflags) + define compile_rule_cpp + $1: $2 + @-$(CXX) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CXX) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + +endif + +# $(call get_obj,obj_dir,source) +get_obj = $(addprefix $1/, $(subst .c,.o,$(notdir $2))) + +# $(call get_obj_asm,obj_dir,source) +get_obj_asm = $(addprefix $1/, $(subst .S,.o,$(notdir $2))) + +# $(call get_obj,obj_dir,source) +get_obj_cpp = $(addprefix $1/, $(subst .cpp,.o,$(notdir $2))) + +# $(call compile_all,obj_dir,cflags) +define compile_all +$(foreach i, $(SRC), \ + $(call compile_rule,$(call get_obj,$1,$i),$i,$2)) +endef + +# $(call compile_all_asm,obj_dir,asmflags) +define compile_all_asm +$(foreach i, $(ASM), \ + $(call compile_rule_asm,$(call get_obj_asm,$1,$i),$i,$2)) +endef + +# $(call compile_all_cpp,obj_dir,cflags) +define compile_all_cpp +$(foreach i, $(CPP_SRC), \ + $(call compile_rule_cpp,$(call get_obj_cpp,$1,$i),$i,$2)) +endef + +#----------------------------------------------------------------- +# Dependency rule functions +#----------------------------------------------------------------- +# $(call depend_rule,depend,source) +define depend_rule +$1: $2 + @echo Depending $(notdir $2) \ + && $(GCC) -MM -MF $1 -MP -MT $(basename $1).o $(GCCFLAGS) $2 \ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) + +endef + +define depend_rule_asm +$1: $2 + @echo Depending $(notdir $2) \ + && $(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) \ + && rm -f $(basename $1).o + +endef + +define depend_rule_cpp +$1: $2 + @echo Depending $(notdir $2) \ + && $(CXX) -MM -MF $1 -MP -MT $(basename $1).o $(GCCFLAGS) $2\ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) + +endef + +# $(call get_dep,dep_dir,source) +get_dep = $(addprefix $1/, $(subst .c,.d,$(notdir $2))) + +# $(call get_dep_asm,dep_dir,source) +get_dep_asm = $(addprefix $1/, $(subst .S,.d,$(notdir $2))) + +# $(call get_dep_cpp,dep_dir,source) +get_dep_cpp = $(addprefix $1/, $(subst .cpp,.d,$(notdir $2))) + +define depend_all +$(foreach i, $(SRC), \ + $(call depend_rule,$(call get_dep,$1,$i),$i)) +endef + +# $(call dep_all_asm,dep_dir) +define depend_all_asm +$(foreach i, $(ASM), \ + $(call depend_rule_asm,$(call get_dep_asm,$1,$i),$i)) +endef + +define depend_all_cpp +$(foreach i, $(CPP_SRC), \ + $(call depend_rule_cpp,$(call get_dep_cpp,$1,$i),$i)) +endef + +#---------------------------------------------------------------------- +# LINT rule functions +#---------------------------------------------------------------------- +# $(call get_lint,lint_dir,source) +get_lint = $(addprefix $1/, $(subst .c,.lob,$(notdir $2))) + +# $(call lint_rule,output,source) +define lint_rule +$1: $2 + @-echo Review $(notdir $2) \ + && $(LT) $(PCLINTFLAGS) -u -zero -oo[$1] $2 >> $$(lint_file) + +endef + +# && $(LT) $(PCLINTFLAGS) $2 >> $$(lint_file) + +define lint_all +$1: +$(foreach i, $(SRC), \ + $(call lint_rule,$(call get_lint,$1,$i),$i)) + @-echo Review \(Internal Relation\) \ + && $(LT) $(PCLINTFLAGS) $(LINT_DIR)/"*.lob" >> $$(lint_file) + -rm -rf --no-preserve-root $(LINT_ROOTDIR) + +endef + +#---------------------------------------------------------------------- +# Goals +#---------------------------------------------------------------------- +ifeq "$(ISOLATE_DEP)" "ON" + + ifeq "$(MAKECMDGOALS)" "dep" + $(eval $(call depend_all,$(OBJ_RELEASE))) + $(eval $(call depend_all_asm,$(OBJ_RELEASE))) + $(eval $(call depend_all_cpp,$(OBJ_RELEASE))) + $(eval $(call depend_all,$(OBJ_DEBUG))) + $(eval $(call depend_all_asm,$(OBJ_DEBUG))) + $(eval $(call depend_all_cpp,$(OBJ_DEBUG))) + endif + + ifeq "$(MAKECMDGOALS)" "" + .DEFAULT_GOAL := all + endif + +else + + ifeq "$(MAKECMDGOALS)" "" + -include $(DEPFILE_D) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) + endif + + ifeq "$(MAKECMDGOALS)" "rebuild" + -include $(DEPFILE_D) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) + endif + +endif + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),debug build_pipe_D)) + -include $(DEPFILE_D) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) +endif + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),release build_pipe_R)) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) +endif + +ifeq "$(MAKECMDGOALS)" "lint" + $(eval $(call lint_all,$(LINT_DIR))) +endif diff --git a/board/novatek/na51068/loader/MakeCommon/MakeOption.txt b/board/novatek/na51068/loader/MakeCommon/MakeOption.txt new file mode 100755 index 000000000000..38dfdf15975f --- /dev/null +++ b/board/novatek/na51068/loader/MakeCommon/MakeOption.txt @@ -0,0 +1,278 @@ +ifeq "$(OPTION_LOADED)" "" + +#---------------------------------------------------------------------- +# Set option file loaded +#---------------------------------------------------------------------- +export OPTION_LOADED := TRUE + +#---------------------------------------------------------------------- +# Set the target CPU architecture +# +# ARM : ARM CPU +# MIPS : MIPS CPU (24KEc) +#---------------------------------------------------------------------- +export ARCH := ARM +#export ARCH := MIPS + +#---------------------------------------------------------------------- +# Set the toolchain +# +# ARM : ARM ADS, RealView +# GNU : GNU C, ASM and linker +#---------------------------------------------------------------------- +#export TOOLCHAIN := ARM +export TOOLCHAIN := GNU + +#---------------------------------------------------------------------- +# Set the floating point +# +# SW/HW : soft or hard float point unit +#---------------------------------------------------------------------- +#export FPU := hard +export FPU := soft + +#---------------------------------------------------------------------- +# Set the CPU type +# +# cortex-a9 or a53 +#---------------------------------------------------------------------- +export CPU := cortex-a9 +#export CPU := cortex-a53 + + +#---------------------------------------------------------------------- +# Set branched project code +# +# The project code must be 4 characters, please refer to +# http://mynvt.novatek.com.tw/deptsites/IM/Shared%20Documents/VersionControl.doc +# for more detailed information. +# Leaves this variable empty if not branched yet. +#---------------------------------------------------------------------- +export _BRANCH_PROJECT_ := + +#---------------------------------------------------------------------- +# PClint parameters +#---------------------------------------------------------------------- +export PCLINT_PARAMETER := -b -v + +#---------------------------------------------------------------------- +# Set log file option +# +# ON : Save warning/error message to log files (Win32 Default) +# OFF : Just output warning/error message to stdout (Linux Default) +#---------------------------------------------------------------------- +ifeq "$(shell uname)" "Linux" +export LOG_ERR := OFF +else +export LOG_ERR := ON +endif + +#---------------------------------------------------------------------- +# Set clean log file option +# +# ON : Clean log files before make +# OFF : Don't clean log files before make +# (You should execute "make clean" to clean the log files) +#---------------------------------------------------------------------- +export CLEAN_LOG := ON +#export CLEAN_LOG := OFF + +#---------------------------------------------------------------------- +# Keep going when encounter error or not +# +# ON : Make will keep going when encounter error +# OFF : Make will stop when encounter error +#---------------------------------------------------------------------- +#export KEEP_GOING := ON +export KEEP_GOING := OFF + +#---------------------------------------------------------------------- +# Isolate creating dependency files process +# +# ON : You have to run "make dep" to create dependency files +# OFF : dependency file will be created when making the file +#---------------------------------------------------------------------- +export ISOLATE_DEP := ON +#export ISOLATE_DEP := OFF + +#---------------------------------------------------------------------- +# Generate debug symbol in release target +# Release target won't generate debug symbol by default, if you want to +# generate debug symbol in release target, please turn on this option +# +# ON : Generate debug symbol in release target +# OFF : Don't generate debug symbol in release target (default value) +#---------------------------------------------------------------------- +#export RELEASE_SYMBOL := ON +export RELEASE_SYMBOL := OFF + +#---------------------------------------------------------------------- +# Generate debug callback of entry and exit to functions +# Only support on MIPS (This is GCC Extension) +# Reference: http://blog.linux.org.tw/~jserv/archives/001870.html +# +# ON : Generate debug callback +# OFF : Don't generate debug callback (default value) +#---------------------------------------------------------------------- +#export INSTRUMENT_FUNCTION := ON +export INSTRUMENT_FUNCTION := OFF + +#---------------------------------------------------------------------- +# Generate one ELF section for each function +# Compiler will generate one ELF section for one .c file by default. +# If the .c file contains lots of function that are unused, turn on +# this function can reduce code size. +# (Linker will remove unused section by default) +# Valid only in release target +# +# ON : One ELF section for each function +# OFF : One ELF section for each .c file (default value of ADS/GNU C compiler) +#---------------------------------------------------------------------- +export SECTION_BY_FUNC := ON +#export SECTION_BY_FUNC := OFF + +#---------------------------------------------------------------------- +# Copy bin file to storage after bin file is created +# You have to set an environment variable named "NVT_STG_PATH" (without +# quote) to work with this function. +# Example: set "NVT_STG_PATH" to "H:/" (without quote). +# +# ON : Copy bin file to storage after bin file is created +# OFF : Don't copy bin file to storage after bin file is created +#---------------------------------------------------------------------- +export COPY_BIN_2_STG := ON +#export COPY_BIN_2_STG := OFF + +#---------------------------------------------------------------------- +# Select emulation or design-in (Release code) environment +# +# ON : Emulation environment +# OFF : Design-in environment +#---------------------------------------------------------------------- +export EMULATION := ON +#export EMULATION := OFF + +#---------------------------------------------------------------------- +# Select FPGA or Realchip platform for emulation. +# Valid only when EMULATION is ON +# +# ON : FPGA platform +# OFF : Realchip platform +#---------------------------------------------------------------------- +#export FPGA_EMULATION := ON +export FPGA_EMULATION := OFF + +#---------------------------------------------------------------------- +# Set PLL OSC frequency for FPGA EMULATION +# Valid only when FPGA_EMULATION is ON +# +# For example, you should set it to 27000000 if your FPGA is connected +# with a 27 MHz OSC. +#---------------------------------------------------------------------- +export FPGA_PLL_OSC := 24000000 + +#---------------------------------------------------------------------- +# Set INCLUDE RULE +# +# ON : Enable include rule checking of platform +# OFF : Disable include rule checking of platform +#---------------------------------------------------------------------- +export INCLUDE_RULE := ON +#export INCLUDE_RULE := OFF + +#---------------------------------------------------------------------- +# Use eCos kernel or uITRON kernel +# +# ON : Use eCos kernel and light weight uITRON kernel compatible wrapper +# OFF : Use light weight uITRON kernel +#---------------------------------------------------------------------- +#export USE_ECOS_KERNEL := ON +export USE_ECOS_KERNEL := OFF + +#---------------------------------------------------------------------- +# PM demo based on customized building way +# +# ON : compile rule depends on _PM_DEMO_ that is informal way. +# OFF : formal way to build code +#---------------------------------------------------------------------- +#export PM_DEMO := ON +export PM_DEMO := OFF + +#---------------------------------------------------------------------- +# Set the dump encrypt binary tool +# +# ARCH := ARM 'Use ARMv4 as target +# ARCH := MIPS 'Use MIPS24Ke as target +#---------------------------------------------------------------------- +export ENCRYPT_DUMP := ON +#export ENCRYPT_DUMP := OFF + +#---------------------------------------------------------------------- +# Use ARM GIC as interrupt controller +# +# ON : Use GIC +# OFF : Use Lagacy interrupt as interrupt controller +#---------------------------------------------------------------------- +export ARM_GIC_400 := ON +#export ARM_GIC_400 := OFF + +#---------------------------------------------------------------------- +# Set the parameters of GNU toolchain +#---------------------------------------------------------------------- +ifeq "$(TOOLCHAIN)" "GNU" +ifeq "$(shell uname)" "Linux" + CROSS_COMPILE := /opt/ivot/gcc-linaro-6.4.1-2018.05-x86_64_arm-eabi/bin/arm-eabi- + TOOLS_DIR = ../../Tools/Bin + TOOLS_SUFFIX = +else + CROSS_COMPILE := arm-eabi- + TOOLS_DIR = ../../Tools/Bin + TOOLS_SUFFIX = .exe +endif + export CC = $(CROSS_COMPILE)gcc + export AS = $(CROSS_COMPILE)as + export LD = $(CROSS_COMPILE)ld + export AR = $(CROSS_COMPILE)ar + export OBJDUMP = $(CROSS_COMPILE)objdump + export FE = $(CROSS_COMPILE)objcopy + export NM = $(CROSS_COMPILE)nm + export LT = "C:/lint/lint-nt.exe" + export GCC = $(CROSS_COMPILE)gcc + export CXX = $(CROSS_COMPILE)g++ + export BFC = $(TOOLS_DIR)/bfc$(TOOLS_SUFFIX) + export LDNVT = $(TOOLS_DIR)/nvt-ld-op$(TOOLS_SUFFIX) + export EBIN = $(TOOLS_DIR)/encrypt_boot_dump$(TOOLS_SUFFIX) + export CFGRAM = $(TOOLS_DIR)/Configram321$(TOOLS_SUFFIX) + export ARMINC_DIR := +endif + + +#---------------------------------------------------------------------- +# Set make flags +# +# Note: Don't modify this if you didn't add new option +#---------------------------------------------------------------------- +# Slient mode +MAKEFLAGS := s + +# Keep going or not +ifeq "$(KEEP_GOING)" "ON" + MAKEFLAGS := $(MAKEFLAGS)k +endif + +#---------------------------------------------------------------------- +# OS Type and Number of CPUs +#---------------------------------------------------------------------- +NPROCS=1 +export OS:=$(shell uname -s) + +ifeq ($(OS),Linux) + NPROCS:=$(shell grep -c ^processor /proc/cpuinfo) +endif +ifeq ($(findstring CYGWIN_NT,$(OS)),CYGWIN_NT) + NPROCS:=$(NUMBER_OF_PROCESSORS) +endif + +export JOB_FLAGS:= -j$(NPROCS) + +endif diff --git a/board/novatek/na51068/loader/MakeCommon/Makefile b/board/novatek/na51068/loader/MakeCommon/Makefile new file mode 100755 index 000000000000..8661c7b2a70c --- /dev/null +++ b/board/novatek/na51068/loader/MakeCommon/Makefile @@ -0,0 +1,128 @@ +include MakeOption.txt + +ENCBIN = ../Tools/Bin/encrypt_boot_dump$(TOOLS_SUFFIX) +OTP_KEY = $(TOOLS_DIR)/aes.txt +module_Common := $(dir $(wildcard ../Common/Makefile)) +module_Drv := $(dir $(wildcard ../Drv/Makefile)) +module_DrvExt := $(dir $(wildcard ../DrvExt/Makefile)) +module_Lib := $(dir $(wildcard ../Lib/Makefile)) +module_LibExt := $(dir $(wildcard ../LibExt/Makefile)) +module_App := $(dir $(wildcard ../App/Makefile)) +module_AppExt := $(dir $(wildcard ../AppExt/Makefile)) +module_Alg := $(dir $(wildcard ../Alg/Makefile)) + +-include ../Project/ProjectConfig.txt + +ifneq "$(ACTIVE_PROJECT)" "" +module_Prj := ../Project/$(ACTIVE_PROJECT)/ +else +# Find the first folder in ../Project/ that contains "Makefile" +ifeq "$(shell uname)" "Linux" +module_Prj := $(dir $(firstword $(sort $(shell find ../Project -name 'Makefile')))) +else +module_Prj := $(dir $(firstword $(sort $(shell find ../Project -name \'Makefile\')))) +endif +endif +test_if_unix_file_fmt = $(shell cd $(1); ret=`if [ "$(OS)" == "Linux" ]; then tools/recursive_dir -t . --exclude-ext .o .a .bin .axf .7z --exclude-dir .svn .git; else tools/recursive_dir.exe -t . --exclude-ext .o .a .bin .axf .7z --exclude-dir .svn .git; fi`; echo "$$ret";) + +module_all := \ + $(module_Common) \ + $(module_Drv) \ + $(module_DrvExt) \ + $(module_Lib) \ + $(module_LibExt) \ + $(module_App) \ + $(module_AppExt) \ + $(module_Alg) + +ifeq "$(LOG_ERR)" "ON" +define copy_log + @-cp \ + $(module_Common)log*.txt \ + $(module_Drv)log*.txt \ + $(module_DrvExt)log*.txt \ + $(module_Lib)log*.txt \ + $(module_LibExt)log*.txt \ + $(module_App)log*.txt \ + $(module_AppExt)log*.txt \ + $(module_Alg)log*.txt \ + $(module_Prj)log*.txt \ + . +endef +else +define copy_log +endef +endif + +ifeq "$(ISOLATE_DEP)" "ON" +.PHONY: all rm_log $(module_all) $(module_Prj) clean rebuild debug release dep + +all: rm_log + @make dep + @make debug + @make release + $(call copy_log) +else +.PHONY: all rm_log $(module_all) $(module_Prj) clean rebuild debug release + +all: rm_log $(module_all) $(module_Prj) + $(call copy_log) +endif + +$(module_all): +ifeq ($(OS),Linux) + @$(MAKE) --directory=$@ $(MAKECMDGOALS) +else + @$(MAKE) --directory=$@ $(MAKECMDGOALS) $(JOB_FLAGS) +endif + +$(module_Prj):$(module_all) + @$(MAKE) --directory=$@ $(MAKECMDGOALS) + +rm_log: + @-rm -f log*.txt + +clean: rm_log $(module_all) $(module_Prj) + +ifeq "$(ISOLATE_DEP)" "ON" +rebuild: + @make clean + @make dep + @make debug + @make release + $(call copy_log) + +dep: $(module_all) $(module_Prj) +else +rebuild: rm_log $(module_all) $(module_Prj) + $(call copy_log) +endif + +debug: rm_log $(module_Prj) + $(call copy_log) + +release: rm_log $(module_Prj) + $(call copy_log) + +rm_chk_log: + @-rm -f chk*.txt + +chk: rm_chk_log $(module_all) $(module_Prj) + +chkclean: $(module_all) $(module_Prj) + +rm_lint_log: + @-rm -f lint*.txt + +lint: rm_lint_log $(module_all) $(module_Prj) + +lintclean: $(module_all) $(module_Prj) + +chk_unix: + @result="$(call test_if_unix_file_fmt, ../)"; if [ ! -z "$$result" ]; then \ + echo -e "\e[1;31mUNIX file format check failed:\e[0m" >&2; \ + for n in $$result; do \ + echo -e "\t$$n" >&2; \ + done; \ + exit 1; \ + fi \ No newline at end of file diff --git a/board/novatek/na51068/loader/MakeCommon/OutputImg.txt b/board/novatek/na51068/loader/MakeCommon/OutputImg.txt new file mode 100755 index 000000000000..ee5327b90e75 --- /dev/null +++ b/board/novatek/na51068/loader/MakeCommon/OutputImg.txt @@ -0,0 +1,553 @@ +#---------------------------------------------------------------------- +# Local variable to determine create library or binary file +#---------------------------------------------------------------------- +OUTPUT_FILE = BIN + +#---------------------------------------------------------------------- +# include make common and make option files +#---------------------------------------------------------------------- +include $(MAKE_COMMON_DIR)/MakeOption.txt +include $(MAKE_COMMON_DIR)/MakeCommon.txt + +#---------------------------------------------------------------------- +# CHIPCFG parameters +#---------------------------------------------------------------------- +ifeq "$(CHIPCFG)" "" + CHIPCFG := CHIPCFG +endif + +#---------------------------------------------------------------------- +# get force link ThirdParty symbols for both debug and release +#---------------------------------------------------------------------- +ifeq "$(USE_ECOS_KERNEL)" "ON" +rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d)) +LIB_ECOS_RTK_WIFI_DIR = $(ROOT_DIR)/ThirdParty/devs_eCos-rtl +LIB_ECOS_SELECT_RTK_WIFI_DIR = $(ROOT_DIR)/ThirdParty/devs_eCos-rtl$(WIFIMDL)es +LIB_ECOS_BASE_DIR = $(ROOT_DIR)/ThirdParty +LIB_ECOS_TMP = $(call rwildcard,$(LIB_ECOS_BASE_DIR)/,*.a) +LIB_ECOS_WO_RTK_WIFI_LIB = $(filter-out $(LIB_ECOS_RTK_WIFI_DIR)%, $(LIB_ECOS_TMP)) +LIB_ECOS_RTK_WIFI_LIB = $(call rwildcard,$(LIB_ECOS_SELECT_RTK_WIFI_DIR)/,*.a) +LIB_ECOS = $(LIB_ECOS_WO_RTK_WIFI_LIB) $(LIB_ECOS_RTK_WIFI_LIB) +#There are two eCos .o not in archive +ALL_OBJ_R += $(wildcard $(LIB_ECOS_BASE_DIR)/eCos/lib/*.o) +ALL_OBJ_D += $(wildcard $(LIB_ECOS_BASE_DIR)/eCos/lib/*.o) +endif + +#---------------------------------------------------------------------- +# get force link IPL symbols for both debug and release +#---------------------------------------------------------------------- +SYMBOL_IPL := IPL_SetDZoomFCB IPL_SetSleepFCB IPL_SetWakeupFCB IPL_GetCapRawFCB IPL_SetPauseDMAFCB IPL_SetResumeDMAFCB IPL_SetImgInOutFCB IPL_SetVAFCB IPL_GetIMEHalIdxFCB IPL_GetIPLInfoFCB IPL_TrigFCB IPL_SetTrigInfoFCB IPL_Stream2PauseFCB IPL_Pause2StreamFCB DCE_D2D_CB IPE_D2D_CB IFE_D2D_CB IFE2_D2D_CB IME_D2D_CB DRE_D2D_CB RHEIME_D2D_IFECB RHEIME_D2D_DCECB RHEIME_D2D_IPECB RHEIME_D2D_IMECB RHEIME_D2D_RHECB IPL_GetCtrlFlowFCB IQUC_InitCtrlItem + +#---------------------------------------------------------------------- +# include the libraries +#---------------------------------------------------------------------- +# +# get Debug LIBs +# +LIB_ALG_DIR_D = $(ARC_BASE_DIR)/../Alg/ARC/Debug +LIB_APP_DIR_D = $(ARC_BASE_DIR)/App/Debug +LIB_COM_DIR_D = $(ARC_BASE_DIR)/Common/Debug +LIB_DRV_DIR_D = $(ARC_BASE_DIR)/Drv/Debug +LIB_LIB_DIR_D = $(ARC_BASE_DIR)/Lib/Debug + +# get Alg libraries +LIB_ALG_D := $(wildcard $(LIB_ALG_DIR_D)/*.a) + +# get App/AppExt libraries +LIB_APP_D := $(wildcard $(LIB_APP_DIR_D)/*.a) + +# get Common libraries +LIB_COM_D := $(wildcard $(LIB_COM_DIR_D)/*.a) + +# get Drv/DrvExt libraries +LIB_DRV_ALL_D := $(wildcard $(LIB_DRV_DIR_D)/*.a) + +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_DIR_D = $(ARC_BASE_DIR)/Lib/Debug +LIB_STRGEXT_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/STRGEXT_*.a) +LIB_STRGEXT_D := $(wildcard $(LIB_LIB_DIR_D)/STRGEXT_$(STORAGEEXT)_D.a) +LIB_STRGINT_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/STRGINT_*.a) +LIB_STRGINT_D := $(wildcard $(LIB_LIB_DIR_D)/STRGINT_$(STORAGEINT)_D.a) +LIB_REMAP_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/Remap_*.a) +LIB_REMAP_D := $(wildcard $(LIB_LIB_DIR_D)/Remap_$(RESETFLAG)_D.a) +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_ALL_D := $(filter-out $(LIB_PARSER_ALL_D) $(LIB_SLIDE_ALL_D), $(wildcard $(LIB_LIB_DIR_D)/*.a)) + +LIB_LIB_D := $(filter-out $(LIB_STRGEXT_ALL_D) $(LIB_STRGINT_ALL_D) $(LIB_REMAP_ALL_D), $(LIB_LIB_ALL_D)) + +# +# get Release LIBs +# +LIB_LIB_DIR_R = $(ARC_BASE_DIR)/Lib/Release +LIB_STRGEXT_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/STRGEXT_*.a) +LIB_STRGEXT_R := $(wildcard $(LIB_LIB_DIR_R)/STRGEXT_$(STORAGEEXT).a) +LIB_STRGINT_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/STRGINT_*.a) +LIB_STRGINT_R := $(wildcard $(LIB_LIB_DIR_R)/STRGINT_$(STORAGEINT).a) +LIB_REMAP_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/Remap_*.a) +LIB_REMAP_R := $(wildcard $(LIB_LIB_DIR_R)/Remap_$(RESETFLAG).a) +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_ALL_R := $(filter-out $(LIB_PARSER_ALL_R) $(LIB_SLIDE_ALL_R), $(wildcard $(LIB_LIB_DIR_R)/*.a)) + +#LIB_LIB_R := $(filter-out $(LIB_STRGEXT_ALL_R) $(LIB_STRGINT_ALL_R) $(LIB_REMAP_ALL_R), $(LIB_LIB_ALL_R)) +LIB_LIB_R := $(filter-out $(LIB_STRGEXT_ALL_R) $(LIB_REMAP_ALL_R), $(LIB_LIB_ALL_R)) + + +# get total libraries for Debug & Release mode; note we cannot get string of LIB_R from LIB_D, or vice versa, +# because we may build Debug and Release output separately, the library of one mode maybe not exist, and cause +# the link problem. So, while adding/deleting libraries, please be patient to do it for Debug and Release mode both. + +LIB_R := \ + $(LIB_LIB_R) \ + $(LIB_STRGEXT_R) \ + $(LIB_REMAP_R) + +LIB_D := \ + $(LIB_LIB_D) \ + $(LIB_STRGEXT_D) \ + $(LIB_STRGINT_D) \ + $(LIB_REMAP_D) + +# If some libraries only available in Release mode, add these libraries in Debug mode too. +LIB_D += $(filter-out $(subst Debug/,Release/,$(LIB_D:_D.a=.a)),$(LIB_R)) + +# Append eCos library to both Debug and Release mode +# (We don't have debug mode's eCos library) +LIB_R += $(LIB_ECOS) +LIB_D += $(LIB_ECOS) + +#---------------------------------------------------------------------- +# set the make outputs +#---------------------------------------------------------------------- +# for debug target +IMAGE_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.axf +BIN_D = $(IMG_DEBUG)/$(LDR_NAME).bin +MAP_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.txt +MAP2_D = $(IMG_DEBUG)/$(PRJ_NAME)_ldmap_D.txt +SYM_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.sym +DASM_D = $(IMG_DEBUG)/$(PRJ_NAME)_dasm_D.txt +ifeq "$(MODELEXT_BUILT_IN)" "MODELEXT_BUILT_IN_OFF" +MODELEXT_D = $(IMG_DEBUG)/$(BIN_NAME).ext.bin +endif + + +# for release target +IMAGE_R = $(IMG_RELEASE)/$(PRJ_NAME).axf +BIN_R = $(IMG_RELEASE)/$(LDR_NAME).bin +TMP_R = $(IMG_RELEASE)/$(TMP_NAME).bin +TMPCOMPRESSED_R = $(IMG_RELEASE)/$(TMP_NAME)LZ.bin +MAP_R = $(IMG_RELEASE)/$(PRJ_NAME).txt +MAP2_R = $(IMG_RELEASE)/$(PRJ_NAME)_ldmap.txt +SYM_R = $(IMG_RELEASE)/$(PRJ_NAME).sym +DASM_R = $(IMG_RELEASE)/$(PRJ_NAME)_dasm.txt +ifeq "$(MODELEXT_BUILT_IN)" "MODELEXT_BUILT_IN_OFF" +MODELEXT_R = $(IMG_RELEASE)/$(BIN_NAME).ext.bin +endif + +#---------------------------------------------------------------------- +# if enable LDS_MAP +#---------------------------------------------------------------------- +ifeq "$(LDS_MAP)" "ON" +LDMAP_D = -Map $(MAP2_D) +LDMAP_R = -Map $(MAP2_R) +endif + +#---------------------------------------------------------------------- +# set the warning/error log file option +#---------------------------------------------------------------------- +log_file = log_Prj.txt + +# 0: Standard input (stdin), 1: Standard output (stdout), 2: Standard error (stderr) +# 2>>$(log_file) means redirect standard error to $(log_file) +# 2>>/dev/null means redirect standard error to NULL (Don't display error message) +ifeq "$(LOG_ERR)" "ON" +LOG_OPTION = 2>>$(log_file) +endif + +#---------------------------------------------------------------------- +# set robustness checking log file +#---------------------------------------------------------------------- +lint_file = lint_Prj.txt +lintopt_file = options_Prj.lnt +lintsum_file = lintsum_Prj.txt + +#---------------------------------------------------------------------- +# set the make targets +#---------------------------------------------------------------------- +build_D: make_debug_begin prepare_log $(IMAGE_D) $(BIN_D) +build_R: make_release_begin prepare_log $(IMAGE_R) $(BIN_R) +build_pipe_D: $(IMAGE_D) $(BIN_D) +build_pipe_R: $(IMAGE_R) $(BIN_R) + +ifeq "$(ISOLATE_DEP)" "ON" +build_DEP: make_dep_begin $(SRC) $(ASM) $(CPP_SRC) $(ALL_DEP) +endif + +build_LINT: make_lint_begin $(LINT_FILE) + +prepare_log: + @$(LOG_OPTION) + +ifeq "$(ARCH)" "ARM" +#arm-none-eabi-gcc -march=armv7-a -mcpu=cortex-a9 -mfpu=neon -mfloat-abi=softfp -print-file-name=libm.a +ifeq "$(FPU)" "hard" +libgcc_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mabi=aapcs -mfpu=neon -mfloat-abi=$(FPU) -print-libgcc-file-name) +libgcc_dir_el = $(shell dirname "$(libgcc_path)") +libstdc_path = $(shell $(CC) -msoft-float -print-file-name=libstdc++.a) +libstdc_dir_el = $(shell dirname "$(libstdc_path)") +libm_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mfpu=neon -mfloat-abi=$(FPU) -print-file-name=libm.a) +libm_dir = $(shell dirname "$(libm_path)") +else +libgcc_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mabi=aapcs -mfloat-abi=$(FPU) -print-libgcc-file-name) +libgcc_dir_el = $(shell dirname "$(libgcc_path)") +libstdc_path = $(shell $(CC) -msoft-float -print-file-name=libstdc++.a) +libstdc_dir_el = $(shell dirname "$(libstdc_path)") +libm_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mfloat-abi=$(FPU) -print-file-name=libm.a) +libm_dir = $(shell dirname "$(libm_path)") +endif +endif + +define append_modelext + echo Append $1 into $4. \ + && $(AR) x $3 $1.o \ + && $(FE) --only-section=modelext_header.$1 -O binary -S -R .comment -R .note $1.o $2/$1.header \ + && cat $2/$1.header >> $4 \ + && $(FE) --only-section=modelext_data.$1 -O binary -S -R .comment -R .note $1.o $2/$1.data \ + && cat $2/$1.data >> $4 +endef + + +#Replace string existing in lds file +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_256" + BOARD_UITRON_ADDR = 0x8000000 +endif +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_512" + BOARD_UITRON_ADDR = 0x10000000 +endif +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_1024" + BOARD_UITRON_ADDR = 0x20000000 +endif +endif + +LD_REMAP_LIB = Remap_$(RESETFLAG) +LD_DOREMAP = doremap$(RESETFLAG) +ifeq "$(BL_COMPRESS)" "ENABLE" +LD_CONFIGRAM = configramLZ +else +LD_CONFIGRAM = configramNM +endif +ifeq "$(UBOOT_BIND)" "UBOOT_BIND_ON" +LD_LDS_EXTERN = lzma_inflate +LOADER_FIXED_BIN_SIZE = 0x00028000 +else +LD_LDS_EXTERN = bl_mainFlow +LOADER_FIXED_BIN_SIZE = 0x00010000 +endif + +LD_REPLACE_VAR = sed \ + -e 's/$$LD_REMAP_LIB/$(LD_REMAP_LIB)/g' \ + -e 's/$$LD_DOREMAP/$(LD_DOREMAP)/g' \ + -e 's/$$LD_CONFIGRAM/$(LD_CONFIGRAM)/g' \ + -e 's/$$LD_BASE_ADDR/$(LD_BASE_ADDR)/g' \ + -e 's/$$LD_LDS_EXTERN/$(LD_LDS_EXTERN)/g' \ + -e 's/$$LOADER_FIXED_BIN_SIZE/$(LOADER_FIXED_BIN_SIZE)/g' \ + $(SCATTER) + +#The folder, the working space to fill the full path into lds file +LD_DIR_WORKING_D= $(IMG_BASE_DIR)/Debug/ObjectLds +#Generate the working folder and temp lds file called replace.lds +LD_REPLACE_LDS_D= $(shell mkdir -p $(LD_DIR_WORKING_D)) $(shell $(OBJDUMP) -h $(LIB_D) | grep ".version.info" > tmp_awk1) $(shell $(LD_REPLACE_VAR) > $(LD_DIR_WORKING_D)/replace.lds) +#The real lds file replaced of using by linker +LD_PATH_LDS_D = $(LD_DIR_WORKING_D)/$(basename $(SCATTER))_D.lds +#Here have some steps as following to get a some files explained below, +#Step 1: Generate temp lds file +#Step 2: export the contents of $(LIB_D) into libs.txt +#Step 3: export the contents of $(ALL_OBJ_D) into objs.txt +#Step 4: Give mips-nvt.exe libs.txt, objs.txt and replace.lds to get ld_ext.d, ld_lib.txt, ld_lib_ban.txt and real lds file for linker. +# Where, +# ld_ext.d is a decency file depends on .o used in lds file +# ld_lib_ban is a list of .a files to ban, because linker should use the .a file after extracting .o. +# real lds file is replaced by full path. +LD_DFILE_D = $(LD_REPLACE_LDS_D) $(shell echo $(LIB_D) > $(LD_DIR_WORKING_D)/libs.txt ) $(shell echo $(ALL_OBJ_D) > $(LD_DIR_WORKING_D)/objs.txt ) $(shell $(LDNVT) --lds-dst=$(LD_PATH_LDS_D) --lds-dir=$(LD_DIR_WORKING_D) --lds-src=$(LD_DIR_WORKING_D)/replace.lds --libs-src=$(LD_DIR_WORKING_D)/libs.txt --objs-src=$(LD_DIR_WORKING_D)/objs.txt --objs-dir=$(OBJ_DEBUG)) $(LD_DIR_WORKING_D)/ld_ext.d +#Getting the contents of ld_lib.txt +LD_LIB_D = $(shell cat $(LD_DIR_WORKING_D)/ld_lib.txt 2>>/dev/null) +#Getting the contents of ld_lib_ban.txt +LD_LIB_BAN_D = $(shell cat $(LD_DIR_WORKING_D)/ld_lib_ban.txt 2>>/dev/null) +tmp_awk2 = $(shell awk -F" " '{print $$2}' tmp_awk1 | awk -F"." '{print $$5}') +tmp_awk3 = $(addsuffix _LIBRARY_VERSION_INFO, $(tmp_awk2)) + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),debug build_pipe_D)) +include $(LD_DFILE_D) +endif + +$(LD_LIB_D): $(MODELEXT_D) + +#$(MODELEXT_D): $(LIB_MODELEXT_D) +# @echo Creating modelext $@ ... \ +# && rm -f $@ \ +# && $(call append_modelext,modelext_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,bin_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,pinmux_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,intdir_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,emb_partition_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,gpio_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,dram_partition_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,model_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(EBIN) $(EBIN_METHOD) $@ 0x18 $(EBIN_MNAME) +# @BIN_SIZE=`ls -l $@ | cut -d ' ' -f 5`; \ +# RESIDUAL=$$(($${BIN_SIZE} % 4)); \ +# if [ "$${RESIDUAL}" -ne "0" ]; then \ +# echo "sizeof($@) is not 4-byte aligned"; \ +# exit 1; \ +# fi + +$(IMAGE_D): $(SRC) $(ASM) $(CPP_SRC) $(ALL_OBJ_D) $(LIB_D) $(LD_LIB_D) $(MODELEXT_D) + $(shell mv *.o $(IMG_BASE_DIR)/Debug/ObjectCode 2>>/dev/null) + @echo '-o $@ $(ALL_OBJ_D)'> ld_d.tmp + @echo '--start-group $(LD_LIB_D) $(filter-out $(LD_LIB_BAN_D),$(LIB_D)) --end-group -Bstatic -EL --no-wchar-size-warning --gc-sections -T $(LD_PATH_LDS_D) -L "$(libgcc_dir_el)" -L"$(libstdc_dir_el)" -L"$(libm_dir)" -lgcc $(LDMAP_D)' >> ld_d.tmp +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" + @echo "Linking CA53_core2...$(LD_PATH_LDS_D)" \ + && echo Creating image $@ ... \ + && $(LD) @ld_d.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_D) \ + && $(NM) -n $@ > tmp_sym_d \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_d > $(SYM_D) \ + && rm -f tmp_sym_d \ + && rm -f ld_d.tmp \ + && rm -f tmp_awk1 +else + @echo "Linking ..." \ + && echo Creating image $@ ... \ + && $(LD) @ld_d.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_D) \ + && $(NM) -n $@ > tmp_sym_d \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_d > $(SYM_D) \ + && rm -f tmp_sym_d \ + && rm -f ld_d.tmp \ + && rm -f tmp_awk1 +endif + + +$(BIN_D): $(IMAGE_D) +ifeq "$(MULTI_REGIONS)" "ON" + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ \ + && mv $(IMG_DEBUG)/SPECIAL_RO $(BIN_D) +else + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ +endif +ifeq "$(LDS_MAP)" "ON" + @echo Generate LDS map file $(MAP2_D): ok +endif +ifeq "$(AXF_DIS)" "ON" + @echo Translate AXF $< to disassembly... \ + && $(OBJDUMP) -D $(IMAGE_D) > $(DASM_D) +endif + +ifeq "$(BL_COMPRESS)" "ENABLE" + @echo Compressing file $(@)\ + && $(BFC) c lz $(BIN_D) tmp 1 $(UNCOMPRESSEDPART_SIZE_OFFSET) \ + && cp -f tmp $(BIN_D) \ + && rm -f tmp \ + && echo Encrypt binary file $@ for $(CHIP)... $(CHIP_VER) $(DMA_CLOCK) $(SDRAM_SIZE) $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE)\ + && $(EBIN) $@ $@ 680 + $(CFGRAM) $@ -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI_STR) -chip=660 -package=$(CHIP) -ldver=$(LOADER_VERSION) -gui=$(CONFIG_RAM_GUI_EN) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) -ddr16bit=$(DRAM1_16BIT_PARAM) -ddr_width_detect=$(DRAM_WIDTH_DET_PARAM) +# $(CFGRAM) $@ ../../Tools/ConfigRam/$(CHIP)_$(CHIP_VER)_$(DMA_CLOCK)_$(SDRAM_SIZE)$(DDR_FILE_STR).ini 650 $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE) $(LV1_CLK) +else + @echo Encrypt binary file $@ for $(CHIP)...\ + && $(EBIN) $@ $@ 680 $(SECURE_BOOT) +endif + +ifeq "$(COPY_BIN_2_STG)" "ON" +ifneq "$(NVT_STG_PATH)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH) ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH)$(notdir $(BIN_D)) +endif +ifneq "$(NVT_STG_PATH_MIPS2)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin +endif + +ifneq "$(NVT_STG_PATH_CA532)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH_CA532)_FWCA532.bin ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH_CA532)_FWCA532.bin +endif +endif + +#Please refer LD_DIR_WORKING_D for getting explanation. Ohters are in the same way. +LD_DIR_WORKING_R= $(IMG_BASE_DIR)/Release/ObjectLds +LD_REPLACE_LDS_R= $(shell mkdir -p $(LD_DIR_WORKING_R)) $(shell $(OBJDUMP) -h $(LIB_R) | grep ".version.info" > tmp_awk1) $(shell $(LD_REPLACE_VAR) > $(LD_DIR_WORKING_R)/replace.lds) +LD_PATH_LDS_R = $(LD_DIR_WORKING_R)/$(basename $(SCATTER))_R.lds +LD_DFILE_R = $(LD_REPLACE_LDS_R) $(shell echo $(LIB_R) > $(LD_DIR_WORKING_R)/libs.txt ) $(shell echo $(ALL_OBJ_R) > $(LD_DIR_WORKING_R)/objs.txt ) $(shell $(LDNVT) --lds-dst=$(LD_PATH_LDS_R) --lds-dir=$(LD_DIR_WORKING_R) --lds-src=$(LD_DIR_WORKING_R)/replace.lds --libs-src=$(LD_DIR_WORKING_R)/libs.txt --objs-src=$(LD_DIR_WORKING_R)/objs.txt --objs-dir=$(OBJ_RELEASE)) $(LD_DIR_WORKING_R)/ld_ext.d +LD_LIB_R = $(shell cat $(LD_DIR_WORKING_R)/ld_lib.txt 2>>/dev/null) +LD_LIB_BAN_R = $(shell cat $(LD_DIR_WORKING_R)/ld_lib_ban.txt 2>>/dev/null) +tmp_awk2 = $(shell awk -F" " '{print $$2}' tmp_awk1 | awk -F"." '{print $$5}') +tmp_awk3 = $(addsuffix _LIBRARY_VERSION_INFO, $(tmp_awk2)) + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),release build_pipe_R)) +include $(LD_DFILE_R) +endif + +$(LD_LIB_R): $(MODELEXT_R) + +#$(MODELEXT_R): $(LIB_MODELEXT_R) +# @echo Creating modelext $@ \ +# && rm -f $@ \ +# && $(call append_modelext,modelext_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,bin_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,pinmux_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,intdir_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,emb_partition_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,gpio_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,dram_partition_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,model_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(EBIN) $(EBIN_METHOD) $@ 0x18 $(EBIN_MNAME) +# @BIN_SIZE=`ls -l $@ | cut -d ' ' -f 5`; \ +# RESIDUAL=$$(($${BIN_SIZE} % 4)); \ +# if [ "$${RESIDUAL}" -ne "0" ]; then \ +# echo "sizeof($@) is not 4-byte aligned"; \ +# exit 1; \ +# fi + +$(IMAGE_R): $(SRC) $(ASM) $(CPP_SRC) $(ALL_OBJ_R) $(LIB_R) $(LD_LIB_R) $(MODELEXT_R) + $(shell mv *.o $(IMG_BASE_DIR)/Release/ObjectCode 2>>/dev/null) + @echo '-o $@ $(ALL_OBJ_R) '> ld_r.tmp + @echo '--start-group $(LD_LIB_R) $(filter-out $(LD_LIB_BAN_R),$(LIB_R)) --end-group -Bstatic -EL --no-wchar-size-warning --gc-sections -T $(LD_PATH_LDS_R) -L"$(libgcc_dir_el)" -L"$(libstdc_dir_el)" -lgcc $(LDMAP_R)' >> ld_r.tmp + +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" + @echo "Linking CA53_core2...$(LD_PATH_LDS_R)" \ + && echo Creating image $@ ... \ + && $(LD) @ld_r.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_R) \ + && $(NM) -n $@ > tmp_sym_r \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_r > $(SYM_R) \ + && rm -f tmp_sym_r \ + && rm -f ld_r.tmp \ + && rm -f tmp_awk1 +else + @echo "Linking ..." \ + && echo Creating image $@ ... \ + && $(LD) @ld_r.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t -marm $@ > $(MAP_R) \ + && $(NM) -n $@ > tmp_sym_r \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_r > $(SYM_R) \ + && rm -f tmp_sym_r \ + && rm -f ld_r.tmp \ + && rm -f tmp_awk1 +endif + +$(BIN_R): $(IMAGE_R) +ifeq "$(MULTI_REGIONS)" "ON" +ifeq "$(BL_COMPRESS)" "ENABLE" + @echo Creating executable $(TMP_R) ...\ + && $(FE) --gap-fill=0xff -O binary $< $(TMP_R) +else + @echo Creating executable $< $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ \ + && mv $(IMG_RELEASE)/SPECIAL_RO $(BIN_R) +endif +else +ifeq "$(BL_COMPRESS)" "ENABLE" + @echo Creating executable $(TMP_R) ...\ + && $(FE) --gap-fill=0xff -O binary $< $(TMP_R) +else + @echo Creating executable $< $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ +endif +endif + +ifeq "$(LDS_MAP)" "ON" + @echo Generate LDS map file $(MAP2_R): ok +endif +ifeq "$(AXF_DIS)" "ON" + @echo Translate AXF $< to disassembly... \ + && $(OBJDUMP) -D $(IMAGE_R) > $(DASM_R) +endif +ifeq "$(BL_COMPRESS)" "ENABLE" + @echo Compressing file $(TMP_R) $(@)\ + && $(BFC) c lz $(TMP_R) $(TMPCOMPRESSED_R) 1 $(UNCOMPRESSEDPART_SIZE_OFFSET) + +ifeq "$(UBOOT_BIND)" "UBOOT_BIND_ON" + cat $(TMPCOMPRESSED_R) $(UBOOT_PATH) > lu.bin && \ + mv lu.bin $(TMPCOMPRESSED_R) +endif + @echo Encrypt binary file $@ for $(CHIP)... $(CHIP_VER) $(DMA_CLOCK) $(SDRAM_SIZE) $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE)\ + && $(EBIN) $(TMPCOMPRESSED_R) $@ $(CHIPID) \ + && $(CFGRAM) $@ -freq=$(DRAM1_CLK) -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI2_STR) -chip=$(CHIPID) -package=$(CHIP) -ldver=$(LOADER_VERSION) -storage=$(STORAGEINT) -dram_ssc=$(DRAM_SSC_PARAM) -dram_2nd_tlb=$(2ND_INI) -dram_hl_swap=$(DRAM_HL_SWAP_PARAM) -dram_sa_swap=$(DRAM_SA_SWAP_PARAM)\ + && $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) $(ENCRYPT_DATA) $(SECUREBOOT_MSG) $(AES_KEY_FILE_DIR) $(RSA_PUB_KEY_FILE_DIR) $(RSA_PRV_KEY_FILE_DIR) +# $(CFGRAM) $@ -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI_STR) -chip=660 -package=$(CHIP) -ldver=$(LOADER_VERSION) -gui=$(CONFIG_RAM_GUI_EN) -storage=$(STORAGEINT) +# $(CFGRAM) $@ ../../Tools/ConfigRam/$(CHIP)_$(CHIP_VER)_$(DMA_CLOCK)_$(SDRAM_SIZE)$(DDR_FILE_STR).ini 650 $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE) $(LV1_CLK) +else + @echo Encrypt binary file $@ for $(CHIP) Not support...\ + && $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) +endif + +ifeq "$(COPY_BIN_2_STG)" "ON" +ifneq "$(NVT_STG_PATH)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH) ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH)$(notdir $(BIN_R)) +endif +ifneq "$(NVT_STG_PATH_MIPS2)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH_MIPS2) ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin +endif + +ifneq "$(NVT_STG_PATH_CA532)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH_CA532)_FWCA532.bin ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH_CA532)_FWCA532.bin +endif +endif + +.PHONY: +rm_log: +ifeq "$(CLEAN_LOG)" "ON" + @-rm -f $(log_file) +endif + +clean: + @-echo Clean $(basename $(notdir $(IMAGE_R))) ... \ + && rm -rf --no-preserve-root $(IMG_BASE_DIR) $(log_file) $(lint_file) + +ifeq "$(ISOLATE_DEP)" "ON" +all: rm_log + @make dep + @make debug + @make release + +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: build_DEP +else +rebuild: clean build_D build_R +endif + +debug: rm_log make_debug_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_D +else + $(MAKE) build_pipe_D $(JOB_FLAGS) +endif + +release: rm_log make_release_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_R +else + $(MAKE) build_pipe_R $(JOB_FLAGS) +endif + +#remove unused remap.a for sdk +remap: + rm -v $(filter-out $(LIB_REMAP_D), $(LIB_REMAP_ALL_D)) $(filter-out $(LIB_REMAP_R), $(LIB_REMAP_ALL_R)) + +codesize: $(IMAGE_R) + @$(OBJDUMP) -t $< > $<.sym && \ + $(LDNVT) -j $<.sym && \ + mv RO_RW.txt ZI.txt $(IMG_RELEASE) \ No newline at end of file diff --git a/board/novatek/na51068/loader/MakeCommon/OutputLib.txt b/board/novatek/na51068/loader/MakeCommon/OutputLib.txt new file mode 100755 index 000000000000..cf436efaa33d --- /dev/null +++ b/board/novatek/na51068/loader/MakeCommon/OutputLib.txt @@ -0,0 +1,155 @@ +#---------------------------------------------------------------------- +# Local variable to determine create library or binary file +#---------------------------------------------------------------------- +OUTPUT_FILE = LIB + +#---------------------------------------------------------------------- +# include make common and make option files +#---------------------------------------------------------------------- +ifeq "$(OPTION_LOADED)" "" + include $(MAKE_COMMON_DIR)/MakeOption.txt + LOCAL_CLEAN_LOG = $(CLEAN_LOG) +else + LOCAL_CLEAN_LOG = OFF +endif + +include $(MAKE_COMMON_DIR)/MakeCommon.txt + +#---------------------------------------------------------------------- +# set the make outputs +#---------------------------------------------------------------------- +IMAGE_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.a +IMAGE_R = $(IMG_RELEASE)/$(PRJ_NAME).a + +#---------------------------------------------------------------------- +# set the warning/error log file option +#---------------------------------------------------------------------- +# $(APP_PATH), $(APPEXT_PATH), $(LIB_PATH), $(LIBEXT_PATH) will be assigned value in MakeCommon.txt +ifneq "$(ALG_PATH)" "" + log_file := $(subst MakeCommon,Alg/log_Alg.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Alg/lint_Alg.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Alg.lnt + lintsum_file := $(subst MakeCommon,App/lintsum_Alg.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(APP_PATH)" "" + log_file := $(subst MakeCommon,App/log_App.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,App/lint_App.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_App.lnt + lintsum_file := $(subst MakeCommon,App/lintsum_App.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(APPEXT_PATH)" "" + log_file := $(subst MakeCommon,AppExt/log_AppExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,AppExt/lint_AppExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_AppExt.lnt + lintsum_file := $(subst MakeCommon,AppExt/lintsum_AppExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(LIB_PATH)" "" + log_file := $(subst MakeCommon,Lib/log_Lib.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Lib/lint_Lib.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Lib.lnt + lintsum_file := $(subst MakeCommon,Lib/lintsum_Lib.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(LIBEXT_PATH)" "" + log_file := $(subst MakeCommon,LibExt/log_LibExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,LibExt/lint_LibExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_LibExt.lnt + lintsum_file := $(subst MakeCommon,LibExt/lintsum_LibExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(DRV_PATH)" "" + log_file := $(subst MakeCommon,Drv/log_Drv.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Drv/lint_Drv.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Drv.lnt + lintsum_file := $(subst MakeCommon,Drv/lintsum_Drv.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(DRVEXT_PATH)" "" + log_file := $(subst MakeCommon,DrvExt/log_DrvExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,DrvExt/lint_DrvExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_DrvExt.lnt + lintsum_file := $(subst MakeCommon,DrvExt/lintsum_DrvExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(COM_PATH)" "" + log_file := $(subst MakeCommon,Common/log_Common.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Common/lint_Common.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Common.lnt + lintsum_file := $(subst MakeCommon,Common/lintsum_Common.txt,$(MAKE_COMMON_DIR)) +else + log_file := /dev/null + lint_file := /dev/null + lintopt_file := /dev/null + lintsum_file := /dev/null +endif + +ifeq "$(LOG_ERR)" "ON" + LOG_OPTION = 2>>$(log_file) + LOG_DATE = date >>$(log_file) + LOG_SPACE = echo >>$(log_file) +endif + +#---------------------------------------------------------------------- +# set the make targets +#---------------------------------------------------------------------- +build_D: make_debug_begin $(IMAGE_D) +build_R: make_release_begin $(IMAGE_R) +build_pipe_D: $(IMAGE_D) +build_pipe_R: $(IMAGE_R) + +ifeq "$(ISOLATE_DEP)" "ON" +build_DEP: make_dep_begin $(ALL_DEP) +endif + +build_LINT: make_lint_begin $(LINT_FILE) + +$(IMAGE_D): $(ALL_OBJ_D) + @echo Creating library $(notdir $@) ... \ + && rm -f $(IMAGE_D) \ + && $(AR) -cru $@ $^ + +$(IMAGE_R): $(ALL_OBJ_R) + @echo Creating library $(notdir $@) ... \ + && rm -f $(IMAGE_R) \ + && $(AR) -cru $@ $^ + +.PHONY: +rm_log: +ifeq "$(LOCAL_CLEAN_LOG)" "ON" + @-rm -f $(log_file) +endif + +clean: + @-echo Clean $(basename $(notdir $(IMAGE_R))) ... \ + && rm -rf --no-preserve-root $(PRJ_NAME)_Data $(log_file) $(lint_file) + +ifeq "$(ISOLATE_DEP)" "ON" +all: rm_log + @make dep + @make debug + @make release + +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: build_DEP +else +rebuild: clean build_D build_R +endif + +debug: rm_log make_debug_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_D +else + $(MAKE) build_pipe_D $(JOB_FLAGS) +endif + +release: rm_log make_release_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_R +else + $(MAKE) build_pipe_R $(JOB_FLAGS) +endif + +rm_lint_log: +ifeq "$(LOCAL_CLEAN_LOG)" "ON" + @-rm -f $(lint_file) +endif + +lint: rm_lint_log build_LINT + +lintclean: + @-echo Clean Lint $(basename $(notdir $(IMAGE_R))) checking data ... \ + && rm -rf --no-preserve-root $(LINT_DIR) $(lint_file) diff --git a/board/novatek/na51068/loader/MakeCommon/dump_tmp b/board/novatek/na51068/loader/MakeCommon/dump_tmp new file mode 100755 index 000000000000..e69de29bb2d1 diff --git a/board/novatek/na51068/loader/Project/Model/LDS_LZ.lds b/board/novatek/na51068/loader/Project/Model/LDS_LZ.lds new file mode 100755 index 000000000000..0c5e94143ce2 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/LDS_LZ.lds @@ -0,0 +1,186 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + _loader_fixed_bin_size = $LOADER_FIXED_BIN_SIZE; + .BOOT_EXEC 0xFE080000|0x00000000: + AT (0) + { + _stext = .; + _load_BOOT_EXEC_start_base = .; + KEEP(Reset/reset.o(.data*)); + Reset/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xFE080000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP(Reset/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + } + .LOADER_CONFIGRAM2 (0xFE080000|0x00000000) + 0x300: + AT (0x300) + { + config_dram_tbl_start_base = .; + KEEP(Reset/config_dram1_tbl.o(.rodata*)); + config_dram_tbl_end_base = .; + } + .LOADER_CONFIGRAM3 (0xFE080000|0x00000000) + 0x400: + AT (0x400) + { + config_dram_tbl2_start_base = .; + KEEP(Reset/config_dram1_2_tbl.o(.rodata*)); + config_dram_tbl2_end_base = .; + } + LOADER_CORE2_ENTRY_PROGRAM (0xFE080000|0x00000000) + 0x500: + AT (0x500) + { + _load_core2_jump_program_start_base = .; + KEEP(Reset/core2_jump.o(.text)); + _load_core2_jump_program_end_base = .; + _load_core2_entry_program_start_base = .; + KEEP(Reset/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + + .LOADER_REMAP (0xFE080000|0x00000000) + 0x700: + AT (0x700) + { + _load_LOADER_REMAP_start_base = .; + KEEP($LD_REMAP_LIB/$LD_DOREMAP.o(.text* .data*)); + _load_LOADER_REMAP_end_base = .; + KEEP(Reset/configDDR.o (.text* .rodata* .data* .bss*)); + KEEP(Reset/ddr_basic.o (.text* .rodata* .data*)); + KEEP(Reset/ddr_control.o (.text* .rodata*)); + KEEP(Reset/ddr_globals.o (.data*)); + KEEP(Reset/ddr_io.o (.text* .rodata*)); + KEEP(Reset/clk_tree_k.o (.text* .rodata*)); + KEEP(Reset/zqk.o (.text* .rodata*)); + KEEP(Reset/dutyk.o (.text* .rodata* .data* .bss*)); + KEEP(Reset/issue_cmd.o (.text* .rodata*)); + KEEP(Reset/phy_bist.o (.text* .rodata*)); + KEEP(Reset/psdk.o (.text* .rodata*)); + KEEP(Reset/qsen.o (.text* .rodata* .data* .bss*)); + KEEP(Reset/read_eye.o (.text* .rodata* .data*)); + KEEP(Reset/read_vref.o (.text* .rodata*)); + KEEP(Reset/write_eye.o (.text* .rodata* .data*)); + KEEP(Reset/write_vref.o (.text* .rodata* .data* .bss*)); + KEEP(Reset/write_leveling.o (.text* .rodata*)); + KEEP(Reset/register_673c.o(.text* .rodata* .data* .bss*)); + KEEP(Driver/serial.o(.text* .data* .rodata*)); + KEEP(Driver/timer.o(.text* .rodata*)); + KEEP(Debug/debug.o (.text* .data* .bss*)); + KEEP(Common/global.o (.text* .data* .bss*)); + KEEP(Reset/ddr_basic.o(.bss*)); + KEEP(Reset/ddr_io.o(.bss*)); + KEEP(Reset/write_eye.o(.bss*)); + *libgcc.a:*(.text*); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + . = ALIGN(4); + .LOADER_EXEC ADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP) : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + * (.part1) + KEEP(CA9/cache.o(.text)); + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + . = ALIGN(4); + .text $LD_BASE_ADDR: + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _etext = .; + _loader_exec_compres_end = .; + } + + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + _sdata = .; + .data : { *(.data*) } + _image_general_var_limit = .; + _edata = .; + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got*) } + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(8); /* This is MUST. Ensure ro size is 2 word aligned. */ + } + + .bss : { + _image_general_zi_zi_base = .; + _sbss = . ; + *(.bss*) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + _image_general_zi_zi_limit = .; + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + _ebss = . ; + } + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + .lzma : + { + _lzma_tmp_start = .; + . += 0x10000; + _lzma_tmp_end = .; + } + . = ALIGN(64); + _stack_start = .; + +} + +EXTERN($LD_LDS_EXTERN) diff --git a/board/novatek/na51068/loader/Project/Model/LDS_NM.lds b/board/novatek/na51068/loader/Project/Model/LDS_NM.lds new file mode 100755 index 000000000000..9616ae518db6 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/LDS_NM.lds @@ -0,0 +1,144 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xFE080000|0x00000000: + AT (0) + { + _stext = .; + _load_BOOT_EXEC_start_base = .; + KEEP(Reset/reset.o(.data*)); + Reset/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xFE080000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP(Reset/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + } + .LOADER_CONFIGRAM2 (0xFE080000|0x00000000) + 0x200: + AT (0x200) + { + } + + .LOADER_CORE2_ENTRY_PROGRAM (0xFE080000|0x00000000) + 0x300: + AT (0x300) + { + _load_core2_jump_program_start_base = .; + KEEP(Reset/core2_jump.o(.text)); + _load_core2_jump_program_end_base = .; + _load_core2_entry_program_start_base = .; + KEEP(Reset/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + .LOADER_REMAP (0xFE080000|0x00000000) + 0x4C0: + AT (0x4C0) + { + _load_LOADER_REMAP_start_base = .; + KEEP($LD_REMAP_LIB/$LD_DOREMAP.o(.text*)); + KEEP($LD_REMAP_LIB/$LD_DOREMAP.o(.data*)); + _load_LOADER_REMAP_end_base = .; + KEEP(Reset/configDDR.o(.text*)); + KEEP(Reset/configDDR.o(.rodata*)); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + . = ALIGN(4); + .LOADER_EXEC ADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP) : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.text*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .text $LD_BASE_ADDR: + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _etext = .; + _loader_exec_compres_end = .; + } + + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + _loader_exec_compress_load_size = SIZEOF(.text); + + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + _sdata = .; + .data : { *(.data*) } + _image_general_var_limit = .; + _edata = .; + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got*) } + . = ALIGN(4); + .rodata : { *(.rodata*) } + . = ALIGN(4); + + .bss : { + _image_general_zi_zi_base = .; + _sbss = . ; + *(.bss*) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + _image_general_zi_zi_limit = .; + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + _ebss = . ; + } + _loader_data_size = SIZEOF(.data) + _image_general_zi_zi_base - _edata; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; +} + +EXTERN(bl_mainFlow) diff --git a/board/novatek/na51068/loader/Project/Model/MakeConfig.txt b/board/novatek/na51068/loader/Project/Model/MakeConfig.txt new file mode 100755 index 000000000000..82af4073af66 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/MakeConfig.txt @@ -0,0 +1,720 @@ +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +#------------------------------------------------------------------------------ +# Loader version : unsigned long loader version definition +#------------------------------------------------------------------------------ +LOADER_VERSION = 0x01000001 +BL_LOADER_VER_PARAM = \ + -D_LDR_VER_="$(LOADER_VERSION)" + +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +# +# Hardware device selection +# +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +#------------------------------------------------------------------------------ +# Select chip version +#------------------------------------------------------------------------------ +#CHIP_VER = A +#CHIP_VER = B + +#------------------------------------------------------------------------------ +# Select LV1 clock rate +# LV1: 491MHz / 593MHz +#------------------------------------------------------------------------------ +#LV1_CLK = 491 +#LV1_CLK = 593 + +#------------------------------------------------------------------------------ +# Select DMA clock rate +#------------------------------------------------------------------------------ +#DMA_CLOCK = LV0 +#DMA_CLOCK = LV1 + +#ifeq "$(DMA_CLOCK)" "LV1" +#ifeq "$(LV1_CLK)" "491" +#DMA_CLOCK = LV1_4 +#else +#DMA_CLOCK = LV1_5 +#endif +#endif + +ifeq "$(CHIP)" "321" +# external dram +else ifeq "$(CHIP)" "323" +# external dram +else + +endif + +#------------------------------------------------------------------------------ +# Select DRAM Size (unit: Giga bit) +#------------------------------------------------------------------------------ +#SDRAM_SIZE = 1024 +#SDRAM_SIZE = 2048 +#SDRAM_SIZE = 4096 + +#------------------------------------------------------------------------------ +# Select DRAM Type (DDR3L curruently NOT available) +#------------------------------------------------------------------------------ +#DRAM_TYPE = DDR3 +#DRAM_TYPE = DDR3L + +#------------------------------------------------------------------------------ +# Select Phy analog block LV / HV +# (Don't modify this item) +#------------------------------------------------------------------------------ +PHY_ANALOG_HV = HV + +#------------------------------------------------------------------------------ +# CPU Core version configuration +# (Don't modify this item) +#------------------------------------------------------------------------------ +#CA53_ARCH32 +#CA9 +CPU_CORE = CA9 + +#------------------------------------------------------------------------------ +# Select internal storage device +#------------------------------------------------------------------------------ +#STORAGEINT = NandEccRS +#STORAGEINT = NandSpi +#STORAGEINT = SpiFlash + +#------------------------------------------------------------------------------ +# Select external storage device +#------------------------------------------------------------------------------ +#STORAGEEXT = Sdio1 +#STORAGEEXT = Sdio2 +#STORAGEEXT = Usb + +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +# +# Software function selection +# +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#------------------------------------------------------------------------------ +# Dram range scan loader support enable +# (Don't modify this item) +#------------------------------------------------------------------------------ +DRAM_RANGE_SCAN_SUPPORT_EN = ENABLE +#DRAM_RANGE_SCAN_SUPPORT_EN = DISABLE + +#------------------------------------------------------------------------------ +# Select GUI interface display or not +#------------------------------------------------------------------------------ +# [CONFIG_RAM_GUI_EN] +# ENABLE +# DISABLE +CONFIG_RAM_GUI_EN = DISABLE + +#------------------------------------------------------------------------------ +# Set binary file build name +#------------------------------------------------------------------------------ +CHIP_SHORT = $(shell echo $(CHIP)|awk '{print substr($$0,length($$0)-2,3)}') + +ifeq "$(STORAGEEXT)" "Eth" +LDR_NAME = loader +else +LDR_NAME = $(BIN_NAME) +endif +BL_UPDATE_CALNAME = FW96$(CHIP_SHORT)C.BIN +BL_CALIBRATION_FWNAME = CALFW680.BIN +TMP_NAME = LD96$(CHIP)1 + +#------------------------------------------------------------------------------ +# 1st NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_1st)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_1st_ = default_1 +else +ifeq "$(LOADER_SUPPORT_NAND_1st)" "" + _LOADER_NAND_SUPPORT_NAND_1st_ = default_1 +else + _LOADER_NAND_SUPPORT_NAND_1st_ = $(LOADER_SUPPORT_NAND_1st) +endif +endif +#------------------------------------------------------------------------------ +# 1st NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# 2nd NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_2nd)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_2nd_=default_2 +else +ifeq "$(LOADER_SUPPORT_NAND_2nd)" "" + _LOADER_NAND_SUPPORT_NAND_2nd_ = default_2 +else + _LOADER_NAND_SUPPORT_NAND_2nd_ = $(LOADER_SUPPORT_NAND_2nd) +endif +endif +#------------------------------------------------------------------------------ +# 2nd NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# 3rd NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_3rd)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_3rd_ = default_3 +else +ifeq "$(LOADER_SUPPORT_NAND_3rd)" "" + _LOADER_NAND_SUPPORT_NAND_3rd_ = default_3 +else + _LOADER_NAND_SUPPORT_NAND_3rd_ = $(LOADER_SUPPORT_NAND_3rd) +endif +endif + +#------------------------------------------------------------------------------ +# 3rd NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# Set bootloader specific strings +#------------------------------------------------------------------------------ +STR_MODEL = $(MODEL_DESC) +STR_DATE = $(shell date +%m/%d/%Y) +STR_TIME = $(shell date +%H:%M:%S) + +BL_START = "Loader NT98$(CHIP) Start ..." +BL_UPDATE_LOADERNAME = $(BIN_NAME).BIN + +BL_WRKEY_FWNAME := WRKEY.BIN +BL_UBOOT_FWNAME := UBOOTBIN.BIN + + +MODEL_DESC = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE)Gb_DRAM2_$(SDRAM2_SIZE)Gb" +MODEL_DESC2 = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_2ND_CLK)_$(SDRAM_2ND_SIZE)Gb_DRAM2_$(SDRAM2_2ND_SIZE)Gb" + +BL_VERSION = "$(MODEL_DESC) $(STR_DATE) $(STR_TIME)" +BL_VERSION2 = "$(MODEL_DESC2) $(STR_DATE) $(STR_TIME)" + +#------------------------------------------------------------------------------ +# Select bootloader compression +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [BL_COMPRESS] +# ENABLE +# DISABLE +BL_COMPRESS = ENABLE + +#Do not modify this parameter 0x08 if loader compress enabled +# [UNCOMPRESSEDPART_SIZE_OFFSET] +# 0x60 +# 0x08 +UNCOMPRESSEDPART_SIZE_OFFSET = 0x08 + +#------------------------------------------------------------------------------ +# Select compressable f/w (main code) +#------------------------------------------------------------------------------ +# [MAINCODE_COMPRESS] +# ENABLE +# DISABLE +MAINCODE_COMPRESS = DISABLE + +#------------------------------------------------------------------------------ +# Select firmware image checksum validation +#------------------------------------------------------------------------------ +# [CHKFWIMAGE] +# NOCHECK +# CHECKSUM +# CRC +CHKFWIMAGE = CHECKSUM + +#------------------------------------------------------------------------------ +# Select loader flow +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [LOADER_FLOW ] +# NORMAL_LDR_FLOW +# MODULE_TST_FLOW +LOADER_FLOW = NORMAL_LDR_FLOW + +ifeq "$(LOADER_FLOW)" "NORMAL_LDR_FLOW" +BL_LOADER_FLOW = 0 +else +BL_LOADER_FLOW = 1 +endif + +BL_LOADER_FLOW_PARAM = \ +-D_BL_MAIN_SPECIAL_FLOW_=$(BL_LOADER_FLOW) + +#------------------------------------------------------------------------------ +# Select Duty calibration ENABLE / DISABLE +#------------------------------------------------------------------------------ +DUTY_CALIBRATION = DISABLE + +#------------------------------------------------------------------------------ +# Select Duty calibration type +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [DUTY_CALIBRATION_TYPE ] +# AUTO +# MANUAL +DUTY_CALIBRATION_TYPE = AUTO + +ifeq "$(DUTY_CALIBRATION_TYPE)" "AUTO" +BL_DUTY_CALIBRATION_TYPE = 0 +else +BL_DUTY_CALIBRATION_TYPE = 1 +endif + +BL_DUTY_CALIBRATION_TYPE_PARAM = \ +-D_LOADER_DUTY_CALIBRATION_TYPE_=$(BL_DUTY_CALIBRATION_TYPE) + +#------------------------------------------------------------------------------ +# Select Duty calibration LOG ENABLE / DISABLE +#------------------------------------------------------------------------------ +# [DUTY_CALIBRATION_LOG] +# ENABLE +# DISABLE +DUTY_CALIBRATION_LOG = DISABLE + +ifeq "$(LOADER_FLOW)" "MODULE_TST_FLOW" +DUTY_CALIBRATION = DISABLE +endif + +ifeq "$(DUTY_CALIBRATION)" "DISABLE" +DUTY_CALIBRATION_LOG = DISABLE +else +ifeq "$(DUTY_CALIBRATION_TYPE)" "MANUAL" +DUTY_CALIBRATION_LOG = DISABLE +endif +endif + +ifeq "$(DUTY_CALIBRATION)" "ENABLE" +BL_DUTY_CALIBRATION = 1 +else +BL_DUTY_CALIBRATION = 0 +endif + +ifeq "$(DUTY_CALIBRATION_LOG)" "ENABLE" +BL_DUTY_CALIBRATION_LOG = 1 +else +BL_DUTY_CALIBRATION_LOG = 0 +endif + +BL_DUTY_CALIBRATION_PARAM = \ +-D_LOADER_DUTY_CALIBRATION_LOG_=$(BL_DUTY_CALIBRATION_LOG)\ +-D_LOADER_DUTY_CALIBRATION_=$(BL_DUTY_CALIBRATION) + + +#------------------------------------------------------------------------------ +# Bootloader update image file name parameters +#------------------------------------------------------------------------------ +BL_UPDATE_NAME_PARAM = \ + -D_UPDATE_FW_NAME_=\"$(BL_UPDATE_FWNAME)\" \ + -D_UPDATE_LOADER_NAME_=\"$(BL_UPDATE_LOADERNAME)\" \ + -D_RUN_FW_NAME_=\"$(BL_RUN_FWNAME)\" \ + -D_UPDATE_CALFW_NAME_=\"$(BL_UPDATE_CALNAME)\"\ + -D_RUN_CAL_FW_NAME_=\"$(BL_CALIBRATION_FWNAME)\" \ + -D_WR_KEY_FW_NAME_=\"$(BL_WRKEY_FWNAME)\" \ + -D_RECOVERY_FW_NAME_=\"$(BL_RECOVERY_FWNAME)\" + + +#------------------------------------------------------------------------------ +# Bootloader specific strings parameters +#------------------------------------------------------------------------------ +BL_STRINGS_PARAM = \ +-D_LOADER_VERSION_STR_=\"\\\r\\\n$(BL_VERSION)\\\r\\\n\\\r\\\n\" \ +-D_LOADER_VERSION_STR2_=\"\\\r\\\n$(BL_VERSION2)\\\r\\\n\\\r\\\n\" \ +-D_LOADER_START_STR_=\"\\\r\\\n$(BL_START)\\\r\\\n\" + +#------------------------------------------------------------------------------ +# Bootloader compression parameters +#------------------------------------------------------------------------------ +ifeq "$(BL_COMPRESS)" "ENABLE" + BL_COMPRESS_CFG = 1 + ifeq "$(CHIP)" "321" + RESETFLAG = LZ321 + else ifeq "$(CHIP)" "323" + RESETFLAG = LZ323 + else ifeq "$(CHIP)" "621" + RESETFLAG = LZ621 + else ifeq "$(CHIP)" "623" + RESETFLAG = LZ623 + else ifeq "$(CHIP)" "NC321" + RESETFLAG = LZNC321 + else ifeq "$(CHIP)" "NC323" + RESETFLAG = LZNC323 + else + RESETFLAG = LZ + endif +else + $(error BL_COMPRESS need enabled!!!) + BL_COMPRESS_CFG = 0 + ifeq "$(CHIP)" "321" + RESETFLAG = NM321 + else + RESETFLAG = NM + endif +endif + +ifeq "$(MAINCODE_COMPRESS)" "ENABLE" + FWCOMPRESS_PARAM = -D_MAINCODE_COMPRESS_=1 +else + FWCOMPRESS_PARAM = -D_MAINCODE_COMPRESS_=0 +endif + +BL_COMPRESS_PARAM = \ +-D_LOADER_COMPRESSED_=$(BL_COMPRESS_CFG) + +BL_COMPRESS_PARAM_ASM = +#\ +#-PD "_LOADER_COMPRESSED_ SETA $(BL_COMPRESS_CFG)" + +#------------------------------------------------------------------------------ +# Firmware image checksum validation parameters +#------------------------------------------------------------------------------ +ifeq "$(CHKFWIMAGE)" "NOCHECK" + CHKFWIMAGE_CFG = FW_CHECK_NOCHECK +endif + +ifeq "$(CHKFWIMAGE)" "CHECKSUM" + CHKFWIMAGE_CFG = FW_CHECK_CHECKSUM +endif + +ifeq "$(CHKFWIMAGE)" "CRC" + CHKFWIMAGE_CFG = FW_CHECK_CRC +endif + +CHKFWIMAGE_PARAM = \ + -DFW_CHECK_NOCHECK=0 \ + -DFW_CHECK_CHECKSUM=1 \ + -DFW_CHECK_CRC=2 \ + -DFW_CHECK_METHOD=$(CHKFWIMAGE_CFG) + +#------------------------------------------------------------------------------ +# External Storage define +#------------------------------------------------------------------------------ +ifeq "$(STORAGEEXT)" "Sdio1" + STORAGE_EXT_TYPE = STORAGE_EXT_SDIO1 +else ifeq "$(STORAGEEXT)" "Uart" + STORAGE_EXT_TYPE = STORAGE_EXT_UART +else ifeq "$(STORAGEEXT)" "Usb" + STORAGE_EXT_TYPE = STORAGE_EXT_USB +else ifeq "$(STORAGEEXT)" "Eth" + STORAGE_EXT_TYPE = STORAGE_EXT_ETH +else ifeq "$(STORAGEEXT)" "NONE" + STORAGE_EXT_TYPE = STORAGE_EXT_NONE +else + STORAGE_EXT_TYPE = STORAGE_EXT_UNKOWN +endif + +EXTSTRG_PARAM = \ + -DSTORAGE_EXT_UNKOWN=0 \ + -DSTORAGE_EXT_SDIO1=1 \ + -DSTORAGE_EXT_UART=2 \ + -DSTORAGE_EXT_USB=3 \ + -DSTORAGE_EXT_ETH=4 \ + -DSTORAGE_EXT_NONE=5\ + -DSTORAGE_EXT_TYPE=$(STORAGE_EXT_TYPE) + +#------------------------------------------------------------------------------ +# SPI define +#------------------------------------------------------------------------------ +ifeq "$(STORAGEINT)" "SpiFlash" + STORAGE_INT_TYPE = -DSTORAGEINT_SPI=1 +else + STORAGE_INT_TYPE = +endif + +ifeq "$(STORAGEINT)" "SpiFlash" +else ifeq "$(STORAGEINT)" "NandSpi" +else +$(error Neither SpiFlash nor NandSpi was configured @ STORAGEINT) +endif + + +ifeq "$(SPI_SETTING)" "SPI_4BITS" + SPI_PINMUX = SPI_PINMUX_4BITS +endif + +ifeq "$(SPI_SETTING)" "SPI_NORMAL" + SPI_PINMUX = SPI_PINMUX_NORMAL +endif + +SPIPINMUX_PARAM = \ + -DSPI_PINMUX_NORMAL=0 \ + -DSPI_PINMUX_4BITS=1 \ + -DSPI_PINMUX_SETTING=$(SPI_PINMUX) + +#------------------------------------------------------------------------------ +# Dram range scan support enable parameters +#------------------------------------------------------------------------------ +ifeq "$(DRAM_RANGE_SCAN_SUPPORT_EN)" "ENABLE" + DRAM_SCAN_EN = 1 +else + DRAM_SCAN_EN = 0 +endif + +DRAMSCAN_PARAM = -DDRAM_RANGE_SCAN_EN=$(DRAM_SCAN_EN) + +#------------------------------------------------------------------------------ +# Chip ID related parameters +#------------------------------------------------------------------------------ +ifeq "$(CHIP)" "321" +CHIPID = 321 +else +CHIPID = 321 +endif +#------------------------------------------------------------------------------ +# Secure boot parameters +#------------------------------------------------------------------------------ +ifeq "$(SECUREBOOT)" "Secure" +SECUREBOOT_MSG = 0 +ifeq "$(SIGNATUREMETHOD)" "AES128" +#Secure enable + AES signature +SECURE_BOOT = 1 +else +#Secure enable + RSA signature +SECURE_BOOT = 2 +endif +ifeq "$(ENCRYPTDATA)" "AES128" +ENCRYPT_DATA = 1 +else +ENCRYPT_DATA = 0 +endif +else +SECURE_BOOT = 0 +endif + + + +#------------------------------------------------------------------------------ +# DRAM ini file name generation +#------------------------------------------------------------------------------ +#ifeq "$(DRAM_TYPE)" "DDR3L" +# ifeq "$(DMA_CLOCK)" "LV0" +# $(error DDR3L only support DMA_CLOCK = LV1) +# endif +# ifeq "$(LV1_CLK)" "373" +# $(error DDR3L only support LV1_CLK = 400) +# endif +# DDR_FILE_STR = _DDR3L +#else +# DDR_FILE_STR = +#endif + +ifeq "$(DRAM_2ND_TBL_DETECT)" "1" + +ifeq "$(DRAM1_16BIT_MODE)" "Enabled" +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_16_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +else +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_32_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +endif + +ifeq "$(DRAM1_2ND_16BIT_MODE)" "Enabled" +DDR_INI2_STR = $(CHIP)/51068A_$(DRAM_2ND_TYPE)_16_$(SDRAM_2ND_SIZE)_$(SDRAM2_2ND_SIZE)_$(DRAM1_2ND_CLK)_$(DRAM_2ND_MUX).ini +else +DDR_INI2_STR = $(CHIP)/51068A_$(DRAM_2ND_TYPE)_32_$(SDRAM_2ND_SIZE)_$(SDRAM2_2ND_SIZE)_$(DRAM1_2ND_CLK)_$(DRAM_2ND_MUX).ini +endif + +2ND_INI = 1 + +else ifeq "$(DRAM_2ND_TBL_DETECT)" "2" + +ifeq "$(DRAM1_16BIT_MODE)" "Enabled" +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_16_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +else +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_32_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +endif + +ifeq "$(DRAM1_2ND_16BIT_MODE)" "Enabled" +DDR_INI2_STR = $(CHIP)/51068A_$(DRAM_2ND_TYPE)_16_$(SDRAM_2ND_SIZE)_$(SDRAM2_2ND_SIZE)_$(DRAM1_2ND_CLK)_$(DRAM_2ND_MUX).ini +else +DDR_INI2_STR = $(CHIP)/51068A_$(DRAM_2ND_TYPE)_32_$(SDRAM_2ND_SIZE)_$(SDRAM2_2ND_SIZE)_$(DRAM1_2ND_CLK)_$(DRAM_2ND_MUX).ini +endif + +2ND_INI = 2 + +else ifeq "$(DRAM_2ND_TBL_DETECT)" "3" + +ifeq "$(DRAM1_16BIT_MODE)" "Enabled" +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_16_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +else +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_32_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +endif + +ifeq "$(DRAM1_2ND_16BIT_MODE)" "Enabled" +DDR_INI2_STR = $(CHIP)/51068A_$(DRAM_2ND_TYPE)_16_$(SDRAM_2ND_SIZE)_$(SDRAM2_2ND_SIZE)_$(DRAM1_2ND_CLK)_$(DRAM_2ND_MUX).ini +else +DDR_INI2_STR = $(CHIP)/51068A_$(DRAM_2ND_TYPE)_32_$(SDRAM_2ND_SIZE)_$(SDRAM2_2ND_SIZE)_$(DRAM1_2ND_CLK)_$(DRAM_2ND_MUX).ini +endif + +2ND_INI = 3 + +else ifeq "$(DRAM_2ND_TBL_DETECT)" "4" + +ifeq "$(DRAM1_16BIT_MODE)" "Enabled" +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_16_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +else +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_32_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +endif + +ifeq "$(DRAM1_2ND_16BIT_MODE)" "Enabled" +DDR_INI2_STR = $(CHIP)/51068A_$(DRAM_2ND_TYPE)_16_$(SDRAM_2ND_SIZE)_$(SDRAM2_2ND_SIZE)_$(DRAM1_2ND_CLK)_$(DRAM_2ND_MUX).ini +else +DDR_INI2_STR = $(CHIP)/51068A_$(DRAM_2ND_TYPE)_32_$(SDRAM_2ND_SIZE)_$(SDRAM2_2ND_SIZE)_$(DRAM1_2ND_CLK)_$(DRAM_2ND_MUX).ini +endif + +2ND_INI = 4 + +else ifeq "$(DRAM_2ND_TBL_DETECT)" "5" + +ifeq "$(DRAM1_16BIT_MODE)" "Enabled" +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_16_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +else +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_32_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +endif + +ifeq "$(DRAM1_2ND_16BIT_MODE)" "Enabled" +DDR_INI2_STR = $(CHIP)/51068A_$(DRAM_2ND_TYPE)_16_$(SDRAM_2ND_SIZE)_$(SDRAM2_2ND_SIZE)_$(DRAM1_2ND_CLK)_$(DRAM_2ND_MUX).ini +else +DDR_INI2_STR = $(CHIP)/51068A_$(DRAM_2ND_TYPE)_32_$(SDRAM_2ND_SIZE)_$(SDRAM2_2ND_SIZE)_$(DRAM1_2ND_CLK)_$(DRAM_2ND_MUX).ini +endif + +2ND_INI = 5 + +else + +ifeq "$(DRAM1_16BIT_MODE)" "Enabled" +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_16_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +else +DDR_INI_STR = $(CHIP)/51068A_$(DRAM_TYPE)_32_$(SDRAM_SIZE)_$(SDRAM2_SIZE)_$(DRAM1_CLK)_$(DRAM_MUX).ini +endif + +DDR_INI2_STR = "" +2ND_INI = 0 + +endif + +#DDR_INI2_STR = $(CHIP)/51068A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE).ini + + +ifeq "$(DRAM1_POWEROFF_S3)" "Enabled" +DRAM1_RST_PARAM = 1 +else +DRAM1_RST_PARAM = 0 +endif + +ifeq "$(DRAM_WIDTH_DETECT)" "Enabled" +DRAM_WIDTH_DET_PARAM = 1 +else +DRAM_WIDTH_DET_PARAM = 0 +endif + +ifeq "$(DRAM1_16BIT_MODE)" "Enabled" +DRAM1_16BIT_PARAM = 1 +else +DRAM1_16BIT_PARAM = 0 +endif + +ifeq "$(DRAM_SSC_ENABLE)" "Normal" +DRAM_SSC_PARAM = 0 +else ifeq "$(DRAM_SSC_ENABLE)" "1" +DRAM_SSC_PARAM = 1 +else ifeq "$(DRAM_SSC_ENABLE)" "2" +DRAM_SSC_PARAM = 2 +else ifeq "$(DRAM_SSC_ENABLE)" "3" +DRAM_SSC_PARAM = 3 +else ifeq "$(DRAM_SSC_ENABLE)" "4" +DRAM_SSC_PARAM = 4 +else ifeq "$(DRAM_SSC_ENABLE)" "5" +DRAM_SSC_PARAM = 5 +else +DRAM_SSC_PARAM = 0 +endif + +ifeq "$(DRAM_HL_SWAP)" "Enabled" +DRAM_HL_SWAP_PARAM = 1 +else +DRAM_HL_SWAP_PARAM = 0 +endif + +ifeq "$(DRAM_SA_SWAP)" "Enabled" +DRAM_SA_SWAP_PARAM = 1 +else +DRAM_SA_SWAP_PARAM = 0 +endif + + + +#---------------------------------------------------------------------- +# set the scatter file name here +#---------------------------------------------------------------------- +ifeq "$(BL_COMPRESS)" "ENABLE" +SCATTER = LDS_LZ.lds +else +SCATTER = LDS_NM.lds +endif + +#---------------------------------------------------------------------- +# set loader execution DRAM address +#---------------------------------------------------------------------- +# 255MB +ifeq "$(SDRAM_SIZE)" "1024" +LD_BASE_ADDR = 0 +else ifeq "$(SDRAM_SIZE)" "2048" +LD_BASE_ADDR = 0 +else +LD_BASE_ADDR = 0 +endif +BL_LDADDR_PARAM = \ +-DLD_BASE_ADDR=$(LD_BASE_ADDR) + +#---------------------------------------------------------------------- +# set loader internal storage type +#---------------------------------------------------------------------- +BL_STORAGEINT_PARAM = \ +-D_STORAGEINT_$(STORAGEINT)_ + +#---------------------------------------------------------------------- +# Model parameters +#---------------------------------------------------------------------- +ifeq "$(MODEL)" "EMU_EVB" + MODEL_TYPE = _MODEL_EMU_EVB_ +endif + +ifeq "$(MODEL)" "DEMO1_EVB" + MODEL_TYPE = _MODEL_DEMO1_EVB_ +endif + +ifeq "$(MODEL)" "ARTOSYN_EVB" + MODEL_TYPE = _MODEL_ARTOSYN_EVB_ +endif +MODEL_PARAM = \ + -D_MODEL_EMU_EVB_=0 \ + -D_MODEL_DEMO1_EVB_=1 \ + -D_MODEL_ARTOSYN_EVB_=2 \ + -D_MODEL_DSC_=$(MODEL_TYPE) +#------------------------------------------------------------------------------- +# uboot encrypt binary or not parameters +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT_DECRYPT_UBOOT)" "Normal" + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_DISABLE_ +else ifeq "$(SECUREBOOT_DECRYPT_UBOOT)" "Secure" + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_ENABLE_ +else + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_DISABLE_ +endif + +SECURE_DECRYPT_UBOOT_PARAM = \ + -D_SECURE_DECRYPT_UBOOT_DISABLE_=0 \ + -D_SECURE_DECRYPT_UBOOT_ENABLE_=1 \ + -DSECURE_DECRYPT_UBOOT=$(UBOOT_DECRYPT_TYPE) + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +UBOOT_BIND_PARAM = \ + -D_$(UBOOT_BIND)_ \ + -D_SDRAM_SIZE_=$(SDRAM_SIZE) diff --git a/board/novatek/na51068/loader/Project/Model/Makefile b/board/novatek/na51068/loader/Project/Model/Makefile new file mode 100755 index 000000000000..176124fae9ca --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/Makefile @@ -0,0 +1,129 @@ +#---------------------------------------------------------------------- +# set the ROOT directory here +#---------------------------------------------------------------------- +ROOT_DIR = ../.. + +#---------------------------------------------------------------------- +# include make config file +#---------------------------------------------------------------------- +include ModelConfig.txt +include ModelConfig_$(MODEL).txt +include MakeConfig.txt + +#---------------------------------------------------------------------- +# set the project name here +#---------------------------------------------------------------------- +PRJ_NAME = Loader$(CHIP) + +#---------------------------------------------------------------------- +# set loader execution DRAM address +#---------------------------------------------------------------------- +ifeq "$(SDRAM_SIZE)" "1024" +# 1Gb*2 => 256MB => 0x1000_0000 +LD_BASE_ADDR = 0xF000000 +else ifeq "$(SDRAM_SIZE)" "2048" +# 2Gb*2 => 512MB => 0x2000_0000 +LD_BASE_ADDR = 0x1F000000 +else +# 4Gb*2 => 1024MB => 0x4000_0000 +LD_BASE_ADDR = 0x3F000000 +endif + +ifeq "$(LOADER_DRAM_ADDR)" "" +LD_BASE_ADDR = 0x00100000 +else +LD_BASE_ADDR = $(LOADER_DRAM_ADDR) +endif + +#---------------------------------------------------------------------- +# set the include directory here +#---------------------------------------------------------------------- +INC_DIR = . \ + ../../Include + +#---------------------------------------------------------------------- +# add/delete the project assembly files here +#---------------------------------------------------------------------- +#ASM = Src/reset.S \ +#Src/remap.S + + + + +#---------------------------------------------------------------------- +# add/delete the project C source files here +#---------------------------------------------------------------------- +SRC = \ + Src/prj_main.c \ + Src/USB/usb_update.c \ + Src/UART/uart_upgrade.c + + + + +#---------------------------------------------------------------------- +# set the image output directory here +#---------------------------------------------------------------------- +IMG_BASE_DIR = $(PRJ_NAME)_Data + +#---------------------------------------------------------------------- +# set the library directory here +#---------------------------------------------------------------------- +LIB_BASE_DIR = ../../LIB + +#---------------------------------------------------------------------- +# set the library directory here +#---------------------------------------------------------------------- +ARC_BASE_DIR = $(ROOT_DIR)/ARC + +#---------------------------------------------------------------------- +# add additional C and assembly flags here, for example, -O2 +#---------------------------------------------------------------------- +C_DEFINE_EXT = \ + $(MODEL_PARAM) \ + $(BL_UPDATE_NAME_PARAM) \ + $(BL_STRINGS_PARAM) \ + $(BL_COMPRESS_PARAM) \ + $(CHKFWIMAGE_PARAM) \ + $(FWCOMPRESS_PARAM) \ + $(BL_LOADER_VER_PARAM) \ + $(BL_LDADDR_PARAM) \ + $(EXTSTRG_PARAM) \ + $(STORAGE_INT_TYPE)\ + $(SPIPINMUX_PARAM)\ + $(DRAMSCAN_PARAM)\ + $(BL_DUTY_CALIBRATION_PARAM)\ + $(BL_DUTY_CALIBRATION_TYPE_PARAM)\ + $(BL_LOADER_FLOW_PARAM) \ + $(BL_STORAGEINT_PARAM) \ + $(SECURE_DECRYPT_UBOOT_PARAM) \ + $(UBOOT_BIND_PARAM) + +CFLAGS_R = $(C_DEFINE_EXT) +CFLAGS_D = $(C_DEFINE_EXT) + +ASMFLAGS_R = \ + $(BL_COMPRESS_PARAM_ASM) + +ASMFLAGS_D = \ + $(BL_COMPRESS_PARAM_ASM) + +GCCFLAGS = \ + $(MODEL_PARAM) \ + $(BL_UPDATE_NAME_PARAM) \ + $(BL_STRINGS_PARAM) \ + $(BL_COMPRESS_PARAM) \ + $(CHKFWIMAGE_PARAM) \ + $(FWCOMPRESS_PARAM) \ + $(BL_LOADER_VER_PARAM) \ + $(STORAGE_INT_TYPE)\ + $(DRAMSCAN_PARAM)\ + $(BL_DUTY_CALIBRATION_PARAM)\ + $(BL_DUTY_CALIBRATION_TYPE_PARAM)\ + $(BL_LOADER_FLOW_PARAM) + +#---------------------------------------------------------------------- +# include common parts of the makefile +#---------------------------------------------------------------------- +MAKE_COMMON_DIR = ../../MakeCommon +include $(MAKE_COMMON_DIR)/OutputImg.txt diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig.txt new file mode 100755 index 000000000000..1c9c0c0b901e --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig.txt @@ -0,0 +1,19 @@ +#---------------------------------------------------------------------- +# Set model here +#---------------------------------------------------------------------- +# EMU_EVB +# DEMO1_EVB +# 321_DDR3_4Gx1_NAND_SYS +# 321_DDR4_8GX1_NAND_SYS +# 323_DDR3_4GX2_NAND_EVB_SYS +# 323_DDR4_8GX2_NAND_EVB_SYS +# NC321_DDR3_4GX1_NAND_SYS +# NC323_DDR3_4GX2_NAND_EVB_SYS +# WRLD_USB_321_DDR3_4GX1_SYS +# WRLD_USB_321_DDR4_8GX1_NAND_SYS +# WRLD_USB_323_DDR3_4GX2_NAND_EVB +# WRLD_USB_323_DDR4_8GX2_SYS +# WRLD_USB_NC321_DDR3_4GX1_SYS +# WRLD_USB_NC323_DDR3_4GX2_NAND_EVB_SYS +# OpenIPC: 321_DDR3_4GX1_NOR_EVB, 323_DDR4_4GX1_NOR_EVB +MODEL = 323_DDR4_4GX1_NOR_EVB diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_321_DDR3_4GX1_NOR_EVB.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_321_DDR3_4GX1_NOR_EVB.txt new file mode 100644 index 000000000000..b6ba4008559e --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_321_DDR3_4GX1_NOR_EVB.txt @@ -0,0 +1,214 @@ +#---------------------------------------------------------------------- +# OpenIPC: 321_DDR3_4Gx1_NAND_SYS with the U-Boot on the SPI NOR +# (STORAGEINT SpiFlash), and no update from an SD card at boot +# (STORAGEEXT NONE): U-Boot recovers from the card instead. +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 321 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1066 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 0 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = UBT + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Enabled + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = SpiFlash + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = NONE + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_321_DDR3_4Gx1_NAND_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_321_DDR3_4Gx1_NAND_SYS.txt new file mode 100755 index 000000000000..243f796d6dca --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_321_DDR3_4Gx1_NAND_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 321 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1066 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 0 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = UBT + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Enabled + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Sdio1 + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_321_DDR4_8GX1_NAND_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_321_DDR4_8GX1_NAND_SYS.txt new file mode 100755 index 000000000000..87b4f5a21cdb --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_321_DDR4_8GX1_NAND_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 321 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1200 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 8192 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 0 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = UBT + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Enabled + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR4 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Sdio1 + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_323_DDR3_4GX2_NAND_EVB_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_323_DDR3_4GX2_NAND_EVB_SYS.txt new file mode 100755 index 000000000000..45d33bbc4a25 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_323_DDR3_4GX2_NAND_EVB_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 323 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1066 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 4096 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = FB + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Normal + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Sdio1 + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_323_DDR4_4GX1_NOR_EVB.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_323_DDR4_4GX1_NOR_EVB.txt new file mode 100644 index 000000000000..d25a12628a50 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_323_DDR4_4GX1_NOR_EVB.txt @@ -0,0 +1,216 @@ +#---------------------------------------------------------------------- +# OpenIPC: 321_DDR4_8GX1_NAND_SYS with the U-Boot on the SPI NOR +# (STORAGEINT SpiFlash), and no update from an SD card at boot +# (STORAGEEXT NONE): U-Boot recovers from the card instead. +# NT98323 with one 4 Gb DDR4 die, as the SDK's cfg_98323_DDR4_4GX1_NOR_EVB: +# CHIP 323, SDRAM_SIZE 4096, DRAM_MUX FB. +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 323 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1200 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 0 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = FB + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Enabled + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR4 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = SpiFlash + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = NONE + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_323_DDR4_8GX2_NAND_EVB_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_323_DDR4_8GX2_NAND_EVB_SYS.txt new file mode 100755 index 000000000000..547858eb46ac --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_323_DDR4_8GX2_NAND_EVB_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 323 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1200 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 8192 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 8192 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = FB + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Normal + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR4 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Sdio1 + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_EMU_EVB.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_EMU_EVB.txt new file mode 100755 index 000000000000..8b3deaf7769e --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_EMU_EVB.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 323 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1200 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 4096 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = FB + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Normal + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR4 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Sdio1 + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_NC321_DDR3_4GX1_NAND_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_NC321_DDR3_4GX1_NAND_SYS.txt new file mode 100755 index 000000000000..d81ce46c64e2 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_NC321_DDR3_4GX1_NAND_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = NC321 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1066 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 0 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = UBT + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Enabled + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Sdio1 + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_NC323_DDR3_4GX2_NAND_EVB_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_NC323_DDR3_4GX2_NAND_EVB_SYS.txt new file mode 100755 index 000000000000..e56701408d5d --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_NC323_DDR3_4GX2_NAND_EVB_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = NC323 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1066 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 4096 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = FB + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Normal + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Sdio1 + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_321_DDR3_4GX1_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_321_DDR3_4GX1_SYS.txt new file mode 100755 index 000000000000..453fbf72fcbe --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_321_DDR3_4GX1_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 321 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1066 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 0 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = UBT + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Enabled + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Usb + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_321_DDR4_8GX1_NAND_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_321_DDR4_8GX1_NAND_SYS.txt new file mode 100755 index 000000000000..afacb7b4989d --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_321_DDR4_8GX1_NAND_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 321 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1200 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 8192 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 0 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = UBT + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Enabled + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR4 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Usb + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_323_DDR3_4GX2_NAND_EVB.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_323_DDR3_4GX2_NAND_EVB.txt new file mode 100755 index 000000000000..c7cce82189b5 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_323_DDR3_4GX2_NAND_EVB.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 323 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1066 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 4096 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = FB + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Normal + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Usb + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_323_DDR4_8GX2_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_323_DDR4_8GX2_SYS.txt new file mode 100755 index 000000000000..3bc05f982493 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_323_DDR4_8GX2_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = 323 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1200 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 8192 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 8192 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = FB + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Normal + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR4 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Usb + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_NC321_DDR3_4GX1_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_NC321_DDR3_4GX1_SYS.txt new file mode 100755 index 000000000000..3468ae0ff0dc --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_NC321_DDR3_4GX1_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = NC321 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1066 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 0 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = UBT + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Enabled + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Usb + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_NC323_DDR3_4GX2_NAND_EVB_SYS.txt b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_NC323_DDR3_4GX2_NAND_EVB_SYS.txt new file mode 100755 index 000000000000..b2f5ac65924b --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/ModelConfig_WRLD_USB_NC323_DDR3_4GX2_NAND_EVB_SYS.txt @@ -0,0 +1,210 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN +BL_RECOVERY_FWNAME = FW98$(CHIP_SHORT)R.BIN + +# [CHIP] : main chip ID +# 321 +# 323 +# 621 +# 623 +# NC321 +CHIP = NC323 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_CLK = 1066 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_SIZE = 4096 + +# [SDRAM2_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_SIZE = 4096 + +# [DRAM_MUX] : Dram mux +# FB +# UBT +DRAM_MUX = FB + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Enabled + +# [DRAM_WIDTH_DETECT] : enable DRAM1 width detect by P_GPIO16 (only valid with 98535) +# Normal +# Enabled +#DRAM_WIDTH_DETECT = Enabled + +# [DRAM1_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_16BIT_MODE = Normal + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO. When gpio high, using 2nd ini table; when gpio low, using original table +# 0: Normal +# 1: GPIO0_4 +# 2: GPIO0_26 +# 3: GPIO1_0 +# 4: GPIO1_1 +# 5: GPIO1_10 +DRAM_2ND_TBL_DETECT = 0 + +# [DRAM1_2ND_CLK] : DRAM1 clock rate +# 800 +# 933 +# 1066 +# 1200 +# 1333 (DDR4 only) +# 1600 (DDR4 only) +DRAM1_2ND_CLK = 1333 + +# [SDRAM_2ND_SIZE] : DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM_2ND_SIZE = 8192 + +# [SDRAM2_2ND_SIZE] : DRAM2 Size (unit: Giga bit) +# 0 +# 1024 +# 2048 +# 4096 +# 8192 +SDRAM2_2ND_SIZE = 8192 + +# [DRAM_2ND_MUX] : Dram mux +# FB +# UBT +DRAM_2ND_MUX = FB + +# [DRAM1_2ND_16BIT_MODE] : DRAM1 only connect one ddr chip +# Normal +# Enabled +DRAM1_2ND_16BIT_MODE = Normal + +# [DRAM_2ND_TYPE] : DRAM Type +# DDR3 +# DDR3L +# DDR4 +DRAM_2ND_TYPE = DDR4 + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_HL_SWAP] : ddr high byte low byte swap (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb (original) when this option open will change to 2Gb+4Gb +# Normal: origin(big+small) +# Enabled: big+small --> small+big +DRAM_HL_SWAP = Normal + +# [DRAM_SA_SWAP] : ddr system address 0x0 mapping to 16bit ddr or 32bit ddr (only in heterogeneous mode) +# for example: ddr 4Gb+2Gb original mapping address 0x0 to 32bit ddr when this option open will change address 0x0 mapping to 16bit ddr +# Normal: origin(mapping to 32bit ddr) +# Enabled: mapping to 16bit ddr +DRAM_SA_SWAP = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +STORAGEINT = NandSpi + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth +# Uart +STORAGEEXT = Usb + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = RSA2048 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x20000 +LOADER_DRAM_ADDR = 0x00100000 +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader bind uboot # +#==============================================================================# +# [UBOOT_BIND] +# UBOOT_BIND_ON +# UBOOT_BIND_OFF +UBOOT_BIND = UBOOT_BIND_OFF + +# [UBOOT_PATH] (relative to Model/Makefile) +UBOOT_PATH = ../../u-boot.lzma.bin diff --git a/board/novatek/na51068/loader/Project/Model/Src/UART/uart_upgrade.c b/board/novatek/na51068/loader/Project/Model/Src/UART/uart_upgrade.c new file mode 100755 index 000000000000..e65a7d7a9d04 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/Src/UART/uart_upgrade.c @@ -0,0 +1,211 @@ +#include +#include "constant.h" +#include "top_ctrl.h" +#include "uart_upgrade.h" +#include "rcw_macro.h" +#include "scsi_op.h" +#include "debug.h" +#include "debug.h" +#include "global.h" + +UART_Verify_CB guiUARTCheck_cb; +UART_Vendor_CB guiUARTVendor_cb; +static int uartrom_exit = 0; +static unsigned int chipid = 0; +static CONSOLE_OBJ *m_console = NULL; +static INT32U nvtuart_opened = 1; + +static INT32U calc_sum(INT32U dat0, INT32U dat1, INT32U dat2, INT32U dat3) +{ + INT32U sum = 0; + + sum = (dat0 & 0xFFFF) + ((dat0 >> 16)) + (dat1 & 0xFFFF) + ((dat1 >> 16)) + + (dat2 & 0xFFFF) + ((dat2 >> 16)) + (dat3 & 0xFFFF) + ((dat3 >> 16)) + 28; + + return sum & 0xFFFF; +} + +static INT32U make_sum(INT32U dat0, INT32U dat1, INT32U dat2, INT32U dat3) +{ + INT32U sum = 0; + + sum = (dat0 & 0xFFFF) + ((dat0 >> 16)) + (dat1 & 0xFFFF) + ((dat1 >> 16)) + + (dat2 & 0xFFFF) + ((dat2 >> 16)) + (dat3 & 0xFFFF) + ((dat3 >> 16)) + 28; + + sum = (~sum + 1) & 0xFFFF; + + return sum; +} + +static int recv_data(char *p, unsigned int len) +{ + while (len) { + *p = m_console->getc(); + p++; + len--; + } + return 0; +} + +static int send_data(char *p, unsigned int len) +{ + while (len) { + m_console->putc(*p); + p++; + len--; + } + return 0; +} + +static void uart_send_csw(INT32U *cdb, int er) +{ + char *p_cdb = (char *)cdb; + p_cdb[IDX_CDB_UART_STATUS_ER] = er; + + unsigned int sum = make_sum(cdb[0], cdb[1], cdb[2], (cdb[3] & 0xFFFF)); + cdb[3] |= sum << 16; + + send_data((char *)cdb, sizeof(INT32U) * 4); +} + + +static int uart_cmd(INT32U *cdb) +{ + unsigned int cmd_id = ((cdb[0] >> 8) & 0xFF); + unsigned int insize = ((cdb[1] >> 16) & 0xFFFF) + ((cdb[2] & 0xFFFF) << 16); + unsigned int tmp1, tmp2; + + switch (cmd_id) { + case SCSIOP_OUT_OPEN_DEVICE: + nvtuart_opened = 1; + uart_send_csw(cdb, 0); + break; + + case SCSIOP_IN_WAIT_DONE: + uartrom_exit = 1; + uart_send_csw(cdb, 0); + break; + + case SCSIOP_IN_IS_NVT: + chipid = uart_read_reg(TOP_CTRL_VERSION_REG); + uart_send_csw(cdb, 0); + send_data((char *)&chipid, sizeof(chipid)); + break; + + case SCSIOP_OUT_ADDR_WRITE: + tmp1 = ((cdb[0] >> 16) & 0xFFFF) + ((cdb[1] & 0xFFFF) << 16); //addr + tmp2 = ((cdb[1] >> 16) & 0xFFFF) + ((cdb[2] & 0xFFFF) << 16); //data + *(INT32U *)tmp1 = tmp2; + __asm__ __volatile__("dsb\n\t"); + uart_send_csw(cdb, 0); + break; + + case SCSIOP_IN_ADDR_READ: + tmp1 = ((cdb[0] >> 16) & 0xFFFF) + ((cdb[1] & 0xFFFF) << 16); //addr + tmp2 = *(INT32U *)tmp1; + __asm__ __volatile__("dsb\n\t"); + uart_send_csw(cdb, 0); + send_data((char *)&tmp1, sizeof(tmp2)); //repeat addr + send_data((char *)&tmp2, sizeof(tmp2)); //reply data + break; + + default: + if (guiUARTCheck_cb != NULL) { + NVT_SCSI_CBW cbw; + unsigned int OutDataBuf = 0; + utl_memset(&cbw, 0, sizeof(cbw)); + cbw.dCBWDataTransferLength = insize; + utl_memcpy(cbw.CBWCB, cdb, 4 * sizeof(unsigned int)); + int er = guiUARTCheck_cb((unsigned int)&cbw, (unsigned int *)&OutDataBuf, (unsigned int *)&insize); + utl_memcpy(cdb, cbw.CBWCB, 4 * sizeof(unsigned int)); + if (er != 0) { + uart_send_csw(cdb, 1); + return -1; + } else { + uart_send_csw(cdb, 0); + } + if ((cmd_id & 0x80)) { + //dir-in + guiUARTVendor_cb((unsigned int)&cbw); + if (insize) { + send_data((char *)OutDataBuf, insize); + } + } else { + //dir-out + if (insize) { + recv_data((char *)OutDataBuf, insize); + } + guiUARTVendor_cb((unsigned int)&cbw); + } + } + break; + + } + return 0; +} + +static void uart_upgrade_routine(void) +{ + static int idx_cdb = 0; + static INT32U cdb[4] = {0}; + + char *p_cdb = (char *)cdb; + + p_cdb[idx_cdb++] = m_console->getc(); + + // loop to cdb fill 16 bytes + if (idx_cdb < 16) { + return ; + } + + idx_cdb = 0; // reset idx + + // Parse SCSI command + if (!(((cdb[0] & 0xFF) == SCSI_OP_SET0) || ((cdb[0] & 0xFF) == SCSI_OP_SET1) || ((cdb[0] & 0xFF) == SCSI_OP_SET2))) { + uart_send_csw(cdb, 1); + debug_err("uart opset ng.\r\n"); + } + + if (calc_sum(cdb[0], cdb[1], cdb[2], cdb[3]) != 0) { + uart_send_csw(cdb, 1); + debug_err("uart cmd sum ng.\r\n"); + return; + } + + uart_cmd(cdb); +} + +void uart_upgrade_procedure() +{ + if(utl_get_chipversion() != CHIPVER_A) { + m_console = get_uart_object(CONSOLE_UART0); + } else { + m_console = get_uart_object(CONSOLE_UART1); + } + + m_console->hook(); + + while (1) { + + if (uartrom_exit > 0) { + break; + } + + uart_upgrade_routine(); + } + + uartrom_exit = 0; + +} + +void loader_installUART_Verify_CB(UART_Verify_CB callback) +{ + guiUARTCheck_cb = callback; +} + +void loader_installUART_Vendor_CB(UART_Vendor_CB callback) +{ + guiUARTVendor_cb = callback; +} + + diff --git a/board/novatek/na51068/loader/Project/Model/Src/UART/uart_upgrade.h b/board/novatek/na51068/loader/Project/Model/Src/UART/uart_upgrade.h new file mode 100755 index 000000000000..e86ca378a441 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/Src/UART/uart_upgrade.h @@ -0,0 +1,100 @@ +#ifndef __UART_UPGRADE_H + #define __UART_UPGRADE_H + + +/** + Open NVT Device + + The commands except SCSIOP_IN_IS_NVT can be run if open device success. + If not open first, the operation commands got CSW Status 0x1 means command failed. + + @DATA_PHASE: None. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_OUT_OPEN_DEVICE 0x01C0 + + +/** + Send Write Loader + + The Write Address @ CDB[2]~[5]; + For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE + CDB[6]~[16] shall follow checksum rule. Content is dont care. + + @DATA_PHASE: OUT. Size is at CBW[8]~[11] DataTransferLength. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_OUT_WRLOADER 0x02C0 + +/** + Address WRITE WORD (DRAM/REG/SRAM dont care) + + The Write Address @ CDB[2]~[5]; + For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE + The Write DATA @ CDB[6]~[9]. + For example address 0x12345678 shall fill CDB[6]=0x78 CDB[7]=0x56 CDB[8]=0x34 CDB[9]=0x12 + CDB[10]~[15] shall follow checksum rule. Content is dont care. + + @DATA_PHASE: None. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_OUT_ADDR_WRITE 0x03C0 + +/** + Address READ WORD (DRAM/REG/SRAM dont care) + + The READ Address @ CDB[2]~[5]; + For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE + CDB[6]~[15] shall follow checksum rule. Content is dont care. + + @DATA_PHASE: IN 8 bytes return. DATA[0]~[3] is repeat CDB address. Read out DATA is [3] ~[7]. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_IN_ADDR_READ 0x83C0 + + +/** + Ask if NVT Device + + CDB[2]~[15] shall follow checksum rule + + @DATA_PHASE: IN 4 bytes return; The value 0x81200000 woule be return for 98321. <8321 = 0x2081> If checksum fail, the 0x0 would be returned. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. + +*/ +#define UARTOP_IN_IS_NVT 0x81C0 // ???O???O???a?? device (?o?????n?? SCSIOP_IN_OPEN_DEVICE) + + +/** + End USB ROM CODE. + + Exit USB ROM code after receiving this command. The checksum must be correct. + + CDB[2]~[15] shall follow checksum rule + + @DATA_PHASE: None. + @CSW_PHASE status code: 0 is success and end usb rom. 0x1 means checksum failed. +*/ +#define UARTOP_IN_WAIT_DONE 0x82C0 + + +typedef int (*UART_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); ///< Callback for verify the Vendor Command is supported or not +typedef int (*UART_Vendor_CB)(unsigned int pCmdBuf); ///< Callback for Vendor Command processing + + +extern void loader_installUARTCB(UART_Verify_CB callback); +extern void uart_upgrade_procedure(void); + +static __inline unsigned int uart_read_reg(unsigned int reg) +{ + return *((volatile unsigned int *)reg); +} + +static __inline void uart_write_reg(unsigned int reg, unsigned int value) +{ + *((volatile unsigned int *)reg) = value; +} + + + +#endif diff --git a/board/novatek/na51068/loader/Project/Model/Src/USB/usb_update.c b/board/novatek/na51068/loader/Project/Model/Src/USB/usb_update.c new file mode 100755 index 000000000000..05f1f52373b8 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/Src/USB/usb_update.c @@ -0,0 +1,1240 @@ + +#include "board.h" +#include "fuart.h" +#include "usb_update.h" +#include "debug.h" +#include "timer.h" + +#define IOADDR_USB_REG_BASE (0xF9100000) + + +void fLib_USB_Update_FW(void); + +int usbrom_exit = 0; +volatile DEV *ptusbdev; +#define ptotg ((volatile OTG200 *)IOADDR_USB_REG_BASE) + +#define FUSB200_MAX_EP 8 // 1..10 +#define FUSB200_MAX_FIFO 4 // 0.. 9 + +#define mUsbEPMap(EPn, MAP) (ptusbdev->ep_map[EPn-1] = MAP) +#define mUsbEPMapRd(EPn) (ptusbdev->ep_map[EPn-1]) + +#define mUsbFIFOMap(FIFOn, MAP) (ptusbdev->fifo_map[FIFOn] = MAP) +#define mUsbFIFOMapRd(FIFOn) (ptusbdev->fifo_map[FIFOn]) +#define mUsbFIFOConfigRd(FIFOn) (ptusbdev->fifo_cfg[FIFOn]) + +static USB_st tusb; +static MassStorageState eUsbMassStorageState = MS_STATE_CBW; +CBW tCBW; +CSW tCSW; +SCSISense tSCSIsense; +SCSIDeviceResp tSCSIDeviceResp; + +MSDC_Verify_CB guiU2MsdcCheck_cb; +MSDC_VenDone_CB guiU2MsdcVendorDone_cb; + +int trigger_done_cb = 0; + +static const unsigned char u8RequestSenseData[DATA_LENGTH_REQUEST_SENSE] __attribute__((aligned(4))) = +{ + 0x70, // 0, response code + 0x00, // 1, obsolete + 0x00, // 2, sense key + 0x00, // 3-6, information + + 0x00, + 0x00, + 0x00, + 0x0A, // 7, additional length (n - 7), n = 17 + + 0x00, // 8-11, information + 0x00, + 0x00, + 0x00, + + 0x00, // 12, additional sense code + 0x00, // 13, additional sense code qualifier + 0x00, // 14, field replaceable unit code + 0x00, // 15-17, sense-key specific + + 0x00, + 0x00 +}; + + +static const unsigned char u8ModeSenseData[DATA_LENGTH_MODE_SENSE] __attribute__((aligned(4))) = +{ + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + + +#define USB_BUFF_SZ 128 +unsigned int u32Usb_buffer[USB_BUFF_SZ/4]; // may less than USB_BUFF_SZ + +static INT32U nvtdev_opened = 1; +#define mCxType(cmd) ((cmd[0] & (BIT6 | BIT5)) >> 5) +#define mCxRequest(cmd) ((unsigned char)(cmd[0] >> 8)) +#define mCxValue(cmd) ((unsigned short)(cmd[0] >> 16)) // get 3rd byte, 4th byte +#define mCxIndex(cmd) ((unsigned short)(cmd[1])) // get 5th byte, 6th byte +#define mCxLength(cmd) ((unsigned short)(cmd[1] >> 16)) // get 7th byte, 8th byte + + +#define mUsbRmWkupST() (ptusbdev->main_ctl & BIT0) +#define mUsbRmWkupClr() (ptusbdev->main_ctl &= ~BIT0) +#define mUsbRmWkupSet() (ptusbdev->main_ctl |= BIT0) +#define mUsbTsMdWr(item) (ptusbdev->phy_tms = item) +#define mUsbIntF2OUTDis() (ptusbdev->int_mgrp1 |= (BIT5 | BIT4)) +#define mUsbIntF2OUTEn() (ptusbdev->int_mgrp1 &= ~(BIT5 | BIT4)) +#define mUsbIntF0INDis() (ptusbdev->int_mgrp1 |= BIT16) +#define mUsbIntF0INEn() (ptusbdev->int_mgrp1 &= ~BIT16) +// Endpoint & FIFO Configuration +#define mUsbEPMxPtSz(EPn, dir, size) (ptusbdev->ep_xpsz[dir][EPn - 1] = size) +#define mUsbEPStallST(EPn, dir) (((ptusbdev->ep_xpsz[dir][EPn - 1]) & BIT11) >> 11) +#define mUsbEPRsTgSet(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] |= BIT12) +#define mUsbEPRsTgClr(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] &= ~BIT12) +#define mUsbEPStallClr(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] &= ~BIT11) +#define mUsbEPStallSet(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] |= BIT11) + +extern void CPUflushReadCache(UINT32 uiStartAddr, UINT32 uiLength); +extern void CPUflushWriteCache(UINT32 uiStartAddr, UINT32 uiLength); + +INT32S my_SCSICmd(CBW * ptcbw); + +signed int usb_DxFifoRdWr(unsigned char * buf, unsigned int count, unsigned int Rd) +{ + signed int ret = -1; // assume fail + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: enter usb_DxFifoRdWr\r\n"); + //#endif + + CPUflushWriteCache((UINT32) buf, (UINT32) count); + CPUflushReadCache((UINT32) buf, (UINT32) count); + + //#ifdef __FREERTOS + //if(buf == (unsigned char *)0xFE080000) + // ptusbdev->dma_addr = (INT32U)buf; + //else + // ptusbdev->dma_addr = dma_getPhyAddr(buf); + + //dma_flushWriteCache((UINT32)buf, count); + //dma_flushReadCache((UINT32)buf, count); + //#else + ptusbdev->dma_addr = (INT32U)buf;//dma_getPhyAddr(buf); + + __asm__ __volatile__("dsb\n\t"); + //#endif + + + if (Rd) { + // fifo select + ptusbdev->dma_fifo = BIT2; + // ctrl setting + ptusbdev->dma_ctl = (count << 8) | // dma byte count + (0 << 2) | // not dma io to io + (0 << 1); // fifo 2 memory + + #ifdef USBROM_RTOS_DBG + debug_msg("MSG: count = %d, Read CTRL = %x\r\n", count, ptusbdev->dma_ctl); + #endif + + } else { + // fifo select + ptusbdev->dma_fifo = BIT0; + // ctrl setting + ptusbdev->dma_ctl = (count << 8) | // dma byte count + (0 << 2) | // not dma io to io + (1 << 1); // memory 2 fifo + + #ifdef USBROM_RTOS_DBG + debug_msg("MSG: Write count = %d, Write CTRL = %x\r\n", count, ptusbdev->dma_ctl); + #endif + } + + // dma start + ptusbdev->dma_ctl |= BIT0; + + while (1) { + INT32U temp; + + temp = ptusbdev->int_grp2 & ~ ptusbdev->int_mgrp2; + + if (temp & BIT7) { // dma completion + ret = 0; // ok + break; + } + if (temp & (BIT2 | BIT1)) { // bus condiction + // clear cx fifo + ptusbdev->cx_cf |= BIT3; + break; + } + if (temp & BIT8) { // dma error + // clear cx fifo + ptusbdev->cx_cf |= BIT3; + break; + } + } + + // clear (dma error & dma completion) interrupt + ptusbdev->int_grp2 |= (BIT8 | BIT7); + CPUflushReadCache((UINT32) buf, (UINT32) count); + + //debug_msg("done\r\n"); + + //#ifdef __FREERTOS + //dma_flushReadCache((UINT32)buf, count); + //#endif + + return ret; +} + +void vSCSIHWError(void) +{ + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + if ((tCBW.CB0_cblen_lun_flag&0xFF) == CBW_FLAG_OUT) { + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + } else { + //debug_msg("S1\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + } + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: vSCSIHWError\r\n"); + //#endif + + tSCSIsense.u8Key = KEY_NOT_READY; + tSCSIsense.u8KeyAdd = ADDKEY_MEDIUM_NOT_PRESENT; +} + + +////////////////////////////////////////////////////////////////////////////////// +MassStorageState eScsiIn(void) +{ + + switch (tSCSIDeviceResp.u8MemIndex) { + case CARD_INDEX_SRAM: + // unit: byte + if (usb_DxFifoRdWr((INT8U *)u32Usb_buffer, tSCSIDeviceResp.u16DataResidue, 0) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + if (tCSW.u32DataResidue) { + // wait for fifo empty + while ((ptusbdev->cx_cf & (BIT8 | BIT9)) != (BIT8 | BIT9)) { + // if (VBUS == 0) + // return MS_STATE_CSW; + } + //debug_msg("S2\r\n"); + //mUsbEPStallSet(IN_EP, DIRECTION_IN); // case MS13Case_5: + } + return MS_STATE_CSW; + } + break; + + case CARD_INDEX_FSM_SS: + if (usb_DxFifoRdWr((INT8U *)tSCSIDeviceResp.u32IOAddr, tSCSIDeviceResp.u16DataResidue, 0) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + return MS_STATE_CSW; + } else { + mUsbEPStallSet(OUT_EP, DIRECTION_IN); // case MS13Case_11: + } + break; + + + default: + break; + } + vSCSIHWError(); + return MS_STATE_CSW; +} + + +////////////////////////////////////////////////////////////////////////////////// +MassStorageState eScsiOut(void) +{ + switch (tSCSIDeviceResp.u8MemIndex) { + case CARD_INDEX_SRAM: + if (usb_DxFifoRdWr((INT8U *)u32Usb_buffer, tSCSIDeviceResp.u16DataResidue, 1) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + if (tCSW.u32DataResidue) + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); // case MS13Case_11: + return MS_STATE_CSW; + } + break; + + case CARD_INDEX_FSM_SS: + if (usb_DxFifoRdWr((INT8U *)tSCSIDeviceResp.u32IOAddr, tSCSIDeviceResp.u16DataResidue, 1) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + return MS_STATE_CSW; + } else { + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); // case MS13Case_11: + } + break; + default: + break; + } + vSCSIHWError(); + return MS_STATE_CSW; +} + +typedef unsigned int size_t; +extern void *utl_memcpy(void *dest, const void *src, size_t count); + +void vSCSICmd_RequestSense(void) +{ + // Device intend to send data + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + tSCSIDeviceResp.u16DataResidue = sizeof(u8RequestSenseData); + + // copy response to sram + utl_memcpy ((UINT32 *)u32Usb_buffer, (UINT32 *)u8RequestSenseData, (UINT32)sizeof(u8RequestSenseData)); + + *((unsigned int *)u32Usb_buffer + (SENSE_OFFSET_KEY>>2)) += (tSCSIsense.u8Key&0xFF)<<16; + *((unsigned int *)u32Usb_buffer + (SENSE_OFFSET_ADD>>2)) += (tSCSIsense.u8KeyAdd&0xFF); + + // all key disappear + tSCSIsense.u8Key = KEY_NO_SENSE; + tSCSIsense.u8KeyAdd = ADDKEY_NO_ADDITIONAL; +} + +void vSCSICmd_ModeSense(void) +{ + + //switch (tCBW.u8CB[2]) { + switch ((tCBW.CB1_CB15[0]>>8)&0xFF) { + case 0x00: // return mode parameter header and block descriptor + //debug_msg("MODE_SENSE 00\r\n"); + tSCSIDeviceResp.u16DataResidue = 0x0C; + break; + case 0x3F: // all pages + //debug_msg("MODE_SENSE 3F\r\n"); + tSCSIDeviceResp.u16DataResidue = sizeof(u8ModeSenseData); + break; + default: + //debug_msg("MODE_SENSE ERR\r\n"); + tSCSIsense.u8Key = KEY_ILLEGAL_REQUEST; + tSCSIsense.u8KeyAdd = ADDKEY_INVALID_FIELD_IN_CMD; + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + return; + } + // Device intend to send data + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + + // copy response to sram + utl_memcpy((UINT32 *)u32Usb_buffer, (UINT32 *)u8ModeSenseData, (UINT32)tSCSIDeviceResp.u16DataResidue); +} + + + +void vSCSICmd_Unsupport(void) +{ + // Device intend to transfer no data + tSCSIsense.u8Key = KEY_ILLEGAL_REQUEST; + tSCSIsense.u8KeyAdd = ADDKEY_INVALID_CMD_OP_CODE; + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + + //#ifdef DISPLAY_USB_INFORMATION + //DBG_DUMP("MSG: UnSupported SCSI Command (op code = 0x%x)\r\n", tCBW.u8CB[0]); + //#endif +} + +MassStorageState eMassStorage13case(void) +{ + MassStorage13Case eCase = 0x0; + MassStorageState estate; + INT32U u32DeviceRespDataLength = 0x0; + + switch(tSCSIDeviceResp.u8MemIndex) { + case CARD_INDEX_SRAM: + u32DeviceRespDataLength = tSCSIDeviceResp.u16DataResidue; + tSCSIDeviceResp.u32IOAddr += tSCSIDeviceResp.u16TfSzCurrent; + break; + case CARD_INDEX_FSM_SS: + u32DeviceRespDataLength = tSCSIDeviceResp.u16DataResidue; + break; + default:// SPI + u32DeviceRespDataLength = tSCSIDeviceResp.u16DataResidue * 2112; + break; + } + + // Mass Storage the thirteen case + if (tCBW.u32DataTransferLength == u32DeviceRespDataLength) { + // normal case + if (tCBW.u32DataTransferLength == 0) + eCase = MS13Case_1; // MassStorage case (1) + else { + if ((tCBW.CB0_cblen_lun_flag&0xFF) == tSCSIDeviceResp.u8Flags) { + if ((tCBW.CB0_cblen_lun_flag&0xFF) == CBW_FLAG_IN) + eCase = MS13Case_6; // MassStorage case (6) + else + eCase = MS13Case_12; // MassStorage case (12) + } + } + + //#ifdef DISPLAY_USB_INFORMATION + // vShowSCSI(); + //#endif + + } else { + if (tCBW.u32DataTransferLength == 0) + eCase = MS13Case_2_3; // MassStorage case (2)(3) + else if ((tCBW.CB0_cblen_lun_flag&0xFF) == CBW_FLAG_IN) { + if (u32DeviceRespDataLength == 0) + eCase = MS13Case_4; // MassStorage case (4) + else if (tSCSIDeviceResp.u8Flags == CBW_FLAG_IN) { + if (tCBW.u32DataTransferLength > u32DeviceRespDataLength) + eCase = MS13Case_5; // MassStorage case (5) + else + eCase = MS13Case_7_8; // MassStorage case (7)(8) + } + } + else { //tCBW.u8Flags == CBW_FLAG_OUT + if (u32DeviceRespDataLength == 0) + eCase = MS13Case_9; // MassStorage case (9) + else if (tSCSIDeviceResp.u8Flags == CBW_FLAG_OUT) { + if (tCBW.u32DataTransferLength > u32DeviceRespDataLength) + eCase = MS13Case_11; // MassStorage case (11) + else + eCase = MS13Case_10_13; // MassStorage case (10)(13) + } + } + +//#ifdef DISPLAY_USB_INFORMATION +// { + //vShowUsb(); +// DBG_DUMP("MSG: MS13Case = 0x%x\r\n", eCase); +// DBG_DUMP("MSG: , u32DeviceRespDataLength = 0x%x\r\n", u32DeviceRespDataLength); +// } +//#endif + + } + + // assume the next state is STATE_CSW + estate = MS_STATE_CSW; + switch (eCase) { + case MS13Case_2_3: + //debug_msg("S3\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + tCSW.u8Status = CSW_STATUS_PHASE_ERROR; + break; + case MS13Case_4: + //debug_msg("S4\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + break; + case MS13Case_5: + case MS13Case_6: + estate = eScsiIn(); + break; + case MS13Case_11: + case MS13Case_12: + estate = eScsiOut(); + break; + case MS13Case_7_8: + //debug_msg("S5\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + tCSW.u8Status = CSW_STATUS_PHASE_ERROR; + break; + case MS13Case_9: + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + break; + case MS13Case_10_13: + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + tCSW.u8Status = CSW_STATUS_PHASE_ERROR; + //debug_msg("S6\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + break; + default: // MS13Case_1; + // do nothing here + break; + } + return estate; +} + + +MassStorageState eSCSI_CmdDecode(void) //trace, different from FUSB100-CardReader +{ + //debug_msg("eSCSI_CmdDecode\r\n"); + // Assume SCSI Response data length will be 0 + tSCSIDeviceResp.u16DataResidue = 0; + if (((tCBW.CB0_cblen_lun_flag >> 8)&0xFF) >= CARD_TYPE_MAX_REPORT) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + tSCSIsense.u8Key = KEY_NOT_READY; + tSCSIsense.u8KeyAdd = ADDKEY_LOGICAL_UNIT_NOT_SUPPORT; + } else { + // Parse SCSI command + //switch (tCBW.u8CB[0]) { // Operation Code + switch ((tCBW.CB0_cblen_lun_flag >> 24)&0xFF) { // Operation Code + case SCSI_OP_REQUEST_SENSE: + vSCSICmd_RequestSense(); + //debug_msg("vSCSICmd_RequestSense\r\n"); + break; + case SCSI_OP_MEDIUM_REMOVAL: + //vSCSICmd_MediumRemoval(); + debug_msg("SCSI_OP_MEDIUM_REMOVAL\r\n"); + break; + case SCSI_OP_INQUIRY: + //vSCSICmd_Inquiry(); + debug_msg("SCSI_OP_INQUIRY\r\n"); + break; + case SCSI_OP_MODE_SENSE: + vSCSICmd_ModeSense(); + //debug_msg("SCSI_OP_MODE_SENSE 22\r\n"); + break; + + case SCSI_OP_TEST_UNIT_READY: + case SCSI_OP_READ_CAPACITY: + case SCSI_OP_READ_10: + case SCSI_OP_WRITE_10: + case SCSI_OP_VERIFY: + //debug_msg("SCSI_OP_TEST_UNIT_READY\r\n"); + tSCSIsense.u8Key = KEY_NOT_READY; + tSCSIsense.u8KeyAdd = ADDKEY_MEDIUM_NOT_PRESENT; + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + break; + + default: + if (my_SCSICmd(&tCBW) < 0) { + //#ifdef USBROM_RTOS_DBG + debug_msg("MSG: SCSI cmd: UNSUPPOR\r\n"); + //#endif + vSCSICmd_Unsupport(); + } + break; + } + } + return eMassStorage13case(); +} + + + + + +MassStorageState eUsbProessCBW(void) +{ + usb_DxFifoRdWr((unsigned char *)&tCBW, 31, 1); + + if(tCBW.u32Signature != CBW_SIGNATE) { + return MS_STATE_CBW; + } else { + // pass u32DataTransferLength to u32DataResidue + tCSW.u32DataResidue = tCBW.u32DataTransferLength; + + #ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: tCSW.u32DataResidue = %d, dir = %d\r\n", tCBW.u32DataTransferLength, tCBW.u8Flags); + #endif + + // pass Tag from CBW to CSW + tCSW.u32Tag = tCBW.u32Tag; + // Assume Status is CMD_PASS + tCSW.u8Status = CSW_STATUS_CMD_PASS; + + return eSCSI_CmdDecode(); + } +} + +void vUsbUnplug(void) +{ + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: Unplug.. pls check\r\n"); + //#endif + // mUsbUnPlug(); + ptusbdev->phy_tms |= BIT0; +} + +void vUsb_BulkIntOnOff(void) +{ + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: st 0x%x", eUsbMassStorageState); + //#endif + + switch(eUsbMassStorageState) + { + case MS_STATE_CBW: + mUsbIntF2OUTEn(); + mUsbIntF0INDis(); + break; + case MS_STATE_CB_DMA_IN: + if (mUsbEPStallST (IN_EP, DIRECTION_IN)) { + // wait for clear feature, and then enable F0 + } + else + mUsbIntF0INEn(); + break; + case MS_STATE_CB_DMA_OUT: + mUsbIntF2OUTEn(); + break; + case MS_STATE_CSW: + mUsbIntF2OUTDis(); + if (mUsbEPStallST (IN_EP, DIRECTION_IN)) { + // wait for clear feature, and then enable F0 + } + else { + mUsbIntF0INEn(); + } + break; + case MS_STATE_BGD: + mUsbIntF2OUTDis(); + mUsbIntF0INDis(); + break; + default: + //#ifdef USBROM_RTOS_DBG + debug_msg("MSG: Error MS_STATE\r\n"); + //#endif + vUsbUnplug(); + break; + } +} + +void vUsb_F0_In(void) +{ + switch(eUsbMassStorageState) + { + case MS_STATE_CSW: + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP1 IN CSW\r\n"); + //#endif + + if (trigger_done_cb) { + trigger_done_cb = 0; + + if (guiU2MsdcVendorDone_cb != NULL) { + if (guiU2MsdcVendorDone_cb((unsigned int)&tCBW) != 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } + } + } + + usb_DxFifoRdWr((unsigned char *)&tCSW, 13, 0); + + //mUsbFIFODone(FIFO0); + eUsbMassStorageState = MS_STATE_CBW; + if(usbrom_exit == 1) + usbrom_exit = 2; + break; + case MS_STATE_CB_DMA_IN: + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP1 CS DMA IN\r\n"); + //#endif + eUsbMassStorageState = eScsiOut(); + break; + default: + //#ifdef USBROM_RTOS_DBG + debug_msg("MSG: Error FIFO0_IN interrupt.\r\n"); + //#endif + + break; + } + vUsb_BulkIntOnOff(); +} + +void vUsb_F2_Out(unsigned int u32FIFOByteCount) +{ + switch(eUsbMassStorageState) { + case MS_STATE_CBW: + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP2 Out CBW\r\n"); + //#endif + + if (u32FIFOByteCount == 31) { + eUsbMassStorageState = eUsbProessCBW(); + } + else{ + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP out STAL SET\r\n"); + //#endif + + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + } + break; + case MS_STATE_CB_DMA_OUT: + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP2 Out CB DMA Out\r\n"); + //#endif + + eUsbMassStorageState = eScsiOut(); + break; + default: + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: Error FIFO2_OUT interrupt.\r\n"); + //#endif + + break; + } + + vUsb_BulkIntOnOff(); +} + + + + +/////////////////////////////////////////////////////////////////////////////// +// bClear_feature() +// Description: +// 1. Send 2 bytes status to host. +// input: none +// output: TRUE or FALSE (BOOLEAN) +/////////////////////////////////////////////////////////////////////////////// +signed int usb_Clear_feature(void) +{ + unsigned int ep_n; + unsigned int fifo_n; + signed int bdir; + + switch (mCxValue (tusb.u32UsbCmd)) { // FeatureSelector + case 0: // ENDPOINT_HALE + // Clear "Endpoint_Halt", Turn off the "STALL" bit in Endpoint Control Function Register + if(mCxIndex (tusb.u32UsbCmd) == 0x00) + tusb.bUsbEP0HaltSt = FALSE; + else { + ep_n = mCxIndex (tusb.u32UsbCmd) & 0x7F; // which ep will be clear + // over the Max. ep count ? + if (ep_n > FUSB200_MAX_EP) + return -1; + // the direction of this ep + // bdir =0 if OUT + bdir = mCxIndex (tusb.u32UsbCmd) & BIT7;; + // get the relatived FIFO number + if (bdir) + fifo_n = mUsbEPMapRd(ep_n) & 0x0F; + else + fifo_n = mUsbEPMapRd(ep_n) >> 4; + // over the Max. fifo count ? + if (fifo_n >= FUSB200_MAX_FIFO) + return -1; + + // Check the FIFO had been enable ? + if ((mUsbFIFOConfigRd(fifo_n) & BIT5) == 0) + return -1; + // bdir =0 if IN, 1 if OUT + bdir = bdir ? 0: 1; + mUsbEPRsTgSet(ep_n, bdir); // Set Rst_Toggle Bit + mUsbEPRsTgClr(ep_n, bdir); // Clear Rst_Toggle Bit + mUsbEPStallClr(ep_n, bdir); // Clear Stall Bit + vUsb_BulkIntOnOff(); + } + break; + case 1 : // Device Remote Wakeup + // Clear "Device_Remote_Wakeup", Turn off the"RMWKUP" bit in Main Control Register + mUsbRmWkupClr(); + break; + case 2 : // Test Mode + // do not break here + default : + return -1; + } + tusb.eUsbCxAction = ACT_DONE; + return 0; +} + + + +signed int usb_StandardCommand(void) +{ + switch (mCxRequest (tusb.u32UsbCmd)) { // by Standard Request codes + //case 0: // get status + // return (usb_Get_status()); + + case 1: // clear feature + return (usb_Clear_feature()); + + //case 3: // set feature + // return (usb_Set_feature()); + + //case 5: // set address + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Set_address()); + // break; + + //case 6: // get descriptor + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Get_descriptor()); + // break; + + //case 8: // get configuration + // if (!tusb.bUsbEP0HaltSt) + // vGet_configuration(); + // return 0; + + //case 9: // set configuration + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Set_configuration()); + // break; + + //case 10: // get interface + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Get_interface()); + // break; + + // case 11: // set interface + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Set_interface()); + // break; + + case 2: // Reserved for further use + case 4: // Reserved for further use + case 7: // set descriptor, not support + case 12: // synch frame, not support + default: + break; + } + return -1; +} + +/////////////////////////////////////////////////////////////////////////////// +// vUsb_ep0setup() +// Description: +// 1. Read 8-byte setup packet. +// 2. Decode command as Standard, Class, Vendor or NOT support command +// input: none +// output: none +/////////////////////////////////////////////////////////////////////////////// +void vUsb_ep0setup(void) +{ + /* + if(tusb.bUsbChirpFinish == 0) + { + // first ep0 command after usb reset, means we can check usb speed right now. + tusb.bUsbChirpFinish = 1; + + if (ptusbdev->main_ctl & BIT6) { + tusb.bHighSpeed = 1; + //DBG_DUMP("MSG: L%x, high speed mode\r\n", tusb.u8LineCount ++); + } + else { + tusb.bHighSpeed = 0; + //DBG_DUMP("MSG: L%x, full speed mode\r\n", tusb.u8LineCount ++); + } + // Init AP + vUsbMassStorageInit(); + } + */ + + // select dma target fifo no.: + //ptusbdev->dma_fifo = BIT4; + + // Read 8-byte setup packet from FIFO + tusb.u32UsbCmd[0] = ptusbdev->dma_data; + tusb.u32UsbCmd[1] = ptusbdev->dma_data; + + #if 0//def USBROM_RTOS_DBG + DBG_DUMP("MSG: L%x, EP0Cmd: %x %x %x %x %x %x %x %x\r\n", + tusb.u8LineCount ++, (INT8U)(tusb.u32UsbCmd[0] >> 0) + , (INT8U)(tusb.u32UsbCmd[0] >> 8) + , (INT8U)(tusb.u32UsbCmd[0] >> 16) + , (INT8U)(tusb.u32UsbCmd[0] >> 24) + , (INT8U)(tusb.u32UsbCmd[1] >> 0) + , (INT8U)(tusb.u32UsbCmd[1] >> 8) + , (INT8U)(tusb.u32UsbCmd[1] >> 16) + , (INT8U)(tusb.u32UsbCmd[1] >> 24)); + #endif + + // Command Decode + switch (mCxType(tusb.u32UsbCmd)) { + case 0: // standard command + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: Standard command\r\n"); + //#endif + + if (usb_StandardCommand() < 0) + tusb.eUsbCxAction = ACT_STALL; + break; +/* + case 1: // class command + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("MSG: class command\r\n"); + #endif + + if (usb_ClassCommand() < 0) + tusb.eUsbCxAction = ACT_STALL; + break; + + case 2: // vendor command + #ifdef USBROM_RTOS_DBG + DBG_DUMP("MSG: vendor command\r\n"); + #endif +// if (usb_UsbVendorCommand() < 0 + tusb.eUsbCxAction = ACT_STALL; + break; +*/ + default: + // Invalid(bad) command, Return EP0_STALL flag + tusb.eUsbCxAction = ACT_STALL; + break; + } +} + + + + +void vUsbInit(void) +{ + ptusbdev = ((volatile DEV *)(IOADDR_USB_REG_BASE + 0x100)); + + // init variables + tusb.eUsbCxAction = ACT_IDLE; + tusb.bUsbChirpFinish = 0; + + tusb.u16TxRxCounter = 0; + tusb.eUsbCxCommand = CMD_VOID; + tusb.u8UsbConfigValue = 0; + tusb.u8UsbInterfaceValue = 0; + tusb.u8UsbInterfaceAlternateSetting = 0; + tusb.bUsbEP0HaltSt = FALSE; + + // init hardware + //vFUSB200Init(); + tusb.u8LineCount = 1; + + tCSW.u32Signature = CSW_SIGNATE; + eUsbMassStorageState = MS_STATE_CBW; + mUsbIntF2OUTEn (); + mUsbIntF0INDis(); + +} + + + +void vUsbIsr2(void) +{ + INT32U level1; + INT32U level2; + + level1 = ptusbdev->int_grp & ~ ptusbdev->int_mgrp; + + if (0 == level1) + return; + + if (level1 & BIT2) { //Group 2 + + level2 = ptusbdev->int_grp2 & ~ ptusbdev->int_mgrp2; + + if (level2) { + + //debug_msg("MSG: IntSCR2\r\n"); + + if (level2 & BIT0) { + //debug_msg("MSG: BUS RST\r\n"); + } + + if (level2 & BIT1) { + //debug_msg("MSG: BUS SUSPEND\r\n"); + ptusbdev->int_grp2 |= BIT1; + } + + if (level2 & BIT2) { + //debug_msg("MSG: BUS RESUME\r\n"); + ptusbdev->int_grp2 |= BIT2; + } + + if (level2 & BIT5) { + //debug_msg("MSG: TX0B\r\n"); + + ptusbdev->tx0byte |= 0; + ptusbdev->int_grp2 |= BIT5; + } + + if (level2 & BIT6) { + //debug_msg("MSG: RX0B\r\n"); + ptusbdev->rx0byte |= 0; + ptusbdev->int_grp2 |= BIT6; + } + + } + } + + + if (level1 & BIT0) { //Group 0 + level2 = ptusbdev->int_grp0 & ~ ptusbdev->int_mgrp0; + if (level2) { + //debug_msg("MSG: IntSCR0\r\n"); + + if (level2 & BIT0) { + //debug_msg("MSG: USB ep0 Setup\r\n"); + vUsb_ep0setup(); + } + else if (level2 & BIT3) { + //debug_msg("MSG: USB ep0 end\r\n"); + //vUsb_ep0end(); + } + if (level2 & BIT1) { + //debug_msg("MSG: USB ep0 TX\r\n"); + //vUsb_ep0tx(); + } + if (level2 & BIT2) { + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: USB ep0 RX\r\n"); + //#endif + //vUsb_ep0rx(); + } + if (level2 & BIT4) { + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: USB ep0 fail\r\n"); + //#endif + // stall cx: mUsbEP0StallSet(); + //ptusbdev->cx_cf |= BIT2; + } + if (level2 & BIT5) { + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: cmd abort\r\n"); + //#endif + ptusbdev->int_grp0 |= BIT5; + } + } + + + if (tusb.eUsbCxAction == ACT_STALL) { + ptusbdev->cx_cf |= BIT2; + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: EP0 STALL\r\n"); + //#endif + } + else if (tusb.eUsbCxAction == ACT_DONE) { + ptusbdev->cx_cf |= BIT0; + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: EP0 DONE\r\n"); + //#endif + } + // Clear Action + tusb.eUsbCxAction = ACT_IDLE; + + + } + + if (level1 & BIT1) { //Group Byte 1 + level2 = ptusbdev->int_grp1 & ~ ptusbdev->int_mgrp1; + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: IntSCR1\r\n"); + //#endif + + if (level2 & (BIT5 | BIT4)) { // F2 out (full or short) + vUsb_F2_Out(ptusbdev->fifo_bc[2]); + } + + if (level2 & BIT16) // F0 in + vUsb_F0_In(); + } +} + + + +static INT32U calc_sum_v2(INT32U dat0, INT32U dat1, INT32U dat2, INT32U dat3) +{ + INT32U sum=0; + + sum = (dat0&0xFFFF)+((dat0>>16))+(dat1&0xFFFF)+((dat1>>16)) + + (dat2&0xFFFF)+((dat2>>16))+(dat3&0xFFFF)+((dat3>>16)) + 28; + + //DBG_DUMP("SUM = 0x%08X\r\n",sum); + return sum&0xFFFF; +} + +INT32S my_SCSICmd(CBW * ptcbw) +{ + INT32U temp1, temp2; + INT32U CDB[4]; + + CDB[0] = ((ptcbw->CB0_cblen_lun_flag >> 24) & 0xFF) + ((ptcbw->CB1_CB15[0]&0xFFFFFF)<<8); + CDB[1] = ((ptcbw->CB1_CB15[0] >> 24) & 0xFF) + ((ptcbw->CB1_CB15[1]&0xFFFFFF)<<8); + CDB[2] = ((ptcbw->CB1_CB15[1] >> 24) & 0xFF) + ((ptcbw->CB1_CB15[2]&0xFFFFFF)<<8); + CDB[3] = ((ptcbw->CB1_CB15[2] >> 24) & 0xFF) + ((ptcbw->CB1_CB15[3]&0xFFFFFF)<<8); + + // Parse SCSI command + if (!(((CDB[0]&0xFF) == SCSI_OP_SET0)||((CDB[0]&0xFF) == SCSI_OP_SET1)||((CDB[0]&0xFF) == SCSI_OP_SET2))) + return -1; + + // check sum + if(calc_sum_v2(CDB[0],CDB[1],CDB[2],CDB[3])) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + u32Usb_buffer[0] = 0; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("CHKSUM FAILED\r\n"); + #endif + return -1; + } + + tCSW.u8Status = CSW_STATUS_CMD_PASS; + + switch (((CDB[0] >> 8) &0xFF)) { + + case SCSIOP_OUT_OPEN_DEVICE: { + nvtdev_opened = 1; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_OUT_OPEN_DEVICE\r\n"); + #endif + } + break; + + case SCSIOP_IN_WAIT_DONE: { + usbrom_exit = 1; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_IN_WAIT_DONE\r\n"); + #endif + } + break; + + + case SCSIOP_IN_IS_NVT: { + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + tSCSIDeviceResp.u16DataResidue = 4; + + tCSW.u8Status = CSW_STATUS_CMD_PASS; + u32Usb_buffer[0] = 0x81200000; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_IN_IS_NVT\r\n"); + #endif + } + break; + + case SCSIOP_OUT_ADDR_WRITE: { + + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + // address + temp1 = ((CDB[0]>>16)&0xFFFF)+((CDB[1]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[2]); + // data + temp2 = ((CDB[1]>>16)&0xFFFF)+((CDB[2]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[6]); + + *(INT32U *)temp1 = temp2; + __asm__ __volatile__("dsb\n\t"); + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_OUT_ADDR_WRITE 0x%08X 0x%08X\r\n", temp1, temp2); + #endif + } + } + break; + + case SCSIOP_IN_ADDR_READ: { + + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + // address + temp1 = ((CDB[0]>>16)&0xFFFF)+((CDB[1]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[2]); + + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + tSCSIDeviceResp.u16DataResidue = 8; + u32Usb_buffer[0] = temp1; + u32Usb_buffer[1] = *((INT32U *)temp1); + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_IN_ADDR_READ 0x%08X 0x%08X\r\n", temp1, u32Usb_buffer[1]); + #endif + } + } + break; +#if 0 //only rom code support + case SCSIOP_OUT_WRLOADER: { + + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + // address + temp1 = ((CDB[0]>>16)&0xFFFF)+((CDB[1]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[2]); + + tSCSIDeviceResp.u32IOAddr = temp1; + tSCSIDeviceResp.u8Flags = CBW_FLAG_OUT; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_FSM_SS; + tSCSIDeviceResp.u16DataResidue = ptcbw->u32DataTransferLength; + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_OUT_WRLOADER 0x%08X 0x%08X\r\n", temp1, tSCSIDeviceResp.u16DataResidue); + #endif + + } + } + break; +#endif + default: { + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + int ret = -1; + unsigned int OutDataBuf=0, insize=0; + + if (guiU2MsdcCheck_cb != NULL) { + ret = guiU2MsdcCheck_cb((unsigned int)ptcbw, (unsigned int *) &OutDataBuf, (unsigned int *)&insize); + } else { + ret = -1; + } + + if(ret == 0) { + + if (ptcbw->CB0_cblen_lun_flag & CBW_FLAG_IN) { + tSCSIDeviceResp.u32IOAddr = OutDataBuf; + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_FSM_SS; + tSCSIDeviceResp.u16DataResidue = insize; + + } else { + tSCSIDeviceResp.u32IOAddr = OutDataBuf; + tSCSIDeviceResp.u8Flags = CBW_FLAG_OUT; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_FSM_SS; + tSCSIDeviceResp.u16DataResidue = ptcbw->u32DataTransferLength; + } + + trigger_done_cb = 1; + } else { + return ret; + } + } + } + break; + + } + + return 0; + +} + + + +void fLib_USB_Update_FW(void) +{ + debug_msg("USBFW UPDATE\r\n"); + + vUsbInit(); + + while (1) { + + vUsbIsr2(); + + if(usbrom_exit > 1) { + mdelay(300); //make sure that pc recevie scsi status + vUsbUnplug(); + mdelay(300); //make sure that pc recevie usb plug-out single + break; + } + + } + + usbrom_exit = 0; + +} + + + + + + + + + + + + + diff --git a/board/novatek/na51068/loader/Project/Model/Src/USB/usb_update.h b/board/novatek/na51068/loader/Project/Model/Src/USB/usb_update.h new file mode 100755 index 000000000000..acc7d94669cf --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/Src/USB/usb_update.h @@ -0,0 +1,297 @@ + +#ifndef __USB_UPDATE_H +#define __USB_UPDATE_H +#include "scsi_op.h" + + +typedef int (*MSDC_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); ///< Callback for verify the Vendor Command is supported or not +typedef int (*MSDC_VenDone_CB)(unsigned int pCmdBuf); ///< Callback for verify the Vendor Command is supported or not + + +// KEY_ILLEGAL_REQUEST: Additional key +#define ADDKEY_INVALID_CMD_OP_CODE 0x20 +#define ADDKEY_INVALID_FIELD_IN_CMD 0x24 + +#define CBW_FLAG_IN 0x80 +#define CBW_FLAG_OUT 0x00 + +// Endpoint or FIFO direction define +#define DIRECTION_IN 0 ///1 +#define DIRECTION_OUT 1 ///0 + +#define EP0 0x00 +#define EP1 0x01 +#define EP2 0x02 +#define EP3 0x03 + +// FIFO number define +#define FIFO0 0x0 +#define FIFO1 0x1 +#define FIFO2 0x2 +#define FIFO3 0x3 +#define FIFO4 0x4 +#define FIFO5 0x5 +#define FIFO6 0x6 +#define FIFO7 0x7 +#define FIFO8 0x8 +#define FIFO9 0x9 + +#define OUT_EP EP2 +#define IN_EP EP1 +#define OUT_FIFO FIFO2 +#define IN_FIFO FIFO0 + +typedef enum { + MS13Case_1 = 0, + MS13Case_2_3, + MS13Case_4, + MS13Case_5, + MS13Case_6, + MS13Case_7_8, + MS13Case_9, + MS13Case_10_13, + MS13Case_11, + MS13Case_12 +} MassStorage13Case; + +#define CBW_SIGNATE 0x43425355 +#define CSW_SIGNATE 0x53425355 +#define CSW_STATUS_CMD_PASS 0x00 +#define CSW_STATUS_CMD_FAIL 0x01 +#define CSW_STATUS_PHASE_ERROR 0x02 + +// Request Sense data format +#define SENSE_OFFSET_KEY 0x02 +#define SENSE_OFFSET_ADD 0x0C +#define SENSE_OFFSET_ADD_QUALIFIER 0x0D + +// KEY_NO_SENSE: Additional key +#define ADDKEY_NO_ADDITIONAL 0x00 + +// all response data length +#define DATA_LENGTH_INQUIRY 36 +#define DATA_LENGTH_REQUEST_SENSE 18 +#define DATA_LENGTH_MODE_SENSE 8 + +// SCSI command operation code +#define SCSI_OP_TEST_UNIT_READY 0x00 +#define SCSI_OP_REQUEST_SENSE 0x03 +#define SCSI_OP_INQUIRY 0x12 +#define SCSI_OP_MODE_SELECT 0x15 +#define SCSI_OP_MODE_SENSE 0x1A +#define SCSI_OP_MEDIUM_REMOVAL 0x1E +#define SCSI_OP_READ_FORMAT_CAPACITY 0x23 // unsupported +#define SCSI_OP_READ_CAPACITY 0x25 +#define SCSI_OP_READ_10 0x28 +#define SCSI_OP_WRITE_10 0x2A +#define SCSI_OP_VERIFY 0x2F + +#define CARD_INDEX_SRAM 7 +#define CARD_INDEX_FSM_SS 3 +#define CARD_TYPE_MAX_REPORT 1 + +// KEY_NOT_READY: Additional key +#define ADDKEY_LOGICAL_UNIT_NOT_READY 0x04 +#define ADDKEY_LOGICAL_UNIT_NOT_SUPPORT 0x25 +#define ADDKEY_MEDIUM_NOT_PRESENT 0x3A + +// Sense key +#define KEY_NO_SENSE 0x00 +#define KEY_RECOVERED_ERROR 0x01 +#define KEY_NOT_READY 0x02 +#define KEY_MEDIUM_ERROR 0x03 +#define KEY_HARDWARE_ERROR 0x04 +#define KEY_ILLEGAL_REQUEST 0x05 +#define KEY_UNIT_ATTENTION 0x06 +#define KEY_DATA_PROTECT 0x07 +#define KEY_BLANK_CHECK 0x08 +#define KEY_VENDOR_SPECIFIC 0x09 +#define KEY_COPY_ABORTED 0x0A +#define KEY_ABORTED_CMD 0x0B +#define KEY_OBSOLETE 0x0C +#define KEY_VOLUMN_OVERFLOW 0x0D +#define KEY_MISCOMPARE 0x0E +#define KEY_RESERVED 0x0F + +typedef struct // SCSI device response +{ + unsigned int u8MemIndex; // current access memory type + unsigned int u8Flags; // In or Out + unsigned int u32IOAddr; // block addr in Card controller + unsigned int u16DataResidue; // residue (block count for card content, or byte count for information) + unsigned int u16TfSzCurrent; // current transfer length (block count for card content, or byte count for information) +} SCSIDeviceResp; + +typedef struct SCSI_Sense_Data +{ + unsigned int u8Key; + unsigned int u8KeyAdd; +} SCSISense; + +typedef enum { + MS_STATE_IDLE = 0, + MS_STATE_CBW = 1, + MS_STATE_CB_DMA_IN = 2, + MS_STATE_CB_DMA_OUT = 3, + MS_STATE_CSW = 4, + MS_STATE_STALL = 5, + MS_STATE_BGD = 6 +} MassStorageState; + + +typedef struct CommandBlockWrapper +{ + unsigned int u32Signature; + unsigned int u32Tag; + unsigned int u32DataTransferLength; + unsigned int CB0_cblen_lun_flag; + unsigned int CB1_CB15[4]; + //unsigned char u8Flags; + //unsigned char u8LUN; + //unsigned char u8CBLength; + //unsigned char u8CB[16]; +} CBW; + +typedef struct CommandStatusWrapper +{ + unsigned int u32Signature; + unsigned int u32Tag; + unsigned int u32DataResidue; + unsigned int u8Status; +} CSW; + +// Host Controller (HC) +typedef struct { + INT32U cap; // 0x00: capability + INT32U ports; // 0x04: Structural Parameter + INT32U capp; // 0x08: capability Parameter + INT32U reserved1; // 0X0c + INT32U cmd; // 0x10: USB command + INT32U status; // 0X14: status + INT32U int_en; // 0X18: interrupt enable + INT32U fm_idx; // 0X1c: frame Index + INT32U reserved2; // 0x20 + INT32U periodic; // 0X24: periodic Frame List Base Address. must 4KB align. + INT32U asynch; // 0X28: Current Asynchronous List Address, must 32B align. + INT32U reserved3; // 0X2c + INT32U port; // 0x30: port status and Control + INT32U reserved4[3]; // 0X34 ~ 0X3c + INT32U misc; // 0x40 + INT32U reserved5[15]; // 0x44 ~ 0x7C +} HC; + +// OTG Controller (OTG) +typedef struct { + INT32U ctl_st; // 0x80: control/status + INT32U int_st; // 0x84: interrupt status + INT32U int_en; // 0x88: interrupt enable + INT32U reserved[13]; // 0x8C ~ 0xBC +} OTG; + +// Global Controller (GL) +typedef struct { + INT32U int_st; // 0xC0: interrupt status + INT32U interrupt; // 0xC4: interrupt mask + INT32U reserved[14]; // 0xC8 ~ 0xFC +} GL; + +// Device Controller (DEV) +typedef struct { + INT32U main_ctl; // 0x100: device main control + INT32U dev_adr; // 0x104: device address + INT32U tst_ep; // 0x108: device test + INT32U frm_no; // 0x10C: device SOF [13: 11] SOF micro frame number, [10: 0] SOF frame number + INT32U sof_tmsk; // 0x110: device SOF mask timer [15: 0] SOF mask timer + INT32U phy_tms; // 0x114: PHY test mode selector + INT32U vnd_ctl; // 0x118: vendor specific IO control + INT32U cx_cs; // 0x11C: CX configuration and status + INT32U cx_cf; // 0x120: CX configuration and FIFO empty status + INT32U idle_cnt; // 0x124: Device idel counter + INT32U cx_dataport; // 0x128: device cx data register + INT32U reserved1[1]; // 0x128 ~ 0x12C + INT32U int_mgrp; // 0x130: mask of interrupt group + INT32U int_mgrp0; // 0x134: mask of interrupt source group 0 + INT32U int_mgrp1; // 0x138: mask of interrupt source group 1 + INT32U int_mgrp2; // 0x13C: mask of interrupt source group 2 + INT32U int_grp; // 0x140: interrupt group + INT32U int_grp0; // 0x144: interrupt group 0 + INT32U int_grp1; // 0x148: interrupt group 1 + INT32U int_grp2; // 0x14C: interrupt group 2 + INT32U rx0byte; // 0x150: receive zero-length data packet + INT32U tx0byte; // 0x154: rtransfer zero-length data packet + INT32U iso_seq_err; // 0x158: iso. sequential error/abort + INT32U reserved2; // 0x15C + INT32U ep_xpsz[2][8]; // 0x160: IN endpoint x MaxPacketSize Reg + // 0x170: IN endpoint x MaxPacketSize Reg + // 0x180: OUT endpoint x MaxPacketSize Reg + // 0x190: OUT endpoint x MaxPacketSize Reg + INT8U ep_map[8]; // 0x1A0: endpoint 1 ~ 8 map Reg + INT8U fifo_map[4]; // 0x1A8: FIFO 0 ~ 3 map Reg + INT8U fifo_cfg[4]; // 0x1AC: FIFO 0 ~ 3 configuration + INT32U fifo_bc[4]; // 0x1B0: FIFO x instruction and byte count + INT32U dma_fifo; // 0x1C0: dma target FIFO number + INT32U reserved3; // 0x1C4 + INT32U dma_ctl; // 0x1C8: DMA controller parameter setting 1 + INT32U dma_addr; // 0x1CC: DMA controller parameter setting 2, address + INT32U dma_data; // 0x1D0: DMA controller parameter setting 3, Cx data +} DEV; + +// OTG Controller +typedef struct { + HC hc; // 0x00 ~ 0x7F + OTG otg; // 0x80 ~ 0xBF + GL gl; // 0xC0 ~ 0xFF + DEV dev; // 0x100 ~ 0x1FF +} OTG200; + + + +typedef enum +{ + ACT_IDLE, + ACT_DONE, + ACT_STALL, + + ACT_DUMMY = 0x80000000 +} Action; + +typedef enum +{ + CMD_VOID, // No command + CMD_GET_DESCRIPTOR, // Get_Descriptor command + CMD_SET_DESCRIPTOR, // Set_Descriptor command + + CommandType_dummy = 0x80000000 +} CommandType; + +typedef struct USB_s +{ + // end pointer 0 information + unsigned int u32UsbCmd[8/4]; + unsigned int bUsbChirpFinish; + Action eUsbCxAction; + unsigned int u16TxRxCounter; + unsigned char * pu8Descriptor; + unsigned int u8UsbConfigValue; + unsigned int u8UsbInterfaceValue; + unsigned int u8UsbInterfaceAlternateSetting; + unsigned int bUsbEP0HaltSt; + unsigned int bHighSpeed; // high speed + CommandType eUsbCxCommand; + // for display + unsigned int u8LineCount; +} USB_st; + + + + + + + +#endif /* __USB_OTG_H */ + + + + + + diff --git a/board/novatek/na51068/loader/Project/Model/Src/prj_main.c b/board/novatek/na51068/loader/Project/Model/Src/prj_main.c new file mode 100755 index 000000000000..3602ea52a1d3 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/Src/prj_main.c @@ -0,0 +1,190 @@ +/* + Project layer Main control function + + This file is implement by user mode + + @file prj_main.c + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ +/* +#include "fat.h" +#include "rtc.h" +#include "timer.h" +#include "StorageDef.h" +#include "global.h" +#include "Clock.h" +#include "string.h" +*/ +#include "board.h" +#include "debug.h" +#include "mmc_api.h" +#include "fuart.h" +#include "prj_main.h" + +extern UINT32 LoaderInternalInfo[]; + +#if (DEBUG_MSG == ENABLE) +//weak function mechanism for debug msg output +extern void config_dma_log(void); +void config_dma_log(void) {} +#endif + +#if (SPECIAL_KEY_UPDATE == 1) +/** + Check special key1(s) is(are) pressed. + + Check special key1(s) is(are) pressed or not. + + @return Key pressed status + - @b TRUE: Special key(s) is(are) pressed + - @b FALSE: Otherwise +*/ +static BOOL prj_isSpecialKeyPressed(void) +{ + // Detect key example, must press shutter2 and playback mode keys + // OUT_0: DGPIO 0 + // OUT_1: DGPIO 14 + // OUT_2: DGPIO 2 + // OUT_3: DGPIO 3 + // OUT_4: DGPIO 4 + // IN_0 : DGPIO 5 + // IN_1 : DGPIO 6 + // IN_2 : DGPIO 7 + // IN_3 : DGPIO 8 + // KEY_IN_0 KEY_IN_1 KEY_IN_2 KEY_IN_3 + // KEY_OUT_0 MENU SET PLAYBACK DISPLAY + // KEY_OUT_1 WIDE LEFT MOVIE + // KEY_OUT_2 TELE DOWN TRASH + // KEY_OUT_3 SHUTTER2 RIGHT CAPTURE + // KEY_OUT_4 SHUTTER1 UP + // Add the necessary code.. + return TRUE; +} +#endif + +#if (CHECK_CARD_EXIST == 1) +// MC16 default is config as input and pull up +static BOOL prj_checkCardExist(void) +{ +#if (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + return TRUE; // force ethernet probe DHCP server +#else + return (gpio_getPin(DGPIO_CARD_DETECT) == 0 ? TRUE : FALSE); +#endif +} +#endif + +#if (CHECK_RECOVERY_TRIGGER == 1) +static BOOL prj_isRecoveryTriggered(void) +{ + #if 1 + return FALSE; + #else + //just a sample for using P_GPIO_0 high active to trigger recovery flow + return (gpio_getPin(P_GPIO_0) == 1 ? TRUE : FALSE); + #endif +} +#endif + +#if 0 +static BOOL bl_spiIdentify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + // Sample to support SST25VF032 + if ((uiMfgID == 0xBF) && + (uiCapacityID == 0x4A)) + { + pIdentify->bDualRead = FALSE; + pIdentify->bSupportAAI = TRUE; + pIdentify->bSupportEWSR = TRUE; + pIdentify->uiFlashSize = 4*1024*1024; + return TRUE; + } + + return FALSE; +} + +static void bl_flashLED(void) +{ + // use GPIO to control LED +} +#endif + +// main entry of project layer code +void prj_main(void) +{ + PSTORAGE_OBJ strg_obj = NULL; + PSTORAGE_OBJ strg2_obj = NULL; + loader_setVersion(_LDR_VER_); + + // Print project layer info + + if ((LoaderInternalInfo[6] & 0x100000) == 0x100000) { + debug_msg(_LOADER_VERSION_STR2_); + } else { + debug_msg(_LOADER_VERSION_STR_); + } + + // Setup loader/fw file names + loader_setUpdateFwName(_UPDATE_FW_NAME_); + loader_setUpdateLdrName(_UPDATE_LOADER_NAME_); + loader_setRunFwName(_RUN_FW_NAME_); + // Setup FW_MAC_CODE_SIZE (i.e. FWResvSize in RTOS) + +#if defined(_STORAGEINT_NandSpi_) + strg_obj = nand_get_storage_object(); + loader_setStorageIntType(STORAGEINT_SPI_NAND, strg_obj); + strg2_obj = nor_get_storage_object(); + strg2_obj->flash_setConfig(FLASH_CFG_ID_CS_SELECT, 1); +#elif defined(_STORAGEINT_SpiFlash_) + strg_obj = nor_get_storage_object(); + loader_setStorageIntType(STORAGEINT_SPI_NOR, strg_obj); + strg2_obj = nand_get_storage_object(); + strg2_obj->flash_setConfig(FLASH_CFG_ID_CS_SELECT, 1); +#else + #error "Internal storage not configured !!!"; +#endif + + +#if 0 +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + +#if 0 + // Sample to hook spi flash extending function + flash_installIdentifyCB(bl_spiIdentify); +#endif + +#if 0 + // Sample to hook flash programming LED callback + flash_installAccessCB(bl_flashLED); +#endif + +#if 0 + // Sample to enable eMMC 8 bits boot + // *Note*: MUST ensure your PCB has BS[7] = HIGH + if (INREG32(0xF0010000) & (1<<7)) { + // If bootstrap pin[7] is pulled high + // enable eMMC 8 bit + debug_msg("Enable eMMC 8 bit mode\r\n"); + flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, TRUE); + } +#endif + +#if (SPECIAL_KEY_UPDATE == ENABLE) + loader_installSpecialKeyCB(prj_isSpecialKeyPressed); +#endif + +#if (CHECK_CARD_EXIST == ENABLE) + loader_installCardDetectCB(prj_checkCardExist); +#endif + +#if (CHECK_RECOVERY_TRIGGER == ENABLE) + loader_setRecoveryPartitionID(2); + loader_setRecoveryFwName(_RECOVERY_FW_NAME_); + loader_installRecoveryTriggerCB(prj_isRecoveryTriggered); +#endif +#endif +} + diff --git a/board/novatek/na51068/loader/Project/Model/Src/prj_main.h b/board/novatek/na51068/loader/Project/Model/Src/prj_main.h new file mode 100755 index 000000000000..63a99b133f55 --- /dev/null +++ b/board/novatek/na51068/loader/Project/Model/Src/prj_main.h @@ -0,0 +1,72 @@ +/** + Loader project header file + + Loader project header file + + @file prj_main.h + @note Nothing +*/ + +#ifndef _PRJ_MAIN_H +#define _PRJ_MAIN_H + +#include "constant.h" +#include "loader.h" +//#include "GPIO.h" + +// Define SPECIAL_KEY_UPDATE == ENABLE will require user to press special key +// to update firmware +#ifndef SPECIAL_KEY_UPDATE +#define SPECIAL_KEY_UPDATE 0 +#endif + +#ifndef SPI_PINMUX_NORMAL +#define SPI_PINMUX_NORMAL (0) +#endif + +#ifndef SPI_PINMUX_4BITS +#define SPI_PINMUX_4BITS (1) +#endif + +#ifndef SPI_PINMUX_SETTING +#define SPI_PINMUX_SETTING (SPI_PINMUX_4BITS) +#endif + +// Define MACROs for external storage +// +#ifndef STORAGE_EXT_UNKOWN +#define STORAGE_EXT_UNKOWN (0) +#endif + +#ifndef STORAGE_EXT_SDIO1 +#define STORAGE_EXT_SDIO1 (1) +#endif + +#ifndef STORAGE_EXT_UART +#define STORAGE_EXT_UART (2) +#endif + +#ifndef STORAGE_EXT_USB +#define STORAGE_EXT_USB (3) +#endif + +#ifndef STORAGE_EXT_ETH +#define STORAGE_EXT_ETH (4) +#endif + +#ifndef STORAGE_EXT_TYPE +#define STORAGE_EXT_TYPE (STORAGE_EXT_SDIO1) +#endif + + +// Card detect GPIO offset +#define DGPIO_CARD_DETECT (0)// | GPIO_IS_DGPIO) + +#define CHECK_CARD_EXIST (0) + +//check recovery trigger condition +#define CHECK_RECOVERY_TRIGGER (0) + +#define DEBUG_MSG DISABLE + +#endif diff --git a/board/novatek/na51068/loader/Tools/Bin/Configram321 b/board/novatek/na51068/loader/Tools/Bin/Configram321 new file mode 100755 index 000000000000..2c0133773d49 Binary files /dev/null and b/board/novatek/na51068/loader/Tools/Bin/Configram321 differ diff --git a/board/novatek/na51068/loader/Tools/Bin/bfc b/board/novatek/na51068/loader/Tools/Bin/bfc new file mode 100755 index 000000000000..03b06d7d9ab1 Binary files /dev/null and b/board/novatek/na51068/loader/Tools/Bin/bfc differ diff --git a/board/novatek/na51068/loader/Tools/Bin/encrypt_boot b/board/novatek/na51068/loader/Tools/Bin/encrypt_boot new file mode 100755 index 000000000000..8fbf8de688b7 Binary files /dev/null and b/board/novatek/na51068/loader/Tools/Bin/encrypt_boot differ diff --git a/board/novatek/na51068/loader/Tools/Bin/encrypt_boot_dump b/board/novatek/na51068/loader/Tools/Bin/encrypt_boot_dump new file mode 100755 index 000000000000..1a44cedcf2ce Binary files /dev/null and b/board/novatek/na51068/loader/Tools/Bin/encrypt_boot_dump differ diff --git a/board/novatek/na51068/loader/Tools/Bin/nvt-ld-op b/board/novatek/na51068/loader/Tools/Bin/nvt-ld-op new file mode 100755 index 000000000000..99cf292f35b3 Binary files /dev/null and b/board/novatek/na51068/loader/Tools/Bin/nvt-ld-op differ diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_1024_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_1024_0_1066_UBT.ini new file mode 100755 index 000000000000..ec42b615bf5b --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_1024_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae1c +mau_reg_010 = 0x4550edd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x04 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x3c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_1024_0_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_1024_0_800_UBT.ini new file mode 100755 index 000000000000..eecfa80c6235 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_1024_0_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210305 +pllRatio = 0x00215556 +mau_reg_008 = 0x14c2ff04 +mau_reg_00C = 0x1cbc8b16 +mau_reg_010 = 0x4556b16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x13 +reg_013 = 0x03 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x2d +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_1024_0_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_1024_0_933_UBT.ini new file mode 100755 index 000000000000..72b535a27a66 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_1024_0_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d1a +mau_reg_010 = 0x4557cfae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x38 +reg_162 = 0x40 +reg_163 = 0x38 +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x03 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x35 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_2048_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_2048_0_1066_UBT.ini new file mode 100755 index 000000000000..c2c095d24e26 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_2048_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae5c +mau_reg_010 = 0x455057d0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0xc4 +reg_013 = 0x05 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_2048_0_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_2048_0_800_UBT.ini new file mode 100755 index 000000000000..d88f85cc9751 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_2048_0_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x14c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556016c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0s +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x53 +reg_013 = 0x04 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_2048_0_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_2048_0_933_UBT.ini new file mode 100755 index 000000000000..f9361d54f81c --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_2048_0_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x38 +reg_162 = 0x40 +reg_163 = 0x38 +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8f +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x4c +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_1066_FB.ini new file mode 100755 index 000000000000..a5e536ad88ab --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xdd +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x11 +reg_0C8 = 0xdd +reg_0C9 = 0xdd +reg_161 = 0x3c +reg_162 = 0x40 +reg_163 = 0x3c +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x32 +reg_0D3 = 0x32 +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_1066_UBT.ini new file mode 100755 index 000000000000..04a4611b34de --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x80201201 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_800_UBT.ini new file mode 100755 index 000000000000..e443f889f2b5 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x14c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556a16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_933_UBT.ini new file mode 100755 index 000000000000..7fca3fbce153 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_4096_0_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x38 +reg_162 = 0x40 +reg_163 = 0x38 +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x7b +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_8192_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_8192_0_1066_UBT.ini new file mode 100755 index 000000000000..f5c610a77b7f --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR3_16_8192_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x30200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xef +reg_0C5 = 0xef +reg_0C6 = 0x23 +reg_0C7 = 0x23 +reg_0C8 = 0xef +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xf1 +reg_0D3 = 0xf1 +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR4_16_4096_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR4_16_4096_0_1200_FB.ini new file mode 100755 index 000000000000..8a5fdaf77f3b --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR4_16_4096_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x07220584 +mau_reg_010 = 0x45517052 +mau_reg_01C = 0x0131272c +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453e15 +mau_reg_32C = 0x03fc0000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x974 +mau_reg_404 = 0x1 +mau_reg_408 = 0x228 +mau_reg_40C = 0x0 +mau_reg_410 = 0x1800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x24 +reg_117 = 0x24 +reg_113 = 0x24 +reg_0F4 = 0x24 +reg_101 = 0x24 +reg_145 = 0x24 +reg_0EF = 0x24 +reg_0F5 = 0x24 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xdd +reg_0C2 = 0x25 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x11 +reg_0C8 = 0xdd +reg_0C9 = 0xdd +reg_161 = 0x3f +reg_162 = 0x3f +reg_163 = 0x3f +reg_164 = 0x3f +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x66 +reg_000 = 0x88 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x96 +reg_011 = 0x00 +reg_012 = 0x10 +reg_013 = 0x05 +reg_015 = 0x74 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x18 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x05 +reg_004 = 0x05 +reg_005 = 0x83 +reg_006 = 0x06 +reg_007 = 0x02 +reg_009 = 0x10 +reg_00A = 0x0d +reg_00B = 0x12 +reg_020 = 0x24 +reg_021 = 0x09 +reg_022 = 0x4e +reg_023 = 0x03 +reg_027 = 0x00 +reg_028 = 0x01 +reg_02D = 0x2f +reg_28E = 0x95 +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR4_16_4096_0_1200_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR4_16_4096_0_1200_UBT.ini new file mode 100755 index 000000000000..cd8f691c2957 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR4_16_4096_0_1200_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c482 +mau_reg_010 = 0x45517032 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xbb +reg_0C6 = 0xef +reg_0C7 = 0xef +reg_0C8 = 0xab +reg_0C9 = 0xab +reg_161 = 0x28 +reg_162 = 0x30 +reg_163 = 0x28 +reg_164 = 0x30 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0x20 +reg_013 = 0x05 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x4f +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x10 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR4_16_8192_0_1200_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR4_16_8192_0_1200_UBT.ini new file mode 100755 index 000000000000..c5c7e5b96bfd --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/321/51068A_DDR4_16_8192_0_1200_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c4c2 +mau_reg_010 = 0x45514832 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xa800d8 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000d8 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0xd20006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xbb +reg_0C6 = 0xef +reg_0C7 = 0xef +reg_0C8 = 0xab +reg_0C9 = 0xab +reg_161 = 0x28 +reg_162 = 0x30 +reg_163 = 0x28 +reg_164 = 0x30 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0xd0 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x6a +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x10 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_2048_0_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_2048_0_1066_FB.ini new file mode 100755 index 000000000000..8d925251edf3 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_2048_0_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x30210225 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae5c +mau_reg_010 = 0x455057d0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0xc4 +reg_013 = 0x05 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_2048_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_2048_0_1200_FB.ini new file mode 100755 index 000000000000..debc21d517cc --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_2048_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x00320000 +mau_reg_008 = 0x15247f04 +mau_reg_00C = 0x0900c040 +mau_reg_010 = 0x45518012 +mau_reg_01C = 0x0131572a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x08443590 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x238 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x11 +reg_2BC = 0x11 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0xe1 +reg_011 = 0x93 +reg_012 = 0x74 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x38 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x09 +reg_004 = 0x09 +reg_005 = 0x07 +reg_006 = 0x10 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0a +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x61 +reg_023 = 0x06 +reg_027 = 0x81 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_2048_0_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_2048_0_933_FB.ini new file mode 100755 index 000000000000..eb707c195e9f --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_2048_0_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x4C +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_1066_FB.ini new file mode 100755 index 000000000000..411baa436c0d --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_1066_UBT.ini new file mode 100755 index 000000000000..43b201ecd518 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x34 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_1200_FB.ini new file mode 100755 index 000000000000..82380371e5ed --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x00320000 +mau_reg_008 = 0x15247f04 +mau_reg_00C = 0x0900c080 +mau_reg_010 = 0x45517012 +mau_reg_01C = 0x0131572a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x08443590 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x238 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x11 +reg_2BC = 0x11 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0xe1 +reg_011 = 0x93 +reg_012 = 0x34 +reg_013 = 0x0a +reg_015 = 0x44 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x38 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x09 +reg_004 = 0x09 +reg_005 = 0x07 +reg_006 = 0x10 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0a +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x9d +reg_023 = 0x06 +reg_027 = 0x81 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_933_FB.ini new file mode 100755 index 000000000000..6d3ebc28c6c1 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_16_4096_0_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0xF3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x7B +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_1066_FB.ini new file mode 100755 index 000000000000..65de29139518 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20201125 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae5c +mau_reg_010 = 0x455057d0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0xc4 +reg_013 = 0x05 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_800_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_800_FB.ini new file mode 100755 index 000000000000..15f4f73661ff --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_800_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x10210513 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556016c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x53 +reg_013 = 0x04 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_800_UBT.ini new file mode 100755 index 000000000000..ed466edbd74c --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556016c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x53 +reg_013 = 0x04 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_933_FB.ini new file mode 100755 index 000000000000..9e0da5af5eec --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x4C +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_933_UBT.ini new file mode 100755 index 000000000000..91fa3e5f20e0 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_2048_2048_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x4C +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_2048_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_2048_1066_FB.ini new file mode 100755 index 000000000000..9c72ae17bd37 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_2048_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20201104 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef84 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd1000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_2048_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_2048_1066_UBT.ini new file mode 100755 index 000000000000..1d7b64286260 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_2048_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20201021 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef84 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd1000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x34 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_1066_FB.ini new file mode 100755 index 000000000000..84d94552ac81 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_1066_UBT.ini new file mode 100755 index 000000000000..deb12bc12527 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x34 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_800_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_800_FB.ini new file mode 100755 index 000000000000..e29cc5a28688 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_800_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x10210513 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556a16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_800_UBT.ini new file mode 100755 index 000000000000..18657b7666b1 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556a16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_933_FB.ini new file mode 100755 index 000000000000..0c993d16bc40 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0xF3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x7B +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_933_UBT.ini new file mode 100755 index 000000000000..41e8d5465c76 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_4096_4096_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0xF3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x7B +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_8192_8192_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_8192_8192_1066_FB.ini new file mode 100755 index 000000000000..a1a6c9059c57 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR3_32_8192_8192_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x40210422 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x0f +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xff +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x54 +reg_0C3 = 0x06 +reg_0C4 = 0xdb +reg_0C5 = 0x1f +reg_0C6 = 0x1f +reg_0C7 = 0x53 +reg_0C8 = 0xdb +reg_0C9 = 0x1f +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x30 +reg_164 = 0x30 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x1e +reg_0D3 = 0x3e +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_16_4096_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_16_4096_0_1200_FB.ini new file mode 100755 index 000000000000..caaf19ffe98f --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_16_4096_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x90200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c482 +mau_reg_010 = 0x45517032 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0x20 +reg_013 = 0x05 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x4f +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_16_8192_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_16_8192_0_1200_FB.ini new file mode 100755 index 000000000000..5c0dd0fa2e6a --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_16_8192_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c4c2 +mau_reg_010 = 0x45514832 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xa800d8 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000d8 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0xd20006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0xd0 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x6a +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_32_4096_4096_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_32_4096_4096_1200_FB.ini new file mode 100755 index 000000000000..98045718baf8 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_32_4096_4096_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x4d248f10 +mau_reg_00C = 0x0712c482 +mau_reg_010 = 0x45517032 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0x20 +reg_013 = 0x05 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x4f +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_32_8192_8192_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_32_8192_8192_1200_FB.ini new file mode 100755 index 000000000000..d2ebf5cb766b --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/323/51068A_DDR4_32_8192_8192_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x4d248f10 +mau_reg_00C = 0x0712c4c2 +mau_reg_010 = 0x45514832 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xa800d8 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000d8 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0xd20006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0xd0 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x6a +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_1024_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_1024_0_1066_UBT.ini new file mode 100755 index 000000000000..ec42b615bf5b --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_1024_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae1c +mau_reg_010 = 0x4550edd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x04 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x3c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_1024_0_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_1024_0_800_UBT.ini new file mode 100755 index 000000000000..eecfa80c6235 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_1024_0_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210305 +pllRatio = 0x00215556 +mau_reg_008 = 0x14c2ff04 +mau_reg_00C = 0x1cbc8b16 +mau_reg_010 = 0x4556b16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x13 +reg_013 = 0x03 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x2d +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_1024_0_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_1024_0_933_UBT.ini new file mode 100755 index 000000000000..72b535a27a66 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_1024_0_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d1a +mau_reg_010 = 0x4557cfae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x38 +reg_162 = 0x40 +reg_163 = 0x38 +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x03 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x35 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_2048_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_2048_0_1066_UBT.ini new file mode 100755 index 000000000000..c2c095d24e26 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_2048_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae5c +mau_reg_010 = 0x455057d0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0xc4 +reg_013 = 0x05 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_2048_0_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_2048_0_800_UBT.ini new file mode 100755 index 000000000000..d88f85cc9751 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_2048_0_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x14c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556016c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0s +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x53 +reg_013 = 0x04 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_2048_0_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_2048_0_933_UBT.ini new file mode 100755 index 000000000000..f9361d54f81c --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_2048_0_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x38 +reg_162 = 0x40 +reg_163 = 0x38 +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8f +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x4c +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_1066_FB.ini new file mode 100755 index 000000000000..a5e536ad88ab --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xdd +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x11 +reg_0C8 = 0xdd +reg_0C9 = 0xdd +reg_161 = 0x3c +reg_162 = 0x40 +reg_163 = 0x3c +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x32 +reg_0D3 = 0x32 +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_1066_UBT.ini new file mode 100755 index 000000000000..04a4611b34de --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x80201201 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_800_UBT.ini new file mode 100755 index 000000000000..e443f889f2b5 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x14c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556a16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_933_UBT.ini new file mode 100755 index 000000000000..7fca3fbce153 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_4096_0_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x38 +reg_162 = 0x40 +reg_163 = 0x38 +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x7b +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_8192_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_8192_0_1066_UBT.ini new file mode 100755 index 000000000000..f5c610a77b7f --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR3_16_8192_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x30200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xef +reg_0C5 = 0xef +reg_0C6 = 0x23 +reg_0C7 = 0x23 +reg_0C8 = 0xef +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xf1 +reg_0D3 = 0xf1 +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR4_16_4096_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR4_16_4096_0_1200_FB.ini new file mode 100755 index 000000000000..8a5fdaf77f3b --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR4_16_4096_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x07220584 +mau_reg_010 = 0x45517052 +mau_reg_01C = 0x0131272c +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453e15 +mau_reg_32C = 0x03fc0000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x974 +mau_reg_404 = 0x1 +mau_reg_408 = 0x228 +mau_reg_40C = 0x0 +mau_reg_410 = 0x1800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x24 +reg_117 = 0x24 +reg_113 = 0x24 +reg_0F4 = 0x24 +reg_101 = 0x24 +reg_145 = 0x24 +reg_0EF = 0x24 +reg_0F5 = 0x24 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xdd +reg_0C2 = 0x25 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x11 +reg_0C8 = 0xdd +reg_0C9 = 0xdd +reg_161 = 0x3f +reg_162 = 0x3f +reg_163 = 0x3f +reg_164 = 0x3f +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x66 +reg_000 = 0x88 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x96 +reg_011 = 0x00 +reg_012 = 0x10 +reg_013 = 0x05 +reg_015 = 0x74 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x18 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x05 +reg_004 = 0x05 +reg_005 = 0x83 +reg_006 = 0x06 +reg_007 = 0x02 +reg_009 = 0x10 +reg_00A = 0x0d +reg_00B = 0x12 +reg_020 = 0x24 +reg_021 = 0x09 +reg_022 = 0x4e +reg_023 = 0x03 +reg_027 = 0x00 +reg_028 = 0x01 +reg_02D = 0x2f +reg_28E = 0x95 +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR4_16_4096_0_1200_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR4_16_4096_0_1200_UBT.ini new file mode 100755 index 000000000000..cd8f691c2957 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR4_16_4096_0_1200_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c482 +mau_reg_010 = 0x45517032 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xbb +reg_0C6 = 0xef +reg_0C7 = 0xef +reg_0C8 = 0xab +reg_0C9 = 0xab +reg_161 = 0x28 +reg_162 = 0x30 +reg_163 = 0x28 +reg_164 = 0x30 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0x20 +reg_013 = 0x05 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x4f +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x10 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR4_16_8192_0_1200_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR4_16_8192_0_1200_UBT.ini new file mode 100755 index 000000000000..c5c7e5b96bfd --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/621/51068A_DDR4_16_8192_0_1200_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c4c2 +mau_reg_010 = 0x45514832 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xa800d8 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000d8 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0xd20006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xbb +reg_0C6 = 0xef +reg_0C7 = 0xef +reg_0C8 = 0xab +reg_0C9 = 0xab +reg_161 = 0x28 +reg_162 = 0x30 +reg_163 = 0x28 +reg_164 = 0x30 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0xd0 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x6a +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x10 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_2048_0_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_2048_0_1066_FB.ini new file mode 100755 index 000000000000..8d925251edf3 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_2048_0_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x30210225 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae5c +mau_reg_010 = 0x455057d0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0xc4 +reg_013 = 0x05 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_2048_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_2048_0_1200_FB.ini new file mode 100755 index 000000000000..debc21d517cc --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_2048_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x00320000 +mau_reg_008 = 0x15247f04 +mau_reg_00C = 0x0900c040 +mau_reg_010 = 0x45518012 +mau_reg_01C = 0x0131572a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x08443590 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x238 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x11 +reg_2BC = 0x11 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0xe1 +reg_011 = 0x93 +reg_012 = 0x74 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x38 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x09 +reg_004 = 0x09 +reg_005 = 0x07 +reg_006 = 0x10 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0a +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x61 +reg_023 = 0x06 +reg_027 = 0x81 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_2048_0_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_2048_0_933_FB.ini new file mode 100755 index 000000000000..eb707c195e9f --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_2048_0_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x4C +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_1066_FB.ini new file mode 100755 index 000000000000..411baa436c0d --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_1066_UBT.ini new file mode 100755 index 000000000000..43b201ecd518 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x34 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_1200_FB.ini new file mode 100755 index 000000000000..82380371e5ed --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x00320000 +mau_reg_008 = 0x15247f04 +mau_reg_00C = 0x0900c080 +mau_reg_010 = 0x45517012 +mau_reg_01C = 0x0131572a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x08443590 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x238 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x11 +reg_2BC = 0x11 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0xe1 +reg_011 = 0x93 +reg_012 = 0x34 +reg_013 = 0x0a +reg_015 = 0x44 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x38 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x09 +reg_004 = 0x09 +reg_005 = 0x07 +reg_006 = 0x10 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0a +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x9d +reg_023 = 0x06 +reg_027 = 0x81 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_933_FB.ini new file mode 100755 index 000000000000..6d3ebc28c6c1 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_16_4096_0_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0xF3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x7B +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_1066_FB.ini new file mode 100755 index 000000000000..65de29139518 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20201125 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae5c +mau_reg_010 = 0x455057d0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0xc4 +reg_013 = 0x05 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_800_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_800_FB.ini new file mode 100755 index 000000000000..15f4f73661ff --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_800_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x10210513 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556016c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x53 +reg_013 = 0x04 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_800_UBT.ini new file mode 100755 index 000000000000..ed466edbd74c --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556016c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x53 +reg_013 = 0x04 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_933_FB.ini new file mode 100755 index 000000000000..9e0da5af5eec --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x4C +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_933_UBT.ini new file mode 100755 index 000000000000..91fa3e5f20e0 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_2048_2048_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x4C +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_2048_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_2048_1066_FB.ini new file mode 100755 index 000000000000..9c72ae17bd37 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_2048_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20201104 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef84 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd1000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_2048_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_2048_1066_UBT.ini new file mode 100755 index 000000000000..1d7b64286260 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_2048_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20201021 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef84 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd1000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x34 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_1066_FB.ini new file mode 100755 index 000000000000..84d94552ac81 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_1066_UBT.ini new file mode 100755 index 000000000000..deb12bc12527 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x34 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_800_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_800_FB.ini new file mode 100755 index 000000000000..e29cc5a28688 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_800_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x10210513 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556a16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_800_UBT.ini new file mode 100755 index 000000000000..18657b7666b1 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556a16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_933_FB.ini new file mode 100755 index 000000000000..0c993d16bc40 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0xF3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x7B +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_933_UBT.ini new file mode 100755 index 000000000000..41e8d5465c76 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_4096_4096_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0xF3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x7B +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_8192_8192_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_8192_8192_1066_FB.ini new file mode 100755 index 000000000000..a1a6c9059c57 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR3_32_8192_8192_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x40210422 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x0f +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xff +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x54 +reg_0C3 = 0x06 +reg_0C4 = 0xdb +reg_0C5 = 0x1f +reg_0C6 = 0x1f +reg_0C7 = 0x53 +reg_0C8 = 0xdb +reg_0C9 = 0x1f +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x30 +reg_164 = 0x30 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x1e +reg_0D3 = 0x3e +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_16_4096_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_16_4096_0_1200_FB.ini new file mode 100755 index 000000000000..caaf19ffe98f --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_16_4096_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x90200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c482 +mau_reg_010 = 0x45517032 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0x20 +reg_013 = 0x05 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x4f +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_16_8192_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_16_8192_0_1200_FB.ini new file mode 100755 index 000000000000..5c0dd0fa2e6a --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_16_8192_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c4c2 +mau_reg_010 = 0x45514832 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xa800d8 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000d8 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0xd20006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0xd0 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x6a +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_32_4096_4096_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_32_4096_4096_1200_FB.ini new file mode 100755 index 000000000000..98045718baf8 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_32_4096_4096_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x4d248f10 +mau_reg_00C = 0x0712c482 +mau_reg_010 = 0x45517032 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0x20 +reg_013 = 0x05 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x4f +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_32_8192_8192_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_32_8192_8192_1200_FB.ini new file mode 100755 index 000000000000..d2ebf5cb766b --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/623/51068A_DDR4_32_8192_8192_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x4d248f10 +mau_reg_00C = 0x0712c4c2 +mau_reg_010 = 0x45514832 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xa800d8 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000d8 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0xd20006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0xd0 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x6a +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_1024_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_1024_0_1066_UBT.ini new file mode 100755 index 000000000000..ec42b615bf5b --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_1024_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae1c +mau_reg_010 = 0x4550edd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x04 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x3c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_1024_0_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_1024_0_800_UBT.ini new file mode 100755 index 000000000000..eecfa80c6235 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_1024_0_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210305 +pllRatio = 0x00215556 +mau_reg_008 = 0x14c2ff04 +mau_reg_00C = 0x1cbc8b16 +mau_reg_010 = 0x4556b16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x13 +reg_013 = 0x03 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x2d +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_1024_0_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_1024_0_933_UBT.ini new file mode 100755 index 000000000000..72b535a27a66 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_1024_0_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d1a +mau_reg_010 = 0x4557cfae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x38 +reg_162 = 0x40 +reg_163 = 0x38 +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8f +reg_012 = 0x93 +reg_013 = 0x03 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x35 +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_2048_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_2048_0_1066_UBT.ini new file mode 100755 index 000000000000..c2c095d24e26 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_2048_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae5c +mau_reg_010 = 0x455057d0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0xc4 +reg_013 = 0x05 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_2048_0_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_2048_0_800_UBT.ini new file mode 100755 index 000000000000..d88f85cc9751 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_2048_0_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x14c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556016c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0s +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x53 +reg_013 = 0x04 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_2048_0_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_2048_0_933_UBT.ini new file mode 100755 index 000000000000..f9361d54f81c --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_2048_0_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x38 +reg_162 = 0x40 +reg_163 = 0x38 +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8f +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x4c +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_1066_FB.ini new file mode 100755 index 000000000000..a5e536ad88ab --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xdd +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x11 +reg_0C8 = 0xdd +reg_0C9 = 0xdd +reg_161 = 0x3c +reg_162 = 0x40 +reg_163 = 0x3c +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x32 +reg_0D3 = 0x32 +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_1066_UBT.ini new file mode 100755 index 000000000000..04a4611b34de --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x80201201 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_800_UBT.ini new file mode 100755 index 000000000000..e443f889f2b5 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x14c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556a16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_933_UBT.ini new file mode 100755 index 000000000000..7fca3fbce153 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_4096_0_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x22 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x01 +reg_0C7 = 0x01 +reg_0C8 = 0xcd +reg_0C9 = 0xcd +reg_161 = 0x38 +reg_162 = 0x40 +reg_163 = 0x38 +reg_164 = 0x40 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x0f +reg_0D3 = 0x0f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8f +reg_012 = 0xf3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0f +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0e +reg_020 = 0x37 +reg_021 = 0x0e +reg_022 = 0x7b +reg_023 = 0x06 +reg_027 = 0x2c +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_8192_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_8192_0_1066_UBT.ini new file mode 100755 index 000000000000..f5c610a77b7f --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR3_16_8192_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x30200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xef +reg_0C5 = 0xef +reg_0C6 = 0x23 +reg_0C7 = 0x23 +reg_0C8 = 0xef +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xf1 +reg_0D3 = 0xf1 +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR4_16_4096_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR4_16_4096_0_1200_FB.ini new file mode 100755 index 000000000000..8a5fdaf77f3b --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR4_16_4096_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x07220584 +mau_reg_010 = 0x45517052 +mau_reg_01C = 0x0131272c +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453e15 +mau_reg_32C = 0x03fc0000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x974 +mau_reg_404 = 0x1 +mau_reg_408 = 0x228 +mau_reg_40C = 0x0 +mau_reg_410 = 0x1800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x24 +reg_117 = 0x24 +reg_113 = 0x24 +reg_0F4 = 0x24 +reg_101 = 0x24 +reg_145 = 0x24 +reg_0EF = 0x24 +reg_0F5 = 0x24 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xdd +reg_0C2 = 0x25 +reg_0C3 = 0x08 +reg_0C4 = 0xdd +reg_0C5 = 0xdd +reg_0C6 = 0x11 +reg_0C7 = 0x11 +reg_0C8 = 0xdd +reg_0C9 = 0xdd +reg_161 = 0x3f +reg_162 = 0x3f +reg_163 = 0x3f +reg_164 = 0x3f +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x66 +reg_000 = 0x88 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x96 +reg_011 = 0x00 +reg_012 = 0x10 +reg_013 = 0x05 +reg_015 = 0x74 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x18 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x05 +reg_004 = 0x05 +reg_005 = 0x83 +reg_006 = 0x06 +reg_007 = 0x02 +reg_009 = 0x10 +reg_00A = 0x0d +reg_00B = 0x12 +reg_020 = 0x24 +reg_021 = 0x09 +reg_022 = 0x4e +reg_023 = 0x03 +reg_027 = 0x00 +reg_028 = 0x01 +reg_02D = 0x2f +reg_28E = 0x95 +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR4_16_4096_0_1200_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR4_16_4096_0_1200_UBT.ini new file mode 100755 index 000000000000..cd8f691c2957 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR4_16_4096_0_1200_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c482 +mau_reg_010 = 0x45517032 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xbb +reg_0C6 = 0xef +reg_0C7 = 0xef +reg_0C8 = 0xab +reg_0C9 = 0xab +reg_161 = 0x28 +reg_162 = 0x30 +reg_163 = 0x28 +reg_164 = 0x30 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0x20 +reg_013 = 0x05 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x4f +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x10 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR4_16_8192_0_1200_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR4_16_8192_0_1200_UBT.ini new file mode 100755 index 000000000000..c5c7e5b96bfd --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC321/51068A_DDR4_16_8192_0_1200_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c4c2 +mau_reg_010 = 0x45514832 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xa800d8 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000d8 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0xd20006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xbb +reg_0C6 = 0xef +reg_0C7 = 0xef +reg_0C8 = 0xab +reg_0C9 = 0xab +reg_161 = 0x28 +reg_162 = 0x30 +reg_163 = 0x28 +reg_164 = 0x30 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0xd0 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x6a +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x10 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_2048_0_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_2048_0_1066_FB.ini new file mode 100755 index 000000000000..8d925251edf3 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_2048_0_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x30210225 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae5c +mau_reg_010 = 0x455057d0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0xc4 +reg_013 = 0x05 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_2048_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_2048_0_1200_FB.ini new file mode 100755 index 000000000000..debc21d517cc --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_2048_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x00320000 +mau_reg_008 = 0x15247f04 +mau_reg_00C = 0x0900c040 +mau_reg_010 = 0x45518012 +mau_reg_01C = 0x0131572a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x08443590 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x238 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x11 +reg_2BC = 0x11 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0xe1 +reg_011 = 0x93 +reg_012 = 0x74 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x38 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x09 +reg_004 = 0x09 +reg_005 = 0x07 +reg_006 = 0x10 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0a +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x61 +reg_023 = 0x06 +reg_027 = 0x81 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_2048_0_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_2048_0_933_FB.ini new file mode 100755 index 000000000000..eb707c195e9f --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_2048_0_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x4C +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_1066_FB.ini new file mode 100755 index 000000000000..411baa436c0d --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_1066_UBT.ini new file mode 100755 index 000000000000..43b201ecd518 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x1503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x34 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_1200_FB.ini new file mode 100755 index 000000000000..82380371e5ed --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x00320000 +mau_reg_008 = 0x15247f04 +mau_reg_00C = 0x0900c080 +mau_reg_010 = 0x45517012 +mau_reg_01C = 0x0131572a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x08443590 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x238 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x11 +reg_2BC = 0x11 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0xe1 +reg_011 = 0x93 +reg_012 = 0x34 +reg_013 = 0x0a +reg_015 = 0x44 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x38 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x09 +reg_004 = 0x09 +reg_005 = 0x07 +reg_006 = 0x10 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0a +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x9d +reg_023 = 0x06 +reg_027 = 0x81 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_933_FB.ini new file mode 100755 index 000000000000..6d3ebc28c6c1 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_16_4096_0_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210225 +pllRatio = 0x0026e000 +mau_reg_008 = 0x14e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0xF3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x7B +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_1066_FB.ini new file mode 100755 index 000000000000..65de29139518 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20201125 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae5c +mau_reg_010 = 0x455057d0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0xc4 +reg_013 = 0x05 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x57 +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_800_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_800_FB.ini new file mode 100755 index 000000000000..15f4f73661ff --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_800_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x10210513 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556016c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x53 +reg_013 = 0x04 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_800_UBT.ini new file mode 100755 index 000000000000..ed466edbd74c --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556016c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0x53 +reg_013 = 0x04 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x41 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_933_FB.ini new file mode 100755 index 000000000000..9e0da5af5eec --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x4C +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_933_UBT.ini new file mode 100755 index 000000000000..91fa3e5f20e0 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_2048_2048_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x45572dae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0x13 +reg_013 = 0x05 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x4C +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_2048_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_2048_1066_FB.ini new file mode 100755 index 000000000000..9c72ae17bd37 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_2048_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20201104 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef84 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd1000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_2048_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_2048_1066_UBT.ini new file mode 100755 index 000000000000..1d7b64286260 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_2048_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20201021 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef84 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd1000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x34 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_1066_FB.ini new file mode 100755 index 000000000000..84d94552ac81 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x34 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_1066_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_1066_UBT.ini new file mode 100755 index 000000000000..deb12bc12527 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_1066_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x50200901 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x30 +reg_162 = 0x34 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_800_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_800_FB.ini new file mode 100755 index 000000000000..e29cc5a28688 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_800_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x10210513 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556a16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x33 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x10 +reg_0D3 = 0x2f +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_800_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_800_UBT.ini new file mode 100755 index 000000000000..18657b7666b1 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_800_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x20210406 +pllRatio = 0x00215556 +mau_reg_008 = 0x04c2ff04 +mau_reg_00C = 0x1cbc8b56 +mau_reg_010 = 0x4556a16c +mau_reg_01C = 0x012d04e9 +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844350b +mau_reg_32C = 0x00000000 +mau_reg_014 = 0xd70 +mau_reg_018 = 0x218 +mau_reg_324 = 0X40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x41 +reg_011 = 0x0d +reg_012 = 0xd3 +reg_013 = 0x06 +reg_015 = 0x70 +reg_016 = 0x0d +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x07 +reg_004 = 0x07 +reg_005 = 0x05 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x08 +reg_00A = 0x05 +reg_00B = 0x0c +reg_020 = 0x31 +reg_021 = 0x0c +reg_022 = 0x69 +reg_023 = 0x06 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x4f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_933_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_933_FB.ini new file mode 100755 index 000000000000..0c993d16bc40 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_933_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x44 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xef +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0xff +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0xF3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x7B +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_933_UBT.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_933_UBT.ini new file mode 100755 index 000000000000..41e8d5465c76 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_4096_4096_933_UBT.ini @@ -0,0 +1,147 @@ +ini_ver = 0x60200918 +pllRatio = 0x0026e000 +mau_reg_008 = 0x04e36f04 +mau_reg_00C = 0x00de9d5a +mau_reg_010 = 0x4557e7ae +mau_reg_01C = 0x012d0daa +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844352d +mau_reg_32C = 0x00100000 +mau_reg_014 = 0xf14 +mau_reg_018 = 0x220 +mau_reg_324 = 0x40000 +mau_reg_384 = 0x9 +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x00 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x08 +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xf8 +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x43 +reg_0C3 = 0x08 +reg_0C4 = 0xcc +reg_0C5 = 0xee +reg_0C6 = 0xf0 +reg_0C7 = 0x12 +reg_0C8 = 0xbc +reg_0C9 = 0xde +reg_161 = 0x40 +reg_162 = 0x48 +reg_163 = 0x40 +reg_164 = 0x44 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x06 +reg_091 = 0x55 +reg_0D2 = 0xfe +reg_0D3 = 0x0d +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x23 +reg_011 = 0x8F +reg_012 = 0xF3 +reg_013 = 0x07 +reg_015 = 0x14 +reg_016 = 0x0F +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x20 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x08 +reg_007 = 0x03 +reg_009 = 0x09 +reg_00A = 0x07 +reg_00B = 0x0E +reg_020 = 0x37 +reg_021 = 0x0E +reg_022 = 0x7B +reg_023 = 0x06 +reg_027 = 0x2C +reg_028 = 0x01 +reg_02D = 0x4F +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_8192_8192_1066_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_8192_8192_1066_FB.ini new file mode 100755 index 000000000000..a1a6c9059c57 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR3_32_8192_8192_1066_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x40210422 +pllRatio = 0x002c7000 +mau_reg_008 = 0x0503ef04 +mau_reg_00C = 0x04e0ae9c +mau_reg_010 = 0x45502dd0 +mau_reg_01C = 0x012f364a +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x500 +mau_reg_148 = 0x0844354e +mau_reg_32C = 0x01500000 +mau_reg_014 = 0x124 +mau_reg_018 = 0x228 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xa +mau_reg_3F4 = 0x0 +mau_reg_420 = 0x0 +mau_reg_424 = 0x0 +mau_reg_428 = 0x0 +mau_reg_42C = 0x0 +mau_reg_430 = 0x0 +mau_reg_434 = 0x0 +mau_reg_438 = 0x0 +mau_reg_400 = 0x0 +mau_reg_404 = 0x0 +mau_reg_408 = 0x0 +mau_reg_40C = 0x0 +mau_reg_410 = 0x0 +mau_reg_414 = 0x0 +mau_reg_418 = 0x0 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x04 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x0f +reg_117 = 0x0f +reg_113 = 0x0f +reg_0F4 = 0x0f +reg_101 = 0x0f +reg_145 = 0x0f +reg_0EF = 0x0f +reg_0F5 = 0x0f +reg_10F = 0x03 +reg_102 = 0x13 +reg_106 = 0x36 +reg_121 = 0x31 +reg_0EE = 0x03 +reg_13A = 0x3f +reg_108 = 0x03 +reg_0E7 = 0x30 +reg_0EC = 0x03 +reg_103 = 0x60 +reg_122 = 0xf3 +reg_0F3 = 0x03 +reg_0F2 = 0x08 +reg_11B = 0x08 +reg_0E8 = 0x08 +reg_11A = 0x18 +reg_112 = 0x0f +reg_14D = 0x80 +reg_14E = 0x80 +reg_0F0 = 0x08 +reg_115 = 0x08 +reg_100 = 0x80 +reg_104 = 0x80 +reg_141 = 0xff +reg_142 = 0x01 +reg_0F1 = 0x01 +reg_138 = 0x20 +reg_118 = 0x01 +reg_139 = 0x11 +reg_148 = 0x10 +reg_0C1 = 0xff +reg_0C2 = 0x54 +reg_0C3 = 0x06 +reg_0C4 = 0xdb +reg_0C5 = 0x1f +reg_0C6 = 0x1f +reg_0C7 = 0x53 +reg_0C8 = 0xdb +reg_0C9 = 0x1f +reg_161 = 0x30 +reg_162 = 0x30 +reg_163 = 0x30 +reg_164 = 0x30 +reg_092 = 0x44 +reg_093 = 0x44 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x07 +reg_091 = 0x55 +reg_0D2 = 0x1e +reg_0D3 = 0x3e +reg_000 = 0x00 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x82 +reg_011 = 0x11 +reg_012 = 0x14 +reg_013 = 0x09 +reg_015 = 0x24 +reg_016 = 0x01 +reg_017 = 0x00 +reg_018 = 0x00 +reg_019 = 0x28 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x00 +reg_062 = 0x00 +reg_063 = 0x00 +reg_064 = 0x00 +reg_065 = 0x00 +reg_001 = 0x02 +reg_002 = 0x08 +reg_004 = 0x08 +reg_005 = 0x06 +reg_006 = 0x09 +reg_007 = 0x03 +reg_009 = 0x0a +reg_00A = 0x08 +reg_00B = 0x10 +reg_020 = 0xff +reg_021 = 0x0f +reg_022 = 0x8c +reg_023 = 0x06 +reg_027 = 0x57 +reg_028 = 0x01 +reg_02D = 0x5f +reg_28E = 0x95 +reg_066 = 0x00 +reg_251 = 0x30 +reg_143 = 0x0f +reg_11C = 0xf0 +reg_0EA = 0x00 +reg_13B = 0x0f +reg_120 = 0xf0 +reg_144 = 0xff +reg_105 = 0xf0 +reg_10A = 0xf0 +reg_107 = 0xf0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_16_4096_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_16_4096_0_1200_FB.ini new file mode 100755 index 000000000000..caaf19ffe98f --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_16_4096_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x90200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c482 +mau_reg_010 = 0x45517032 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0x20 +reg_013 = 0x05 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x4f +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_16_8192_0_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_16_8192_0_1200_FB.ini new file mode 100755 index 000000000000..5c0dd0fa2e6a --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_16_8192_0_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x5d248f10 +mau_reg_00C = 0x0712c4c2 +mau_reg_010 = 0x45514832 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xa800d8 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000d8 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0xd20006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0xd0 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x6a +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_32_4096_4096_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_32_4096_4096_1200_FB.ini new file mode 100755 index 000000000000..98045718baf8 --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_32_4096_4096_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x4d248f10 +mau_reg_00C = 0x0712c482 +mau_reg_010 = 0x45517032 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xde00a2 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000a2 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0x9c0006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0x20 +reg_013 = 0x05 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x4f +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_32_8192_8192_1200_FB.ini b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_32_8192_8192_1200_FB.ini new file mode 100755 index 000000000000..d2ebf5cb766b --- /dev/null +++ b/board/novatek/na51068/loader/Tools/ConfigRam/NC323/51068A_DDR4_32_8192_8192_1200_FB.ini @@ -0,0 +1,147 @@ +ini_ver = 0x70200901 +pllRatio = 0x00320000 +mau_reg_008 = 0x4d248f10 +mau_reg_00C = 0x0712c4c2 +mau_reg_010 = 0x45514832 +mau_reg_01C = 0x0131270e +mau_reg_020 = 0xd0000000 +mau_reg_050 = 0x706 +mau_reg_148 = 0x08453d94 +mau_reg_32C = 0x03f80000 +mau_reg_014 = 0x144 +mau_reg_018 = 0x438 +mau_reg_324 = 0x40000 +mau_reg_384 = 0xf000 +mau_reg_3F4 = 0xa800d8 +mau_reg_420 = 0x1 +mau_reg_424 = 0xb0003 +mau_reg_428 = 0x20000d8 +mau_reg_42C = 0x1800100 +mau_reg_430 = 0x90006 +mau_reg_434 = 0xd20006 +mau_reg_438 = 0x31248 +mau_reg_400 = 0x944 +mau_reg_404 = 0x1 +mau_reg_408 = 0x218 +mau_reg_40C = 0x0 +mau_reg_410 = 0x800 +mau_reg_414 = 0x1400 +mau_reg_418 = 0x800 +mau_reg_640 = 0x0 +axic0_reg_440 = 0x1010 +axic2_reg_440 = 0x1010 +axic2_reg_444 = 0x1010 +axic2_reg_448 = 0x1010 +axic2_reg_44C = 0x1010 +reg_0BC = 0x08 +reg_14A = 0x00 +reg_14C = 0x00 +reg_146 = 0x18 +reg_117 = 0x18 +reg_113 = 0x18 +reg_0F4 = 0x18 +reg_101 = 0x18 +reg_145 = 0x18 +reg_0EF = 0x18 +reg_0F5 = 0x18 +reg_10F = 0x04 +reg_102 = 0x24 +reg_106 = 0x46 +reg_121 = 0x42 +reg_0EE = 0x04 +reg_13A = 0x4b +reg_108 = 0x00 +reg_0E7 = 0x00 +reg_0EC = 0x00 +reg_103 = 0x00 +reg_122 = 0xb0 +reg_0F3 = 0x00 +reg_0F2 = 0x09 +reg_11B = 0x09 +reg_0E8 = 0x09 +reg_11A = 0x29 +reg_112 = 0x09 +reg_14D = 0x90 +reg_14E = 0x90 +reg_0F0 = 0x09 +reg_115 = 0x09 +reg_100 = 0x90 +reg_104 = 0x90 +reg_141 = 0xb9 +reg_142 = 0x02 +reg_0F1 = 0x02 +reg_138 = 0x40 +reg_118 = 0x02 +reg_139 = 0x22 +reg_148 = 0x20 +reg_0C1 = 0xff +reg_0C2 = 0x55 +reg_0C3 = 0x08 +reg_0C4 = 0xbb +reg_0C5 = 0xdd +reg_0C6 = 0xee +reg_0C7 = 0x00 +reg_0C8 = 0xaa +reg_0C9 = 0xcc +reg_161 = 0x30 +reg_162 = 0x38 +reg_163 = 0x30 +reg_164 = 0x38 +reg_092 = 0x55 +reg_093 = 0x55 +reg_2BB = 0x22 +reg_2BC = 0x22 +reg_426 = 0x00 +reg_091 = 0xff +reg_0D2 = 0x99 +reg_0D3 = 0x88 +reg_000 = 0x80 +reg_00D = 0x20 +reg_00E = 0x00 +reg_00F = 0x00 +reg_010 = 0x97 +reg_011 = 0x00 +reg_012 = 0xd0 +reg_013 = 0x06 +reg_015 = 0x44 +reg_016 = 0x09 +reg_017 = 0x01 +reg_018 = 0x00 +reg_019 = 0x18 +reg_01A = 0x02 +reg_01B = 0x00 +reg_01C = 0x00 +reg_060 = 0x00 +reg_061 = 0x08 +reg_062 = 0x00 +reg_063 = 0x14 +reg_064 = 0x00 +reg_065 = 0x08 +reg_001 = 0x01 +reg_002 = 0x06 +reg_004 = 0x06 +reg_005 = 0x85 +reg_006 = 0x07 +reg_007 = 0x03 +reg_009 = 0x0c +reg_00A = 0x0c +reg_00B = 0x12 +reg_020 = 0x25 +reg_021 = 0x09 +reg_022 = 0x6a +reg_023 = 0x05 +reg_027 = 0x01 +reg_028 = 0x01 +reg_02D = 0x3f +reg_28E = 0x8d +reg_066 = 0x02 +reg_251 = 0x30 +reg_143 = 0x0b +reg_11C = 0xb0 +reg_0EA = 0x00 +reg_13B = 0x0b +reg_120 = 0xb0 +reg_144 = 0xbb +reg_105 = 0xb0 +reg_10A = 0xb0 +reg_107 = 0xb0 diff --git a/board/novatek/na51068/na51068.c b/board/novatek/na51068/na51068.c new file mode 100644 index 000000000000..fd302ade2563 --- /dev/null +++ b/board/novatek/na51068/na51068.c @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Novatek NA51068 DVR/NVR board (NT98321, NT98323): the device tree the + * loader hands over, the memory split the vendor kernels expect in it, + * the Ethernet glue and the SD host. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +/* + * The loader leaves its device tree, which describes the board for the + * vendor kernels, in DDR and its address in SHMINFO. OpenIPC uImages carry + * no device tree, so bootm passes this one (${fdtaddr}). It lies where the + * kernel is unpacked, so it is copied away first. + */ +static void nvt_fdt_init(void) +{ + const void *fdt = nvt_loader_fdt(); + void *copy; + + if (!fdt) { + printf("FDT: no device tree from the loader\n"); + return; + } + copy = malloc(fdt_totalsize(fdt)); + if (!copy) + return; + memcpy(copy, fdt, fdt_totalsize(fdt)); + env_set_hex("fdtaddr", (ulong)copy); +} + +int misc_init_r(void) +{ + int ret = openipc_helper(); + + /* After the helper's first saveenv: the address is this boot's */ + nvt_fdt_init(); + return ret; +} + +/* + * U-Boot relocates to the top of the loader's region for it + * (/nvt_memory_cfg/uboot), as on NA51089: clear of core2entry2 at the + * top of the 512 MiB, where the second core waits for Linux. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + return NVT_UBOOT_BASE + NVT_UBOOT_SIZE; +} + +/* What Linux gets of the DDR (mem=); the vendor media modules get the rest */ +static ulong nvt_osmem(void) +{ + char *end; + ulong osmem = ustrtoul(env_get("osmem") ?: "", &end, 0); + + if (!osmem || osmem > gd->ram_size) + osmem = gd->ram_size; + return osmem; +} + +/* + * The device tree and initrd go where Linux can reach them: everything + * past ${osmem} is reserved. lmb refuses a reservation that overlaps one + * it has (U-Boot's own, up to the end of DDR), so only the gaps are. + */ +void board_lmb_reserve(struct lmb *lmb) +{ + struct lmb_property rsv[8]; + phys_addr_t lo = NVT_DDR_BASE + nvt_osmem(); + phys_addr_t hi = NVT_DDR_BASE + gd->ram_size; + unsigned long i, n = min_t(unsigned long, lmb->reserved.cnt, + ARRAY_SIZE(rsv)); + + /* A copy: the reservations below insert into the sorted list */ + memcpy(rsv, &lmb->reserved.region[0], n * sizeof(rsv[0])); + for (i = 0; i < n && lo < hi; i++) { + phys_addr_t base = rsv[i].base; + phys_addr_t end = base + rsv[i].size; + + if (end <= lo || base >= hi) + continue; + if (base > lo) + lmb_reserve(lmb, lo, base - lo); + lo = max(lo, end); + } + if (lo < hi) + lmb_reserve(lmb, lo, hi - lo); +} + +/* + * As the vendor U-Boot's nvt_boot: Linux gets the first ${osmem} of the + * DDR, and the media pool of the vendor modules (/hdal-memory/media) the + * rest. + */ +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ulong osmem = nvt_osmem(); + fdt32_t media[2]; + int node, ret; + + ret = fdt_fixup_memory(blob, NVT_DDR_BASE, osmem); + if (ret) + return ret; + + node = fdt_path_offset(blob, "/hdal-memory/media"); + if (node < 0) + return 0; + media[0] = cpu_to_fdt32(NVT_DDR_BASE + osmem); + media[1] = cpu_to_fdt32(gd->ram_size - osmem); + return fdt_setprop(blob, node, "reg", media, sizeof(media)); +} + +static u32 nvt_fdt_u32(const void *fdt, const char *path, const char *prop, + u32 def) +{ + const fdt32_t *val = NULL; + int node; + + if (fdt) { + node = fdt_path_offset(fdt, path); + if (node >= 0) + val = fdt_getprop(fdt, node, prop, NULL); + } + return val ? fdt32_to_cpu(*val) : def; +} + +#ifdef CONFIG_NVT_EQOS +/* + * Ethernet: two MACs, each wired by /top@fe030000/eth pinmux in the + * loader's device tree to an RGMII or RMII PHY on its own pads, or to the + * embedded PHY (0x1201 on the SDK's NT98323 boards: MAC 0 RGMII, the + * embedded PHY on MAC 1). Pins, clocks, resets and the PHY as by the + * vendor U-Boot's eth_na51068.c; nvt_eqos does the MAC. Each MAC with a + * PHY is registered, eth0 first: U-Boot goes on to the next if one has + * no link. + */ +#define ETH_RGMII(n) BIT(n) /* 0x001, 0x002 */ +#define ETH_RMII(n) BIT(4 + (n)) /* 0x010, 0x020 */ +#define ETH_EMB_PHY(n) BIT(8 + (n)) /* 0x100, 0x200 */ + +#define CG(off) (NVT_CG_BASE + (off)) +#define TOP(off) (NVT_TOP_BASE + (off)) +#define PAD(off) (NVT_PAD_BASE + (off)) +#define CG_AXI_RSTN CG(0x54) +#define CG_MOD_RSTN CG(0x58) +#define CG_BUS_GATE CG(0x60) +#define CG_MOD_GATE CG(0x70) +#define CG_GPIO_GATE CG(0x74) +#define CG_ETH_GLUE CG(0xE4) +#define TOP_EMB_PHY TOP(0xC8) /* bit 0: to MAC 0, else MAC 1 */ + +/* The glue, at +0x3000; the embedded PHY at +0x3800 */ +#define ETH_PHY_SEL(b) ((b) + 0x3004) +#define PHY_SEL_EXT BIT(8) +#define ETH_LED_CTRL(b) ((b) + 0x300C) +#define ETH_CLK_CTRL(b) ((b) + 0x3014) +#define CLK_REF_IN BIT(0) +#define CLK_REF_PAD BIT(2) +#define CLK_REF_OUT BIT(4) +#define CLK_TXD_SRC (3 << 30) +#define CLK_TXD_RGMII (1 << 30) +#define PHY(b, off) ((b) + 0x3800 + (off)) +#define PHY_SW_RESET BIT(1) +#define PHY_PLLREGWR BIT(3) + +int nvt_eqos_register(const char *name, ulong base, phy_interface_t intf, + u32 cr); + +static const struct nvt_mac { + ulong base; + const char *node; + u8 axi_rst, mod_rst, glue_rst, bus_gate, mod_gate; + u8 gpio_gate, gpio_rst, refclk_gate, phyclk_out; + ulong phyclk_mux; /* the PHY's 25 MHz on a pad, [2:0] */ + u32 phy_rst; /* the PHY's reset GPIO, the EVB's */ +} nvt_macs[2] = { + { NVT_ETH0_BASE, "/eth0@fcc00000", 1, 9, 8, 16, 9, 5, 29, 4, 7, + TOP(0x70), 2 * 32 + 21 }, + { NVT_ETH1_BASE, "/eth1@fcd00000", 2, 10, 24, 17, 10, 4, 28, 20, 23, + TOP(0x50), 1 * 32 + 17 }, +}; + +/* The four FTGPIO010 banks, 32 pins each */ +static const ulong nvt_gpio_bank[4] = { + 0xFE400000, NVT_GPIO1_BASE, NVT_GPIO2_BASE, 0xFE640000, +}; + +#define GPIO_DIR 0x08 +#define GPIO_SET 0x10 +#define GPIO_CLEAR 0x14 + +/* Hold an external PHY in reset for 10 ms, then 50 ms to wake up */ +static void nvt_phy_reset(u32 pin) +{ + ulong bank; + + if (pin / 32 >= ARRAY_SIZE(nvt_gpio_bank)) + return; + bank = nvt_gpio_bank[pin / 32]; + setbits_le32(bank + GPIO_DIR, BIT(pin % 32)); + writel(BIT(pin % 32), bank + GPIO_CLEAR); + mdelay(10); + writel(BIT(pin % 32), bank + GPIO_SET); + mdelay(50); +} + +/* The pads of an external PHY, as the vendor's mac0/1_pinmux_en() */ +static void nvt_mac_pins(int n, phy_interface_t intf) +{ + bool rgmii = intf == PHY_INTERFACE_MODE_RGMII; + + if (n == 0) { + /* Drive: PHYCLK 8 mA, and for RGMII the Tx pads too */ + clrsetbits_le32(PAD(0xC0), rgmii ? 0xffc0003 : 0xfc0033, + rgmii ? 0x5540001 : 0x1); + clrsetbits_le32(TOP(0xC8), 0xf << 4, (rgmii ? 1 : 4) << 4); + clrsetbits_le32(TOP(0x70), rgmii ? 0xffffff0f : 0xfff0f, + rgmii ? 0x11111101 : 0x00222202); + clrsetbits_le32(TOP(0x74), rgmii ? 0xffffffff : 0xff00fff0, + rgmii ? 0x11111111 : 0x22002220); + clrsetbits_le32(PAD(0x40), 0xf000000c, 0xa0000008); + } else { + if (rgmii) { + clrsetbits_le32(PAD(0xA0), 0x30003, 0x10001); + clrsetbits_le32(PAD(0xA4), 0x3ff, 0x155); + } else { + clrsetbits_le32(PAD(0xA0), 0xf, 0x1); + clrbits_le32(PAD(0xA4), 0x3f); + } + clrsetbits_le32(TOP(0x50), rgmii ? 0xffffff0f : 0xffff0f, + rgmii ? 0x66666606 : 0x222202); + clrsetbits_le32(TOP(0x54), rgmii ? 0xffffff0f : 0xff00fff0, + rgmii ? 0x66666606 : 0x22002220); + clrsetbits_le32(TOP(0xC8), 0xf << 8, (rgmii ? 1 : 4) << 8); + } +} + +/* Clocks and resets, as the vendor's mac0/1_clk_en() */ +static void nvt_mac_clocks(const struct nvt_mac *m, phy_interface_t intf) +{ + clrbits_le32(CG_AXI_RSTN, BIT(m->axi_rst)); + clrbits_le32(CG_MOD_RSTN, BIT(m->mod_rst)); + clrbits_le32(CG_ETH_GLUE, BIT(m->glue_rst)); + clrbits_le32(CG_BUS_GATE, BIT(m->bus_gate)); + clrbits_le32(CG_MOD_GATE, BIT(m->mod_gate)); + clrbits_le32(CG_GPIO_GATE, BIT(m->gpio_gate)); + /* The embedded PHY: MAC 0 gates its RMII reference in, MAC 1 not */ + if (intf == PHY_INTERFACE_MODE_MII) { + if (m->base == NVT_ETH0_BASE) + setbits_le32(CG_ETH_GLUE, BIT(m->refclk_gate)); + else + clrbits_le32(CG_ETH_GLUE, BIT(m->refclk_gate)); + } + setbits_le32(CG_AXI_RSTN, BIT(m->axi_rst)); + setbits_le32(CG_MOD_RSTN, BIT(m->mod_rst) | BIT(m->gpio_rst)); + setbits_le32(CG_ETH_GLUE, BIT(m->glue_rst)); +} + +/* The embedded PHY: power on, then its own reset, as the vendor */ +static void nvt_emb_phy_on(ulong b) +{ + setbits_le32(PHY(b, 0xF8), BIT(7)); + udelay(20); + clrbits_le32(PHY(b, 0xC8), BIT(0)); + udelay(200); + clrbits_le32(PHY(b, 0xC8), BIT(1)); + udelay(250); + clrbits_le32(PHY(b, 0x2E8), BIT(0)); + clrbits_le32(PHY(b, 0xCC), BIT(0)); + setbits_le32(PHY(b, 0xDC), BIT(0)); + clrbits_le32(PHY(b, 0x9C), BIT(0)); + + setbits_le32(PHY(b, 0x000), PHY_SW_RESET); + /* The break-link timer, and the LEDs blinking, as the vendor */ + writel(0x53, PHY(b, 0x288)); + writel(0x07, PHY(b, 0x28C)); + writel(0xC9, PHY(b, 0x284)); + writel(0x40, PHY(b, 0x100)); + writel(0x312, ETH_LED_CTRL(b)); + mdelay(10); + clrsetbits_le32(PHY(b, 0x000), PHY_SW_RESET, PHY_PLLREGWR); +} + +/* The PHY side, as the vendor's extphy0/1_clk_en() */ +static void nvt_mac_phy(const void *fdt, const struct nvt_mac *m, + phy_interface_t intf) +{ + ulong b = m->base; + + if (intf == PHY_INTERFACE_MODE_MII) { + clrbits_le32(ETH_PHY_SEL(b), PHY_SEL_EXT); + nvt_emb_phy_on(b); + return; + } + if (intf == PHY_INTERFACE_MODE_RMII) { + u32 v = readl(ETH_CLK_CTRL(b)) & ~(CLK_REF_PAD | CLK_TXD_SRC); + + if (nvt_fdt_u32(fdt, m->node, "ref-clk-out", 0)) + v = (v & ~CLK_REF_IN) | CLK_REF_OUT; + writel(v, ETH_CLK_CTRL(b)); + } else { + setbits_le32(ETH_CLK_CTRL(b), CLK_TXD_RGMII); + } + setbits_le32(ETH_PHY_SEL(b), PHY_SEL_EXT); + writel(0x1FF, ETH_LED_CTRL(b)); + + /* The PHY's 25 MHz crystal clock from the SoC */ + if (nvt_fdt_u32(fdt, m->node, "sp-clk", 0)) { + setbits_le32(CG_ETH_GLUE, BIT(m->phyclk_out)); + clrsetbits_le32(m->phyclk_mux, 0x7, + intf == PHY_INTERFACE_MODE_RMII ? 2 : + m->base == NVT_ETH0_BASE ? 1 : 6); + } + nvt_phy_reset(nvt_fdt_u32(fdt, m->node, "phy-rst", m->phy_rst)); +} + +int board_eth_init(struct bd_info *bis) +{ + const void *fdt = nvt_loader_fdt(); + u32 pins = nvt_fdt_u32(fdt, "/top@fe030000/eth", "pinmux", + ETH_EMB_PHY(1)); + u32 misc = nvt_fdt_u32(fdt, "/top@fe030000/misc", "pinmux", 0); + int n, ret = 0; + + /* The embedded PHY's LEDs, on either of two pad pairs */ + if (misc & BIT(20)) + clrsetbits_le32(TOP(0x20), 0xff0, 0x550); + else if (misc & BIT(21)) + clrsetbits_le32(TOP(0x44), 0xff, 0x33); + + for (n = 0; n < 2; n++) { + const struct nvt_mac *m = &nvt_macs[n]; + phy_interface_t intf; + char name[8]; + + writel(0x3FF, ETH_LED_CTRL(m->base)); + if (fdt && fdt_path_offset(fdt, m->node) < 0) + continue; + if (pins & ETH_RMII(n)) + intf = PHY_INTERFACE_MODE_RMII; + else if (pins & ETH_RGMII(n)) + intf = PHY_INTERFACE_MODE_RGMII; + else if (pins & ETH_EMB_PHY(n)) + intf = PHY_INTERFACE_MODE_MII; + else + continue; + + if (intf == PHY_INTERFACE_MODE_MII) { + if (n == 0) + clrsetbits_le32(TOP_EMB_PHY, 0xf << 4, BIT(0)); + else + clrbits_le32(TOP_EMB_PHY, 0xf << 8 | BIT(0)); + } else { + nvt_mac_pins(n, intf); + } + nvt_mac_clocks(m, intf); + nvt_mac_phy(fdt, m, intf); + + /* MDC: the CSR clock is the 150 MHz APB, CR 1 (/62) */ + snprintf(name, sizeof(name), "eth%d", n); + if (!nvt_eqos_register(name, m->base, intf, 1)) + ret++; + } + return ret; +} +#endif + +#ifdef CONFIG_MMC_SDHCI +/* + * The SD card: a standard SDHCI 3.0 at 0xFA600000 (the vendor's + * nvt_ivot_sdc021.c), 4-bit, its base clock from its capabilities, up to + * the device tree's max-frequency. Its pins as /top@fe030000/sdio pinmux + * says: 0x10 the first pad set, 0x20 the second (the SDK's boards). + */ +#define SDIO_PINS_1ST BIT(4) +#define SDIO_PINS_2ND BIT(5) + +int board_mmc_init(struct bd_info *bis) +{ + const void *fdt = nvt_loader_fdt(); + u32 pins = nvt_fdt_u32(fdt, "/top@fe030000/sdio", "pinmux", + SDIO_PINS_2ND); + u32 max_hz = nvt_fdt_u32(fdt, "/mmc@fa600000", "max-frequency", + 12000000); + struct sdhci_host *host; + + if (!(pins & (SDIO_PINS_1ST | SDIO_PINS_2ND))) + return 0; + setbits_le32(CG(0x54), BIT(10)); /* out of reset */ + clrbits_le32(CG(0x68), BIT(10)); /* clock on */ + clrbits_le32(CG(0x18C), 0x3f << 8); /* the clock undivided */ + /* Pins, and pull-ups on the data and command lines */ + if (pins & SDIO_PINS_1ST) { + clrsetbits_le32(TOP(0x28), 0xf << 28, BIT(28) | BIT(30)); + clrsetbits_le32(TOP(0x2C), 0xf | 0xf << 28, + 0x5 | BIT(28) | BIT(30)); + clrsetbits_le32(TOP(0x30), 0xfff | 0xf << 16, + 0x555 | BIT(16) | BIT(18)); + clrsetbits_le32(PAD(0x04), 0xf << 14 | 0x3 << 30, + BIT(15) | BIT(17) | BIT(31)); + clrsetbits_le32(PAD(0x08), 0x33f, BIT(1) | BIT(3) | BIT(5) | + BIT(9)); + } else { + clrsetbits_le32(TOP(0x2C), 0x770, 0x550); + clrsetbits_le32(TOP(0x40), 0x77700000, 0x66600000); + clrsetbits_le32(TOP(0x44), 0x77, 0x66); + clrsetbits_le32(PAD(0x04), 0xf << 18, BIT(19) | BIT(21)); + clrsetbits_le32(PAD(0x10), 0x3ff << 10, BIT(11) | BIT(13) | + BIT(15) | BIT(17) | BIT(19)); + } + + host = calloc(1, sizeof(*host)); + if (!host) + return -ENOMEM; + host->name = "sdhci"; + host->ioaddr = (void *)NVT_SDHCI_BASE; + host->host_caps = MMC_MODE_4BIT; + return add_sdhci(host, max_hz, 400000); +} +#endif diff --git a/board/novatek/na51068/u-boot.lds b/board/novatek/na51068/u-boot.lds new file mode 100644 index 000000000000..f781f4533b51 --- /dev/null +++ b/board/novatek/na51068/u-boot.lds @@ -0,0 +1,249 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * arch/arm/cpu/u-boot.lds with the HEADINFO of the Novatek NA51068 + * loader at 0x300. + * + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + */ + +#include +#include + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ +#ifndef CONFIG_CMDLINE + /DISCARD/ : { *(__u_boot_list_2_cmd_*) } +#endif +#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) + /* + * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not + * bundle with u-boot, and code offsets are fixed. Secure zone + * only needs to be copied from the loading address to + * CONFIG_ARMV7_SECURE_BASE, which is the linking and running + * address for secure code. + * + * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will + * be included in u-boot address space, and some absolute address + * were used in secure code. The absolute addresses of the secure + * code also needs to be relocated along with the accompanying u-boot + * code. + * + * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. + */ + /DISCARD/ : { *(.rel._secure*) } +#endif + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + /* + * The Novatek loader looks for the image's HEADINFO here: + * where to start it and how long it is, with a checksum. + */ + . = 0x300; + KEEP(*(.nvt_headinfo)) + CPUDIR/start.o (.text*) + } + + /* This needs to come before *(.text*) */ + .__efi_runtime_start : { + *(.__efi_runtime_start) + } + + .efi_runtime : { + *(.text.efi_runtime*) + *(.rodata.efi_runtime*) + *(.data.efi_runtime*) + } + + .__efi_runtime_stop : { + *(.__efi_runtime_stop) + } + + .text_rest : + { + *(.text*) + } + +#ifdef CONFIG_ARMV7_NONSEC + + /* Align the secure section only if we're going to use it in situ */ + .__secure_start +#ifndef CONFIG_ARMV7_SECURE_BASE + ALIGN(CONSTANT(COMMONPAGESIZE)) +#endif + : { + KEEP(*(.__secure_start)) + } + +#ifndef CONFIG_ARMV7_SECURE_BASE +#define CONFIG_ARMV7_SECURE_BASE +#define __ARMV7_PSCI_STACK_IN_RAM +#endif + + .secure_text CONFIG_ARMV7_SECURE_BASE : + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) + { + *(._secure.text) + } + + .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) + { + *(._secure.data) + } + +#ifdef CONFIG_ARMV7_PSCI + .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data), + CONSTANT(COMMONPAGESIZE)) (NOLOAD) : +#ifdef __ARMV7_PSCI_STACK_IN_RAM + AT(ADDR(.secure_stack)) +#else + AT(LOADADDR(.secure_data) + SIZEOF(.secure_data)) +#endif + { + KEEP(*(.__secure_stack_start)) + + /* Skip addreses for stack */ + . = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; + + /* Align end of stack section to page boundary */ + . = ALIGN(CONSTANT(COMMONPAGESIZE)); + + KEEP(*(.__secure_stack_end)) + +#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE + /* + * We are not checking (__secure_end - __secure_start) here, + * as these are the load addresses, and do not include the + * stack section. Instead, use the end of the stack section + * and the start of the text section. + */ + ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE, + "Error: secure section exceeds secure memory size"); +#endif + } + +#ifndef __ARMV7_PSCI_STACK_IN_RAM + /* Reset VMA but don't allocate space if we have secure SRAM */ + . = LOADADDR(.secure_stack); +#endif + +#endif + + .__secure_end : AT(ADDR(.__secure_end)) { + *(.__secure_end) + LONG(0x1d1071c); /* Must output something to reset LMA */ + } +#endif + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); + } + + . = ALIGN(4); + + .efi_runtime_rel_start : + { + *(.__efi_runtime_rel_start) + } + + .efi_runtime_rel : { + *(.rel*.efi_runtime) + *(.rel*.efi_runtime.*) + } + + .efi_runtime_rel_stop : + { + *(.__efi_runtime_rel_stop) + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu.hash : { *(.gnu.hash) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } + .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } +} diff --git a/board/novatek/na51089/na51089.c b/board/novatek/na51089/na51089.c index b507611259c6..9c358c450fad 100644 --- a/board/novatek/na51089/na51089.c +++ b/board/novatek/na51089/na51089.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Novatek NA51089 camera board: the device tree the loader hands over, - * and the memory split the vendor kernels expect in it. + * Novatek NA51089, NA51055, NA51084 and NS02501 camera boards: the device + * tree the loader hands over, and the memory split the vendor kernels + * expect in it. */ #include @@ -38,8 +39,26 @@ DECLARE_GLOBAL_DATA_PTR; #define CG_PLL8 BIT(8) /* the CPU's PLL */ #define CG_CLK_SWITCH (NVT_CG_BASE + 0xA0) #define CG_CLKEN_70 (NVT_CG_BASE + 0x70) -#define CG_PLL8_RATIO(n) (NVT_CG_BASE + 0x4420 + 4 * (n)) #define OTP_TIMING 0xF0660010 +#define OTP_TIMING_120 0xFF6050 /* at a 120 MHz APB */ +#define CG_OTP_RSTN BIT(28) /* NS02501, in RSTN0 */ + +/* + * PLL8's ratio, three bytes in three words: only where they are differs + * between the dies (NT9852x SDK: arch/arm/mach-novatek/nvt_na51055_a32/ + * clock.c, CPU_CLOCK_RATE_RATIO*_OFS and *_528_OFS). + */ +static ulong nvt_pll8_ratio(void) +{ + switch (nvt_chip_id()) { + case NVT_CHIP_NA51055: + return NVT_CG_BASE + 0x1188; + case NVT_CHIP_NA51084: + return NVT_CG_BASE + 0x47E0; + default: + return NVT_CG_BASE + 0x4420; + } +} /* Wait 100 ms for (reg & mask) != 0; the vendor waits for ever */ static int nvt_wait_set(ulong reg, u32 mask) @@ -64,12 +83,40 @@ static void nvt_cpu_clk_sel(u32 sel) writel(0x28, CG_CLK_SWITCH); } -/* The vendor's nvt_cpu_freq: 80, 480, or anything else as 960 MHz */ +/* + * PLL8's ratio for a CPU clock, 12 MHz * ratio / 2^17: NA51084's own + * rates (1000 MHz unless the tree asks for 1200 or 1350, which only the + * NT98529 is cleared for; the vendor checks that in the eFuse, here the + * target does), else 960 MHz. + */ +static u32 nvt_pll8_for(u32 mhz) +{ + if (nvt_chip_id() != NVT_CHIP_NA51084) + return 0xA00000; + if (!IS_ENABLED(CONFIG_TARGET_NT98529) && mhz > 1000) + mhz = 1000; + switch (mhz) { + case 1200: + return 0x190000; + case 1350: + return 0x1C2000; + default: + return 0x14D555; + } +} + +/* + * The vendor's nvt_cpu_freq: 480 MHz (and 80 on NA51089) from fixed + * sources, anything else from PLL8 (nvt_pll8_for()) + */ static void nvt_set_cpu_mhz(u32 mhz) { u32 sel = readl(CG_SYSCLK) & SYSCLK_CPU; + ulong ratio = nvt_pll8_ratio(); + u32 pll8; - if (mhz == 80 || mhz == 480) { + if (mhz == 480 || + (mhz == 80 && nvt_chip_id() == NVT_CHIP_NA51089)) { u32 want = mhz == 80 ? SYSCLK_CPU_80 : SYSCLK_CPU_480; if (sel == want) @@ -87,10 +134,10 @@ static void nvt_set_cpu_mhz(u32 mhz) } nvt_cpu_clk_sel(SYSCLK_CPU_PLL8); } - /* 960 MHz: 12 MHz * 0xA00000 / 2^17 */ - writel(0x00, CG_PLL8_RATIO(0)); - writel(0x00, CG_PLL8_RATIO(1)); - writel(0xA0, CG_PLL8_RATIO(2)); + pll8 = nvt_pll8_for(mhz); + writel(pll8 & 0xff, ratio); + writel((pll8 >> 8) & 0xff, ratio + 4); + writel(pll8 >> 16, ratio + 8); } /* The eFuse controller's timing for the APB clock it runs at */ @@ -134,14 +181,39 @@ static void nvt_set_clocks(void) val = fdt_getprop(fdt, node, "clock-frequency", NULL); if (val) nvt_set_cpu_mhz(fdt32_to_cpu(*val) / 1000000); - /* Sic, as the vendor spells it */ - val = fdt_getprop(fdt, node, "apb-frequenccy", NULL); + /* The NT9852x SDK's spelling, or NA51089's vendor U-Boot's */ + val = fdt_getprop(fdt, node, "apb-frequency", NULL); + if (!val) + val = fdt_getprop(fdt, node, "apb-frequenccy", NULL); if (val) nvt_set_apb_mhz(fdt32_to_cpu(*val) / 1000000); } +/* + * NS02501 (the NT98532/533 SDK's ns02501_hw_init.c, nvt-otp.c): the eFuse + * controller's 120 MHz timing and its reset held, the AXI bridge + * timeouts. Its otp_init() then waits 800 ms for a customer's eFuse + * power-down, not done; its USB PHY set-up is compiled out, and its pad + * power set-up reads /top nodes these trees do not have. The CPU clock + * stays as the loader set it: the vendor's nvt_cpu_freq caps it at + * 800 MHz unless an eFuse code allows more, and the trees ask for 800 + * (and for no APB clock). + */ +static void nvt_ns02501_init(void) +{ + writel(OTP_TIMING_120, OTP_TIMING); + clrbits_le32(NVT_CG_RSTN0, CG_OTP_RSTN); + writel(0x7c, 0xF0012018); + writel(0x7c, 0xF0013018); +} + int board_init(void) { + if (IS_ENABLED(CONFIG_NVT_NS02501)) { + nvt_ns02501_init(); + return 0; + } + /* nvt_ivot_hw_init_early() */ nvt_otp_timing(); clrbits_le32(CG_CLKEN_70, BIT(16)); @@ -262,13 +334,17 @@ void board_lmb_reserve(struct lmb *lmb) /* * As the vendor U-Boot's nvt_boot: Linux gets the first ${osmem} of the * DDR, and the media pool of the vendor modules (/hdal-memory/media) the - * rest. + * rest. A second DDR die the tree gives the pool (NA51055 / NA51084: + * <0x40000000 ...> after the first range) stays the pool's. The ranges + * are in /hdal-memory's cells: one each on NA51089 and NA51055; on + * NS02501 two address cells, [DDR id][address], so <0 address size>. */ int ft_board_setup(void *blob, struct bd_info *bd) { ulong osmem = nvt_osmem(); - fdt32_t media[2]; - int node, ret; + const fdt32_t *old; + fdt32_t media[16] = { 0 }; + int node, len, i, j, ac, sc, w, n, ret; ret = fdt_fixup_memory(blob, NVT_DDR_BASE, osmem); if (ret) @@ -277,19 +353,39 @@ int ft_board_setup(void *blob, struct bd_info *bd) node = fdt_path_offset(blob, "/hdal-memory/media"); if (node < 0) return 0; - media[0] = cpu_to_fdt32(NVT_DDR_BASE + osmem); - media[1] = cpu_to_fdt32(gd->ram_size - osmem); - return fdt_setprop(blob, node, "reg", media, sizeof(media)); + ac = fdt_address_cells(blob, fdt_parent_offset(blob, node)); + sc = fdt_size_cells(blob, fdt_parent_offset(blob, node)); + w = ac + sc; + if (ac < 1 || sc < 1 || w > 4) + return -FDT_ERR_BADNCELLS; + media[ac - 1] = cpu_to_fdt32(NVT_DDR_BASE + osmem); + media[w - 1] = cpu_to_fdt32(gd->ram_size - osmem); + n = w; + old = fdt_getprop(blob, node, "reg", &len); + for (i = 0; old && i + w <= len / 4 && n + w <= ARRAY_SIZE(media); + i += w) { + /* The first die's range: replaced by the one above */ + for (j = 0; j < ac - 1 && !old[i + j]; j++) + ; + if (j == ac - 1 && + fdt32_to_cpu(old[i + ac - 1]) < NVT_DDR_BASE + gd->ram_size) + continue; + memcpy(&media[n], &old[i], w * sizeof(media[0])); + n += w; + } + return fdt_setprop(blob, node, "reg", media, n * sizeof(media[0])); } #ifdef CONFIG_NVT_EQOS /* * Ethernet: the pins, clocks and embedded PHY around the MAC - * (drivers/net/nvt_eqos.c), set up as by the vendor U-Boot's - * eth_na51089.c. How the board is wired comes from the loader's device + * (drivers/net/nvt_eqos.c), set up as by the vendor U-Boots' + * eth_na51089.c and, on the NT9852x dies, eth_na51055.c, on NS02501 + * eth_ns02501.c. How the board is wired comes from the loader's device * tree, which the vendor kernels read too: /top@f0010000/eth pinmux. - * Xiongmai boards say 0x22, the embedded PHY with its LEDs on the second - * pads. + * Xiongmai NT98562 boards say 0x22, the embedded PHY with its LEDs on the + * second pads; the NT9852x SDK's boards 0x12, on the first; the NS02501 + * SDK's boards 0, the embedded PHY. */ #define ETH_PIN_RMII BIT(0) /* an external PHY on the LCD pads */ #define ETH_PIN_INTERNAL BIT(1) /* the embedded PHY */ @@ -297,12 +393,17 @@ int ft_board_setup(void *blob, struct bd_info *bd) #define ETH_PIN_LED2 BIT(5) /* or the second */ #define ETH_PIN_RMII_2 BIT(6) /* an external PHY on the P pads */ #define ETH_PIN_LED_ONLY (3 << 10) /* one LED: the pair's 1st, 2nd */ +/* The NT9852x dies' bits where they differ (eth_na51055.c PIN_ETH_CFG_*) */ +#define ETH52X_RGMII BIT(7) /* NA51084 */ +#define ETH52X_LED_ONLY (3 << 8) +#define TOP_PINMUX_ETH84 (NVT_TOP_BASE + 0x10) /* NA51084 [9:8] */ #define TOP_PINMUX_ETH (NVT_TOP_BASE + 0x14) /* RMII [3:2] [31:30] */ #define TOP_PINMUX_MISC (NVT_TOP_BASE + 0x18) #define MISC_PHY_LED(n) ((n) << 13) /* LED pair 1, 2 */ #define MISC_PHY_CLK BIT(28) /* 25 MHz out to a PHY */ #define TOP_GPIO_P (NVT_TOP_BASE + 0xA8) /* pads as GPIO */ +#define TOP_GPIO_L (NVT_TOP_BASE + 0xB8) /* NT9852x: the MAC's */ #define TOP_GPIO_DSI (NVT_TOP_BASE + 0xD0) #define TOP_GPIO_LCD (NVT_TOP_BASE + 0xE8) #define TOP_SRAM_SD (NVT_TOP_BASE + 0x1000) @@ -317,6 +418,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) #define ETH_PLL_RSTN (NVT_ETH_BASE + 0x84) /* [31:30] */ #define ETH_PHY_SEL (NVT_ETH_BASE + 0x3004) #define PHY_SEL_EXT BIT(4) +#define PHY_SEL_EXT_MASK (3 << 4) /* NA51089, NS02501 */ +#define PHY_SEL_EXT_52X BIT(8) +#define CG_PLL16 BIT(16) #define ETH_LED_CTRL (NVT_ETH_BASE + 0x300C) #define LED_INV (3 << 8) #define ETH_RMII_CLK (NVT_ETH_BASE + 0x3014) @@ -324,10 +428,15 @@ int ft_board_setup(void *blob, struct bd_info *bd) #define RMII_REF_OUT BIT(4) #define RMII_REF_CLK_I BIT(5) #define RMII_TXD_SRC (3 << 30) +#define TXD_SRC_RGMII (1 << 30) #define PHY(off) (NVT_ETH_PHY_BASE + (off)) #define PHY_CTRL PHY(0x000) #define PHY_SW_RESET BIT(1) #define PHY_PLLREGWR BIT(3) +#define PHY_MDIO_ADDR PHY(0x01C) +#define PHY_TRIM_SEL PHY(0x368) /* [7:5] RX, [4:2] TX */ +#define PHY_TRIM_ROUT PHY(0x374) /* [5:3]; [2:0] T22 */ +#define PHY_TRIM_DAC PHY(0x378) /* [4:0] */ int nvt_eqos_initialize(phy_interface_t intf); @@ -379,14 +488,19 @@ static void nvt_eth_rmii(const void *fdt, u32 pins) /* The vendor resets the PHY on an EVB GPIO here, not done */ } -/* The embedded PHY: PLL out of reset, power on, then its own reset */ +/* + * The embedded PHY: on NA51089 its PLL out of reset first; power on, then + * its own reset + */ static void nvt_eth_phy_on(u32 led) { - mdelay(20); - clrbits_le32(ETH_PLL_RSTN, 3 << 30); - mdelay(20); - setbits_le32(ETH_PLL_RSTN, 3 << 30); - mdelay(20); + if (nvt_chip_id() == NVT_CHIP_NA51089) { + mdelay(20); + clrbits_le32(ETH_PLL_RSTN, 3 << 30); + mdelay(20); + setbits_le32(ETH_PLL_RSTN, 3 << 30); + mdelay(20); + } setbits_le32(PHY(0xF8), BIT(7)); udelay(20); @@ -399,6 +513,24 @@ static void nvt_eth_phy_on(u32 led) setbits_le32(PHY(0xDC), BIT(0)); clrbits_le32(PHY(0x9C), BIT(0)); + /* + * NS02501 (eth_ns02501.c extphy0_clk_en()): the PHY's MDIO + * address, 1, and its analog trims. The vendor takes the trims + * from the eFuse through its closed reader; these are its + * defaults for a part without them (TX ROUT 0, DAC 0, SEL RX and + * TX 3), and its "best setting" T22 of 5. Linux's driver keeps + * what it finds there. + */ + if (IS_ENABLED(CONFIG_NVT_NS02501)) { + setbits_le32(PHY_CTRL, PHY_SW_RESET); + setbits_le32(PHY_MDIO_ADDR, 1); + clrbits_le32(PHY_CTRL, PHY_SW_RESET); + clrbits_le32(PHY_TRIM_ROUT, 7 << 3); + clrbits_le32(PHY_TRIM_DAC, 0x1f); + clrsetbits_le32(PHY_TRIM_SEL, 0xfc, 3 << 5 | 3 << 2); + clrsetbits_le32(PHY_TRIM_ROUT, 7, 5); + } + setbits_le32(PHY_CTRL, PHY_SW_RESET); /* The break-link timer, and the LED mode, as the vendor */ writel(0x53, PHY(0x288)); @@ -410,12 +542,190 @@ static void nvt_eth_phy_on(u32 led) clrsetbits_le32(PHY_CTRL, PHY_SW_RESET, PHY_PLLREGWR); } +/* The NT9852x dies' (eth_na51055.c: its pin, clock and PHY set-up) */ +static int nvt_eth_init_52x(const void *fdt, u32 pins) +{ + bool na51084 = nvt_chip_id() == NVT_CHIP_NA51084; + u32 ext = ETH_PIN_RMII | + (na51084 ? ETH_PIN_RMII_2 | ETH52X_RGMII : 0); + bool phy_clk = nvt_fdt_u32(fdt, "/eth@f02b0000", "sp-clk", 0); + u32 led = 0x312, pads = 3; /* both LEDs, blinking */ + int n = pins & ETH_PIN_LED1 ? 1 : pins & ETH_PIN_LED2 ? 2 : 0; + phy_interface_t intf = PHY_INTERFACE_MODE_MII; + + if (!(pins & (ext | ETH_PIN_INTERNAL))) + return 0; + + if (n) { + if (pins & ETH52X_LED_ONLY) { + pads = pins & BIT(8) ? 1 : 2; + led = 0x300; + } + clrbits_le32(TOP_GPIO_DSI, n == 1 ? pads : pads << 5); + clrsetbits_le32(TOP_PINMUX_MISC, MISC_PHY_LED(3), + MISC_PHY_LED(n)); + } + if (nvt_fdt_u32(fdt, "/phy@f02b3800", "led-inv", 0)) + led &= ~LED_INV; + + /* mac_pinmux_en() */ + if (!na51084) { + if (pins & ETH_PIN_RMII) { + setbits_le32(TOP_PINMUX_MISC, 0x3000); + clrbits_le32(TOP_GPIO_L, 0x40077f); + } + } else if (pins & ETH_PIN_RMII) { + setbits_le32(TOP_PINMUX_ETH84, 0x100); + clrbits_le32(TOP_GPIO_L, 0x40077f); + } else if (pins & ETH_PIN_RMII_2) { + setbits_le32(TOP_PINMUX_ETH84, 0x200); + clrbits_le32(TOP_GPIO_L, 0x18f3800); + } else if (pins & ETH52X_RGMII) { + setbits_le32(TOP_PINMUX_ETH84, 0x300); + clrbits_le32(TOP_GPIO_L, 0x1fff800); + } + if (pins & ETH_PIN_INTERNAL) { + clrbits_le32(TOP_PINMUX_MISC, MISC_PHY_CLK); + } else if (phy_clk) { + setbits_le32(TOP_PINMUX_MISC, MISC_PHY_CLK); + if (na51084 && !(pins & ETH_PIN_RMII)) + clrbits_le32(TOP_GPIO_DSI, BIT(0)); + else + clrbits_le32(TOP_GPIO_L, BIT(7)); + } + + /* mac_clk_en(): NA51084's embedded PHY runs from 480 MHz */ + if (!na51084) + setbits_le32(CG_PLL_EN, CG_PLL6); + else if (!(pins & ETH_PIN_INTERNAL)) + setbits_le32(CG_PLL_EN, CG_PLL16); + udelay(10); + setbits_le32(NVT_CG_CLKEN0, CG_ETH); + udelay(10); + setbits_le32(NVT_CG_RSTN0, CG_ETH); + udelay(10); + clrbits_le32(TOP_SRAM_SD, SRAM_SD_ETH); + + /* extphy_clk_en() */ + if (pins & ETH52X_RGMII & ext) { + clrsetbits_le32(ETH_RMII_CLK, RMII_TXD_SRC, + RMII_REF_OUT | TXD_SRC_RGMII); + intf = PHY_INTERFACE_MODE_RGMII; + } else if (pins & ext) { + clrsetbits_le32(ETH_RMII_CLK, + RMII_REF_IN | RMII_REF_OUT | + (na51084 ? RMII_TXD_SRC : 0), + RMII_REF_CLK_I | + (nvt_fdt_u32(fdt, "/eth@f02b0000", "ref-clk-out", + 0) ? RMII_REF_OUT : RMII_REF_IN)); + intf = PHY_INTERFACE_MODE_RMII; + } + if (pins & ext) { + setbits_le32(ETH_PHY_SEL, PHY_SEL_EXT_52X); + if (phy_clk) { + setbits_le32(CG_CLKEN2, CG_ETH_PHY_CLK); + setbits_le32(TOP_PINMUX_MISC, MISC_PHY_CLK); + clrbits_le32(TOP_GPIO_L, BIT(7)); + } + /* The vendor resets the PHY on an EVB GPIO here, not done */ + } else { + clrbits_le32(ETH_PHY_SEL, PHY_SEL_EXT_52X); + } + /* Powered either way, as by eqos_probe_hwinit() */ + nvt_eth_phy_on(led); + + return nvt_eqos_initialize(intf); +} + +/* + * NS02501 (eth_ns02501.c: mac0_pinmux_en(), mac0_clk_en(), + * extphy0_clk_en()). Its pinmux bits are its own: RMII on the DSI pads + * (0x1) or the P pads (0x2), the PHY's 25 MHz from the SoC (0x100); + * anything else is the embedded PHY. The vendor muxes no LED pins and + * has no RGMII on this die. + */ +#define ETH02501_RMII_1 BIT(0) +#define ETH02501_RMII_2 BIT(1) +#define ETH02501_EXTPHYCLK BIT(8) +#define TOP_GPIO_DSI_02501 (NVT_TOP_BASE + 0xC8) +#define PAD_DRV_DSI_02501 (NVT_PAD_BASE + 0x44) +#define PAD_DRV_P_02501 (NVT_PAD_BASE + 0x30) +#define RMII_REF_PAD BIT(2) + +static int nvt_eth_init_ns02501(const void *fdt, u32 pins) +{ + int rmii = pins & ETH02501_RMII_1 ? 1 : pins & ETH02501_RMII_2 ? 2 : 0; + bool phy_clk = nvt_fdt_u32(fdt, "/eth0@f02b0000", "sp-clk", 0) || + (pins & ETH02501_EXTPHYCLK); + bool ref_out = nvt_fdt_u32(fdt, "/eth0@f02b0000", "ref-clk-out", 0); + + /* The RMII pins, their drive at level 1 */ + if (rmii == 1) { + /* PHYCLK, TXCTL, TXD0, TXD1, RXCLK */ + clrsetbits_le32(PAD_DRV_DSI_02501, 0x3fcc00, 0x154400); + clrsetbits_le32(TOP_PINMUX_ETH, 3 << 30, 1 << 30); + clrbits_le32(TOP_GPIO_DSI_02501, 0x3bf); + } else if (rmii == 2) { + clrsetbits_le32(PAD_DRV_P_02501, 0xc3003f, 0x410015); + clrsetbits_le32(TOP_PINMUX_ETH, 3 << 30, 2 << 30); + clrbits_le32(TOP_GPIO_P, 0x73f); + } + + setbits_le32(CG_PLL_EN, CG_PLL6); + udelay(10); + setbits_le32(NVT_CG_CLKEN0, CG_ETH); + udelay(10); + setbits_le32(NVT_CG_RSTN0, CG_ETH); + udelay(10); + + if (rmii) { + /* The reference clock from the pad, or out to the PHY */ + clrsetbits_le32(ETH_RMII_CLK, + RMII_REF_IN | RMII_REF_OUT | RMII_REF_PAD | + RMII_TXD_SRC, + RMII_REF_CLK_I | + (ref_out ? RMII_REF_OUT : RMII_REF_IN)); + setbits_le32(ETH_PHY_SEL, PHY_SEL_EXT); + } else { + /* + * The vendor sets bit 4 for the external PHY (as on NA51089) + * but clears bit 8 (as on NT9852x) for the embedded one: + * clear both + */ + clrbits_le32(ETH_PHY_SEL, PHY_SEL_EXT_MASK | PHY_SEL_EXT_52X); + nvt_eth_phy_on(0x312); + } + if (phy_clk) { + setbits_le32(CG_CLKEN2, CG_ETH_PHY_CLK); + if (rmii) { + setbits_le32(TOP_PINMUX_MISC, MISC_PHY_CLK); + setbits_le32(TOP_PINMUX_ETH, rmii << 2); + if (rmii == 1) + clrbits_le32(TOP_GPIO_DSI_02501, BIT(10)); + else + clrbits_le32(TOP_GPIO_P, BIT(11)); + } + } + /* + * The vendor resets an external PHY on DSI_GPIO 6 (RMII_1) or + * P_GPIO 7 (RMII_2) here, its EVB's wiring: not done + */ + + return nvt_eqos_initialize(rmii ? PHY_INTERFACE_MODE_RMII : + PHY_INTERFACE_MODE_MII); +} + int board_eth_init(struct bd_info *bis) { const void *fdt = (const void *)env_get_hex("fdtaddr", 0); u32 pins = nvt_fdt_u32(fdt, "/top@f0010000/eth", "pinmux", ETH_PIN_INTERNAL); bool rmii = pins & (ETH_PIN_RMII | ETH_PIN_RMII_2); + + if (IS_ENABLED(CONFIG_NVT_NS02501)) + return nvt_eth_init_ns02501(fdt, pins); + if (nvt_chip_id() != NVT_CHIP_NA51089) + return nvt_eth_init_52x(fdt, pins); u32 led = 0x312, pads = 3; /* both LEDs, blinking */ int n = pins & ETH_PIN_LED1 ? 1 : pins & ETH_PIN_LED2 ? 2 : 0; diff --git a/board/novatek/na511xx/Makefile b/board/novatek/na511xx/Makefile new file mode 100644 index 000000000000..aaefc8cc89a1 --- /dev/null +++ b/board/novatek/na511xx/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += na511xx.o diff --git a/board/novatek/na511xx/na511xx.c b/board/novatek/na511xx/na511xx.c new file mode 100644 index 000000000000..d0705e4bf8eb --- /dev/null +++ b/board/novatek/na511xx/na511xx.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Novatek NA51103 (NT98332) / NA51090 (NT98633) NVR boards: the device + * tree the loader hands over, the memory split the vendor kernels expect + * in it, and the Ethernet set-up. + * + * The boot chain is the board's own up to here: the mask ROM, the board's + * loader (DDR training), its BL31 (TF-A v2.2), which enters U-Boot in + * AArch64 at EL2 and stays resident at 0x1F00000 for PSCI. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +/* + * The loader leaves its device tree, which describes the board for the + * vendor kernels, in DDR and its address in SHMINFO. OpenIPC uImages carry + * no device tree, so bootm passes this one (${fdtaddr}). It lies where the + * kernel is put (0x80000 on), so it is copied away first. + */ +static void nvt_fdt_init(void) +{ + const void *fdt = nvt_loader_fdt(); + void *copy; + + if (!fdt) { + printf("FDT: no device tree from the loader\n"); + return; + } + copy = malloc(fdt_totalsize(fdt)); + if (!copy) + return; + memcpy(copy, fdt, fdt_totalsize(fdt)); + env_set_hex("fdtaddr", (ulong)copy); +} + +int misc_init_r(void) +{ + int ret = openipc_helper(); + + /* After the helper's first saveenv: the address is this boot's */ + nvt_fdt_init(); + return ret; +} + +/* + * U-Boot relocates to the top of the loader's region for it + * (/nvt_memory_cfg/uboot), as the vendor U-Boot does, not to the top of + * the DDR. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + return NVT_UBOOT_BASE + NVT_UBOOT_SIZE; +} + +/* What Linux gets of the DDR (mem=); the vendor media modules get the rest */ +static ulong nvt_osmem(void) +{ + char *end; + ulong osmem = ustrtoul(env_get("osmem") ?: "", &end, 0); + + if (!osmem || osmem > gd->ram_size) + osmem = gd->ram_size; + return osmem; +} + +/* Reserve [lo, hi) where lmb has nothing yet: it refuses overlaps */ +static void nvt_lmb_reserve_gaps(struct lmb *lmb, phys_addr_t lo, + phys_addr_t hi) +{ + struct lmb_property rsv[8]; + unsigned long i, n = min_t(unsigned long, lmb->reserved.cnt, + ARRAY_SIZE(rsv)); + + /* A copy: the reservations below insert into the sorted list */ + memcpy(rsv, &lmb->reserved.region[0], n * sizeof(rsv[0])); + for (i = 0; i < n && lo < hi; i++) { + phys_addr_t base = rsv[i].base; + phys_addr_t end = base + rsv[i].size; + + if (end <= lo || base >= hi) + continue; + if (base > lo) + lmb_reserve(lmb, lo, base - lo); + lo = max(lo, end); + } + if (lo < hi) + lmb_reserve(lmb, lo, hi - lo); +} + +/* + * The device tree and initrd go where Linux can reach them: everything + * past ${osmem} is reserved. BL31's secure megabyte is the tree's + * /reserved-memory, which bootm reserves itself. + */ +void board_lmb_reserve(struct lmb *lmb) +{ + nvt_lmb_reserve_gaps(lmb, NVT_DDR_BASE + nvt_osmem(), + NVT_DDR_BASE + gd->ram_size); +} + +/* Write a reg in the cells of the node's parent */ +static int nvt_set_reg(void *blob, int node, u64 base, u64 size) +{ + int parent = fdt_parent_offset(blob, node); + int ac = fdt_address_cells(blob, parent); + int sc = fdt_size_cells(blob, parent); + fdt32_t reg[8]; + int i; + + if (ac < 1 || sc < 1 || ac + sc > ARRAY_SIZE(reg)) + return -FDT_ERR_BADNCELLS; + /* Values in the low cells; the vendor's 4-cell addresses lead with 0 */ + for (i = 0; i < ac; i++) + reg[i] = cpu_to_fdt32(i == ac - 1 ? (u32)base : + i == ac - 2 ? (u32)(base >> 32) : 0); + for (i = 0; i < sc; i++) + reg[ac + i] = cpu_to_fdt32(i == sc - 1 ? (u32)size : + i == sc - 2 ? (u32)(size >> 32) : 0); + return fdt_setprop(blob, node, "reg", reg, (ac + sc) * sizeof(reg[0])); +} + +/* + * As the vendor U-Boot's nvt_boot: Linux gets the first ${osmem} of the + * DDR, and the media pool of the vendor modules (/hdal-memory/media) the + * rest. The tree keeps BL31 out of Linux's reach itself + * (/reserved-memory, no-map). + */ +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ulong osmem = nvt_osmem(); + int node, ret; + + ret = fdt_fixup_memory(blob, NVT_DDR_BASE, osmem); + if (ret) + return ret; + + node = fdt_path_offset(blob, "/hdal-memory/media"); + if (node < 0) + return 0; + return nvt_set_reg(blob, node, NVT_DDR_BASE + osmem, + gd->ram_size - osmem); +} + +#ifdef CONFIG_NVT_EQOS +static u32 nvt_fdt_u32(const void *fdt, const char *path, const char *prop, + u32 def) +{ + const fdt32_t *val = NULL; + int node; + + if (fdt) { + node = fdt_path_offset(fdt, path); + if (node >= 0) + val = fdt_getprop(fdt, node, prop, NULL); + } + return val ? fdt32_to_cpu(*val) : def; +} + +int nvt_eqos_initialize(phy_interface_t intf); + +/* + * /top/eth pinmux in the loader's tree (the vendor's PIN_ETH_CFG): how + * the first MAC is wired + */ +#define ETH_PIN_RGMII BIT(0) /* an RGMII PHY on the first pads */ +#define ETH_PIN_RMII BIT(4) /* an RMII PHY on the first pads */ +#define ETH_PIN_REFCLK BIT(8) /* the PHY's 25 MHz from the SoC */ +#define ETH_PIN_RST BIT(9) /* the PHY's reset on E_GPIO 1 */ + +#define TOP(off) (NVT_TOP_BASE + (off)) +#define CG(off) (NVT_CG_BASE + (off)) +#define PAD(off) (NVT_PAD_BASE + (off)) +#define GLUE(off) (NVT_ETH_BASE + 0x3000 + (off)) +#define EPHY(off) (NVT_ETH_BASE + 0x3800 + (off)) + +#define GPIO_DIR(n) (NVT_GPIO_BASE + 0x30 + ((n) >> 5) * 4) +#define GPIO_SET(n) (NVT_GPIO_BASE + 0x60 + ((n) >> 5) * 4) +#define GPIO_CLR(n) (NVT_GPIO_BASE + 0x90 + ((n) >> 5) * 4) +#ifdef CONFIG_NVT_NA51090 +#define E_GPIO(n) (0x80 + (n)) +#define S_GPIO(n) (0xC0 + (n)) +#else +#define E_GPIO(n) (0x60 + (n)) +#endif + +/* A GPIO as an output, at @val */ +static void nvt_gpio_out(unsigned int n, int val) +{ + writel(BIT(n & 31), val ? GPIO_SET(n) : GPIO_CLR(n)); + setbits_le32(GPIO_DIR(n), BIT(n & 31)); +} + +/* The PHY's reset: low for 10 ms, then 50 ms before MDIO, as the vendor */ +static void nvt_phy_reset(unsigned int gpio) +{ + nvt_gpio_out(gpio, 0); + mdelay(10); + nvt_gpio_out(gpio, 1); + mdelay(50); +} + +#ifdef CONFIG_NVT_NA51103 + +/* + * The embedded PHY's power-on, as eth_na51103.c's eth_phy_poweron() and + * its PHY reset, break-link timer and LED settings + */ +static void nvt_eth_phy_on(void) +{ + setbits_le32(EPHY(0xF8), BIT(7)); + udelay(20); + clrbits_le32(EPHY(0xC8), BIT(0)); + udelay(200); + clrbits_le32(EPHY(0xC8), BIT(1)); + udelay(250); + clrbits_le32(EPHY(0x2E8), BIT(0)); + clrbits_le32(EPHY(0xCC), BIT(0)); + setbits_le32(EPHY(0xDC), BIT(0)); + clrbits_le32(EPHY(0x9C), BIT(0)); + + setbits_le32(EPHY(0x000), BIT(1)); + writel(0x53, EPHY(0x288)); + writel(0x07, EPHY(0x28C)); + writel(0xC9, EPHY(0x284)); + writel(0x40, EPHY(0x100)); + mdelay(10); + clrbits_le32(EPHY(0x000), BIT(1)); +} + +/* + * The first MAC (0x2_F044_0000) as the vendor U-Boot's eth_na51103.c sets + * it up: mac0_pinmux_en(), mac0_clk_en(), extphy0_clk_en(), for its first + * pad set (the vendor's second one is compiled out). Xiongmai's + * NBD80N36RA says 0x701: an RGMII PHY with its clock and reset from the + * SoC. + */ +static phy_interface_t nvt_eth_setup(const void *fdt) +{ + u32 pins = nvt_fdt_u32(fdt, "/top/eth", "pinmux", 0); + bool ext_clk = pins & ETH_PIN_REFCLK || + nvt_fdt_u32(fdt, "/eth0", "sp-clk", 0); + phy_interface_t intf; + + if (pins & ETH_PIN_RMII) { + intf = PHY_INTERFACE_MODE_RMII; + clrsetbits_le32(TOP(0x0C), 7 << 0, 2 << 0); + clrsetbits_le32(TOP(0x0C), 3 << 12, 1 << 12); /* MDIO */ + clrbits_le32(TOP(0xB0), 0xCE3C); /* not GPIO */ + } else if (pins & ETH_PIN_RGMII) { + intf = PHY_INTERFACE_MODE_RGMII; + /* PHY clock, Tx clock, control and data at 8 mA */ + clrsetbits_le32(PAD(0x90), 0xf, 0x1); + clrsetbits_le32(PAD(0x94), 0xffffff, 0x111111); + clrsetbits_le32(TOP(0x0C), 7 << 0, 1 << 0); + clrsetbits_le32(TOP(0x0C), 3 << 12, 1 << 12); /* MDIO */ + clrbits_le32(TOP(0xB0), 0xFFFC); /* not GPIO */ + } else { + intf = PHY_INTERFACE_MODE_MII; + setbits_le32(TOP(0x0C), BIT(31)); /* the embedded PHY */ + } + + /* PLL7, the MAC's clock, out of reset */ + setbits_le32(CG(0x00), BIT(7)); + udelay(10); + setbits_le32(CG(0x70), BIT(27)); + udelay(10); + setbits_le32(CG(0x94), BIT(16)); + udelay(10); + + if (intf == PHY_INTERFACE_MODE_RMII) { + u32 v = readl(GLUE(0x14)); + + /* The reference clock: from the PHY, or out to it */ + v &= ~(BIT(2) | BIT(4) | 3 << 30); + v |= BIT(0) | BIT(5); + if (nvt_fdt_u32(fdt, "/eth0", "ref-clk-out", 0)) + v = (v & ~BIT(0)) | BIT(4); + writel(v, GLUE(0x14)); + } else if (intf == PHY_INTERFACE_MODE_RGMII) { + /* As the vendor: [31:30] kept, Tx data from RGMII */ + writel((readl(GLUE(0x14)) & (3 << 30)) | 1 << 30 | 3 << 4, + GLUE(0x14)); + } + if (intf == PHY_INTERFACE_MODE_MII) { + clrbits_le32(GLUE(0x04), 3 << 4); /* the embedded PHY */ + nvt_eth_phy_on(); + } else { + setbits_le32(GLUE(0x04), BIT(4)); /* an external one */ + writel(0x1FF, GLUE(0x0C)); + } + + if (intf != PHY_INTERFACE_MODE_MII && ext_clk) { + /* The PHY's 25 MHz out of the SoC */ + setbits_le32(CG(0x74), BIT(7)); + setbits_le32(TOP(0x0C), BIT(8)); + clrbits_le32(TOP(0xB0), BIT(0)); + } + /* The PHY's reset, on E_GPIO 1 */ + if (intf != PHY_INTERFACE_MODE_MII) + nvt_phy_reset(E_GPIO(1)); + return intf; +} +#endif /* CONFIG_NVT_NA51103 */ + +#ifdef CONFIG_NVT_NA51090 +#define ETH2_PIN_RGMII BIT(12) /* an RGMII PHY on the first pads */ +#define ETH2_PIN_RGMII_2 BIT(13) /* or on the second */ +#define ETH2_PIN_RMII BIT(16) +#define ETH2_PIN_RMII_2 BIT(17) +#define ETH2_PIN_REFCLK BIT(20) /* the PHY's 25 MHz from the SoC */ + +/* The tree's eth0 node: Xiongmai-style "eth0@2,f0210000", or the SDK's */ +static int nvt_eth_node(const void *fdt) +{ + int node = fdt_path_offset(fdt, "/eth0@2,f0210000"); + + return node >= 0 ? node : fdt_path_offset(fdt, "/eth1@2,f0210000"); +} + +/* + * The MAC at 0x2_F021_0000, which the boards' tree calls eth0 and Linux + * uses as eth0, as the vendor U-Boot's eth_na51090.c sets up its MAC1: + * mac1_pinmux_en(), mac1_clk_en(), extphy1_clk_en(). It has no embedded + * PHY. The NT98633 NVR says 0x502501: RGMII on the second pads, the PHY's + * clock from the SoC, its reset on S_GPIO 19. + */ +static phy_interface_t nvt_eth_setup(const void *fdt) +{ + u32 pins = nvt_fdt_u32(fdt, "/top/eth", "pinmux", ETH2_PIN_RGMII); + int node = fdt ? nvt_eth_node(fdt) : -1; + const fdt32_t *spclk = node >= 0 ? + fdt_getprop(fdt, node, "sp-clk", NULL) : NULL; + const fdt32_t *refout = node >= 0 ? + fdt_getprop(fdt, node, "ref-clk-out", NULL) : NULL; + bool ext_clk = pins & ETH2_PIN_REFCLK || + (spclk && fdt32_to_cpu(*spclk)); + int pad = pins & (ETH2_PIN_RGMII_2 | ETH2_PIN_RMII_2) ? 2 : 1; + phy_interface_t intf = pins & (ETH2_PIN_RMII | ETH2_PIN_RMII_2) ? + PHY_INTERFACE_MODE_RMII : + PHY_INTERFACE_MODE_RGMII; + + if (intf == PHY_INTERFACE_MODE_RMII) { + clrsetbits_le32(TOP(0x0C), 7 << 4, (pad == 1 ? 2 : 4) << 4); + } else if (pad == 1) { + clrsetbits_le32(PAD(0x98), 0xf, 0x1); + clrsetbits_le32(PAD(0x9C), 0xffffff, 0x111111); + clrsetbits_le32(TOP(0x0C), 7 << 4, 1 << 4); + } else { + clrsetbits_le32(PAD(0xA8), 0xf << 8, 0x1 << 8); + clrsetbits_le32(PAD(0xAC), 0xffffff << 8, 0x111111 << 8); + clrsetbits_le32(TOP(0x0C), 7 << 4, 3 << 4); + } + clrsetbits_le32(TOP(0x0C), 3 << 20, pad << 20); /* MDIO */ + if (pad == 1) { + clrbits_le32(TOP(0xB0), intf == PHY_INTERFACE_MODE_RMII ? + 0xCE3C0000 : 0xFFFC0000); + } else { + clrbits_le32(TOP(0xC0), intf == PHY_INTERFACE_MODE_RMII ? + 0x38F00000 : 0xFFF00000); + clrbits_le32(TOP(0xC4), 0x3); + } + + /* PLL7, the MAC's clock, out of reset */ + setbits_le32(CG(0x00), BIT(7)); + udelay(10); + setbits_le32(CG(0x70), BIT(28)); + udelay(10); + setbits_le32(CG(0x94), BIT(17)); + udelay(10); + + if (intf == PHY_INTERFACE_MODE_RMII) { + u32 v = readl(GLUE(0x14)); + + v &= ~(BIT(2) | BIT(4) | 3 << 30); + v |= BIT(0) | BIT(5); + if (refout && fdt32_to_cpu(*refout)) + v = (v & ~BIT(0)) | BIT(4); + writel(v, GLUE(0x14)); + } else { + writel((readl(GLUE(0x14)) & (3 << 30)) | 1 << 30 | 3 << 4, + GLUE(0x14)); + } + setbits_le32(GLUE(0x04), BIT(4)); /* an external PHY */ + writel(0x1FF, GLUE(0x0C)); + + if (ext_clk) { + setbits_le32(CG(0x74), BIT(8)); + setbits_le32(TOP(0x0C), BIT(16)); + if (pad == 1) + clrbits_le32(TOP(0xB0), BIT(16)); + else + clrbits_le32(TOP(0xC0), BIT(18)); + } + nvt_phy_reset(pad == 1 ? E_GPIO(17) : S_GPIO(19)); + return intf; +} +#endif /* CONFIG_NVT_NA51090 */ + +int board_eth_init(struct bd_info *bis) +{ + const void *fdt = nvt_loader_fdt(); + + /* + * phylib binds the PHY as the vendor does, as MII: the PHY keeps + * its strapped RGMII delays, and the MAC follows the speed it + * negotiates (1000, 100 or 10 Mb/s). + */ + nvt_eth_setup(fdt); + return nvt_eqos_initialize(PHY_INTERFACE_MODE_MII); +} +#endif /* CONFIG_NVT_EQOS */ diff --git a/board/novatek/na511xx/u-boot.lds b/board/novatek/na511xx/u-boot.lds new file mode 100644 index 000000000000..e0da09100ba2 --- /dev/null +++ b/board/novatek/na511xx/u-boot.lds @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * arch/arm/cpu/armv8/u-boot.lds with the HEADINFO of the Novatek NA51103 / + * NA51090 loader at 0x300. + * + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + */ + +#include +#include + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{ +#ifdef CONFIG_ARMV8_SECURE_BASE + /DISCARD/ : { *(.rela._secure*) } +#endif + . = 0x00000000; + + . = ALIGN(8); + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + /* + * The Novatek loader looks for the image's HEADINFO here: + * where to start it and how long it is, with a checksum. + */ + . = 0x300; + KEEP(*(.nvt_headinfo)) + } + + /* This needs to come before *(.text*) */ + .efi_runtime : { + __efi_runtime_start = .; + *(.text.efi_runtime*) + *(.rodata.efi_runtime*) + *(.data.efi_runtime*) + __efi_runtime_stop = .; + } + + .text_rest : + { + *(.text*) + } + +#ifdef CONFIG_ARMV8_PSCI + .__secure_start : +#ifndef CONFIG_ARMV8_SECURE_BASE + ALIGN(CONSTANT(COMMONPAGESIZE)) +#endif + { + KEEP(*(.__secure_start)) + } + +#ifndef CONFIG_ARMV8_SECURE_BASE +#define CONFIG_ARMV8_SECURE_BASE +#define __ARMV8_PSCI_STACK_IN_RAM +#endif + .secure_text CONFIG_ARMV8_SECURE_BASE : + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) + { + *(._secure.text) + . = ALIGN(8); + __secure_svc_tbl_start = .; + KEEP(*(._secure_svc_tbl_entries)) + __secure_svc_tbl_end = .; + } + + .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) + { + *(._secure.data) + } + + .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data), + CONSTANT(COMMONPAGESIZE)) (NOLOAD) : +#ifdef __ARMV8_PSCI_STACK_IN_RAM + AT(ADDR(.secure_stack)) +#else + AT(LOADADDR(.secure_data) + SIZEOF(.secure_data)) +#endif + { + KEEP(*(.__secure_stack_start)) + + . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; + + . = ALIGN(CONSTANT(COMMONPAGESIZE)); + + KEEP(*(.__secure_stack_end)) + } + +#ifndef __ARMV8_PSCI_STACK_IN_RAM + . = LOADADDR(.secure_stack); +#endif + + .__secure_end : AT(ADDR(.__secure_end)) { + KEEP(*(.__secure_end)) + LONG(0x1d1071c); /* Must output something to reset LMA */ + } +#endif + + . = ALIGN(8); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(8); + .data : { + *(.data*) + } + + . = ALIGN(8); + + . = .; + + . = ALIGN(8); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); + } + + . = ALIGN(8); + + .efi_runtime_rel : { + __efi_runtime_rel_start = .; + *(.rel*.efi_runtime) + *(.rel*.efi_runtime.*) + __efi_runtime_rel_stop = .; + } + + . = ALIGN(8); + + .image_copy_end : + { + *(.__image_copy_end) + } + + . = ALIGN(8); + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rela.dyn : { + *(.rela*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + + . = ALIGN(8); + + .bss_start : { + KEEP(*(.__bss_start)); + } + + .bss : { + *(.bss*) + . = ALIGN(8); + } + + .bss_end : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } + +#ifdef CONFIG_LINUX_KERNEL_IMAGE_HEADER +#include "linux-kernel-image-header-vars.h" +#endif +} diff --git a/board/novatek/ns02501/loader/.gitattributes b/board/novatek/ns02501/loader/.gitattributes new file mode 100644 index 000000000000..1c5b20e00b05 --- /dev/null +++ b/board/novatek/ns02501/loader/.gitattributes @@ -0,0 +1,2 @@ +# The vendor loader, as the SDK ships it: no line-ending conversion +* -text diff --git a/board/novatek/ns02501/loader/.gitignore b/board/novatek/ns02501/loader/.gitignore new file mode 100644 index 000000000000..f84d41d3cbe0 --- /dev/null +++ b/board/novatek/ns02501/loader/.gitignore @@ -0,0 +1,2 @@ +# The vendor libraries the loader links against +!*.a diff --git a/board/novatek/ns02501/loader/ARC/Lib/Release/CA9.a b/board/novatek/ns02501/loader/ARC/Lib/Release/CA9.a new file mode 100644 index 000000000000..a647a8aad25c Binary files /dev/null and b/board/novatek/ns02501/loader/ARC/Lib/Release/CA9.a differ diff --git a/board/novatek/ns02501/loader/ARC/Lib/Release/Common_exFAT.a b/board/novatek/ns02501/loader/ARC/Lib/Release/Common_exFAT.a new file mode 100644 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a/board/novatek/ns02501/loader/ARC/Lib/Release/nvtpack.a b/board/novatek/ns02501/loader/ARC/Lib/Release/nvtpack.a new file mode 100644 index 000000000000..24bfb85547a8 Binary files /dev/null and b/board/novatek/ns02501/loader/ARC/Lib/Release/nvtpack.a differ diff --git a/board/novatek/ns02501/loader/Include/CMacro.h b/board/novatek/ns02501/loader/Include/CMacro.h new file mode 100755 index 000000000000..8d4bcd2f4a15 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/CMacro.h @@ -0,0 +1,35 @@ +/*++ + +Copyright (c) 2005 Novatek Microelectronics Corporation + +Module Name: + StdCMac.h + +Abstract: + Standard C Macros for shared header file of ARM ASM and C + You should include this file first and then include the shared header file + For more information, please refer to http://www.arm.com/support/faqdev/1208.html + +Environment: + For nt96610 + +Notes: + Copyright (c) 2005 Novatek Microelectronics Corporation. All Rights Reserved. + +Revision History: + ??/??/??: Created by ARM + 03/17/05: Modify by Chris Hsu for NT96610 uITRON project +--*/ + +#ifndef __C_MACRO_H +#define __C_MACRO_H + + +/* Comment */ +#define COMMENT + +/* end */ +#define END + +#endif // __C_MACRO_H + diff --git a/board/novatek/ns02501/loader/Include/Driver/CC.h b/board/novatek/ns02501/loader/Include/Driver/CC.h new file mode 100755 index 000000000000..7a1bd23aacd6 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/CC.h @@ -0,0 +1,65 @@ +/** + Header file for CC (Core Communicator) module. + + This file is the header file that define the API and data type + for CC module. + + @file CC.h + @ingroup mIDrvSys_CC + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ + +#ifndef _CC_H +#define _CC_H + +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + +#define CC_CORE_CA53_CORE1 0 +#define CC_CORE_CA53_CORE2 1 +#define CC_CORE_DSP 2 +#define CC_CORE_DSP2 3 + +typedef enum +{ + DMA_ID_1, ///< DMA Controller + DMA_ID_2, ///< DMA Controller 2 + + DMA_ID_COUNT, //< DMA controller count + + ENUM_DUMMY4WORD(DMA_ID) +} DMA_ID; + +typedef enum +{ + CC_RESOURCE_UART, + + CC_RESOURCE_COUNT, //< DMA controller count + + ENUM_DUMMY4WORD(CC_RESOURCE_ID) +} CC_RESOURCE_ID; + +typedef enum { + CC_CORE_CPU1 = 0x1, ///< 1st Core CPU + CC_CORE_CPU2 = 0x2, ///< 2nd Core CPU + CC_CORE_MCU = 0x3, ///< MCU + CC_CORE_MAX = 0x3, + CC_CORE_DUMMY = 0xFFFFFFFF, +} CC_CORE_ID; + +typedef struct { + UINT32 cmd_buf[3]; +} CC_CMD, *PCC_CMD; + +extern void cc_setCore2Base(UINT32 uiBaseAddr); +extern ER cc_startCore(UINT32 uiCoreID) __attribute__ ((section (".part1"))); +extern void cc_stopCore(UINT32 uiCoreID); +extern UINT32 dma_get_dram_capacity(DMA_ID id); +extern int cc_getCoreCount(void) __attribute__ ((section (".part1"))); // total cnt = cc_getCoreCount() + 1 +extern int cc_getCoreId(void) __attribute__ ((section (".part1"))); +extern void cc_lock_resource(UINT32 uiCoreID, UINT32 resource) __attribute__ ((section (".part1"))); +extern void cc_unlock_resource(UINT32 uiCoreID, UINT32 resource) __attribute__ ((section (".part1"))); +extern int cc_send_core_cmd(int core_id, PCC_CMD p_cmd); + +#endif diff --git a/board/novatek/ns02501/loader/Include/Driver/Cache.h b/board/novatek/ns02501/loader/Include/Driver/Cache.h new file mode 100755 index 000000000000..37e0eb9dc3dc --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/Cache.h @@ -0,0 +1,535 @@ +/** + CPU module driver. + + This file is the driver of CPU module. + + @file Cache.h + @ingroup mIHALCore + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2005. All rights reserved. +*/ + +#ifndef _CACHE_H +#define _CACHE_H +#include "constant.h" + + +/* + csselrcache level & type selection + + Detailed reference to [trm p4-177 CSSELR] +*/ +typedef enum _CACHE_LV_TYPE_ +{ + LEVEL_1_DCACHE = 0x0, //< Level 1 data cache + LEVEL_1_ICACHE, //< Level 1 instruction cache + LEVEL_2_DCACHE, //< Level 2 data cache +} CACHE_LV_TYPE; + + +/* + Values for Ctype fields in CLIDR +*/ + +typedef enum _CLIDR_CTYPE_ +{ + CLIDR_CTYPE_NO_CACHE = 0x0, + CLIDR_CTYPE_INSTRUCTION_ONLY= 0x1, + CLIDR_CTYPE_DATA_ONLY = 0x2, + CLIDR_CTYPE_INSTRUCTION_DATA= 0x3, + CLIDR_CTYPE_UNIFIED = 0x4, +}CLIDR_CTYPE; + + +//Instruction Synchronization Barrier. +#define _ISB() \ + __asm__ __volatile__("isb\n\t") + +//Data Synchronization Barrier +#define _DSB() \ + __asm__ __volatile__("dsb\n\t") + +//Data Memory Barrier +#define _DMB() \ + __asm__ __volatile__("dmb\n\t") + + +/* + ************************************************************************ + * Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |W|W|R|W|NumSets |Associativity |L | + * |T|B|A|A| | |S | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_DC_SETS 8 +#define S_DC_W 2 +#define S_DC_LS 5 + +#define _DC_SETS (1 << S_DC_SETS) /* 256 sets */ +#define _DC_W (1 << S_DC_W) /* 4 way */ +#define _DC_LS (1 << S_DC_LS) /* 32 byte line size */ + +#define S_IC_SETS 8 +#define S_IC_W 2 +#define S_IC_LS 5 + +#define _IC_SETS (1 << S_IC_SETS) /* 256 sets */ +#define _IC_W (1 << S_IC_W) /* 4 way */ +#define _IC_LS (1 << S_IC_LS) /* 32 byte line size */ + +#define S_DC_W_L2 4 /* L2 way shift*/ + +#define S_SC_SETS 9 +#define S_SC_W 3 +#define S_SC_LS 5 + +#define _SC_SETS (1 << S_SC_SETS) /* 512 sets */ +#define _SC_W (1 << S_SC_W) /* 8 way */ +#define _SC_LS (1 << S_SC_LS) /* 32 byte line size */ + + +#define S_CCSIDR_WT 31 +#define M_CCSIDR_WT (0x1 << S_CCSIDR_WT) /* Support write-through */ +#define S_CCSIDR_WB 30 +#define M_CCSIDR_WB (0x1 << S_CCSIDR_WB) /* Support write-back */ +#define S_CCSIDR_RA 29 +#define M_CCSIDR_RA (0x1 << S_CCSIDR_RA) /* Support read-allocation */ +#define S_CCSIDR_WA 28 +#define M_CCSIDR_WA (0x1 << S_CCSIDR_WA) /* Support write-allocation */ +#define S_CCSIDR_SETS 13 +#define M_CCSIDR_SETS (0x7fff << S_CCSIDR_SETS) /* Number of sets */ +#define S_CCSIDR_A 3 +#define M_CCSIDR_A (0x3ff << S_CCSIDR_A) /* Number of associatiovity */ +#define S_CCSIDR_LS 0 +#define M_CCSIDR_LS (0x7 << S_CCSIDR_LS) /* Cache line size */ + + +/* + * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_WXN (1 << 19) /* Write Permision Imply XN */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ + +#define SCTLR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + : "=r" (val)); \ + val; \ + }) + +#define LEVEL_1 (1 - 1) +#define LEVEL_2 (2 - 1) + +#define CCSIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__( \ + "mrc p15, 1, %0, c0, c0, 0\n\t" \ + : "=r" (val)); \ + val; \ + }) + + +#define sel_CSSELR(InD) \ + __asm__ __volatile__( \ + "mcr p15, 2, %0, c0, c0, 0\n\t" \ + : \ + : "r"(InD)); + +#define _ICACHE_INV_ALL() _ICIALLU() \ + _BPIALL() + +/* + ICIALLU, Instruction Cache Invalidate All to PoU + The ICIALLU characteristics are: + + Invalidate all instruction caches to PoU. If branch predictors are + architecturally visible, also flush branch predictors. + + This register is part of the Cache maintenance instructions functional group. + + Usage constraints + If EL3 is implemented and is using AArch32, this operation can be performed at the following + exception levels: +*/ +#define _ICIALLU() \ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); + +/* + Branch Predictor Invalidate All + The BPIALL characteristics are: + + Invalidate all entries from branch predictors. + This register is part of the Cache maintenance instructions functional group. + Usage constraints + If EL3 is implemented and is using AArch32, this operation can be performed at the following + exception levels: +*/ +#define _BPIALL() \ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); + + +/* + ICIMVAU : Instruction Cache line Invalidate by VA to PoU +*/ +#define _ICACHE_INV_MVAU(addr) _ICIMVAU(addr) +#define _ICIMVAU(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c5, 1\n\t" \ + : \ + : "r"(addr)); + +#define _DCACHE_INV_MVAC(addr) _DCIMVAC(addr) +#define _DCIMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c6, 1\n\t" \ + : \ + : "r"(addr)); + +//DCCMVAC Clean data cache line by VA to PoC +#define _DCACHE_WBACK_MVAC(addr) _DCCMVAC(addr) +#define _DCCMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c10, 1\n\t" \ + : \ + : "r"(addr)); + +//_DCCIMVAC Clean and invalidate data cache line by VA to PoC +#define _DCACHE_WBACK_INV_MVAC(addr) _DCCIMVAC(addr) +#define _DCCIMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c14, 1\n\t" \ + : \ + : "r"(addr)); + +//DCCISW Clean and invalidate data cache line by set/way +#define _DCCISW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c14, 2\n\t" \ + : \ + : "r"(way_set)); + +//DCISW Invalidate data cache line by set/way +/* + The DCISW input value bit assignments are: + + |31......................4 | 3...1 | 0 | + Setway level rsv + bit[3..1] = 0x0 = Level 1 + bit[3..1] = 0x1 = Level 2 + ... +*/ +#define _DCISW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c6, 2\n\t" \ + : \ + : "r"(way_set)); + + +//DCCSW Clean data cache line by set/way +/* + The DCCSW input value bit assignments are: + + |31......................4 | 3...1 | 0 | + Setway level rsv + bit[3..1] = 0x0 = Level 1 + bit[3..1] = 0x1 = Level 2 + ... +*/ +#define _DCCSW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c10, 2\n\t" \ + : \ + : "r"(way_set)) + + + + +/* Cache dirty register () */ +#define read_CDSR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c7, c10, 6\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +/* Get CPU ID */ +#define read_MPIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c0, c0, 5\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +/* ead current CP15 Cache Level ID Register */ +#define read_CLIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 1, %0, c0, c0, 1\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +#define change_property() \ + ({ \ + __asm__ __volatile__( \ + ".arch_extension sec\n\t" \ + "smc #123\n\t" \ + : \ + : \ + ); \ + }) + +#define CLEAR_MMU() \ + __asm__ __volatile__("mcr p15, 0, r0, c8, c7, 0\n\t"); + + +#define DISABLE_MMU() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x1\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define ENABLE_MMU() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "orr %0, %0, #0x1\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define DISABLE_DCACHE() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x4\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define ENABLE_DCACHE() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "orr %0, %0, #0x4\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define DISABLE_ICACHE() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x1000\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define SETUP_TTBR0(val) \ + ({ \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c2, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) +/* Cache dirty register () */ +#define read_CDSR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c7, c10, 6\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) +/** + @addtogroup mIHALCore +*/ +//@{ + +/** + @name CPU clean invalidate all DCache + + Clean and invalidate all data cache + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCacheAll() cpu_cleanInvalidateDCacheAll() ///< clean invalidate all DCache +//@} + +/** + @name CPU clean invalidate DCache + + Clean and invalidate data cache + Cache line associated with input address will be clean and invalidated + + @param[in] addr data address to be clean and invalidated + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCache(addr) cpu_cleanInvalidateDCache(addr) ///< clean invalidate DCache +//@} + +/** + @name CPU clean invalidate DCache block + + Clean and invalidate data cache block + Cache line associated with input region will be clean and invalidated + + @param[in] m starting data address to be clean and invalidated + @param[in] n end data address to be clean and invalidated + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCacheBlock(m,n) cpu_cleanInvalidateDCacheBlock(m, n) ///< clean invalidate DCache block +//@} + +/** + @name CPU invalidate DCache + + Invalidate data cache + Cache line associated with input address will be invalidated + + @param[in] addr data address to be invalidated + + @return void +*/ +//@{ +#define CPUInvalidateDCache(m) cpu_invalidateDCache(m) ///< invalidate DCache +//@} + +/** + @name CPU invalidate DCache block + + Invalidate data cache block + Cache line associated with input region will be invalidated + + @param[in] m starting data address to be invalidated + @param[in] n end data address to be invalidated + + @return void +*/ +//@{ +#define CPUInvalidateDCacheBlock(m,n) cpu_invalidateDCacheBlock(m,n) ///< invalidate DCache block +//@} + +/** + @name CPU clean DCache + + Clean data cache + Cache line associated with input address will be clean + + @param[in] addr data address to be clean + + @return void +*/ +//@{ +#define CPUCleanDCache(m) cpu_cleanDCache(m) ///< clean DCache +//@} + +/** + @name CPU clean DCache block + + Clean data cache block + Cache line associated with input region will be clean + + @param[in] m starting data address to be clean + @param[in] n end data address to be clean + + @return void +*/ +//@{ +#define CPUCleanDCacheBlock(m, n) cpu_cleanDCacheBlock(m, n) ///< clean DCache block +//@} + +/** + @name CPU invalidate all DCache + + Invalidate all data cache + + @return void +*/ +//@{ +#define CPUInvalidateDCacheAll() cpu_invalidateDCacheAll() ///< invalidate all DCache +//@} + + +extern BOOL CPUChkDCacheEnabled(UINT32 addr); +extern void CPUInvalidateICacheAll(void) __attribute__ ((section (".part1"))); +//extern void CPUInvalidateICacheAll(void) __attribute__ ((section (".part1"), far)); +//extern void CPUInvalidateICache(UINT32 addr); +extern void CPUInvalidateICacheBlock(UINT32 start, UINT32 end); + +#if 0 +extern void CPUInvalidateDCacheAll(void); +extern void CPUInvalidateDCache(UINT32 addr); +extern void CPUInvalidateDCacheBlock(UINT32 start, UINT32 end); +#endif +extern void cpu_invalidateDCacheBlock(UINT32 start, UINT32 end); +extern void cpu_invalidateDCache(UINT32 addr); +extern void cpu_invalidateDCacheAll(void)__attribute__ ((section (".part1"))); +extern void cpu_cleanDCache(UINT32 addr); +extern void cpu_cleanDCacheBlock(UINT32 start, UINT32 end)__attribute__ ((section (".part1"))); +extern void _cache_clean_d_cache_all(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); +extern void _cache_invalidate_data_cache_all(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); +extern void _cache_clean_invalidate_d_cache_All(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); + + + +extern void cpu_cleanInvalidateDCacheAll(void)__attribute__ ((section (".part1"))); +//extern void cpu_cleanInvalidateDCacheAll(void)__attribute__ ((section (".part1"), far)); +extern void cpu_cleanInvalidateDCache(UINT32 addr)__attribute__ ((section (".part1"))); +extern void cpu_cleanInvalidateDCacheBlock(UINT32 start, UINT32 end)__attribute__ ((section (".part1"))); + +extern void CPUflushReadCache(UINT32 uiStartAddr, UINT32 uiLength)__attribute__ ((section (".part1"))); +extern void CPUflushWriteCache(UINT32 uiStartAddr, UINT32 uiLength)__attribute__ ((section (".part1"))); + + + +#endif + +//@} diff --git a/board/novatek/ns02501/loader/Include/Driver/Clock.h b/board/novatek/ns02501/loader/Include/Driver/Clock.h new file mode 100755 index 000000000000..2b626aa3ed6e --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/Clock.h @@ -0,0 +1,34 @@ +/** + System Clock APIs header file + + System Clock APIs header. + + @file clock.h + @ingroup mIHALSysCG + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __CLOCK_H +#define __CLOCK_H + +#include "IOReg.h" + +/** \addtogroup mIHALSysCG */ +//@{ +// For SM host clock rate +#define GZ_CLOCK_RATE_240_MHZ (0x00 << 12) +#define GZ_CLOCK_RATE_320_MHZ (0x01 << 12) +#define GZ_CLOCK_RATE_480_MHZ (0x02 << 12) +#define GZ_CLOCK_RATE_MASK (0x03 << 12) + + +#define enableGZReset() CLRREG32(CLOCK_GEN_REG_BASE_ADDR + 0x8C, (1 << 7)) +#define disableGZReset() SETREG32(CLOCK_GEN_REG_BASE_ADDR + 0x8C, (1 << 7)) + +#define enableGZClock() SETREG32(CLOCK_GEN_REG_BASE_ADDR + 0x78, (1 << 11)) +#define disableGZClock() CLRREG32(CLOCK_GEN_REG_BASE_ADDR + 0x78, (1 << 11)) +//@} + +#endif // __CLOCK_H diff --git a/board/novatek/ns02501/loader/Include/Driver/GPIO.h b/board/novatek/ns02501/loader/Include/Driver/GPIO.h new file mode 100755 index 000000000000..f139775a27b2 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/GPIO.h @@ -0,0 +1,371 @@ +/** + General Purpose I/O controller header file + + General Purpose I/O controller header file + + @file GPIO.h + @ingroup mIIOGPIO + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _GPIO_H +#define _GPIO_H + +#include "IOReg.h" + +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + +/** + @addtogroup mIDrvIO_GPIO +*/ +//@{ + +/** + GPIO direction + + GPIO direction definition for gpio_setDir() and gpio_getDir() +*/ +typedef enum { + GPIO_DIR_INPUT = 0, ///< GPIO is input direction + GPIO_DIR_OUTPUT = 1, ///< GPIO is output direction + + ENUM_DUMMY4WORD(GPIO_DIR) +} GPIO_DIR; + +/** + GPIO interrupt type + + GPIO interrupt type definition for type argument of gpio_setIntTypePol() +*/ +typedef enum { + GPIO_INTTYPE_EDGE = 0, ///< GPIO interrupt is edge trigger + GPIO_INTTYPE_LEVEL = 1, ///< GPIO interrupt is level trigger + + ENUM_DUMMY4WORD(GPIO_INTTYPE) +} GPIO_INTTYPE; + +/** + GPIO interrupt polarity + + GPIO interrupt polarity definition for pol argument of gpio_setIntTypePol() +*/ +typedef enum { + GPIO_INTPOL_POSHIGH = 0, ///< GPIO interrupt polarity is \n + ///< - @b positvie edge for edge trigger + ///< - @b high level for level trigger + GPIO_INTPOL_NEGLOW = 1, ///< GPIO interrupt polarity is \n + ///< - @b negative edge for edge trigger + ///< - @b low level for level trigger + GPIO_INTPOL_BOTHEDGE = 2, ///< GPIO interrupt polarity is \n + ///< - @b both edge for edge trigger + ENUM_DUMMY4WORD(GPIO_INTPOL) +} GPIO_INTPOL; + + + +/** + @name GPIO pins ID + + GPIO pins ID definition + + For detail GPIO pin out, please refer to NT96520 data sheet. +*/ +//@{ +/*Storage GPIO - CGPIO*/ +#define C_GPIO_0 0 ///< C_GPIO[0] +#define C_GPIO_1 1 ///< C_GPIO[1] +#define C_GPIO_2 2 ///< C_GPIO[2] +#define C_GPIO_3 3 ///< C_GPIO[3] +#define C_GPIO_4 4 ///< C_GPIO[4] +#define C_GPIO_5 5 ///< C_GPIO[5] +#define C_GPIO_6 6 ///< C_GPIO[6] +#define C_GPIO_7 7 ///< C_GPIO[7] +#define C_GPIO_8 8 ///< C_GPIO[8] +#define C_GPIO_9 9 ///< C_GPIO[9] +#define C_GPIO_10 10 ///< C_GPIO[10] +#define C_GPIO_11 11 ///< C_GPIO[11] +#define C_GPIO_12 12 ///< C_GPIO[12] +#define C_GPIO_13 13 ///< C_GPIO[13] +#define C_GPIO_14 14 ///< C_GPIO[14] +#define C_GPIO_15 15 ///< C_GPIO[15] +#define C_GPIO_16 16 ///< C_GPIO[16] +#define C_GPIO_17 17 ///< C_GPIO[17] +#define C_GPIO_18 18 ///< C_GPIO[18] +#define C_GPIO_19 19 ///< C_GPIO[19] +#define C_GPIO_20 20 ///< C_GPIO[20] +#define C_GPIO_21 21 ///< C_GPIO[21] +#define C_GPIO_22 22 ///< C_GPIO[22] +#define C_GPIO_23 23 ///< C_GPIO[23] +#define C_GPIO_24 24 ///< C_GPIO[24] + + +#define H_GPIO_SHIFT_BASE 32 +#define HSI_GPIO_0 (0 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[0] +#define HSI_GPIO_1 (1 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[1] +#define HSI_GPIO_2 (2 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[2] +#define HSI_GPIO_3 (3 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[3] +#define HSI_GPIO_4 (4 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[4] +#define HSI_GPIO_5 (5 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[5] +#define HSI_GPIO_6 (6 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[6] +#define HSI_GPIO_7 (7 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[7] +#define HSI_GPIO_8 (8 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[8] +#define HSI_GPIO_9 (9 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[9] +#define HSI_GPIO_10 (10+H_GPIO_SHIFT_BASE) ///< HSI_GPIO[10] +#define HSI_GPIO_11 (11+H_GPIO_SHIFT_BASE) ///< HSI_GPIO[11] + +#define S_GPIO_SHIFT_BASE 64 +#define S_GPIO_0 (0 +S_GPIO_SHIFT_BASE) ///< S_GPIO[0] +#define S_GPIO_1 (1 +S_GPIO_SHIFT_BASE) ///< S_GPIO[1] +#define S_GPIO_2 (2 +S_GPIO_SHIFT_BASE) ///< S_GPIO[2] +#define S_GPIO_3 (3 +S_GPIO_SHIFT_BASE) ///< S_GPIO[3] +#define S_GPIO_4 (4 +S_GPIO_SHIFT_BASE) ///< S_GPIO[4] +#define S_GPIO_5 (5 +S_GPIO_SHIFT_BASE) ///< S_GPIO[5] +#define S_GPIO_6 (6 +S_GPIO_SHIFT_BASE) ///< S_GPIO[6] +#define S_GPIO_7 (7 +S_GPIO_SHIFT_BASE) ///< S_GPIO[7] +#define S_GPIO_8 (8 +S_GPIO_SHIFT_BASE) ///< S_GPIO[8] + + +#define P_GPIO_SHIFT_BASE 96 +#define P_GPIO_0 (0 +P_GPIO_SHIFT_BASE) ///< P_GPIO[0] +#define P_GPIO_1 (1 +P_GPIO_SHIFT_BASE) ///< P_GPIO[1] +#define P_GPIO_2 (2 +P_GPIO_SHIFT_BASE) ///< P_GPIO[2] +#define P_GPIO_3 (3 +P_GPIO_SHIFT_BASE) ///< P_GPIO[3] +#define P_GPIO_4 (4 +P_GPIO_SHIFT_BASE) ///< P_GPIO[4] +#define P_GPIO_5 (5 +P_GPIO_SHIFT_BASE) ///< P_GPIO[5] +#define P_GPIO_6 (6 +P_GPIO_SHIFT_BASE) ///< P_GPIO[6] +#define P_GPIO_7 (7 +P_GPIO_SHIFT_BASE) ///< P_GPIO[7] +#define P_GPIO_8 (8 +P_GPIO_SHIFT_BASE) ///< P_GPIO[8] +#define P_GPIO_9 (9 +P_GPIO_SHIFT_BASE) ///< P_GPIO[9] +#define P_GPIO_10 (10+P_GPIO_SHIFT_BASE) ///< P_GPIO[10] +#define P_GPIO_11 (11+P_GPIO_SHIFT_BASE) ///< P_GPIO[11] +#define P_GPIO_12 (12+P_GPIO_SHIFT_BASE) ///< P_GPIO[12] +#define P_GPIO_13 (13+P_GPIO_SHIFT_BASE) ///< P_GPIO[13] +#define P_GPIO_14 (14+P_GPIO_SHIFT_BASE) ///< P_GPIO[14] +#define P_GPIO_15 (15+P_GPIO_SHIFT_BASE) ///< P_GPIO[15] +#define P_GPIO_16 (16+P_GPIO_SHIFT_BASE) ///< P_GPIO[16] +#define P_GPIO_17 (17+P_GPIO_SHIFT_BASE) ///< P_GPIO[17] +#define P_GPIO_18 (18+P_GPIO_SHIFT_BASE) ///< P_GPIO[18] +#define P_GPIO_19 (19+P_GPIO_SHIFT_BASE) ///< P_GPIO[19] +#define P_GPIO_20 (20+P_GPIO_SHIFT_BASE) ///< P_GPIO[20] +#define P_GPIO_21 (21+P_GPIO_SHIFT_BASE) ///< P_GPIO[21] +#define P_GPIO_22 (22+P_GPIO_SHIFT_BASE) ///< P_GPIO[22] +#define P_GPIO_23 (23+P_GPIO_SHIFT_BASE) ///< P_GPIO[23] +#define P_GPIO_24 (24+P_GPIO_SHIFT_BASE) ///< P_GPIO[24] +#define P_GPIO_25 (25+P_GPIO_SHIFT_BASE) ///< P_GPIO[25] + +#define DSI_GPIO_SHIFT_BASE 128 +#define DSI_GPIO_0 (0 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[0] +#define DSI_GPIO_1 (1 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[1] +#define DSI_GPIO_2 (2 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[2] +#define DSI_GPIO_3 (3 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[3] +#define DSI_GPIO_4 (4 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[4] +#define DSI_GPIO_5 (5 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[5] +#define DSI_GPIO_6 (6 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[6] +#define DSI_GPIO_7 (7 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[7] +#define DSI_GPIO_8 (8 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[8] +#define DSI_GPIO_9 (9 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[9] +#define DSI_GPIO_10 (10 +DSI_GPIO_SHIFT_BASE) ///< DSI_GPIO[10] + +#define LCD_GPIO_SHIFT_BASE 160 +#define L_GPIO_0 (0 +LCD_GPIO_SHIFT_BASE) ///< L_GPIO[0] +#define L_GPIO_1 (1 +LCD_GPIO_SHIFT_BASE) ///< L_GPIO[1] +#define L_GPIO_2 (2 +LCD_GPIO_SHIFT_BASE) ///< L_GPIO[2] +#define L_GPIO_3 (3 +LCD_GPIO_SHIFT_BASE) ///< L_GPIO[3] +#define L_GPIO_4 (4 +LCD_GPIO_SHIFT_BASE) ///< L_GPIO[4] +#define L_GPIO_5 (5 +LCD_GPIO_SHIFT_BASE) ///< L_GPIO[5] +#define L_GPIO_6 (6 +LCD_GPIO_SHIFT_BASE) ///< L_GPIO[6] +#define L_GPIO_7 (7 +LCD_GPIO_SHIFT_BASE) ///< L_GPIO[7] +#define L_GPIO_8 (8 +LCD_GPIO_SHIFT_BASE) ///< L_GPIO[8] +#define L_GPIO_9 (9 +LCD_GPIO_SHIFT_BASE) ///< L_GPIO[9] + +#define D_GPIO_SHIFT_BASE 192 +#define D_GPIO_0 (0 +D_GPIO_SHIFT_BASE) ///< DGPIO[0] +#define D_GPIO_1 (1 +D_GPIO_SHIFT_BASE) ///< DGPIO[1] +#define D_GPIO_2 (2 +D_GPIO_SHIFT_BASE) ///< DGPIO[2] +#define D_GPIO_3 (3 +D_GPIO_SHIFT_BASE) ///< DGPIO[3] +#define D_GPIO_4 (4 +D_GPIO_SHIFT_BASE) ///< DGPIO[4] +#define D_GPIO_5 (5 +D_GPIO_SHIFT_BASE) ///< DGPIO[5] +#define D_GPIO_6 (6 +D_GPIO_SHIFT_BASE) ///< DGPIO[6] +#define D_GPIO_7 (7 +D_GPIO_SHIFT_BASE) ///< DGPIO[7] + +#define A_GPIO_SHIFT_BASE 224 +#define A_GPIO_0 (0 +A_GPIO_SHIFT_BASE) ///< A_GPIO[0] +#define A_GPIO_1 (1 +A_GPIO_SHIFT_BASE) ///< A_GPIO[1] +#define A_GPIO_2 (2 +A_GPIO_SHIFT_BASE) ///< A_GPIO[2] +#define A_GPIO_3 (3 +A_GPIO_SHIFT_BASE) ///< A_GPIO[3] + +//@} +#if 0 +/*For temporary usage as passing build codes*/ +#define C_GPIO_23 23 +#define C_GPIO_24 24 +#define C_GPIO_25 25 +#define C_GPIO_26 26 +#define C_GPIO_27 27 +#define C_GPIO_28 28 +#define C_GPIO_29 29 +#define C_GPIO_30 30 +#define C_GPIO_31 31 +#define C_GPIO_32 32 +#define C_GPIO_33 33 +#define L_GPIO_30 (30+L_GPIO_SHIFT_BASE) +#define L_GPIO_31 (31+L_GPIO_SHIFT_BASE) +#define L_GPIO_32 (32+L_GPIO_SHIFT_BASE) +#define GPIO_INT_USBPLUGIN (GPIO_INT_39) +#endif +#define L_GPIO_22 (22+LCD_GPIO_SHIFT_BASE) + + + +/** + @name GPIO Interrupt ID + + GPIO interrupt ID definition + + GPIO interrupt ID for interrupt related APIs. +*/ +//@{ +#define GPIO_INT_00 0 ///< GPIO INT[0]: C_GPIO[0] +#define GPIO_INT_01 1 ///< GPIO INT[1]: C_GPIO[1] +#define GPIO_INT_02 2 ///< GPIO INT[2]: C_GPIO[2] +#define GPIO_INT_03 3 ///< GPIO INT[3]: C_GPIO[3] +#define GPIO_INT_04 4 ///< GPIO INT[4]: C_GPIO[4] +#define GPIO_INT_05 5 ///< GPIO INT[5]: C_GPIO[5] +#define GPIO_INT_06 6 ///< GPIO INT[6]: C_GPIO[6] +#define GPIO_INT_07 7 ///< GPIO INT[7]: C_GPIO[7] +#define GPIO_INT_08 8 ///< GPIO INT[8]: C_GPIO[8] +#define GPIO_INT_09 9 ///< GPIO INT[9]: C_GPIO[9] +#define GPIO_INT_10 10 ///< GPIO INT[10]: C_GPIO[10] +#define GPIO_INT_11 11 ///< GPIO INT[11]: C_GPIO[11] +#define GPIO_INT_12 12 ///< GPIO INT[12]: C_GPIO[12] +#define GPIO_INT_13 13 ///< GPIO INT[13]: C_GPIO[13] +#define GPIO_INT_14 14 ///< GPIO INT[14]: C_GPIO[14] +#define GPIO_INT_15 15 ///< GPIO INT[15]: C_GPIO[15] +#define GPIO_INT_16 16 ///< GPIO INT[16]: C_GPIO[16] +#define GPIO_INT_17 17 ///< GPIO INT[17]: C_GPIO[17] +#define GPIO_INT_18 18 ///< GPIO INT[18]: C_GPIO[18] +#define GPIO_INT_19 19 ///< GPIO INT[19]: C_GPIO[19] +#define GPIO_INT_20 20 ///< GPIO INT[20]: C_GPIO[20] +#define GPIO_INT_21 21 ///< GPIO INT[21]: C_GPIO[21] +#define GPIO_INT_22 22 ///< GPIO INT[22]: C_GPIO[22] +#define GPIO_INT_23 23 ///< GPIO INT[23]: C_GPIO[23] +#define GPIO_INT_24 24 ///< GPIO INT[24]: C_GPIO[24] +#define GPIO_INT_25 25 ///< GPIO INT[25]: HSI_GPIO[0] +#define GPIO_INT_26 26 ///< GPIO INT[26]: HSI_GPIO[1] +#define GPIO_INT_27 27 ///< GPIO INT[27]: HSI_GPIO[2] +#define GPIO_INT_28 28 ///< GPIO INT[28]: HSI_GPIO[3] +#define GPIO_INT_29 29 ///< GPIO INT[29]: HSI_GPIO[4] +#define GPIO_INT_30 30 ///< GPIO INT[30]: HSI_GPIO[5] +#define GPIO_INT_31 31 ///< GPIO INT[31]: HSI_GPIO[6] +#define GPIO_INT_32 32 ///< GPIO INT[0]: HSI_GPIO[7] +#define GPIO_INT_33 33 ///< GPIO INT[1]: HSI_GPIO[8] +#define GPIO_INT_34 34 ///< GPIO INT[2]: HSI_GPIO[9] +#define GPIO_INT_35 35 ///< GPIO INT[3]: HSI_GPIO[10] +#define GPIO_INT_36 36 ///< GPIO INT[4]: HSI_GPIO[11] +#define GPIO_INT_37 37 ///< GPIO INT[5]: S_GPIO[0] +#define GPIO_INT_38 38 ///< GPIO INT[6]: S_GPIO[1] +#define GPIO_INT_39 39 ///< GPIO INT[7]: S_GPIO[2] +#define GPIO_INT_40 40 ///< GPIO INT[8]: S_GPIO[3] +#define GPIO_INT_41 41 ///< GPIO INT[9]: S_GPIO[4] +#define GPIO_INT_42 42 ///< GPIO INT[10]: S_GPIO[5] +#define GPIO_INT_43 43 ///< GPIO INT[11]: S_GPIO[6] +#define GPIO_INT_44 44 ///< GPIO INT[12]: S_GPIO[7] +#define GPIO_INT_45 45 ///< GPIO INT[13]: S_GPIO[8] +#define GPIO_INT_46 46 ///< GPIO INT[14]: P_GPIO[0] +#define GPIO_INT_47 47 ///< GPIO INT[15]: P_GPIO[1] +#define GPIO_INT_48 48 ///< GPIO INT[16]: P_GPIO[2] +#define GPIO_INT_49 49 ///< GPIO INT[17]: P_GPIO[3] +#define GPIO_INT_50 50 ///< GPIO INT[18]: P_GPIO[4] +#define GPIO_INT_51 51 ///< GPIO INT[19]: P_GPIO[5] +#define GPIO_INT_52 52 ///< GPIO INT[20]: P_GPIO[6] +#define GPIO_INT_53 53 ///< GPIO INT[21]: P_GPIO[7] +#define GPIO_INT_54 54 ///< GPIO INT[22]: P_GPIO[8] +#define GPIO_INT_55 55 ///< GPIO INT[23]: P_GPIO[9] +#define GPIO_INT_56 56 ///< GPIO INT[24]: P_GPIO[10] +#define GPIO_INT_57 57 ///< GPIO INT[25]: P_GPIO[11] +#define GPIO_INT_58 58 ///< GPIO INT[26]: P_GPIO[12] +#define GPIO_INT_59 59 ///< GPIO INT[27]: P_GPIO[13] +#define GPIO_INT_60 60 ///< GPIO INT[28]: P_GPIO[14] +#define GPIO_INT_61 61 ///< GPIO INT[29]: P_GPIO[15] +#define GPIO_INT_62 62 ///< GPIO INT[30]: P_GPIO[16] +#define GPIO_INT_63 63 ///< GPIO INT[31]: P_GPIO[17] +#define GPIO_INT_64 64 ///< GPIO INT[0]: P_GPIO[18] +#define GPIO_INT_65 65 ///< GPIO INT[1]: P_GPIO[19] +#define GPIO_INT_66 66 ///< GPIO INT[2]: P_GPIO[20] +#define GPIO_INT_67 67 ///< GPIO INT[3]: P_GPIO[21] +#define GPIO_INT_68 68 ///< GPIO INT[4]: P_GPIO[22] +#define GPIO_INT_69 69 ///< GPIO INT[5]: P_GPIO[23] +#define GPIO_INT_70 70 ///< GPIO INT[6]: P_GPIO[24] +#define GPIO_INT_71 71 ///< GPIO INT[7]: dummy +#define GPIO_INT_72 72 ///< GPIO INT[8]: DSI_GPIO[0] +#define GPIO_INT_73 73 ///< GPIO INT[9]: DSI_GPIO[1] +#define GPIO_INT_74 74 ///< GPIO INT[10]: DSI_GPIO[2] +#define GPIO_INT_75 75 ///< GPIO INT[11]: DSI_GPIO[3] +#define GPIO_INT_76 76 ///< GPIO INT[12]: DSI_GPIO[4] +#define GPIO_INT_77 77 ///< GPIO INT[13]: DSI_GPIO[5] +#define GPIO_INT_78 78 ///< GPIO INT[14]: DSI_GPIO[6] +#define GPIO_INT_79 79 ///< GPIO INT[15]: DSI_GPIO[7] +#define GPIO_INT_80 80 ///< GPIO INT[16]: DSI_GPIO[8] +#define GPIO_INT_81 81 ///< GPIO INT[17]: DSI_GPIO[9] +#define GPIO_INT_82 82 ///< GPIO INT[18]: DSI_GPIO[10] +#define GPIO_INT_83 83 ///< GPIO INT[19]: L_GPIO[0] +#define GPIO_INT_84 84 ///< GPIO INT[20]: L_GPIO[1] +#define GPIO_INT_85 85 ///< GPIO INT[21]: L_GPIO[2] +#define GPIO_INT_86 86 ///< GPIO INT[22]: L_GPIO[3] +#define GPIO_INT_87 87 ///< GPIO INT[23]: L_GPIO[4] +#define GPIO_INT_88 88 ///< GPIO INT[24]: L_GPIO[5] +#define GPIO_INT_89 89 ///< GPIO INT[25]: L_GPIO[6] +#define GPIO_INT_90 90 ///< GPIO INT[26]: L_GPIO[7] +#define GPIO_INT_91 91 ///< GPIO INT[27]: L_GPIO[8] +#define GPIO_INT_92 92 ///< GPIO INT[28]: L_GPIO[9] +#define GPIO_INT_93 93 ///< GPIO INT[29]: D_GPIO[0] +#define GPIO_INT_94 94 ///< GPIO INT[30]: D_GPIO[1] +#define GPIO_INT_95 95 ///< GPIO INT[31]: D_GPIO[2] +#define GPIO_INT_96 96 ///< GPIO INT[0]: D_GPIO[3] +#define GPIO_INT_97 97 ///< GPIO INT[1]: D_GPIO[4] +#define GPIO_INT_98 98 ///< GPIO INT[2]: D_GPIO[5] +#define GPIO_INT_99 99 ///< GPIO INT[3]: D_GPIO[6] +#define GPIO_INT_100 100 ///< GPIO INT[4]: D_GPIO[7] +#define GPIO_INT_101 101 ///< GPIO INT[5]: A_GPIO[0] +#define GPIO_INT_102 102 ///< GPIO INT[6]: A_GPIO[1] +#define GPIO_INT_103 103 ///< GPIO INT[7]: A_GPIO[2] +#define GPIO_INT_104 104 ///< GPIO INT[8]: A_GPIO[3] +#define GPIO_INT_105 105 ///< internal gpio 0 +#define GPIO_INT_106 106 ///< internal gpio 1 +#define GPIO_INT_107 107 ///< internal gpio 2 +#define GPIO_INT_108 108 ///< internal gpio 3 +#define GPIO_INT_109 109 ///< internal gpio 4 +#define GPIO_INT_110 110 ///< internal gpio 5 +#define GPIO_INT_USBWAKEUP 111 ///< USB wakeup +#define GPIO_INT_USBPLUGIN (GPIO_INT_USBWAKEUP) +#define GPIO_INT_SWTRIG GPIO_INT_110 +//@} + +// In order to backward comaptible, DGPIO is used as " GPIO_IS_DGPIO | D_GPIO_* " or "D_GPIO_*" +#define GPIO_IS_DGPIO (128) + + +// +// The general api for the GPIO device driver +// +extern void gpio_setDir(UINT32 pin, UINT32 dir); +extern UINT32 gpio_getDir(UINT32 pin); +extern void gpio_setPin(UINT32 pin); +extern void gpio_clearPin(UINT32 pin); +extern UINT32 gpio_getPin(UINT32 pin); +extern void gpio_pullSet(UINT32 pin); +extern void gpio_pullClear(UINT32 pin); +extern UINT32 gpio_readData(UINT32 dataidx); +extern void gpio_writeData(UINT32 dataidx, UINT32 value); +//extern UINT32 gpio_readDir(UINT32 dataidx); +//extern void gpio_writeDir(UINT32 dataidx, UINT32 value); +extern UINT32 dgpio_readData(void); +extern void dgpio_writeData(UINT32 value); +extern UINT32 top_get_bs(void); +//extern UINT32 dgpio_readDir(void); +//extern void dgpio_writeDir(UINT32 value); +//@} +#endif + diff --git a/board/novatek/ns02501/loader/Include/Driver/Memory.h b/board/novatek/ns02501/loader/Include/Driver/Memory.h new file mode 100755 index 000000000000..d8917e33ff9a --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/Memory.h @@ -0,0 +1,470 @@ +# ifndef _MEMORY_520_H +# define _MEMORY_520_H + +#ifndef __ASSEMBLY__ + COMMENT /* Memory Map */ /* # define BOOT_ROM_RAM_BASE_ADDR 0x20000000*/ +#endif + + +# define DRAM_BASE_ADDR (0x00000000) +# define DRAM_EXP_BASE_ADDR (DRAM_BASE_ADDR + 0x180) +# define DRAM_INT_BASE_ADDR (DRAM_BASE_ADDR + 0x200) + +# define StackSize_KNL 0x1000 /* 4KB */ +# define StackSize_INT 0x400 /* 1KB */ + +# define FAT_HEAP_BUFFER_SIZE 0xA0000//0x1E0000 //0x1E8000 +# define EXFAT_BITMAP_BUFFER_SIZE 0x20000 //0x18000 +# define LOADER_TMP_BUFFER_SIZE 0x80000 + +# define BOOT_ROM_SP_LIMIT_ADDR 0xF07D3000 +# define BOOT_ROM_SP_LIMIT_ADDR2 0xF07D4000 +# define BOOT_ROM_RAM_TEMP_ADDR 0xF0800200 +# define BOOT_ROM_CFG_TEMP_ADDR 0xF0800248 +# define BOOT_ROM_RAM_BASE_ADDR 0x00000000 +# define CC_CTRL_REG_BASE_ADDR 0xF0090000 +# define DMA2_CTRL_REG_BASE_ADDR 0xF0100000 +# define DMA2_PHY_REG_BASE_ADDR 0xF0101000 +# define GZIP_REG_BASE_ADDR 0xF0100000 +# define PR8051_REG_BASE_ADDR 0xF0100000 +# define USB_OTG_REG_BASE_ADDR 0//0xF0600000 +# define DDR_CTRL_REG_BASE_ADDR 0xF0000000 /* DDR phy base address */ +# define DDR_PHY_REG_BASE_ADDR 0xF0001000 +# define DDR_ARB_REG_BASE_ADDR 0xF0008000 +# define DMA2_ARB_REG_BASE_ADDR 0xF0108000 +# define CFE_REG_BASE_ADDR 0xF00D0000 + +# define CLOCK_GEN_REG_BASE_ADDR 0xF0020000 +# define PMU_REG_BASE_ADDR 0xF0024000 +# define TOP_CTRL_REG_BASE_ADDR 0xF0010000 +# define PAD_CTRL_REG_BASE_ADDR 0xF0030000 +# define GPIO_CTRL_REG_BASE_ADDR 0xF0070000 +# define PMC_REG_BASE 0xF00A0000 + +# define TRNG_REG_BASE_ADDR 0xF0680000 + +# define CPU_REG_BASE_ADDR 0xF0FF0000 + +# define UART0_REG_BASE_ADDR 0xF0290000 +// Real board is UART2 +# define UART2_REG_BASE_ADDR 0xF0300000 +# define SM_HOST_REG_BASE_ADDR 0xF0400000 +# define MS_HOST_REG_BASE_ADDR 0xF0410000 +# define SD_HOST1_REG_BASE_ADDR 0xF0420000 +# define SD_HOST2_REG_BASE_ADDR 0xF0500000 +# define SD_HOST3_REG_BASE_ADDR 0xF0510000 +# define SPI_CTRL_REG_BASE_ADDR 0xF0230000 +# define ETH_CTRL_REG_BASE_ADDR 0xF02B0000 +# define EFUSE_CTRL_REG_BASE_ADDR 0xF0660000 +# define TIMER_REG_BASE_ADDR 0xF0040000 +# define HRTIMER_REG_BASE_ADDR 0xF00C0000 +# define WDT_REG_BASE_ADDR 0xF0050000 +# define IPE_SRAM_BASE_ADDR 0xF0700000 +# define IPE_SRAM_BASE_SIZE 0x00020000 +# define YDCC_SRAM_BASE_ADDR 0x40000000 +# define BOOT_LOADER_TMP_BUFFER 0x00001000 +# define CHIP_REMAP_REG_OFFSET 0x00000088 +# define CPE_RTC_BASE 0xF0060000 /* RTC controller */ +# define CPE_GPIO_BASE 0xF0070000 /* GPIO controller */ +# define INTERRUPT_BASE_ADDR 0xF0080000 /* Interrupt controller */ +# define CC_BASE_ADDR 0xF0090000 /* CC controller */ +# define IOADDR_GIC_REG_BASE 0xFFD00000 /* GIC Interrupt */ +# define configARM_TIMER_BASEADDR 0xFFD00200 +# define ARM_TIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ + + +# define BOOT_ROM_RAM_TEMP_ADDR2 0xF07E8000 //Eth +# define PAD_REG_BASE 0xF0030000 +# define L2_MEM_BASE 0xFFE00000 +# define IOADDR_HVYLOAD_REG_BASE 0xF0008000 + +# define CC_CPU2_CPU1_CMDBUF_REG1 0xF0090100 //CC_CPU2_CPU1_CMDBUF_REG1 to store uboot starting address +# define CC_CPU2_CPU1_CMDBUF_REG2 0xF0090104 //CC_CPU2_CPU1_CMDBUF_REG1 has used in core2_entry.s +# define NVT_CORE2_START CC_CPU2_CPU1_CMDBUF_REG2 //core2_entry.S 's entry point + +# define ARM_TIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ +# define ARM_TIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ +# define ARM_TIMER_COUNTER_OFFSET 0x04 /**< Timer Counter Register */ +# define ARM_TIMER_CONTROL_OFFSET 0x08 /**< Timer Control Register */ +# define ARM_TIMER_ISR_OFFSET 0x0C /**< Timer Interrupt Status Register */ +# define ARM_TIMER_COUNTER_OFFSET_L 0x00 /**< Timer Counter Register */ +# define ARM_TIMER_COUNTER_OFFSET_H 0x04 /**< Timer Counter Register */ +# define ARM_TIMER_COUNTER_CMP_OFFSET_L 0x10 /**< Timer Counter Register */ +# define ARM_TIMER_COUNTER_CMP_OFFSET_H 0x14 /**< Timer Counter Register */ +# define CYGHWR_HAL_RTC_PRESCALER 1 +# define ARM_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */ +# define ARM_TIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */ +# define ARM_TIMER_CONTROL_PRESCALER_SHIFT 8 +# define ARM_TIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004 /**< Intr enable */ +# define ARM_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */ +# define ARM_TIMER_CONTROL_ENABLE_MASK 0x00000001 /**< Timer enable */ + +#define ARM_TIMER_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */ +#define CRYPTO_REG_BASE_ADDR 0xF0620000 +#define HASH_REG_BASE_ADDR 0xF0670000 +#define RSA_REG_BASE_ADDR 0xF06A0000 +#define ECDSA_REG_BASE_ADDR 0xF06C0000 + +#define CRYPTO_CONFIG_REG (CRYPTO_REG_BASE_ADDR + 0x00) +#define CRYPTO_CONTROL_REG (CRYPTO_REG_BASE_ADDR + 0x04) +#define CRYPTO_OUT_DATA_REG (CRYPTO_REG_BASE_ADDR + 0x08) +#define CRYPTO_STATUS_REG (CRYPTO_REG_BASE_ADDR + 0x0C) + +#define CRYPTO_PIO_INPUT0_REG (CRYPTO_REG_BASE_ADDR + 0x30) +#define CRYPTO_PIO_INPUT1_REG (CRYPTO_REG_BASE_ADDR + 0x34) +#define CRYPTO_PIO_INPUT2_REG (CRYPTO_REG_BASE_ADDR + 0x38) +#define CRYPTO_PIO_INPUT3_REG (CRYPTO_REG_BASE_ADDR + 0x3C) +#define CRYPTO_PIO_OUTPUT0_REG (CRYPTO_REG_BASE_ADDR + 0x40) +#define CRYPTO_PIO_OUTPUT1_REG (CRYPTO_REG_BASE_ADDR + 0x44) +#define CRYPTO_PIO_OUTPUT2_REG (CRYPTO_REG_BASE_ADDR + 0x48) +#define CRYPTO_PIO_OUTPUT3_REG (CRYPTO_REG_BASE_ADDR + 0x4C) + +// Hash +#define HASH_CONFIG_REG (HASH_REG_BASE_ADDR + 0x00) +#define HASH_PADDING_SIZE_REG (HASH_REG_BASE_ADDR + 0x04) +#define HASH_INTEN_REG (HASH_REG_BASE_ADDR + 0x08) +#define HASH_STATUS_REG (HASH_REG_BASE_ADDR + 0x0C) +#define HASH_OUTPUT_DATA1_REG (HASH_REG_BASE_ADDR + 0x70) +#define HASH_INPUT_DATA_REG (HASH_REG_BASE_ADDR + 0x90) +#define HASH_DMA_START_ADDR_REG (HASH_REG_BASE_ADDR + 0x94) +#define HASH_DMA_TX_SIZE_REG (HASH_REG_BASE_ADDR + 0x9C) +//RSA +#define RSA_CONFIG_REG (RSA_REG_BASE_ADDR + 0x00) +#define RSA_CONTROL_REG (RSA_REG_BASE_ADDR + 0x04) +#define RSA_STATUS_REG (RSA_REG_BASE_ADDR + 0x0C) +#define RSA_KEY_N_REG (RSA_REG_BASE_ADDR + 0x10) +#define RSA_KEY_N_ADDR_REG (RSA_REG_BASE_ADDR + 0x14) +#define RSA_KEY_ED_REG (RSA_REG_BASE_ADDR + 0x18) +#define RSA_KEY_ED_ADDR_REG (RSA_REG_BASE_ADDR + 0x1C) +#define RSA_DATA_REG (RSA_REG_BASE_ADDR + 0x20) +#define RSA_DATA_ADDR_REG (RSA_REG_BASE_ADDR + 0x24) +#define RSA_CRC32_DEFAULT_REG_OFS (RSA_REG_BASE_ADDR + 0x30) +#define RSA_CRC32_POLY_REG_OFS (RSA_REG_BASE_ADDR + 0x34) +#define RSA_CRC32_OUTPUT_REG_OFS (RSA_REG_BASE_ADDR + 0x38) + +// Crypto +#define CRYPTO_CONFREG_SWRST (1<<0) +#define CRYPTO_CONFREG_CRYPTO_EN (1<<1) +#define CRYPTO_CONFREG_AES128 (2<<4) +#define CRYPTO_CONFREG_DECRYPT (1<<8) + +#define CRYPTO_PIO_DONE (1<<0) + +// Hash +#define HASH_CONFREG_INITSTATE (1<<20) +#define HASH_CONFREG_SHA256 (1<<4) +#define HASH_CONFREG_ENABLE (1<<1) +#define HASH_CONFREG_DMA_MODE (1<<12) +#define HASH_CONFREG_DMA_PAD_MODE (1<<13) + +//RSA +#define RSA_ENABLE (1<<0) + +#define RSA_KEYWIDTH_256 (0x0<<1) +#define RSA_KEYWIDTH_512 (0x1<<1) +#define RSA_KEYWIDTH_1024 (0x2<<1) +#define RSA_KEYWIDTH_2048 (0x3<<1) +#define RSA_KEYWIDTH_4096 (0x4<<1) + +#define RSA_NORMAL_MODE (0x0<<4) +#define RSA_MODE_CRC_KEY_N (0x1<<4) +#define RSA_MODE_CRC_KEY_ED (0x2<<4) + + +#define RSA_TRANSFER_END (0x1<<0) +#define RSA_BUSY (0x1<<1) + +#define HASH_TRANSFER_END (0x1<<0) + +//ECDSA +#define NVT_ECDSA_TRG_REG_REG (ECDSA_REG_BASE_ADDR + 0x00) ///< ECDSA Trigger Register +#define NVT_ECDSA_STS_REG (ECDSA_REG_BASE_ADDR + 0x04) ///< ECDSA Status Register +#define NVT_ECDSA_INTEN_REG (ECDSA_REG_BASE_ADDR + 0x08) ///< ECDSA Interrupt Enable Register +#define NVT_ECDSA_SIGN_MSG_REG (ECDSA_REG_BASE_ADDR + 0x40) ///< ECDSA Signature MSG (0x6C-0x40) +#define NVT_ECDSA_PRIV_KEY_REG (ECDSA_REG_BASE_ADDR + 0x80) ///< ECDSA Private Key (0xAC-0x80) +#define NVT_ECDSA_VRIFY_S_REG (ECDSA_REG_BASE_ADDR + 0xC0) ///< ECDSA Verify S Value (0xEC-0xC0) +#define NVT_ECDSA_VPKEY_X_REG (ECDSA_REG_BASE_ADDR + 0x100) ///< ECDSA Verify Public Key X (0x12C-0x100) +#define NVT_ECDSA_VPKEY_Y_REG (ECDSA_REG_BASE_ADDR + 0x140) ///< ECDSA Verify Public Key Y (0x16C-0x140) +#define NVT_ECDSA_BASE_X_REG (ECDSA_REG_BASE_ADDR + 0x180) ///< ECC Base X (0x1AC-0x180) +#define NVT_ECDSA_BASE_Y_REG (ECDSA_REG_BASE_ADDR + 0x1C0) ///< ECC Base Y (0x1EC-0x1C0) +#define NVT_ECDSA_SIGN_R_REG (ECDSA_REG_BASE_ADDR + 0x200) ///< ECDSA Signature R Value (0x22C-0x200) +#define NVT_ECDSA_SIGN_S_REG (ECDSA_REG_BASE_ADDR + 0x240) ///< ECDSA Signature S Value (0x26C-0x240) +#define NVT_ECDSA_GPKEY_X_REG (ECDSA_REG_BASE_ADDR + 0x280) ///< ECDSA Generated Public Key X (0x2AC-0x280) +#define NVT_ECDSA_GPKEY_Y_REG (ECDSA_REG_BASE_ADDR + 0x2C0) ///< ECDSA Generated Public Key Y (0x2EC-0x2C0) +#define NVT_ECDSA_A_VALUE_REG (ECDSA_REG_BASE_ADDR + 0x300) ///< ECDSA A_Value (0x32C-0x300) +#define NVT_ECDSA_PRIME_REG (ECDSA_REG_BASE_ADDR + 0x340) ///< ECDSA Prime (0x36C-0x340) +#define NVT_ECDSA_ORDER_REG (ECDSA_REG_BASE_ADDR + 0x380) ///< ECDSA Order (0x3AC-0x380) + + + +#define TOP_CTRL_SRAM_RESET_REG0 (TOP_CTRL_REG_BASE_ADDR + 0x1000) + +//Shut down SRAM SDIO1 mask +#define TOP_SRAM_SD_SDIO1 0x20000000 +//Shut down SRAM RSA mask +#define TOP_SRAM_SD_RSA 0x800 + + +#define reg0_cache_type_ofs 0x004 //reg0_cache_type +#define CACHE_CTRL_REG_OFS 0x100 +#define CACHE_AUX_CTRL_REG_OFS 0x104 + +#define CACHE_TAG_RAM_CTRL_OFS 0x108 +#define CACHE_DATA_RAM_CTRL_OFS 0x10C + + +#define reg2_int_clear_ofs 0x220 //reg2_int_clear +#define reg7_cache_sync 0x730 //reg7_cache_sync +#define reg7_inv_way 0x77C //reg7_inv_way + +#define CACHE_PREFETCH_REG_OFS 0xF60 + +#define L2_REG0_BASE (L2_MEM_BASE + 0x000) /* Cache ID and Cache Type */ +#define L2_REG1_BASE (L2_MEM_BASE + 0x100) /* Control */ +#define L2_REG2_BASE (L2_MEM_BASE + 0X200) /* Interrupt and Counter Control Registers */ +#define L2_REG7_BASE (L2_MEM_BASE + 0x700) /* Cache Maintenance Operations */ +#define L2_REG9_BASE (L2_MEM_BASE + 0x900) /* Cache Lockdown */ +#define L2_REG12_BASE (L2_MEM_BASE + 0xC00) /* Address Filtering */ +#define L2_REG15_BASE (L2_MEM_BASE + 0xF00) /* Debug, Prefetch and Power */ + +/** + * Cache ID and Cache Type + */ +#define L2_REG0_CACHE_ID (*((volatile unsigned long *)(L2_REG0_BASE + 0x00))) +#define L2_REG0_CACHE_TYPE (*((volatile unsigned long *)(L2_REG0_BASE + 0x04))) + +#define S_L2_REG0_CACHE_TYPE_DB (31) +#define M_L2_REG0_CACHE_TYPE_DB (0xf << S_L2_REG0_CACHE_TYPE_DB) +#define S_L2_REG0_CACHE_TYPE_CTYPE (25) +#define M_L2_REG0_CACHE_TYPE_CTYPE (0xf << S_L2_REG0_CACHE_TYPE_CTYPE) +#define S_L2_REG0_CACHE_TYPE_H (24) +#define M_L2_REG0_CACHE_TYPE_H (0x1 << S_L2_REG0_CACHE_TYPE_H) +#define S_L2_REG0_CACHE_TYPE_DWS (20) +#define M_L2_REG0_CACHE_TYPE_DWS (0x7 << S_L2_REG0_CACHE_TYPE_DWS) +#define S_L2_REG0_CACHE_TYPE_DA (18) +#define M_L2_REG0_CACHE_TYPE_DA (0x1 << S_L2_REG0_CACHE_TYPE_DA) +#define S_L2_REG0_CACHE_TYPE_DLS (12) +#define M_L2_REG0_CACHE_TYPE_DLS (0x3 << S_L2_REG0_CACHE_TYPE_DLS) +#define S_L2_REG0_CACHE_TYPE_IWS (8) +#define M_L2_REG0_CACHE_TYPE_IWS (0x7 << S_L2_REG0_CACHE_TYPE_IWS) +#define S_L2_REG0_CACHE_TYPE_IA (6) +#define M_L2_REG0_CACHE_TYPE_IA (0x1 << S_L2_REG0_CACHE_TYPE_IA) +#define S_L2_REG0_CACHE_TYPE_ILS (0) +#define M_L2_REG0_CACHE_TYPE_ILS (0x3 << S_L2_REG0_CACHE_TYPE_ILS) + +#define K_L2_REG0_CACHE_TYPE_DA_16WAY (1) +#define K_L2_REG0_CACHE_TYPE_DA_8WAY (0) + +/** + * Control + */ +#define L2_REG1_CONTROL (*((volatile unsigned long *)(L2_REG1_BASE + 0x00))) +#define L2_REG1_AUX_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x04))) +#define L2_REG1_TAG_RAM_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x08))) +#define L2_REG1_DATA_RAM_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x0C))) + +#define S_L2_REG1_CONTROL_EN (0) +#define M_L2_REG1_CONTROL_EN (0x1 << S_L2_REG1_CONTROL_EN) + +#define K_L2_REG1_CONTROL_EN_ON 1 +#define K_L2_REG1_CONTROL_EN_OFF 0 + +#define S_L2_REG1_AUX_CTRL_BRESP (30) +#define M_L2_REG1_AUX_CTRL_BRESP (0x1 << S_L2_REG1_AUX_CTRL_BRESP) +#define S_L2_REG1_AUX_CTRL_INSTR_PREF (29) +#define M_L2_REG1_AUX_CTRL_INSTR_PREF (0x1 << S_L2_REG1_AUX_CTRL_INSTR_PREF) +#define S_L2_REG1_AUX_CTRL_DATA_PERF (28) +#define M_L2_REG1_AUX_CTRL_DATA_PERF (0x1 << S_L2_REG1_AUX_CTRL_DATA_PERF) +#define S_L2_REG1_AUX_CTRL_NS_INT_CTRL (27) +#define M_L2_REG1_AUX_CTRL_NS_INT_CTRL (0x1 << S_L2_REG1_AUX_CTRL_NS_INT_CTRL) +#define S_L2_REG1_AUX_CTRL_NS_LOCK_EN (26) +#define M_L2_REG1_AUX_CTRL_NS_LOCK_EN (0x1 << S_L2_REG1_AUX_CTRL_NS_LOCK_EN) +#define S_L2_REG1_AUX_CTRL_CACHE_POLICY (25) +#define M_L2_REG1_AUX_CTRL_CACHE_POLICY (0x1 << S_L2_REG1_AUX_CTRL_CACHE_POLICY) +#define S_L2_REG1_AUX_CTRL_FORCE_WA (23) +#define M_L2_REG1_AUX_CTRL_FORCE_WA (0x3 << S_L2_REG1_AUX_CTRL_FORCE_WA) +#define S_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN (22) +#define M_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN (0x1 << S_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN) +#define S_L2_REG1_AUX_CTRL_PARITY_EN (21) +#define M_L2_REG1_AUX_CTRL_PARITY_EN (0x1 << S_L2_REG1_AUX_CTRL_PARITY_EN) +#define S_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN (20) +#define M_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN (0x1 << S_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN) +#define S_L2_REG1_AUX_CTRL_WAT_SIZE (17) +#define M_L2_REG1_AUX_CTRL_WAT_SIZE (0x7 << S_L2_REG1_AUX_CTRL_WAT_SIZE) +#define S_L2_REG1_AUX_CTRL_ASSOCIATIVITY (16) +#define M_L2_REG1_AUX_CTRL_ASSOCIATIVITY (0x1 << S_L2_REG1_AUX_CTRL_ASSOCIATIVITY) +#define S_L2_REG1_AUX_CTRL_SHARED_INV_EN (13) +#define M_L2_REG1_AUX_CTRL_SHARED_INV_EN (0x1 << S_L2_REG1_AUX_CTRL_SHARED_INV_EN) +#define S_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF (12) +#define M_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF (0x1 << S_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF) +#define S_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN (11) +#define M_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN (0x1 << S_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN) +#define S_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN (10) +#define M_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN (0x1 << S_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN) +#define S_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN (0) +#define M_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN (0x1 << S_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN) + +/** + * Interrupt and Counter Control Registers + */ +#define L2_REG2_EV_CNT_CTRL (*((volatile unsigned long *)(L2_REG2_BASE + 0x00))) +#define L2_REG2_EV_CNT1_CFG (*((volatile unsigned long *)(L2_REG2_BASE + 0x04))) +#define L2_REG2_EV_CNT0_CFG (*((volatile unsigned long *)(L2_REG2_BASE + 0x08))) +#define L2_REG2_EV_CNT1 (*((volatile unsigned long *)(L2_REG2_BASE + 0x0C))) +#define L2_REG2_EV_CNT0 (*((volatile unsigned long *)(L2_REG2_BASE + 0x10))) +#define L2_REG2_INT_MASK (*((volatile unsigned long *)(L2_REG2_BASE + 0x14))) +#define L2_REG2_INT_MASK_STATUS (*((volatile unsigned long *)(L2_REG2_BASE + 0x18))) +#define L2_REG2_INT_RAW_STATUS (*((volatile unsigned long *)(L2_REG2_BASE + 0x1C))) +#define L2_REG2_INT_CLEAR (*((volatile unsigned long *)(L2_REG2_BASE + 0x20))) + +#define S_L2_REG2_INT_DECERR (8) +#define M_L2_REG2_INT_DECERR (0x1 << S_L2_REG2_INT_DECERR) /* Decode error */ +#define S_L2_REG2_INT_SLVERR (7) +#define M_L2_REG2_INT_SLVERR (0x1 << S_L2_REG2_INT_SLVERR) /* Slave error */ +#define S_L2_REG2_INT_ERRRD (6) +#define M_L2_REG2_INT_ERRRD (0x1 << S_L2_REG2_INT_ERRRD) /* Data RAM read error */ +#define S_L2_REG2_INT_ERRRT (5) +#define M_L2_REG2_INT_ERRRT (0x1 << S_L2_REG2_INT_ERRRT) /* Tag RAM read error */ +#define S_L2_REG2_INT_ERRWD (4) +#define M_L2_REG2_INT_ERRWD (0x1 << S_L2_REG2_INT_ERRWD) /* Data RAM write error */ +#define S_L2_REG2_INT_ERRWT (3) +#define M_L2_REG2_INT_ERRWT (0x1 << S_L2_REG2_INT_ERRWT) /* Tag RAM write error */ +#define S_L2_REG2_INT_PARRD (2) +#define M_L2_REG2_INT_PARRD (0x1 << S_L2_REG2_INT_PARRD) /* Parity error on data RAM read */ +#define S_L2_REG2_INT_PARRT (1) +#define M_L2_REG2_INT_PARRT (0x1 << S_L2_REG2_INT_PARRT) /* Pariry error on tag RAM read */ +#define S_L2_REG2_INT_ECNTR (0) +#define M_L2_REG2_INT_ECNTR (0x1 << S_L2_REG2_INT_ECNTR) /* Event counter1/0 overflow increment */ + +/** + * Cache Maintenance Operations + */ +#define L2_REG7_CACHE_SYNC (*((volatile unsigned long *)(L2_REG7_BASE + 0x30))) +#define L2_REG7_INV_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0x70))) +#define L2_REG7_INV_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0x7C))) +#define L2_REG7_CLEAN_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0xB0))) +#define L2_REG7_CLEAN_INDEX (*((volatile unsigned long *)(L2_REG7_BASE + 0xB8))) +#define L2_REG7_CLEAN_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0xBC))) +#define L2_REG7_CLEAN_INV_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0xF0))) +#define L2_REG7_CLEAN_INV_INDEX (*((volatile unsigned long *)(L2_REG7_BASE + 0xF8))) +#define L2_REG7_CLEAN_INV_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0xFC))) + + +#define K_L2_REG7_CACHE_SYNC_C (0x1) + +#define K_L2_REG7_INV_WAY_8WAY (0x00ff) +#define K_L2_REG7_INV_WAY_16WAY (0xffff) +#define K_L2_REG7_CLEAN_WAY_8WAY (0x00ff) +#define K_L2_REG7_CLEAN_WAY_16WAY (0xffff) + + +/** + * Cache Lockdown + */ +#define L2_REG9_D_LOCKDOWN0 (*((volatile unsigned long *)(L2_REG9_BASE + 0x00))) +#define L2_REG9_I_LOCKDOWN0 (*((volatile unsigned long *)(L2_REG9_BASE + 0x04))) +#define L2_REG9_D_LOCKDOWN1 (*((volatile unsigned long *)(L2_REG9_BASE + 0x08))) +#define L2_REG9_I_LOCKDOWN1 (*((volatile unsigned long *)(L2_REG9_BASE + 0x0C))) +#define L2_REG9_D_LOCKDOWN2 (*((volatile unsigned long *)(L2_REG9_BASE + 0x10))) +#define L2_REG9_I_LOCKDOWN2 (*((volatile unsigned long *)(L2_REG9_BASE + 0x14))) +#define L2_REG9_D_LOCKDOWN3 (*((volatile unsigned long *)(L2_REG9_BASE + 0x18))) +#define L2_REG9_I_LOCKDOWN3 (*((volatile unsigned long *)(L2_REG9_BASE + 0x1C))) +#define L2_REG9_D_LOCKDOWN4 (*((volatile unsigned long *)(L2_REG9_BASE + 0x20))) +#define L2_REG9_I_LOCKDOWN4 (*((volatile unsigned long *)(L2_REG9_BASE + 0x24))) +#define L2_REG9_D_LOCKDOWN5 (*((volatile unsigned long *)(L2_REG9_BASE + 0x28))) +#define L2_REG9_I_LOCKDOWN5 (*((volatile unsigned long *)(L2_REG9_BASE + 0x2C))) +#define L2_REG9_D_LOCKDOWN6 (*((volatile unsigned long *)(L2_REG9_BASE + 0x30))) +#define L2_REG9_I_LOCKDOWN6 (*((volatile unsigned long *)(L2_REG9_BASE + 0x34))) +#define L2_REG9_D_LOCKDOWN7 (*((volatile unsigned long *)(L2_REG9_BASE + 0x38))) +#define L2_REG9_I_LOCKDOWN7 (*((volatile unsigned long *)(L2_REG9_BASE + 0x3C))) +#define L2_REG9_LOCK_LINE_EN (*((volatile unsigned long *)(L2_REG9_BASE + 0x50))) +#define L2_REG9_UNLOCK_WAY (*((volatile unsigned long *)(L2_REG9_BASE + 0x54))) + +/** + * Address Filtering + */ +#define L2_REG12_ADDR_FILTERING_START (*((volatile unsigned long *)(L2_REG12_BASE + 0x00))) +#define L2_REG12_ADDR_FILTERING_END (*((volatile unsigned long *)(L2_REG12_BASE + 0x04))) + +/** + * Debug, Prefetch and Power + */ +#define L2_REG15_DEBUG_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x40))) +#define L2_REG15_PREF_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x60))) +#define L2_REG15_POWER_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x80))) + +#define S_L2_REG15_DEBUG_CTRL_SPNIDEN (2) +#define M_L2_REG15_DEBUG_CTRL_SPNIDEN (0x1 << S_L2_REG15_DEBUG_CTRL_SPNIDEN) +#define S_L2_REG15_DEBUG_CTRL_DWB (1) +#define M_L2_REG15_DEBUG_CTRL_DWB (0x1 << S_L2_REG15_DEBUG_CTRL_DWB) +#define S_L2_REG15_DEBUG_CTRL_DCL (0) +#define M_L2_REG15_DEBUG_CTRL_DCL (0x1 << S_L2_REG15_DEBUG_CTRL_DCL) + +#define S_L2_REG15_PREF_CTRL_DL_FILL_EN (30) +#define M_L2_REG15_PREF_CTRL_DL_FILL_EN (0x1 << S_L2_REG15_PREF_CTRL_DL_FILL_EN) +#define S_L2_REG15_PREF_CTRL_INST_PREF_EN (29) +#define M_L2_REG15_PREF_CTRL_INST_PREF_EN (0x1 << S_L2_REG15_PREF_CTRL_INST_PREF_EN) +#define S_L2_REG15_PREF_CTRL_DATA_PREF_EN (28) +#define M_L2_REG15_PREF_CTRL_DATA_PREF_EN (0x1 << S_L2_REG15_PREF_CTRL_DATA_PREF_EN) +#define S_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS (27) +#define M_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS (0x1 << S_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS) +#define S_L2_REG15_PREF_CTRL_PREF_DROP_EN (24) +#define M_L2_REG15_PREF_CTRL_PREF_DROP_EN (0x1 << S_L2_REG15_PREF_CTRL_PREF_DROP_EN) +#define S_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN (23) +#define M_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN (0x1 << S_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN) +#define S_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN (21) +#define M_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN (0x1 << S_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN) +#define S_L2_REG15_PREF_CTRL_PREF_OFF (0) +#define M_L2_REG15_PREF_CTRL_PREF_OFF (0xf << S_L2_REG15_PREF_CTRL_PREF_OFF) + +// DDR phy duty configuration register bit +#define DDR_PHY_INCREASE_DUTY 0x40 // P < N +#define DDR_PHY_DECREASE_DUTY 0x00 // P > N +#define DDR_PHY_DUTY_TYPE_MSK 0x40 // bit mask for increase/decrease duty +#define DDR_PHY_CLK_ADJ_EN 0x80 + +// DDR phy duty calibration control register bit +#define DDR_PHY_CLK_OP_ONGOING 0x10 +#define DDR_PHY_CLK_OP_DONE 0x00 +#define DDR_PHY_DQS_OP_ONGOING 0x20 +#define DDR_PHY_DQS_OP_DONE 0x00 + + +# define DDR_PHY_CAL_CLK_ADJ_OFS 0x000 /* 0x00 */ +# define DDR_PHY_CAL_CMD_ADJ_OFS 0x01C /* 0x1C */ +# define DDR_PHY_CAL_CTRL_OFS 0x150 /* 0x54 */ +# define DDR_PHY_CAL_CLK_CFG_OFS 0x154 /* 0x55 */ +# define DDR_PHY_CAL_DQS_CFG_OFS 0x158 /* 0x56 */ +# define DDR_PHY_CAL_DTY_CNT_LB_OFS 0x15C /* 0x57 duty cnt low byte */ +# define DDR_PHY_CAL_DTY_CNT_HB_OFS 0x160 /* 0x58 duty cnt high byte */ +# define DDR_PHY_CAL_DQS0_ADJ_OFS 0x1D0 /* 0x1D0 */ +# define DDR_PHY_CAL_DQ_ADJ_OFS 0x1D4 /* 0x1D0 */ + + +#define BOOT_SOURCE_SPI 0x00 +#define BOOT_SOURCE_CARD 0x01 +#define BOOT_SOURCE_SPI_NAND_2K 0x02 +#define BOOT_SOURCE_SPI_NAND_RS_2K 0x03 +#define BOOT_SOURCE_ETHERNET 0x04 +#define BOOT_SOURCE_USB 0x05 +#define BOOT_SOURCE_SPI_NAND_4K 0x06 +#define BOOT_SOURCE_BMC 0x07 +#define BOOT_SOURCE_EMMC_4BIT 0x08 +#define BOOT_SOURCE_EMMC_8BIT 0x09 +#define BOOT_SOURCE_SPI_NAND_RS_4K 0x0A +#define BOOT_SOURCE_USB_FULL 0x0B + +#define BOOT_SOURCE_MSK 0x0F + + +# define IDENTIFY_ERR 2 +# define MBR_ERR 3 +# define PBR_ERR 4 +# define READ512_ERR 5 +# define READ_ERR 7 +# define HPA_ERR 8 +# define CHECKSUM_ERR 9 +#ifndef __ASSEMBLY__ + END +#endif +# endif diff --git a/board/novatek/ns02501/loader/Include/Driver/cfe.h b/board/novatek/ns02501/loader/Include/Driver/cfe.h new file mode 100755 index 000000000000..6a5826a01ec4 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/cfe.h @@ -0,0 +1,116 @@ +/** + cfe module driver. + + This file is the driver of config engine module. + + @file cfe.h + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2023. All rights reserved. +*/ + +#ifndef _CFE_DEF_ +#define _CFE_DEF_ + +#include "IOReg.h" + +typedef enum { + I2C = 0x10, + I2C2 = 0x11, + I2C3 = 0x12, + SPI = 0x20, + SPI2 = 0x21, + SPI3 = 0x22, + SIF = 0x40, + SIF2 = 0x41, + SIF3 = 0x42, + SIF4 = 0x43, +} AUTO_DESC_INTF; + +typedef enum { + CFE_RUNNING = 0, + CFE_END, + CFE_CMD_NOT_SUP, + CFE_POL_TOUT, + CFE_I2C_NACK, + CFE_DES_ERR, + CFE_NEVER_USED, +} CFE_STATUS; + +/* ------------------------------------------------------------------------------- + * API + * ------------------------------------------------------------------------------- + */ + // code_sram: + // 0 -> config engine sram (2KB) + // other -> set other sram base address, exp: IFE(0xf07c0000) +void cfe_open(UINT32 code_sram); +void cfe_close(void); +void cfe_trig(void); + +// write data to address +void cfe_write_reg(UINT32 address, UINT32 data); + +// read data from address +// write (data | read_data) to address +void cfe_mask_set(UINT32 address, UINT32 data); + +// read data from address +// write ( !(data) & read_data) to address +void cfe_mask_clear(UINT32 address, UINT32 data); + +// delay 1/120M*cycle +void cfe_delay(UINT32 cycle); + +// read data from address +// loop if(read_data & mask) neq 0 +void cfe_mask_poll_0(UINT32 address, UINT32 mask); + +// read data from address +// loop if(read_data | (!mask)) neq 0xffffffff +void cfe_mask_poll_1(UINT32 address, UINT32 mask); + + +void cfe_auto_desc(UINT32 desc_ddress, AUTO_DESC_INTF interface_sel); + +// read address 32bit data to tmp +// tmp: 0~3 +void cfe_read_reg(UINT32 tmp, UINT32 address); + +// tmp = tmp & value +// tmp: 0~3 +void cfe_and(UINT32 tmp, UINT32 value); + +// tmp = tmp | value +// tmp: 0~3 +void cfe_or(UINT32 tmp, UINT32 value); + +// write tmp to address +// tmp: 0~3 +void cfe_write_tmp(UINT32 tmp, UINT32 address); + +// copy register from source to dest +void cfe_copy_reg(UINT32 source, UINT32 dest); + +// Read data from address +// Write (data ^ read_data) to address +void cfe_xor_set(UINT32 address, UINT32 data); + +// wait config engine finish +void cfe_wait_end(void); + +// get status +// 0: still running +// 1: end +// 2: command not support +// 3: polling timeout +// 4: i2c nack +// 5: des err +// 6: not used +CFE_STATUS cfe_get_status(void); + + +//for test +void cfe_test(void); +#endif + diff --git a/board/novatek/ns02501/loader/Include/Driver/crypto.h b/board/novatek/ns02501/loader/Include/Driver/crypto.h new file mode 100755 index 000000000000..e4230a6a7fb0 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/crypto.h @@ -0,0 +1,103 @@ +/** + Header file for CC (Core Communicator) module. + + This file is the header file that define the API and data type + for CC module. + + @file CC.h + @ingroup mIDrvSys_CC + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ + +#include "constant.h" + +#ifndef _CRYPTO_H +#define _CRYPTO_H + +#define ROM_AES_SIZE (16) +#define ROM_SHA_SIZE (32) // unit: byte +#define ROM_RSA_SIZE (256) // RSA-2048 +#define ROM_RSA_EKEY_SIZE (32) +#define ROM_RSA_CRC32_SIZE (4) +/** + Crypto engine crypto mode +*/ +typedef enum { + CRYPTO_RSV0, + CRYPTO_RSV1, + CRYPTO_AES, ///< Select Crypto mode AES + CRYPTO_MODE_NUM, +} CRYPTO_MODE; + +/** + Crypto engine crypto Operating mode +*/ +typedef enum { + CRYPTO_EBC = 0x00, ///< Select Crypto opmode EBC + CRYPTO_CBC, ///< Select Crypto opmode CBC + CRYPTO_OPMODE_NUM, +} CRYPTO_OPMODE; + +/** + Crypto engine encrypt or decrypt +*/ +typedef enum { + CRYPTO_ENCRYPT = 0x00, ///< Select Crypto engine encrypt + CRYPTO_DECRYPT, ///< Select Crypto engine decrypt + CRYPTO_TYPE_NUM, + +} CRYPTO_TYPE; + +typedef enum { + EFUSE_OTP_1ST_KEY_SET_FIELD = 0x0, // This if for secure boot + EFUSE_OTP_2ND_KEY_SET_FIELD, + EFUSE_OTP_3RD_KEY_SET_FIELD, + EFUSE_OTP_4TH_KEY_SET_FIELD, + + EFUSE_OTP_TOTAL_KEY_SET_FIELD, +} EFUSE_OTP_KEY_SET_FIELD; + +typedef struct _CRYPT_OP { + CRYPTO_OPMODE op_mode; ///< Operation Mode (now support ECB/CBC) + CRYPTO_TYPE en_de_crypt; ///< Encrypt or decrypt (CRYPTO_ENCRYPT or CRYPTO_DECRYPT) + UINT32 src_addr; ///< Source address + UINT32 dst_addr; ///< Destination address + UINT32 length; ///< length + UINT32 iv_init_en; ///< iv init enable + UINT32 iv[4]; //< iv +} CRYPT_OP; + +/** + Crypto engine check +*/ +typedef enum { + SECUREBOOT_SECURE_EN = 0x00, ///< Quary if secure enable or not + SECUREBOOT_DATA_AREA_ENCRYPT, ///< Quary if data area encrypt to cypher text or not + SECUREBOOT_SIGN_RSA, ///< Quary if Signature methed is RSA or not(AES) + SECUREBOOT_SIGN_RSA_CHK, ///< Quary if Signature hash checksum RSA key correct or not + SECUREBOOT_STATUS_NUM, + +} SECUREBOOT_STATUS; + +#define is_secure_enable() quary_secure_boot(SECUREBOOT_SECURE_EN) //For backward compatitable +#define is_data_area_encrypted() quary_secure_boot(SECUREBOOT_DATA_AREA_ENCRYPT) //For backward compatitable +#define is_signature_rsa() quary_secure_boot(SECUREBOOT_SIGN_RSA) //For backward compatitable +#define is_signature_aes() !quary_secure_boot(SECUREBOOT_SIGN_RSA) //For backward compatitable +BOOL quary_secure_boot(SECUREBOOT_STATUS scu_status); +UINT32 crypto_data_operation(EFUSE_OTP_KEY_SET_FIELD key_set, CRYPT_OP crypt_op_param); +void rsa_setConfig(UINT32 mode); +void rsa_setkey_n(UINT8* key, UINT32 len, UINT32 sram_size); +void rsa_setkey_ed(UINT8* key, UINT32 len, UINT32 sram_size); +INT32 rsa_pio_enable(UINT8* data, UINT32 len, UINT32 sram_size); +void rsa_getOutput(UINT8 * Output, UINT32 len, UINT32 sram_size); + +void shahw( const unsigned char *input, int ilen, UINT32 output[8]); +void shahw_dma(const unsigned char *input, int ilen, UINT32 output[8]); +void rsa_decrypt(UINT32 *input ,UINT32 input_len, UINT32 *pRSAN, UINT32 RSAN_len, UINT32 *pRSAED, UINT32 RSAED_len , UINT32 *pShaOut); +BOOL rsa_keycheck(UINT32 *input , BOOL efuseCheck); + +BOOL ecdsa_verify(UINT32 *hash_msg, UINT32 *pub_x, UINT32 *pub_y, UINT32 *sign_r, UINT32 *sign_s); + +#endif diff --git a/board/novatek/ns02501/loader/Include/Driver/kdrv_videoydcc.h b/board/novatek/ns02501/loader/Include/Driver/kdrv_videoydcc.h new file mode 100755 index 000000000000..ea7bf180c0d3 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/kdrv_videoydcc.h @@ -0,0 +1,193 @@ +#ifndef __KDRV_VIDEOYDCC_H__ +#define __KDRV_VIDEOYDCC_H__ + +/* Limit + */ +#define YDCC12_MAX_WIDTH 2880 +#define YDCC12_MAX_HEIGHT 2880 + +#define YDCC8_MAX_WIDTH 640 +#define YDCC8_MAX_HEIGHT 640 + +#define YDCC_ALIGN8(x) ((((x) + 7) >> 3) << 3) +#define YDCC8_DEC_W(x) YDCC_ALIGN8(x) +#define YDCC8_DEC_H(x) YDCC_ALIGN8(x) +#define YDCC8_DEC_RGGB_LOS(x) YDCC_ALIGN8(x) /* 8x */ +#define YDCC8_DEC_Y_WIDTH(x) YDCC_ALIGN8((x)/2) +#define YDCC8_DEC_Y_HEIGHT(x) (YDCC_ALIGN8(x)/2) +#define YDCC8_DEC_Y_LOS(x) YDCC_ALIGN8(YDCC8_DEC_Y_WIDTH(x)) /* frm width/2 and align8 */ + +#define YDCC8_ADDR_SIZE_MASK(x) ((x) & 0x3F) + +#define YDCC12_DEC_W(x) YDCC_ALIGN8(x) +#define YDCC12_DEC_H(x) YDCC_ALIGN8(x) +#define YDCC12_DEC_RGGB_LOS(x) YDCC_ALIGN8(((YDCC12_DEC_W(x) * 3) >> 1)) /* 12bits, final align8 */ +#define YDCC12_DEC_Y_WIDTH(x) YDCC_ALIGN8((x)/2) +#define YDCC12_DEC_Y_HEIGHT(x) (YDCC_ALIGN8(x)/2) +#define YDCC12_DEC_Y_LOS(x) YDCC_ALIGN8(YDCC12_DEC_Y_WIDTH(x)) +#define YDCC12_ADDR_SIZE_MASK(x) ((x) & 0x7F) + +/* no align need */ +#define YDCC12_ENC_W(x) (x) +#define YDCC12_ENC_H(x) (x) + +typedef struct { + unsigned int addr_pa; + unsigned int addr_va; + unsigned int size; +} YDCC_ADDR_INFO; + +typedef enum { + VDOYDCC_SET_INIT = 0, ///< set init info, YDCC_INIT_PARAM. Must be set first. + VDOYDCC_SET_ENC_ADDR, ///< YDCC_ENC_ADDR + VDOYDCC_SET_DEC_ADDR, ///< YDCC_DEC_ADDR + VDOYDCC_SET_ENC_PARAM, ///< set encode parameters, YDCC_ENCODE_PARAM + VDOYDCC_SET_DEC_PARAM, ///< set decode parameters, YDCC_DECODE_PARAM + VDOYDCC_SET_DEC_LOS, ///< set decode line offset. YDCC_DEC_LOS. It is optional. + VDOYDCC_SET_DITH_SEED, ///< for emulation purpose. YDCC_DEC_DITH_SEED + VDOYDCC_SET_SRAM_BUF_INFO, ///< for sram start address and its size. SRAM_BUF_INFO. It is optional. + VDOYDCC_SET_QTBL, ///< for q-table. YDCC_QTBL. used by enc12. + VDOYDCC_SET_GAMMA_TBL, ///< GAMMA_TBL. rggb2mcu(). m0 = (((gamma_tbl[tmp+1] - gamma_tbl[tmp]) * (m0 % 128)) >> 7) + gamma_tbl[tmp]; + VDOYDCC_SET_SIE_FIRE_CB_FUNC, ///< YDCC_CALLBACK_FUNC. used for emulation code that tigger encode followed by sie trigger + VDOYDCC_SET_TIMEOUT_VAL, ///< set timeout value for all encoder/decoder. YDCC_TIMEOUT_VAL + YDOYDCC_SET_AUTOGATING, ///< set auto gating. 1 indicate ON, 0:OFF + YDOYDCC_SET_QP_VALUE, ///< set qp value, from 1 ~ 100, ENC12_QP_VAL + VDOYDCC_GET_WH, ///< get engine type, YDCC_CODEC_ENG + VDOYDCC_GET_DEC_PARAM, ///< get decode param, YDCC_DECODE_PARAM + VDOYDCC_GET_DBG_INFO, ///< get checksum, YDCC_DBG_INFO + VDOYDCC_GET_DEC_LOS, ///< get current line-offset, YDCC_DEC_LOS + VDOYDCC_GET_ENC12_BS_SZ, ///< get encode bs size +} KDRV_VDOYDCC_PARAM_ID; + +typedef enum { + YDCC12_FMT_RGGB = 0, + YDCC12_FMT_GRGB, + YDCC12_FMT_GBRG, + YDCC12_FMT_BGGR, +} YDCC12_FMT; + +typedef enum { + YDCC_DEC_RGGB = 0x1, + YDCC_DEC_Y_ONLY = 0x2, + YDCC_DEC_BOTH = (YDCC_DEC_RGGB | YDCC_DEC_Y_ONLY), +} YDCC_DEC_MODE; + +typedef struct { + unsigned int sram_buf_addr; + unsigned int sram_size; +} SRAM_BUF_INFO; + +typedef struct { + /* source is from SIE */ + YDCC_ADDR_INFO bs_out_addr; ///< Output address of bitstream out (YDCC12 Encode). It is SRAM address. 64 align of enc8/dec8. 128 align for enc12/dec12. +} YDCC_ENC_ADDR; + +typedef struct { + unsigned char bypass_mode; ///< 0: off, 1: enable YDCC12 bypass mode. + unsigned char gamma_correction; ///< 0: disable gamma correction. 1: enable gamma correction + YDCC12_FMT input_fmt; ///< Format of YDCC12 Encode input data +} YDCC_ENCODE_PARAM; + +typedef struct { + unsigned int dec_lofs_rggb; ///< rggb buffer line offset + unsigned int dec_lofs_y; ///< y buffer line offset +} YDCC_DEC_LOS; + +typedef struct { + unsigned short width; ///< 0xC, max:2880 + unsigned short height; +} YDCC_INIT_PARAM; + +typedef struct { + unsigned char qp_val; /* 1 ~ 100 */ +} ENC12_QP_VAL; + +typedef struct { + unsigned int dithering_seed; +} YDCC_DEC_DITH_SEED; + +typedef struct { + unsigned int timeout_value; /* mclk unit */ +} YDCC_TIMEOUT_VAL; + +/* change MSB-5 bits,thus totally 32 entries */ +typedef struct { + unsigned int gm_tbl[16]; /* 11:0 GM_TBL[2N], 23:12 GM_TBL[2N+1], N: 0 ~ 15 */ + unsigned int gm_tbl_16; /* 11:0 GM_TBL[32] */ +} GAMMA_TBL; + +/* don't change order. */ +typedef enum { + YDCC_ENG_ENC12 = 0, /* ydcc encode 12bits */ + YDCC_ENG_MAX, +} YDCC_ENG_TYPE; + +/* VDOYDCC_SET_SIE_FIRE_CB_FUNC */ +typedef struct { + int (*callback)(void *data); + unsigned int usr_data; +} YDCC_CALLBACK_FUNC; + +/*! + * @fn int kdrv_videoydcc_open(unsigned int chip, unsigned int engine) + * @brief open hardware engine + * @param chip the chip id of hardware + * @param engine the engine id YDCC_ENG_TYPE of hardware + * @return return 0 on success, -1 on error + */ +int kdrv_videoydcc_open(unsigned int chip, unsigned int engine); + +/*! + * @fn int kdrv_videoydcc_close(unsigned int chip, unsigned int engine) + * @brief close hardware engine + * @param chip the chip id of hardware + * @param engine the engine id of hardware + * @return return 0 on success, -1 on error + */ +int kdrv_videoydcc_close(unsigned int handle); + +/*! + * @fn int kdrv_videoydcc_get(unsigned int handle, DEC_ID id, void *param) + * @brief set parameters to hardware engine + * @param handler the handler of hardware + * @param id the id of parameters + * @param param the parameters + * @return return 0 on success, -1 on error + */ +int kdrv_videoydcc_get(unsigned int handle, KDRV_VDOYDCC_PARAM_ID parm_id, void *param); + +/*! + * @fn int kdrv_videoydcc_set(KDRV_VDODEC_ID handler, DEC_ID id, void *param) + * @brief get parameters to hardware engine + * @param handler the handler of hardware + * @param id the id of parameters + * @param param the parameters + * @return return 0 on success, -1 on error + */ +int kdrv_videoydcc_set(unsigned int handle, KDRV_VDOYDCC_PARAM_ID parm_id, void *param); + +typedef enum { + YDCC_STS_OK = 0, + YDCC_STS_FAIL = -1, + YDCC_BS_OVERFLOW = -2, + YDCC_BS_VLC_OVERFLOW = -3, + YDCC_BS_OVERSIZE = -4, + YDCC_STS_TIMEOUT = -5, + YDCC_STS_HW_BUSY = -6, + YDCC_STS_NOT_FRAME_DONE = -7, + YDCC_STS_SIE_TRIG_FAIL = -8, + YDCC_OTHERS = -100, +} YDCC_STS; + +/*! + * @fn YDCC_STS kdrv_videoydcc_trigger(KDRV_VDODEC_ID handler) + * @brief trigger hardware engine + * @param handler the handler of hardware + * @param p_enc_info the decode one frame settings + * @param p_cb_func the callback function + * @param user_data the private user data + * @return return 0 on success, -1 on error + */ +YDCC_STS kdrv_videoydcc_trigger(unsigned int handle); + +#endif /* __KDRV_VIDEOYDCC_H__ */ \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Include/Driver/nand.h b/board/novatek/ns02501/loader/Include/Driver/nand.h new file mode 100755 index 000000000000..a4b0801610a7 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/nand.h @@ -0,0 +1,122 @@ +/** + nand module driver. + + This file is the driver of storage module. + + @file nand.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _NAND_DEF_ +#define _NAND_DEF_ + +#include "IOReg.h" + +#define _SNAND_WINBOND_ID (0xEF) +#define _SNAND_ESMT_ID (0xC8) +#define _SNAND_GD_ID (0xC8) +#define _SNAND_MICRON_ID (0x2C) +#define _SNAND_ATO_ID (0x9B) +#define _SNAND_ETRON_ID (0xD5) +#define _SNAND_MXIC_ID (0xC2) +#define _SNAND_TOSHIBA_ID (0x98) +#define _SNAND_DOSILICON_ID (0xE5) + + + +#define _GD_SPI_NAND_1Gb (0xF1) +#define _MXIC_SPI_NAND_1Gb (0x12) +#define _DOSILICON_NAND_1Gb (0x71) +/** + SPI NAND flash QE(quid enable) identify type + +*/ + +//@{ +typedef enum { + SPINAND_QE_NONE = 0x0, ///< SPI NAND flash not with QE bit(only by quad command) + SPINAND_QE_FEATURE2_B0H_BIT0_TYPE1, ///< SPI NAND flash QE bit locate at feature field(0xB0H) bit[0] +} SPINAND_QE_TYPE; + + +/** + SPI NAND flash twp plane identify type + +*/ +//@{ +typedef enum { + SPINAND_2_PLANE_NONE = 0x0, ///< SPI NAND flash not 2 plane type + SPINAND_2_PLANE_COLUMN_ADDR_BIT_12_AS_PLANE_SEL,///< SPI NAND flash use column addr bit[12] as plane select +} SPINAND_PLANE_TYPE; + + + +/** + SPI flash identification structure + + @note For SPIFLASH_IDENTIFY_CB +*/ +typedef struct { + UINT32 pagesize; + UINT32 erasesize; + UINT32 qe_opt; + UINT32 plane_opt; +} SPINAND_IDENTIFY, *PSPINAND_IDENTIFY; + +/** + SPIFLASH identify callback + + Callback routine to be invoked after JEDEC ID is read from spi flash. + Callback routine should check if read ID is supported. + + @note STRG_EXT_CMD_SPI_IDENTIFY_CB + + @param[in] first parameter (JEDEC) manufacturer ID read from spi flash + @param[in] second parameter (JEDEC) type ID read from spi flash + @param[in] third parameter (JEDEC) capacity ID read from spi flash + @param[out] forth parameter flash identification returned to spi flash driver + + @return + - @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information + - @b FALSE: input ID is NOT supported/identified by call back +*/ +typedef BOOL (*SPINAND_IDENTIFY_CB)(UINT32, UINT32, UINT32, PSPINAND_IDENTIFY); + + + + +/** + * struct nand_flash_dev - NAND Flash Device ID Structure + * @mfr_id: manufecturer ID part of the full chip ID array (refers the same + * memory address as @id[0]) + * @dev_id: the device ID (the second byte of the full chip ID array) + * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as + * well as the eraseblock size) is determined from the extended NAND + * chip ID array) + * @erasesize: NAND block size + * @qe_opt: Quad enable type(please reference document to select this option) + * @plane_opt: 2 plane nand option(please reference document to select this option) + * @options: stores various chip bit options + * + */ +typedef struct _nand_flash_dev { + UINT32 mfr_id; + UINT32 dev_id; + UINT32 third_id; + UINT32 pagesize; + UINT32 erasesize; + UINT32 qe_opt; + UINT32 plane_opt; +} NAND_FLASH_DEV, *PNAND_FLASH_DEV; + +#define SPI_ID_NAND(mfrid, devid, third, pagesz, erasesz, opts, plane_opt_type)\ + { .mfr_id =(mfrid), .dev_id = (devid), .third_id = (third), .pagesize = (pagesz), \ + .erasesize = (erasesz), .qe_opt = (opts), .plane_opt=(plane_opt_type) } + +extern BOOL nand_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiThirdID, PSPINAND_IDENTIFY pIdentify); + +#endif + diff --git a/board/novatek/ns02501/loader/Include/Driver/nor.h b/board/novatek/ns02501/loader/Include/Driver/nor.h new file mode 100755 index 000000000000..b3d72eaf5774 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/nor.h @@ -0,0 +1,50 @@ +/** + nand module driver. + + This file is the driver of storage module. + + @file nand.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _NOR_DEF_ +#define _NOR_DEF_ + +#include "IOReg.h" +#include "StorageDef.h" + + +/** + * struct nand_flash_dev - NAND Flash Device ID Structure + * @name: a human-readable name of the NAND chip + * @dev_id: the device ID (the second byte of the full chip ID array) + * @mfr_id: manufecturer ID part of the full chip ID array (refers the same + * memory address as @id[0]) + * @dev_id: device ID part of the full chip ID array (refers the same memory + * address as @id[1]) + * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as + * well as the eraseblock size) is determined from the extended NAND + * chip ID array) + * @chipsize: total chip size in MiB + * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) + * @options: stores various chip bit options + * + */ +typedef struct _nor_flash_dev { + UINT32 mfr_id; + UINT32 dev_id; + UINT32 capacity_id; + UINT32 uiFlashSize; + UINT32 uiBusWidth; +} NOR_FLASH_DEV, *PNOR_FLASH_DEV; + +#define SPI_ID_NOR(mfrid, devid, capacityid, flash_size, bus_width)\ + { .mfr_id =(mfrid), .dev_id = (devid), .capacity_id =(capacityid), \ + .uiFlashSize=(flash_size), .uiBusWidth=(bus_width) } + + +extern BOOL nor_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify); +#endif diff --git a/board/novatek/ns02501/loader/Include/Driver/pad.h b/board/novatek/ns02501/loader/Include/Driver/pad.h new file mode 100755 index 000000000000..c7c9e296191f --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/pad.h @@ -0,0 +1,898 @@ +/** + PAD controller header + + PAD controller header + + @file pad.h + @ingroup mIHALSysPAD + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _PAD_H +#define _PAD_H + +//#include "Type.h" +#include "constant.h" + + + +/** \addtogroup mIHALSysPAD */ +//@{ + +// Macro to generate dummy element for enum type to expand enum size to word (4 bytes) +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + +#if 0 +/** + Pad type select + + Pad type select + + Pad type value for pad_setPullUpDown(). +*/ +typedef enum +{ + PAD_NONE = 0x00, ///< none of pull up/down + PAD_PULLDOWN = 0x01, ///< pull down + PAD_PULLUP = 0x02, ///< pull up + PAD_KEEPER = 0x03, ///< keeper + + ENUM_DUMMY4WORD(PAD_PULL) +} PAD_PULL; + +/** + Pad driving select + + Pad driving select + + Pad driving value for pad_setDrivingSink(). +*/ +typedef enum { + PAD_DRIVINGSINK_2P5MA = 0x01, ///< for backward compatible + PAD_DRIVINGSINK_5MA = 0x02, ///< Pad driver/sink 5mA + PAD_DRIVINGSINK_7P5MA = 0x04, ///< for backward compatible + PAD_DRIVINGSINK_10MA = 0x08, ///< Pad driver/sink 10mA + + PAD_DRIVINGSINK_12P5MA = 0x10, ///< for backward compatible + PAD_DRIVINGSINK_15MA = 0x20, ///< Pad driver/sink 15mA + PAD_DRIVINGSINK_17P5MA = 0x40, ///< for backward compatible + PAD_DRIVINGSINK_20MA = 0x80, ///< Pad driver/sink 20mA + PAD_DRIVINGSINK_25MA = 0x100, ///< Pad driver/sink 25mA + PAD_DRIVINGSINK_30MA = 0x200, ///< Pad driver/sink 30mA + PAD_DRIVINGSINK_35MA = 0x400, ///< Pad driver/sink 35mA + PAD_DRIVINGSINK_40MA = 0x800, ///< Pad driver/sink 40mA + PAD_DRIVINGSINK_4MA = 0x1000, ///< PAD driver/sink 4mA + PAD_DRIVINGSINK_6MA = 0x2000, ///< PAD driver/sink 6mA + PAD_DRIVINGSINK_8MA = 0x4000, ///< PAD driver/sink 8mA + PAD_DRIVINGSINK_16MA = 0x8000, ///< PAD driver/sink 16mA + + ENUM_DUMMY4WORD(PAD_DRIVINGSINK) +} PAD_DRIVINGSINK; + +/** + @name Pad type pin ID. + + Pad type pin ID. + + Pad ID of pad_setPullUpDown(). +*/ +#define PAD_PIN_NOT_EXIST (15) // For backward compatible +//@{ +//CGPIOx group begin +#define PAD_PIN_CGPIO_BASE 0 +#define PAD_PIN_CGPIO0 (PAD_PIN_CGPIO_BASE + 0) ///< CGPIO0 +#define PAD_PIN_CGPIO1 (PAD_PIN_CGPIO_BASE + 1) ///< CGPIO1 +#define PAD_PIN_CGPIO2 (PAD_PIN_CGPIO_BASE + 2) ///< CGPIO2 +#define PAD_PIN_CGPIO3 (PAD_PIN_CGPIO_BASE + 3) ///< CGPIO3 +#define PAD_PIN_CGPIO4 (PAD_PIN_CGPIO_BASE + 4) ///< CGPIO4 +#define PAD_PIN_CGPIO5 (PAD_PIN_CGPIO_BASE + 5) ///< CGPIO5 +#define PAD_PIN_CGPIO6 (PAD_PIN_CGPIO_BASE + 6) ///< CGPIO6 +#define PAD_PIN_CGPIO7 (PAD_PIN_CGPIO_BASE + 7) ///< CGPIO7 +#define PAD_PIN_CGPIO8 (PAD_PIN_CGPIO_BASE + 8) ///< CGPIO8 +#define PAD_PIN_CGPIO9 (PAD_PIN_CGPIO_BASE + 9) ///< CGPIO9 +#define PAD_PIN_CGPIO10 (PAD_PIN_CGPIO_BASE + 10) ///< CGPIO10 +#define PAD_PIN_CGPIO11 (PAD_PIN_CGPIO_BASE + 11) ///< CGPIO11 +#define PAD_PIN_CGPIO12 (PAD_PIN_CGPIO_BASE + 12) ///< CGPIO12 +#define PAD_PIN_CGPIO13 (PAD_PIN_CGPIO_BASE + 13) ///< CGPIO13 +#define PAD_PIN_CGPIO14 (PAD_PIN_CGPIO_BASE + 14) ///< CGPIO14 +#define PAD_PIN_CGPIO15 (PAD_PIN_CGPIO_BASE + 15) ///< CGPIO15 + +#define PAD_PIN_CGPIO16 (PAD_PIN_CGPIO_BASE + 16) ///< CGPIO16 +#define PAD_PIN_CGPIO17 (PAD_PIN_CGPIO_BASE + 17) ///< CGPIO17 +#define PAD_PIN_CGPIO18 (PAD_PIN_CGPIO_BASE + 18) ///< CGPIO18 +#define PAD_PIN_CGPIO19 (PAD_PIN_CGPIO_BASE + 19) ///< CGPIO19 +#define PAD_PIN_CGPIO20 (PAD_PIN_CGPIO_BASE + 20) ///< CGPIO20 +#define PAD_PIN_CGPIO21 (PAD_PIN_CGPIO_BASE + 21) ///< CGPIO21 +#define PAD_PIN_CGPIO22 (PAD_PIN_CGPIO_BASE + 22) ///< CGPIO22 +#define PAD_PIN_CGPIO23 (PAD_PIN_CGPIO_BASE + 23) ///< CGPIO23 +#define PAD_PIN_CGPIO24 (PAD_PIN_CGPIO_BASE + 24) ///< CGPIO24 +#define PAD_PIN_CGPIO25 (PAD_PIN_CGPIO_BASE + 25) ///< CGPIO25 +#define PAD_PIN_CGPIO26 (PAD_PIN_CGPIO_BASE + 26) ///< CGPIO26 +#define PAD_PIN_CGPIO27 (PAD_PIN_CGPIO_BASE + 27) ///< CGPIO27 +#define PAD_PIN_CGPIO28 (PAD_PIN_CGPIO_BASE + 28) ///< CGPIO28 +#define PAD_PIN_CGPIO29 (PAD_PIN_CGPIO_BASE + 29) ///< CGPIO29 +#define PAD_PIN_CGPIO30 (PAD_PIN_CGPIO_BASE + 30) ///< CGPIO30 +#define PAD_PIN_CGPIO31 (PAD_PIN_CGPIO_BASE + 31) ///< CGPIO31 + +#define PAD_PIN_CGPIO32 (PAD_PIN_CGPIO_BASE + 32) ///< CGPIO32 +#define PAD_PIN_CGPIO33 (PAD_PIN_CGPIO_BASE + 33) ///< CGPIO33 +//CGPIOx group end + +//SGPIOx group begin +#define PAD_PIN_SGPIO_BASE 100 +#define PAD_PIN_SGPIO0 (PAD_PIN_SGPIO_BASE + 0) ///< SGPIO0 +#define PAD_PIN_SGPIO1 (PAD_PIN_SGPIO_BASE + 1) ///< SGPIO1 +#define PAD_PIN_SGPIO2 (PAD_PIN_SGPIO_BASE + 2) ///< SGPIO2 +#define PAD_PIN_SGPIO3 (PAD_PIN_SGPIO_BASE + 3) ///< SGPIO3 +#define PAD_PIN_SGPIO4 (PAD_PIN_SGPIO_BASE + 4) ///< SGPIO4 +#define PAD_PIN_SGPIO5 (PAD_PIN_SGPIO_BASE + 5) ///< SGPIO5 +#define PAD_PIN_SGPIO6 (PAD_PIN_SGPIO_BASE + 6) ///< SGPIO6 +#define PAD_PIN_SGPIO7 (PAD_PIN_SGPIO_BASE + 7) ///< SGPIO7 +#define PAD_PIN_SGPIO8 (PAD_PIN_SGPIO_BASE + 8) ///< SGPIO8 +#define PAD_PIN_SGPIO9 (PAD_PIN_SGPIO_BASE + 9) ///< SGPIO9 +#define PAD_PIN_SGPIO10 (PAD_PIN_SGPIO_BASE + 10) ///< SGPIO10 +#define PAD_PIN_SGPIO11 (PAD_PIN_SGPIO_BASE + 11) ///< SGPIO11 +//SGPIOx group end + +//PGPIOx group begin +#define PAD_PIN_PGPIO_BASE 150 +#define PAD_PIN_PGPIO0 (PAD_PIN_PGPIO_BASE + 0) ///< PGPIO0 +#define PAD_PIN_PGPIO1 (PAD_PIN_PGPIO_BASE + 1) ///< PGPIO1 +#define PAD_PIN_PGPIO2 (PAD_PIN_PGPIO_BASE + 2) ///< PGPIO2 +#define PAD_PIN_PGPIO3 (PAD_PIN_PGPIO_BASE + 3) ///< PGPIO3 +#define PAD_PIN_PGPIO4 (PAD_PIN_PGPIO_BASE + 4) ///< PGPIO4 +#define PAD_PIN_PGPIO5 (PAD_PIN_PGPIO_BASE + 5) ///< PGPIO5 +#define PAD_PIN_PGPIO6 (PAD_PIN_PGPIO_BASE + 6) ///< PGPIO6 +#define PAD_PIN_PGPIO7 (PAD_PIN_PGPIO_BASE + 7) ///< PGPIO7 +#define PAD_PIN_PGPIO8 (PAD_PIN_PGPIO_BASE + 8) ///< PGPIO8 +#define PAD_PIN_PGPIO9 (PAD_PIN_PGPIO_BASE + 9) ///< PGPIO9 +#define PAD_PIN_PGPIO10 (PAD_PIN_PGPIO_BASE + 10) ///< PGPIO10 +#define PAD_PIN_PGPIO11 (PAD_PIN_PGPIO_BASE + 11) ///< PGPIO11 +#define PAD_PIN_PGPIO12 (PAD_PIN_PGPIO_BASE + 12) ///< PGPIO12 +#define PAD_PIN_PGPIO13 (PAD_PIN_PGPIO_BASE + 13) ///< PGPIO13 +#define PAD_PIN_PGPIO14 (PAD_PIN_PGPIO_BASE + 14) ///< PGPIO14 +#define PAD_PIN_PGPIO15 (PAD_PIN_PGPIO_BASE + 15) ///< PGPIO15 + +#define PAD_PIN_PGPIO16 (PAD_PIN_PGPIO_BASE + 16) ///< PGPIO16 +#define PAD_PIN_PGPIO17 (PAD_PIN_PGPIO_BASE + 17) ///< PGPIO17 +#define PAD_PIN_PGPIO18 (PAD_PIN_PGPIO_BASE + 18) ///< PGPIO18 +#define PAD_PIN_PGPIO19 (PAD_PIN_PGPIO_BASE + 19) ///< PGPIO19 +#define PAD_PIN_PGPIO20 (PAD_PIN_PGPIO_BASE + 20) ///< PGPIO20 +#define PAD_PIN_PGPIO21 (PAD_PIN_PGPIO_BASE + 21) ///< PGPIO21 +#define PAD_PIN_PGPIO22 (PAD_PIN_PGPIO_BASE + 22) ///< PGPIO22 +#define PAD_PIN_PGPIO23 (PAD_PIN_PGPIO_BASE + 23) ///< PGPIO23 +#define PAD_PIN_PGPIO24 (PAD_PIN_PGPIO_BASE + 24) ///< PGPIO24 +#define PAD_PIN_PGPIO25 (PAD_PIN_PGPIO_BASE + 25) ///< PGPIO25 +#define PAD_PIN_PGPIO26 (PAD_PIN_PGPIO_BASE + 26) ///< PGPIO26 +#define PAD_PIN_PGPIO27 (PAD_PIN_PGPIO_BASE + 27) ///< PGPIO27 +#define PAD_PIN_PGPIO28 (PAD_PIN_PGPIO_BASE + 28) ///< PGPIO28 +#define PAD_PIN_PGPIO29 (PAD_PIN_PGPIO_BASE + 29) ///< PGPIO29 +#define PAD_PIN_PGPIO30 (PAD_PIN_PGPIO_BASE + 30) ///< PGPIO30 +#define PAD_PIN_PGPIO31 (PAD_PIN_PGPIO_BASE + 31) ///< PGPIO31 + +#define PAD_PIN_PGPIO32 (PAD_PIN_PGPIO_BASE + 32) ///< PGPIO32 +#define PAD_PIN_PGPIO33 (PAD_PIN_PGPIO_BASE + 33) ///< PGPIO33 +#define PAD_PIN_PGPIO34 (PAD_PIN_PGPIO_BASE + 34) ///< PGPIO34 +#define PAD_PIN_PGPIO35 (PAD_PIN_PGPIO_BASE + 35) ///< PGPIO35 +#define PAD_PIN_PGPIO36 (PAD_PIN_PGPIO_BASE + 36) ///< PGPIO36 +#define PAD_PIN_PGPIO37 (PAD_PIN_PGPIO_BASE + 37) ///< PGPIO37 +#define PAD_PIN_PGPIO38 (PAD_PIN_PGPIO_BASE + 38) ///< PGPIO38 +#define PAD_PIN_PGPIO39 (PAD_PIN_PGPIO_BASE + 39) ///< PGPIO39 +#define PAD_PIN_PGPIO40 (PAD_PIN_PGPIO_BASE + 40) ///< PGPIO40 +#define PAD_PIN_PGPIO41 (PAD_PIN_PGPIO_BASE + 41) ///< PGPIO41 +#define PAD_PIN_PGPIO42 (PAD_PIN_PGPIO_BASE + 42) ///< PGPIO42 +#define PAD_PIN_PGPIO43 (PAD_PIN_PGPIO_BASE + 43) ///< PGPIO43 +#define PAD_PIN_PGPIO44 (PAD_PIN_PGPIO_BASE + 44) ///< PGPIO44 +#define PAD_PIN_PGPIO45 (PAD_PIN_PGPIO_BASE + 45) ///< PGPIO45 +#define PAD_PIN_PGPIO46 (PAD_PIN_PGPIO_BASE + 46) ///< PGPIO46 +#define PAD_PIN_PGPIO47 (PAD_PIN_PGPIO_BASE + 47) ///< PGPIO47 +//PGPIOx group end + + +//LGPIOx group begin +#define PAD_PIN_LGPIO_BASE 250 +#define PAD_PIN_LGPIO0 (PAD_PIN_LGPIO_BASE + 0) ///< LGPIO0 +#define PAD_PIN_LGPIO1 (PAD_PIN_LGPIO_BASE + 1) ///< LGPIO1 +#define PAD_PIN_LGPIO2 (PAD_PIN_LGPIO_BASE + 2) ///< LGPIO2 +#define PAD_PIN_LGPIO3 (PAD_PIN_LGPIO_BASE + 3) ///< LGPIO3 +#define PAD_PIN_LGPIO4 (PAD_PIN_LGPIO_BASE + 4) ///< LGPIO4 +#define PAD_PIN_LGPIO5 (PAD_PIN_LGPIO_BASE + 5) ///< LGPIO5 +#define PAD_PIN_LGPIO6 (PAD_PIN_LGPIO_BASE + 6) ///< LGPIO6 +#define PAD_PIN_LGPIO7 (PAD_PIN_LGPIO_BASE + 7) ///< LGPIO7 +#define PAD_PIN_LGPIO8 (PAD_PIN_LGPIO_BASE + 8) ///< LGPIO8 +#define PAD_PIN_LGPIO9 (PAD_PIN_LGPIO_BASE + 9) ///< LGPIO9 +#define PAD_PIN_LGPIO10 (PAD_PIN_LGPIO_BASE + 10) ///< LGPIO10 +#define PAD_PIN_LGPIO11 (PAD_PIN_LGPIO_BASE + 11) ///< LGPIO11 +#define PAD_PIN_LGPIO12 (PAD_PIN_LGPIO_BASE + 12) ///< LGPIO12 +#define PAD_PIN_LGPIO13 (PAD_PIN_LGPIO_BASE + 13) ///< LGPIO13 +#define PAD_PIN_LGPIO14 (PAD_PIN_LGPIO_BASE + 14) ///< LGPIO14 +#define PAD_PIN_LGPIO15 (PAD_PIN_LGPIO_BASE + 15) ///< LGPIO15 + +#define PAD_PIN_LGPIO16 (PAD_PIN_LGPIO_BASE + 16) ///< LGPIO16 +#define PAD_PIN_LGPIO17 (PAD_PIN_LGPIO_BASE + 17) ///< LGPIO17 +#define PAD_PIN_LGPIO18 (PAD_PIN_LGPIO_BASE + 18) ///< LGPIO18 +#define PAD_PIN_LGPIO19 (PAD_PIN_LGPIO_BASE + 19) ///< LGPIO19 +#define PAD_PIN_LGPIO20 (PAD_PIN_LGPIO_BASE + 20) ///< LGPIO20 +#define PAD_PIN_LGPIO21 (PAD_PIN_LGPIO_BASE + 21) ///< LGPIO21 +#define PAD_PIN_LGPIO22 (PAD_PIN_LGPIO_BASE + 22) ///< LGPIO22 +#define PAD_PIN_LGPIO23 (PAD_PIN_LGPIO_BASE + 23) ///< LGPIO23 +#define PAD_PIN_LGPIO24 (PAD_PIN_LGPIO_BASE + 24) ///< LGPIO24 +#define PAD_PIN_LGPIO25 (PAD_PIN_LGPIO_BASE + 25) ///< LGPIO25 +#define PAD_PIN_LGPIO26 (PAD_PIN_LGPIO_BASE + 26) ///< LGPIO26 +#define PAD_PIN_LGPIO27 (PAD_PIN_LGPIO_BASE + 27) ///< LGPIO27 +#define PAD_PIN_LGPIO28 (PAD_PIN_LGPIO_BASE + 28) ///< LGPIO28 +#define PAD_PIN_LGPIO29 (PAD_PIN_LGPIO_BASE + 29) ///< LGPIO29 +#define PAD_PIN_LGPIO30 (PAD_PIN_LGPIO_BASE + 30) ///< LGPIO30 +#define PAD_PIN_LGPIO31 (PAD_PIN_LGPIO_BASE + 31) ///< LGPIO31 +#define PAD_PIN_LGPIO32 (PAD_PIN_LGPIO_BASE + 32) ///< LGPIO32 +//LGPIOx group end + +//DGPIO group begin +#define PAD_PIN_DGPIO_BASE 300 +#define PAD_PIN_DGPIO0 (PAD_PIN_DGPIO_BASE + 0) ///< DGPIO0 +#define PAD_PIN_DGPIO1 (PAD_PIN_DGPIO_BASE + 1) ///< DGPIO1 +#define PAD_PIN_DGPIO2 (PAD_PIN_DGPIO_BASE + 2) ///< DGPIO2 +#define PAD_PIN_DGPIO3 (PAD_PIN_DGPIO_BASE + 3) ///< DGPIO3 +#define PAD_PIN_DGPIO4 (PAD_PIN_DGPIO_BASE + 4) ///< DGPIO4 +#define PAD_PIN_DGPIO5 (PAD_PIN_DGPIO_BASE + 5) ///< DGPIO5 +#define PAD_PIN_DGPIO6 (PAD_PIN_DGPIO_BASE + 6) ///< DGPIO6 +#define PAD_PIN_DGPIO7 (PAD_PIN_DGPIO_BASE + 7) ///< DGPIO7 +#define PAD_PIN_DGPIO8 (PAD_PIN_DGPIO_BASE + 8) ///< DGPIO8 +#define PAD_PIN_DGPIO9 (PAD_PIN_DGPIO_BASE + 9) ///< DGPIO9 +#define PAD_PIN_DGPIO10 (PAD_PIN_DGPIO_BASE + 10) ///< DGPIO10 +#define PAD_PIN_DGPIO11 (PAD_PIN_DGPIO_BASE + 11) ///< DGPIO11 +#define PAD_PIN_DGPIO12 (PAD_PIN_DGPIO_BASE + 12) ///< DGPIO12 +//DGPIO group end + +//@} + + + +#define PAD_DS_GROUP4_10 0x0000 +#define PAD_DS_GROUP6_16 0x1000 +#define PAD_DS_GROUP8 0x2000 +#define PAD_DS_GROUP16 0x4000 +#define PAD_DS_GROUP5_40 0x8000 + +/** + @name Pad driving pin ID. + + Pad driving pin ID. + + Pad ID of pad_setDrivingSink() +*/ +//@{ +//CGPIO group begin +#define PAD_DS_CGPIO_BASE 0 +#define PAD_DS_CGPIO0 (PAD_DS_CGPIO_BASE + 0) ///< CGPIO0 +#define PAD_DS_CGPIO1 (PAD_DS_CGPIO_BASE + 1) ///< CGPIO1 +#define PAD_DS_CGPIO2 (PAD_DS_CGPIO_BASE + 2) ///< CGPIO2 +#define PAD_DS_CGPIO3 (PAD_DS_CGPIO_BASE + 3) ///< CGPIO3 +#define PAD_DS_CGPIO4 (PAD_DS_CGPIO_BASE + 4) ///< CGPIO4 +#define PAD_DS_CGPIO5 (PAD_DS_CGPIO_BASE + 5) ///< CGPIO5 +#define PAD_DS_CGPIO6 (PAD_DS_CGPIO_BASE + 6) ///< CGPIO6 +#define PAD_DS_CGPIO7 (PAD_DS_CGPIO_BASE + 7) ///< CGPIO7 +#define PAD_DS_CGPIO8 (PAD_DS_CGPIO_BASE + 8) ///< CGPIO8 +#define PAD_DS_CGPIO9 ((PAD_DS_CGPIO_BASE + 9) | PAD_DS_GROUP6_16) ///< CGPIO9 +#define PAD_DS_CGPIO10 (PAD_DS_CGPIO_BASE + 10) ///< CGPIO10 +#define PAD_DS_CGPIO11 (PAD_DS_CGPIO_BASE + 11) ///< CGPIO11 +#define PAD_DS_CGPIO12 (PAD_DS_CGPIO_BASE + 12) ///< CGPIO12 +#define PAD_DS_CGPIO13 (PAD_DS_CGPIO_BASE + 13) ///< CGPIO13 +#define PAD_DS_CGPIO14 (PAD_DS_CGPIO_BASE + 14) ///< CGPIO14 +#define PAD_DS_CGPIO15 (PAD_DS_CGPIO_BASE + 15) ///< CGPIO15 + +#define PAD_DS_CGPIO16 ((PAD_DS_CGPIO_BASE + 16) | PAD_DS_GROUP5_40) ///< CGPIO16 +#define PAD_DS_CGPIO17 ((PAD_DS_CGPIO_BASE + 17) | PAD_DS_GROUP5_40) ///< CGPIO17 +#define PAD_DS_CGPIO18 ((PAD_DS_CGPIO_BASE + 18) | PAD_DS_GROUP5_40) ///< CGPIO18 +#define PAD_DS_CGPIO19 ((PAD_DS_CGPIO_BASE + 19) | PAD_DS_GROUP5_40) ///< CGPIO19 +#define PAD_DS_CGPIO20 ((PAD_DS_CGPIO_BASE + 20) | PAD_DS_GROUP5_40) ///< CGPIO20 +#define PAD_DS_CGPIO21 ((PAD_DS_CGPIO_BASE + 21) | PAD_DS_GROUP5_40) ///< CGPIO21 +#define PAD_DS_CGPIO22 ((PAD_DS_CGPIO_BASE + 22) | PAD_DS_GROUP5_40) ///< CGPIO22 +#define PAD_DS_CGPIO23 ((PAD_DS_CGPIO_BASE + 23) | PAD_DS_GROUP5_40) ///< CGPIO23 +#define PAD_DS_CGPIO24 ((PAD_DS_CGPIO_BASE + 24) | PAD_DS_GROUP5_40) ///< CGPIO24 +#define PAD_DS_CGPIO25 ((PAD_DS_CGPIO_BASE + 25) | PAD_DS_GROUP5_40) ///< CGPIO25 +#define PAD_DS_CGPIO26 ((PAD_DS_CGPIO_BASE + 26) | PAD_DS_GROUP5_40) ///< CGPIO26 +#define PAD_DS_CGPIO27 ((PAD_DS_CGPIO_BASE + 27) | PAD_DS_GROUP5_40) ///< CGPIO27 +#define PAD_DS_CGPIO28 ((PAD_DS_CGPIO_BASE + 28) | PAD_DS_GROUP6_16) ///< CGPIO28 +#define PAD_DS_CGPIO29 (PAD_DS_CGPIO_BASE + 29) ///< CGPIO29 +#define PAD_DS_CGPIO30 (PAD_DS_CGPIO_BASE + 30) ///< CGPIO30 +#define PAD_DS_CGPIO31 (PAD_DS_CGPIO_BASE + 31) ///< CGPIO31 + +#define PAD_DS_CGPIO32 (PAD_DS_CGPIO_BASE + 32) ///< CGPIO32 +#define PAD_DS_CGPIO33 (PAD_DS_CGPIO_BASE + 33) ///< CGPIO33 +//CGPIO group end + +//SGPIO group Driving/Sink begin +#define PAD_DS_SGPIO_BASE 48 +#define PAD_DS_SGPIO0 ((PAD_DS_SGPIO_BASE + 0) | PAD_DS_GROUP6_16) ///< SGPIO0 +#define PAD_DS_SGPIO1 ((PAD_DS_SGPIO_BASE + 1) | PAD_DS_GROUP8) ///< SGPIO1 +#define PAD_DS_SGPIO2 ((PAD_DS_SGPIO_BASE + 2) | PAD_DS_GROUP8) ///< SGPIO2 +#define PAD_DS_SGPIO3 ((PAD_DS_SGPIO_BASE + 3) | PAD_DS_GROUP8) ///< SGPIO3 +#define PAD_DS_SGPIO4 ((PAD_DS_SGPIO_BASE + 4) | PAD_DS_GROUP8) ///< SGPIO4 +#define PAD_DS_SGPIO5 ((PAD_DS_SGPIO_BASE + 5) | PAD_DS_GROUP6_16) ///< SGPIO5 +#define PAD_DS_SGPIO6 ((PAD_DS_SGPIO_BASE + 6) | PAD_DS_GROUP8) ///< SGPIO6 +#define PAD_DS_SGPIO7 ((PAD_DS_SGPIO_BASE + 7) | PAD_DS_GROUP8) ///< SGPIO7 +#define PAD_DS_SGPIO8 (PAD_DS_SGPIO_BASE + 8) ///< SGPIO8 +#define PAD_DS_SGPIO9 (PAD_DS_SGPIO_BASE + 9) ///< SGPIO9 +#define PAD_DS_SGPIO10 (PAD_DS_SGPIO_BASE + 10) ///< SGPIO10 +#define PAD_DS_SGPIO11 (PAD_DS_SGPIO_BASE + 11) ///< SGPIO11 +//SGPIO group Driving/Sink end + +//PGPIO group Driving/Sink begin +#define PAD_DS_PGPIO_BASE 64 +#define PAD_DS_PGPIO0 (PAD_DS_PGPIO_BASE + 0) ///< PGPIO0 +#define PAD_DS_PGPIO1 (PAD_DS_PGPIO_BASE + 1) ///< PGPIO1 +#define PAD_DS_PGPIO2 (PAD_DS_PGPIO_BASE + 2) ///< PGPIO2 +#define PAD_DS_PGPIO3 (PAD_DS_PGPIO_BASE + 3) ///< PGPIO3 +#define PAD_DS_PGPIO4 (PAD_DS_PGPIO_BASE + 4) ///< PGPIO4 +#define PAD_DS_PGPIO5 (PAD_DS_PGPIO_BASE + 5) ///< PGPIO5 +#define PAD_DS_PGPIO6 (PAD_DS_PGPIO_BASE + 6) ///< PGPIO6 +#define PAD_DS_PGPIO7 (PAD_DS_PGPIO_BASE + 7) ///< PGPIO7 +#define PAD_DS_PGPIO8 (PAD_DS_PGPIO_BASE + 8) ///< PGPIO8 +#define PAD_DS_PGPIO9 (PAD_DS_PGPIO_BASE + 9) ///< PGPIO9 +#define PAD_DS_PGPIO10 (PAD_DS_PGPIO_BASE + 10) ///< PGPIO10 +#define PAD_DS_PGPIO11 (PAD_DS_PGPIO_BASE + 11) ///< PGPIO11 +#define PAD_DS_PGPIO12 (PAD_DS_PGPIO_BASE + 12) ///< PGPIO12 +#define PAD_DS_PGPIO13 (PAD_DS_PGPIO_BASE + 13) ///< PGPIO13 +#define PAD_DS_PGPIO14 (PAD_DS_PGPIO_BASE + 14) ///< PGPIO14 +#define PAD_DS_PGPIO15 (PAD_DS_PGPIO_BASE + 15) ///< PGPIO15 + +#define PAD_DS_PGPIO16 (PAD_DS_PGPIO_BASE + 16) ///< PGPIO16 +#define PAD_DS_PGPIO17 (PAD_DS_PGPIO_BASE + 17) ///< PGPIO17 +#define PAD_DS_PGPIO18 (PAD_DS_PGPIO_BASE + 18) ///< PGPIO18 +#define PAD_DS_PGPIO19 (PAD_DS_PGPIO_BASE + 19) ///< PGPIO19 +#define PAD_DS_PGPIO20 ((PAD_DS_PGPIO_BASE + 20) | PAD_DS_GROUP6_16) ///< PGPIO20 +#define PAD_DS_PGPIO21 ((PAD_DS_PGPIO_BASE + 21) | PAD_DS_GROUP6_16) ///< PGPIO21 +#define PAD_DS_PGPIO22 ((PAD_DS_PGPIO_BASE + 22) | PAD_DS_GROUP6_16) ///< PGPIO22 +#define PAD_DS_PGPIO23 ((PAD_DS_PGPIO_BASE + 23) | PAD_DS_GROUP6_16) ///< PGPIO23 +#define PAD_DS_PGPIO24 (PAD_DS_PGPIO_BASE + 24) ///< PGPIO24 +#define PAD_DS_PGPIO25 (PAD_DS_PGPIO_BASE + 25) ///< PGPIO25 +#define PAD_DS_PGPIO26 (PAD_DS_PGPIO_BASE + 26) ///< PGPIO26 +#define PAD_DS_PGPIO27 (PAD_DS_PGPIO_BASE + 27) ///< PGPIO27 +#define PAD_DS_PGPIO28 (PAD_DS_PGPIO_BASE + 28) ///< PGPIO28 +#define PAD_DS_PGPIO29 (PAD_DS_PGPIO_BASE + 29) ///< PGPIO29 +#define PAD_DS_PGPIO30 (PAD_DS_PGPIO_BASE + 30) ///< PGPIO30 +#define PAD_DS_PGPIO31 (PAD_DS_PGPIO_BASE + 31) ///< PGPIO31 + +#define PAD_DS_PGPIO32 (PAD_DS_PGPIO_BASE + 32) ///< PGPIO32 +#define PAD_DS_PGPIO33 (PAD_DS_PGPIO_BASE + 33) ///< PGPIO33 +#define PAD_DS_PGPIO34 (PAD_DS_PGPIO_BASE + 34) ///< PGPIO34 +#define PAD_DS_PGPIO35 (PAD_DS_PGPIO_BASE + 35) ///< PGPIO35 +#define PAD_DS_PGPIO36 (PAD_DS_PGPIO_BASE + 36) ///< PGPIO36 +#define PAD_DS_PGPIO37 (PAD_DS_PGPIO_BASE + 37) ///< PGPIO37 +#define PAD_DS_PGPIO38 (PAD_DS_PGPIO_BASE + 38) ///< PGPIO38 +#define PAD_DS_PGPIO39 (PAD_DS_PGPIO_BASE + 39) ///< PGPIO39 +#define PAD_DS_PGPIO40 (PAD_DS_PGPIO_BASE + 40) ///< PGPIO40 +#define PAD_DS_PGPIO41 (PAD_DS_PGPIO_BASE + 41) ///< PGPIO41 +#define PAD_DS_PGPIO42 ((PAD_DS_PGPIO_BASE + 42) | PAD_DS_GROUP8) ///< PGPIO42 +#define PAD_DS_PGPIO43 ((PAD_DS_PGPIO_BASE + 43) | PAD_DS_GROUP8) ///< PGPIO43 +#define PAD_DS_PGPIO44 ((PAD_DS_PGPIO_BASE + 44) | PAD_DS_GROUP8) ///< PGPIO44 +#define PAD_DS_PGPIO45 ((PAD_DS_PGPIO_BASE + 45) | PAD_DS_GROUP8) ///< PGPIO45 +#define PAD_DS_PGPIO46 ((PAD_DS_PGPIO_BASE + 46) | PAD_DS_GROUP8) ///< PGPIO46 +#define PAD_DS_PGPIO47 ((PAD_DS_PGPIO_BASE + 47) | PAD_DS_GROUP8) ///< PGPIO47 +//PGPIO group Driving/Sink end + +//LCD group Driving/Sink begin +#define PAD_DS_LGPIO_BASE 112 +#define PAD_DS_LGPIO0 ((PAD_DS_LGPIO_BASE + 0) | PAD_DS_GROUP6_16) ///< LGPIO0 +#define PAD_DS_LGPIO1 ((PAD_DS_LGPIO_BASE + 1) | PAD_DS_GROUP6_16) ///< LGPIO1 +#define PAD_DS_LGPIO2 ((PAD_DS_LGPIO_BASE + 2) | PAD_DS_GROUP6_16) ///< LGPIO2 +#define PAD_DS_LGPIO3 ((PAD_DS_LGPIO_BASE + 3) | PAD_DS_GROUP6_16) ///< LGPIO3 +#define PAD_DS_LGPIO4 ((PAD_DS_LGPIO_BASE + 4) | PAD_DS_GROUP6_16) ///< LGPIO4 +#define PAD_DS_LGPIO5 ((PAD_DS_LGPIO_BASE + 5) | PAD_DS_GROUP6_16) ///< LGPIO5 +#define PAD_DS_LGPIO6 ((PAD_DS_LGPIO_BASE + 6) | PAD_DS_GROUP6_16) ///< LGPIO6 +#define PAD_DS_LGPIO7 ((PAD_DS_LGPIO_BASE + 7) | PAD_DS_GROUP6_16) ///< LGPIO7 +#define PAD_DS_LGPIO8 ((PAD_DS_LGPIO_BASE + 8) | PAD_DS_GROUP6_16) ///< LGPIO8 +#define PAD_DS_LGPIO9 ((PAD_DS_LGPIO_BASE + 9) | PAD_DS_GROUP6_16) ///< LGPIO9 +#define PAD_DS_LGPIO10 ((PAD_DS_LGPIO_BASE + 10)| PAD_DS_GROUP6_16) ///< LGPIO10 +#define PAD_DS_LGPIO11 ((PAD_DS_LGPIO_BASE + 11)| PAD_DS_GROUP6_16) ///< LGPIO11 +#define PAD_DS_LGPIO12 ((PAD_DS_LGPIO_BASE + 12)| PAD_DS_GROUP6_16) ///< LGPIO12 +#define PAD_DS_LGPIO13 ((PAD_DS_LGPIO_BASE + 13)| PAD_DS_GROUP6_16) ///< LGPIO13 +#define PAD_DS_LGPIO14 ((PAD_DS_LGPIO_BASE + 14)| PAD_DS_GROUP6_16) ///< LGPIO14 +#define PAD_DS_LGPIO15 ((PAD_DS_LGPIO_BASE + 15)| PAD_DS_GROUP6_16) ///< LGPIO15 + +#define PAD_DS_LGPIO16 ((PAD_DS_LGPIO_BASE + 16)| PAD_DS_GROUP6_16) ///< LGPIO16 +#define PAD_DS_LGPIO17 ((PAD_DS_LGPIO_BASE + 17)| PAD_DS_GROUP6_16) ///< LGPIO17 +#define PAD_DS_LGPIO18 ((PAD_DS_LGPIO_BASE + 18)| PAD_DS_GROUP6_16) ///< LGPIO18 +#define PAD_DS_LGPIO19 ((PAD_DS_LGPIO_BASE + 19)| PAD_DS_GROUP6_16) ///< LGPIO19 +#define PAD_DS_LGPIO20 ((PAD_DS_LGPIO_BASE + 20)| PAD_DS_GROUP6_16) ///< LGPIO20 +#define PAD_DS_LGPIO21 ((PAD_DS_LGPIO_BASE + 21)| PAD_DS_GROUP6_16) ///< LGPIO21 +#define PAD_DS_LGPIO22 ((PAD_DS_LGPIO_BASE + 22)| PAD_DS_GROUP6_16) ///< LGPIO22 +#define PAD_DS_LGPIO23 ((PAD_DS_LGPIO_BASE + 23)| PAD_DS_GROUP6_16) ///< LGPIO23 +#define PAD_DS_LGPIO24 ((PAD_DS_LGPIO_BASE + 24)| PAD_DS_GROUP6_16) ///< LGPIO24 +#define PAD_DS_LGPIO25 ((PAD_DS_LGPIO_BASE + 25)| PAD_DS_GROUP6_16) ///< LGPIO25 +#define PAD_DS_LGPIO26 ((PAD_DS_LGPIO_BASE + 26)| PAD_DS_GROUP6_16) ///< LGPIO26 +#define PAD_DS_LGPIO27 ((PAD_DS_LGPIO_BASE + 27)| PAD_DS_GROUP6_16) ///< LGPIO27 +#define PAD_DS_LGPIO28 ((PAD_DS_LGPIO_BASE + 28)| PAD_DS_GROUP6_16) ///< LGPIO28 +#define PAD_DS_LGPIO29 ((PAD_DS_LGPIO_BASE + 29)| PAD_DS_GROUP6_16) ///< LGPIO29 +#define PAD_DS_LGPIO30 ((PAD_DS_LGPIO_BASE + 30)| PAD_DS_GROUP4_10) ///< LGPIO30 +#define PAD_DS_LGPIO31 ((PAD_DS_LGPIO_BASE + 31)| PAD_DS_GROUP4_10) ///< LGPIO31 +#define PAD_DS_LGPIO32 ((PAD_DS_LGPIO_BASE + 32)| PAD_DS_GROUP4_10) ///< LGPIO32 +//LCD group Driving/Sink end + +//DGPIO group Driving/Sink begin +#define PAD_DS_DGPIO_BASE 160 +#define PAD_DS_DGPIO0 ((PAD_DS_DGPIO_BASE + 0) | PAD_DS_GROUP16) ///< DGPIO0 +#define PAD_DS_DGPIO1 ((PAD_DS_DGPIO_BASE + 1) | PAD_DS_GROUP16) ///< DGPIO1 +#define PAD_DS_DGPIO2 ((PAD_DS_DGPIO_BASE + 2) | PAD_DS_GROUP16) ///< DGPIO2 +#define PAD_DS_DGPIO3 ((PAD_DS_DGPIO_BASE + 3) | PAD_DS_GROUP16) ///< DGPIO3 +#define PAD_DS_DGPIO4 ((PAD_DS_DGPIO_BASE + 4) | PAD_DS_GROUP16) ///< DGPIO4 +#define PAD_DS_DGPIO5 ((PAD_DS_DGPIO_BASE + 5) | PAD_DS_GROUP16) ///< DGPIO5 +#define PAD_DS_DGPIO6 ((PAD_DS_DGPIO_BASE + 6) | PAD_DS_GROUP8) ///< DGPIO6 +#define PAD_DS_DGPIO7 ((PAD_DS_DGPIO_BASE + 7) | PAD_DS_GROUP8) ///< DGPIO7 +#define PAD_DS_DGPIO8 ((PAD_DS_DGPIO_BASE + 8) | PAD_DS_GROUP8) ///< DGPIO8 +#define PAD_DS_DGPIO9 ((PAD_DS_DGPIO_BASE + 9) | PAD_DS_GROUP8) ///< DGPIO9 +#define PAD_DS_DGPIO10 ((PAD_DS_DGPIO_BASE + 10)| PAD_DS_GROUP8) ///< DGPIO10 +#define PAD_DS_DGPIO11 ((PAD_DS_DGPIO_BASE + 11)| PAD_DS_GROUP4_10) ///< DGPIO11 +#define PAD_DS_DGPIO12 ((PAD_DS_DGPIO_BASE + 12)| PAD_DS_GROUP4_10) ///< DGPIO12 +//DGPIO group Driving/Sink end +//@} + +#endif + +/** + @addtogroup mIDrvSys_PAD +*/ +//@{ +#define PAD_PUPD0_REG_OFS 0x00 + +#define PAD_PWR0_REG_OFS 0x78 + +#define PAD_REG_TO_BASE(reg) (((reg)/(4))*(32)) + +#define PAD_CGPIO_BASE PAD_REG_TO_BASE(0x00) // 0x00~0x04 +#define PAD_PGPIO_BASE PAD_REG_TO_BASE(0x08) // 0x08, 0x0C +#define PAD_DGPIO_BASE PAD_REG_TO_BASE(0x10) // 0x10 +#define PAD_SGPIO_BASE PAD_REG_TO_BASE(0x14) // 0x14 +#define PAD_HSIGPIO_BASE PAD_REG_TO_BASE(0x18) // 0x18 +#define PAD_DSIGPIO_BASE PAD_REG_TO_BASE(0x1C) // 0x1C +#define PAD_LGPIO_BASE PAD_REG_TO_BASE(0x20) // 0x20 +#define PAD_AGPIO_BASE PAD_REG_TO_BASE(0x24) // 0x24 + +/* 4 level */ +#define PAD_4L_DS_CGPIO_BASE PAD_REG_TO_BASE(0x2C) // 0x2C +#define PAD_4L_DS_PGPIO_BASE PAD_REG_TO_BASE(0x30) // 0x30~0x34 +#define PAD_4L_DS_DGPIO_BASE PAD_REG_TO_BASE(0x38) // 0x38 +#define PAD_4L_DS_SGPIO_BASE PAD_REG_TO_BASE(0x3C) // 0x3C +#define PAD_4L_DS_HSIGPIO_BASE PAD_REG_TO_BASE(0x40) // 0x40 +#define PAD_4L_DS_DSIGPIO_BASE PAD_REG_TO_BASE(0x44) // 0x44 +#define PAD_4L_DS_LGPIO_BASE PAD_REG_TO_BASE(0x48) // 0x48 +#define PAD_4L_DS_AGPIO_BASE PAD_REG_TO_BASE(0x4C) // 0x4C + +/* 8 level */ +#define PAD_8L_DS_CGPIO_BASE PAD_REG_TO_BASE(0x50) // 0x50~0x58 +#define PAD_8L_DS_SGPIO_BASE PAD_REG_TO_BASE(0x60) // 0x60 + +/* 2 level */ +#define PAD_2L_DS_HSIGPIO_BASE PAD_REG_TO_BASE(0x5C) // 0x5C + +/** + @name Pad type pin ID. + + Pad type pin ID. + + Pad ID of pad_set_pull_up_down (), pad_get_pull_up_down (). +*/ +#define PAD_PIN_NOT_EXIST (64) // For backward compatible +//@{ +typedef enum { + // CGPIO group + PAD_PIN_CGPIO0 = (PAD_CGPIO_BASE + 0), ///< C_GPIO_0 + PAD_PIN_CGPIO1 = (PAD_CGPIO_BASE + 2), ///< C_GPIO_1 + PAD_PIN_CGPIO2 = (PAD_CGPIO_BASE + 4), ///< C_GPIO_2 + PAD_PIN_CGPIO3 = (PAD_CGPIO_BASE + 6), ///< C_GPIO_3 + PAD_PIN_CGPIO4 = (PAD_CGPIO_BASE + 8), ///< C_GPIO_4 + PAD_PIN_CGPIO5 = (PAD_CGPIO_BASE + 10), ///< C_GPIO_5 + PAD_PIN_CGPIO6 = (PAD_CGPIO_BASE + 12), ///< C_GPIO_6 + PAD_PIN_CGPIO7 = (PAD_CGPIO_BASE + 14), ///< C_GPIO_7 + PAD_PIN_CGPIO8 = (PAD_CGPIO_BASE + 16), ///< C_GPIO_8 + PAD_PIN_CGPIO9 = (PAD_CGPIO_BASE + 18), ///< C_GPIO_9 + PAD_PIN_CGPIO10 = (PAD_CGPIO_BASE + 20), ///< C_GPIO_10 + PAD_PIN_CGPIO11 = (PAD_CGPIO_BASE + 22), ///< C_GPIO_11 + PAD_PIN_CGPIO12 = (PAD_CGPIO_BASE + 24), ///< C_GPIO_12 + PAD_PIN_CGPIO13 = (PAD_CGPIO_BASE + 26), ///< C_GPIO_13 + PAD_PIN_CGPIO14 = (PAD_CGPIO_BASE + 28), ///< C_GPIO_14 + PAD_PIN_CGPIO15 = (PAD_CGPIO_BASE + 30), ///< C_GPIO_15 + PAD_PIN_CGPIO16 = (PAD_CGPIO_BASE + 32), ///< C_GPIO_16 + PAD_PIN_CGPIO17 = (PAD_CGPIO_BASE + 34), ///< C_GPIO_17 + PAD_PIN_CGPIO18 = (PAD_CGPIO_BASE + 36), ///< C_GPIO_18 + PAD_PIN_CGPIO19 = (PAD_CGPIO_BASE + 38), ///< C_GPIO_19 + PAD_PIN_CGPIO20 = (PAD_CGPIO_BASE + 40), ///< C_GPIO_20 + PAD_PIN_CGPIO21 = (PAD_CGPIO_BASE + 42), ///< C_GPIO_21 + PAD_PIN_CGPIO22 = (PAD_CGPIO_BASE + 44), ///< C_GPIO_22 + PAD_PIN_CGPIO23 = (PAD_CGPIO_BASE + 46), ///< C_GPIO_23 + PAD_PIN_CGPIO24 = (PAD_CGPIO_BASE + 48), ///< C_GPIO_24 + + // PGPIO group + PAD_PIN_PGPIO0 = (PAD_PGPIO_BASE + 0), ///< P_GPIO_0 + PAD_PIN_PGPIO1 = (PAD_PGPIO_BASE + 2), ///< P_GPIO_1 + PAD_PIN_PGPIO2 = (PAD_PGPIO_BASE + 4), ///< P_GPIO_2 + PAD_PIN_PGPIO3 = (PAD_PGPIO_BASE + 6), ///< P_GPIO_3 + PAD_PIN_PGPIO4 = (PAD_PGPIO_BASE + 8), ///< P_GPIO_4 + PAD_PIN_PGPIO5 = (PAD_PGPIO_BASE + 10), ///< P_GPIO_5 + PAD_PIN_PGPIO6 = (PAD_PGPIO_BASE + 12), ///< P_GPIO_6 + PAD_PIN_PGPIO7 = (PAD_PGPIO_BASE + 14), ///< P_GPIO_7 + PAD_PIN_PGPIO8 = (PAD_PGPIO_BASE + 16), ///< P_GPIO_8 + PAD_PIN_PGPIO9 = (PAD_PGPIO_BASE + 18), ///< P_GPIO_9 + PAD_PIN_PGPIO10 = (PAD_PGPIO_BASE + 20), ///< P_GPIO_10 + PAD_PIN_PGPIO11 = (PAD_PGPIO_BASE + 22), ///< P_GPIO_11 + PAD_PIN_PGPIO12 = (PAD_PGPIO_BASE + 24), ///< P_GPIO_12 + PAD_PIN_PGPIO13 = (PAD_PGPIO_BASE + 26), ///< P_GPIO_13 + PAD_PIN_PGPIO14 = (PAD_PGPIO_BASE + 28), ///< P_GPIO_14 + PAD_PIN_PGPIO15 = (PAD_PGPIO_BASE + 30), ///< P_GPIO_15 + PAD_PIN_PGPIO16 = (PAD_PGPIO_BASE + 32), ///< P_GPIO_16 + PAD_PIN_PGPIO17 = (PAD_PGPIO_BASE + 34), ///< P_GPIO_17 + PAD_PIN_PGPIO18 = (PAD_PGPIO_BASE + 36), ///< P_GPIO_18 + PAD_PIN_PGPIO19 = (PAD_PGPIO_BASE + 38), ///< P_GPIO_19 + PAD_PIN_PGPIO20 = (PAD_PGPIO_BASE + 40), ///< P_GPIO_20 + PAD_PIN_PGPIO21 = (PAD_PGPIO_BASE + 42), ///< P_GPIO_21 + PAD_PIN_PGPIO22 = (PAD_PGPIO_BASE + 44), ///< P_GPIO_22 + PAD_PIN_PGPIO23 = (PAD_PGPIO_BASE + 46), ///< P_GPIO_23 + PAD_PIN_PGPIO24 = (PAD_PGPIO_BASE + 48), ///< P_GPIO_24 + PAD_PIN_PGPIO25 = (PAD_PGPIO_BASE + 50), ///< P_GPIO_25 + + // DGPIO group + PAD_PIN_DGPIO0 = (PAD_DGPIO_BASE + 0), ///< D_GPIO_0 + PAD_PIN_DGPIO1 = (PAD_DGPIO_BASE + 2), ///< D_GPIO_1 + PAD_PIN_DGPIO2 = (PAD_DGPIO_BASE + 4), ///< D_GPIO_2 + PAD_PIN_DGPIO3 = (PAD_DGPIO_BASE + 6), ///< D_GPIO_3 + PAD_PIN_DGPIO4 = (PAD_DGPIO_BASE + 8), ///< D_GPIO_4 + PAD_PIN_DGPIO5 = (PAD_DGPIO_BASE + 10), ///< D_GPIO_5 + PAD_PIN_DGPIO6 = (PAD_DGPIO_BASE + 12), ///< D_GPIO_6 + PAD_PIN_DGPIO7 = (PAD_DGPIO_BASE + 14), ///< D_GPIO_7 + + // SGPIO group + PAD_PIN_SGPIO0 = (PAD_SGPIO_BASE + 0), ///< S_GPIO_0 + PAD_PIN_SGPIO1 = (PAD_SGPIO_BASE + 2), ///< S_GPIO_1 + PAD_PIN_SGPIO2 = (PAD_SGPIO_BASE + 4), ///< S_GPIO_2 + PAD_PIN_SGPIO3 = (PAD_SGPIO_BASE + 6), ///< S_GPIO_3 + PAD_PIN_SGPIO4 = (PAD_SGPIO_BASE + 8), ///< S_GPIO_4 + PAD_PIN_SGPIO5 = (PAD_SGPIO_BASE + 10), ///< S_GPIO_5 + PAD_PIN_SGPIO6 = (PAD_SGPIO_BASE + 12), ///< S_GPIO_6 + PAD_PIN_SGPIO7 = (PAD_SGPIO_BASE + 14), ///< S_GPIO_7 + PAD_PIN_SGPIO8 = (PAD_SGPIO_BASE + 16), ///< S_GPIO_8 + + // HSIGPIO group + PAD_PIN_HSIGPIO0 = (PAD_HSIGPIO_BASE + 0), ///< HSI_GPIO_0 + PAD_PIN_HSIGPIO1 = (PAD_HSIGPIO_BASE + 2), ///< HSI_GPIO_1 + PAD_PIN_HSIGPIO2 = (PAD_HSIGPIO_BASE + 4), ///< HSI_GPIO_2 + PAD_PIN_HSIGPIO3 = (PAD_HSIGPIO_BASE + 6), ///< HSI_GPIO_3 + PAD_PIN_HSIGPIO4 = (PAD_HSIGPIO_BASE + 8), ///< HSI_GPIO_4 + PAD_PIN_HSIGPIO5 = (PAD_HSIGPIO_BASE + 10), ///< HSI_GPIO_5 + PAD_PIN_HSIGPIO6 = (PAD_HSIGPIO_BASE + 12), ///< HSI_GPIO_6 + PAD_PIN_HSIGPIO7 = (PAD_HSIGPIO_BASE + 14), ///< HSI_GPIO_7 + PAD_PIN_HSIGPIO8 = (PAD_HSIGPIO_BASE + 16), ///< HSI_GPIO_8 + PAD_PIN_HSIGPIO9 = (PAD_HSIGPIO_BASE + 18), ///< HSI_GPIO_9 + PAD_PIN_HSIGPIO10 = (PAD_HSIGPIO_BASE + 20), ///< HSI_GPIO_10 + PAD_PIN_HSIGPIO11 = (PAD_HSIGPIO_BASE + 22), ///< HSI_GPIO_11 + + // DSIGPIO group + PAD_PIN_DSIGPIO0 = (PAD_DSIGPIO_BASE + 0), ///< DSI_GPIO_0 + PAD_PIN_DSIGPIO1 = (PAD_DSIGPIO_BASE + 2), ///< DSI_GPIO_1 + PAD_PIN_DSIGPIO2 = (PAD_DSIGPIO_BASE + 4), ///< DSI_GPIO_2 + PAD_PIN_DSIGPIO3 = (PAD_DSIGPIO_BASE + 6), ///< DSI_GPIO_3 + PAD_PIN_DSIGPIO4 = (PAD_DSIGPIO_BASE + 8), ///< DSI_GPIO_4 + PAD_PIN_DSIGPIO5 = (PAD_DSIGPIO_BASE + 10), ///< DSI_GPIO_5 + PAD_PIN_DSIGPIO6 = (PAD_DSIGPIO_BASE + 12), ///< DSI_GPIO_6 + PAD_PIN_DSIGPIO7 = (PAD_DSIGPIO_BASE + 14), ///< DSI_GPIO_7 + PAD_PIN_DSIGPIO8 = (PAD_DSIGPIO_BASE + 16), ///< DSI_GPIO_8 + PAD_PIN_DSIGPIO9 = (PAD_DSIGPIO_BASE + 18), ///< DSI_GPIO_9 + PAD_PIN_DSIGPIO10 = (PAD_DSIGPIO_BASE + 20), ///< DSI_GPIO_10 + + // LGPIO group + PAD_PIN_LGPIO0 = (PAD_LGPIO_BASE + 0), ///< L_GPIO_0 + PAD_PIN_LGPIO1 = (PAD_LGPIO_BASE + 2), ///< L_GPIO_1 + PAD_PIN_LGPIO2 = (PAD_LGPIO_BASE + 4), ///< L_GPIO_2 + PAD_PIN_LGPIO3 = (PAD_LGPIO_BASE + 6), ///< L_GPIO_3 + PAD_PIN_LGPIO4 = (PAD_LGPIO_BASE + 8), ///< L_GPIO_4 + PAD_PIN_LGPIO5 = (PAD_LGPIO_BASE + 10), ///< L_GPIO_5 + PAD_PIN_LGPIO6 = (PAD_LGPIO_BASE + 12), ///< L_GPIO_6 + PAD_PIN_LGPIO7 = (PAD_LGPIO_BASE + 14), ///< L_GPIO_7 + PAD_PIN_LGPIO8 = (PAD_LGPIO_BASE + 16), ///< L_GPIO_8 + PAD_PIN_LGPIO9 = (PAD_LGPIO_BASE + 18), ///< L_GPIO_9 + + // AGPIO group + PAD_PIN_AGPIO0 = (PAD_AGPIO_BASE + 0), ///< A_GPIO_0 + PAD_PIN_AGPIO1 = (PAD_AGPIO_BASE + 2), ///< A_GPIO_1 + PAD_PIN_AGPIO2 = (PAD_AGPIO_BASE + 4), ///< A_GPIO_2 + PAD_PIN_AGPIO3 = (PAD_AGPIO_BASE + 6), ///< A_GPIO_3 + + PAD_PIN_MAX = PAD_PIN_AGPIO3, + + ENUM_DUMMY4WORD(PAD_PIN) +} PAD_PIN; +//@} + +/** + Pad type select + + Pad type select + + Pad type value for pad_set_pull_up_down(), pad_get_pull_up_down(). +*/ +typedef enum { + PAD_NONE = 0x00, ///< none of pull up/down + PAD_PULLDOWN = 0x01, ///< pull down + PAD_PULLUP = 0x02, ///< pull up + PAD_KEEPER = 0x03, ///< keeper + PAD_STRONG_PULLUP = 0x03, ///< strong pull up + + ENUM_DUMMY4WORD(PAD_PULL) +} PAD_PULL; + +/** + Pad driving select + + Pad driving select + + Pad driving value for pad_set_driving_sink(), pad_get_driving_sink(). +*/ +typedef enum { + PAD_DRIVINGSINK_LEVEL_0 = 0x00, + PAD_DRIVINGSINK_LEVEL_1 = 0x01, + PAD_DRIVINGSINK_LEVEL_2 = 0x02, + PAD_DRIVINGSINK_LEVEL_3 = 0x03, + PAD_DRIVINGSINK_LEVEL_4 = 0x04, + PAD_DRIVINGSINK_LEVEL_5 = 0x05, + PAD_DRIVINGSINK_LEVEL_6 = 0x06, + PAD_DRIVINGSINK_LEVEL_7 = 0x07, + PAD_DRIVINGSINK_LEVEL_8 = 0x08, + PAD_DRIVINGSINK_LEVEL_9 = 0x09, + PAD_DRIVINGSINK_LEVEL_10 = 0x0A, + PAD_DRIVINGSINK_LEVEL_11 = 0x0B, + PAD_DRIVINGSINK_LEVEL_12 = 0x0C, + PAD_DRIVINGSINK_LEVEL_13 = 0x0D, + PAD_DRIVINGSINK_LEVEL_14 = 0x0E, + PAD_DRIVINGSINK_LEVEL_15 = 0x0F, + + + PAD_DRIVINGSINK_10MA = 0x2, + + ENUM_DUMMY4WORD(PAD_DRIVINGSINK) +} PAD_DRIVINGSINK; + +/** + @name Pad driving pin ID. + + Pad driving pin ID. + + Pad ID of pad_set_driving_sink(), pad_get_driving_sink() +*/ +//@{ +typedef enum { + // CGPIO group + PAD_DS_CGPIO0 = (PAD_8L_DS_CGPIO_BASE + 0), ///< C_GPIO_0 + PAD_DS_CGPIO1 = (PAD_8L_DS_CGPIO_BASE + 4), ///< C_GPIO_1 + PAD_DS_CGPIO2 = (PAD_8L_DS_CGPIO_BASE + 8), ///< C_GPIO_2 + PAD_DS_CGPIO3 = (PAD_8L_DS_CGPIO_BASE + 12), ///< C_GPIO_3 + PAD_DS_CGPIO4 = (PAD_8L_DS_CGPIO_BASE + 16), ///< C_GPIO_4 + PAD_DS_CGPIO5 = (PAD_8L_DS_CGPIO_BASE + 20), ///< C_GPIO_5 + PAD_DS_CGPIO6 = (PAD_8L_DS_CGPIO_BASE + 24), ///< C_GPIO_6 + PAD_DS_CGPIO7 = (PAD_8L_DS_CGPIO_BASE + 28), ///< C_GPIO_7 + PAD_DS_CGPIO8 = (PAD_8L_DS_CGPIO_BASE + 32), ///< C_GPIO_8 + PAD_DS_CGPIO9 = (PAD_8L_DS_CGPIO_BASE + 36), ///< C_GPIO_9 + PAD_DS_CGPIO10 = (PAD_8L_DS_CGPIO_BASE + 40), ///< C_GPIO_10 + PAD_DS_CGPIO11 = (PAD_8L_DS_CGPIO_BASE + 44), ///< C_GPIO_11 + PAD_DS_CGPIO12 = (PAD_8L_DS_CGPIO_BASE + 48), ///< C_GPIO_12 + PAD_DS_CGPIO13 = (PAD_8L_DS_CGPIO_BASE + 52), ///< C_GPIO_13 + PAD_DS_CGPIO14 = (PAD_8L_DS_CGPIO_BASE + 56), ///< C_GPIO_14 + PAD_DS_CGPIO15 = (PAD_8L_DS_CGPIO_BASE + 60), ///< C_GPIO_15 + PAD_DS_CGPIO16 = (PAD_8L_DS_CGPIO_BASE + 64), ///< C_GPIO_16 + PAD_DS_CGPIO17 = (PAD_8L_DS_CGPIO_BASE + 68), ///< C_GPIO_17 + PAD_DS_CGPIO18 = (PAD_8L_DS_CGPIO_BASE + 72), ///< C_GPIO_18 + PAD_DS_CGPIO19 = (PAD_8L_DS_CGPIO_BASE + 76), ///< C_GPIO_19 + + PAD_DS_CGPIO20 = (PAD_4L_DS_CGPIO_BASE + 8), ///< C_GPIO_20 + PAD_DS_CGPIO21 = (PAD_4L_DS_CGPIO_BASE + 10), ///< C_GPIO_21 + PAD_DS_CGPIO22 = (PAD_4L_DS_CGPIO_BASE + 12), ///< C_GPIO_22 + PAD_DS_CGPIO23 = (PAD_4L_DS_CGPIO_BASE + 14), ///< C_GPIO_23 + PAD_DS_CGPIO24 = (PAD_4L_DS_CGPIO_BASE + 16), ///< C_GPIO_24 + + // PGPIO group + PAD_DS_PGPIO0 = (PAD_4L_DS_PGPIO_BASE + 0), ///< P_GPIO_0 + PAD_DS_PGPIO1 = (PAD_4L_DS_PGPIO_BASE + 2), ///< P_GPIO_1 + PAD_DS_PGPIO2 = (PAD_4L_DS_PGPIO_BASE + 4), ///< P_GPIO_2 + PAD_DS_PGPIO3 = (PAD_4L_DS_PGPIO_BASE + 6), ///< P_GPIO_3 + PAD_DS_PGPIO4 = (PAD_4L_DS_PGPIO_BASE + 8), ///< P_GPIO_4 + PAD_DS_PGPIO5 = (PAD_4L_DS_PGPIO_BASE + 10), ///< P_GPIO_5 + PAD_DS_PGPIO6 = (PAD_4L_DS_PGPIO_BASE + 12), ///< P_GPIO_6 + PAD_DS_PGPIO7 = (PAD_4L_DS_PGPIO_BASE + 14), ///< P_GPIO_7 + PAD_DS_PGPIO8 = (PAD_4L_DS_PGPIO_BASE + 16), ///< P_GPIO_8 + PAD_DS_PGPIO9 = (PAD_4L_DS_PGPIO_BASE + 18), ///< P_GPIO_9 + PAD_DS_PGPIO10 = (PAD_4L_DS_PGPIO_BASE + 20), ///< P_GPIO_10 + PAD_DS_PGPIO11 = (PAD_4L_DS_PGPIO_BASE + 22), ///< P_GPIO_11 + PAD_DS_PGPIO12 = (PAD_4L_DS_PGPIO_BASE + 24), ///< P_GPIO_12 + PAD_DS_PGPIO13 = (PAD_4L_DS_PGPIO_BASE + 26), ///< P_GPIO_13 + PAD_DS_PGPIO14 = (PAD_4L_DS_PGPIO_BASE + 28), ///< P_GPIO_14 + PAD_DS_PGPIO15 = (PAD_4L_DS_PGPIO_BASE + 30), ///< P_GPIO_15 + PAD_DS_PGPIO16 = (PAD_4L_DS_PGPIO_BASE + 32), ///< P_GPIO_16 + PAD_DS_PGPIO17 = (PAD_4L_DS_PGPIO_BASE + 34), ///< P_GPIO_17 + PAD_DS_PGPIO18 = (PAD_4L_DS_PGPIO_BASE + 36), ///< P_GPIO_18 + PAD_DS_PGPIO19 = (PAD_4L_DS_PGPIO_BASE + 38), ///< P_GPIO_19 + PAD_DS_PGPIO20 = (PAD_4L_DS_PGPIO_BASE + 40), ///< P_GPIO_20 + PAD_DS_PGPIO21 = (PAD_4L_DS_PGPIO_BASE + 42), ///< P_GPIO_21 + PAD_DS_PGPIO22 = (PAD_4L_DS_PGPIO_BASE + 44), ///< P_GPIO_22 + PAD_DS_PGPIO23 = (PAD_4L_DS_PGPIO_BASE + 46), ///< P_GPIO_23 + PAD_DS_PGPIO24 = (PAD_4L_DS_PGPIO_BASE + 48), ///< P_GPIO_24 + PAD_DS_PGPIO25 = (PAD_4L_DS_PGPIO_BASE + 50), ///< P_GPIO_25 + + // DGPIO group + PAD_DS_DGPIO0 = (PAD_4L_DS_DGPIO_BASE + 0), ///< D_GPIO_0 + PAD_DS_DGPIO1 = (PAD_4L_DS_DGPIO_BASE + 2), ///< D_GPIO_1 + PAD_DS_DGPIO2 = (PAD_4L_DS_DGPIO_BASE + 4), ///< D_GPIO_2 + PAD_DS_DGPIO3 = (PAD_4L_DS_DGPIO_BASE + 6), ///< D_GPIO_3 + PAD_DS_DGPIO4 = (PAD_4L_DS_DGPIO_BASE + 8), ///< D_GPIO_4 + PAD_DS_DGPIO5 = (PAD_4L_DS_DGPIO_BASE + 10), ///< D_GPIO_5 + PAD_DS_DGPIO6 = (PAD_4L_DS_DGPIO_BASE + 12), ///< D_GPIO_6 + PAD_DS_DGPIO7 = (PAD_4L_DS_DGPIO_BASE + 14), ///< D_GPIO_7 + PAD_DS_SYS_RST = (PAD_4L_DS_DGPIO_BASE + 28), ///< SYS_RST + + // SGPIO group + PAD_DS_SGPIO0 = (PAD_8L_DS_SGPIO_BASE + 0), ///< S_GPIO_0 + PAD_DS_SGPIO1 = (PAD_4L_DS_SGPIO_BASE + 2), ///< S_GPIO_1 + PAD_DS_SGPIO2 = (PAD_4L_DS_SGPIO_BASE + 4), ///< S_GPIO_2 + PAD_DS_SGPIO3 = (PAD_4L_DS_SGPIO_BASE + 6), ///< S_GPIO_3 + PAD_DS_SGPIO4 = (PAD_4L_DS_SGPIO_BASE + 8), ///< S_GPIO_4 + PAD_DS_SGPIO5 = (PAD_4L_DS_SGPIO_BASE + 10), ///< S_GPIO_5 + PAD_DS_SGPIO6 = (PAD_4L_DS_SGPIO_BASE + 12), ///< S_GPIO_6 + PAD_DS_SGPIO7 = (PAD_4L_DS_SGPIO_BASE + 14), ///< S_GPIO_7 + PAD_DS_SGPIO8 = (PAD_4L_DS_SGPIO_BASE + 16), ///< S_GPIO_8 + + // HSIGPIO group + PAD_DS_HSIGPIO0 = (PAD_2L_DS_HSIGPIO_BASE + 0), ///< HSI_GPIO_0 + PAD_DS_HSIGPIO1 = (PAD_2L_DS_HSIGPIO_BASE + 1), ///< HSI_GPIO_1 + PAD_DS_HSIGPIO2 = (PAD_2L_DS_HSIGPIO_BASE + 2), ///< HSI_GPIO_2 + PAD_DS_HSIGPIO3 = (PAD_2L_DS_HSIGPIO_BASE + 3), ///< HSI_GPIO_3 + PAD_DS_HSIGPIO4 = (PAD_2L_DS_HSIGPIO_BASE + 4), ///< HSI_GPIO_4 + PAD_DS_HSIGPIO5 = (PAD_2L_DS_HSIGPIO_BASE + 5), ///< HSI_GPIO_5 + PAD_DS_HSIGPIO6 = (PAD_2L_DS_HSIGPIO_BASE + 6), ///< HSI_GPIO_6 + PAD_DS_HSIGPIO7 = (PAD_2L_DS_HSIGPIO_BASE + 7), ///< HSI_GPIO_7 + PAD_DS_HSIGPIO8 = (PAD_2L_DS_HSIGPIO_BASE + 8), ///< HSI_GPIO_8 + PAD_DS_HSIGPIO9 = (PAD_2L_DS_HSIGPIO_BASE + 9), ///< HSI_GPIO_9 + PAD_DS_HSIGPIO10 = (PAD_4L_DS_HSIGPIO_BASE + 20), ///< HSI_GPIO_10 + PAD_DS_HSIGPIO11 = (PAD_4L_DS_HSIGPIO_BASE + 22), ///< HSI_GPIO_11 + + // DSIGPIO group + PAD_DS_DSIGPIO0 = (PAD_4L_DS_DSIGPIO_BASE + 0), ///< DSI_GPIO_0 + PAD_DS_DSIGPIO1 = (PAD_4L_DS_DSIGPIO_BASE + 1), ///< DSI_GPIO_1 + PAD_DS_DSIGPIO2 = (PAD_4L_DS_DSIGPIO_BASE + 2), ///< DSI_GPIO_2 + PAD_DS_DSIGPIO3 = (PAD_4L_DS_DSIGPIO_BASE + 3), ///< DSI_GPIO_3 + PAD_DS_DSIGPIO4 = (PAD_4L_DS_DSIGPIO_BASE + 4), ///< DSI_GPIO_4 + PAD_DS_DSIGPIO5 = (PAD_4L_DS_DSIGPIO_BASE + 5), ///< DSI_GPIO_5 + PAD_DS_DSIGPIO6 = (PAD_4L_DS_DSIGPIO_BASE + 6), ///< DSI_GPIO_6 + PAD_DS_DSIGPIO7 = (PAD_4L_DS_DSIGPIO_BASE + 7), ///< DSI_GPIO_7 + PAD_DS_DSIGPIO8 = (PAD_4L_DS_DSIGPIO_BASE + 8), ///< DSI_GPIO_8 + PAD_DS_DSIGPIO9 = (PAD_4L_DS_DSIGPIO_BASE + 9), ///< DSI_GPIO_9 + PAD_DS_DSIGPIO10 = (PAD_4L_DS_DSIGPIO_BASE + 20), ///< DSI_GPIO_10 + + // LGPIO group + PAD_DS_LGPIO0 = (PAD_4L_DS_LGPIO_BASE + 0), ///< L_GPIO_0 + PAD_DS_LGPIO1 = (PAD_4L_DS_LGPIO_BASE + 1), ///< L_GPIO_1 + PAD_DS_LGPIO2 = (PAD_4L_DS_LGPIO_BASE + 2), ///< L_GPIO_2 + PAD_DS_LGPIO3 = (PAD_4L_DS_LGPIO_BASE + 3), ///< L_GPIO_3 + PAD_DS_LGPIO4 = (PAD_4L_DS_LGPIO_BASE + 4), ///< L_GPIO_4 + PAD_DS_LGPIO5 = (PAD_4L_DS_LGPIO_BASE + 5), ///< L_GPIO_5 + PAD_DS_LGPIO6 = (PAD_4L_DS_LGPIO_BASE + 6), ///< L_GPIO_6 + PAD_DS_LGPIO7 = (PAD_4L_DS_LGPIO_BASE + 7), ///< L_GPIO_7 + PAD_DS_LGPIO8 = (PAD_4L_DS_LGPIO_BASE + 8), ///< L_GPIO_8 + PAD_DS_LGPIO9 = (PAD_4L_DS_LGPIO_BASE + 9), ///< L_GPIO_9 + + // AGPIO group + PAD_DS_AGPIO0 = (PAD_4L_DS_AGPIO_BASE + 0), ///< A_GPIO_0 + PAD_DS_AGPIO1 = (PAD_4L_DS_AGPIO_BASE + 1), ///< A_GPIO_1 + PAD_DS_AGPIO2 = (PAD_4L_DS_AGPIO_BASE + 2), ///< A_GPIO_2 + PAD_DS_AGPIO3 = (PAD_4L_DS_AGPIO_BASE + 3), ///< A_GPIO_3 + + PAD_DS_MAX = PAD_DS_SGPIO0, + + ENUM_DUMMY4WORD(PAD_DS) +} PAD_DS; +//@} + +/** + Pad power ID select + + Pad power ID for PAD_POWER_STRUCT. +*/ +typedef enum { + PAD_POWERID_MC0 = 0x00, ///< Pad power id for MC0 + PAD_POWERID_MC1 = 0x01, ///< Pad power id for MC1 + PAD_POWERID_ADC = 0x02, ///< Pad power id for Audio ADC + PAD_POWERID_CSI = 0x04, ///< Pad power id for CSI/LVDS + + ENUM_DUMMY4WORD(PAD_POWERID) +} PAD_POWERID; + +/** + Pad power select + + Pad power value for PAD_POWER_STRUCT. +*/ +typedef enum { + PAD_3P3V = 0x00, ///< Pad power is 3.3V + PAD_AVDD = 0x00, ///< Pad power is AVDD ( for PAD_POWERID_ADC use) + PAD_1P8V = 0x01, ///< Pad power is 1.8V + PAD_PAD_VAD = 0x01, ///< Pad power is PAD_ADC_VAD ( for PAD_POWERID_ADC use) + + ENUM_DUMMY4WORD(PAD_POWER) +} PAD_POWER; + +/** + Pad power VAD for PAD_POWERID_ADC + + Pad power VAD value for PAD_POWER_STRUCT. +*/ +typedef enum { + PAD_VAD_2P9V = 0x00, ///< Pad power VAD = 2.9V + PAD_VAD_3P0V = 0x01, ///< Pad power VAD = 3.0V + PAD_VAD_3P1V = 0x03, ///< Pad power VAD = 3.1V + + PAD_VAD_2P4V = 0x100, ///< Pad power VAD = 2.4V + PAD_VAD_2P5V = 0x101, ///< Pad power VAD = 2.5V + PAD_VAD_2P6V = 0x103, ///< Pad power VAD = 2.6V + + ENUM_DUMMY4WORD(PAD_VAD) +} PAD_VAD; + + +/** + PAD power structure + + PAD power setting for pad_set_power() +*/ +typedef struct { + PAD_POWERID power_id; ///< Pad power id + PAD_POWER power; ///< Pad power + BOOL bias_current; ///< Regulator bias current selection + ///< - @b FALSE: disable + ///< - @b TRUE: enable + BOOL opa_gain; ///< Regulator OPA gain/phase selection + ///< - @b FALSE: disable + ///< - @b TRUE: enable + BOOL pull_down; ///< Regulator output pull down control + ///< - @b FALSE: none + ///< - @b TRUE: pull down enable + BOOL regulator_en; ///< Regulator enable + ///< - @b FALSE: disable + ///< - @b TRUE: enable + PAD_VAD vad; ///< Pad VAD of PAD_POWERID_ADC when PAD_PAD_VAD = 1 +} PAD_POWER_STRUCT; + + + + + + + + +// Backward compatible usages +#define PAD_PIN_CGPIO23 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO23 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO24 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO25 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO26 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO27 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO28 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO29 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO30 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO31 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO32 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO33 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_PGPIO39 PAD_PIN_NOT_EXIST // For backward compatible + + +/* + Exporting APIs +*/ + +extern ER pad_setPullUpDown(UINT32 pin, PAD_PULL pulltype); +extern ER pad_setDrivingSink(UINT32 name, PAD_DRIVINGSINK driving); +//@} + + + +//@} + +#endif diff --git a/board/novatek/ns02501/loader/Include/Driver/regdef.h b/board/novatek/ns02501/loader/Include/Driver/regdef.h new file mode 100755 index 000000000000..802b49d9a059 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/regdef.h @@ -0,0 +1,199 @@ +/* + * MIPS register definitions, originally from: + * + * include/asm-mips/regdefs.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License, Version 2. See the file "COPYING" in the main directory of this + * archive for more details. + * + * Copyright (C) 1994, 1995 by Ralf Baechle + */ + +/* + * Symbolic register names for 32 bit ABI + */ +# define Mode_USR 0x10 /* M[4:0] = 01010 */ +# define Mode_FIQ 0x11 /* M[4:0] = 10001 */ +# define Mode_IRQ 0x12 /* M[4:0] = 10010 */ +# define Mode_SVC 0x13 /* M[4:0] = 10011 */ +# define Mode_ABT 0x17 /* M[4:0] = 10111 */ +# define Mode_UNDEF 0x1B /* M[4:0] = 11011 */ +# define Mode_SYS 0x1F /* M[4:0] = 11111 */ +# define Mode_MSK 0x1F /* M[4:0] = 11111 */ +# define I_Bit 0x80 /* 7 6 5 4 3 2 1 0 */ +# define F_Bit 0x40 /* I F T M4 M3 M2 M1 M0 */ + +/* + ************************************************************************ + * Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |W|W|R|W|NumSets |Associativity |L | + * |T|B|A|A| | |S | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CCSIDR_WT 31 +#define M_CCSIDR_WT (0x1 << S_CCSIDR_WT) /* Support write-through */ +#define S_CCSIDR_WB 30 +#define M_CCSIDR_WB (0x1 << S_CCSIDR_WB) /* Support write-back */ +#define S_CCSIDR_RA 29 +#define M_CCSIDR_RA (0x1 << S_CCSIDR_RA) /* Support read-allocation */ +#define S_CCSIDR_WA 28 +#define M_CCSIDR_WA (0x1 << S_CCSIDR_WA) /* Support write-allocation */ +#define S_CCSIDR_SETS 13 +#define M_CCSIDR_SETS (0x7fff << S_CCSIDR_SETS) /* Number of sets */ +#define S_CCSIDR_A 3 +#define M_CCSIDR_A (0x3ff << S_CCSIDR_A) /* Number of associatiovity */ +#define S_CCSIDR_LS 0 +#define M_CCSIDR_LS (0x7 << S_CCSIDR_LS) /* Cache line size */ + +/* + ************************************************************************ + * Cache Level ID Register, CLIDR (cp15, 1, c0, c0, 1) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |0|0|LoUU |LoC |LoUIS|CT7 |CT6 |CT5 |CT4 |CT3 |CT2 |CT1 | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CLIDR_LoUU 27 +#define M_CLIDR_LoUU (0x7 << S_CLIDR_LoUU) +#define S_CLIDR_LoC 24 +#define M_CLIDR_LoC (0x7 << S_CLIDR_LoC) /* Cache cohernecy level */ +#define S_CLIDR_LoUIS 21 +#define M_CLIDR_LoUIS (0x7 << S_CLIDR_LoUIS) +#define S_CLIDR_Ctype7 18 +#define M_CLIDR_Ctype7 (0x7 << S_CLIDR_Ctype7) /* Cache type of level 7 cache */ +#define S_CLIDR_Ctype6 15 +#define M_CLIDR_Ctype6 (0x7 << S_CLIDR_Ctype6) /* Cache type of level 6 cache */ +#define S_CLIDR_Ctype5 12 +#define M_CLIDR_Ctype5 (0x7 << S_CLIDR_Ctype5) /* Cache type of level 5 cache */ +#define S_CLIDR_Ctype4 9 +#define M_CLIDR_Ctype4 (0x7 << S_CLIDR_Ctype4) /* Cache type of level 4 cache */ +#define S_CLIDR_Ctype3 6 +#define M_CLIDR_Ctype3 (0x7 << S_CLIDR_Ctype3) /* Cache type of level 3 cache */ +#define S_CLIDR_Ctype2 3 +#define M_CLIDR_Ctype2 (0x7 << S_CLIDR_Ctype2) /* Cache type of level 2 cache */ +#define S_CLIDR_Ctype1 0 +#define M_CLIDR_Ctype1 (0x7 << S_CLIDR_Ctype1) /* Cache type of level 1 cache */ + +#define K_CLIDR_Ctype_NO 0 /* No cache */ +#define K_CLIDR_Ctype_IC 1 /* Instruction cache only */ +#define K_CLIDR_Ctype_DC 2 /* Data cache only */ +#define K_CLIDR_Ctype_ID 3 /* Seperate instruction and data caches, Harvard cache */ +#define K_CLIDR_Ctype_U 4 /* Unified cache, von Neumann cacge */ + +/* + ************************************************************************ + * Cache Size Selection Register, CCSELR (cp15, 2, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |Reserved |Level|I| + * | | |n| + * | | |D| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CCSELR_Level 1 +#define M_CCSELR_Level (0x7 << S_CCSELR_Level) /* Cache level */ +#define S_CCSELR_InD 0 +#define M_CCSELR_InD (0x1 << S_CCSELR_InD) /* I$ or D$ */ + +/* + ************************************************************************ + * System Control Register, SCTLR (cp15, 0, c1, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |R|T|A|T|N|0|E|V|1|U|F|U|W|1|H|1|0|R|V|I|Z|S|0|0|B|1|B|1|1|C|A|M| + * | |E|F|R|M| |E|E| | |I|W|X| |A| | | | | | |W| | | | |E| | | | | | + * | | |E|E|F| | | | | | |X|N| | | | | | | | | | | | | |N| | | | | | + * | | | | |I| | | | | | |N| | | | | | | | | | | | | | | | | | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_SCTLR_TE 30 +#define M_SCTLR_TE (0x1 << S_SCTLR_TE) /* Thumb exception enable */ +#define S_SCTLR_AFE 29 +#define M_SCTLR_AFE (0x1 << S_SCTLR_AFE) /* Access flag enable */ +#define S_SCTLR_TRE 28 +#define M_SCTLR_TRE (0x1 << S_SCTLR_TRE) /* TXE remap enable */ +#define S_SCTLR_NMFI 27 +#define M_SCTLR_NMFI (0x1 << S_SCTLR_NMFI) /* None-maskable FIQ enbale (RO) */ +#define S_SCTLR_EE 25 +#define M_SCTLR_EE (0x1 << S_SCTLR_EE) /* Exception Endianness: big-endian */ +#define S_SCTLR_VE 24 +#define M_SCTLR_VE (0x1 << S_SCTLR_VE) /* Interrupt Vector Enable */ +#define S_SCTLR_FI 21 +#define M_SCTLR_FI (0x1 << S_SCTLR_FI) /* Fast interrupt configuraiont enable */ +#define S_SCTLR_UWXN 20 +#define M_SCTLR_UWXN (0x1 << S_SCTLR_UWXN) /* */ +#define S_SCTLR_WXN 19 +#define M_SCTLR_WXN (0x1 << S_SCTLR_WXN) +#define S_SCTLR_HA 17 +#define M_SCTLR_HA (0x1 << S_SCTLR_HA) /* Hardware access flag enable */ +#define S_SCTLR_RR 14 +#define M_SCTLR_RR (0x1 << S_SCTLR_RR) /* Round-robin select */ +#define S_SCTLR_V 13 +#define M_SCTLR_V (0x1 << S_SCTLR_V) /* Vector bits */ +#define S_SCTLR_I 12 +#define M_SCTLR_I (0x1 << S_SCTLR_I) /* Instruction cache enable */ +#define S_SCTLR_Z 11 +#define M_SCTLR_Z (0x1 << S_SCTLR_Z) /* Branch prediction enable */ +#define S_SCTLR_SW 10 +#define M_SCTLR_SW (0x1 << S_SCTLR_SW) /* SW and SWP enable */ +#define S_SCTLR_CP15BEN 5 +#define M_SCTLR_CP15BEN (0x1 << S_SCTLR_CP15BEN) /* CP15 barrier support */ +#define S_SCTLR_C 2 +#define M_SCTLR_C (0x1 << S_SCTLR_C) /* Data and Unidied cache enable */ +#define S_SCTLR_A 1 +#define M_SCTLR_A (0x1 << S_SCTLR_A) /* Alignment fault checking enable */ +#define S_SCTLR_M 0 +#define M_SCTLR_M (0x1 << S_SCTLR_M) /* PL1&0 stage MMU enable */ + +/************************************************************************ + * Auxiliary Control Register, ACTLR (cp15, 0, c1, c0, 1) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |UNP/SBZP |P|A|E|S|RAZ|W|L|L|F| + * | |a|l|X|M| | |1|2|W| + * | |r|l|C|P| |f| | | | + * | | |o|L| | |l|p|p| | + * | |o|c| | | | |r|r| | + * | |n| | | | |z|e|e| | + * | | |o| | | |e|f|f| | + * | | |n| | | |r| | | | + * | | |e| | | |o|e|e| | + * | | | | | | |s|n|n| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_ACTLR_PAR_ON 9 +#define M_ACTLR_PAR_ON (0x1 << S_ACTLR_PAR_ON) /* Parity on */ +#define S_ACTLR_ALLOC_ONE 8 +#define M_ACTLR_ALLOC_ONE (0x1 << S_ACTLR_ALLOC_ONE) /* Alloc in one way */ +#define S_ACTLR_EXCL 7 +#define M_ACTLR_EXCL (0x1 << S_ACTLR_EXCL) /* Exclusive cache */ +#define S_ACTLR_SMP 6 +#define M_ACTLR_SMP (0x1 << S_ACTLR_SMP) /* SMP */ +#define S_ACTLR_W_FL_ZEROS 3 +#define M_ACTLR_W_FL_ZEROS (0x1 << S_ACTLR_W_FL_ZEROS) /* Write full line of zeros mode */ +#define S_ACTLR_L1_PERF_EN 2 +#define M_ACTLR_L1_PERF_EN (0x1 << S_ACTLR_L1_PERF_EN) /* Dside prefetch enable */ +#define S_ACTLR_L2_PERF_EN 1 +#define M_ACTLR_L2_PERF_EN (0x1 << S_ACTLR_L2_PERF_EN) /* L2 prefetch enable */ +#define S_ACTLR_FW 0 +#define M_ACTLR_FW (0x1 << S_ACTLR_FW) /* Cache and TLB maintenance boardcast */ + + diff --git a/board/novatek/ns02501/loader/Include/Driver/sie_base.h b/board/novatek/ns02501/loader/Include/Driver/sie_base.h new file mode 100755 index 000000000000..f5b99bb63c50 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/sie_base.h @@ -0,0 +1,808 @@ +/* + Public header file for SIE module. + + Copyright Novatek Microelectronics Corp. 2023. All rights reserved. +*/ + +#ifndef _SIE_BASE_H_ +#define _SIE_BASE_H_ + +#include "constant.h" + +#ifndef ENUM_DUMMY4WORD +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 +#endif + +typedef enum { + FUNC_PATGEN_EN = (1<<1), + FUNC_DVI_EN = (1<<2), + FUNC_OB_BYPASS_EN = (1<<5), + FUNC_DVS_DECOMP_EN = (1<<10), ///< only SIE3 + FUNC_DPC_EN = (1<<11), ///< only SIE1/2 + FUNC_ACT_DATAEXT_EN = (1<<13), ///< only SIE1/2 + FUNC_ECS_EN = (1<<15), + FUNC_DGAIN_EN = (1<<16), + FUNC_BS_H_EN = (1<<17), + FUNC_BS_V_EN = (1<<18), + FUNC_RAWENC_EN = (1<<19), ///< only SIE1/2 + FUNC_CGAIN_EN = (1<<20), + FUNC_STCS_HISTO_Y_EN = (1<<22), + FUNC_STCS_LA_EN = (1<<23), + FUNC_STCS_CA_EN = (1<<24), + FUNC_STCS_DGAIN_EN = (1<<25), + FUNC_EVS_EN = (1<<26), ///< only SIE3 + FUNC_DRAM_OUT0_EN = (1<<27), + FUNC_COMPANDING_EN = (1<<28) ///< only SIE1/2 +} SIE_FUNCTION_SEL; + +typedef enum { + MAIN_IN_PARA_MSTR_SNR = 0, ///< Parallel Master Sensor + MAIN_IN_CSI_1, ///< Serial Sensor from CSI-1 + MAIN_IN_CSI_2, ///< Serial Sensor from CSI-2 + MAIN_IN_2PPATGEN, ///< Self Pattern-Generator(2-pixel) + MAIN_IN_DRAM_IN, ///< from DRAM IN1 + MAIN_IN_MAX, + ENUM_DUMMY4WORD(SIE_MAIN_INPUT_SEL) +} SIE_MAIN_INPUT_SEL; + +typedef enum { + DATA_PHASE_RISING = 0, ///< rising edge latch/trigger + DATA_PHASE_FALLING, ///< falling edge latch/trigger + DATA_PHASE_MAX, + ENUM_DUMMY4WORD(SIE_PHASE_SEL) +} SIE_PHASE_SEL; + +typedef enum { + /* for RGGB 2x2 */ + CFAPAT_R = 0, ///< start pixel is R + CFAPAT_Gr = 1, ///< start pixel is GR + CFAPAT_Gb = 2, ///< start pixel is GB + CFAPAT_B = 3, ///< start pixel is B + + /* for RGBIR 4x4 */ + CFAPAT_RG_GI = 0, + CFAPAT_GB_IG = 1, + CFAPAT_GI_BG = 2, + CFAPAT_IG_GR = 3, + CFAPAT_BG_GI = 4, + CFAPAT_GR_IG = 5, + CFAPAT_GI_RG = 6, + CFAPAT_IG_GB = 7, + + CFAPAT_MAX, + ENUM_DUMMY4WORD(SIE_CFAPAT_SEL) +} SIE_CFAPAT_SEL; + +typedef enum { + PATGEN_MODE_COLORBAR_V = 1, ///< Color bar, Vertical + PATGEN_MODE_RANDOM, ///< Random + PATGEN_MODE_FIXED, ///< Fixed + PATGEN_MODE_HINCREASE, ///< 1D Increment + PATGEN_MODE_HVINCREASE, ///< 2D increment + PATGEN_MODE_MAX, + ENUM_DUMMY4WORD(SIE_PATGEN_MODE) +} SIE_PATGEN_MODE; + +typedef enum { + DATA_PACKBUS_8 = 0, ///< 8 bits packing + DATA_PACKBUS_10, ///< 10 bits packing + DATA_PACKBUS_12, ///< 12 bits packing + DATA_PACKBUS_16, ///< 16 bits packing + DATA_PACKBUS_MAX, + ENUM_DUMMY4WORD(SIE_DATA_PACKBUS_SEL) +} SIE_DATA_PACKBUS_SEL; + +typedef enum { + PARAL_RAW_BIT_12 = 0, ///< 12 bits input + PARAL_RAW_BIT_10, ///< 10 bits input + PARAL_RAW_BIT_MAX, + ENUM_DUMMY4WORD(SIE_PARAL_RAW_BITDEPTH) +} SIE_PARAL_RAW_BITDEPTH; + +typedef enum { + DRAM_OUT_MODE_NORMAL = 0, + DRAM_OUT_MODE_SINGLE, + DRAM_OUT_MODE_MAX, + ENUM_DUMMY4WORD(SIE_DRAM_OUT_MODE) +} SIE_DRAM_OUT_MODE; + +typedef enum { + TIMING_DELAY_0T = 0, + TIMING_DELAY_4T, + TIMING_DELAY_8T, + TIMING_DELAY_16T, + TIMING_DELAY_MAX, + ENUM_DUMMY4WORD(SIE_TIMING_DELAY) +} SIE_TIMING_DELAY; + +typedef enum { + SIE_LOAD_DISABLE = 0, + SIE_LOAD_FROM_SIE1, + SIE_LOAD_FROM_SIE2, + SIE_LOAD_FROM_MAX, + ENUM_DUMMY4WORD(SIE_LOAD_SRC) +} SIE_LOAD_SRC; + +typedef enum { + SIE_OUTBIT_12 = 0, ///< 12 output bits + SIE_OUTBIT_10, ///< 10 output bits + SIE_OUTBIT_8, ///< 8 output bits + SIE_OUTBIT_MAX, + ENUM_DUMMY4WORD(SIE_OUTBIT_SEL) +} SIE_OUTBIT_SEL; + +typedef enum { + SIE_PACK_AT_MSB = 0, ///< data output at MSB + SIE_PACK_AT_LSB, ///< data output at LSB + SIE_PACK_AT_MAX, + ENUM_DUMMY4WORD(SIE_PACK_FORMAT) +} SIE_PACK_FORMAT; + +typedef enum { + SIE_FMT_BAYER = 0, ///< Bayer 2x2 format + SIE_FMT_RGBIR, ///< RGB-IR 4x4 format + SIE_FMT_MAX, + ENUM_DUMMY4WORD(SIE_BAYER_FMT) +} SIE_BAYER_FMT; + +typedef enum { + ECS_BAYER_3CH_10BIT = 0, ///< Bayer 2x2 format + ECS_BAYER_4CH_8BIT, ///< RGB-IR 4x4 format + ECS_BAYER_MAX, + ENUM_DUMMY4WORD(SIE_ECS_BAYER_FMT) +} SIE_ECS_BAYER_FMT; + +typedef enum { + SIE_OB_SUB_OFS = 0, ///< ob sub use ofs + SIE_OB_SUB_OBAVG, ///< ob sub use ob avg result + SIE_OB_SUB_MAX, + ENUM_DUMMY4WORD(SIE_OB_SUB_MODE) +} SIE_OB_SUB_MODE; ///< not supported + +typedef enum { + ECS_MAPSIZE_65X65 = 0, ///< 65x65 + ECS_MAPSIZE_49X49, ///< 49x49 + ECS_MAPSIZE_33X33, ///< 33x33 + ECS_MAPSIZE_MAX, + ENUM_DUMMY4WORD(SIE_ECS_MSIZE_SEL) +} SIE_ECS_MSIZE_SEL; + +typedef enum { + STCS_HISTO_POST_GAMMA = 0, + STCS_HISTO_PRE_GAMMA, + STCS_HISTO_SRC_MAX, + ENUM_DUMMY4WORD(SIE_HISTO_SRC_SEL) +} SIE_HISTO_SRC_SEL; + +typedef enum { + STCS_CA_SRC_AFTER_IRSUB = 0, + STCS_CA_SRC_BEFORE_OB, + STCS_CA_SRC_SEL_MAX, + ENUM_DUMMY4WORD(SIE_CA_SRC_SEL) +} SIE_CA_SRC_SEL; + +typedef enum { + STCS_LA1_POST_CG = 0, ///< LA1 source from data right after color-gain + STCS_LA1_PRE_CG, ///< LA1 source from data right before color-gain + STCS_LA1_SRC_MAX, + ENUM_DUMMY4WORD(SIE_STCS_LA1_SRC_SEL) +} SIE_STCS_LA1_SRC_SEL; + +typedef enum { + STCS_LA1_RGB = 0, + STCS_LA1_G, + STCS_LA1_MAX, + ENUM_DUMMY4WORD(SIE_STCS_LA_RGB2Y1_MOD_SEL) +} SIE_STCS_LA_RGB2Y1_MOD_SEL; + +typedef enum { + STCS_LA2_RGB = 0, + STCS_LA2_G, + STCS_LA2_MAX, + ENUM_DUMMY4WORD(SIE_STCS_LA_RGB2Y2_MOD_SEL) +} SIE_STCS_LA_RGB2Y2_MOD_SEL; + +typedef enum { + DEF_FACT_50 = 0, ///< defect concealment cross-channel weighting = 50% + DEF_FACT_25, ///< defect concealment cross-channel weighting = 25%; recommanded + DEF_FACT_12, ///< defect concealment cross-channel weighting = 12.5% + DEF_FACT_06, ///< defect concealment cross-channel weighting = 6.25% + DEF_FACT_MAX, + ENUM_DUMMY4WORD(SIE_DEF_FACT_SEL) +} SIE_DEF_FACT_SEL; + +typedef enum { + GAIN_FIELD_2_8 = 0, ///< 2bits decimal, 8bits fraction + GAIN_FIELD_3_7, ///< 3bits decimal, 7bits fraction + GAIN_FIELD_MAX, + ENUM_DUMMY4WORD(SIE_GAIN_FIELD) +} SIE_GAIN_FIELD; + +typedef enum { + EV_FMT_16BIT = 0, ///< 16bit mode + EV_FMT_20BIT, ///< 20bit mode + EV_FMT_MAX, + ENUM_DUMMY4WORD(SIE_COMPANDING_EV_FMT_SEL) +} SIE_COMPANDING_EV_FMT_SEL; + +typedef enum { + DATAEXT_ORDER_EXT_SKIP = 0, + DATAEXT_ORDER_SKIP_EXT, + DATAEXT_ORDER_MAX, + ENUM_DUMMY4WORD(SIE_DATAEXT_ORDER) +} SIE_DATAEXT_ORDER; + +typedef enum { + DATAEXT_INI_OP_DROP_INI_LINE = 0, + DATAEXT_INI_OP_KEEP_INI_LINE, + DATAEXT_INI_OP_MAX, + ENUM_DUMMY4WORD(SIE_DATAEXT_INI_OP) +} SIE_DATAEXT_INI_OP; + +typedef enum { + DVI_CCIR_MODE_SD = 0, ///< SD mode (8 bits) + DVI_CCIR_MODE_HD, ///< HD mode (16bits) + DVI_CCIR_MODE_MAX, + ENUM_DUMMY4WORD(SIE_DVI_CCIR_MODE_SEL) +} SIE_DVI_CCIR_MODE_SEL; + +typedef enum { + DVI_CCIR_FMT_601 = 0, ///< CCIR 601 + DVI_CCIR_FMT_656_EAV, ///< CCIR 656 EAV code recognition + DVI_CCIR_FMT_656_ACT, ///< CCIR 656 ACT size setting (ACT_WIDTH and ACT_HEIGHT are used to determine active region size) + DVI_CCIR_FMT_MAX, + ENUM_DUMMY4WORD(SIE_DVI_CCIR_FMT_SEL) +} SIE_DVI_CCIR_FMT_SEL; + +typedef enum { + DVI_CCIR_VD_MODE_FIELD = 0,///< interlace + DVI_CCIR_VD_MODE_SAV, ///< progressive + DVI_CCIR_VD_MODE_MAX, + ENUM_DUMMY4WORD(SIE_DVI_CCIR_VD_MODE_SEL) +} SIE_DVI_CCIR_VD_MODE_SEL; + +typedef enum { + DVI_OUT_SWAP_YUYV = 0, + DVI_OUT_SWAP_YVYU, + DVI_OUT_SWAP_UYVY, + DVI_OUT_SWAP_VYUY, + DVI_OUT_SWAP_MAX, + ENUM_DUMMY4WORD(SIE_DVI_OUT_SWAP_SEL) +} SIE_DVI_OUT_SWAP_SEL; ///< output swap for DVI_IN_FMT_YUV422 + +typedef enum { + ENC_ADJ_MODE_NORMAL = 0, ///< rawenc parameters for normal mode + ENC_ADJ_MODE_AGGRESIVE, ///< rawenc parameters for aggresive mode + ENC_ADJ_MODE_MAX, + ENUM_DUMMY4WORD(SIE_RAWENC_ADJ_MODE_SEL) +} SIE_RAWENC_ADJ_MODE_SEL; + +typedef enum { + ENC_RATE_50 = 0, + ENC_RATE_58, + ENC_RATE_66, ///< not supported + ENC_RATE_41, ///< not supported + ENC_RATE_MAX, + ENUM_DUMMY4WORD(SIE_RAWENC_RATE_SEL) +} SIE_RAWENC_RATE_SEL; + +typedef enum { + ENC_SHARE_NONE = 0, + ENC_SHARE_SHARED, + ENC_SHARE_MAX, + ENUM_DUMMY4WORD(SIE_RAWENC_SHARE_SEL) +} SIE_RAWENC_SHARE_SEL; + +typedef enum { + ENC_FRM_RST_ID_0 = 0, + ENC_FRM_RST_ID_1, + ENC_FRM_RST_ID_MAX, + ENUM_DUMMY4WORD(SIE_RAWENC_FRM_RST_ID_SEL) +} SIE_RAWENC_FRM_RST_ID_SEL; ///< only supported for SIE1 + +typedef struct { + UINT8 tbl_idx[8]; ///< Raw encoder - Quality DCT Table + UINT8 lvl_thres[4]; ///< Raw encoder - Quality DCT Level Threshold +} SIE_RAWENC_DCT_PARAM; + +typedef struct { + SIE_RAWENC_ADJ_MODE_SEL adj_mode; ///< Raw encoder - Table parameter adjust mode + SIE_RAWENC_RATE_SEL rate; ///< Raw encoder - Target rate of encoded bitstream per segment + BOOL gamma_en; ///< Raw encoder - Gamma + SIE_RAWENC_DCT_PARAM dct; ///< Raw encoder - DCT Param +} SIE_RAWENC_PARAM; + +typedef struct { + SIE_PHASE_SEL vd_phase; ///< VD phase + SIE_PHASE_SEL hd_phase; ///< HD phase + SIE_PHASE_SEL data_phase; ///< Data phase + BOOL vd_inv; ///< VD Invert + BOOL hd_inv; ///< HD Invert + SIE_PARAL_RAW_BITDEPTH raw_bitdepsel; +} SIE_PARAL_SIGNAL_PARAM; + +typedef struct { + SIE_PATGEN_MODE patgen_mode; + UINT32 patgen_val; +} SIE_PATGEN_PARAM; + +typedef struct { + UINT32 sz_x; ///< horizontal size + UINT32 sz_y; ///< vertical size +} SIE_SRC_WIN_PARAM; + +typedef struct { + UINT16 st_x; ///< horizontal start + UINT16 st_y; ///< vertical start + UINT32 sz_x; ///< horizontal size + UINT32 sz_y; ///< vertical size + SIE_CFAPAT_SEL cfa_pat; ///< CFA start pattern +} SIE_ACT_WIN_PARAM; + +typedef struct { + UINT16 st_x; ///< horizontal start + UINT16 st_y; ///< vertical start + UINT32 sz_x; ///< horizontal size + UINT32 sz_y; ///< vertical size + SIE_CFAPAT_SEL cfa_pat; ///< CFA start pattern +} SIE_CRP_WIN_PARAM; + +typedef struct { + SIE_TIMING_DELAY vd_delay; + SIE_TIMING_DELAY hd_delay; +} SIE_VDHD_DELAY_PARAM; + +typedef enum { + DRAM_BURST_LEN_64 = 0, + DRAM_BURST_LEN_48, + DRAM_BURST_LEN_32, + DRAM_BURST_LEN_16, + DRAM_BURST_LEN_MAX, + ENUM_DUMMY4WORD(SIE_DRAM_BURST_LEN_SEL) +} SIE_DRAM_BURST_LEN_SEL; + +typedef enum { + DRAM_OUT0_BURST_LEN_128 = 0, + DRAM_OUT0_BURST_LEN_96, + DRAM_OUT0_BURST_LEN_64, + DRAM_OUT0_BURST_LEN_32, + DRAM_OUT0_BURST_LEN_MAX, + ENUM_DUMMY4WORD(SIE_DRAM_OUT0_BURST_LEN_SEL) +} SIE_DRAM_OUT0_BURST_LEN_SEL; + +typedef enum { + DRAM_OUT2_BURST_LEN_32 = 0, + DRAM_OUT2_BURST_LEN_16, + DRAM_OUT2_BURST_LEN_MAX, + ENUM_DUMMY4WORD(SIE_DRAM_OUT2_BURST_LEN_SEL) +} SIE_DRAM_OUT2_BURST_LEN_SEL; + +typedef struct { + SIE_DRAM_OUT0_BURST_LEN_SEL out0; + SIE_DRAM_BURST_LEN_SEL out1; + SIE_DRAM_OUT2_BURST_LEN_SEL out2; + SIE_DRAM_BURST_LEN_SEL in1; + SIE_DRAM_BURST_LEN_SEL in2; +} SIE_DRAM_BURST_LEN_PARAM; + +typedef struct { + UINT32 addr_pa; +} SIE_DRAM_ADDR; + +typedef struct { + UINT32 lofs; ///< line-offset + SIE_DATA_PACKBUS_SEL pack_bus; ///< pack bus bit number +} SIE_DRAM_IN1_PARAM; + +typedef struct { + UINT32 lofs; ///< line-offset + SIE_DATA_PACKBUS_SEL pack_bus; ///< pack bus bit number + BOOL hflip; ///< mirror + BOOL vflip; ///< flip + BOOL ringbuf_en; + UINT16 ringbuf_len; + SIE_OUTBIT_SEL out_bitdepth; + SIE_PACK_FORMAT pack_fmt; +} SIE_DRAM_OUT0_PARAM; + +typedef struct { + UINT32 lofs; ///< line-offset + BOOL vflip; ///< H flip + BOOL hflip; ///< V flip +} SIE_DRAM_OUT1_PARAM; + +typedef struct { + UINT8 pos_code; ///< positive code value + UINT8 neg_code; ///< negative code value + UINT8 nochg_code; ///< no changed code value +} SIE_DVS_CODE_PARAM; + +typedef struct { + UINT32 sz_x; + UINT32 sz_y; +} SIE_DVS_WIN_PARAM; + +typedef struct { + UINT32 mot_out_sz; ///< must > 0 and align 4 +} SIE_EVS_OUT_PARAM; + +typedef struct { + UINT16 r_gain; ///< Color Gain, R Gain + UINT16 gr_gain; ///< Color Gain, Gr Gain + UINT16 gb_gain; ///< Color Gain, Gb Gain + UINT16 b_gain; ///< Color Gain, B Gain + UINT16 ir_gain; ///< Color Gain, B Gain + SIE_GAIN_FIELD gain_sel; ///< gain filed selection +} SIE_CGAIN_PARAM; + +typedef struct { + UINT32 gain_8p8bit; ///< digital gain in 8.8 bits format +} SIE_DGAIN_PARAM; + +typedef struct { + UINT16 decomp_kp[11]; ///< 0 ~ 0xfff + UINT16 decomp_sp[12]; ///< 0 ~ 0xfff + UINT8 decomp_sb[12]; ///< 0 ~ 0xf +} SIE_DECOMPANDING_PARAM; + +typedef struct { + UINT8 comp_kp[11]; ///< 0 ~ 0x1f + UINT16 comp_sp[12]; ///< 0 ~ 0xfff + UINT8 comp_sb[12]; ///< 0 ~ 0xf +} SIE_COMPANDING_PARAM; + +typedef struct { + UINT16 ofs; +} SIE_OB_OFS_PARAM; + +typedef struct { + BOOL dither_en; ///< dithering enable + BOOL dither_rst; ///< dithering reset + UINT32 dither_lvl; ///< dithering level; 0x0=bit[1:0], 0x7=bit[8:7] + SIE_ECS_MSIZE_SEL map_size_sel; ///< ecs table size + UINT32 map_shift; ///< multiplication shift bit number +} SIE_ECS_PARAM; + +typedef struct { + UINT32 hscl_fctr; ///< map horizontal scaling factor + UINT32 vscl_fctr; ///< map vertical scaling factor +} SIE_ECS_SCAL_PARAM; + +typedef struct { + SIE_DEF_FACT_SEL fact; + SIE_CFAPAT_SEL cfa_pat; +} SIE_DPC_PARAM; + +typedef struct { + SIE_DATAEXT_ORDER ext_order; + SIE_DATAEXT_INI_OP ini_line_op; + UINT8 ext_data_skip; + UINT8 ext_data_len; + UINT16 ini_line_len; +} SIE_DATAEXT_PARAM; + +typedef struct { + BOOL src_intpV; ///< vertical interpolation, only for input width<=8188 or 5504 + UINT32 iv; ///< bayer scaling - integration value + UINT32 sv; ///< bayer scaling - skipping value + UINT32 bvR; ///< bayer scaling - begin value for R/Gb channel + UINT32 bvB; ///< bayer scaling - begin value for B/Gr channel + UINT32 out_sz; ///< bayer scaling - output size + UINT32 divM[2]; ///< bayer scaling - division parameter M + UINT32 divS[2]; ///< bayer scaling - division parameter S +} SIE_BS_H_PARAM; + +typedef struct { + UINT32 iv; ///< bayer scaling - integration value + UINT32 sv; ///< bayer scaling - skipping value + UINT32 bvR; ///< bayer scaling - begin value for R/Gb channel + UINT32 bvB; ///< bayer scaling - begin value for B/Gr channel + UINT32 out_sz; ///< bayer scaling - output size + UINT32 divM[2]; ///< bayer scaling - division parameter M + UINT32 divS[2]; ///< bayer scaling - division parameter S + UINT32 in_shift; ///< bayer scaling - input shift + UINT32 divMRb[16]; ///< bayer scaling - division parameter M for R/B + UINT32 divSRb[16]; ///< bayer scaling - division parameter S for R/B +} SIE_BS_V_PARAM; + +typedef struct { + UINT32 in_sz_x; ///< input horizontal size + UINT32 in_sz_y; ///< input vertical size + UINT32 out_sz_x; ///< output horizontal size + UINT32 out_sz_y; ///< output vertical size + UINT32 lpf; ///< low-pass valumn, 0~100, (suggestion: 50) + UINT32 bin_pwr; ///< binning, 0~2, (suggestion: 0) + BOOL adaptivelpf_en; ///< 0: LPF is absolute value; 1: LPF is adaptive value (suggestion: 1) +} SIE_BS_PARAM; + +typedef struct { + BOOL la_cg_en; + BOOL la_gamma_en; + BOOL la_th_en; ///< not supported + BOOL ca_th_en; + UINT16 companding_shift; ///< must setup when companding enable and roi_acc or ca/la enable + SIE_HISTO_SRC_SEL histo_src_sel; + SIE_STCS_LA1_SRC_SEL la1_src_sel; + SIE_STCS_LA_RGB2Y1_MOD_SEL la_rgb2y1_mod; + SIE_STCS_LA_RGB2Y2_MOD_SEL la_rgb2y2_mod; + SIE_CA_SRC_SEL ca_accm_src; +} SIE_STCS_PATH_PARAM; + +typedef struct { + SIE_CFAPAT_SEL ca_cfa_pat; + UINT32 ca_roi_stx; + UINT32 ca_roi_sty; + UINT32 ca_roi_szx; + UINT32 ca_roi_szy; + UINT32 ca_win_numx; + UINT32 ca_win_numy; + UINT32 la_roi_stx; + UINT32 la_roi_sty; + UINT32 la_roi_szx; + UINT32 la_roi_szy; + UINT32 la_win_numx; + UINT32 la_win_numy; +} SIE_STCS_CALASIZE_INFO; + +typedef struct { + UINT16 ca_ob_ofs; ///< OB ofs for CA + UINT16 la_ob_ofs; ///< OB ofs for LA +} SIE_STCS_OB_PARAM; + +typedef struct { + UINT32 fctr_x; ///< horizontal scaling factor + UINT32 fctr_y; ///< vertical scaling factor +} SIE_CA_SCALE_PARAM; + +typedef struct { + UINT32 ca_irsub_rwet; ///< IR weight for subtraction, R channel + UINT32 ca_irsub_gwet; ///< IR weight for subtraction, G channel + UINT32 ca_irsub_bwet; ///< IR weight for subtraction, B channel +} SIE_CA_IRSUB_PARAM; + +typedef struct { + UINT32 la_irsub_rwet; ///< IR weight for subtraction, R channel + UINT32 la_irsub_gwet; ///< IR weight for subtraction, G channel + UINT32 la_irsub_bwet; ///< IR weight for subtraction, B channel +} SIE_LA_IRSUB_PARAM; + +typedef struct { + UINT32 st_x; ///< horizontal start + UINT32 st_y; ///< vertical start + UINT32 sz_x; ///< horizontal size + UINT32 sz_y; ///< vertical size + SIE_CFAPAT_SEL cfa_pat; ///< CFA start pattern +} SIE_CA_CROP_PARAM; + +typedef struct { + UINT32 st_x; ///< horizontal start + UINT32 st_y; ///< vertical start + UINT32 sz_x; ///< horizontal size + UINT32 sz_y; ///< vertical size +} SIE_LA_CROP_PARAM; + +typedef struct { + UINT32 win_numx; ///< color accumulation - horizontal window number + UINT32 win_numy; ///< color accumulation - vertical window number + UINT32 win_szx; ///< color accumulation - horizontal window size + UINT32 win_szy; ///< color accumulation - vertical window size +} SIE_CA_WIN_PARAM; + +typedef struct { + UINT32 win_numx; ///< color accumulation - horizontal window number + UINT32 win_numy; ///< color accumulation - vertical window number + UINT32 win_szx; ///< color accumulation - horizontal window size + UINT32 win_szy; ///< color accumulation - vertical window size +} SIE_LA_WIN_PARAM; + +typedef struct { + UINT16 r_gain; ///< R Gain + UINT16 g_gain; ///< G Gain + UINT16 b_gain; ///< B Gain +} SIE_LA_CG_PARAM; + +typedef struct { + UINT16 *buf_la1; + UINT16 *buf_la2; +} SIE_LA_RSLT; + +typedef struct { + UINT16 *buf_r; + UINT16 *buf_g; + UINT16 *buf_b; + UINT16 *buf_ir; + UINT16 *acc_cnt; +} SIE_CA_RSLT; + +typedef struct { + UINT16 g_th_lower; + UINT16 g_th_upper; + UINT16 rg_th_lower; + UINT16 rg_th_upper; + UINT16 bg_th_lower; + UINT16 bg_th_upper; + UINT16 pg_th_lower; + UINT16 pg_th_upper; +} SIE_CA_TH_PARAM; + +typedef struct { + SIE_CA_WIN_PARAM ca_win; + SIE_STCS_OB_PARAM stcs_ob; + SIE_CGAIN_PARAM cgain; + SIE_BAYER_FMT bayer_fmt; +} SIE_CA_RSLT_PARAMS; + +typedef struct { + UINT16 *buf_hist; +} SIE_HIST_RSLT; + +typedef struct { + SIE_DVI_CCIR_MODE_SEL mode; ///< SD(8bits)/HD(16bits) + SIE_DVI_CCIR_FMT_SEL fmt; ///< CCIR601/CCIR656 + SIE_DVI_CCIR_VD_MODE_SEL vd_mode; ///< 0:interlace 1:progressive + BOOL id_auto_align; ///< demux channel data base on CHID in EAV/SAV, 0:disable 1:enable + BOOL field_enb; ///< check field_sel and output corresponding frame + BOOL field_sel; ///< 0:receive data when field=0, 1:receive data when field=1 + BOOL hd_in_swap; ///< byte swap control when in HD(16bit) mode + + UINT8 data_period; ///< receive data period used with data_idx + UINT8 data_idx; ///< index of selected pixel, as target channel id if enable ccir_id_auto_align +} SIE_DVI_CCIR_PARAM; + +typedef struct { + SIE_DVI_OUT_SWAP_SEL out_swap; ///< swap control for DVI_IN_FMT_YUV422 + BOOL out_split; ///< must enable when DVI_IN_FMT_YUV420 or out_yuv420_en = 1 + BOOL out_yuv420_en; ///< YUV422 to YUV420 control for DVI_IN_FMT_YUV422 + + SIE_DVI_CCIR_PARAM ccir; ///< ccir receive parameter +} SIE_DVI_PARAM; + +/************************************************************************************* + * Public Set Function Prototype [Direct apply] + *************************************************************************************/ +int sie_eng_set_soft_reset_hw_reg(void *handle, BOOL enb); +int sie_eng_set_checksum_en_hw_reg(void *handle, BOOL enb); +int sie_eng_set_interrupt_enable_hw_reg(void *handle, UINT32 int_en); +int sie_eng_set_load_hw_reg(void *handle); +int sie_eng_set_dramin_start_hw_reg(void *handle); +int sie_eng_set_main_input_hw_reg(void *handle, SIE_MAIN_INPUT_SEL mainInInfo); +int sie_eng_set_vdhd_delay_hw_reg(void *handle, SIE_VDHD_DELAY_PARAM *p_dly_info); +int sie_eng_set_global_load_src_hw_reg(void *handle, SIE_LOAD_SRC src); +int sie_eng_set_parallel_sig_hw_reg(void *handle, SIE_PARAL_SIGNAL_PARAM *p_paral_info); +int sie_eng_set_dvs_code_hw_reg(void *handle, SIE_DVS_CODE_PARAM *p_dvs); +int sie_eng_set_ccir_header_check_hw_reg(void *handle, UINT32 header); + +int sie_eng_set_companding_hw_reg(void *handle, SIE_COMPANDING_PARAM *p_companding); +int sie_eng_set_decompanding_hw_reg(void *handle, SIE_DECOMPANDING_PARAM *p_decompanding); + +int sie_eng_set_la_gamma_hw_reg(void *handle, UINT16 *p_gam_tbl); + +int sie_eng_set_rawenc_share_sel_hw_reg(void *handle, SIE_RAWENC_SHARE_SEL share); +int sie_eng_set_rawenc_frm_rst_id_hw_reg(void *handle, SIE_RAWENC_FRM_RST_ID_SEL frm_rst_id); + +int sie_eng_set_dma_ch_disable_hw_reg(void *handle, BOOL disable); +int sie_eng_set_tcm_wait_b_resp_enb_hw_reg(void *handle, BOOL enb); + +/************************************************************************************* + * Public Set Function Prototype [VD latched] + *************************************************************************************/ +int sie_eng_set_ipp_ctrl_buf_reg(void *handle, BOOL direct2ipp_en); +int sie_eng_set_ydcc_direct_buf_reg(void *handle, BOOL enb); +int sie_eng_set_function_enable_buf_reg(void *handle, UINT32 func_en); +int sie_eng_set_single_function_enable_buf_reg(void *handle, SIE_FUNCTION_SEL func_item, BOOL enb); +int sie_eng_set_bayer_fmt_buf_reg(void *handle, SIE_BAYER_FMT fmt); +int sie_eng_set_ecs_mode_buf_reg(void *handle, SIE_ECS_BAYER_FMT mode); +int sie_eng_set_dvi_buf_reg(void *handle, SIE_DVI_PARAM *p_dvi); +int sie_eng_set_patgen_buf_reg(void *handle, SIE_PATGEN_PARAM *p_param); + +int sie_eng_set_rawenc_rate_buf_reg(void *handle, SIE_RAWENC_RATE_SEL rate); +int sie_eng_set_rawenc_gamma_en_buf_reg(void *handle, BOOL enb); +int sie_eng_set_rawenc_dct_buf_reg(void *handle, SIE_RAWENC_DCT_PARAM *p_dct); +int sie_eng_set_rawenc_param_buf_reg(void *handle, SIE_RAWENC_ADJ_MODE_SEL mode, SIE_RAWENC_RATE_SEL rate); + +int sie_eng_set_src_win_buf_reg(void *handle, SIE_SRC_WIN_PARAM *p_src_win); +int sie_eng_set_act_win_buf_reg(void *handle, SIE_ACT_WIN_PARAM *p_act_win); +int sie_eng_set_crop_win_buf_reg(void *handle, SIE_CRP_WIN_PARAM *p_crp_win); + +int sie_eng_set_bp1_buf_reg(void *handle, UINT32 bp); +int sie_eng_set_bp2_buf_reg(void *handle, UINT32 bp); +int sie_eng_set_bp3_buf_reg(void *handle, UINT32 bp); + +int sie_eng_set_cgain_buf_reg(void *handle, SIE_CGAIN_PARAM *p_cgain); +int sie_eng_set_dgain_buf_reg(void *handle, SIE_DGAIN_PARAM *p_dgain); + +int sie_eng_set_ecs_buf_reg(void *handle, SIE_ECS_PARAM *p_ecs, SIE_ACT_WIN_PARAM *p_actwin); +int sie_eng_set_ecs_scale_buf_reg(void *handle, SIE_ECS_SCAL_PARAM *p_ecs_scal); + +int sie_eng_set_dpc_buf_reg(void *handle, SIE_DPC_PARAM *p_dpc); + +int sie_eng_set_ob_ofs_buf_reg(void *handle, SIE_OB_OFS_PARAM *p_ob_ofs); + +int sie_eng_set_dataext_buf_reg(void *handle, SIE_DATAEXT_PARAM *p_dataext); + +int sie_eng_set_bs_buf_reg(void *handle, SIE_BS_PARAM *p_bs); +int sie_eng_set_bsh_buf_reg(void *handle, SIE_BS_H_PARAM *p_bsh); +int sie_eng_set_bsv_buf_reg(void *handle, SIE_BS_V_PARAM *p_bsv); + +int sie_eng_set_stcs_path_buf_reg(void *handle, SIE_STCS_PATH_PARAM *p_stcs_path); +int sie_eng_set_stcs_ob_buf_reg(void *handle, SIE_STCS_OB_PARAM *p_stcs_ob); + +int sie_eng_set_ca_crop_buf_reg(void *handle, SIE_CA_CROP_PARAM *p_ca_crop); +int sie_eng_set_ca_scale_buf_reg(void *handle, SIE_CA_SCALE_PARAM *p_ca_scal); +int sie_eng_set_ca_win_buf_reg(void *handle, SIE_CA_WIN_PARAM *p_la_win); +int sie_eng_set_ca_th_buf_reg(void *handle, SIE_CA_TH_PARAM *p_ca_th); +int sie_eng_set_ca_irsub_buf_reg(void *handle, SIE_CA_IRSUB_PARAM *p_ca_irsub); + +int sie_eng_set_la_crop_buf_reg(void *handle, SIE_LA_CROP_PARAM *p_la_crop); +int sie_eng_set_la_win_buf_reg(void *handle, SIE_LA_WIN_PARAM *p_la_win); +int sie_eng_set_la_irsub_buf_reg(void *handle, SIE_LA_IRSUB_PARAM *p_la_irsub); +int sie_eng_set_la_cg_buf_reg(void *handle, SIE_LA_CG_PARAM *p_la_cg); + +int sie_eng_set_cala_size_buf_reg(void *handle, SIE_STCS_CALASIZE_INFO *p_sz_info, SIE_LA_WIN_PARAM *p_win_param); + +int sie_eng_set_dvs_win_buf_reg(void *handle, SIE_DVS_WIN_PARAM *p_dvs_win); +int sie_eng_set_evs_out_buf_reg(void *handle, SIE_EVS_OUT_PARAM *p_evs_out); + +int sie_eng_set_dramin1_addr_buf_reg(void *handle, SIE_DRAM_ADDR *p_in1); +int sie_eng_set_dramin2_addr_buf_reg(void *handle, SIE_DRAM_ADDR *p_in2); +int sie_eng_set_dramout0_addr_buf_reg(void *handle, SIE_DRAM_ADDR *p_dout0); +int sie_eng_set_dramout1_addr_buf_reg(void *handle, SIE_DRAM_ADDR *p_dout1); +int sie_eng_set_dramout2_addr_buf_reg(void *handle, SIE_DRAM_ADDR *p_dout2); + +int sie_eng_set_dramin1_buf_reg(void *handle, SIE_DRAM_IN1_PARAM *p_din1); +int sie_eng_set_dramout0_buf_reg(void *handle, SIE_DRAM_OUT0_PARAM *p_dout0); +int sie_eng_set_dramout1_buf_reg(void *handle, SIE_DRAM_OUT1_PARAM *p_dout1); + +int sie_eng_set_dramout0_singleout_mode_buf_reg(void *handle, SIE_DRAM_OUT_MODE mode); +int sie_eng_set_dramout1_singleout_mode_buf_reg(void *handle, SIE_DRAM_OUT_MODE mode); +int sie_eng_set_dramout2_singleout_mode_buf_reg(void *handle, SIE_DRAM_OUT_MODE mode); + +int sie_eng_set_dramout0_singleout_en_buf_reg(void *handle, BOOL enb); +int sie_eng_set_dramout1_singleout_en_buf_reg(void *handle, BOOL enb); +int sie_eng_set_dramout2_singleout_en_buf_reg(void *handle, BOOL enb); + +int sie_eng_set_dram_burst_len_buf_reg(void *handle, SIE_DRAM_BURST_LEN_PARAM *p_burst_len); + +/************************************************************************************* + * Public Get Function Prototype + *************************************************************************************/ +int sie_eng_get_dramout0_singleout_en_buf_reg(void *handle, BOOL *enb); +int sie_eng_get_dramout1_singleout_en_buf_reg(void *handle, BOOL *enb); +int sie_eng_get_dramout2_singleout_en_buf_reg(void *handle, BOOL *enb); +int sie_eng_get_dramout3_singleout_en_buf_reg(void *handle, BOOL *enb); + +int sie_eng_get_dramin1_buf_reg(void *handle, SIE_DRAM_IN1_PARAM *p_din1); +int sie_eng_get_dramout0_buf_reg(void *handle, SIE_DRAM_OUT0_PARAM *p_dout0); +int sie_eng_get_dramout1_buf_reg(void *handle, SIE_DRAM_OUT1_PARAM *p_dout1); + +int sie_eng_get_bayer_fmt_buf_reg(void *handle, SIE_BAYER_FMT *p_fmt); + +int sie_eng_get_cgain_buf_reg(void *handle, SIE_CGAIN_PARAM *p_cgain); +int sie_eng_get_dgain_buf_reg(void *handle, SIE_DGAIN_PARAM *p_dgain); + +int sie_eng_get_ca_rslt(void *handle, UINT32 addr_va, SIE_CA_RSLT *p_ca_rslt, SIE_CA_RSLT_PARAMS *p_ca_rslt_info); +int sie_eng_get_la_rslt(void *handle, UINT32 addr_va, SIE_LA_RSLT *p_la_rslt, SIE_LA_WIN_PARAM *p_la_win); +int sie_eng_get_hist(void *handle, SIE_HIST_RSLT *p_hist_rslt); + +int sie_eng_get_function_enable_buf_reg(void *handle, UINT32 *func_en); +int sie_eng_get_crop_win_buf_reg(void *handle, SIE_CRP_WIN_PARAM *p_crp_win); +int sie_eng_get_dvi_buf_reg(void *handle, SIE_DVI_PARAM *p_dvi); +int sie_eng_get_ccir_header_status_hw_reg(void *handle, UINT32 *status); + +int sie_eng_get_bsh_buf_reg(void *handle, SIE_BS_H_PARAM *p_bsh); +int sie_eng_get_bsv_buf_reg(void *handle, SIE_BS_V_PARAM *p_bsv); + +int sie_eng_get_stcs_path_buf_reg(void *handle, SIE_STCS_PATH_PARAM *p_stcs_path); +int sie_eng_get_stcs_ob_buf_reg(void *handle, SIE_STCS_OB_PARAM *p_stcs_ob); + +int sie_eng_get_ca_crop_buf_reg(void *handle, SIE_CA_CROP_PARAM *p_ca_crop); +int sie_eng_get_la_crop_buf_reg(void *handle, SIE_LA_CROP_PARAM *p_la_crop); +int sie_eng_get_ca_win_buf_reg(void *handle, SIE_CA_WIN_PARAM *p_ca_win); +int sie_eng_get_la_win_buf_reg(void *handle, SIE_LA_WIN_PARAM *p_la_win); + +int sie_eng_get_evs_total_cnt_hw_reg(void *handle, UINT32 *p_cnt); + +int sie_eng_get_ir_level(void *handle, UINT32 *level); +int sie_eng_calc_ir_level(void *handle, SIE_CA_RSLT *ca_rst, SIE_CA_WIN_PARAM *p_ca_win, SIE_CA_IRSUB_PARAM *p_ca_ir_sub); + +#endif /* _SIE_BASE_H_ */ diff --git a/board/novatek/ns02501/loader/Include/Driver/sie_eng.h b/board/novatek/ns02501/loader/Include/Driver/sie_eng.h new file mode 100755 index 000000000000..0e563e79a5af --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/sie_eng.h @@ -0,0 +1,106 @@ +/* + Public header file for SIE module. + + Copyright Novatek Microelectronics Corp. 2023. All rights reserved. +*/ +#ifndef _SIE_ENG_H_ +#define _SIE_ENG_H_ + +#include "sie_base.h" + +/************************************************************************************* + * SIE Driver Version Definition + *************************************************************************************/ +#define SIE_DRV_VERSION "0.01.01" + +/************************************************************************************* + * SIE Engine Index Definition + *************************************************************************************/ +typedef enum { + SIE_ENG_ID_1 = 0, ///< SIE1 + SIE_ENG_ID_2, ///< SIE2 + SIE_ENG_ID_3, ///< SIE3 + SIE_ENG_ID_MAX +} SIE_ENG_ID_T; + +/************************************************************************************* + * SIE Engine Clock Source Definition + *************************************************************************************/ +typedef enum { + SIE_ENG_CLKSRC_480 = 0, + SIE_ENG_CLKSRC_RSVD1, + SIE_ENG_CLKSRC_PLL5, + SIE_ENG_CLKSRC_RSVD3, + SIE_ENG_CLKSRC_PLL12, + SIE_ENG_CLKSRC_320, + SIE_ENG_CLKSRC_192, + SIE_ENG_CLKSRC_RSVD7, + SIE_ENG_CLKSRC_MAX +} SIE_ENG_CLKSRC; + +/************************************************************************************* + * SIE Internal Clock Source Definition + *************************************************************************************/ +typedef enum { + SIE_ENG_INTCLKSRC_SIE1 = 0, ///< engine clock from SIE1_CLK, available for SIE2 + SIE_ENG_INTCLKSRC_SIE2, + SIE_ENG_INTCLKSRC_SIE3, + SIE_ENG_INTCLKSRC_MAX +} SIE_ENG_INTCLKSRC; + +/************************************************************************************* + * SIE Interrupt Definition + *************************************************************************************/ +#define SIE_INT_VD 0x00000001 +#define SIE_INT_BP1 0x00000002 +#define SIE_INT_BP2 0x00000004 +#define SIE_INT_BP3 0x00000008 +#define SIE_INT_ACTST 0x00000010 +#define SIE_INT_CRPST 0x00000020 +#define SIE_INT_DRAM_IN_OUT_ERR 0x00000040 +#define SIE_INT_DRAM_OUT0_END 0x00000080 +#define SIE_INT_DRAM_OUT1_END 0x00000100 +#define SIE_INT_DRAM_OUT2_END 0x00000200 +#define SIE_INT_DPCF 0x00002000 +#define SIE_INT_SIECLK_ERR 0x00004000 +#define SIE_INT_RAWENC_OVFL 0x00008000 +#define SIE_INT_ACTEND 0x00010000 +#define SIE_INT_CROPEND 0x00020000 +#define SIE_INT_BEHAVIOR_ERR 0x00040000 +#define SIE_INT_HISTO_END 0x00100000 +#define SIE_INT_RAWENC_DATA_OVLAP 0x00800000 ///< BCC share and process data overlap +#define SIE_INT_CCIR656_HEADER_HIT 0x01000000 +#define SIE_INT_ALL 0x0197e3ff + +/************************************************************************************* + * SIE Common Definition + *************************************************************************************/ +typedef struct { + SIE_ENG_CLKSRC clk_src; ///< engine operation clock source + UINT32 clk_rate; ///< engine operation clock rate(Hz) + SIE_ENG_INTCLKSRC int_clk_src; ///< engine internal clock source for bcc share used +} SIE_INIT_CFG; + +typedef struct { + BOOL act_en; +} SIE_START_CFG; + +/************************************************************************************* + * SIE Public Function Prototype + *************************************************************************************/ +void *sie_eng_get_handle(UINT32 id); +int sie_eng_open(UINT32 id, SIE_INIT_CFG *init_cfg); +int sie_eng_close(UINT32 id); +int sie_eng_trig_hw_reg(void *handle, SIE_START_CFG *trig_cfg); +int sie_eng_stop_hw_reg(void *handle); +int sie_eng_set_clock(void *handle, SIE_ENG_CLKSRC clk_src, UINT32 clk_rate); +int sie_eng_set_intclock(void *handle, SIE_ENG_INTCLKSRC clk_src); + +int sie_eng_write_hw_reg(void *handle, UINT32 reg_ofs, UINT32 val); +UINT32 sie_eng_read_hw_reg(void *handle, UINT32 reg_ofs); + +int sie_eng_patgen_simple_test(UINT32 id, UINT32 out0_enb, UINT32 ydcc_direct); +int sie_eng_dramin_simple_test(UINT32 id, UINT32 out0_enb, UINT32 ydcc_direct); + +#endif /* _SIE_ENG_H_ */ + diff --git a/board/novatek/ns02501/loader/Include/Driver/sie_limit.h b/board/novatek/ns02501/loader/Include/Driver/sie_limit.h new file mode 100755 index 000000000000..d5e940fb239a --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Driver/sie_limit.h @@ -0,0 +1,211 @@ +/* + Public header file for SIE module. + + Copyright Novatek Microelectronics Corp. 2023. All rights reserved. +*/ +#ifndef _SIE_LIMIT_H_ +#define _SIE_LIMIT_H_ + +/*********************************************************************************************** + * SIE Master Clock Max Frequency Definition + ***********************************************************************************************/ +#define SIE1_MAX_CLK_FREQ 320000000 ///< 320MHz, 2-pixel base, BCC_2P +#define SIE2_MAX_CLK_FREQ 320000000 ///< 320MHz, 2-pixel base, BCC_SIE1(Shared) +#define SIE3_MAX_CLK_FREQ 320000000 ///< 320MHz, 2-pixel base + +/*********************************************************************************************** + * SIE Global Hardware Limitation Definition + ***********************************************************************************************/ +#define SIE_MAX_ENG_NUM 3 ///< SIE1~3 + +#define SIE_MAX_OUTPUT_NUM 3 ///< OUT0:IMG, OUT1:CA/UV, OUT2:LA +#define SIE_MAX_INPUT_NUM 2 ///< IN1 :DPC/IMG, IN2 :ECS + +#define SIE_CA_MAX_WIN_NUM 32 +#define SIE_LA_MAX_WIN_NUM 32 +#define SIE_LA_HISTO_BIN_NUM 64 + +#define SIE_PATGEN_SRC_WIN_W_ALIGN 2 +#define SIE_PATGEN_SRC_WIN_H_ALIGN 2 +#define SIE_PATGEN_SRC_WIN_MIN_W 16 +#define SIE_PATGEN_SRC_WIN_MIN_H 16 +#define SIE_PATGEN_SRC_WIN_MAX_W 16382 +#define SIE_PATGEN_SRC_WIN_MAX_H 16382 + +#define SIE_ACT_ECS_WIN_MIN_W 256 ///< for ECS table size 65x65 +#define SIE_ACT_ECS_WIN_MIN_H 256 ///< for ECS table size 65x65 + +#define SIE_ACT_WIN_W_ALIGN 2 +#define SIE_ACT_WIN_H_ALIGN 2 +#define SIE_ACT_WIN_X_ALIGN 1 +#define SIE_ACT_WIN_Y_ALIGN 1 +#define SIE_ACT_WIN_MAX_X 16383 +#define SIE_ACT_WIN_MAX_Y 16383 +#define SIE_ACT_WIN_MIN_W 16 +#define SIE_ACT_WIN_MIN_H 2 +#define SIE_ACT_WIN_MAX_W 16382 +#define SIE_ACT_WIN_MAX_H 16382 + +#define SIE_CROP_WIN_W_ALIGN 2 +#define SIE_CROP_WIN_H_ALIGN 2 +#define SIE_CROP_WIN_X_ALIGN 1 +#define SIE_CROP_WIN_Y_ALIGN 1 +#define SIE_CROP_WIN_MAX_X 16383 +#define SIE_CROP_WIN_MAX_Y 16383 +#define SIE_CROP_WIN_MIN_W 16 +#define SIE_CROP_WIN_MIN_H 2 +#define SIE_CROP_WIN_MAX_W 16382 +#define SIE_CROP_WIN_MAX_H 16382 + +#define SIE_CROP_BS_WIN_H_ALIGN 2 ///< reserve for backward compatiable, will be remove +#define SIE_CROP_BS_IN_WIN_W_ALIGN 2 ///< when bayer-scaling horizontial on, crop width should be 2x +#define SIE_CROP_BS_IN_WIN_H_ALIGN 2 ///< when bayer-scaling vertical on, crop height should be 2x + +#define SIE_CROP_WIN_MAX_W_8BIT SIE_CROP_WIN_MAX_W +#define SIE_CROP_WIN_MAX_W_10BIT SIE_CROP_WIN_MAX_W +#define SIE_CROP_WIN_MAX_W_12BIT SIE_CROP_WIN_MAX_W +#define SIE_CROP_WIN_MAX_W_16BIT SIE_CROP_WIN_MAX_W + +#define SIE_ACT_DATAEXT_SKIPLEN_MIN 1 +#define SIE_ACT_DATAEXT_LEN_MIN 1 +#define SIE_ACT_DATAEXT_INILEN_MIN 0 +#define SIE_ACT_DATAEXT_SKIPLEN_MAX 255 +#define SIE_ACT_DATAEXT_LEN_MAX 255 +#define SIE_ACT_DATAEXT_INILEN_MAX 4095 + +#define SIE_SCALE_WIN_W_ALIGN 2 +#define SIE_SCALE_WIN_H_ALIGN 2 +#define SIE_SCALE_INPUT_WIN_MAX_W 4096 +#define SIE_SCALE_INPUT_WIN_MAX_H 16382 +#define SIE_SCALE_OUTPUT_WIN_MAX_W 2880 +#define SIE_SCALE_OUTPUT_WIN_MAX_H 8190 +#define SIE_SCALE_W_RATIO 8 +#define SIE_SCALE_H_RATIO 8 + +#define SIE_CA_CROP_WIN_W_ALIGN 2 +#define SIE_CA_CROP_WIN_H_ALIGN 2 +#define SIE_CA_CROP_WIN_X_ALIGN 1 +#define SIE_CA_CROP_WIN_Y_ALIGN 1 +#define SIE_CA_CROP_WIN_MAX_X 16383 +#define SIE_CA_CROP_WIN_MAX_Y 16383 +#define SIE_CA_CROP_WIN_MAX_W 10208 ///< (16383*(640/2-1) / 1024 + 1 )*2 = 10208 +#define SIE_CA_CROP_WIN_MAX_H 8160 ///< (16383*(512/2-1) / 1024 + 1 )*2 = 8160 +#define SIE_CA_CROP_WIN_MIN_W 64 +#define SIE_CA_CROP_WIN_MIN_H 64 + +#define SIE_CA_SMPL_MAX_W 640 ///< max horizontal subsample output, line buffer 640x12bit +#define SIE_CA_SMPL_MAX_H 512 ///< max vertical subsample output + +#define SIE_CA_WIN_W_ALIGN 2 +#define SIE_CA_WIN_H_ALIGN 2 +#define SIE_CA_WIN_MIN_W 4 +#define SIE_CA_WIN_MIN_H 2 +#define SIE_CA_WIN_MAX_W 254 +#define SIE_CA_WIN_MAX_H 254 + +#define SIE_LA_CROP_WIN_W_ALIGN 2 +#define SIE_LA_CROP_WIN_H_ALIGN 2 +#define SIE_LA_CROP_WIN_X_ALIGN 1 +#define SIE_LA_CROP_WIN_Y_ALIGN 1 +#define SIE_LA_CROP_WIN_MAX_X 320 ///< 640/2 +#define SIE_LA_CROP_WIN_MAX_Y 256 ///< 512/2 +#define SIE_LA_CROP_WIN_MAX_W 320 ///< scale down from 640, split to rgb, transfer to Y only +#define SIE_LA_CROP_WIN_MAX_H 256 ///< scale down from 512, split to rgb, transfer to Y only +#define SIE_LA_CROP_WIN_MIN_W 32 +#define SIE_LA_CROP_WIN_MIN_H 32 + +#define SIE_LA_WIN_W_ALIGN 1 +#define SIE_LA_WIN_H_ALIGN 1 +#define SIE_LA_WIN_MIN_W 4 +#define SIE_LA_WIN_MIN_H 1 +#define SIE_LA_WIN_MAX_W 255 +#define SIE_LA_WIN_MAX_H 255 + +#define SIE_IN1_LINEOFFSET_ALIGN 4 ///< word align +#define SIE_OUT0_LINEOFFSET_ALIGN 4 ///< word align +#define SIE_OUT1_LINEOFFSET_ALIGN 4 ///< word align +#define SIE_OUT2_LINEOFFSET_ALIGN 4 ///< word align +#define SIE_OUT3_LINEOFFSET_ALIGN 4 ///< word align + +#define SIE_IN1_LINEOFFSET_MAX_SIZE 65532 ///< Byte +#define SIE_OUT0_LINEOFFSET_MAX_SIZE 65532 ///< Byte +#define SIE_OUT1_LINEOFFSET_MAX_SIZE 65532 ///< Byte +#define SIE_OUT2_LINEOFFSET_MAX_SIZE 65532 ///< Byte + +#define SIE_RING_BUFFER_MAX_LEN 2047 ///< line count, ring buffer as line base + +#define SIE_DVS_WIN_W_ALIGN 8 ///< dvs 1 group is 8 pixel +#define SIE_DVS_WIN_H_ALIGN 1 +#define SIE_DVS_WIN_MIN_W 8 +#define SIE_DVS_WIN_MIN_H 1 +#define SIE_DVS_WIN_MAX_W 16376 ///< 16383 align to 8 +#define SIE_DVS_WIN_MAX_H 8191 + +#define SIE_EVS_MOT_OUT_ALIGN 4 +#define SIE_EVS_MOT_OUT_MIN_SIZE 4 +#define SIE_EVS_MOT_OUT_MAX_SIZE 0xfffffffc + +/*********************************************************************************************** + * SIE1 Hardware Limitation Definition (2-pixel base) + ***********************************************************************************************/ +#define SIE1_MAX_OUTPUT_NUM SIE_MAX_OUTPUT_NUM +#define SIE1_MAX_INPUT_NUM SIE_MAX_INPUT_NUM + +#define SIE1_LA_MAX_WIN_NUM SIE_LA_MAX_WIN_NUM + +#define SIE1_CROP_WIN_MAX_W_8BIT SIE_CROP_WIN_MAX_W_8BIT +#define SIE1_CROP_WIN_MAX_W_10BIT SIE_CROP_WIN_MAX_W_10BIT +#define SIE1_CROP_WIN_MAX_W_12BIT SIE_CROP_WIN_MAX_W_12BIT +#define SIE1_CROP_WIN_MAX_W_16BIT SIE_CROP_WIN_MAX_W_16BIT + +#define SIE1_OUT0_LINEOFFSET_ALIGN_HFLIP_8BIT SIE_OUT0_LINEOFFSET_ALIGN +#define SIE1_OUT0_LINEOFFSET_ALIGN_HFLIP_10BIT SIE_OUT0_LINEOFFSET_ALIGN +#define SIE1_OUT0_LINEOFFSET_ALIGN_HFLIP_12BIT SIE_OUT0_LINEOFFSET_ALIGN +#define SIE1_OUT0_LINEOFFSET_ALIGN_HFLIP_16BIT SIE_OUT0_LINEOFFSET_ALIGN + +#define SIE1_BCC_HW_ABILITY 1 ///< support BCC hardware function +#define SIE1_BCC_SHARE_SRC 0 ///< SIE1 + +/*********************************************************************************************** + * SIE2 Hardware Limitation Definition (2-pixel base) + ***********************************************************************************************/ +#define SIE2_MAX_OUTPUT_NUM SIE_MAX_OUTPUT_NUM +#define SIE2_MAX_INPUT_NUM SIE_MAX_INPUT_NUM + +#define SIE2_LA_MAX_WIN_NUM SIE_LA_MAX_WIN_NUM + +#define SIE2_CROP_WIN_MAX_W_8BIT SIE_CROP_WIN_MAX_W_8BIT +#define SIE2_CROP_WIN_MAX_W_10BIT SIE_CROP_WIN_MAX_W_10BIT +#define SIE2_CROP_WIN_MAX_W_12BIT SIE_CROP_WIN_MAX_W_12BIT +#define SIE2_CROP_WIN_MAX_W_16BIT SIE_CROP_WIN_MAX_W_16BIT + +#define SIE2_OUT0_LINEOFFSET_ALIGN_HFLIP_8BIT SIE_OUT0_LINEOFFSET_ALIGN +#define SIE2_OUT0_LINEOFFSET_ALIGN_HFLIP_10BIT SIE_OUT0_LINEOFFSET_ALIGN +#define SIE2_OUT0_LINEOFFSET_ALIGN_HFLIP_12BIT SIE_OUT0_LINEOFFSET_ALIGN +#define SIE2_OUT0_LINEOFFSET_ALIGN_HFLIP_16BIT SIE_OUT0_LINEOFFSET_ALIGN + +#define SIE2_BCC_HW_ABILITY 0 ///< not support BCC hardware function, share with SIE1 +#define SIE2_BCC_SHARE_SRC 0 ///< SIE1 + +/*********************************************************************************************** + * SIE3 Hardware Limitation Definition (2-pixel base) + ***********************************************************************************************/ +#define SIE3_MAX_OUTPUT_NUM SIE_MAX_OUTPUT_NUM +#define SIE3_MAX_INPUT_NUM SIE_MAX_INPUT_NUM + +#define SIE3_LA_MAX_WIN_NUM 8 + +#define SIE3_CROP_WIN_MAX_W_8BIT SIE_CROP_WIN_MAX_W_8BIT +#define SIE3_CROP_WIN_MAX_W_10BIT SIE_CROP_WIN_MAX_W_10BIT +#define SIE3_CROP_WIN_MAX_W_12BIT SIE_CROP_WIN_MAX_W_12BIT +#define SIE3_CROP_WIN_MAX_W_16BIT SIE_CROP_WIN_MAX_W_16BIT + +#define SIE3_OUT0_LINEOFFSET_ALIGN_HFLIP_8BIT SIE_OUT0_LINEOFFSET_ALIGN +#define SIE3_OUT0_LINEOFFSET_ALIGN_HFLIP_10BIT SIE_OUT0_LINEOFFSET_ALIGN +#define SIE3_OUT0_LINEOFFSET_ALIGN_HFLIP_12BIT SIE_OUT0_LINEOFFSET_ALIGN +#define SIE3_OUT0_LINEOFFSET_ALIGN_HFLIP_16BIT SIE_OUT0_LINEOFFSET_ALIGN + +#define SIE3_BCC_HW_ABILITY 0 ///< not support BCC hardware function +#define SIE3_BCC_SHARE_SRC 2 ///< SIE3 + +#endif /* _SIE_LIMIT_H_ */ diff --git a/board/novatek/ns02501/loader/Include/IOReg.h b/board/novatek/ns02501/loader/Include/IOReg.h new file mode 100755 index 000000000000..3aa2c51cc59d --- /dev/null +++ b/board/novatek/ns02501/loader/Include/IOReg.h @@ -0,0 +1,190 @@ +/** + I/O Access header file + + I/O Access header file + + @file IOReg.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef __IO_REG_H +#define __IO_REG_H + +#include "constant.h" +#include "CMacro.h" +#include "Memory.h" + +/** + @addtogroup mISYSUtil +*/ +//@{ + +/** + @name Input 8bit IO register + + Input 8bit IO register + + @param[in] x I/O address + + @return register value +*/ +//@{ +#define INREG8(x) (*((volatile UINT8*)(x))) ///< Read 8bits IO register +//@} + +/** + @name Output 8bit IO register + + Output to 8bit IO register + + @param[in] x I/O address + @param[in] y Value to be output + + @return void +*/ +//@{ +#define OUTREG8(x, y) (*((volatile UINT8*)(x)) = (y)) ///< Write 8bits IO register +//@} + +/** + @name Set bits to 8bit IO register + + Set bits to 8bit IO register + + @param[in] x I/O address + @param[in] y Value to be set. y will be ORed to this address + + @return register value +*/ +//@{ +#define SETREG8(x, y) OUTREG8((x), INREG8(x) | (y)) ///< Set 8bits IO register +//@} + +/** + @name Clear bits from 8bit IO register + + Clear bits from 8bit IO register + + @param[in] x I/O address + @param[in] y Value to be clear. ~(y) will be ANDed to this address + + @return register value +*/ +//@{ +#define CLRREG8(x, y) OUTREG8((x), INREG8(x) & ~(y)) ///< Clear 8bits IO register +//@} + +/** + @name Input 16bit IO register + + Input 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + + @return register value +*/ +//@{ +#define INREG16(x) (*((volatile UINT16*)(x))) ///< Read 16bits IO register +//@} + +/** + @name Output 16bit IO register + + Output to 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + @param[in] y Value to be output + + @return void +*/ +//@{ +#define OUTREG16(x, y) (*((volatile UINT16*)(x)) = (y)) ///< Write 16bits IO register +//@} + +/** + @name Set bits to 16bit IO register + + Set bits to 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + @param[in] y Value to be set. y will be ORed to this address + + @return register value +*/ +//@{ +#define SETREG16(x, y) OUTREG16((x), INREG16(x) | (y)) ///< Set 16bits IO register +//@} + +/** + @name Clear bits from 16bit IO register + + Clear bits from 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + @param[in] y Value to be clear. ~(y) will be ANDed to this address + + @return register value +*/ +//@{ +#define CLRREG16(x, y) OUTREG16((x), INREG16(x) & ~(y)) ///< Clear 16bits IO register +//@} + +/** + @name Input 32bit IO register + + Input 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + + @return register value +*/ +//@{ +#define INREG32(x) (*((volatile UINT32*)(x))) ///< Read 32bits IO register +//@} + +/** + @name Output 32bit IO register + + Output to 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + @param[in] y Value to be output + + @return void +*/ +//@{ +#define OUTREG32(x, y) (*((volatile UINT32*)(x)) = (y)) ///< Write 32bits IO register +//@} + +/** + @name Set bits to 32bit IO register + + Set bits to 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + @param[in] y Value to be set. y will be ORed to this address + + @return register value +*/ +//@{ +#define SETREG32(x, y) OUTREG32((x), INREG32(x) | (y)) ///< Set 32bits IO register +//@} + +/** + @name Clear bits from 32bit IO register + + Clear bits from 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + @param[in] y Value to be clear. ~(y) will be ANDed to this address + + @return register value +*/ +//@{ +#define CLRREG32(x, y) OUTREG32((x), INREG32(x) & ~(y)) ///< Clear 32bits IO register +//@} + +//@} + +#endif // __IO_REG_H diff --git a/board/novatek/ns02501/loader/Include/SMacro.h b/board/novatek/ns02501/loader/Include/SMacro.h new file mode 100755 index 000000000000..bb11ace09ee9 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/SMacro.h @@ -0,0 +1,129 @@ +; Global vars for arg parsing + + GBLS _arg0 + GBLS _arg1 + +; _spaces_remove +; remove start and end spaces from global variable wstring + + MACRO + _spaces_remove $wstring + WHILE ( ("*" :CC: $wstring) :RIGHT: 1 = " ") +$wstring SETS ($wstring :LEFT: (:LEN: $wstring - 1)) + WEND + WHILE ( ($wstring :CC: "*") :LEFT: 1 = " ") +$wstring SETS ($wstring :RIGHT: (:LEN: $wstring - 1)) + WEND + MEND + +; _lbracket_remove +; Attempt to remove a single left bracket - error if not there + + MACRO + _lbracket_remove $s + ASSERT $s:LEFT:1 = "(" +$s SETS $s:RIGHT:(:LEN:$s-1) + _spaces_remove $s + MEND + +; _rbracket_remove +; Attempt to remove a single right bracket - error if not there +; then removes excess spaces + + MACRO + _rbracket_remove $s + ASSERT $s:RIGHT:1 = ")" +$s SETS $s:LEFT:(:LEN:$s-1) + _spaces_remove $s + MEND + +; _comment_remove +; Remove any comment from line end and then strip any spaces + + MACRO + _comment_remove $s + _spaces_remove $s + IF (("**":CC:$s):RIGHT:2) = "*/" + WHILE ($s:RIGHT:2) <> "/*" +$s SETS $s:LEFT:(:LEN:$s-1) + WEND +$s SETS $s:LEFT:(:LEN:$s-2) + _spaces_remove $s + ENDIF + MEND + +; _arg_remove +; Pull an argument from the front of a spaces stripped string + + MACRO + _arg_remove $s,$arg + LCLA _arglen + LCLL _ok +_arglen SETA 0 +_ok SETL {TRUE} + WHILE _ok + IF _arglen>=:LEN:$s +_ok SETL {FALSE} ; break if used up input string + ELSE +$arg SETS ($s:LEFT:(_arglen+1)):RIGHT:1 ; next character + IF $arg=" " +_ok SETL {FALSE} + ELSE +_arglen SETA _arglen+1 + ENDIF + ENDIF + WEND +$arg SETS $s:LEFT:_arglen +$s SETS $s:RIGHT:(:LEN:$s-_arglen) + _spaces_remove $s + MEND + +; ifndef +; Purpose: Allow #ifndef for common C headers (Just for guarded C header file) +; Syntax : #ifndef + + MACRO + ifndef $a + MEND + +; define +; Purpose: Allow #defines for common C/Assembler headers +; Syntax : #define + + MACRO +$la define $a +_arg0 SETS "$a" + ASSERT "$la"="#" ; syntax: # define fred 1 + _comment_remove _arg0 + _arg_remove _arg0,_arg1 + IF "$_arg0"<>"" +$_arg1 EQU $_arg0 + ENDIF + MEND + + +; COMMENT +; Purpose: Allow comments in common C/Assembler headers +; Syntax : COMMENT + + MACRO + COMMENT $a,$b,$c,$d,$e,$f,$g,$h + MEND + +; local labels use label$l to get a local label and LOCAL to start a new +; area + + GBLA LocalCount + GBLS l +LocalCount SETA 1 +l SETS "x$LocalCount" + +; increment local variable number + + MACRO + LOCAL +LocalCount SETA LocalCount+1 +l SETS "x$LocalCount" + MEND + + END diff --git a/board/novatek/ns02501/loader/Include/StorageDef.h b/board/novatek/ns02501/loader/Include/StorageDef.h new file mode 100755 index 000000000000..e9366f4a3d4e --- /dev/null +++ b/board/novatek/ns02501/loader/Include/StorageDef.h @@ -0,0 +1,481 @@ +/** + Storage module driver. + + This file is the driver of storage module. + + @file StorageDef.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _STORAGE_DEF_ +#define _STORAGE_DEF_ + +#include "constant.h" + +#define _STORAGE_OBJ_ 1 +/** + @addtogroup mIDrvStorage +*/ +//@{ + +/** + @name External storage type + +*/ +//@{ +#define EXT_STORAGE_TYPE_NONE (0) +#define EXT_STORAGE_TYPE_SDIO1 (1) +#define EXT_STORAGE_TYPE_SDIO2 (2) +#define EXT_STORAGE_TYPE_USB (3) +#define EXT_STORAGE_TYPE_ETH (4) +//*} + +/** + @name SPI Bus Width + + @note for SPI_IDENTIFY +*/ +//@{ +#define SPI_BUSWIDTH_NORMAL 0x00000000 ///< Normal (1-bit) +#define SPI_BUSWIDTH_DUAL 0x00000001 ///< Dual read (2-bit) + +#define SPI_BUSWIDTH_QUAD_TYPE1 0x00000010 ///< Quad read (4-bit) Type1: QE(Quad Enable) bit is in Status Reigster[bit 6] and 0x6B command requires 8 dummy clocks. +#define SPI_BUSWIDTH_QUAD_TYPE2 0x00000020 ///< Quad read (4-bit) Type2: QE(Quad Enable) bit is in Status Register[bit 9] and 0x6B command requires 8 dummy clocks. +#define SPI_BUSWIDTH_QUAD_TYPE3 0x00000040 ///< Quad read (4-bit) Type3: QE(Quad Enable) NOT exist and 0x6B command requires 8 dummy clocks. +#define SPI_BUSWIDTH_QUAD_TYPE4 0x00000080 ///< Quad read (4-bit) Type4: QE(Quad Enable) bit is in Status Register[bit 9] and 0x6B command requires 8 dummy clocks. + ///< But QE should be modified by 0x31 command + +#define SPI_BUSWIDTH_OCTAL_TYPE1 0x00010000 ///< Octal IO Type1: Octal Page Program(1-1-8, 82h/84h) and Read(1-1-8, 8Bh/7Ch) +#define SPI_BUSWIDTH_OCTAL_TYPE2 0x00020000 ///< Octal IO Type2: MXIC type (OPI 2Byte cmd)(TBD) + +#define SPI_BUSWIDTH_DTR_READ 0x00100000 ///< Support DTR IO read(TBD) + +#define SPI_QUAD_MASK (SPI_BUSWIDTH_QUAD_TYPE1|SPI_BUSWIDTH_QUAD_TYPE2|SPI_BUSWIDTH_QUAD_TYPE3|SPI_BUSWIDTH_QUAD_TYPE4) +//@} + + +/** + @name SPI RDCR read type + + @note for SPI_IDENTIFY +*/ +//@{ +#define SPI_RDCR_NONE 0 ///< Not support +#define SPI_RDCR_TYPE1 1 ///< Support RDCR(0x15) bit[7..6] need config as 0x3 +//@} + +/** + @name SPI DTR read type + + @note for SPI_IDENTIFY +*/ +//@{ +#define SPI_DTR_NONE 0 ///< Not support +#define SPI_DTR_SUPPORT 1 ///< Support SPI Double Transfer Rate +//@} + +/** + @name EMMC BOOT Partition + + @note for flash_setConfig +*/ +//@{ +#define EMMC_BOOT_PARTITION_1 1 +#define EMMC_BOOT_PARTITION_2 2 +#define EMMC_BOOT_PARTITION_USER 7 + +//@} + +/** + SPI flash identify descriptor + + @note For STRG_IDENTIFY_CB +*/ +typedef struct +{ + BOOL bSupportEWSR; ///< EWSR(0x50) command capability + ///< - @b TRUE: support EWSR command + ///< - @b FALSE: NOT support EWSR command + BOOL bSupportAAI; ///< AAI program(0xAD) command capability + ///< - @b TRUE: ONLY support AAI program command + ///< - @b FALSE: NOT support AAI program command, but support page program command + UINT32 uiBusWidth; ///< Flash bus width config: normal(1-bit) / dual(2-bit) / quad(4-bit) / octal(8-bit) + UINT32 uiFlashSize; ///< Flash total byte size. (unit: byte) + UINT32 uiDummyCycle; ///< [Optional] DTR mode dummy cycle +} SPI_IDENTIFY, *PSPI_IDENTIFY; + +/** + @name Storage Access CallBack + + Storage Access CallBack Prototype + + @return void +*/ +//@{ +typedef void (*STRG_ACCESS_CB)(void); ///< Storage access call back prototype +//@} + +/** + @name Storage Identify CallBack + + Storage Identify CallBack Prototype + + @param[in] UINT32 uiMfgID (JEDEC) manufacturer ID read from spi flash + @param[in] UINT32 uiTypeID (JEDEC) type ID read from spi flash + @param[in] UINT32 uiCapacityID (JEDEC) capacity ID read from spi flash + @param[out] PSPI_IDENTIFY flash identification returned to spi flash driver + + @return + - @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information + - @b FALSE: input ID is NOT supported/identified by call back +*/ +//@{ +typedef BOOL (*STRG_IDENTIFY_CB)(UINT32, UINT32, UINT32, PSPI_IDENTIFY); ///< Storage identify call back prototype +//@} + +/** + @name Storage return value + + @note for flash_open(), flash_readSectors(), and flash_writeSectors() +*/ +//@{ +#define E_OK 0 ///< Success +#define E_NAND_IDENTIFY_ERR -1 ///< Read NAND ID (information) error +#define E_NAND_INSUFFICINET_BLK -2 ///< Bad block is too much to write data +#define E_NAND_BLK_NOT_FOUND -3 ///< Logic block number not found in physical block +#define E_NAND_WRITE_PAGEDATA_ERR -4 ///< Logic block number not found in physical block +#define E_NAND_ERASEE_BLK_ERR -5 ///< NAND erase block error +#define E_NAND_READ_PAGE_ERR -6 ///< NAND read page data error +#define E_NAND_READ_BLK_ERR -7 ///< NAND read block data error +#define E_NAND_ID_NOT_SUPPORT -8 ///< Not support NAND ID +#define E_IDENTIFY_ERR -9 ///< SPI IDENTIFY error +#define E_SYS -10 ///< System Error +#define E_NAND_ALIGN_ERR -11 ///< Not block alignment +#define E_NAND_BOUNDARY_ERR -12 ///< boundary < write buffer +#define E_OK_TABLE_FOUND 1 ///< Success & NAND table find +#define E_OK_TABLE_NOT_FOUND 2 ///< Success & NAND table not find +//@} + +/** + @name Internal Storage Update Region + + @note for flash_readSectors(), and flash_writeSectors() +*/ +//@{ +#define NAND_RW_LOADER 0 ///< Update Region is Loader (Update size is assumed 16 KB) +#define NAND_RW_RESERVED 1 ///< Update Region is reserved area (Update size is assumed 16 KB) +#define NAND_RW_FIRMWARE 2 ///< Update Region is FW (Update size is variable) +#define NAND_RW_FIRMWARE_2 3 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_3 4 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_4 5 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_5 6 ///< Update Region is FW from 2-5(Update size is variable) +//@} + +/** + @name Internal Storage Configuration ID + + @note for flash_setConfig() +*/ +//@{ +#define FLASH_CFG_ID_NONE 0 +#define FLASH_CFG_ID_SPI_SUPPORT_4BITS 1 ///< Enable your project to support 4 bit SPI flash. ONLY enable when you ENSURE SPI_D0~SPI_D3 are connected to SPI flash in your PCB!!! +#define FLASH_CFG_ID_EMMC_SUPPORT_8BITS 2 ///< Enable your project to support 8 bit EMMC. ONLY enable when you ENSURE EMMC_D0~SPI_D7 are connected to EMMC flash in your PCB!!! +#define FLASH_CFG_ID_CS_SELECT 3 ///< Select this flash (nand/nor) is connected with CS0 or CS1 +#define FLASH_CFG_ID_SPI_IDENTIFY_CB 4 ///< Install flash identify call back +#define FLASH_CFG_ID_SIM_BURN_IMG 5 ///< During BCH host ECC, simulate burning machine's flow +#define FLASH_CFG_ID_HIGH_SPEED 6 ///< Experimental config for fast boot +#define FLASH_CFG_ID_EMMC_BOOT_AREA 7 ///< Enable your project to support EMMC boot area. +#define FLASH_CFG_ID_SPI_SUPPORT_DTR 8 ///< Enable your project to support DTR. ONLY available @ read path & Quad mode and MXIC(MX25L25635E) +#define FLASH_CFG_ID_EMMC_CLEAR_WP 9 ///< Enable CLEAR_WRITE_PROT CMD. Clear the write protection bit of the addressed group +//@} + +#if (_STORAGE_OBJ_== 1) + + +#define BOOT_SOURCE_SPI 0x00 +#define BOOT_SOURCE_SPI_NAND_2K 0x02 +#define BOOT_SOURCE_SPI_NAND_4K 0x06 +#define BOOT_SOURCE_SPI_NAND_BCH_2K 0x03 +#define BOOT_SOURCE_SPI_NAND_BCH_4K 0x0A +#define BOOT_SOURCE_EMMC_4BIT 0x08 +#define BOOT_SOURCE_EMMC_8BIT 0x09 + +/** + @name New storage object interface + + For new version storage device driver +*/ +//@{ +typedef struct { + INT32(*flash_open)(void); ///< Flash Open + void(*flash_close)(void); ///< Flash Close + INT32(*flash_readSectors)(UINT32, UINT32, UINT8 *,UINT32); ///< Flash Read Sector + INT32(*flash_writeSectors)(UINT32, UINT32, UINT8 *, UINT32); ///< Flash Write Sector + INT32(*flash_writePartition)(UINT32, UINT32, UINT32, UINT8 *, UINT32); ///< Flash Write Sector, and remain space need erase + UINT32(*flash_getBlockSize)(void); ///< Flash Get Block Size + void(*flash_setReservedBadBlockNumber)(UINT32); ///< Flash Set Reserved Bad Block Number + void(*flash_setReservedAreaMaxBlockNumber)(UINT32); ///< Flash Set Reserved Area Block Number + UINT64(*flash_getTotalSize)(void); + void(*flash_installAccessCB)(STRG_ACCESS_CB); + void(*flash_installIdentifyCB)(STRG_IDENTIFY_CB); + void(*flash_setFrequency)(UINT32); + INT32(*flash_setConfig)(UINT32, UINT32); + INT32(*flash_get_spare_data)(UINT32, UINT32 *); + INT32(*flash_auto_tune_read_block)(UINT32, UINT32, UINT8 *,UINT32); ///< Flash auto tunning API for read block +} STORAGE_OBJ, *PSTORAGE_OBJ; + +extern PSTORAGE_OBJ none_get_storage_object(void); +extern PSTORAGE_OBJ emmc_get_storage_object(void); +extern PSTORAGE_OBJ nand_get_storage_object(void); +extern PSTORAGE_OBJ nor_get_storage_object(void); +extern PSTORAGE_OBJ nand_bch_get_storage_object(void); + +//@} +#else +#define FLASH_OPEN(m) flash_open() +#define FLASH_CLOSE(m) flash_close() +#define FLASH_READSECTOR(m, n, o, x, y) flash_readSectors(n,o,x,y) ///< Flash Read Sector +#define FLASH_WRITESECTOR(m, n, o, x, y) flash_writeSectors(n,o,x,y) ///< Flash Write Sector +#define FLASH_GETBLKSIZE(m) flash_getBlockSize() + + void(*flash_setReservedBadBlockNumber)(UINT32); ///< Flash Set Reserved Bad Block Number + void(*flash_setReservedAreaMaxBlockNumber)(UINT32); ///< Flash Set Reserved Area Block Number + UINT64(*flash_getTotalSize)(void); + void(*flash_installAccessCB)(STRG_ACCESS_CB); + void(*flash_installIdentifyCB)(STRG_IDENTIFY_CB); + void(*flash_setFrequency)(UINT32); + INT32(*flash_setConfig)(UINT32, UINT32); +} STORAGE_OBJ, *PSTORAGE_OBJ; + +/** + Flash Open + + This function will initialize internal flash driver + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return + - @b E_OK: open success + - @b E_IDENTIFY_ERR: identify fail (SPI path) + - @b E_NAND_IDENTIFY_ERR: identify fail (NAND path) + - @b E_NAND_ID_NOT_SUPPORT: not supported NAND flash +*/ +extern INT32 flash_open(void); +/** + Flash Close + + This function will close internal flash driver + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return void +*/ +extern void flash_close(void); + +/** + Flash Read Sector + + This function will read data from internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] startblk Start block of this read operation (unit: flash block) + @param[in] length Length of read operation (unit: byte) + @param[out] buffer Pointer to DRAM buffer to receive read data (word alignment) + @param[in] updateType Operation Access Region + - @b NAND_RW_LOADER: loader region + - @b NAND_RW_RESERVED: reserved area + - @b NAND_RW_FIRMWARE: f/w region + + @return + - @b E_OK: read success + - @b E_NAND_BLK_NOT_FOUND: can not find available physical block + - @b E_NAND_READ_BLK_ERR: NAND access block error + - @b E_NAND_READ_PAGE_ERR: NAND access page error +*/ +extern INT32 flash_readSectors(UINT32 startblk, UINT32 length, UINT8 * buffer, UINT32 updateType); + +/** + Flash Write Sector + + This function will write data to internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] startblk Start block of this write operation (unit: flash block) + @param[in] length Length of write operation (unit: byte) + @param[in] buffer Pointer to DRAM buffer of written data (word alignment) + @param[in] updateType Operation Access Region + - @b NAND_RW_LOADER: loader region + - @b NAND_RW_RESERVED: reserved area + - @b NAND_RW_FIRMWARE: f/w region + + @return + - @b E_OK: read success + - @b E_NAND_BLK_NOT_FOUND: can not find available physical block + - @b E_NAND_ERASEE_BLK_ERR: erase block error + - @b E_NAND_WRITE_PAGEDATA_ERR: page program error + - @b E_NAND_INSUFFICINET_BLK: insufficient good block +*/ +extern INT32 flash_writeSectors(UINT32 startblk, UINT32 length, UINT8 * buffer, UINT32 updateType); + +/** + Flash Get Block Size + + This function will return block size of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return block size (unit: byte) +*/ +extern UINT32 flash_getBlockSize(void); + +/** + Flash Set Reserved Bad Block Number + + This function will set block count reserved to do bad block replacement + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] badBlkNum reserved bad block count (unit: block) + + @return void +*/ +extern void flash_setReservedBadBlockNumber(UINT32 badBlkNum); + +//#NT#2010/04/20#Steven Wang -begin +//#NT#Autumn reserved area from 2 ~ 23 +/** + Flash Set Reserved Area Block Number + + This function will set reserved area max block count + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] RsvMaxBlkNum max reserved area block count (unit: block) + + @return void +*/ +extern void flash_setReservedAreaMaxBlockNumber(UINT32 RsvMaxBlkNum); +//#NT#2010/04/20#Steven Wang -end + +/** + Flash Get Total Size + + This function will return total size of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return total size (unit: byte) +*/ +extern UINT64 flash_getTotalSize(void); + +/** + Install Flash Access CallBack + + This function will install access callback. + The installed callback will be invoked when one block/page is programmed + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @param[in] accessCB installed callback + + @return void +*/ +extern void flash_installAccessCB(STRG_ACCESS_CB accessCB); + +/** + Install Flash Identify CallBack + + This function will install identification callback. + The installed callback will be invoked when spi flash driver is opened. + + @note NAND driver will NOT invoke the installed call back + + @param[in] identifyCB installed callback + + @return void +*/ +extern void flash_installIdentifyCB(STRG_IDENTIFY_CB identifyCB); + +/** + Flash Set Bus Frequency + + This function will set operating frequency of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] uiFreq Operating frequency (unit: MHz) + + @return void +*/ +extern void flash_setFrequency(UINT32 uiFreq); + +/** + Flash Set Configuration + + This function will set specific configuration for internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] uiConfigId Configuration ID, can be: + - @b FLASH_CFG_ID_SPI_SUPPORT_4BITS: configure to support 4 bit SPI flash + @param[in] uiContext Configuration context for uiConfigId + When uiConfigId == FLASH_CFG_ID_SPI_SUPPORT_4BITS: + - @b TRUE: use 4 bit read when attached SPI flash support 4 bit read + - @b FALSE: won't use 4 bit read + + @return + - @b E_OK: success + - @b Else: fail +*/ +extern INT32 flash_setConfig(UINT32 uiConfigId, UINT32 uiContext); +#endif +// External storage public API ( SDIO/MS/xD ) +/** + Open card driver + + This function will initialize card driver and register it to file system + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return + - @b TRUE: open success + - @b FALSE: open fail +*/ +extern INT32 card_open(void); + +/** + Close card driver + + This function will close card driver + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return void +*/ +extern void card_close(void); + +/** + Get card type + + This function is used to get card storage type + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return void +*/ + +extern UINT32 card_get_type(void); + +//@} + +extern void USBOTGReset(void); +//extern INT32 USB3Download(void); +extern INT32 USBDownload(void); +extern void USBSetResult(UINT32 uiResult); +extern INT32 USBStateMachine(void); +#endif diff --git a/board/novatek/ns02501/loader/Include/Type.h b/board/novatek/ns02501/loader/Include/Type.h new file mode 100755 index 000000000000..4c6cb91f1602 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/Type.h @@ -0,0 +1,9 @@ +#ifndef __TYPE_H +#define __TYPE_H + +#include +//#include + +#define _ALIGNED(x) __attribute__((aligned(x))) + +#endif // __TYPE_H diff --git a/board/novatek/ns02501/loader/Include/at80c51.h b/board/novatek/ns02501/loader/Include/at80c51.h new file mode 100755 index 000000000000..f2184654bb75 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/at80c51.h @@ -0,0 +1,30 @@ +#ifndef _AT80C51_H +#define _AT80C51_H + +typedef enum _MCU_CC_TYPE { + MCU_CC_TYPE_UNKNOWN, + MCU_CC_TYPE_SYSTEM, + MCU_CC_TYPE_USER, +} MCU_CC_TYPE; + +// if modified, wq_cc.h at80c51.h (sdk, loader) must sync +typedef enum _MCU_CC_SYSCMD_ID { + MCU_CC_SYSCMD_ID_UNKNOWN, + MCU_CC_SYSCMD_ID_SHUTDOWN, + MCU_CC_SYSCMD_ID_SHUTDOWN_AT80C51_PD1, + MCU_CC_SYSCMD_ID_SHUTDOWN_AT80C51_PD2, + MCU_CC_SYSCMD_ID_PERIODIC_MANUAL_PD1, + MCU_CC_SYSCMD_ID_PERIODIC_MANUAL_PD2, + MCU_CC_SYSCMD_ID_PERIODIC_VD_PD1, + MCU_CC_SYSCMD_ID_PERIODIC_VD_PD2, + MCU_CC_SYSCMD_ID_SIMULATE_YDCC_ALARM, + MCU_CC_SYSCMD_ID_MODE_PREROLL, // shutdown main-part for preroll + MCU_CC_SYSCMD_ID_MODE_SENTRY, // shutdown main-part for sentry + MCU_CC_SYSCMD_ID_SET_LOADER2_OFS, // rtos notify flash offset of loader2 (aov) to 8051 + MCU_CC_SYSCMD_ID_REBOOT_TO_MAIN, // loader2 (aov) reboot to loader1 +} MCU_CC_SYSCMD_ID; + +extern int at80c51_ipc(MCU_CC_SYSCMD_ID cmd_id, UINT32 param); +extern int at80c51_is_opened(void); + +#endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Include/constant.h b/board/novatek/ns02501/loader/Include/constant.h new file mode 100755 index 000000000000..6375cad45993 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/constant.h @@ -0,0 +1,115 @@ +#ifndef _CONSTANT_H +#define _CONSTANT_H + +//Size MNEMONIC + +#define SZ_1 (1 << 0) /* 0x00000001 */ +#define SZ_2 (1 << 1) /* 0x00000002 */ +#define SZ_4 (1 << 2) /* 0x00000004 */ +#define SZ_8 (1 << 3) /* 0x00000008 */ +#define SZ_16 (1 << 4) /* 0x00000010 */ +#define SZ_32 (1 << 5) /* 0x00000020 */ +#define SZ_64 (1 << 6) /* 0x00000040 */ +#define SZ_128 (1 << 7) /* 0x00000080 */ +#define SZ_256 (1 << 8) /* 0x00000100 */ +#define SZ_512 (1 << 9) /* 0x00000200 */ + +#define SZ_1K (1 << 10) /* 0x00000400 */ +#define SZ_2K (1 << 11) /* 0x00000800 */ +#define SZ_4K (1 << 12) /* 0x00001000 */ +#define SZ_8K (1 << 13) /* 0x00002000 */ +#define SZ_16K (1 << 14) /* 0x00004000 */ +#define SZ_32K (1 << 15) /* 0x00008000 */ +#define SZ_64K (1 << 16) /* 0x00010000 */ +#define SZ_128K (1 << 17) /* 0x00020000 */ +#define SZ_256K (1 << 18) /* 0x00040000 */ +#define SZ_512K (1 << 19) /* 0x00080000 */ + +#define SZ_1M (1 << 20) /* 0x00100000 */ +#define SZ_2M (1 << 21) /* 0x00200000 */ +#define SZ_4M (1 << 22) /* 0x00400000 */ +#define SZ_8M (1 << 23) /* 0x00800000 */ +#define SZ_16M (1 << 24) /* 0x01000000 */ +#define SZ_32M (1 << 25) /* 0x02000000 */ +#define SZ_64M (1 << 26) /* 0x04000000 */ +#define SZ_128M (1 << 27) /* 0x08000000 */ +#define SZ_256M (1 << 28) /* 0x10000000 */ +#define SZ_512M (1 << 29) /* 0x20000000 */ + +#define SZ_1G (1 << 30) /* 0x40000000 */ +#define SZ_2G (1 << 31) /* 0x80000000 */ + +#define SZ_30M (SZ_32M - SZ_2M) + +// ASCII code + +#define CR 0x0D +#define LF 0x0A +#define BS 0x08 +#define ESC 27 + +// Boolean constant definition + +#if 0 +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef ON +#define ON 1 +#endif + +#ifndef OFF +#define OFF 0 +#endif + +#ifndef ENABLE +#define ENABLE 1 +#endif + +#ifndef DISABLE +#define DISABLE 0 +#endif + +#ifndef DISK_FULL +#define DISK_FULL (-1) +#endif + +// type declaration + +typedef int BOOLEAN; +typedef unsigned long long UINT64; +typedef long long INT64; +typedef unsigned long UINT32; +typedef unsigned long INT32U; +typedef unsigned INT32S; +typedef unsigned char INT8U; +typedef long INT32; +typedef unsigned short UINT16; +typedef short INT16; +typedef unsigned char UINT8; +typedef char INT8; +typedef unsigned long long u64; +typedef unsigned int u32; +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int uint; +typedef unsigned short ushort; +typedef unsigned char uchar; +typedef unsigned int UINT; +typedef int INT; + +typedef enum {FALSE, TRUE} BOOL; + +// error codes +typedef long ER; + +#endif diff --git a/board/novatek/ns02501/loader/Include/ctype.h b/board/novatek/ns02501/loader/Include/ctype.h new file mode 100755 index 000000000000..977d3c69676c --- /dev/null +++ b/board/novatek/ns02501/loader/Include/ctype.h @@ -0,0 +1,36 @@ + + +#ifndef NVT_CTYPES_H__ +#define NVT_CTYPES_H__ + + +#define _U 0x01 /* upper */ +#define _L 0x02 /* lower */ +#define _D 0x04 /* digit */ +#define _C 0x08 /* cntrl */ +#define _P 0x10 /* punct */ +#define _S 0x20 /* white space (space/lf/tab) */ +#define _X 0x40 /* hex digit */ +#define _SP 0x80 /* hard space (0x20) */ + +extern unsigned char _ctype[]; + +#define __ismask(x) (_ctype[(int)(unsigned char)(x)]) + +#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) +#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) +#define iscntrl(c) ((__ismask(c)&(_C)) != 0) +#define isdigit(c) ((__ismask(c)&(_D)) != 0) +#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) +#define islower(c) ((__ismask(c)&(_L)) != 0) +#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) +#define ispunct(c) ((__ismask(c)&(_P)) != 0) +#define isspace(c) ((__ismask(c)&(_S)) != 0) +#define isupper(c) ((__ismask(c)&(_U)) != 0) +#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) + +#define isascii(c) (((unsigned char)(c))<=0x7f) +#define toascii(c) (((unsigned char)(c))&0x7f) + + +#endif diff --git a/board/novatek/ns02501/loader/Include/debug.h b/board/novatek/ns02501/loader/Include/debug.h new file mode 100755 index 000000000000..a8f8bbd730fb --- /dev/null +++ b/board/novatek/ns02501/loader/Include/debug.h @@ -0,0 +1,35 @@ +/** + string header + + string header + + @file string.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_DEBUG_H__ +#define __NVT_DEBUG_H__ + +#include "fuart.h" +/** \addtogroup mISYSClib */ +//@{ + +extern void debug_set_console(CONSOLE_OBJ *p_obj); +extern CONSOLE_OBJ *debug_get_console(void); +extern void debug_err(char *str); +extern void debug_err_var(char *str, int var); +extern void debug_msg(char *str) __attribute__ ((section (".part1"))); +extern void debug_msg_var(char *str, int var) __attribute__ ((section (".part1"))); +extern void debug_dump_addr(UINT32 addr, UINT32 size); +extern int printf(char const *fmt, ...); +extern void perf_mark(char *str); +extern void perf_dump(void); +extern void perf_get_buf(unsigned long *p_buf, int *p_cnt); + +//@} + +#endif + diff --git a/board/novatek/ns02501/loader/Include/fat.h b/board/novatek/ns02501/loader/Include/fat.h new file mode 100755 index 000000000000..488a78e8d2dc --- /dev/null +++ b/board/novatek/ns02501/loader/Include/fat.h @@ -0,0 +1,50 @@ +/** + File system library + + This file is the library of file system + + @file fat.h + @ingroup mISYSFile + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _FAT_H +#define _FAT_H + +#include "constant.h" +#include "StorageDef.h" + +/** + @addtogroup mISYSFile +*/ +//@{ + +#define FAT_READ_TOTAL_FILE_LENGTH 0 + +typedef void (*TOGGLE_LED)(UINT8 WithCount); + +extern BOOL fat_initFAT(UINT32 uiBuf, UINT32 uiSize); +extern UINT32 fat_getPartitionCount(void); +extern BOOL fat_mountPartition(UINT32 partition_id); +extern void fat_closeFAT(void); +extern BOOL fat_open_rootfile(UINT8 *pfilename); +extern UINT32 fat_read_rootfile(UINT8 *pbuf, UINT32 uiRdLen); +extern UINT32 fat_getRootfileSize(void); +extern void fat_close_rootfile(void); +extern void fat_regToggleLED(TOGGLE_LED pToggleLED); +extern void fat_installAccessCB(STRG_ACCESS_CB accessCB); +extern UINT32 fat_write_rootfile(UINT8 *pbuf, UINT32 uiWrLen); + +// For SD registration +extern BOOL fat_internal_initFAT(UINT32 uiBuf, UINT32 uiSize); +extern BOOL fat_internal_open_rootfile(UINT8 *pfilename); +extern UINT32 fat_internal_read_rootfile(UINT8 *pbuf, UINT32 uiRdLen); +extern void fat_internal_close_rootfile(void); +extern UINT32 fat_internal_write_rootfile(UINT8 *pbuf, UINT32 uiWrLen); + +//@} + +#endif + diff --git a/board/novatek/ns02501/loader/Include/fdt/compiler.h b/board/novatek/ns02501/loader/Include/fdt/compiler.h new file mode 100755 index 000000000000..4dc88e80a7ba --- /dev/null +++ b/board/novatek/ns02501/loader/Include/fdt/compiler.h @@ -0,0 +1,50 @@ +#pragma once +/* +* Keep all the ugly #ifdef for system stuff here +*/ + +#ifndef __COMPILER_H__ +#define __COMPILER_H__ + +#ifndef NULL +#define NULL 0 +#endif + +#define uswap_16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) +#define uswap_32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) +#define _uswap_64(x, sfx) \ + ((((x) & 0xff00000000000000##sfx) >> 56) | \ + (((x) & 0x00ff000000000000##sfx) >> 40) | \ + (((x) & 0x0000ff0000000000##sfx) >> 24) | \ + (((x) & 0x000000ff00000000##sfx) >> 8) | \ + (((x) & 0x00000000ff000000##sfx) << 8) | \ + (((x) & 0x0000000000ff0000##sfx) << 24) | \ + (((x) & 0x000000000000ff00##sfx) << 40) | \ + (((x) & 0x00000000000000ff##sfx) << 56)) +#if defined(__GNUC__) +#define uswap_64(x) _uswap_64(x, ull) +#else +#define uswap_64(x) _uswap_64(x, ) +#endif +#define cpu_to_le16(x) (x) +#define cpu_to_le32(x) (x) +#define cpu_to_le64(x) (x) +#define le16_to_cpu(x) (x) +#define le32_to_cpu(x) (x) +#define le64_to_cpu(x) (x) +#define cpu_to_be16(x) uswap_16(x) +#define cpu_to_be32(x) uswap_32(x) +#define cpu_to_be64(x) uswap_64(x) +#define be16_to_cpu(x) uswap_16(x) +#define be32_to_cpu(x) uswap_32(x) +#define be64_to_cpu(x) uswap_64(x) + +/* Type for `void *' pointers. */ +typedef unsigned long int uintptr_t; +#endif diff --git a/board/novatek/ns02501/loader/Include/fdt/fdt.h b/board/novatek/ns02501/loader/Include/fdt/fdt.h new file mode 100755 index 000000000000..74961f9026d1 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/fdt/fdt.h @@ -0,0 +1,111 @@ +#ifndef FDT_H +#define FDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ASSEMBLY__ + +struct fdt_header { + fdt32_t magic; /* magic word FDT_MAGIC */ + fdt32_t totalsize; /* total size of DT block */ + fdt32_t off_dt_struct; /* offset to structure */ + fdt32_t off_dt_strings; /* offset to strings */ + fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ + fdt32_t version; /* format version */ + fdt32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + fdt32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + fdt32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + fdt32_t size_dt_struct; /* size of the structure block */ +}; + +struct fdt_reserve_entry { + fdt64_t address; + fdt64_t size; +}; + +struct fdt_node_header { + fdt32_t tag; + char name[0]; +}; + +struct fdt_property { + fdt32_t tag; + fdt32_t len; + fdt32_t nameoff; + char data[0]; +}; + +#endif /* !__ASSEMBLY */ + +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_TAGSIZE sizeof(fdt32_t) + +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, + size, content */ +#define FDT_NOP 0x4 /* nop */ +#define FDT_END 0x9 + +#define FDT_V1_SIZE (7*sizeof(fdt32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) +#define FDT_V16_SIZE FDT_V3_SIZE +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) + +#endif /* FDT_H */ diff --git a/board/novatek/ns02501/loader/Include/fdt/libfdt.h b/board/novatek/ns02501/loader/Include/fdt/libfdt.h new file mode 100755 index 000000000000..57031b9a590d --- /dev/null +++ b/board/novatek/ns02501/loader/Include/fdt/libfdt.h @@ -0,0 +1,1970 @@ +#ifndef LIBFDT_H +#define LIBFDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#define FDT_FIRST_SUPPORTED_VERSION 0x02 +#define FDT_LAST_SUPPORTED_VERSION 0x11 + +/* Error codes: informative error codes */ +#define FDT_ERR_NOTFOUND 1 + /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ +#define FDT_ERR_EXISTS 2 + /* FDT_ERR_EXISTS: Attempted to create a node or property which + * already exists */ +#define FDT_ERR_NOSPACE 3 + /* FDT_ERR_NOSPACE: Operation needed to expand the device + * tree, but its buffer did not have sufficient space to + * contain the expanded tree. Use fdt_open_into() to move the + * device tree to a buffer with more space. */ + +/* Error codes: codes for bad parameters */ +#define FDT_ERR_BADOFFSET 4 + /* FDT_ERR_BADOFFSET: Function was passed a structure block + * offset which is out-of-bounds, or which points to an + * unsuitable part of the structure for the operation. */ +#define FDT_ERR_BADPATH 5 + /* FDT_ERR_BADPATH: Function was passed a badly formatted path + * (e.g. missing a leading / for a function which requires an + * absolute path) */ +#define FDT_ERR_BADPHANDLE 6 + /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle. + * This can be caused either by an invalid phandle property + * length, or the phandle value was either 0 or -1, which are + * not permitted. */ +#define FDT_ERR_BADSTATE 7 + /* FDT_ERR_BADSTATE: Function was passed an incomplete device + * tree created by the sequential-write functions, which is + * not sufficiently complete for the requested operation. */ + +/* Error codes: codes for bad device tree blobs */ +#define FDT_ERR_TRUNCATED 8 + /* FDT_ERR_TRUNCATED: FDT or a sub-block is improperly + * terminated (overflows, goes outside allowed bounds, or + * isn't properly terminated). */ +#define FDT_ERR_BADMAGIC 9 + /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a + * device tree at all - it is missing the flattened device + * tree magic number. */ +#define FDT_ERR_BADVERSION 10 + /* FDT_ERR_BADVERSION: Given device tree has a version which + * can't be handled by the requested operation. For + * read-write functions, this may mean that fdt_open_into() is + * required to convert the tree to the expected version. */ +#define FDT_ERR_BADSTRUCTURE 11 + /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt + * structure block or other serious error (e.g. misnested + * nodes, or subnodes preceding properties). */ +#define FDT_ERR_BADLAYOUT 12 + /* FDT_ERR_BADLAYOUT: For read-write functions, the given + * device tree has it's sub-blocks in an order that the + * function can't handle (memory reserve map, then structure, + * then strings). Use fdt_open_into() to reorganize the tree + * into a form suitable for the read-write operations. */ + +/* "Can't happen" error indicating a bug in libfdt */ +#define FDT_ERR_INTERNAL 13 + /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. + * Should never be returned, if it is, it indicates a bug in + * libfdt itself. */ + +/* Errors in device tree content */ +#define FDT_ERR_BADNCELLS 14 + /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells + * or similar property with a bad format or value */ + +#define FDT_ERR_BADVALUE 15 + /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected + * value. For example: a property expected to contain a string list + * is not NUL-terminated within the length of its value. */ + +#define FDT_ERR_BADOVERLAY 16 + /* FDT_ERR_BADOVERLAY: The device tree overlay, while + * correctly structured, cannot be applied due to some + * unexpected or missing value, property or node. */ + +#define FDT_ERR_NOPHANDLES 17 + /* FDT_ERR_NOPHANDLES: The device tree doesn't have any + * phandle available anymore without causing an overflow */ + +#define FDT_ERR_MAX 17 + +/**********************************************************************/ +/* Low-level functions (you probably don't need these) */ +/**********************************************************************/ + +#ifndef SWIG /* This function is not useful in Python */ +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); +#endif +static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) +{ + return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); +} + +uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); + +/** + * NVT_MODIFIED: + * On ARM, unaligned access is supported, so memcpy is not needed. + * Avoid using memcpy to improve performance in fdt_check_full(). + */ +#if 0 +/* + * Alignment helpers: + * These helpers access words from a device tree blob. They're + * built to work even with unaligned pointers on platforms (ike + * ARM) that don't like unaligned loads and stores + */ + +static inline uint32_t fdt32_ld(const fdt32_t *p) +{ + fdt32_t v; + + memcpy(&v, p, sizeof(v)); + return fdt32_to_cpu(v); +} + +static inline uint64_t fdt64_ld(const fdt64_t *p) +{ + fdt64_t v; + + memcpy(&v, p, sizeof(v)); + return fdt64_to_cpu(v); +} +#else +#define fdt32_ld(p) fdt32_to_cpu(*p) +#define fdt64_ld(p) fdt64_to_cpu(*p) +#endif + +/**********************************************************************/ +/* Traversal functions */ +/**********************************************************************/ + +int fdt_next_node(const void *fdt, int offset, int *depth); + +/** + * fdt_first_subnode() - get offset of first direct subnode + * + * @fdt: FDT blob + * @offset: Offset of node to check + * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + */ +int fdt_first_subnode(const void *fdt, int offset); + +/** + * fdt_next_subnode() - get offset of next direct subnode + * + * After first calling fdt_first_subnode(), call this function repeatedly to + * get direct subnodes of a parent node. + * + * @fdt: FDT blob + * @offset: Offset of previous subnode + * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes + */ +int fdt_next_subnode(const void *fdt, int offset); + +/** + * fdt_for_each_subnode - iterate over all subnodes of a parent + * + * @node: child node (int, lvalue) + * @fdt: FDT blob (const void *) + * @parent: parent node (int) + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_subnode(node, fdt, parent) { + * Use node + * ... + * } + * + * if ((node < 0) && (node != -FDT_ERR_NOT_FOUND)) { + * Error handling + * } + * + * Note that this is implemented as a macro and @node is used as + * iterator in the loop. The parent variable be constant or even a + * literal. + * + */ +#define fdt_for_each_subnode(node, fdt, parent) \ + for (node = fdt_first_subnode(fdt, parent); \ + node >= 0; \ + node = fdt_next_subnode(fdt, node)) + +/**********************************************************************/ +/* General functions */ +/**********************************************************************/ +#define fdt_get_header(fdt, field) \ + (fdt32_ld(&((const struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) +#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) +#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) +#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) +#define fdt_version(fdt) (fdt_get_header(fdt, version)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) + +#define fdt_set_hdr_(name) \ + static inline void fdt_set_##name(void *fdt, uint32_t val) \ + { \ + struct fdt_header *fdth = (struct fdt_header *)fdt; \ + fdth->name = cpu_to_fdt32(val); \ + } +fdt_set_hdr_(magic); +fdt_set_hdr_(totalsize); +fdt_set_hdr_(off_dt_struct); +fdt_set_hdr_(off_dt_strings); +fdt_set_hdr_(off_mem_rsvmap); +fdt_set_hdr_(version); +fdt_set_hdr_(last_comp_version); +fdt_set_hdr_(boot_cpuid_phys); +fdt_set_hdr_(size_dt_strings); +fdt_set_hdr_(size_dt_struct); +#undef fdt_set_hdr_ + +/** + * fdt_header_size - return the size of the tree's header + * @fdt: pointer to a flattened device tree + */ +size_t fdt_header_size_(uint32_t version); +static inline size_t fdt_header_size(const void *fdt) +{ + return fdt_header_size_(fdt_version(fdt)); +} + +/** + * fdt_check_header - sanity check a device tree header + + * @fdt: pointer to data which might be a flattened device tree + * + * fdt_check_header() checks that the given buffer contains what + * appears to be a flattened device tree, and that the header contains + * valid information (to the extent that can be determined from the + * header alone). + * + * returns: + * 0, if the buffer appears to contain a valid device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_TRUNCATED, standard meanings, as above + */ +int fdt_check_header(const void *fdt); + +/** + * fdt_move - move a device tree around in memory + * @fdt: pointer to the device tree to move + * @buf: pointer to memory where the device is to be moved + * @bufsize: size of the memory space at buf + * + * fdt_move() relocates, if possible, the device tree blob located at + * fdt to the buffer at buf of size bufsize. The buffer may overlap + * with the existing device tree blob at fdt. Therefore, + * fdt_move(fdt, fdt, fdt_totalsize(fdt)) + * should always succeed. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_move(const void *fdt, void *buf, int bufsize); + +/**********************************************************************/ +/* Read-only functions */ +/**********************************************************************/ + +int fdt_check_full(const void *fdt, size_t bufsize); + +/** + * fdt_get_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * @lenp: optional pointer to return the string's length + * + * fdt_get_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt, and optionally also + * returns the string's length in *lenp. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds, or doesn't point to a valid string + */ +const char *fdt_get_string(const void *fdt, int stroffset, int *lenp); + +/** + * fdt_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * + * fdt_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds, or doesn't point to a valid string + */ +const char *fdt_string(const void *fdt, int stroffset); + +/** + * fdt_get_max_phandle - retrieves the highest phandle in a tree + * @fdt: pointer to the device tree blob + * + * fdt_get_max_phandle retrieves the highest phandle in the given + * device tree. This will ignore badly formatted phandles, or phandles + * with a value of 0 or -1. + * + * returns: + * the highest phandle on success + * 0, if no phandle was found in the device tree + * -1, if an error occurred + */ +uint32_t fdt_get_max_phandle(const void *fdt); + +/** + * fdt_num_mem_rsv - retrieve the number of memory reserve map entries + * @fdt: pointer to the device tree blob + * + * Returns the number of entries in the device tree blob's memory + * reservation map. This does not include the terminating 0,0 entry + * or any other (0,0) entries reserved for expansion. + * + * returns: + * the number of entries + */ +int fdt_num_mem_rsv(const void *fdt); + +/** + * fdt_get_mem_rsv - retrieve one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: pointers to 64-bit variables + * + * On success, *address and *size will contain the address and size of + * the n-th reserve map entry from the device tree blob, in + * native-endian format. + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); + +/** + * fdt_subnode_offset_namelen - find a subnode based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_subnode_offset(), but only examine the first + * namelen characters of name for matching the subnode name. This is + * useful for finding subnodes based on a portion of a larger string, + * such as a full path. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, + const char *name, int namelen); +#endif +/** + * fdt_subnode_offset - find a subnode of a given node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node at structure block + * offset parentoffset with the given name. name may include a unit + * address, in which case fdt_subnode_offset() will find the subnode + * with that unit address, or the unit address may be omitted, in + * which case fdt_subnode_offset() will find an arbitrary subnode + * whose name excluding unit address matches the given name. + * + * returns: + * structure block offset of the requested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); + +/** + * fdt_path_offset_namelen - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * @namelen: number of characters of path to consider + * + * Identical to fdt_path_offset(), but only consider the first namelen + * characters of path as the path name. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); +#endif + +/** + * fdt_path_offset - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * + * fdt_path_offset() finds a node of a given path in the device tree. + * Each path component may omit the unit address portion, but the + * results of this are undefined if any such path component is + * ambiguous (that is if there are multiple nodes at the relevant + * level matching the given component, differentiated only by unit + * address). + * + * returns: + * structure block offset of the node with the requested path (>=0), on + * success + * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_NOTFOUND, if the requested node does not exist + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_path_offset(const void *fdt, const char *path); + +/** + * fdt_get_name - retrieve the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the starting node + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_name() retrieves the name (including unit address) of the + * device tree node at structure block offset nodeoffset. If lenp is + * non-NULL, the length of this name is also returned, in the integer + * pointed to by lenp. + * + * returns: + * pointer to the node's name, on success + * If lenp is non-NULL, *lenp contains the length of that name + * (>=0) + * NULL, on error + * if lenp is non-NULL *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); + +/** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_for_each_property_offset - iterate over all properties of a node + * + * @property_offset: property offset (int, lvalue) + * @fdt: FDT blob (const void *) + * @node: node offset (int) + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_property_offset(property, fdt, node) { + * Use property + * ... + * } + * + * if ((property < 0) && (property != -FDT_ERR_NOT_FOUND)) { + * Error handling + * } + * + * Note that this is implemented as a macro and property is used as + * iterator in the loop. The node variable can be constant or even a + * literal. + */ +#define fdt_for_each_property_offset(property, fdt, node) \ + for (property = fdt_first_property_offset(fdt, node); \ + property >= 0; \ + property = fdt_next_property_offset(fdt, property)) + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * Note that this code only works on device tree versions >= 16. fdt_getprop() + * works on all versions. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** + * fdt_get_property_namelen - find a property based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_get_property(), but only examine the first namelen + * characters of name for matching the property name. + */ +#ifndef SWIG /* Not available in Python */ +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int nodeoffset, + const char *name, + int namelen, int *lenp); +#endif + +/** + * fdt_get_property - find a given property in a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property() retrieves a pointer to the fdt_property + * structure within the device tree blob corresponding to the property + * named 'name' of the node at offset nodeoffset. If lenp is + * non-NULL, the length of the property value is also returned, in the + * integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, + const char *name, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @ffset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#ifndef SWIG /* This function is not useful in Python */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); +#endif + +/** + * fdt_getprop_namelen - get property value based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_getprop(), but only examine the first namelen + * characters of name for matching the property name. + */ +#ifndef SWIG /* Not available in Python */ +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp); +static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset, + const char *name, int namelen, + int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name, + namelen, lenp); +} +#endif + +/** + * fdt_getprop - retrieve the value of a given property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline void *fdt_getprop_w(void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_get_phandle - retrieve the phandle of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the node + * + * fdt_get_phandle() retrieves the phandle of the device tree node at + * structure block offset nodeoffset. + * + * returns: + * the phandle of the node at nodeoffset, on success (!= 0, != -1) + * 0, if the node has no phandle, or another error occurs + */ +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); + +/** + * fdt_get_alias_namelen - get alias based on substring + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * @namelen: number of characters of name to consider + * + * Identical to fdt_get_alias(), but only examine the first namelen + * characters of name for matching the alias name. + */ +#ifndef SWIG /* Not available in Python */ +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen); +#endif + +/** + * fdt_get_alias - retrieve the path referenced by a given alias + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * + * fdt_get_alias() retrieves the value of a given alias. That is, the + * value of the property named 'name' in the node /aliases. + * + * returns: + * a pointer to the expansion of the alias named 'name', if it exists + * NULL, if the given alias or the /aliases node does not exist + */ +const char *fdt_get_alias(const void *fdt, const char *name); + +/** + * fdt_get_path - determine the full path of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose path to find + * @buf: character buffer to contain the returned path (will be overwritten) + * @buflen: size of the character buffer at buf + * + * fdt_get_path() computes the full path of the node at offset + * nodeoffset, and records that path in the buffer at buf. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * 0, on success + * buf contains the absolute path of the node at + * nodeoffset, as a NUL-terminated string. + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) + * characters and will not fit in the given buffer. + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); + +/** + * fdt_supernode_atdepth_offset - find a specific ancestor of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * @supernodedepth: depth of the ancestor to find + * @nodedepth: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_supernode_atdepth_offset() finds an ancestor of the given node + * at a specific depth from the root (where the root itself has depth + * 0, its immediate subnodes depth 1 and so forth). So + * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); + * will always return 0, the offset of the root node. If the node at + * nodeoffset has depth D, then: + * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); + * will return nodeoffset itself. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * structure block offset of the node at node offset's ancestor + * of depth supernodedepth (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of + * nodeoffset + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth); + +/** + * fdt_node_depth - find the depth of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_node_depth() finds the depth of a given node. The root node + * has depth 0, its immediate subnodes depth 1 and so forth. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * depth of the node at nodeoffset (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_depth(const void *fdt, int nodeoffset); + +/** + * fdt_parent_offset - find the parent of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_parent_offset() locates the parent node of a given node (that + * is, it finds the offset of the node which contains the node at + * nodeoffset as a subnode). + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset, *twice*. + * + * returns: + * structure block offset of the parent of the node at nodeoffset + * (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_parent_offset(const void *fdt, int nodeoffset); + +/** + * fdt_node_offset_by_prop_value - find nodes with a given property value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * + * fdt_node_offset_by_prop_value() returns the offset of the first + * node after startoffset, which has a property named propname whose + * value is of length proplen and has value equal to propval; or if + * startoffset is -1, the very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, + * propval, proplen); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, + * propval, proplen); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen); + +/** + * fdt_node_offset_by_phandle - find the node with a given phandle + * @fdt: pointer to the device tree blob + * @phandle: phandle value + * + * fdt_node_offset_by_phandle() returns the offset of the node + * which has the given phandle value. If there is more than one node + * in the tree with the given phandle (an invalid tree), results are + * undefined. + * + * returns: + * structure block offset of the located node (>= 0), on success + * -FDT_ERR_NOTFOUND, no node with that phandle exists + * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); + +/** + * fdt_node_check_compatible: check a node's compatible property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @compatible: string to match against + * + * + * fdt_node_check_compatible() returns 0 if the given node contains a + * 'compatible' property with the given string as one of its elements, + * it returns non-zero otherwise, or on error. + * + * returns: + * 0, if the node has a 'compatible' property listing the given string + * 1, if the node has a 'compatible' property, but it does not list + * the given string + * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property + * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible); + +/** + * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @compatible: 'compatible' string to match against + * + * fdt_node_offset_by_compatible() returns the offset of the first + * node after startoffset, which has a 'compatible' property which + * lists the given compatible string; or if startoffset is -1, the + * very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible); + +/** + * fdt_stringlist_contains - check a string list property for a string + * @strlist: Property containing a list of strings to check + * @listlen: Length of property + * @str: String to search for + * + * This is a utility function provided for convenience. The list contains + * one or more strings, each terminated by \0, as is found in a device tree + * "compatible" property. + * + * @return: 1 if the string is found in the list, 0 not found, or invalid list + */ +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); + +/** + * fdt_stringlist_count - count the number of strings in a string list + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @return: + * the number of strings in the given property + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist + */ +int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property); + +/** + * fdt_stringlist_search - find a string in a string list and return its index + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @string: string to look up in the string list + * + * Note that it is possible for this function to succeed on property values + * that are not NUL-terminated. That's because the function will stop after + * finding the first occurrence of @string. This can for example happen with + * small-valued cell properties, such as #address-cells, when searching for + * the empty string. + * + * @return: + * the index of the string in the list of strings + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist or does not contain + * the given string + */ +int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, + const char *string); + +/** + * fdt_stringlist_get() - obtain the string at a given index in a string list + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @index: index of the string to return + * @lenp: return location for the string length or an error code on failure + * + * Note that this will successfully extract strings from properties with + * non-NUL-terminated values. For example on small-valued cell properties + * this function will return the empty string. + * + * If non-NULL, the length of the string (on success) or a negative error-code + * (on failure) will be stored in the integer pointer to by lenp. + * + * @return: + * A pointer to the string at the given index in the string list or NULL on + * failure. On success the length of the string will be stored in the memory + * location pointed to by the lenp parameter, if non-NULL. On failure one of + * the following negative error codes will be returned in the lenp parameter + * (if non-NULL): + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist + */ +const char *fdt_stringlist_get(const void *fdt, int nodeoffset, + const char *property, int index, + int *lenp); + +/**********************************************************************/ +/* Read-only functions (addressing related) */ +/**********************************************************************/ + +/** + * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells + * + * This is the maximum value for #address-cells, #size-cells and + * similar properties that will be processed by libfdt. IEE1275 + * requires that OF implementations handle values up to 4. + * Implementations may support larger values, but in practice higher + * values aren't used. + */ +#define FDT_MAX_NCELLS 4 + +/** + * fdt_address_cells - retrieve address size for a bus represented in the tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address size for + * + * When the node has a valid #address-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 2, if the node has no #address-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #address-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_address_cells(const void *fdt, int nodeoffset); + +/** + * fdt_size_cells - retrieve address range size for a bus represented in the + * tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address range size for + * + * When the node has a valid #size-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 2, if the node has no #size-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #size-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_size_cells(const void *fdt, int nodeoffset); + + +/**********************************************************************/ +/* Write-in-place functions */ +/**********************************************************************/ + +/** + * fdt_setprop_inplace_namelen_partial - change a property's value, + * but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @namelen: number of characters of name to consider + * @idx: index of the property to change in the array + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * Identical to fdt_setprop_inplace(), but modifies the given property + * starting from the given index, and using only the first characters + * of the name. It is useful when you want to manipulate only one value of + * an array and you have a string that doesn't end with \0. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, + const char *name, int namelen, + uint32_t idx, const void *val, + int len); +#endif + +/** + * fdt_setprop_inplace - change a property's value, but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * fdt_setprop_inplace() replaces the value of a given property with + * the data in val, of length len. This function cannot change the + * size of a property, and so will only work if len is equal to the + * current length of the property. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if len is not equal to the property's current length + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#ifndef SWIG /* Not available in Python */ +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len); +#endif + +/** + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to replace the property with + * + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_nop_property - replace a property with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_nop_property() will replace a given property's representation + * in the blob with FDT_NOP tags, effectively removing it from the + * tree. + * + * This function will alter only the bytes in the blob which contain + * the property, and will not alter or move any other part of the + * tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_property(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_nop_node - replace a node (subtree) with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_nop_node() will replace a given node's representation in the + * blob, including all its subnodes, if any, with FDT_NOP tags, + * effectively removing it from the tree. + * + * This function will alter only the bytes in the blob which contain + * the node and its properties and subnodes, and will not alter or + * move any other part of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Sequential write functions */ +/**********************************************************************/ + +int fdt_create(void *buf, int bufsize); +int fdt_resize(void *fdt, void *buf, int bufsize); +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); +int fdt_finish_reservemap(void *fdt); +int fdt_begin_node(void *fdt, const char *name); +int fdt_property(void *fdt, const char *name, const void *val, int len); +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} + +#ifndef SWIG /* Not available in Python */ +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} +#endif + +/** + * fdt_property_placeholder - add a new property and return a ptr to its value + * + * @fdt: pointer to the device tree blob + * @name: name of property to add + * @len: length of property value in bytes + * @valp: returns a pointer to where where the value should be placed + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_NOSPACE, standard meanings + */ +int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp); + +#define fdt_property_string(fdt, name, str) \ + fdt_property(fdt, name, str, strlen(str)+1) +int fdt_end_node(void *fdt); +int fdt_finish(void *fdt); + +/**********************************************************************/ +/* Read-write functions */ +/**********************************************************************/ + +int fdt_create_empty_tree(void *buf, int bufsize); +int fdt_open_into(const void *fdt, void *buf, int bufsize); +int fdt_pack(void *fdt); + +/** + * fdt_add_mem_rsv - add one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: 64-bit values (native endian) + * + * Adds a reserve map entry to the given blob reserving a region at + * address address of length size. + * + * This function will insert data into the reserve map and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new reservation entry + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); + +/** + * fdt_del_mem_rsv - remove a memory reserve map entry + * @fdt: pointer to the device tree blob + * @n: entry to remove + * + * fdt_del_mem_rsv() removes the n-th memory reserve map entry from + * the blob. + * + * This function will delete data from the reservation table and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there + * are less than n+1 reserve map entries) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_mem_rsv(void *fdt, int n); + +/** + * fdt_set_name - change the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * @name: name to give the node + * + * fdt_set_name() replaces the name (including unit address, if any) + * of the given node with the given string. NOTE: this function can't + * efficiently check if the new name is unique amongst the given + * node's siblings; results are undefined if this function is invoked + * with a name equal to one of the given node's siblings. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob + * to contain the new name + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_set_name(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_setprop - create or change a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_setprop() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_placeholder - allocate space for a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @len: length of the property value + * @prop_data: return pointer to property data + * + * fdt_setprop_placeholer() allocates the named property in the given node. + * If the property exists it is resized. In either case a pointer to the + * property data is returned. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name, + int len, void **prop_data); + +/** + * fdt_setprop_u32 - set a property to a 32-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) + * + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_setprop_string - set a property to a string value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value for the property + * + * fdt_setprop_string() sets the value of the named property in the + * given node to the given string value (using the length of the + * string to determine the new length of the property), or creates a + * new property with that value if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_string(fdt, nodeoffset, name, str) \ + fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + + +/** + * fdt_setprop_empty - set a property to an empty value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * + * fdt_setprop_empty() sets the value of the named property in the + * given node to an empty (zero length) value, or creates a new empty + * property if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_empty(fdt, nodeoffset, name) \ + fdt_setprop((fdt), (nodeoffset), (name), NULL, 0) + +/** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_u32 - append a 32-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_delprop - delete a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_del_property() will delete the given property. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_delprop(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_add_subnode_namelen - creates a new node based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_add_subnode(), but use only the first namelen + * characters of name as the name of the new node. This is useful for + * creating subnodes based on a portion of a larger string, such as a + * full path. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen); +#endif + +/** + * fdt_add_subnode - creates a new node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_add_subnode() creates a new node as a subnode of the node at + * structure block offset parentoffset, with the given name (which + * should include the unit address, if any). + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + + * returns: + * structure block offset of the created nodeequested subnode (>=0), on + * success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE + * tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * fdt_del_node - delete a node (subtree) + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_del_node() will remove the given node, including all its + * subnodes if any, from the blob. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_node(void *fdt, int nodeoffset); + +/** + * fdt_overlay_apply - Applies a DT overlay on a base DT + * @fdt: pointer to the base device tree blob + * @fdto: pointer to the device tree overlay blob + * + * fdt_overlay_apply() will apply the given device tree overlay on the + * given base device tree. + * + * Expect the base device tree to be modified, even if the function + * returns an error. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there's not enough space in the base device tree + * -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or + * properties in the base DT + * -FDT_ERR_BADPHANDLE, + * -FDT_ERR_BADOVERLAY, + * -FDT_ERR_NOPHANDLES, + * -FDT_ERR_INTERNAL, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADOFFSET, + * -FDT_ERR_BADPATH, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_overlay_apply(void *fdt, void *fdto); + +/**********************************************************************/ +/* Debugging / informational functions */ +/**********************************************************************/ + +const char *fdt_strerror(int errval); + +#endif /* LIBFDT_H */ diff --git a/board/novatek/ns02501/loader/Include/fdt/libfdt_env.h b/board/novatek/ns02501/loader/Include/fdt/libfdt_env.h new file mode 100755 index 000000000000..69b04322fcb0 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/fdt/libfdt_env.h @@ -0,0 +1,178 @@ +#ifndef LIBFDT_ENV_H +#define LIBFDT_ENV_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +//#include +#include "compiler.h" + +#ifdef __KERNEL__ +#include +#include +#define strtoul simple_strtoul +#else +//#include +#include +#include +#include +#endif + +#include +#define memcpy utl_memcpy +#define memset utl_memset + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +typedef __u8 uint8_t; +typedef __u16 uint16_t; +typedef __u32 uint32_t; +typedef __s32 int32_t; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __u64 uint64_t; +typedef __u64 u_int64_t; +typedef __s64 int64_t; +#endif + + +#ifdef __CHECKER__ +#define FDT_FORCE __attribute__((force)) +#define FDT_BITWISE __attribute__((bitwise)) +#else +#define FDT_FORCE +#define FDT_BITWISE +#endif + +typedef uint16_t FDT_BITWISE fdt16_t; +typedef uint32_t FDT_BITWISE fdt32_t; +typedef uint64_t FDT_BITWISE fdt64_t; + +#define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n]) +#define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1)) +#define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \ + (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3)) +#define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \ + (EXTRACT_BYTE(x, 2) << 40) | (EXTRACT_BYTE(x, 3) << 32) | \ + (EXTRACT_BYTE(x, 4) << 24) | (EXTRACT_BYTE(x, 5) << 16) | \ + (EXTRACT_BYTE(x, 6) << 8) | EXTRACT_BYTE(x, 7)) + +static inline uint16_t fdt16_to_cpu(fdt16_t x) +{ + return (FDT_FORCE uint16_t)CPU_TO_FDT16(x); +} +static inline fdt16_t cpu_to_fdt16(uint16_t x) +{ + return (FDT_FORCE fdt16_t)CPU_TO_FDT16(x); +} + +static inline uint32_t fdt32_to_cpu(fdt32_t x) +{ + return (FDT_FORCE uint32_t)CPU_TO_FDT32(x); +} +static inline fdt32_t cpu_to_fdt32(uint32_t x) +{ + return (FDT_FORCE fdt32_t)CPU_TO_FDT32(x); +} + +static inline uint64_t fdt64_to_cpu(fdt64_t x) +{ + return (FDT_FORCE uint64_t)CPU_TO_FDT64(x); +} +static inline fdt64_t cpu_to_fdt64(uint64_t x) +{ + return (FDT_FORCE fdt64_t)CPU_TO_FDT64(x); +} +#undef CPU_TO_FDT64 +#undef CPU_TO_FDT32 +#undef CPU_TO_FDT16 +#undef EXTRACT_BYTE + +#ifdef __APPLE__ +#include + +/* strnlen() is not available on Mac OS < 10.7 */ +# if !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < \ + MAC_OS_X_VERSION_10_7) + +#define strnlen fdt_strnlen + +/* + * fdt_strnlen: returns the length of a string or max_count - which ever is + * smallest. + * Input 1 string: the string whose size is to be determined + * Input 2 max_count: the maximum value returned by this function + * Output: length of the string or max_count (the smallest of the two) + */ +static inline size_t fdt_strnlen(const char *string, size_t max_count) +{ + const char *p = memchr(string, 0, max_count); + return p ? p - string : max_count; +} + +#endif /* !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < + MAC_OS_X_VERSION_10_7) */ + +#endif /* __APPLE__ */ + +#endif /* LIBFDT_ENV_H */ diff --git a/board/novatek/ns02501/loader/Include/fuart.h b/board/novatek/ns02501/loader/Include/fuart.h new file mode 100755 index 000000000000..471c20f58207 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/fuart.h @@ -0,0 +1,85 @@ +/** + Header file for UART + + This file is the header file for UART driver + + @file fuart.h + @ingroup mIIOUART + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + + +#ifndef _FUART_H +#define _FUART_H + +#include "constant.h" + +/** + @addtogroup mIIOUART +*/ +//@{ +#ifndef ENUM_DUMMY4WORD +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 +#endif + +typedef enum { + CONSOLE_UART0, + CONSOLE_UART1, + + ENUM_DUMMY4WORD(UART_CONSOLE_CH) +} UART_CONSOLE_CH; + + +typedef struct _CONSOLE { + void (*hook)(void); ///< start this object + void (*putc)(char c); ///< console input funciton pointer + unsigned char (*getc)(void); ///< console output function point +} CONSOLE_OBJ, *PCONSOLE_OBJ; + + + +/** + @name Put system UART string + + Print string to UART + + @param[in] m printed string +*/ +//@{ +#define uart_putSystemUARTStr(m) fLib_PutSerialStr(m) ///< Print string MACRO +//@} + +/** + @name Put system UART character + + Print character to UART + + @param[in] m printed character +*/ +//@{ +#define uart_putSystemUARTChar(m) fLib_PutSerialChar(m) ///< Print character MACRO +//@} + +extern void fLib_PutSerialChar(char Ch) __attribute__ ((section (".part1"))); +extern void fLib_PutSerialStr(char *Str) __attribute__ ((section (".part1"))); +extern void uart_openSystemUART(void); +extern void uart_openSystemUART2(void); + +extern void uart_getChar_polling(char * c); +extern void uart_chkChar(char * c); +extern void uart_getStr_polling(char * c); +extern void uart_getBinary(char *pcString, UINT32 BufferLen); + +void serial_init(void); +unsigned char serial_getc(void); +void serial_putc(char c); +void serial2_init(void); +unsigned char serial2_getc(void); +void serial2_putc(char c); +PCONSOLE_OBJ get_uart_object(UART_CONSOLE_CH uart_ch); + +//@} + +#endif diff --git a/board/novatek/ns02501/loader/Include/gic.h b/board/novatek/ns02501/loader/Include/gic.h new file mode 100755 index 000000000000..aaec4784afb6 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/gic.h @@ -0,0 +1,195 @@ + +#ifndef _ASM_ARMV8_GIC_H_ +#define _ASM_ARMV8_GIC_H_ +//#include "FLibARM.h" +#define UART_INTID 43 + + + +#define GIC_UART_INTID (UART_INTID + 32) +#if 0 +/* + * Distributor layout + */ +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_IGROUP 0x0080 +#define GICD_ISENABLE 0x0100 +#define GICD_ICENABLE 0x0180 +#define GICD_ISPEND 0x0200 +#define GICD_ICPEND 0x0280 +#define GICD_ISACTIVE 0x0300 +#define GICD_ICACTIVE 0x0380 +#define GICD_IPRIORITY 0x0400 +#define GICD_ITARGETS 0x0800 +#define GICD_ICFG 0x0c00 +#define GICD_PPISR 0x0d00 +#define GICD_SPISR 0x0d04 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGI 0x0f10 +#define GICD_SPENDSGI 0x0f20 +#define GICD_PIDR4 0x0fd0 +#define GICD_PIDR5 0x0fd4 +#define GICD_PIDR6 0x0fd8 +#define GICD_PIDR7 0x0fdc +#define GICD_PIDR0 0x0fe0 +#define GICD_PIDR1 0x0fe4 +#define GICD_PIDR2 0x0fe8 +#define GICD_PIDR3 0x0fec +#define GICD_CIDR0 0x0ff0 +#define GICD_CIDR1 0x0ff4 +#define GICD_CIDR2 0x0ff8 +#define GICD_CIDR3 0x0ffc + +/* + * CPU Interface layout + */ +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000c +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APR0 0x00d0 +#define GICC_NSAPR0 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 +#endif + +#define MAX_SPIS 480 + +#define MAX_PPIS 14 +#define MAX_SGIS 16 + +#define MIN_SGI_ID 0 +#define MIN_PPI_ID 16 +#define MIN_SPI_ID 32 + +#define GRP0 0 +#define GRP1 1 + +#define _GICD_ 0x1000 +#define _GICC_ 0x2000 +#define _GICH_ 0x4000 +#define _GICV_ 0x6000 + +#define GIC_PRI_MASK 0xff +#define GIC_HIGHEST_SEC_PRIORITY 0 +#define GIC_LOWEST_SEC_PRIORITY 127 +#define GIC_HIGHEST_NS_PRIORITY 128 +#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ +#define GIC_SPURIOUS_INTERRUPT 1023 +#define GIC_TARGET_CPU_MASK 0xff + +/* Distributor interface definitions */ +#define GICD_CTLR _GICD_ + 0x0 +#define GICD_TYPER _GICD_ + 0x4 +#define GICD_IGROUPR _GICD_ + 0x80 +#define GICD_ISENABLER _GICD_ + 0x100 +#define GICD_ICENABLER _GICD_ + 0x180 +#define GICD_ISPENDR _GICD_ + 0x200 +#define GICD_ICPENDR _GICD_ + 0x280 +#define GICD_ISACTIVER _GICD_ + 0x300 +#define GICD_ICACTIVER _GICD_ + 0x380 +#define GICD_IPRIORITYR _GICD_ + 0x400 +#define GICD_ITARGETSR _GICD_ + 0x800 +#define GICD_ICFGR _GICD_ + 0xC00 +#define GICD_SGIR _GICD_ + 0xF00 +#define GICD_CPENDSGIR _GICD_ + 0xF10 +#define GICD_SPENDSGIR _GICD_ + 0xF20 + +#define IGROUPR_SHIFT 5 +#define ISENABLER_SHIFT 5 +#define ICENABLER_SHIFT ISENABLER_SHIFT +#define ISPENDR_SHIFT 5 +#define ICPENDR_SHIFT ISPENDR_SHIFT +#define ISACTIVER_SHIFT 5 +#define ICACTIVER_SHIFT ISACTIVER_SHIFT +#define IPRIORITYR_SHIFT 2 +#define ITARGETSR_SHIFT 2 +#define ICFGR_SHIFT 4 +#define CPENDSGIR_SHIFT 2 +#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT + +/* GICD_TYPER bit definitions */ +#define IT_LINES_NO_MASK 0x1f + +/* GICD_ICFGR bit definitions */ +#define LEVEL_SENSITIVE 0x0 +#define TRIGGER_SENSITIVE 0x1 + +/* Physical CPU Interface registers */ +#define GICC_CTLR _GICC_ + 0x0 +#define GICC_PMR _GICC_ + 0x4 +#define GICC_BPR _GICC_ + 0x8 +#define GICC_IAR _GICC_ + 0xC +#define GICC_EOIR _GICC_ + 0x10 +#define GICC_RPR _GICC_ + 0x14 +#define GICC_HPPIR _GICC_ + 0x18 +#define GICC_AHPPIR _GICC_ + 0x28 +#define GICC_IIDR _GICC_ + 0xFC +#define GICC_DIR _GICC_ + 0x1000 +#define GICC_PRIODROP _GICC_ + GICC_EOIR + +/* GICC_CTLR bit definitions */ +#define EOI_MODE_NS (1 << 10) +#define EOI_MODE_S (1 << 9) +#define IRQ_BYP_DIS_GRP1 (1 << 8) +#define FIQ_BYP_DIS_GRP1 (1 << 7) +#define IRQ_BYP_DIS_GRP0 (1 << 6) +#define FIQ_BYP_DIS_GRP0 (1 << 5) +#define CBPR (1 << 4) +#define FIQ_EN (1 << 3) +#define ACK_CTL (1 << 2) +#define ENABLE_GRP1 (1 << 1) +#define ENABLE_GRP0 (1 << 0) + +/* GICC_IIDR bit masks and shifts */ +#define GICC_IIDR_PID_SHIFT 20 +#define GICC_IIDR_ARCH_SHIFT 16 +#define GICC_IIDR_REV_SHIFT 12 +#define GICC_IIDR_IMP_SHIFT 0 + +#define GICC_IIDR_PID_MASK 0xfff +#define GICC_IIDR_ARCH_MASK 0xf +#define GICC_IIDR_REV_MASK 0xf +#define GICC_IIDR_IMP_MASK 0xfff + +/* HYP view virtual CPU Interface registers */ +#define GICH_CTL 0x0 +#define GICH_VTR 0x4 +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_APR0 0xF0 +#define GICH_LR_BASE 0x100 + +/* Virtual CPU Interface registers */ +#define GICV_CTL 0x0 +#define GICV_PRIMASK 0x4 +#define GICV_BP 0x8 +#define GICV_INTACK 0xC +#define GICV_EOI 0x10 +#define GICV_RUNNINGPRI 0x14 +#define GICV_HIGHESTPEND 0x18 +#define GICV_DEACTIVATE 0x1000 + +extern void nvt_enable_irq(int number); +extern void nvt_disable_irq(int number); +extern void arm_gic_cpuif_setup(void); +extern void arm_gic_distif_setup(void); +extern void gicd_write_igroupr(UINT32 id, UINT32 val); +extern void gicd_write_ipriorityr(UINT32 id, UINT32 val); + +extern UINT32 gicc_get_IAR(void); +extern void gicc_set_EOIR(UINT32 val); + + + + +#endif /* _ASM_ARMV8_GIC_H_ */ diff --git a/board/novatek/ns02501/loader/Include/global.h b/board/novatek/ns02501/loader/Include/global.h new file mode 100755 index 000000000000..e993985303ca --- /dev/null +++ b/board/novatek/ns02501/loader/Include/global.h @@ -0,0 +1,73 @@ +/** + Global utility header file + + Global utility header file + + @file global.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef _GLOBAL_H +#define _GLOBAL_H + +#include "constant.h" + +#define BOOT_SOURCE_SPI 0x00 +#define BOOT_SOURCE_CARD 0x01 +#define BOOT_SOURCE_SPI_NAND_2K 0x02 +#define BOOT_SOURCE_SPI_NAND_BCH_2K 0x03 +#define BOOT_SOURCE_ETHERNET 0x04 +#define BOOT_SOURCE_USB 0x05 +#define BOOT_SOURCE_SPI_NAND_4K 0x06 +#define BOOT_SOURCE_RESERVED 0x07 +#define BOOT_SOURCE_EMMC_4BIT 0x08 +#define BOOT_SOURCE_EMMC_8BIT 0x09 +#define BOOT_SOURCE_SPI_NAND_BCH_4K 0x0A +#define BOOT_SOURCE_USB_FULL 0x0B +#define BOOT_SOURCE_UART 0x0C + +#define BOOT_SOURCE_MSK 0x0F + +// rom auto boot - current boot src +#define ROM_GetCurrBS() *(UINT32*)(0xF07D2000) + +#define CHIPVER_A 0x0 + +/** + @addtogroup mISYSUtil +*/ +//@{ + +extern UINT32 bitCount(UINT32 data); +extern void UTL_setDrvTmpBufferAddress(UINT32 addr); +extern UINT32 UTL_getDrvTmpBufferAddress(void); +extern char* Dec2HexStr(UINT32 data); +//extern void PrintDec2Hex(UINT32 data) __attribute__ ((section (".part1"))); +extern void rom_Dec2HexStr(UINT32 data) __attribute__ ((section (".part1"))); +#define PrintDec2Hex(m) rom_Dec2HexStr(m) +extern char* Dec2HexStr2Bytes(UINT32 data); +extern void PrintDec2HexStr2Bytes(UINT32 data) __attribute__ ((section (".part1"))); +extern UINT32 DecStr2Int(char* str); +extern BOOL UTL_canUpdateSecKey(void); +extern BOOL utl_is_sram_fw(UINT32 fw_addr); +extern void utl_test_checksum(UINT32 addr, UINT32 size); +extern void utl_dram_protect_enable(UINT32 addr, UINT32 size); +extern void utl_dram_protect_disable(void); +extern UINT32 utl_dram_protect_check(void); +extern UINT32 utl_get_bootsrc(void); +extern UINT32 utl_get_chipversion(void); + +#if (_ROM_PUBLIC_API_ == 1) +extern void rom_debug_msg(char* str); +extern void rom_debug_msg_var(char *str, int var); +extern void rom_Dec2HexStr(UINT32 data); +extern int rom_public_api_available(void); + +#endif +extern void load_dram_scan(UINT32 addr, UINT32 size) __attribute__ ((section (".dram_text"))); +extern void timer_delay(UINT32 US) __attribute__ ((section (".part1"))); + +//@} + +#endif diff --git a/board/novatek/ns02501/loader/Include/limits.h b/board/novatek/ns02501/loader/Include/limits.h new file mode 100755 index 000000000000..1def5890ed05 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/limits.h @@ -0,0 +1,31 @@ + + +#ifndef __NVT_LIBC_LIMITS_H +#define __NVT_LIBC_LIMITS_H + +#define CHAR_BIT 8 /* number of bits in a char */ +#define SCHAR_MIN (-128) /* minimum signed char value */ +#define SCHAR_MAX 127 /* maximum signed char value */ +#define UCHAR_MAX 0xff /* maximum unsigned char value */ + +#ifndef _CHAR_UNSIGNED +#define CHAR_MIN SCHAR_MIN /* mimimum char value */ +#define CHAR_MAX SCHAR_MAX /* maximum char value */ +#else +#define CHAR_MIN 0 +#define CHAR_MAX UCHAR_MAX +#endif /* _CHAR_UNSIGNED */ + +#define MB_LEN_MAX 2 /* max. # bytes in multibyte char */ +#define SHRT_MIN (-32768) /* minimum (signed) short value */ +#define SHRT_MAX 32767 /* maximum (signed) short value */ +#define USHRT_MAX 0xffff /* maximum unsigned short value */ +#define INT_MIN (-2147483647 - 1) /* minimum (signed) int value */ +#define INT_MAX 2147483647 /* maximum (signed) int value */ +#define UINT_MAX 0xffffffff /* maximum unsigned int value */ +#define LONG_MIN (-2147483647L - 1) /* minimum (signed) long value */ +#define LONG_MAX 2147483647L /* maximum (signed) long value */ +#define ULONG_MAX 0xffffffffUL /* maximum unsigned long value */ + +#endif + diff --git a/board/novatek/ns02501/loader/Include/loader.h b/board/novatek/ns02501/loader/Include/loader.h new file mode 100755 index 000000000000..a10a43b5a7ec --- /dev/null +++ b/board/novatek/ns02501/loader/Include/loader.h @@ -0,0 +1,83 @@ +/** + Global loader header file + + Global loader header file + + @file loader.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef _LOADER_H +#define _LOADER_H + +#include "constant.h" +#include "StorageDef.h" + +/** + @name Special key detect CallBack + + Special key detect Prototype + + Project layer can detect special key in this callback. + If callback returns TRUE, loader will try to find files on SD card. + + @return + - @b TRUE: special key is pressed + - @b FALSE: special key is NOT pressed +*/ +//@{ +typedef BOOL (*LDR_SPECIAL_KEY_CB)(void); +//@} + +/** + @name Card detect CallBack + + Card detect Prototype + + Project layer can detect SD card existence in this callback. + If callback returns TRUE, loader will consider SD is plugged + + @return + - @b TRUE: SD exist + - @b FALSE: SD NOT exist +*/ +//@{ +typedef BOOL (*LDR_CARD_DETECT_CB)(void); +//@} +/** + @name Recovery Trigger CallBack + + Recovery trigger Prototype + + Project layer can detect if the recovery flow should started. + If callback returns TRUE, recovery flow will start. + + @return + - @b TRUE: Recovery flow is triggered. + - @b FALSE: Recovery flow is NOT triggered. +*/ +//@{ +typedef BOOL (*LDR_RECOVERY_TRIGGER_CB)(void); +//@} + +typedef enum _STORAGEINT { + STORAGEINT_UNKNOWN, + STORAGEINT_SPI_NAND, + STORAGEINT_SPI_NOR, + STORAGEINT_EMMC, +} STORAGEINT; + +extern void loader_setUpdateFwName(char* fileName); +extern void loader_setUpdateLdrName(char* fileName); +extern void loader_setRunFwName(char* fileName); +extern void loader_setRecoveryFwName(char *fileName); +extern void loader_setRecoveryPartitionID(UINT32 partition_id); +extern void loader_setVersion(UINT32 version); +extern void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj); +extern void loader_installSpecialKeyCB(LDR_SPECIAL_KEY_CB callback); +extern void loader_installCardDetectCB(LDR_CARD_DETECT_CB callback); +extern void loader_installRecoveryTriggerCB(LDR_RECOVERY_TRIGGER_CB callback); + +#endif + diff --git a/board/novatek/ns02501/loader/Include/lz.h b/board/novatek/ns02501/loader/Include/lz.h new file mode 100755 index 000000000000..cc4e45a6b318 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/lz.h @@ -0,0 +1,36 @@ +/** + Decompress library header file + + Decompress library header file + + @file lz.h + @ingroup mISYSUtil + @note Nothing +*/ +#ifndef __NVT_LZ_DEF__ +#define __NVT_LZ_DEF__ + +#include "constant.h" + +/** + @addtogroup mISYSUtil +*/ +//@{ +#if (_GZIP_ENABLE_API_ == 1) + +#endif +extern unsigned int GZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize)__attribute__ ((section (".part1"))); +//#else +#if (_ROM_PUBLIC_API_ == 1) +#define LZ_Un_compress(a,b,c) rom_LZ_Uncompress(a,b,c) +extern unsigned int rom_LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize)__attribute__ ((section (".part1"))); +extern unsigned int LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize); +#else +extern unsigned int LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize)__attribute__ ((section (".part1"))); +#define LZ_Un_compress(a,b,c) LZ_Uncompress(a,b,c) +#endif +//extern void LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize) __attribute__ ((section (".part1"), far)); + +//@} +//#endif +#endif diff --git a/board/novatek/ns02501/loader/Include/modelext/bin_info.h b/board/novatek/ns02501/loader/Include/modelext/bin_info.h new file mode 100755 index 000000000000..cfae0d5de444 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/modelext/bin_info.h @@ -0,0 +1,209 @@ +/** + Bin File Information + + Bin file layout + + ----------------------------------------------------- + HEADINFO 0x00 ~ 0x80 = 128 bytes = 32 WORDS + ----------------------------------------------------- + + EXCEPTION_TABLE: 0x180 ~ 0x200 = 128 bytes = 32 WORDS (see exception_MIPS.s) + + ----------------------------------------------------- + + VECTOR_TABLE: 0x200 ~ 0x2f0 = 240 bytes = 60 WORDS (see isr_MIPS.s) + + ----------------------------------------------------- + + Code Info: 0x2f0 ~ 0x400 = 272 bytes = 68 WORDS (see CodeInfo_MIPS.s) + + ----------------------------------------------------- + + Code Entry: 0x400 (see Loader_MIPS.s) + + : + + PART-1 + PART-2 + PART-3 + : + PART-N + + ----------------------------------------------------- + + @file bin_info.h + @ingroup mMODELEXT + @note THESE STRUCTS ARE VERY VERY IMPORTANT FORMAT DEFINITION OF SYSTEM, + DO NOT MODIFY ANY ITEM OR INSERT/REMOVE ANY ITEM OF THESE STRUCTS!!! + + Copyright Novatek Microelectronics Corp. 2011. All rights reserved. +*/ +#ifndef _BINI_NFO_H +#define _BINI_NFO_H + +#define BIN_INFO_VER 0x19062115 ///< YYYY/MM/DD HH + +#define BIN_INFO_OFFSET_RTOS 0x00000200 ///< rtos HEADINFO.o attached to this offset +#define BIN_INFO_OFFSET_UBOOT 0x00000300 ///< uboot HEADINFO.o attached to this +#define BIN_INFO_OFFSET_NUTTX 0x00000100 ///< nuttx +#define BIN_INFO_OFFSET_TEEOS 0x00000100 ///< teeos +#define BIN_INFO_OFFSET_BL31 0x00000300 ///< bl31 +#define BIN_INFO_OFFSET_8051 0x00000300 ///< 8051 + +//Ep: Encryption Program (CheckSum version) +//Epcrc: Encryption Program (CRC version) +//Bfc: Bin File Compress +//Ld: Loader +//Fw: Firmware + +//Head control flag for HEADINFO.BinCtrl +#define HDCF_LZCOMPRESS_EN 0x0000001 ///< BIT 0.compressed enable (0=no,1=yes) + +//Head control flag for HEADINFO.BinCtrl (BL31) +#define BINCTRL_BL31_OS_AMP 0x00000001UL ///< indicate os multi-core heterogeneous + +/** + @name Ld control flag for LDINFO.LdCtrl +*/ +//@{ +#define BOOT_FLAG_PARTLOAD_EN 0x0000001 ///< BIT 0.PARTLOAD_EN (0=no,1=yes) +//@} + +/** + * @brief for encrypt_sign_tool bitwise to HEADINFO::BinCtrl + */ +#define SIGN_BINCTRL_LIMITED_SIZE 0x1 //indicate if sha_limited_size is enabled +#define SIGN_BINCTRL_NO_ENCRYPTIONDATA 0x2 //indicate if signature only without encrypted context + +//HEADINFO::Resv field definition +typedef enum _HEADINFO_RESV_IDX_{ + HEADINFO_RESV_IDX_FDT_ADDR = 0, + HEADINFO_RESV_IDX_SHM_ADDR = 1, + HEADINFO_RESV_IDX_BOOT_FLAG = 2, + HEADINFO_RESV_IDX_DRAM_SIZE = 3, + HEADINFO_RESV_IDX_COUNTS = 19, +} HEADINFO_RESV_IDX; + +//HEADINFO::Resv field definition for teeos +typedef enum HEADINFO_TEEOS_RESV_IDX{ + HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR = 0, + HEADINFO_TEEOS_RESV_IDX_UBOOT_ADDR = 1, //< write by loader + HEADINFO_TEEOS_RESV_IDX_KERNEL_ENTRY_ADDR = 2, //< write by loader + HEADINFO_TEEOS_RESV_IDX_KERNEL_FDT_ADDR = 3, //< write by loader + HEADINFO_TEEOS_RESV_IDX_COUNTS = 19, +} HEADINFO_TEEOS_RESV_IDX; + +//HEADINFO::Resv field definition for bl31 +typedef enum HEADINFO_BL31_RESV_IDX{ + HEADINFO_BL31_RESV_IDX_LOAD_ADDR = 0, + HEADINFO_BL31_RESV_IDX_UBOOT_ADDR = 1, //< write by loader + HEADINFO_BL31_RESV_IDX_TEEOS_ADDR = 2, //< write by loader + HEADINFO_BL31_RESV_IDX_RTOS_ADDR = 3, //< write by loader + HEADINFO_BL31_RESV_IDX_COUNTS = 19, +} HEADINFO_BL31_RESV_IDX; + +/** + * @brief HEADINFO::Resv1 for encrypt_sign_tool + */ +typedef enum HEADINFO_SIGN_RESV_IDX{ + HEADINFO_SIGN_RESV_IDX_LIMITED_SIZE = 0, //value to sha_limited_size + HEADINFO_SIGN_RESV_IDX_COUNTS = 19, +} HEADINFO_SIGN_RESV_IDX; + +/** + Header information + + 0x00 ~ 0x80 = 128 bytes = 32 WORDS +*/ +typedef struct HEADINFO { + unsigned int CodeEntry; ///< [0x00] fw CODE entry (4) ----- r by Ld + unsigned int Resv1[HEADINFO_RESV_IDX_COUNTS]; + ///< [0x04~0x50] reserved (4*19) -- reserved, its mem value will filled by Ld + ///< Resv1[HEADINFO_RESV_IDX_FDT_ADDR]: store fdt addr for rtos + ///< Resv1[HEADINFO_RESV_IDX_SHM_ADDR]: store shm addr for rtos + ///< Resv1[HEADINFO_RESV_IDX_BOOT_FLAG]: boot flag for rtos + ///< Resv1[HEADINFO_RESV_IDX_DRAM_SIZE]: Total DRAM size for rtos + char BinInfo_1[8]; ///< [0x50~0x58] CHIP-NAME (8) ---- r by Ep + char BinInfo_2[8]; ///< [0x58~0x60] SDK version (8) + char BinInfo_3[8]; ///< [0x60~0x68] SDK releasedate (8) + unsigned int BinLength; ///< [0x68] Bin File Length (4) --- w by Ep/bfc + unsigned int Checksum; ///< [0x6c] Check Sum or CRC (4) ----- w by Ep/Epcrc + unsigned int CRCLenCheck; ///< [0x70~0x74] Length check for CRC (4) ----- w by Epcrc (total len ^ 0xAA55) + unsigned int ModelextAddr;///< [0x74~0x78] where modelext data is. w by Ld / u-boot + unsigned int BinCtrl; ///< [0x78~0x7C] Bin flag (4) --- w by bfc + ///< BIT 0.compressed enable (w by bfc) + ///< BIT 1.Linux SMP enable (1: SMP/VOS, 0: Dual OS) + unsigned int CRCBinaryTag;///< [0x7C~0x80] Binary Tag for CRC (4) ----- w by Epcrc (0xAA55 + "NT") +} +HEADINFO; + +typedef struct HEADINFO64 { + unsigned long long CodeEntry; ///< [0x00] fw CODE entry (4) ----- r by Ld + unsigned long long Resv1[HEADINFO_RESV_IDX_COUNTS]; + ///< [0x08~0xA0] reserved (4*19) -- reserved, its mem value will filled by Ld + ///< Resv1[HEADINFO_RESV_IDX_FDT_ADDR]: store fdt addr for rtos + ///< Resv1[HEADINFO_RESV_IDX_SHM_ADDR]: store shm addr for rtos + ///< Resv1[HEADINFO_RESV_IDX_BOOT_FLAG]: boot flag for rtos + ///< Resv1[HEADINFO_RESV_IDX_DRAM_SIZE]: Total DRAM size for rtos + char BinInfo_1[8]; ///< [0xA0~0xA8] CHIP-NAME (8) ---- r by Ep + char BinInfo_2[8]; ///< [0xA8~0xB0] SDK version (8) + char BinInfo_3[8]; ///< [0xB0~0xB8] SDK releasedate (8) + unsigned int BinLength; ///< [0xB8] Bin File Length (4) --- w by Ep/bfc + unsigned int Checksum; ///< [0xBc] Check Sum or CRC (4) ----- w by Ep/Epcrc + unsigned int CRCLenCheck; ///< [0xC0~0xC4] Length check for CRC (4) ----- w by Epcrc (total len ^ 0xAA55) + unsigned int ModelextAddr;///< [0xC4~0xC8] where modelext data is. w by Ld / u-boot + unsigned int BinCtrl; ///< [0xC8~0xCC] Bin flag (4) --- w by bfc + ///< BIT 0.compressed enable (w by bfc) + ///< BIT 1.Linux SMP enable (1: SMP/VOS, 0: Dual OS) + unsigned int CRCBinaryTag;///< [0xCC~0xD0] Binary Tag for CRC (4) ----- w by Epcrc (0xAA55 + "NT") +} +HEADINFO64; + +STATIC_ASSERT(sizeof(HEADINFO) == 128); + + +/** + Binary file information + + 0x00 ~ 0x180 = 384 bytes = 96 WORDS +*/ +typedef struct _BININFO { + HEADINFO head; ///< 0x00 ~ 0x80 = 128 bytes = 32 WORDS, header information + unsigned int Resv[64]; ///< 0x80 ~ 0x180 = 384 bytes = 64 WORDS, reserved information + ///< Resv[0]: signature size, for sha is made for part of content +} +BININFO; + +STATIC_ASSERT(sizeof(BININFO) == 384); + +/////////////////////////////////////////////////////////////////////////////// +//Code Info: 0x2f0 ~ 0x400 +#if defined(__aarch64__) +#define ZI_SECTION_OFFSET (0x3f0+0x10) // ZI area information of starting offset +#define CODE_SECTION_OFFSET (0x3f0+0x20) ///< code section information of starting offset +#else +#define ZI_SECTION_OFFSET (0x3f0+0x10) ///< ZI area information of starting offset +#define CODE_SECTION_OFFSET (0x3f0+0x18) ///< code section information of starting offset +#endif +#define CODE_SECTION_OFFSET64 (0x3f0+0x20) ///< on 32 bit loader to load rtos-64 +/* +bfc syntex + +bfc.exe p1 p2 p3 p4 p5 p6 p7 p8 p9 + +p1: compress/decompress +p2: compress method +p3: input file name +p4: output file name +p5: partial load flag ('1' means partial load) +p6: partial load file start [locate offset of bin file] +p7: output binary file length [locate offset of bin file] +p8: partial compress flag [locate offset of bin file] +p9: NAND block size (option) + +NOTE: p6~p9 must be hex format (0x****) + +@$(BFC) c lz $(BIN_R) tmp 1 0x310 0x68 0x78 $(EMBMEM_BLK_SIZE) +*/ + +#endif diff --git a/board/novatek/ns02501/loader/Include/modelext/dram_partition_info.h b/board/novatek/ns02501/loader/Include/modelext/dram_partition_info.h new file mode 100755 index 000000000000..887494dc2bae --- /dev/null +++ b/board/novatek/ns02501/loader/Include/modelext/dram_partition_info.h @@ -0,0 +1,58 @@ +#ifndef _DRAM_PARTITION_INFO_H +#define _DRAM_PARTITION_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#else +#include "nvt_type.h" +#endif + +/** + DRAM Partition + + This is common header used between firmware of uITRON, eCos, Linux, DSP + so !!!!!! DO NOT modify it !!!!!! +*/ + +#define DRAM_PARTITION_INFO_VER 0x17032309 ///< YYYY/MM/DD HH + +typedef struct _DRAM_PARTITION { + unsigned int fourcc; ///< FourCC DRAM + unsigned int info_size; ///< sizeof(CORE_INFO) + unsigned int dram_addr; ///< whole dram starting address + unsigned int dram_size; ///< whole dram size + unsigned int rev_addr; ///< reversed starting address + unsigned int rev_size; ///< reversed size + unsigned int fdt_addr; ///< ipc starting address + unsigned int fdt_size; ///< ipc size + unsigned int linux_addr;///< linux-kernel starting address + unsigned int linux_size;///< linux-kernel size + unsigned int uboot_addr;///< u-boot starting address + unsigned int uboot_size;///< u-boot size + unsigned int rtos_addr; ///< rtos starting address + unsigned int rtos_size; ///< rtos size + unsigned int dsp1_addr; ///< DSP1 starting address + unsigned int dsp1_size; ///< DSP1 size + unsigned int dsp2_addr; ///< ecos(na51023) / DSP2(na51000) starting address + unsigned int dsp2_size; ///< ecos(na51023) / DSP2(na51000) size + unsigned int loader_addr; ///< loader starting address + unsigned int loader_size; ///< loader size + unsigned int nuttx_addr; ///< nuttx starting address + unsigned int nuttx_size; ///< nuttx size + unsigned int teeos_addr; ///< teeos starting address + unsigned int teeos_size; ///< teeos size + unsigned int hdal1_addr; ///< hdal[0] starting address + unsigned int hdal1_size; ///< hdal[0] size + unsigned int hdal2_addr; ///< hdal[1] starting address for dram2 + unsigned int hdal2_size; ///< hdal[1] size for dram2 + unsigned int core2_entry1_addr; ///< for smp boot, cpu2 start at 0 then jump to core2_entry2 for addr 0 can be reuse. + unsigned int core2_entry1_size; ///< for smp boot, cpu2 start at 0 then jump to core2_entry2 for addr 0 can be reuse. + unsigned int core2_entry2_addr; ///< asm code to start smp + unsigned int core2_entry2_size; ///< asm code to start smp + unsigned int bl31_addr; ///< bl31 for secure boot + unsigned int bl31_size; ///< bl31 for secure boot + + +}DRAM_PARTITION; + +#endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Include/modelext/emb_partition_info.h b/board/novatek/ns02501/loader/Include/modelext/emb_partition_info.h new file mode 100755 index 000000000000..504222efc244 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/modelext/emb_partition_info.h @@ -0,0 +1,57 @@ +#ifndef _EMB_PARTITION_INFO_H +#define _EMB_PARTITION_INFO_H + +#define EMB_PARTITION_INFO_VER 0x16072117 ///< YYYY/MM/DD HH + +/** + Partition Infomation + This is common header used between firmware of uITRON, eCos, Linux, DSP + so !!!!!! DO NOT modify it !!!!!! +*/ + +#define EMB_PARTITION_INFO_COUNT 16 + +#define EMBTYPE_UNKNOWN 0x00 +#define EMBTYPE_LOADER 0x01 /* loader must always put in partition[0] */ +#define EMBTYPE_MODELEXT 0x02 /* modelext must always put in partition[1] */ +#define EMBTYPE_UITRON 0x03 +#define EMBTYPE_ECOS 0x04 +#define EMBTYPE_UBOOT 0x05 +#define EMBTYPE_LINUX 0x06 +#define EMBTYPE_DSP 0x07 +#define EMBTYPE_PSTORE 0x08 +#define EMBTYPE_FAT 0x09 +#define EMBTYPE_EXFAT 0x0A +#define EMBTYPE_ROOTFS 0x0B +#define EMBTYPE_RAMFS 0x0C +#define EMBTYPE_UENV 0x0D /* u-boot environment data */ +#define EMBTYPE_MBR 0x0E /* for emmc partition, mbr always put in partition[0] instead of loader */ +#define EMBTYPE_NUTTX 0x0F +#define EMBTYPE_RTOS 0x10 +#define EMBTYPE_TEEOS 0x11 +#define EMBTYPE_BL31 0x12 + +/** + customer defined data partition format +*/ +#define EMBTYPE_USER0 0x80 +#define EMBTYPE_USER1 0x81 +#define EMBTYPE_USER2 0x82 +#define EMBTYPE_USER3 0x83 +#define EMBTYPE_USER4 0x84 +#define EMBTYPE_USER5 0x85 +#define EMBTYPE_USER6 0x86 +#define EMBTYPE_USER7 0x87 + + +/* for reason of compatiable linux, we use original type to decalre */ + +typedef struct _EMB_PARTITION { + unsigned short EmbType; /* EMBTYPE_ */ + unsigned short OrderIdx; /* Order index of the same EmbType based on '0' */ + unsigned long long PartitionOffset; /* Phyical offset of partition */ + unsigned long long PartitionSize; /* Size of this partition */ + unsigned long long ReversedSize; /* Reserved size for bad block */ +} EMB_PARTITION, *PEMB_PARTITION; + +#endif diff --git a/board/novatek/ns02501/loader/Include/modelext/gpio_info.h b/board/novatek/ns02501/loader/Include/modelext/gpio_info.h new file mode 100755 index 000000000000..22f3969102a8 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/modelext/gpio_info.h @@ -0,0 +1,42 @@ +/** + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. + + @file gpio_info.h + @ingroup mMODELEXT + + @brief Header file of IO config + This file is the header file of IO config + + @note Nothing. + @date 2016/06/24 +*/ + +/** \addtogroup mIPRJAPCommonIO */ +//@{ + +#ifndef _GPIO_INFO_H +#define _GPIO_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#else +#include "nvt_type.h" +#endif + +#define GPIO_INFO_VER 0x16062414 ///< YYYY/MM/DD HH + + +//-------------------------------------------------------------------- +// GPIO common +//-------------------------------------------------------------------- +typedef struct _GPIO_INIT_OBJ{ + UINT32 GpioPin; + UINT32 GpioDir; + UINT32 PadDir; + UINT32 PadPin; +} GPIO_INIT_OBJ,*PGPIO_INIT_OBJ; + +#endif + +//@} + diff --git a/board/novatek/ns02501/loader/Include/modelext/interrupt.h b/board/novatek/ns02501/loader/Include/modelext/interrupt.h new file mode 100755 index 000000000000..c48007907aeb --- /dev/null +++ b/board/novatek/ns02501/loader/Include/modelext/interrupt.h @@ -0,0 +1,764 @@ +/** + Header file for Interrupt module + + This file is the header file that define the API for Interrupt module. + + @file Interrupt.h + @ingroup mIDrvSys_Interrupt + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2010. All rights reserved. +*/ + +#ifndef _INTERRUPT_H +#define _INTERRUPT_H + +#if defined(__UITRON) +#include "Type.h" +#include "cc.h" +#else +#include "nvt_type.h" +#include "modelext/cc.h" +#define _ARM_GIC_USAGE_ ENABLE +#endif + +// Interrupt number <= 32 +//typedef UINT32 INT_PTN; +// Interrupt number > 32 +typedef UINT64 INT_PTN; + +/** + @addtogroup mIDrvSys_Interrupt +*/ +//@{ +#define INT_GIC_ID_DST_VER 0x16080216 + + +/** + Interrupt configuration identifier + + @note For int_setConfig() +*/ +typedef enum +{ + INT_CONFIG_ID_GIC_DESTINATION = 0, ///< Configured Interrupt exception destination to CPU/CPU2 + ///< @note + ///< Context is : + ///< - @b PINT_ID_GIC_DST : Point of destination table + + INT_CONFIG_ID_INTC_DESTINATION, ///< Configured Interrupt exception destination to DSP/DSP2 + ///< @note + ///< Context is : + ///< - @b PINT_ID_INTC_DST : Point of destination table + + + + ENUM_DUMMY4WORD(INT_CONFIG_ID) +} INT_CONFIG_ID; + +/** + Interrupt module ID + + Interrupt module ID for int_getIRQId() and int_getDummyId(). +*/ +#if(_ARM_GIC_USAGE_ == DISABLE) +#define INT_GIC_SPI_START_ID 0 +#else +#define INT_GIC_SPI_START_ID 32 +#endif + +typedef enum +{ + INT_ID_TIMER = INT_GIC_SPI_START_ID, + INT_ID_SIE, + INT_ID_SIE2, + INT_ID_SIE3, + + INT_ID_SIE4, + INT_ID_IPE, + INT_ID_IME, + INT_ID_DCE, + + INT_ID_IFE, + INT_ID_IFE2, + INT_ID_DIS, + INT_ID_FDE, + +// INT_ID_RDE, //Removed @ NT96680 + INT_ID_ETH_LPI, //Ethernet_LPI + INT_ID_RHE, + INT_ID_DRE, + INT_ID_DAI, //15 + + INT_ID_H26X, + INT_ID_JPEG, + INT_ID_GRAPHIC, + INT_ID_GRAPHIC2, + + INT_ID_AFFINE, + INT_ID_ISE, + INT_ID_TGE, + INT_ID_TSMUX, + + INT_ID_GPIO, + INT_ID_REMOTE, + INT_ID_PWM, + INT_ID_USB, + + INT_ID_USB3, + INT_ID_NAND, + INT_ID_SDIO, + INT_ID_SDIO2, //31 + + INT_ID_SDIO3, + INT_ID_DMA, + INT_ID_ETHERNET, + INT_ID_SPI, + + INT_ID_SPI2, + INT_ID_SPI3, + INT_ID_SPI4, +// INT_ID_SPI5, //Removed @ NT96680 + INT_ID_ETH_REV_MII, //Ethernet_RevMII + + INT_ID_SIF, + INT_ID_I2C, + INT_ID_I2C2, + INT_ID_UART, //43 + + INT_ID_UART2, + INT_ID_UART3, + INT_ID_UART4, + INT_ID_ADC, + + INT_ID_IDE, + INT_ID_IDE2, + INT_ID_DSI, + INT_ID_MI, //51 + + INT_ID_HDMI, +// INT_ID_VX1, //Removed @ NT96680 + INT_ID_DMA2, //New @ NT96680 + INT_ID_LVDS, + INT_ID_LVDS2, //55 + + INT_ID_RTC, + INT_ID_WDT, + INT_ID_CG, + INT_ID_CC, //59 + + INT_ID_I2C3, //60 +// New add @ NT96680 + INT_ID_SLVS_EC, + INT_ID_LVDS3, //share with HiSPi3/CSI3 + INT_ID_LVDS4, //share with HiSPi4/CSI4 + + INT_ID_LVDS5, //share with HiSPi5/CSI5 + INT_ID_LVDS6, //share with HiSPi6/CSI6 + INT_ID_LVDS7, //share with HiSPi7/CSI7 + INT_ID_LVDS8, //share with HiSPi8/CSI8 + + INT_ID_SIE5, + INT_ID_SIE6, + INT_ID_SIE7, + INT_ID_SIE8, + + INT_ID_IVE, + INT_ID_SVM, + INT_ID_SDE, + INT_ID_CNN, //75 + + INT_ID_DSP, + INT_ID_DSP2, + INT_ID_CANBUS, + INT_ID_CRYPTO, //79 + + INT_ID_COPY, + INT_ID_ROTATE, + INT_ID_I2C4, + INT_ID_I2C5, //83 + +// INT_ID_I2C6, +// INT_ID_I2C7, + INT_ID_DRTC, + INT_ID_ISE2, + INT_ID_TIMER2, + INT_ID_GPIO2, //87 + + INT_ID_PWM2, + INT_ID_CC2, //89 + INT_ID_SIF2, + + INT_ID_DSP_2, + INT_ID_DSP_2_2, + INT_ID_TSDEMUX, //93 + + INT_ID_CNT, + INT_ID_MAX = INT_ID_CNT - INT_GIC_SPI_START_ID, //94 + + + INT_ID_WFI = 229, + INT_ID_GIC_TOTAL = 256, + ENUM_DUMMY4WORD(INT_ID) +} INT_ID; + +typedef enum +{ + INT_TARGET_CORE0 = 1, + INT_TARGET_CORE1, + ENUM_DUMMY4WORD(INT_CORE_ID) +} INT_CORE_ID; + +/* + Interrupt module ID of GIC + + Indicate which core will configured as destination + + @note For DMA_WRITEPROT_ATTR +*/ + + +typedef union +{ + INT_PTN Reg[2]; + struct + { + //INT0 + UINT32 bInt_ID_TIMER:1; + UINT32 bInt_ID_SIE:1; + UINT32 bInt_ID_SIE2:1; + UINT32 bInt_ID_SIE3:1; + + UINT32 bInt_ID_SIE4:1; + UINT32 bInt_ID_IPE:1; + UINT32 bInt_ID_IME:1; + UINT32 bInt_ID_DCE:1; + + UINT32 bInt_ID_IFE:1; + UINT32 bInt_ID_IFE2:1; + UINT32 bInt_ID_DIS:1; + UINT32 bInt_ID_FDE:1; + +// UINT32 bInt_ID_RDE:1; + UINT32 bInt_ID_Ethernet_LPI:1; + UINT32 bInt_ID_RHE:1; + UINT32 bInt_ID_DRE:1; + UINT32 bInt_ID_DAI:1; + + + //INT16 + UINT32 bInt_ID_H264:1; + UINT32 bInt_ID_JPEG:1; + UINT32 bInt_ID_GRAPHIC:1; + UINT32 bInt_ID_GRAPHIC2:1; + + UINT32 bInt_ID_AFFINE:1; + UINT32 bInt_ID_ISE:1; + UINT32 bInt_ID_TGE:1; + UINT32 bInt_ID_TSMUX:1; + + UINT32 bInt_ID_GPIO:1; + UINT32 bInt_ID_REMOTE:1; + UINT32 bInt_ID_PWM:1; + UINT32 bInt_ID_USB:1; + + UINT32 bInt_ID_USB3:1; + UINT32 bInt_ID_NAND:1; + UINT32 bInt_ID_SDIO:1; + UINT32 bInt_ID_SDIO2:1; + + //INT32 + UINT32 bInt_ID_SDIO3:1; + UINT32 bInt_ID_DMA:1; + UINT32 bInt_ID_ETHERNET:1; + UINT32 bInt_ID_SPI:1; + + UINT32 bInt_ID_SPI2:1; + UINT32 bInt_ID_SPI3:1; + UINT32 bInt_ID_SPI4:1; + UINT32 bInt_ID_Ehternet_RevMII:1; +// UINT32 bInt_ID_SPI5:1; + + + UINT32 bInt_ID_SIF:1; + UINT32 bInt_ID_I2C:1; + UINT32 bInt_ID_I2C2:1; + UINT32 bInt_ID_UART:1; + + UINT32 bInt_ID_UART2:1; + UINT32 bInt_ID_UART3:1; + UINT32 bInt_ID_UART4:1; + UINT32 bInt_ID_ADC:1; + + //INT48 + UINT32 bInt_ID_IDE:1; + UINT32 bInt_ID_IDE2:1; + UINT32 bInt_ID_DSI:1; + UINT32 bInt_ID_MI:1; + + //INT52 + UINT32 bInt_ID_HDMI:1; +// UINT32 bInt_ID_VX1:1; + UINT32 bInt_ID_DMA2:1; + UINT32 bInt_ID_LVDS:1; // LVDS& HiSPI& CSI + UINT32 bInt_ID_LVDS2:1; //LVDS2&HiSPI2&CSI2 + + //INT56 + UINT32 bInt_ID_RTC:1; + UINT32 bInt_ID_WDT:1; + UINT32 bInt_ID_CG:1; + UINT32 bInt_ID_CC:1; + + //INT60 + UINT32 bInt_ID_I2C3:1; + UINT32 bInt_ID_SLVS_EC:1; + UINT32 bInt_ID_LVDS3:1; //LVDS3&HiSPI3&CSI3 + UINT32 bInt_ID_LVDS4:1; //LVDS4&HiSPI4&CSI4 + + //INT64 + UINT32 bInt_ID_LVDS5:1; //LVDS5&HiSPI5&CSI5 + UINT32 bInt_ID_LVDS6:1; //LVDS6&HiSPI6&CSI6 + UINT32 bInt_ID_LVDS7:1; //LVDS7&HiSPI7&CSI7 + UINT32 bInt_ID_LVDS8:1; //LVDS8&HiSPI8&CSI8 + + //INT68 + UINT32 bInt_ID_SIE5:1; + UINT32 bInt_ID_SIE6:1; + UINT32 bInt_ID_SIE7:1; + UINT32 bInt_ID_SIE8:1; + + //INT72 + UINT32 bInt_ID_IVE:1; + UINT32 bInt_ID_SVM:1; + UINT32 bInt_ID_SDE:1; + UINT32 bInt_ID_CNN:1; + + //INT76 + UINT32 bInt_ID_DSP:1; + UINT32 bInt_ID_DSP2:1; + UINT32 bInt_ID_CANBUS:1; + UINT32 bInt_ID_CRYPTO:1; + + //INT80 + UINT32 bInt_ID_HWCOPY:1; + UINT32 bInt_ID_ROTATE:1; + UINT32 bInt_ID_I2C4:1; + UINT32 bInt_ID_I2C5:1; + + //INT84 + UINT32 bInt_ID_I2C6:1; + UINT32 bInt_ID_I2C7:1; + UINT32 bInt_ID_TIMER2:1; //Timer to CA53 core2 + UINT32 bInt_ID_GPIO2:1; //GPIO to CA53 core2 + + //INT88 + UINT32 bInt_ID_PWM2:1; + UINT32 bInt_ID_CC2:1; + UINT32 bInt_ID_SIF2:1; //Timer to CA53 core2 + UINT32 bInt_ID_DSP_2:1; //?? + + //INT92 + UINT32 bInt_ID_DSP2_2:1; //?? + UINT32 bInt_ID_TMDEMUX:1; + UINT32 bReserved92:2; + //INT96 => 4 + UINT32 bReserved96:4; + //INT100=> 4 + UINT32 bReserved100:4; + //INT104=> 4 + UINT32 bReserved104:4; + //INT108=> 4 + UINT32 bReserved108:4; + //INT112=> 4 + UINT32 bReserved112:4; + //INT116=> 4 + UINT32 bReserved116:4; + //INT120=> 4 + UINT32 bReserved120:4; + //INT124=> 4 + UINT32 bReserved124:4; + }Bit; +} INT_GIC_ID_DST, *PINT_GIC_ID_DST; + +/* + Interrupt module ID of INTC + + Indicate which core will configured as destination + + @note For DMA_WRITEPROT_ATTR +*/ + + +typedef union +{ + INT_PTN Reg[2]; + struct + { + //INT0 + UINT32 bInt_ID_TIMER:1; + UINT32 bInt_ID_SIE:1; + UINT32 bInt_ID_SIE2:1; + UINT32 bInt_ID_SIE3:1; + + UINT32 bInt_ID_SIE4:1; + UINT32 bInt_ID_IPE:1; + UINT32 bInt_ID_IME:1; + UINT32 bInt_ID_DCE:1; + + UINT32 bInt_ID_IFE:1; + UINT32 bInt_ID_IFE2:1; + UINT32 bInt_ID_DIS:1; + UINT32 bInt_ID_FDE:1; + + //INT12 + UINT32 bReserved12:1; + UINT32 bInt_ID_RHE:1; + UINT32 bInt_ID_DRE:1; + UINT32 bInt_ID_DAI:1; + + + //INT16 + UINT32 bInt_ID_H264:1; + UINT32 bInt_ID_JPEG:1; + UINT32 bInt_ID_GRAPHIC:1; + UINT32 bInt_ID_GRAPHIC2:1; + + //INT20 + UINT32 bInt_ID_AFFINE:1; + UINT32 bInt_ID_ISE:1; + UINT32 bInt_ID_TGE:1; + UINT32 bInt_ID_TSMUX:1; + + UINT32 bInt_ID_GPIO:1; + UINT32 bInt_ID_REMOTE:1; + UINT32 bInt_ID_PWM:1; + UINT32 bInt_ID_USB:1; + + UINT32 bInt_ID_USB3:1; + UINT32 bInt_ID_NAND:1; + UINT32 bInt_ID_SDIO:1; + UINT32 bInt_ID_SDIO2:1; + + //INT32 + UINT32 bInt_ID_SDIO3:1; + UINT32 bInt_ID_DMA:1; + UINT32 bInt_ID_ETHERNET:1; + UINT32 bInt_ID_SPI:1; + + //INT36 + UINT32 bInt_ID_SPI2:1; + UINT32 bInt_ID_SPI3:1; + UINT32 bInt_ID_SPI4:1; + UINT32 bReserved39:1; +// UINT32 bInt_ID_SPI5:1; + + //INT40 + UINT32 bReserved40:1; + UINT32 bInt_ID_I2C:1; + UINT32 bInt_ID_I2C2:1; + UINT32 bInt_ID_UART:1; + + UINT32 bInt_ID_UART2:1; + UINT32 bInt_ID_UART3:1; + UINT32 bInt_ID_UART4:1; + UINT32 bInt_ID_ADC:1; + + //INT48 + UINT32 bInt_ID_IDE:1; + UINT32 bInt_ID_IDE2:1; + UINT32 bInt_ID_DSI:1; + UINT32 bInt_ID_MI:1; + + //INT52 + UINT32 bInt_ID_HDMI:1; +// UINT32 bInt_ID_VX1:1; + UINT32 bInt_ID_DMA2:1; + UINT32 bInt_ID_LVDS:1; // LVDS& HiSPI& CSI + UINT32 bInt_ID_LVDS2:1; //LVDS2&HiSPI2&CSI2 + + //INT56 + UINT32 bInt_ID_RTC:1; + UINT32 bInt_ID_WDT:1; + UINT32 bInt_ID_CG:1; + UINT32 bInt_ID_CC:1; + + //INT60 + UINT32 bInt_ID_I2C3:1; + UINT32 bInt_ID_SLVS_EC:1; + UINT32 bInt_ID_LVDS3:1; //LVDS3&HiSPI3&CSI3 + UINT32 bInt_ID_LVDS4:1; //LVDS4&HiSPI4&CSI4 + + //INT64 + UINT32 bInt_ID_LVDS5:1; //LVDS5&HiSPI5&CSI5 + UINT32 bInt_ID_LVDS6:1; //LVDS6&HiSPI6&CSI6 + UINT32 bInt_ID_LVDS7:1; //LVDS7&HiSPI7&CSI7 + UINT32 bInt_ID_LVDS8:1; //LVDS8&HiSPI8&CSI8 + + //INT68 + UINT32 bInt_ID_SIE5:1; + UINT32 bInt_ID_SIE6:1; + UINT32 bInt_ID_SIE7:1; + UINT32 bInt_ID_SIE8:1; + + //INT72 + UINT32 bInt_ID_IVE:1; + UINT32 bInt_ID_SVM:1; + UINT32 bInt_ID_SDE:1; + UINT32 bInt_ID_CNN:1; + + //INT76 + UINT32 bInt_ID_DSP:1; + UINT32 bInt_ID_DSP2:1; + UINT32 bInt_ID_CANBUS:1; + UINT32 bInt_ID_CRYPTO:1; + + //INT80 + UINT32 bInt_ID_HWCOPY:1; + UINT32 bInt_ID_ROTATE:1; + UINT32 bInt_ID_I2C4:1; + UINT32 bInt_ID_I2C5:1; + + //INT84 + UINT32 bInt_ID_I2C6:1; + UINT32 bInt_ID_I2C7:1; + UINT32 bReserved86:1; + UINT32 bReserved87:1; + + //INT88 + UINT32 bInt_ID_TMDEMUX:1; + UINT32 bReserved89:3; + + //INT92 + UINT32 bReserved92:4; + //INT96 => 4 + UINT32 bReserved96:4; + //INT100=> 4 + UINT32 bReserved100:4; + //INT104=> 4 + UINT32 bReserved104:4; + //INT108=> 4 + UINT32 bReserved108:4; + //INT112=> 4 + UINT32 bReserved112:4; + //INT116=> 4 + UINT32 bReserved116:4; + //INT120=> 4 + UINT32 bReserved120:4; + //INT124=> 4 + UINT32 bReserved124:4; + }Bit; +} INT_INTC_ID_DST, *PINT_INTC_ID_DST; + +typedef union +{ + INT_PTN Reg[4]; + struct + { + //INT0 + UINT32 bInt_ID_TIMER:1; + UINT32 bInt_ID_SIE:1; + UINT32 bInt_ID_SIE2:1; + UINT32 bInt_ID_SIE3:1; + + UINT32 bInt_ID_SIE4:1; + UINT32 bInt_ID_IPE:1; + UINT32 bInt_ID_IME:1; + UINT32 bInt_ID_DCE:1; + + UINT32 bInt_ID_IFE:1; + UINT32 bInt_ID_IFE2:1; + UINT32 bInt_ID_DIS:1; + UINT32 bInt_ID_FDE:1; + +// UINT32 bInt_ID_RDE:1; + UINT32 bInt_ID_Ethernet_LPI:1; + UINT32 bInt_ID_RHE:1; + UINT32 bInt_ID_DRE:1; + UINT32 bInt_ID_DAI:1; + + + //INT16 + UINT32 bInt_ID_H264:1; + UINT32 bInt_ID_JPEG:1; + UINT32 bInt_ID_GRAPHIC:1; + UINT32 bInt_ID_GRAPHIC2:1; + + UINT32 bInt_ID_AFFINE:1; + UINT32 bInt_ID_ISE:1; + UINT32 bInt_ID_TGE:1; + UINT32 bInt_ID_TSMUX:1; + + UINT32 bInt_ID_GPIO:1; + UINT32 bInt_ID_REMOTE:1; + UINT32 bInt_ID_PWM:1; + UINT32 bInt_ID_USB:1; + + UINT32 bInt_ID_USB3:1; + UINT32 bInt_ID_NAND:1; + UINT32 bInt_ID_SDIO:1; + UINT32 bInt_ID_SDIO2:1; + + //INT32 + UINT32 bInt_ID_SDIO3:1; + UINT32 bInt_ID_DMA:1; + UINT32 bInt_ID_ETHERNET:1; + UINT32 bInt_ID_SPI:1; + + UINT32 bInt_ID_SPI2:1; + UINT32 bInt_ID_SPI3:1; + UINT32 bInt_ID_SPI4:1; + UINT32 bInt_ID_Ehternet_RevMII:1; +// UINT32 bInt_ID_SPI5:1; + + + UINT32 bInt_ID_SIF:1; + UINT32 bInt_ID_I2C:1; + UINT32 bInt_ID_I2C2:1; + UINT32 bInt_ID_UART:1; + + UINT32 bInt_ID_UART2:1; + UINT32 bInt_ID_UART3:1; + UINT32 bInt_ID_UART4:1; + UINT32 bInt_ID_ADC:1; + + //INT48 + UINT32 bInt_ID_IDE:1; + UINT32 bInt_ID_IDE2:1; + UINT32 bInt_ID_DSI:1; + UINT32 bInt_ID_MI:1; + + //INT52 + UINT32 bInt_ID_HDMI:1; +// UINT32 bInt_ID_VX1:1; + UINT32 bInt_ID_DMA2:1; + UINT32 bInt_ID_LVDS:1; // LVDS& HiSPI& CSI + UINT32 bInt_ID_LVDS2:1; //LVDS2&HiSPI2&CSI2 + + //INT56 + UINT32 bInt_ID_RTC:1; + UINT32 bInt_ID_WDT:1; + UINT32 bInt_ID_CG:1; + UINT32 bInt_ID_CC:1; + + //INT60 + UINT32 bInt_ID_I2C3:1; + UINT32 bInt_ID_SLVS_EC:1; + UINT32 bInt_ID_LVDS3:1; //LVDS3&HiSPI3&CSI3 + UINT32 bInt_ID_LVDS4:1; //LVDS4&HiSPI4&CSI4 + + //INT64 + UINT32 bInt_ID_LVDS5:1; //LVDS5&HiSPI5&CSI5 + UINT32 bInt_ID_LVDS6:1; //LVDS6&HiSPI6&CSI6 + UINT32 bInt_ID_LVDS7:1; //LVDS7&HiSPI7&CSI7 + UINT32 bInt_ID_LVDS8:1; //LVDS8&HiSPI8&CSI8 + + //INT68 + UINT32 bInt_ID_SIE5:1; + UINT32 bInt_ID_SIE6:1; + UINT32 bInt_ID_SIE7:1; + UINT32 bInt_ID_SIE8:1; + + //INT72 + UINT32 bInt_ID_IVE:1; + UINT32 bInt_ID_SVM:1; + UINT32 bInt_ID_SDE:1; + UINT32 bInt_ID_CNN:1; + + //INT76 + UINT32 bInt_ID_DSP:1; + UINT32 bInt_ID_DSP2:1; + UINT32 bInt_ID_CANBUS:1; + UINT32 bInt_ID_CRYPTO:1; + + //INT80 + UINT32 bInt_ID_HWCOPY:1; + UINT32 bInt_ID_ROTATE:1; + UINT32 bInt_ID_I2C4:1; + UINT32 bInt_ID_I2C5:1; + + //INT84 + UINT32 bInt_ID_I2C6:1; + UINT32 bInt_ID_I2C7:1; + UINT32 bInt_ID_TIMER2:1; //Timer to CA53 core2 + UINT32 bInt_ID_GPIO2:1; //GPIO to CA53 core2 + + //INT88 + UINT32 bInt_ID_PWM2:1; + UINT32 bInt_ID_CC2:1; + UINT32 bInt_ID_SIF2:1; //Timer to CA53 core2 + UINT32 bInt_ID_DSP_2:1; //?? + + //INT92 + UINT32 bInt_ID_DSP2_2:1; //?? + UINT32 bInt_ID_TMDEMUX:1; + UINT32 bReserved92:2; + //INT96 => 4 + UINT32 bReserved96:4; + //INT100=> 4 + UINT32 bReserved100:4; + //INT104=> 4 + UINT32 bReserved104:4; + //INT108=> 4 + UINT32 bReserved108:4; + //INT112=> 4 + UINT32 bReserved112:4; + //INT116=> 4 + UINT32 bReserved116:4; + //INT120=> 4 + UINT32 bReserved120:4; + //INT124=> 4 + UINT32 bReserved124:4; + }Bit; +} INT_GIC_ID_ENABLE, *PINT_GIC_ID_ENABLE; + +typedef struct +{ + INT_GIC_ID_DST int_id_dst[CC_CORE_CA53_CORE_NUM]; +} INT_GIC_DST, *PINT_GIC_DST; + +typedef struct +{ + INT_INTC_ID_DST int_id_dst[CC_CORE_DSP_NUM]; +} INT_INTC_DST, *PINT_INTC_DST; + +typedef struct +{ + INT_GIC_ID_ENABLE int_id_enable; +} INT_INTC_ENABLE, *PINT_INTC_ENABLE; + + +// MIPI CSI share the interrupt ID with LVDS / HiSPi +#define INT_ID_CSI INT_ID_LVDS +#define INT_ID_CSI2 INT_ID_LVDS2 + +#define INT_ID_CSI3 INT_ID_LVDS3 +#define INT_ID_CSI4 INT_ID_LVDS4 + +#define INT_ID_CSI5 INT_ID_LVDS5 +#define INT_ID_CSI6 INT_ID_LVDS6 +#define INT_ID_CSI7 INT_ID_LVDS7 +#define INT_ID_CSI8 INT_ID_LVDS8 + +#define INT_ID_VX1 INT_ID_LVDS5 +#define INT_ID_VX1_2 INT_ID_LVDS6 + +// Macro to generate bit value from ID +#define INT_ID_TO_BIT(Id) ((INT_PTN)(1) << (Id)) + +// check type and ID +STATIC_ASSERT((INT_ID_MAX - INT_GIC_SPI_START_ID) <= (sizeof(INT_PTN) << 3)); + +#define INT_ALL_MODULES ((sizeof(INT_PTN) == 4) ? 0xFFFFFFFFul : 0xFFFFFFFFFFFFFFFFull) + +extern INT_PTN int_getEnable(void); +extern INT_PTN int_getFlag(void); +extern INT_ID int_getIRQId(void); +extern INT_ID int_getDummyId(void); +extern UINT32 int_getLatency(void); +extern void int_setConfig(INT_CONFIG_ID ConfigID, UINT32 uiConfig); +extern void int_get_gic_enable(PINT_INTC_ENABLE gic_int_en); + + +//@} + +#endif diff --git a/board/novatek/ns02501/loader/Include/modelext/model_cfg.h b/board/novatek/ns02501/loader/Include/modelext/model_cfg.h new file mode 100755 index 000000000000..eb7be844cc5e --- /dev/null +++ b/board/novatek/ns02501/loader/Include/modelext/model_cfg.h @@ -0,0 +1,8 @@ +#ifndef _MODEL_CFG_H +#define _MODEL_CFG_H + +#define MODEL_CFG_VER 0x16072510 ///< YYYY/MM/DD HH + +//No data structure, just a string. + +#endif diff --git a/board/novatek/ns02501/loader/Include/modelext/modelext_info.h b/board/novatek/ns02501/loader/Include/modelext/modelext_info.h new file mode 100755 index 000000000000..b96b50b966dd --- /dev/null +++ b/board/novatek/ns02501/loader/Include/modelext/modelext_info.h @@ -0,0 +1,35 @@ +#ifndef _MODELEXT_INFO_H +#define _MODELEXT_INFO_H + +#define MODELEXT_INFO_VER 0x16072219 ///< YYYY/MM/DD HH + +typedef enum _MODELEXT_TYPE { + MODELEXT_TYPE_DUMMY = 0, + MODELEXT_TYPE_INFO , + MODELEXT_TYPE_BIN_INFO , + MODELEXT_TYPE_PINMUX_CFG , + MODELEXT_TYPE_INTDIR_CFG , + MODELEXT_TYPE_EMB_PARTITION, + MODELEXT_TYPE_GPIO_INFO , + MODELEXT_TYPE_DRAM_PARTITION, + MODELEXT_TYPE_MODEL_CFG, + MODELEXT_TYPE_MAX +} MODELEXT_TYPE; + +typedef struct _MODELEXT_HEADER { + unsigned int size; ///< header size + container size + unsigned int type; ///< MODELEXT_TYPE + unsigned int number; ///< number of carried data elements + unsigned int version; ///< data header version +} MODELEXT_HEADER; + +typedef struct _MODELEXT_INFO { + char name[8]; ///< always be 'M','O','D','E','L','E','X','T' + char chip_name[8]; ///< CHIP_NAME (8) ---- check by encrypt_bin + char version[8]; ///< Reversed + char date[8]; ///< date + unsigned int ext_bin_length; ///< Bin File Length (4) --- write by encrypt_bin + unsigned int check_sum; ///< Check Sum Value (4) ----- write by encrypt_bin +} MODELEXT_INFO; + +#endif diff --git a/board/novatek/ns02501/loader/Include/modelext/modelext_parser.h b/board/novatek/ns02501/loader/Include/modelext/modelext_parser.h new file mode 100755 index 000000000000..e00170ea1a85 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/modelext/modelext_parser.h @@ -0,0 +1,78 @@ +#ifndef _MODELEXT_PARSER_H +#define _MODELEXT_PARSER_H + +#include "modelext_info.h" + +/** + modelext inline parse. + + modelext info tables are set to an certain memory address, + which use to get data pointer you want. + + @param[in] modelext info address. + @param[in] refer to MODELEXT_TYPE_ + @param[in] a memory space will be stored with description of modelext type. + @return + - @b address: the data pointer of result. +*/ +static inline unsigned char *modelext_get_cfg(unsigned char *buf, unsigned int type, MODELEXT_HEADER **header) +{ +#define MAGIC "MODELEXT" + + MODELEXT_HEADER *h = (MODELEXT_HEADER*)buf; + MODELEXT_INFO *d = (MODELEXT_INFO*)(buf + sizeof(MODELEXT_HEADER)); + + if(type >= MODELEXT_TYPE_MAX) + { + if(header) + { + *header = NULL; + } + return NULL; + } + + if(memcmp(d->name, MAGIC, strlen(MAGIC))) + { + if(header) + { + *header = NULL; + } + return NULL; + } + + MODELEXT_HEADER* h_tail = (MODELEXT_HEADER*)(buf + d->ext_bin_length); + + while(h->size) + { + if(h->type == type) + { + break; + } + else + { + h = (MODELEXT_HEADER*)(((char*)h) + h->size); + if(h >= h_tail) + { + return NULL; + } + } + } + + if(!h->size) + { + if(header) + { + *header = NULL; + } + return NULL; + } + + if(header) + { + *header = h; + } + + return (unsigned char*)(((unsigned char*)h) + sizeof(MODELEXT_HEADER)); +} + +#endif diff --git a/board/novatek/ns02501/loader/Include/modelext/shm_info.h b/board/novatek/ns02501/loader/Include/modelext/shm_info.h new file mode 100755 index 000000000000..911d5d4ccbc4 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/modelext/shm_info.h @@ -0,0 +1,135 @@ +/** + @file shm_info.h + @ingroup + @note THESE STRUCTS ARE VERY VERY IMPORTANT FORMAT DEFINITION OF SYSTEM, + DO NOT MODIFY ANY ITEM OR INSERT/REMOVE ANY ITEM OF THESE STRUCTS!!! + + Copyright Novatek Microelectronics Corp. 2018. All rights reserved. +*/ +#ifndef __ARCH_COMMON_SHM_INFO_H +#define __ARCH_COMMON_SHM_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#elif defined(_NVT_LINUX_) +#include +#else +#include +#endif + +#define SHM_INFO_VER 0x18060815 ///< YYYY/MM/DD HH + +/** + @name Ld control flag for LDINFO.LdCtrl +*/ +//@{ +#define LDCF_PARTLOAD_EN 0x0000001 ///< BIT 0.PARTLOAD_EN (0=no,1=yes) +//@} + +/** + @name Ld control flag for LDINFO.LdCtrl2 +*/ +//@{ +#define LDCF_UPDATE_FW 0x0000001 ///< BIT 0.UPDATE_FW (0=no,1=yes) +#define LDCF_UPDATE_LD 0x0000002 ///< BIT 1.UPDATE_LD (0=no,1=yes) +#define LDCF_BOOT_CARD 0x0000004 ///< BIT 2.BOOT_CARD (0=no,1=yes) +#define LDCF_BOOT_FLASH 0x0000008 ///< BIT 3.BOOT_FLASH (0=no,1=yes) +#define LDCF_UPDATE_CAL 0x0000010 ///< BIT 4.UPDATE_CAL (0=no,1=yes) +#define LDCF_UPDATE_FW_DONE 0x0000100 ///< BIT 8.UPDATE_FW_DONE (0=no,1=yes) +#define LDCF_S3_BOOT 0x0000200 ///< BIT 9.BOOT FROM S3 STATE (0=no,1=yes) +#define LDCF_DTR80_BOOT 0x0000400 ///< BIT 10.BOOT WITH FLASH DTR-80 SUPPORT (0=no,1=yes) +#define LDCF_8051_BOOT 0x0000800 ///< BIT 11.BOOT FROM 8051 (0=no,1=yes) +#define LDCF_FAST_SENSOR 0x0001000 ///< BIT 12.INDICATE LOADER USE CFE TO CFG SENSOR (0=no,1=yes) +//@} + +/** + Loader information + + MUST 28 WORDS +*/ +typedef struct _BOOTINFO { + char LdInfo_1[16]; ///< LD-NAME(16) ------ w by Ld + UINT32 LdCtrl; ///< Fw flag (4) ----------- r by Ld + ///< BIT 0.enable part-load (0=full load,1=part load) + UINT32 LdCtrl2; ///< Ld flag (4) ----------- w by Ld, Ref: LDCF_??????? + UINT32 LdLoadSize; ///< Ld load size (4) ------ w by Ld (NOTE: this value must be block size align) + UINT32 LdLoadTime; ///< Ld exec time(us) (4) -- w by Ld + UINT32 LdResvSize; ///< Ld size (by bytes, reserved size in partition) (4) ------ w by Ld + UINT32 FWResvSize; ///< FW reserved size (4) ------ w by Ld + UINT16 LdPackage; ///< IC package expected by Ld (0xFF: ES, 0: 660, 3: 663, 5: 665, etc...) + UINT16 LdStorage; ///< Internal storage expected by Ld (0: unkown, 1: nand, 2: spi nand, 3: spi nor) + UINT32 fdt_addr; + UINT32 Resv[16]; ///< (4*5) ------------ reserved for project Ld +} BOOTINFO; + +STATIC_ASSERT(sizeof(BOOTINFO) == 112); + +/** + communication information + + MUST 54 WORDS +*/ +//BOOT_REASON +#define BOOT_REASON_NORMAL 0 // normal or from sd +#define BOOT_REASON_FWUPDFW 1 // Firmware update Firmware +#define BOOT_REASON_FROM_USB 2 // Update from USB +#define BOOT_REASON_FROM_ETH 3 // Update from ethernet +#define BOOT_REASON_FORMAT_ROOTFS 4 // Format rootfs because rootfs broken is detected +#define BOOT_REASON_RECOVERY_SYS 5 // System recovery from eMMC +#define BOOT_REASON_FROM_UART 6 // Update from uart + +//COMMINFO::Resv field definition +typedef enum _COMM_RESV_IDX_{ + COMM_RESV_IDX_BOOT_REASON = 0, + COMM_RESV_IDX_CORE1_START = 1, + COMM_RESV_IDX_CORE2_START = 2, + COMM_RESV_IDX_UITRON_COMP_ADDR = 3, + COMM_RESV_IDX_UITRON_COMP_LEN = 4, + COMM_RESV_IDX_FW_UPD_ADDR = 5, + COMM_RESV_IDX_FW_UPD_LEN = 6, + COMM_RESV_IDX_OTA_NAME_ADDR = 7, + COMM_RESV_IDX_S3_APB_ADDR = 8, + COMM_RESV_IDX_S3_APB_LEN = 9, + COMM_RESV_IDX_CORE1_LINUX_ADDR = 10, + COMM_RESV_IDX_CORE1_FDT_ADDR = 11, + COMM_RESV_IDX_LD_TIME_ADDR = 12, + COMM_RESV_IDX_LD_TIME_CNTS = 13, +} COMM_RESV_IDX; + +typedef struct _COMMINFO { + char CommInfo_1[16];///< COMMINFO (16) + UINT32 Resv[45];///< reversed data for communication between loader, uboot, uitron, linux + // Resv[0]: COMM_RESV_IDX_BOOT_REASON, + // BYTE[0]: BOOT_REASON: use #define COMM_BOOT_REASON_ + // BYTE[1]: BOOT_DONE: 0:Not yet, 1:Done 2:NG + // BYTE[2]: DSP_DONE: 0:Not yet, 1:Done 2:NG + // Resv[1]: COMM_CORE1_START (used on uboot trigger loader to start uitron) + // Resv[2]: COMM_CORE2_START (used on uitron trigger linux resume) + // Resv[3]: COMM_UITRON_COMP_ADDR + // Resv[4]: COMM_UITRON_COMP_LEN + // Resv[5]: COMM_FW_UPD_ADDR + // Resv[6]: COMM_FW_UPD_LEN + // Resv[7]: COMM_OTA_NAME_ADDR : OTA name + // Resv[8]: COMM_S3_APB_ADDR : S3-resume's apb register info addr + // Resv[9]: COMM_S3_APB_LEN : S3-resume's apb register info len + // Resv[10]: COMM_RESV_IDX_CORE1_LINUX_ADDR = 10: linux addr, for rtos on core2 to boot linux on core1 + // Resv[11]: COMM_RESV_IDX_CORE1_FDT_ADDR = 11, fdt addr, reconstruct fdt, for rtos on core2 to boot linux on core1 + // Resv[12]: COMM_RESV_IDX_LD_TIME_ADDR = 12, loader performance tag address (from per_mark, passed to RTOS) + // Resv[13]: COMM_RESV_IDX_LD_TIME_CNTS = 13, loader performance tag count (from per_mark, passed to RTOS) + UINT32 UserDef[5]; ///< can be used for customer +} COMMINFO; + +STATIC_ASSERT(sizeof(COMMINFO) == 216); + +/** + Binary file information + + MUST 82 WORDS +*/ +typedef struct _SHMINFO { + BOOTINFO boot; + COMMINFO comm; +} SHMINFO; + +STATIC_ASSERT(sizeof(SHMINFO) == 328); +#endif /* __ARCH_COMMON_SHM_INFO_H */ diff --git a/board/novatek/ns02501/loader/Include/modelext/top.h b/board/novatek/ns02501/loader/Include/modelext/top.h new file mode 100755 index 000000000000..2011294fca65 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/modelext/top.h @@ -0,0 +1,1382 @@ +/** + TOP controller header + + Sets the pinmux of each module. + + @file top.h + @ingroup mIDrvSys_TOP + @note Refer NT96650 data sheet for PIN/PAD naming + + Copyright Novatek Microelectronics Corp. 2013. All rights reserved. +*/ + +#ifndef _TOP_H +#define _TOP_H + +#if defined(__UITRON) +#include "Type.h" +#else +#include "nvt_type.h" +#endif +//#define TOP_NEW_API (0) + +/** + @addtogroup mIDrvSys_TOP +*/ +//@{ +#define PIN_GROUP_CONFIG_VER 0x16062910 + +/** + Debug port select ID + + Debug port select value for pinmux_select_debugport(). +*/ +typedef enum +{ + PINMUX_DEBUGPORT_CKG = 0x0000, ///< CKGen + PINMUX_DEBUGPORT_ARB = 0x0001, ///< Arbiter + PINMUX_DEBUGPORT_DDR = 0x0002, ///< DDR + PINMUX_DEBUGPORT_APBTG = 0x0003, ///< APBTG + PINMUX_DEBUGPORT_OCPBRG = 0x0004, ///< OCP BRG + PINMUX_DEBUGPORT_INTC = 0x0005, ///< INTC + PINMUX_DEBUGPORT_IDE = 0x0006, ///< IDE + PINMUX_DEBUGPORT_IDE2 = 0x0007, ///< IDE2 + PINMUX_DEBUGPORT_MI = 0x0008, ///< MI + PINMUX_DEBUGMIPI_DSI = 0x0009, ///< MIPI DSI + PINMUX_DEBUGMIPI_CC = 0x000A, ///< CC + PINMUX_DEBUGMIPI_EFUSE = 0x000B, ///< EFUSE + PINMUX_DEBUGMIPI_ETH = 0x000C, ///< ETH + PINMUX_DEBUGMIPI_AHBC_ETH = 0x000D, ///< AHBC ETH + PINMUX_DEBUGMIPI_TSMUX = 0x000E, ///< TSMUX + + PINMUX_DEBUGPORT_TIMER = 0x0010, ///< Timer + PINMUX_DEBUGPORT_WDT = 0x0011, ///< WDT + PINMUX_DEBUGPORT_GPIO = 0x0012, ///< GPIO + PINMUX_DEBUGPORT_SSP = 0x0013, ///< SSP (DAI) + PINMUX_DEBUGPORT_AUDIO = 0x0014, ///< AUDIO + PINMUX_DEBUGPORT_SDIO1 = 0x0015, ///< SDIO1 + PINMUX_DEBUGPORT_SDIO2 = 0x0016, ///< SDIO2 + PINMUX_DEBUGPORT_SDIO3 = 0x0017, ///< SDIO3 + PINMUX_DEBUGPORT_SMMC = 0x0018, ///< XD/NAND/SMC + PINMUX_DEBUGPORT_USB = 0x0019, ///< USB + PINMUX_DEBUGPORT_USB2 = 0x001A, ///< USB2 + PINMUX_DEBUGPORT_AHBC_USB = 0x001B, ///< AHBC_USB + PINMUX_DEBUGPORT_AHBC_USB2 = 0x001C, ///< AHBC_USB2 + PINMUX_DEBUGPORT_I2C = 0x001D, ///< I2C + PINMUX_DEBUGPORT_I2C2 = 0x001E, ///< I2C2 + PINMUX_DEBUGPORT_SIF = 0x001F, ///< SIF + PINMUX_DEBUGPORT_SPI = 0x0020, ///< SPI + PINMUX_DEBUGPORT_SPI2 = 0x0021, ///< SPI2 + PINMUX_DEBUGPORT_SPI3 = 0x0022, ///< SPI3 + PINMUX_DEBUGPORT_SPI4 = 0x0023, ///< SPI4 + PINMUX_DEBUGPORT_SPI5 = 0x0024, ///< SPI5 + PINMUX_DEBUGPORT_PWM = 0x0025, ///< PWM + PINMUX_DEBUGPORT_ADM = 0x0026, ///< ADC + PINMUX_DEBUGPORT_REMOTE = 0x0027, ///< Remote + PINMUX_DEBUGPORT_CRYPTO = 0x0028, ///< Crypto + + PINMUX_DEBUGPORT_OCP2BRG = 0x0030, ///< OCP2 BRG + PINMUX_DEBUGPORT_DSP = 0x0031, ///< DSP + PINMUX_DEBUGPORT_H264 = 0x0038, ///< H.264 + + PINMUX_DEBUGMIPI_CSI = 0x0040, ///< MIPI CSI + PINMUX_DEBUGMIPI_CSI2 = 0x0041, ///< MIPI CSI2 + PINMUX_DEBUGMIPI_VX1 = 0x0042, ///< VX1 + PINMUX_DEBUGPORT_SIE = 0x0043, ///< SIE + PINMUX_DEBUGMIPI_SIE2 = 0x0044, ///< SIE2 + PINMUX_DEBUGPORT_SIE3 = 0x0045, ///< SIE3 + PINMUX_DEBUGMIPI_SIE4 = 0x0046, ///< SIE4 + PINMUX_DEBUGPORT_TGE = 0x0047, ///< TGE + PINMUX_DEBUGPORT_DIS = 0x0048, ///< DIS + PINMUX_DEBUGPORT_FDE = 0x0049, ///< FDE + PINMUX_DEBUGPORT_JPEG = 0x004A, ///< JPEG + PINMUX_DEBUGPORT_GRAPHIC = 0x004B, ///< GRAPHIC + PINMUX_DEBUGPORT_GRAPHIC2 = 0x004C, ///< GRAPHIC2 + PINMUX_DEBUGPORT_IFE = 0x004D, ///< IFE + PINMUX_DEBUGPORT_AFFINE = 0x004E, ///< Affine + PINMUX_DEBUGPORT_ISE = 0x004F, ///< ISE + PINMUX_DEBUGPORT_RDE = 0x0050, ///< RDE + PINMUX_DEBUGPORT_RHE = 0x0051, ///< RHE + PINMUX_DEBUGPORT_I2C3 = 0x0052, ///< I2C3 + + PINMUX_DEBUGPORT_IPE = 0x0060, ///< IPE + PINMUX_DEBUGPORT_IME = 0x0061, ///< IME + PINMUX_DEBUGPORT_IFE2 = 0x0062, ///< IFE2 + PINMUX_DEBUGPORT_HDMI = 0x0063, ///< HDMI + PINMUX_DEBUGPORT_DCE = 0x0064, ///< DCE + PINMUX_DEBUGPORT_DRE = 0x0065, ///< DRE + +/* //remove for NT96660 + PINMUX_DEBUGPORT_AMBARD = 0x0000, ///< AMBA RD + PINMUX_DEBUGPORT_AMBAWR = 0x0001, ///< AMBA WR + PINMUX_DEBUGPORT_AHB = 0x0002, ///< AHB + PINMUX_DEBUGPORT_AHBC0 = 0x0003, ///< AHB C0 + PINMUX_DEBUGPORT_AHBC1 = 0x0004, ///< AHB C1 + PINMUX_DEBUGPORT_APBBRG = 0x0005, ///< APB BRG + PINMUX_DEBUGPORT_DDRIO = 0x0006, ///< DDRIO + PINMUX_DEBUGPORT_LVDS = 0x001F, ///< LVDS + PINMUX_DEBUGPORT_SDIO1_FIFO = 0x0022, ///< SDIO1 FIFO + PINMUX_DEBUGPORT_SDIO2_FIFO = 0x0023, ///< SDIO2 FIFO + PINMUX_DEBUGPORT_BMC = 0x0024, ///< BMC + PINMUX_DEBUGPORT_IRDA1 = 0x0025, ///< IRDA1 + PINMUX_DEBUGPORT_IRDA2 = 0x0026, ///< IRDA2 + PINMUX_DEBUGMIPI_OCP = 0x0029, ///< OCP + PINMUX_DEBUGPORT_PRE = 0x0030, ///< PRE +*/ + PINMUX_DEBUGPORT_GROUP_NONE = 0x0000, ///< No debug port is output + PINMUX_DEBUGPORT_GROUP1 = 0x0100, ///< Output debug port to MC[18..0] + PINMUX_DEBUGPORT_GROUP2 = 0x0200, ///< Output debug port to LCD[18..0] + + ENUM_DUMMY4WORD(PINMUX_DEBUGPORT) +} PINMUX_DEBUGPORT; + +// for backward compatible +#define PINMUX_DEBUGMIPI_OCP PINMUX_DEBUGPORT_OCPBRG + +/* + PIN state for SDIO + + (Reserved for driver internal usage) + + @note For pinmux_getPinmux() +*/ +typedef enum +{ + PIN_SDIO_STATE_NONE, + PIN_SDIO_STATE_ACTIVE = 0x0100, //< SD active + ENUM_DUMMY4WORD(PIN_SDIO_STATE) +} PIN_SDIO_STATE; + +/* + PIN state for SPI + + (Reserved for driver internal usage) + + @note For pinmux_getPinmux() +*/ +typedef enum +{ + PIN_SPI_STATE_NONE, + PIN_SPI_STATE_ACTIVE = 0x10000, //< SPI active + ENUM_DUMMY4WORD(PIN_SPI_STATE) +} PIN_SPI_STATE; + +/* + PIN state for NAND + + (Reserved for driver internal usage) + + @note For pinmux_getPinmux() +*/ +typedef enum +{ + PIN_NAND_STATE_NONE, + PIN_NAND_STATE_ACTIVE = 0x0400, //< NAND active + ENUM_DUMMY4WORD(PIN_NAND_STATE) +} PIN_NAND_STATE; + +/* + PINMUX selection for I2C + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_I2C_SEL_INACTIVE, //< I2C inactive + PINMUX_I2C_SEL_ACTIVE, //< I2C active + ENUM_DUMMY4WORD(PINMUX_I2C_SEL) +} PINMUX_I2C_SEL; + +/* + PINMUX selection for PWM + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_PWM_SEL_INACTIVE, //< PWM inactive + PINMUX_PWM_SEL_ACTIVE, //< PWM active + ENUM_DUMMY4WORD(PINMUX_PWM_SEL) +} PINMUX_PWM_SEL; + +/* + PINMUX selection for SIF + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_SIF_SEL_INACTIVE, //< SIF inactive + PINMUX_SIF_SEL_ACTIVE, //< SIF active + ENUM_DUMMY4WORD(PINMUX_SIF_SEL) +} PINMUX_SIF_SEL; + +/* + PINMUX selection for I2S + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_I2S_SEL_INACTIVE, //< I2S inactive + PINMUX_I2S_SEL_ACTIVE, //< I2S active + ENUM_DUMMY4WORD(PINMUX_I2S_SEL) +} PINMUX_I2S_SEL; + +/* + PINMUX selection for UART + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_UART_SEL_INACTIVE, //< UART inactive + PINMUX_UART_SEL_ACTIVE, //< UART active + ENUM_DUMMY4WORD(PINMUX_UART_SEL) +} PINMUX_UART_SEL; + + +/** + OCP Debug port select ID + + Debug port select value for pinmux_select_ocp_debugport(). +*/ +typedef enum +{ + PINMUX_DEBUGPORT_OCPCMD_DMA_APB = 0x0, ///< OCP CMD vs. DMA/APB + PINMUX_DEBUGPORT_OCPCMD_HANDSHAKE = 0x1, ///< OCP CMD handshaking + PINMUX_DEBUGPORT_OCP_DMA = 0x2, ///< OCP vs. DMA + PINMUX_DEBUGPORT_OCP_DEBUG_3 = 0x3, ///< OCP debug 3 + PINMUX_DEBUGPORT_OCP_DEBUG_4 = 0x4, ///< OCP debug 4 + + ENUM_DUMMY4WORD(PINMUX_DEBUGPORT_OCP) +} PINMUX_DEBUGPORT_OCP; + +/** + Function group + + @note For pinmux_init() +*/ +typedef enum +{ + PIN_FUNC_SDIO, ///< SDIO. Configuration refers to PIN_SDIO_CFG. + PIN_FUNC_SDIO2, ///< SDIO2. Configuration refers to PIN_SDIO_CFG. + PIN_FUNC_SDIO3, ///< SDIO3. Configuration refers to PIN_SDIO_CFG. + PIN_FUNC_NAND, ///< NAND. Configuration refers to PIN_NAND_CFG. + PIN_FUNC_SENSOR, ///< sensor interface. Configuration refers to PIN_SENSOR_CFG. + PIN_FUNC_SENSOR2, ///< sensor2 interface. Configuration refers to PIN_SENSOR2_CFG. + PIN_FUNC_SENSOR3, ///< sensor3 interface. Configuration refers to PIN_SENSOR3_CFG. + PIN_FUNC_SENSOR4, ///< sensor4 interface. Configuration refers to PIN_SENSOR4_CFG. + PIN_FUNC_SENSOR5, ///< sensor5 interface. Configuration refers to PIN_SENSOR5_CFG. + PIN_FUNC_SENSOR6, ///< sensor6 interface. Configuration refers to PIN_SENSOR6_CFG. + PIN_FUNC_SENSOR7, ///< sensor7 interface. Configuration refers to PIN_SENSOR7_CFG. + PIN_FUNC_SENSOR8, ///< sensor8 interface. Configuration refers to PIN_SENSOR8_CFG. + PIN_FUNC_MIPI_LVDS, ///< MIPI/LVDS interface configuration. Configuration refers to PIN_MIPI_LVDS_CFG. + PIN_FUNC_I2C, ///< I2C. Configuration refers to PIN_I2C_CFG. + PIN_FUNC_SIF, ///< SIF. Configuration refers to PIN_SIF_CFG. + PIN_FUNC_UART, ///< UART. Configuration refers to PIN_UART_CFG. + PIN_FUNC_SPI, ///< SPI. Configuration refers to PIN_SPI_CFG. + PIN_FUNC_REMOTE, ///< REMOTE. Configuration refers to PIN_REMOTE_CFG. + PIN_FUNC_PWM, ///< PWM. Configuration refers to PIN_PWM_CFG. + PIN_FUNC_AUDIO, ///< AUDIO. Configuration refers to PIN_PWM_CFG. + PIN_FUNC_LCD, ///< LCD interface. Configuration refers to PINMUX_LCDINIT, PINMUX_PMI_CFG, PINMUX_DISPMUX_SEL. + PIN_FUNC_LCD2, ///< LCD2 interface. Configuration refers to PINMUX_LCDINIT, PINMUX_PMI_CFG, PINMUX_DISPMUX_SEL. + PIN_FUNC_TV, ///< TV interface. Configuration refers to PINMUX_TV_HDMI_CFG. + PIN_FUNC_HDMI, ///< HDMI. Configuration refers to PINMUX_LCDINIT, PINMUX_TV_HDMI_CFG, PINMUX_HDMI_CFG. + PIN_FUNC_ETH, ///< ETH. Configuration refers to + + ENUM_DUMMY4WORD(PIN_FUNC) +} PIN_FUNC; + +/** + PIN config for SDIO + + @note For pinmux_init() with PIN_FUNC_SDIO or PIN_FUNC_SDIO2 or PIN_FUNC_SDIO3.\n + For example, you can use {PIN_FUNC_SDIO, PIN_SDIO_CFG_1ST_PINMUX|PIN_SDIO_CFG_4BITS}\n + to declare SDIO is 4 bits and located in 1st pinmux location. +*/ +typedef enum +{ + PIN_SDIO_CFG_NONE, + PIN_SDIO_CFG_4BITS = 0x01, ///< 4 bits wide + PIN_SDIO_CFG_8BITS = 0x02, ///< 8 bits wide + + PIN_SDIO_CFG_1ST_PINMUX = 0x00, ///< 1st pinmux location + ///< For SDIO: enable SD_CLK/SD_CMD/SD_D[0..3] on MC[16..21] (C_GPIO[16..21]) + ///< For SDIO2: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[22..27] (C_GPIO[22..27]) + ///< For SDIO3: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[28..33] (C_GPIO[28..33]) + PIN_SDIO_CFG_2ND_PINMUX = 0x10, ///< 2nd pinmux location + ///< For SDIO: enable SD_CLK/SD_CMD/SD_D[0..3] on MC[16..21] (C_GPIO[16..21]) (SDIO only has one pinmux pad group) + ///< For SDIO2: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[22..27] (C_GPIO[22..27]) (SDIO2 only has one pinmux pad group) + ///< For SDIO3: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[0..3]/MC9/MC11 (C_GPIO[0..3], 9, 11) + ///< When 8 bits, enable MC[0..7]/MC9/MC11 (C_GPIO[0..7], 9, 11) + + ENUM_DUMMY4WORD(PIN_SDIO_CFG) +} PIN_SDIO_CFG; + +/** + PIN config for NAND + + @note For pinmux_init() with PIN_FUNC_NAND.\n + For example, you can use {PIN_FUNC_NAND, PIN_NAND_CFG_1CS} to declare NAND with 1 CS. +*/ +typedef enum +{ + PIN_NAND_CFG_NONE, + PIN_NAND_CFG_1CS = 0x01, ///< 1 chip select. Enable NAND_D[0..7]/NAND_CS0/NAND_WE/NAND_RE/NAND_CLE/NAND_ALE/NAND_WP/NAND_RDY on MC[0..8]/MC[10..15] (C_GPIO[0..8], C_GPIO[10..15]) + PIN_NAND_CFG_2CS = 0x02, ///< 2 chip select. Enable NAND_D[0..7]/NAND_CS[0..1]/NAND_WE/NAND_RE/NAND_CLE/NAND_ALE/NAND_WP/NAND_RDY on MC[0..8]/MC[10..15] (C_GPIO[0..15]) + PIN_NAND_CFG_SPI_NAND = 0x4, ///< Virtual enum for project layer configuration + PIN_NAND_CFG_SPI_NOR = 0x8, ///< Virtual enum for project layer configuration + ENUM_DUMMY4WORD(PIN_NAND_CFG) +} PIN_NAND_CFG; + +/** + PIN config for Sensor + + @note For pinmux_init() with PIN_FUNC_SENSOR.\n + For example, you can use {PIN_FUNC_SENSOR, PIN_SENSOR_CFG_10BITS|PIN_SENSOR_CFG_SHUTTER|PIN_SENSOR_CFG_MCLK}\n + to declare sensor interface is 10 bits sensor, has SHUTTER and MCLK. +*/ +typedef enum +{ + PIN_SENSOR_CFG_NONE, + PIN_SENSOR_CFG_8BITS = 0x01, ///< 8 bits sensor. Enable SN_D[4..11]/SN_PXCLK/SN_VD/SN_HD on HSI_D[1..4]N/HSI_D[1..4]P/SN_PXCLK/SN_VD/SN_HD (S_GPI[1..3]/S_GPI[1..3]) + PIN_SENSOR_CFG_10BITS = 0x02, ///< 10 bits sensor. Enable SN_D[2..11]/SN_PXCLK/SN_VD/SN_HD on HSI_D[0..4]N/HSI_D[0..4]P0/SN_PXCLK/SN_VD/SN_HD (S_GPI[1..3]/S_GPI[1..3]) + PIN_SENSOR_CFG_12BITS = 0x04, ///< 12 bits sensor. Enable SN_D[0..11]/SN_PXCLK/SN_VD/SN_HD on HSI_D[0..4]N/HSI_D[0..4]P/HSI_CK0N/HSI_CK0P/SN_PXCLK/SN_VD/SN_HD (S_GPI[1..3]/S_GPI[1..3]) + PIN_SENSOR_CFG_MIPI = 0x20, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR_CFG_LVDS = 0x40, ///< LVDS sensor PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR_CFG_LVDS_VDHD = 0x80, ///< Backward compatible + + PIN_SENSOR_CFG_SHUTTER = 0x100, ///< Enable SN_SHUTTER on SN_GPIO[10] (SN_GPIO[10]) + PIN_SENSOR_CFG_MCLK = 0x200, ///< Enable SN_MCLK on SN_MCLK (S_GPIO[0]) + PIN_SENSOR_CFG_MCLK2 = 0x400, ///< Enable SN_MCLK2 on SBCS0 (S_GPIO[4]) + PIN_SENSOR_CFG_MES0 = 0x800, ///< Enable ME_SHUT0 on PWM0 (P_GPIO[0]) + PIN_SENSOR_CFG_MES0_2ND = 0x1000, ///< Enable (2nd) ME_SHUT0 on PWM16 (P_GPIO[16]) + PIN_SENSOR_CFG_MES1 = 0x2000, ///< Enable ME_SHUT1 on PWM1 (P_GPIO[1]) + PIN_SENSOR_CFG_MES1_2ND = 0x4000, ///< Enable (2nd) ME_SHUT1 on PWM17 (P_GPIO[17]) + PIN_SENSOR_CFG_FLCTR = 0x8000, ///< Enable SN_FLCTR on SN_FLCTR (P_GPIO[40]) + PIN_SENSOR_CFG_STROBE = 0x10000, ///< Enable SN_FLASH on SN_GPIO[9] (SN_GPIO[9]) + PIN_SENSOR_CFG_SPCLK = 0x20000, ///< Enable SP_CLK on SN_SPCLK (P_GPIO[20]) + PIN_SENSOR_CFG_SPCLK_2ND = 0x40000, ///< Enable SP_CLK on LCD27 (L_GPIO[27]) + PIN_SENSOR_CFG_SP2CLK = 0x80000, ///< Enable SP2_CLK on REMOTE_RX(P_GPIO[39]) + PIN_SENSOR_CFG_SP2CLK_2ND = 0x100000,///< Enable SP2_CLK on SBCS3 (P_GPIO[24]) + PIN_SENSOR_CFG_MES2 = 0x200000, ///< Enable ME_SHUT2 on PWM2 (P_GPIO[2]) + PIN_SENSOR_CFG_MES2_2ND = 0x400000, ///< Enable (2nd) ME_SHUT2 on PWM18 (P_GPIO[18]) + PIN_SENSOR_CFG_MES3 = 0x800000, ///< Enable ME_SHUT3 on PWM3 (P_GPIO[3]) + PIN_SENSOR_CFG_MES3_2ND = 0x1000000, ///< Enable (2nd) ME_SHUT3 on PWM19 (P_GPIO[19]) + PIN_SENSOR_CFG_LOCKN = 0x2000000, ///< Enable LOCKN on PGPIO30 + PIN_SENSOR_CFG_LOCKN2= 0x4000000, ///< Enable LOCKN2 on PGPIO31 + + + ENUM_DUMMY4WORD(PIN_SENSOR_CFG) +} PIN_SENSOR_CFG; + +/** + PIN config for Sensor2 + + @note For pinmux_init() with PIN_FUNC_SENSOR2.\n + For example, you can use {PIN_FUNC_SENSOR2, PIN_SENSOR2_CFG_CCIR8BITS}\n + to declare sensor2 interface connect a CCIR 8 bits sensor. +*/ +typedef enum +{ + PIN_SENSOR2_CFG_NONE, + PIN_SENSOR2_CFG_CCIR8BITS = 0x08, ///< Backward compatible + PIN_SENSOR2_CFG_CCIR16BITS = 0x10, ///< Backward compatible + PIN_SENSOR2_CFG_MIPI = 0x20, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR2_CFG_LVDS = 0x40, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR2_CFG_LVDS_VDHD = 0x80, ///< Backward compatible + PIN_SENSOR2_CFG_10BITS = 0x100, ///< Backward compatible + + PIN_SENSOR2_CFG_MCLK2 = 0x200, ///< Enable SN_MCLK2 on SBCS0 (S_GPIO[4]) + PIN_SENSOR2_CFG_MES2 = 0x400, ///< Enable ME_SHUT2 on PWM2 (P_GPIO[2]) + PIN_SENSOR2_CFG_MES2_2ND = 0x800, ///< Enable (2nd) ME_SHUT2 on PWM18 (P_GPIO[18]) + PIN_SENSOR2_CFG_MES3 = 0x1000, ///< Enable ME_SHUT3 on PWM3 (P_GPIO[3]) + PIN_SENSOR2_CFG_MES3_2ND = 0x2000, ///< Enable (2nd) ME_SHUT3 on PWM19 (P_GPIO[19]) + + ENUM_DUMMY4WORD(PIN_SENSOR2_CFG) +} PIN_SENSOR2_CFG; + +/** + PIN config for Sensor3 + + @note For pinmux_init() with PIN_FUNC_SENSOR3.\n + For example, you can use {PIN_FUNC_SENSOR3, PIN_SENSOR3_CFG_8BITS}\n + to declare sensor3 interface connect a 8 bits sensor. +*/ +typedef enum +{ + PIN_SENSOR3_CFG_NONE, + PIN_SENSOR3_CFG_8BITS = 0x01, ///< 8 bits sensor. Enable SIE3[0..7]/SIE3_PXCEL/SIE3_VD/SIE3_HD on P_GPIO[0..10] + PIN_SENSOR3_CFG_10BITS = 0x02, ///< 10 bits sensor. + PIN_SENSOR3_CFG_12BITS = 0x04, ///< 12 bits sensor. + PIN_SENSOR3_CFG_16BITS = 0x08, ///< 16 bits sensor. + PIN_SENSOR3_CFG_MIPI = 0x10, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR3_CFG_LVDS = 0x20, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR3_CFG_MCLK2 = 0x100, ///< MCLK2 + + ENUM_DUMMY4WORD(PIN_SENSOR3_CFG) +} PIN_SENSOR3_CFG; + +/** + PIN config for Sensor4 + + @note For pinmux_init() with PIN_FUNC_SENSOR4.\n + For example, you can use {PIN_FUNC_SENSOR4, xxxx} +*/ +typedef enum +{ + PIN_SENSOR4_CFG_NONE, + PIN_SENSOR4_CFG_8BITS = 0x01, ///< Backward compatible + PIN_SENSOR4_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR4_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR4_CFG_MCLK2 = 0x10, ///< MCLK2 + + ENUM_DUMMY4WORD(PIN_SENSOR4_CFG) +} PIN_SENSOR4_CFG; + +/** + PIN config for Sensor5 + + @note For pinmux_init() with PIN_FUNC_SENSOR5.\n + For example, you can use {PIN_FUNC_SENSOR5, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR5_CFG_NONE, + PIN_SENSOR5_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR5_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR5_CFG_MCLK2 = 0x10, ///< MCLK2 + + ENUM_DUMMY4WORD(PIN_SENSOR5_CFG) +} PIN_SENSOR5_CFG; + +/** + PIN config for Sensor6 + + @note For pinmux_init() with PIN_FUNC_SENSOR6.\n + For example, you can use {PIN_FUNC_SENSOR6, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR6_CFG_NONE, + PIN_SENSOR6_CFG_8BITS = 0x01, ///< 8 bit sensor + PIN_SENSOR6_CFG_16BITS= 0x02, ///< 16 bit sensor + PIN_SENSOR6_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR6_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR6_CFG_MCLK2 = 0x10, ///< + + ENUM_DUMMY4WORD(PIN_SENSOR6_CFG) +} PIN_SENSOR6_CFG; + +/** + PIN config for Sensor7 + + @note For pinmux_init() with PIN_FUNC_SENSOR7.\n + For example, you can use {PIN_FUNC_SENSOR7, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR7_CFG_NONE, + PIN_SENSOR7_CFG_8BITS = 0x01, ///< 8 bit sensor + PIN_SENSOR7_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR7_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR7_CFG_MCLK2 = 0x10, ///< + + ENUM_DUMMY4WORD(PIN_SENSOR7_CFG) +} PIN_SENSOR7_CFG; + +/** + PIN config for Sensor8 + + @note For pinmux_init() with PIN_FUNC_SENSOR8.\n + For example, you can use {PIN_FUNC_SENSOR8, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR8_CFG_NONE, + PIN_SENSOR8_CFG_8BITS = 0x01, ///< 8 bit sensor + PIN_SENSOR8_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR8_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR8_CFG_MCLK2 = 0x10, ///< + + ENUM_DUMMY4WORD(PIN_SENSOR8_CFG) +} PIN_SENSOR8_CFG; + + +/** + PIN config for MIPI/LVDS + + @note For pinmux_init() with PIN_FUNC_MIPI_LVDS.\n + For example, you can use {PIN_FUNC_MIPI_LVDS, PIN_MIPI_LVDS_CFG_CLK0|PIN_MIPI_LVDS_CFG_DAT0|PIN_MIPI_LVDS_CFG_DAT4|PIN_MIPI_LVDS_CFG_DAT7|PIN_MIPI_LVDS_CFG_DAT9}\n + to declare LVDS/MIPI connect sensor with CLK0/D0/D4/D7/D9 lanes. +*/ +typedef enum +{ + PIN_MIPI_LVDS_CFG_NONE, + + PIN_MIPI_LVDS_CFG_CLK0 = 0x1, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK1 = 0x2, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK2 = 0x4, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK3 = 0x8, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK4 = 0x10, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK5 = 0x20, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK6 = 0x40, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK7 = 0x80, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + + PIN_MIPI_LVDS_CFG_DAT0 = 0x100, ///< DATA lane 0. Enable HSI_D0N/HSI_D0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT1 = 0x200, ///< DATA lane 1. Enable HSI_D1N/HSI_D1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT2 = 0x400, ///< DATA lane 2. Enable HSI_D2N/HSI_D2P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT3 = 0x800, ///< DATA lane 3. Enable HSI_D3N/HSI_D3P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT4 = 0x1000, ///< DATA lane 4. Enable HSI_D4N/HSI_D4P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT5 = 0x2000, ///< DATA lane 5. Enable HSI_D5N/HSI_D5P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT6 = 0x4000, ///< DATA lane 6. Enable HSI_D6N/HSI_D6P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT7 = 0x8000, ///< DATA lane 7. Enable HSI_D7N/HSI_D7P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT8 = 0x10000, ///< Backward compatible + PIN_MIPI_LVDS_CFG_DAT9 = 0x20000, ///< Backward compatible + + ENUM_DUMMY4WORD(PIN_MIPI_LVDS_CFG) +} PIN_MIPI_LVDS_CFG; + +/** + PIN config for I2C + + @note For pinmux_init() with PIN_FUNC_I2C.\n + For example, you can use {PIN_FUNC_I2C, PIN_I2C_CFG_CH1|PIN_I2C_CFG_CH1_2ND_PINMUX}\n + to declare I2C channel1 both output to 1st and 2nd pinmux location. +*/ +typedef enum +{ + PIN_I2C_CFG_NONE, + PIN_I2C_CFG_CH1 = 0x1, ///< Enable channel 1. + PIN_I2C_CFG_CH1_2ND_PINMUX = 0x2, ///< Enable 2nd pinmux of channel 1. + PIN_I2C_CFG_CH2 = 0x10, ///< Enable channel 2. + PIN_I2C_CFG_CH2_2ND_PINMUX = 0x20, ///< Enable 2nd pinmux of channel 2. + PIN_I2C_CFG_CH3 = 0x100, ///< Enable channel 3. + PIN_I2C_CFG_CH3_2ND_PINMUX = 0x200, ///< Enable 2nd pinmux of channel 3. + PIN_I2C_CFG_CH3_3RD_PINMUX = 0x400, ///< Enable 3nd pinmux of channel 3. + PIN_I2C_CFG_CH4 = 0x1000, ///< Enable channel 4. + PIN_I2C_CFG_CH4_2ND_PINMUX = 0x2000, ///< Enable 2nd pinmux of channel 4. + PIN_I2C_CFG_CH4_3RD_PINMUX = 0x4000, ///< Enable 3nd pinmux of channel 4. + PIN_I2C_CFG_CH4_4TH_PINMUX = 0x8000, ///< Enable 4th pinmux of channel 4. + PIN_I2C_CFG_CH5 = 0x10000, ///< Enable channel 5. + PIN_I2C_CFG_CH5_2ND_PINMUX = 0x20000, ///< Enable 2nd pinmux of channel 5. + + ENUM_DUMMY4WORD(PIN_I2C_CFG) +} PIN_I2C_CFG; + +/** + PIN config for SIF + + *note For pinmux_init() with PIN_FUNC_SIF.\n + For example, you can use {PIN_FUNC_SIF, PIN_SIF_CFG_CH0|PIN_SIF_CFG_CH2}\n + to declare SIF channel0 and channel2 pinmux are enabled. +*/ +typedef enum +{ + PIN_SIF_CFG_NONE, + + PIN_SIF_CFG_CH0 = 0x01, ///< Enable SIF channel 0. Enable SN_CS0/SN_SCK0/SN_DAT0 (L_GPIO 27/28/29) + PIN_SIF_CFG_CH0_2ND_PINMUX = 0x02, ///< Enable SIF channel 0 2'nd pinmux. Enable SN_CS0/SN_SCK0/SN_SAT0 (P_GPIO 16/18/19) + PIN_SIF_CFG_CH0_3RD_PINMUX = 0x04, ///< Enable SIF channel 0 3'rd pinmux. Enable SN_CS0/SN_SCK0/SN_SAT0 (P_GPIO 17/18/19) + + PIN_SIF_CFG_CH1 = 0x08, ///< Enable SIF channel 1. Enable SN_CS1/SN_SCK1/SN_DAT1 (L_GPIO 30/31/32) + PIN_SIF_CFG_CH1_2ND_PINMUX = 0x10, ///< Backward compatible + + PIN_SIF_CFG_CH2 = 0x20, ///< Enable SIF channel 2. Enable SB_CS2/SB_CK23/SB_DAT23 (P_GPIO 30/32/33) + PIN_SIF_CFG_CH2_2ND_PINMUX = 0x40, ///< Enable SIF channel 2 2'nd pinmux. Enable SB_CS2/SB_CK23/SB_DAT23 (P_GPIO 8/10/11) + + PIN_SIF_CFG_CH3 = 0x80, ///< Enable SIF channel 3. Enable SB_CS3/SB_CK23/SB_DAT23 (P_GPIO 31/32/33) + PIN_SIF_CFG_CH3_2ND_PINMUX = 0x100, ///< Enable SIF channel 3 2'nd pinmux. Enable SB_CS2/SB_CK23/SB_DAT23 (P_GPIO 9/10/11) + + PIN_SIF_CFG_CH4 = 0x200, ///< Enable SIF channel 4. Enable SB_CS4/SB_CK45/SB_DAT45 (P_GPIO 24/26/27) + + PIN_SIF_CFG_CH5 = 0x400, ///< Enable SIF channel 5. Enable SB_CS5/SB_CK45/SB_DAT45 (P_GPIO 25/26/27) + + PIN_SIF_CFG_CH6 = 0x800, ///< Enable SIF channel 6. Enable SB_CS6/SB_CK67/SB_DAT67 (S_GPIO 8/9/10) + + PIN_SIF_CFG_CH7 = 0x1000, ///< Enable SIF channel 7. Enable SB_CS7/SB_CK67/SB_DAT67 (S_GPIO 11/8/9) + + ENUM_DUMMY4WORD(PIN_SIF_CFG) +} PIN_SIF_CFG; + +/** + PIN config for UART + + @note For pinmux_init() with PIN_FUNC_UART.\n + For example, you can use {PIN_FUNC_UART, PIN_UART_CFG_CH1}\n + to declare UART1 pinmux is enabled. +*/ +typedef enum +{ + PIN_UART_CFG_NONE, + + PIN_UART_CFG_CH1 = 0x01, ///< Enable channel 1. Enable UART TX and RX + PIN_UART_CFG_CH1_TX = 0x02, ///< Enalbe channel 1. Enable only UART_TX + + PIN_UART_CFG_CH2 = 0x04, ///< Enable channel 2. Enable UART2 TX and RX + PIN_UART_CFG_CH2_CTSRTS = 0x08, ///< Enable channel 2 HW handshake. Enable UART2 CTS and RTS + PIN_UART_CFG_CH2_2ND = 0x10, ///< Enable channel 2 to 2ND pinmux (UART2_2) + + PIN_UART_CFG_CH3 = 0x20, ///< Enable channel 3. Enable UART3 TX and RX + PIN_UART_CFG_CH3_CTSRTS = 0x40, ///< Enable channel 3 HW handshake. Enable UART3 CTS and RTS + PIN_UART_CFG_CH3_2ND = 0x80, ///< Enable channel 3 to 2ND pinmux (UART3_2) + + PIN_UART_CFG_CH4 = 0x100, ///< Enable channel 4. Enable UART4 TX and RX + PIN_UART_CFG_CH4_CTSRTS = 0x200, ///< Enable channel 4 HW handshake. Enable UART4 CTS and RTS + PIN_UART_CFG_CH4_2ND = 0x400, ///< Enable channel 4 to 2ND pinmux (UART4_2) + + ENUM_DUMMY4WORD(PIN_UART_CFG) +} PIN_UART_CFG; + +/** + PIN config for SPI + + @note For pinmux_init() with PIN_FUNC_SPI.\n + For example, you can use {PIN_FUNC_SPI, PIN_SPI_CFG_CH1|PIN_SPI_CFG_CH3}\n + to declare SPI channel1 and channel3 are enabled. +*/ +typedef enum +{ + PIN_SPI_CFG_NONE, + + PIN_SPI_CFG_CH1 = 0x1, ///< Enable channel 1. Enable SPI_DO/SPI_CLK/SPI_CS on MC[0]/MC[2]/MC8 (C_GPIO[0]/C_GPIO[2]/C_GPIO[8]) + PIN_SPI_CFG_CH1_2BITS = 0x2, ///< Enable channel 1 with 2 bits mode. Enable SPI_DO/SPI_DI/SPI_CLK/SPI_CS on MC[0..2]/MC8 (C_GPIO[0..2]/C_GPIO[8]) + PIN_SPI_CFG_CH1_4BITS = 0x4, ///< Backward compatible + PIN_SPI_CFG_CH1_2ND_PINMUX = 0x8, ///< Enable 2nd pinmux of channel 1. + + PIN_SPI_CFG_CH2 = 0x10, ///< Enable channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO on SPI_CS/SPI_CLK/SPI_DO(P_GPIO[35..37]) + PIN_SPI_CFG_CH2_2BITS = 0x20, ///< Enable channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO/SPI2_DI on SPI_CS/SPI_CLK/SPI_DO/SPI_DI(P_GPIO[35..38]) + PIN_SPI_CFG_CH2_2ND_PINMUX = 0x40, ///< Enable 2nd pinmux of channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO/SPI2_DI on (P_GPIO[16..19]) + PIN_SPI_CFG_CH2_3RD_PINMUX = 0x80, ///< Enable 3rd pinmux of channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO/SPI2_DI on (P_GPIO[16..19]) + + + PIN_SPI_CFG_CH3 = 0x100, ///< Enable channel 3. Eanble SPI3_CS/SPI3_CLK/SPI3_DO on SB_CS2/SB_CK23/SB_DAT23 (P_GPIO[23]/P_GPIO[25..26]) + PIN_SPI_CFG_CH3_2BITS = 0x200, ///< Enable channel 3. Eanble SPI3_CS/SPI3_DI/SPI3_CLK/SPI3_DO on SB_CS2/SB_CS3/SB_CK23/SB_DAT23 (P_GPIO[23..26]) + PIN_SPI_CFG_CH3_2ND_PINMUX = 0x400, ///< Enable 2nd pinmux of channel 3. Enable SPI3_CLK/SPI3_CS/SPI3_DO/SPI3_DI on PWM[12..15] (P_GPIO[12..15]) + PIN_SPI_CFG_CH3_3RD_PINMUX = 0x800, ///< Backward compatible + PIN_SPI_CFG_CH3_RDY = 0x1000, + PIN_SPI_CFG_CH3_RDY_2ND_PINMUX = 0x2000, + + PIN_SPI_CFG_CH4 = 0x10000, ///< Enable channel 4. Eanble SPI4_CS/SPI4_CLK/SPI4_DO on MC[28..29]/MC[31] (C_GPIO[28..29]/C_GPIO[31]) + PIN_SPI_CFG_CH4_2BITS = 0x20000, ///< Enable channel 4. Eanble SPI4_CS/SPI4_DI/SPI4_CLK/SPI4_DO on MC[28..31] (C_GPIO[28..31]) + PIN_SPI_CFG_CH4_2ND_PINMUX = 0x40000, ///< Enable 2nd pinmux of channel 4. Enable SPI4_CLK/SPI4_CS/SPI4_DO/SPI4_DI on PWM[8..11] (P_GPIO[8..11]) + PIN_SPI_CFG_CH4_RDY = 0x80000, ///< Backward compatible + PIN_SPI_CFG_CH4_3RD_PINMUX = 0x100000, ///< Enable 3rd pinmux of channel 4. + + PIN_SPI_CFG_CH5 = 0x1000000,///< Backward compatible + PIN_SPI_CFG_CH5_2BITS = 0x2000000,///< Backward compatible + PIN_SPI_CFG_CH5_2ND_PINMUX = 0x4000000,///< Backward compatible + + ENUM_DUMMY4WORD(PIN_SPI_CFG) +} PIN_SPI_CFG; + +/** + PIN config for REMOTE + + @note For pinmux_init() with PIN_FUNC_REMOTE.\n + For example, you can use {PIN_FUNC_REMOTE, PIN_REMOTE_CFG_CH1}\n + to declare remote pinmux is enabled. +*/ +typedef enum +{ + PIN_REMOTE_CFG_NONE, + PIN_REMOTE_CFG_CH1, ///< Enable remote rx channel 1. Enable REMOTE_RX (on P_GPIO[39]) + + ENUM_DUMMY4WORD(PIN_REMOTE_CFG) +} PIN_REMOTE_CFG; + +/** + PIN config for PWM + + @note For pinmux_init() with PIN_FUNC_PWM.\n + For example, you can use {PIN_FUNC_PWM, PIN_PWM_CFG_PWM0|PIN_PWM_CFG_PWM1|PIN_PWM_CFG_PWM2|PIN_PWM_CFG_PWM3}\n + to declare your system need PWM channel0/1/2/3. +*/ +typedef enum +{ + PIN_PWM_CFG_NONE, + PIN_PWM_CFG_PWM0 = 0x01, ///< Enable PWM0 (on P_GPIO[0]) + PIN_PWM_CFG_PWM1 = 0x02, ///< Enable PWM1 (on P_GPIO[1]) + PIN_PWM_CFG_PWM2 = 0x04, ///< Enable PWM2 (on P_GPIO[2]) + PIN_PWM_CFG_PWM3 = 0x08, ///< Enable PWM3 (on P_GPIO[3]) + PIN_PWM_CFG_PWM4 = 0x10, ///< Enable PWM4 (on P_GPIO[4]) + PIN_PWM_CFG_PWM5 = 0x20, ///< Enable PWM5 (on P_GPIO[5]) + PIN_PWM_CFG_PWM6 = 0x40, ///< Enable PWM6 (on P_GPIO[6]) + PIN_PWM_CFG_PWM7 = 0x80, ///< Enable PWM7 (on P_GPIO[7]) + PIN_PWM_CFG_PWM8 = 0x100, ///< Enable PWM8 (on P_GPIO[8]) + PIN_PWM_CFG_PWM9 = 0x200, ///< Enable PWM9 (on P_GPIO[9]) + PIN_PWM_CFG_PWM10= 0x400, ///< Enable PWM10 (on P_GPIO[10]) + PIN_PWM_CFG_PWM11= 0x800, ///< Enable PWM11 (on P_GPIO[11]) + PIN_PWM_CFG_PWM12= 0x1000, ///< Enable PWM12 (on P_GPIO[12]) + PIN_PWM_CFG_PWM13= 0x2000, ///< Enable PWM13 (on P_GPIO[13]) + PIN_PWM_CFG_PWM14= 0x4000, ///< Enable PWM14 (on P_GPIO[14]) + PIN_PWM_CFG_PWM15= 0x8000, ///< Enable PWM15 (on P_GPIO[15]) + PIN_PWM_CFG_PWM16= 0x10000, ///< Enable PWM16 (on P_GPIO[16]) + PIN_PWM_CFG_PWM17= 0x20000, ///< Enable PWM17 (on P_GPIO[17]) + PIN_PWM_CFG_PWM18= 0x40000, ///< Enable PWM18 (on P_GPIO[18]) + PIN_PWM_CFG_PWM19= 0x80000, ///< Enable PWM19 (on P_GPIO[19]) + + PIN_PWM_CFG_CCNT = 0x1000000, ///< Enable PICNT_1 + PIN_PWM_CFG_CCNT_2ND = 0x2000000, ///< Enable PICNT_2 + PIN_PWM_CFG_CCNT2 = 0x4000000, ///< Enable PICNT2_1 + PIN_PWM_CFG_CCNT2_2ND = 0x8000000, ///< Enable PICNT2_2 + PIN_PWM_CFG_CCNT3 = 0x10000000, ///< Enable PICNT3 + PIN_PWM_CFG_CCNT3_2ND = 0x20000000, ///< Enable PICNT3_2 + PIN_PWM_CFG_CCNT4 = 0x40000000, ///< Enable PICNT4_1 + PIN_PWM_CFG_CCNT4_2ND = 0x80000000, ///< Enable PICNT4_2 + + ENUM_DUMMY4WORD(PIN_PWM_CFG) +} PIN_PWM_CFG; + +/** + PIN config for AUDIO + + @note For pinmux_init() with PIN_FUNC_AUDIO.\n + For example, you can use {PIN_FUNC_AUDIO, PIN_AUDIO_CFG_I2S|PIN_AUDIO_CFG_MCLK}\n + to declare pinmux of I2S and I2S MCLK are enabled. +*/ +typedef enum +{ + PIN_AUDIO_CFG_NONE, + PIN_AUDIO_CFG_I2S = 0x01, ///< Enable I2S channel. Enable I2S_BCK/I2S_FCK/I2S_DO/I2S_DI/ (on P_GPIO[31..34]) + PIN_AUDIO_CFG_I2S_2ND_PINMUX = 0x02,///< Backward compatible + + PIN_AUDIO_CFG_MCLK = 0x10, ///< Enable audio MCLK. Enable I2S_MCLK (on P_GPIO[20]) + PIN_AUDIO_CFG_MCLK_2ND_PINMUX = 0x20,///< Backward compatible + + ENUM_DUMMY4WORD(PIN_AUDIO_CFG) +} PIN_AUDIO_CFG; + +/** + PIN config of LCD modes + + @note For pinmux_init() with PIN_FUNC_LCD or PIN_FUNC_LCD2.\n + For example, you can use {PIN_FUNC_LCD, PINMUX_DISPMUX_SEL_LCD | PINMUX_LCDMODE_RGB_SERIAL}\n + to tell display object that PIN_FUNC_LCD is located on primary LCD pinmux,\n + and it's LCD mode is RGB serial. +*/ +typedef enum +{ + PINMUX_LCDMODE_RGB_SERIAL = 0, ///< LCD MODE is RGB Serial or UPS051 + PINMUX_LCDMODE_RGB_PARALL = 1, ///< LCD MODE is RGB Parallel (888) + PINMUX_LCDMODE_YUV640 = 2, ///< LCD MODE is YUV640 + PINMUX_LCDMODE_YUV720 = 3, ///< LCD MODE is YUV720 + PINMUX_LCDMODE_RGBD360 = 4, ///< LCD MODE is RGB Dummy 360 + PINMUX_LCDMODE_RGBD320 = 5, ///< LCD MODE is RGB Dummy 320 + PINMUX_LCDMODE_RGB_THROUGH = 6, ///< LCD MODE is RGB through mode + PINMUX_LCDMODE_CCIR601 = 7, ///< LCD MODE is CCIR601 + PINMUX_LCDMODE_CCIR656 = 8, ///< LCD MODE is CCIR656 + PINMUX_LCDMODE_RGB_PARALL666 = 9, ///< LCD MODE is RGB Parallel 666 + PINMUX_LCDMODE_RGB_PARALL565 = 10, ///< LCD MODE is RGB Parallel 565 + PINMUX_LCDMODE_RGB_PARALL_DELTA = 11, ///< LCD MODE is RGB Parallel Delta + PINMUX_LCDMODE_MIPI = 12, ///< LCD MODE is MIPI Display + + PINMUX_LCDMODE_MI_OFFSET = 32, ///< Memory LCD MODE offset + PINMUX_LCDMODE_MI_FMT0 = 32+0, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT1 = 32+1, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT2 = 32+2, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT3 = 32+3, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT4 = 32+4, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT5 = 32+5, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT6 = 32+6, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT7 = 32+7, ///< LCD MODE is Memory(Parallel Interface) 9bits + PINMUX_LCDMODE_MI_FMT8 = 32+8, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT9 = 32+9, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT10 = 32+10, ///< LCD MODE is Memory(Parallel Interface) 18bits + PINMUX_LCDMODE_MI_FMT11 = 32+11, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT12 = 32+12, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT13 = 32+13, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT14 = 32+14, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_SERIAL_BI = 32+20, ///< LCD MODE is Serial Interface bi-direction + PINMUX_LCDMODE_MI_SERIAL_SEP = 32+21, ///< LCD MODE is Serial Interface separation + + PINMUX_LCDMODE_AUTO_PINMUX = 0x01<<22, ///< Set display device to GPIO mode when display device is closed. Select this filed will inform display object to switch to GPIO when display device is closed. + + + PINMUX_HDMIMODE_OFFSET = 64, ///< HDMI MODE offset + PINMUX_HDMIMODE_640X480P60 = 64+1, ///< HDMI Video format is 640x480 & Progressive 60fps + PINMUX_HDMIMODE_720X480P60 = 64+2, ///< HDMI Video format is 720x480 & Progressive 60fps & 4:3 + PINMUX_HDMIMODE_720X480P60_16X9 = 64+3, ///< HDMI Video format is 720x480 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_1280X720P60 = 64+4, ///< HDMI Video format is 1280x720 & Progressive 60fps + PINMUX_HDMIMODE_1920X1080I60 = 64+5, ///< HDMI Video format is 1920x1080 & Interlaced 60fps + PINMUX_HDMIMODE_720X480I60 = 64+6, ///< HDMI Video format is 720x480 & Interlaced 60fps + PINMUX_HDMIMODE_720X480I60_16X9 = 64+7, ///< HDMI Video format is 720x480 & Interlaced 60fps & 16:9 + PINMUX_HDMIMODE_720X240P60 = 64+8, ///< HDMI Video format is 720x240 & Progressive 60fps + PINMUX_HDMIMODE_720X240P60_16X9 = 64+9, ///< HDMI Video format is 720x240 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_1440X480I60 = 64+10, ///< HDMI Video format is 1440x480 & Interlaced 60fps + PINMUX_HDMIMODE_1440X480I60_16X9 = 64+11, ///< HDMI Video format is 1440x480 & Interlaced 60fps & 16:9 + PINMUX_HDMIMODE_1440X240P60 = 64+12, ///< HDMI Video format is 1440x240 & Progressive 60fps + PINMUX_HDMIMODE_1440X240P60_16X9 = 64+13, ///< HDMI Video format is 1440x240 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_1440X480P60 = 64+14, ///< HDMI Video format is 1440x480 & Progressive 60fps + PINMUX_HDMIMODE_1440X480P60_16X9 = 64+15, ///< HDMI Video format is 1440x480 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_720X576P50 = 64+17, ///< HDMI Video format is 720x576 & Progressive 50fps + PINMUX_HDMIMODE_720X576P50_16X9 = 64+18, ///< HDMI Video format is 720x576 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1280X720P50 = 64+19, ///< HDMI Video format is 1280x720 & Progressive 50fps + PINMUX_HDMIMODE_1920X1080I50 = 64+20, ///< HDMI Video format is 1920x1080 & Interlaced 50fps + PINMUX_HDMIMODE_720X576I50 = 64+21, ///< HDMI Video format is 720x576 & Interlaced 50fps + PINMUX_HDMIMODE_720X576I50_16X9 = 64+22, ///< HDMI Video format is 720x576 & Interlaced 50fps & 16:9 + PINMUX_HDMIMODE_720X288P50 = 64+23, ///< HDMI Video format is 720x288 & Progressive 50fps + PINMUX_HDMIMODE_720X288P50_16X9 = 64+24, ///< HDMI Video format is 720x288 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1440X576I50 = 64+25, ///< HDMI Video format is 1440x576 & Interlaced 50fps + PINMUX_HDMIMODE_1440X576I50_16X9 = 64+26, ///< HDMI Video format is 1440x576 & Interlaced 50fps & 16:9 + PINMUX_HDMIMODE_1440X288P50 = 64+27, ///< HDMI Video format is 1440x288 & Progressive 50fps + PINMUX_HDMIMODE_1440X288P50_16X9 = 64+28, ///< HDMI Video format is 1440x288 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1440X576P50 = 64+29, ///< HDMI Video format is 1440x576 & Progressive 50fps + PINMUX_HDMIMODE_1440X576P50_16X9 = 64+30, ///< HDMI Video format is 1440x576 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1920X1080P50 = 64+31, ///< HDMI Video format is 1920x1080 & Progressive 50fps + PINMUX_HDMIMODE_1920X1080P24 = 64+32, ///< HDMI Video format is 1920x1080 & Progressive 24fps + PINMUX_HDMIMODE_1920X1080P25 = 64+33, ///< HDMI Video format is 1920x1080 & Progressive 25fps + PINMUX_HDMIMODE_1920X1080P30 = 64+34, ///< HDMI Video format is 1920x1080 & Progressive 30fps + PINMUX_HDMIMODE_1920X1080I50_VT1250 = 64+39, ///< HDMI Video format is 1920x1080 & Interlaced 50fps & V-total is 1250 lines + PINMUX_HDMIMODE_1920X1080I100 = 64+40, ///< HDMI Video format is 1920x1080 & Interlaced 100fps + PINMUX_HDMIMODE_1280X720P100 = 64+41, ///< HDMI Video format is 1280X720 & Progressive 100fps + PINMUX_HDMIMODE_720X576P100 = 64+42, ///< HDMI Video format is 720X576 & Progressive 100fps + PINMUX_HDMIMODE_720X576P100_16X9 = 64+43, ///< HDMI Video format is 720X576 & Progressive 100fps & 16:9 + PINMUX_HDMIMODE_720X576I100 = 64+44, ///< HDMI Video format is 720X576 & Interlaced 100fps + PINMUX_HDMIMODE_720X576I100_16X9 = 64+45, ///< HDMI Video format is 720X576 & Interlaced 100fps & 16:9 + PINMUX_HDMIMODE_1920X1080I120 = 64+46, ///< HDMI Video format is 1920X1080 & Interlaced 120fps + PINMUX_HDMIMODE_1280X720P120 = 64+47, ///< HDMI Video format is 1280X720 & Progressive 120fps + PINMUX_HDMIMODE_720X480P120 = 64+48, ///< HDMI Video format is 720X480 & Progressive 120fps + PINMUX_HDMIMODE_720X480P120_16X9 = 64+49, ///< HDMI Video format is 720X480 & Progressive 120fps & 16:9 + PINMUX_HDMIMODE_720X480I120 = 64+50, ///< HDMI Video format is 720X480 & Interlaced 120fps + PINMUX_HDMIMODE_720X480I120_16X9 = 64+51, ///< HDMI Video format is 720X480 & Interlaced 120fps & 16:9 + PINMUX_HDMIMODE_720X576P200 = 64+52, ///< HDMI Video format is 720X576 & Progressive 200fps + PINMUX_HDMIMODE_720X576P200_16X9 = 64+53, ///< HDMI Video format is 720X576 & Progressive 200fps & 16:9 + PINMUX_HDMIMODE_720X576I200 = 64+54, ///< HDMI Video format is 720X576 & Interlaced 200fps + PINMUX_HDMIMODE_720X576I200_16X9 = 64+55, ///< HDMI Video format is 720X576 & Interlaced 200fps & 16:9 + PINMUX_HDMIMODE_720X480P240 = 64+56, ///< HDMI Video format is 720X480 & Progressive 240fps + PINMUX_HDMIMODE_720X480P240_16X9 = 64+57, ///< HDMI Video format is 720X480 & Progressive 240fps & 16:9 + PINMUX_HDMIMODE_720X480I240 = 64+58, ///< HDMI Video format is 720X480 & Interlaced 240fps + PINMUX_HDMIMODE_720X480I240_16X9 = 64+59, ///< HDMI Video format is 720X480 & Interlaced 240fps & 16:9 + + PINMUX_DSI_1_LANE_CMD_MODE_RGB565 = 128+0, ///< DSI command mode with RGB565 format + PINMUX_DSI_1_LANE_CMD_MODE_RGB666P = 128+1, ///< DSI command mode with RGB666 packed + PINMUX_DSI_1_LANE_CMD_MODE_RGB666L = 128+2, ///< DSI command mode with RGB666 loosely + PINMUX_DSI_1_LANE_CMD_MODE_RGB888 = 128+3, ///< DSI command mode with RGB888 + + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB565 = 128+4, ///< DSI video sync pulse mode with RGB565 format + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB666P = 128+5, ///< DSI video sync pulse mode with RGB666 packed + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB666L = 128+6, ///< DSI video sync pulse mode with RGB666 loosely + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB888 = 128+7, ///< DSI video sync pulse mode with RGB888 + + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB565 = 128+8, ///< DSI video sync event burst mode with RGB565 format + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB666P = 128+9, ///< DSI video sync event burst mode with RGB666 packed + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB666L = 128+10,///< DSI video sync event burst mode with RGB666 loosely + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB888 = 128+11,///< DSI video sync event burst mode with RGB888 + + PINMUX_DSI_2_LANE_CMD_MODE_RGB565 = 128+12,///< DSI command mode with RGB565 format + PINMUX_DSI_2_LANE_CMD_MODE_RGB666P = 128+13,///< DSI command mode with RGB666 packed + PINMUX_DSI_2_LANE_CMD_MODE_RGB666L = 128+14,///< DSI command mode with RGB666 loosely + PINMUX_DSI_2_LANE_CMD_MODE_RGB888 = 128+15,///< DSI command mode with RGB888 + + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB565 = 128+16,///< DSI video sync pulse mode with RGB565 format + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB666P = 128+17,///< DSI video sync pulse mode with RGB666 packed + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB666L = 128+18,///< DSI video sync pulse mode with RGB666 loosely + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB888 = 128+19,///< DSI video sync pulse mode with RGB888 + + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB565 = 128+20,///< DSI video sync event burst mode with RGB565 format + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB666P = 128+21,///< DSI video sync event burst mode with RGB666 packed + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB666L = 128+22,///< DSI video sync event burst mode with RGB666 loosely + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB888 = 128+23,///< DSI video sync event burst mode with RGB888 + + PINMUX_DSI_4_LANE_CMD_MODE_RGB565 = 128+24,///< DSI command mode with RGB565 format + PINMUX_DSI_4_LANE_CMD_MODE_RGB666P = 128+25,///< DSI command mode with RGB666 packed + PINMUX_DSI_4_LANE_CMD_MODE_RGB666L = 128+26,///< DSI command mode with RGB666 loosely + PINMUX_DSI_4_LANE_CMD_MODE_RGB888 = 128+27,///< DSI command mode with RGB888 + + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB565 = 128+28,///< DSI video sync pulse mode with RGB565 format + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB666P = 128+29,///< DSI video sync pulse mode with RGB666 packed + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB666L = 128+30,///< DSI video sync pulse mode with RGB666 loosely + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB888 = 128+31,///< DSI video sync pulse mode with RGB888 + + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB565 = 128+32,///< DSI video sync event burst mode with RGB565 format + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB666P = 128+33,///< DSI video sync event burst mode with RGB666 packed + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB666L = 128+34,///< DSI video sync event burst mode with RGB666 loosely + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB888 = 128+35,///< DSI video sync event burst mode with RGB888 + + + + ENUM_DUMMY4WORD(PINMUX_LCDINIT) +} PINMUX_LCDINIT; + +/** + PIN config for Parallel MI + + @note For pinmux_init() with PIN_FUNC_LCD or PIN_FUNC_LCD2.\n + For example, you can use {PIN_FUNC_LCD, PINMUX_DISPMUX_SEL_LCD|PINMUX_PMI_CFG_NORMAL|PINMUX_LCDMODE_MI_FMT0}\n + to tell display object that PIN_FUNC_LCD is bound to MI and format is FMT0,\n + and MI is located at primary location. +*/ +typedef enum +{ + PINMUX_PMI_CFG_NORMAL = 0x00, ///< Normal Parallel MI location (at LCD) + PINMUX_PMI_CFG_2ND_PINMUX = 0x01<<26, ///< Secondary Parallel MI location (at LGPIO[12..25]) + + PINMUX_PMI_CFG_MASK = 0x03<<26, + ENUM_DUMMY4WORD(PINMUX_PMI_CFG) +} PINMUX_PMI_CFG; + +/** + PIN config for TV/HDMI + + @note For pinmux_init() for PIN_FUNC_TV or PIN_FUNC_HDMI.\n + For example, you can use {PIN_FUNC_HDMI, PINMUX_TV_HDMI_CFG_NORMAL|PINMUX_HDMIMODE_1280X720P60}\n + to tell display object that HDMI activation will disable PANEL,\n + and HDMI mode is 1280x720 P60. +*/ +typedef enum +{ + PINMUX_TV_HDMI_CFG_GPIO = 0x00, ///< TV activation will disable PINMUX to GPIO + PINMUX_TV_HDMI_CFG_NORMAL = 0x00, ///< TV activation will disable PANEL which shared the same IDE + PINMUX_TV_HDMI_CFG_PINMUX_ON = 0x01<<28, ///< TV activation will keep PINMUX setting + + PINMUX_TV_HDMI_CFG_MASK = 0x03<<28, + ENUM_DUMMY4WORD(PINMUX_TV_HDMI_CFG) +} PINMUX_TV_HDMI_CFG; + +/** + PIN config for HDMI + + @note For pinmux_init() for PIN_FUNC_HDMI.\n + For example, you can use {PIN_FUNC_HDMI, PINMUX_HDMI_CFG_CEC|PINMUX_TV_HDMI_CFG_NORMAL}\n + to declare HDMI CEC pinmux is enabled. +*/ +typedef enum +{ + PINMUX_HDMI_CFG_GPIO = 0x00, ///< HDMI specific PIN to GPIO + PINMUX_HDMI_CFG_HOTPLUG = 0x01<<26, ///< HDMI HOTPLUG. Enable HDMI_PLUG (on P_GPIO[30]) + PINMUX_HDMI_CFG_CEC = 0x02<<26, ///< HDMI CEC. Enable HDMI_CEC (on P_GPIO[27]) + + PINMUX_HDMI_CFG_MASK = 0x03<<26, + ENUM_DUMMY4WORD(PINMUX_HDMI_CFG) +} PINMUX_HDMI_CFG; + +/** + PIN location of LCD + + @note For pinmux_init() with PIN_FUNC_LCD or PIN_FUNC_LCD2.\n + For example, you can use {PIN_FUNC_LCD, PINMUX_DISPMUX_SEL_LCD2|PINMUX_LCDMODE_XXX}\n + to tell display object that PIN_FUNC_LCD is located on secondary LCD pinmux. +*/ +typedef enum +{ + PINMUX_DISPMUX_SEL_NONE = 0x00<<28, ///< PINMUX none + PINMUX_DISPMUX_SEL_LCD = 0x01<<28, ///< PINMUX at LCD interface + PINMUX_DISPMUX_SEL_LCD2 = 0x02<<28, ///< PINMUX at LCD2 interface + + PINMUX_DISPMUX_SEL_MASK = 0x03<<28, + ENUM_DUMMY4WORD(PINMUX_DISPMUX_SEL) +} PINMUX_DISPMUX_SEL; + +/** + PIN config for ETH + + @note For pinmux_init() for PIN_FUNC_ETH.\n + For example, you can use {PIN_FUNC_ETH, PINMUX_ETH_CFG_MII}\n + to select USB as device. +*/ +typedef enum +{ + PIN_ETH_CFG_NONE = 0x00, ///< PINMUX none + PIN_ETH_CFG_MII = 0x01, ///< ETH MII + PIN_ETH_CFG_RMII = 0x02, ///< ETH RMII + PIN_ETH_CFG_GMII = 0x04, ///< ETH GMII + PIN_ETH_CFG_RGMII = 0x08, ///< ETH RGMII + PIN_ETH_CFG_REVMII_10_100 = 0x10, ///< ETH REVMII_10_100 + PIN_ETH_CFG_REVMII_10_1000 = 0x20, ///< ETH REVMII_10_1000 + + ENUM_DUMMY4WORD(PINMUX_ETH_CFG) +} PINMUX_ETH_CFG; + + +/** + Pinmux Function identifier + + @note For pinmux_getDispMode(), pinmux_setPinmux(). +*/ +typedef enum +{ + PINMUX_FUNC_ID_LCD, ///< 1st Panel (LCD), pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + ///< - @b PINMUX_LCD_SEL_CCIR656 + ///< - @b PINMUX_LCD_SEL_CCIR601 + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_6BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_8BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_YCbCr_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_9BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDIO + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDI_SDO + ///< ORed with + ///< - @b PINMUX_LCD_SEL_DE_ENABLE + ///< - @b PINMUX_LCD_SEL_TE_ENABLE + PINMUX_FUNC_ID_LCD2, ///< 2nd Panel (LCD), pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + ///< - @b PINMUX_LCD_SEL_CCIR656 + ///< - @b PINMUX_LCD_SEL_CCIR601 + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_6BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_8BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_YCbCr_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_9BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDIO + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDI_SDO + ///< ORed with + ///< - @b PINMUX_LCD_SEL_DE_ENABLE + PINMUX_FUNC_ID_TV, ///< TV, pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + PINMUX_FUNC_ID_HDMI, ///< HDMI, pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + PINMUX_FUNC_ID_SN_MES0, ///< Sensor MES0, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MES1, ///< Sensor MES1, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MES2, ///< Sensor MES2, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MES3, ///< Sensor MES3, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_FLCTR, ///< Sensor Flash Control, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MCLK, ///< Sensor MCLK, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SPI2, ///< SPI channel2 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_SPI3, ///< SPI channel3 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_SPI4, ///< SPI channel4 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_SPI5, ///< SPI channel5 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_COUNT, //< Total function count + + ENUM_DUMMY4WORD(PINMUX_FUNC_ID) +} PINMUX_FUNC_ID; + +/** + Pinmux selection for LCD + + @note For PINMUX_FUNC_ID_LCD, PINMUX_FUNC_ID_LCD2 +*/ +typedef enum +{ + PINMUX_LCD_SEL_GPIO, ///< GPIO + PINMUX_LCD_SEL_CCIR656, ///< CCIR-656 8 bits. Enable CCIR_YC[0..7]/CCIR_CLK on LCD[0..8] (L_GPIO[0..8]) + PINMUX_LCD_SEL_CCIR656_16BITS, ///< CCIR-656 16 bits. Enable CCIR_Y[0..7]/CCIR_CLK/CCIR_C[0..7] on LCD[0..8]/LCD[12..19] (L_GPIO[0..8]/L_GPIO[12..19]) + PINMUX_LCD_SEL_CCIR601, ///< CCIR-601 8 bits. Enable CCIR_YC[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD on LCD[0..10] (L_GPIO[0..10]) + PINMUX_LCD_SEL_CCIR601_16BITS, ///< CCIR-601 16 bits. Enable CCIR_Y[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD/CCIR_C[0..7] on LCD[0..19] (L_GPIO[0..19]) + PINMUX_LCD_SEL_SERIAL_RGB_6BITS, ///< Serial RGB 6 bits. Enable RGB_D[2..7]/RGB_CLK/RGB_VD/RGB_HD on LCD[2..10] (L_GPIO[2..10]) + PINMUX_LCD_SEL_SERIAL_RGB_8BITS, ///< Serial RGB 8 bits. Enable RGB_D[0..7]/RGB_CLK/RGB_VD/RGB_HD on LCD[0..10] (L_GPIO[0..10]) + PINMUX_LCD_SEL_SERIAL_YCbCr_8BITS, ///< Serial YCbCr 8 bits. Enable CCIR_YC[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD on LCD[0..10] (L_GPIO[0..10]) + PINMUX_LCD_SEL_PARALLE_RGB565, ///< Parallel RGB565. Enable RGB_C0_[0..4]/RGB_DCLK/RGB_VS/RGB_HS/RGB_C1_[0..5]/RGB_C2_[0..4] on LCD[3..10]/LCD[14..19]/LCD[23..27] (L_GPIO[3..10]/L_GPIO[14..19]/L_GPIO[23..27]) + PINMUX_LCD_SEL_PARALLE_RGB666, ///< Parallel RGB666. Enable RGB_C0_[0..5]/RGB_DCLK/RGB_VS/RGB_HS/RGB_C1_[0..5]/RGB_C2_[0..5] on LCD[2..10]/LCD[14..19]/LCD[22..27] (L_GPIO[2..10]/L_GPIO[14..19]/L_GPIO[22..27]) + PINMUX_LCD_SEL_PARALLE_RGB888, ///< Parallel RGB888. Enable RGB_C0_[0..7]/RGB_DCLK/RGB_VS/RGB_HS/RGB_C1_[0..7]/RGB_C2_[0..7] on LCD[0..10]/LCD[12..27] (L_GPIO[2..10]/L_GPIO[12..27]) + PINMUX_LCD_SEL_RGB_16BITS, ///< RGB 16 bits. Enable CCIR_Y[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD/CCIR_C[0..7] on LCD[0..19] (L_GPIO[0..19]) + PINMUX_LCD_SEL_PARALLE_MI_8BITS, ///< Parallel MI 8 bits. + ///< When PINMUX_PMI_CFG_NORMAL is set, Enable MPU_D[0..7]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..12] (L_GPIO[0..7]/L_GPIO[9..12]) + ///< When PINMUX_PMI_CFG_2ND_PINMUX is set, Enable MPU2_RS/MPU2_CS/MPU2_D[0..7]/MPU2_WR/MPU2_RD on LCD[12..22]/LCD[24] (L_GPIO[12..22]/L_GPIO[24]) + PINMUX_LCD_SEL_PARALLE_MI_9BITS, ///< Parallel MI 9 bits. + ///< When PINMUX_PMI_CFG_NORMAL is set, Enable MPU_D[0..8]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..13] (L_GPIO[0..7]/L_GPIO[9..13]) + ///< When PINMUX_PMI_CFG_2ND_PINMUX is set, Enable MPU2_RS/MPU2_CS/MPU2_D[0..8]/MPU2_WR/MPU2_RD on LCD[12..24] (L_GPIO[12..24]) + PINMUX_LCD_SEL_PARALLE_MI_16BITS, ///< Parallel MI 16 bits. Enable MPU_D[0..15]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..20] (L_GPIO[0..7]/L_GPIO[9..20]) + PINMUX_LCD_SEL_PARALLE_MI_18BITS, ///< Parallel MI 18 bits. Enable MPU_D[0..17]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..22] (L_GPIO[0..7]/L_GPIO[9..22]) + PINMUX_LCD_SEL_SERIAL_MI_SDIO, ///< Serial MI SDIO bi-direction. Enable MPU_CS/MPU_RS/MPU_CLK/MPU_SDIO on LCD[15..18] (L_GPIO[15..18]) + PINMUX_LCD_SEL_SERIAL_MI_SDI_SDO, ///< Serial MI SDI/SDO seperate. Enable MPU_SDO/MPU_SDI/MPU_CS/MPU_RS/MPU_CLK on LCD[13..17] (L_GPIO[13..17]) + PINMUX_LCD_SEL_MIPI, ///< MIPI DSI + + PINMUX_LCD_SEL_TE_ENABLE = 0x01<<23, ///< TE Enable (For Parallel/Serial MI) + ///< When normal (PINMUX_PMI_CFG_NORMAL) parallel MI, enable MPU_TE on LCD8 (L_GPIO[8]). + ///< When 2nd (PINMUX_PMI_CFG_2ND_PINMUX) parallel MI, enable MPU_TE on LCD25 (L_GPIO[25]). + ///< When serial MI, enable MI_TE on LCD19 (L_GPIO[19]). + PINMUX_LCD_SEL_DE_ENABLE = 0x01<<24, ///< DE Enable (For CCIR656 8/16bits, CCIR601 16bits, Serial RGB 6/8bits, Serial YCbCr 8 bits, RGB 16 bits) + ///< When corresponding item in pinmux_init() is set with PINMUX_DISPMUX_SEL_LCD, enable CCIR_DE on LCD11 (L_GPIO[11]). + ///< When corresponding item in pinmux_init() is set with PINMUX_DISPMUX_SEL_LCD2, enable CCIR2_DE on LCD23 (L_GPIO[23]). + PINMUX_LCD_SEL_HVLD_VVLD = 0x01<<25, ///< HVLD/VVLD Enable (For CCIR-601 8 bits). Enable CCIR_HVLD/CCIR_VVLD on LCD[12..13] (L_GPIO[12..13]) + PINMUX_LCD_SEL_FIELD = 0x01<<26, ///< FIELD Enable (For CCIR-601 8 bits). Enable CCIR_FIELD on LCD14 (L_GPIO[14]) + + PINMUX_LCD_SEL_FEATURE_MSK = 0x0F<<23, + + ENUM_DUMMY4WORD(PINMUX_LCD_SEL) +} PINMUX_LCD_SEL; + +/** + Pinmux selection for Storage + + @note For PINMUX_FUNC_ID_SDIO, PINMUX_FUNC_ID_SPI, PINMUX_FUNC_ID_NAND +*/ +typedef enum +{ + PINMUX_STORAGE_SEL_INACTIVE, ///< Inactive storage + PINMUX_STORAGE_SEL_ACTIVE, ///< Active storage + PINMUX_STORAGE_SEL_INEXIST, ///< Inexist storage + PINMUX_STORAGE_SEL_EXIST, ///< Exist storage + ENUM_DUMMY4WORD(PINMUX_STORAGE_SEL) +} PINMUX_STORAGE_SEL; + +/** + Pinmux selection for sensor + + @note For PINMUX_FUNC_ID_SN_MES0, PINMUX_FUNC_ID_SN_MES1, PINMUX_FUNC_ID_SN_FLCTR +*/ +typedef enum +{ + PINMUX_SENSOR_SEL_INACTIVE, ///< Inactive + PINMUX_SENSOR_SEL_ACTIVE, ///< Active + ENUM_DUMMY4WORD(PINMUX_SENSOR_SEL) +} PINMUX_SENSOR_SEL; + +/** + Pinmux selection for sensor + + @note For PINMUX_FUNC_ID_USB_VBUSI +*/ +typedef enum +{ + PINMUX_USB_SEL_INACTIVE, ///< Inactive + PINMUX_USB_SEL_ACTIVE, ///< Active + ENUM_DUMMY4WORD(PINMUX_USB_SEL) +} PINMUX_USB_SEL; + +/** + Pinmux selection for SPI + + @note For PINMUX_FUNC_ID_SPI2, PINMUX_FUNC_ID_SPI3 +*/ +typedef enum +{ + PINMUX_SPI_SEL_INACTIVE, ///< Inactive + PINMUX_SPI_SEL_ACTIVE, ///< Active + ENUM_DUMMY4WORD(PINMUX_SPI_SEL) +} PINMUX_SPI_SEL; + +/** + Pinmux group + + @note For pinmux_init() +*/ +typedef struct +{ + PIN_FUNC pin_function; ///< PIN Function group + UINT32 config; ///< Configuration for pinFunction +} PIN_GROUP_CONFIG; + +/* + Pinmux Function identifier for driver only + + @note For pinmux_setPinmux(). +*/ +typedef enum +{ + PINMUX_FUNC_ID_SDIO = 0x8000000, ///< SDIO, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_SDIO2, ///< SDIO2, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_SDIO3, ///< SDIO3, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_SPI, ///< SPI, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_NAND, ///< NAND, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_BMC, ///< BMC, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_USB_VBUSI, ///< USB VBUSI, pinmux can be: + ///< - @b PINMUX_USB_SEL_INACTIVE + ///< - @b PINMUX_USB_SEL_ACTIVE + PINMUX_FUNC_ID_USB2_VBUSI, ///< USB2 VBUSI, pinmux can be: + ///< - @b PINMUX_USB_SEL_INACTIVE + ///< - @b PINMUX_USB_SEL_ACTIVE + PINMUX_FUNC_ID_I2C1_1ST, ///< I2C channel1 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C1_2ND, ///< I2C channel1 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C2_1ST, ///< I2C channel2 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C2_2ND, ///< I2C channel2 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C3_1ST, ///< I2C channel3 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C3_2ND, ///< I2C channel3 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C3_3RD, ///< I2C channel3 3rd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_1ST, ///< I2C channel4 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_2ND, ///< I2C channel4 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_3RD, ///< I2C channel4 3rd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_4TH, ///< I2C channel4 4th pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C5_1ST, ///< I2C channel5 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C5_2ND, ///< I2C channel5 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_SN_VDHD, ///< SN VD/HD, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_0, ///< PWM channel 0 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_1, ///< PWM channel 1 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_2, ///< PWM channel 2 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_3, ///< PWM channel 3 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_4, ///< PWM channel 4 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_5, ///< PWM channel 5 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_6, ///< PWM channel 6 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_7, ///< PWM channel 7 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_8, ///< PWM channel 8 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_9, ///< PWM channel 9 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_10, ///< PWM channel 10 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_11, ///< PWM channel 11 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_12, ///< PWM channel 12 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_13, ///< PWM channel 13 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_14, ///< PWM channel 14 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_15, ///< PWM channel 15 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_16, ///< PWM channel 16 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_17, ///< PWM channel 17 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_18, ///< PWM channel 18 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_19, ///< PWM channel 19 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_0, ///< SIF channel 0 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_1, ///< SIF channel 1 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_2, ///< SIF channel 2 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_3, ///< SIF channel 3 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_4, ///< SIF channel 4 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_5, ///< SIF channel 5 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_6, ///< SIF channel 6 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_7, ///< SIF channel 7 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_UART_1, ///< UART channel 1 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_UART_2, ///< UART channel 2 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_UART_3, ///< UART channel 3 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_UART_4, ///< UART channel 4 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_I2S, ///< I2S + ///< - @b PINMUX_I2S_SEL_INACTIVE + ///< - @b PINMUX_I2S_SEL_ACTIVE + PINMUX_FUNC_ID_I2S_MCLK, ///< I2S MCLK + ///< - @b PINMUX_I2S_SEL_INACTIVE + ///< - @b PINMUX_I2S_SEL_ACTIVE + + ENUM_DUMMY4WORD(PINMUX_FUNC_ID_DRV) +} PINMUX_FUNC_ID_DRV; + +// +// API for Top controller +// +extern void pinmux_select_debugport(PINMUX_DEBUGPORT uiDebug); +extern void pinmux_select_ocp_debugport(PINMUX_DEBUGPORT_OCP uiDebug); + +extern ER pinmux_init(PIN_GROUP_CONFIG *pConfig); +extern ER pinmux_setDispMode(PINMUX_FUNC_ID id, PINMUX_LCDINIT dispMode); +extern PINMUX_LCDINIT pinmux_getDispMode(PINMUX_FUNC_ID id); +extern ER pinmux_set_pinmux(PINMUX_FUNC_ID id, UINT32 pinmux); +extern BOOL pinmux_chkPinmux(PINMUX_FUNC_ID id, UINT32 pinmux); +//@} //addtogroup mIHALSysCfg + +#endif + diff --git a/board/novatek/ns02501/loader/Include/nvtpack/nvtpack.h b/board/novatek/ns02501/loader/Include/nvtpack/nvtpack.h new file mode 100755 index 000000000000..2a2e5c0f6d3f --- /dev/null +++ b/board/novatek/ns02501/loader/Include/nvtpack/nvtpack.h @@ -0,0 +1,193 @@ +#ifndef _NVTPACK_H +#define _NVTPACK_H + +#define NVTPACK_CHKSUM_HDR_VERSION 0x16040719U +#define NVTPACK_FW_HDR2_VERSION 0x16071515U + +typedef enum _NVTPACK_ER { + NVTPACK_ER_SUCCESS = 0, + NVTPACK_ER_FAILED = -1, + NVTPACK_ER_UNKNOWN_FORMAT = -2, + NVTPACK_ER_CHECK_SUM = -3, + NVTPACK_ER_NOT_FOUND = -4, + NVTPACK_ER_USER_BREAK = -5, + NVTPACK_ER_PARAM = -6, + NVTPACK_ER_MEM_NOT_ENOUGH = -7, + NVTPACK_ER_UITRON_SIZE_ALIGN4 = -8, ///< uITRON size must align by 4 + NVTPACK_ER_INVALID_WHOLE_SIZE = -9, ///< after nvtpack, whole size must align by 4 + NVTPACK_ER_SRC_NAME_BLANK = -10, ///< resource's SrcName cannot be NULL or blank + NVTPACK_ER_SRC_NAME_EXCEED = -11, ///< resource's SrcName cannot exceed 12 bytes + NVTPACK_ER_SRC_NAME_INVALID = -12, ///< resource's SrcName include invalid character + NVTPACK_ER_SRC_NAME_ALIKE = -13, ///< there resource's SrcName are alike. +} NVTPACK_ER; + +typedef enum _NVTPACK_VER { + NVTPACK_VER_UNKNOWN, ///< UNKNOWN + NVTPACK_VER_13012816, ///< NT9666X, NT9850X + NVTPACK_VER_16072017, ///< NT9668X +} NVTPACK_VER; + +#if !defined(_WIN32) +typedef struct _GUID { + unsigned int Data1; + unsigned short Data2; + unsigned short Data3; + unsigned char Data4[8]; +} GUID; +#endif + +typedef struct _NVTPACK_RES_HDR { + GUID guid; ///< {B5CB64AE-05DD-46FA-B906-0C62D22958D6} + unsigned int TotalSize; + unsigned int CheckSum; + unsigned int ContentSize; + char SrcName[16]; ///< original packed bin file name + char DstName[16]; ///< target file name +} NVTPACK_RES_HDR; + +typedef struct _NVTPACK_FW_HDR { + GUID guid; ///< {8827BE90-36CD-4FC2-A987-73A8484E84B1} + unsigned int TotalSize; ///< sizeof(NVTPACK_FW_HDR) + n*sizeof(NVTPACK_PARTITION_HDR) + unsigned int CheckSum; ///< check sum of sizeof(NVTPACK_FW_HDR) + n*sizeof(NVTPACK_PARTITION_HDR) + unsigned int TotalRes; ///< total partitions +} NVTPACK_FW_HDR; + +typedef struct _NVTPACK_FW_HDR2 { + GUID guid; ///< {D6012E07-10BC-4F91-B28A-352F82261A50} + unsigned int uiVersion; ///< NVTPACK_FW_HDR2_VERSION + unsigned int uiHdrSize; ///< sizeof(NVTPACK_FW_HDR2); + unsigned int TotalRes; ///< total resource counts + unsigned int TotalSize; ///< whole bin size + unsigned int uiChkMethod; ///< 0: CheckSum + unsigned int uiChkValue; ///< check sum value or crc value within NVTPACK_FW_HDR2 + unsigned int uiUserData[4]; ///< user defined data that may be used in future + unsigned int uiReversed[18];///< align to 128 bytes +} NVTPACK_FW_HDR2; + +typedef struct _NVTPACK_PARTITION_HDR { + unsigned int Offset; + unsigned int Size; + unsigned int PartitionID; +} NVTPACK_PARTITION_HDR; + +typedef struct _NVTPACK_CHKSUM_HDR { + unsigned int uiFourCC ; ///< 'C','K','S','M' + unsigned int uiVersion; ///< NVTPACK_CHKSUM_HDR header version + unsigned int uiChkMethod; ///< 0: CheckSum + unsigned int uiChkValue; ///< check sum value or crc value within NVTPACK_CHKSUM_HDR + unsigned int uiDataOffset; ///< real data starting offset without NVTPACK_CHKSUM_HDR + unsigned int uiDataSize; ///< real data size without NVTPACK_CHKSUM_HDR + unsigned int uiPaddingSize; ///< padding bytes for check sum + unsigned int uiEmbType; ///< relate to EMBTYPE_????? + unsigned int uiReversed[8]; ///< align to 64 bytes +} NVTPACK_CHKSUM_HDR; + +typedef struct _NVTPACK_BFC_HDR { + unsigned int uiFourCC; ///< FourCC = BCL1 + unsigned int uiAlgorithm; ///< algorithm always is 9 + unsigned int uiSizeUnComp;///< big endian uncompressed size + unsigned int uiSizeComp; ///< big endian compressed size +} NVTPACK_BFC_HDR; + +typedef struct _NVTPACK_BININFO_HDR { + unsigned int CodeEntry; ///< [0x00] fw CODE entry (4) ----- r by Ld + unsigned int Resv1[19]; ///< [0x04~0x50] reserved (4*19) -- reserved, its mem value will filled by Ld + char BinInfo_1[8]; ///< [0x50~0x58] CHIP-NAME (8) ---- r by Ep + char BinInfo_2[8]; ///< [0x58~0x60] SDK version (8) + char BinInfo_3[8]; ///< [0x60~0x68] SDK release-date (8) + unsigned int BinLength; ///< [0x68] Bin File Length (4) --- w by Ep/bfc + unsigned int Checksum; ///< [0x6c] Check Sum or CRC (4) ----- w by Ep/Epcrc + unsigned int CRCLenCheck; ///< [0x70~0x74] Length check for CRC (4) ----- w by Epcrc (total len ^ 0xAA55) + unsigned int Resv2; ///< [0x74~0x78] reserved (4) --- reserved for other bin tools + unsigned int BinCtrl; ///< [0x78~0x7C] Bin flag (4) --- w by bfc + ///< BIT 0.compressed enable (w by bfc) + unsigned int CRCBinaryTag; ///< [0x7C~0x80] Binary Tag for CRC (4) ----- w by Epcrc (0xAA55 + "NT") +} NVTPACK_BININFO_HDR; + +typedef struct _NVTPACK_MEM { + void *p_data; + unsigned int len; +} NVTPACK_MEM; + +typedef struct _NVTPACK_VERIFY_OUTPUT { + NVTPACK_VER ver; ///< indicate package type + unsigned int partition_cnt; ///< total partition counts +} NVTPACK_VERIFY_OUTPUT; + +typedef struct _NVTPACK_GET_PARTITION_INPUT { + unsigned int id; + NVTPACK_MEM mem; +} NVTPACK_GET_PARTITION_INPUT; + +typedef struct _NVTPACK_GET_RESOURCE_INPUT { + const char *filename; + NVTPACK_MEM mem; +} NVTPACK_GET_RESOURCE_INPUT; + +typedef struct _NVTPACK_ENUM_PARTITION_INPUT { + NVTPACK_MEM mem; + void *p_user_data; ///< [Optional] e.g. if use c class, you can pass that class point to your static callback. + int (*fp_enum)(unsigned int id, NVTPACK_MEM *p_mem, void *p_user_data); +} NVTPACK_ENUM_PARTITION_INPUT; + +typedef struct _NVTPACK_ENUM_RESOURCE_INPUT { + NVTPACK_MEM mem; + void *p_user_data; ///< [Optional] e.g. if use c class, you can pass that class point to your static callback. + int (*fp_enum)(NVTPACK_RES_HDR *p_hdr, NVTPACK_MEM *p_mem, void *p_user_data); +} NVTPACK_ENUM_RESOURCE_INPUT; + +typedef struct _NVTPACK_PARTITION_ITEM { + unsigned int id; + NVTPACK_MEM mem; +} NVTPACK_PARTITION_ITEM; + +typedef struct _NVTPACK_MAKE_PARTITION_INPUT { + NVTPACK_VER ver; ///< package version + NVTPACK_PARTITION_ITEM *p_list; ///< data list + int num; ///< data counts + NVTPACK_MEM mem_work; ///< working buffer +} NVTPACK_MAKE_PARTITION_INPUT; + +typedef struct _NVTPACK_RESOURCE_ITEM { + char SrcName[16]; ///< original name + char DstName[16]; ///< target file name + NVTPACK_MEM mem; +} NVTPACK_RESOURCE_ITEM; + +typedef struct _NVTPACK_MAKE_RESOURCE_INPUT { + NVTPACK_RESOURCE_ITEM *p_list; + int num; + NVTPACK_MEM mem_work; +} NVTPACK_MAKE_RESOURCE_INPUT; + +#ifndef IsEqualGUID +#define IsEqualGUID(rguid1, rguid2) (!memcmp(rguid1, rguid2, sizeof(GUID))) +#endif + +#ifndef MAKEFOURCC +#define MAKEFOURCC(ch0, ch1, ch2, ch3) ((unsigned int)(unsigned char)(ch0) | ((unsigned int)(unsigned char)(ch1) << 8) | ((unsigned int)(unsigned char)(ch2) << 16) | ((unsigned int)(unsigned char)(ch3) << 24 )) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +extern unsigned int nvtpack_calc_nvt_sum(NVTPACK_MEM *p_mem); +extern NVTPACK_ER nvtpack_getver(NVTPACK_MEM *p_mem, NVTPACK_VER *p_ver); +extern NVTPACK_ER nvtpack_verify(NVTPACK_MEM *p_mem, NVTPACK_VERIFY_OUTPUT *p_output); +extern NVTPACK_ER nvtpack_get_partition(NVTPACK_GET_PARTITION_INPUT *p_input, NVTPACK_MEM *p_out); +extern NVTPACK_ER nvtpack_enum_partition(NVTPACK_ENUM_PARTITION_INPUT *p_input); +//NVTPACK_VER_13012816: need sizeof(NVTPACK_FW_HDR) +n*(sizeof(NVTPACK_PARTITION_HDR) + 4) + whole_data_size +//NVTPACK_VER_16072017: need sizeof(NVTPACK_FW_HDR2) +n*(sizeof(NVTPACK_PARTITION_HDR) + 4) + whole_data_size +extern NVTPACK_ER nvtpack_make_parition_pkg(NVTPACK_MAKE_PARTITION_INPUT *p_input, NVTPACK_MEM *p_out); + +extern NVTPACK_ER nvtpack_get_resource(NVTPACK_GET_RESOURCE_INPUT *p_input, NVTPACK_MEM *p_out); +extern NVTPACK_ER nvtpack_enum_resource(NVTPACK_ENUM_RESOURCE_INPUT *p_input); +//buf need n*(sizeof(NVTPACK_RES_HDR)+32)+ whole_data_size +extern NVTPACK_ER nvtpack_make_resource_pkg(NVTPACK_MAKE_RESOURCE_INPUT *p_input, NVTPACK_MEM *p_out); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Include/rcw_macro.h b/board/novatek/ns02501/loader/Include/rcw_macro.h new file mode 100755 index 000000000000..0ca5093c5d97 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/rcw_macro.h @@ -0,0 +1,160 @@ +/* + Driver Register Cache Word (RCW) operation header file. + + Driver Register Cache Word (RCW) operation header file. + The macros defined in this header file is used to simply the register + bit field read and write. By adapting this way of register access, + it shall provide more error-proof and more readable way to write + drivers. It also does register access in load/store way which allow + one to accurately control the number of counts the register read and + write is proceeded from code writing. + + @file RCWMacro.h + @ingroup mIDriver + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2010. All rights reserved. +*/ + +#ifndef __ASM_ARCH_NVT_IVOT_RCW_MACRO_H +#define __ASM_ARCH_NVT_IVOT_RCW_MACRO_H +#if defined(__FREERTOS) +#include +#elif defined(__KERNEL__) +#include +#endif +/** + @addtogroup mIDriver +*/ +//@{ + +// +// Register word value type +// +// The size in bits of this type should match the RCW type +#define REGVALUE unsigned int //uint32_t + +#define UBITFIELD unsigned int /* Unsigned bit field */ +#define BITFIELD signed int /* Signed bit field */ + + +#define FALSE 0 +#define TRUE 1 + +/** + @name Assert macros +*/ +//@{ +#define ASSERT_CONCAT_(a, b) a##b +#define ASSERT_CONCAT(a, b) ASSERT_CONCAT_(a, b) + +#if defined(__COUNTER__) + +#define STATIC_ASSERT(expr) \ +enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __COUNTER__) = 1/(expr) } + +#else + +// This might cause compile error when writing STATIC_ASSERT at the same line +// in two (or more) files and one file include another one. +#define STATIC_ASSERT(expr) \ +enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __LINE__) = 1/(expr) } + +#endif + +#define OUTW(addr,value) (*(REGVALUE volatile *)(addr) = (REGVALUE)(value)) +#define INW(addr) (*(REGVALUE volatile *)(addr)) + + +// +// Macros for Register Cache Word (RCW) type definition +// +// Each RCW type should be exactly the same size with REGVALUE type +// For example, to declare a Register Cache Word type: +// +// #define rcwname_OFS 0x00 /* the name of RCW corresponding register address offset +// should be in specific format with "_OFS" appended */ +// REGDEF_BEGIN(rcwname) +// REGDEF_BIT(field1, 8) /* declare field1 as 8 bits width */ +// REGDEF_BIT(field2, 8) /* declare field1 as 8 bits width */ +// REGDEF_BIT(, 16) /* pad reserved (not-used) bits to fill RCW type same as REGVALUE size */ +// REGDEF_END(rcwname) +// +// Register Cache Word type defintion header +#define REGDEF_BEGIN(name) \ +typedef union \ +{ \ + REGVALUE reg; \ + struct \ + { + +// Register Cache Word bit defintion +#define REGDEF_BIT(field, bits) \ + UBITFIELD field : bits; + +// Register Cache Word type defintion trailer +#define REGDEF_END(name) \ + } bit; \ +} T_##name; \ +STATIC_ASSERT(sizeof(T_##name) == sizeof(REGVALUE)); + +// Macro to define register offset +#define REGDEF_OFFSET(name, ofs) static const uint32_t name##_OFS=(ofs); + +// +// Macros for prerequisite stuff initialization for Register Cache Word +// operations +// +// Macro to set register base address for current module +// One must call this macro somewhere to set register I/O base address for +// current module, either globally or locally before any RCW operations is +// invoked +// What this macro set is only effective in current C file +#define REGDEF_SETIOBASE(base) static const uint32_t _REGIOBASE=(base) + +// Macro to set register repeat group offset address in byte +// This macro is optional and only used where register with repeat group exist, +// only one repeat group is allowed in one file +// If registers with repeat group exist, then one only have to define the RCW type +// for the first group, respective group of registers can be accessed through +// RCW_LD2, RCW_ST2, RCW_LD2OF macros +// What this macro set is only effective in current C file +#define REGDEF_SETGRPOFS(grpofs) static const uint32_t _REGGRPOFS=(grpofs) + +// +// Macros for Register Cache Word (RCW) operations +// +// These RCW operations are most likely to be used inside C functions +// It is not recommended to use RCW_DEF(RCW) in global scope which +// declare RCW as global variable +// RCW_LD/RCW_ST/RCW_LDOF pair is for normal single register access while +// RCW_LD2/RCW_ST2/RCW_LD2OF pair is for repeat group register access +// Beware that the RCW_LD/RCW_ST/RCW_LDOF and RCW_LD2/RCW_ST2/RCW_LD2OF +// must not be mixed used. e.g. use RCW_LD then RCW_ST2 or use RCW_LD2 then RCW_ST +// +// Register Cache Word declaration +#define RCW_DEF(RCW) T##_##RCW t##RCW +// Register Cache Word read from I/O +#define RCW_LD(RCW) t##RCW.reg = INW(_REGIOBASE+RCW##_OFS) +// Register Cache Word repeat from I/O for group read +#define RCW_LD2(RCW, grpidx) t##RCW.reg = INW(_REGIOBASE+RCW##_OFS+(grpidx)*_REGGRPOFS) +// Register Cache Word bit reference +#define RCW_OF(RCW) t##RCW.bit +// Register Cache Word reference +#define RCW_VAL(RCW) t##RCW.reg +// Register Cache Word write to I/O +#define RCW_ST(RCW) OUTW(_REGIOBASE+RCW##_OFS, t##RCW.reg) +// Register Cache Word write to I/O for repeat group +#define RCW_ST2(RCW, grpidx) OUTW(_REGIOBASE+RCW##_OFS+(grpidx)*_REGGRPOFS, t##RCW.reg) +// Register Cache Word read and reference to register cache word bit +// !!!need to check for compiler if support for this syntax +#define RCW_LDOF(RCW) ((T##_##RCW)(RCW_LD(RCW))).bit +// Register Cache Word read and reference to register cache word bit for repeat group +// !!!need to check for compiler if support for this syntax +#define RCW_LD2OF(RCW, grpidx) ((T##_##RCW)(RCW_LD2(RCW, grpidx))).bit + +#define rcw_get_phy_addr(addr) ((addr) & 0x1FFFFFFF) + +//@} + +#endif /* __ASM_ARCH_NVT_IVOT_RCW_MACRO_H */ diff --git a/board/novatek/ns02501/loader/Include/rtc.h b/board/novatek/ns02501/loader/Include/rtc.h new file mode 100755 index 000000000000..692340765cea --- /dev/null +++ b/board/novatek/ns02501/loader/Include/rtc.h @@ -0,0 +1,76 @@ +/** + Header file for RTC module. + + This file is the header file that define the API and data type + for RTC module. + + @file rtc.h + @ingroup mIHALRTC + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __RTC_H +#define __RTC_H +#include "IOReg.h" + +/** + @addtogroup mIHALRTC +*/ +//@{ + +/** + @name RTC power on source + + RTC power on source + + @note For rtc_getPWRONSource() +*/ +//@{ +#if 0 // 567 Not support PWBC +#define RTC_PWR_SW_STS 0x00000100 ///< Power on from switch +#define RTC_PWR_SW2_STS 0x00000200 ///< power on from power switch 2 +#define RTC_PWR_SW3_STS 0x00000400 ///< power on from power switch 3 (Usually for USB VBUS, depend on project) +#define RTC_PWR_VBUS_STS (RTC_PWR_SW3_STS) ///< power on from VBUS (identical to RTC_PWR_SW3_STS) +#define RTC_PWR_SW4_STS 0x00000800 ///< power on from power switch 4 (Usually for VBAT, depend on project) +#define RTC_PWR_VBAT_STS (RTC_PWR_SW4_STS) ///< power on from VBAT (identical to RTC_PWR_SW4_STS) +#define RTC_PWR_ALARM_STS 0x00010000 ///< Power on from PWR ALARM + +//@} + +extern void rtc_resetShutDownTimer(void); +extern void rtc_poweroffPWR(void); +extern UINT32 rtc_getPWRONSource(void); +extern UINT32 rtc_chkS3boot_init(void) __attribute__ ((section (".part1"))); +extern void rtc_chkS3boot_wait_init(void) __attribute__ ((section (".part1"))); +extern UINT32 rtc_chkS3boot(void) __attribute__ ((section (".part1"))); +#endif + +struct rtc_time { + int tm_sec; + int tm_min; + int tm_hour; + int tm_mday; + int tm_mon; + int tm_year; + int tm_wday; + int tm_yday; + int tm_isdst; +}; + + + +extern void rtc_trigger_cset(void); +extern int rtc_get_time(struct rtc_time *tm); +extern int rtc_set_time(struct rtc_time *tm); +extern int rtc_set_alarm_en(UINT32 alarm_en ); +extern int rtc_get_alarm_time(struct rtc_time *tm); +extern int rtc_set_alarm_time(struct rtc_time *tm); +extern void nvt_rtc_add_one_sec(struct rtc_time *tm, UINT32 add_sec ); +extern void rtc_open(void); + + +//@} +#endif // __RTC_H + diff --git a/board/novatek/ns02501/loader/Include/scsi_op.h b/board/novatek/ns02501/loader/Include/scsi_op.h new file mode 100755 index 000000000000..bda03aa4f419 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/scsi_op.h @@ -0,0 +1,205 @@ +#ifndef _SCSI_OP_H +#define _SCSI_OP_H + +/** +Only Support MSDC Vendor command code 0xF0/0xE0/0xC0. +Others vendor code would STALL OUT EP. Sense data would return illegal request sense code. +*/ +#define SCSI_OP_SET0 0xF0 +#define SCSI_OP_SET1 0xE0 +#define SCSI_OP_SET2 0xC0 + + +/////////////////////////////////////////////////////////////////////////////// +// Uart's return status: CDB[13] +// Uart's extra data len: CDB[6] ~ CDB[9] except SCSIOP_OUT_ADDR_WRITE +// Checksum rule: The CDB[0] ~ CDB[15]'s sum LSB 8bits shall be 0x00 +// Checksum is fixed CDB[14] ~ CDB[15] +// When Checksum failed. CSW Status 0x1 means command failed. +/////////////////////////////////////////////////////////////////////////////// +#define IDX_CDB_UART_DATA_LEN_LWLB 6 ///< uart's data len low word low byte +#define IDX_CDB_UART_DATA_LEN_LWHB 7 ///< uart's data len low word high byte +#define IDX_CDB_UART_DATA_LEN_HWLB 8 ///< uart's data len high word low byte +#define IDX_CDB_UART_DATA_LEN_HWHB 9 ///< uart's data len high word low byte +#define IDX_CDB_UART_STATUS_ER 13 ///< uart's csw status +#define IDX_CDB_CHKSUM_LB 14 ///< check sum low bytes +#define IDX_CDB_CHKSUM_HB 15 ///< check sum high bytes + +/////////////////////////////////////////////////////////////////////////////// +// SCSI CBW +/////////////////////////////////////////////////////////////////////////////// +typedef struct _NVT_SCSI_CBW { + unsigned int dCBWSignature; + unsigned int dCBWTag; + unsigned int dCBWDataTransferLength; + unsigned char bmCBWFlags; + unsigned char bCBWLUN; + unsigned char bCBWCBLength; + unsigned char CBWCB[16]; +} NVT_SCSI_CBW; + +/** +Open NVT Device + +The commands except SCSIOP_IN_IS_NVT can be run if open device success. +If not open first, the operation commands got CSW Status 0x1 means command failed. + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_OPEN_DEVICE 0x01 + + +/** +Send Write Loader + +The Write Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_WRLOADER 0x02 + +/** +Address WRITE WORD (DRAM/REG/SRAM dont care) + +The Write Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +The Write DATA @ CDB[6]~[9]. +For example address 0x12345678 shall fill CDB[6]=0x78 CDB[7]=0x56 CDB[8]=0x34 CDB[9]=0x12 +CDB[10]~[15] shall follow checksum rule. Content is dont care. + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_ADDR_WRITE 0x03 + +/** +Write Memory + +The Write Starting Address @ CDB[2]~[5]; +For example offset 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_MEM_WRITE 0x04 + +/** +Read / Write flash + +send SCSIOP_FLASH_OP to loader +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. except CDB[10] +UART: CDB[6]~[9] is SCSIOP_FLASH_OP size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define FLASH_ACCESS_TYPE_AUTO 0 +#define FLASH_ACCESS_TYPE_NAND 1 +#define FLASH_ACCESS_TYPE_NOR 2 +#define FLASH_ACCESS_TYPE_EMMC 3 +typedef struct _SCSIOP_FLASH_OP { + unsigned int type; //FLASH_ACCESS_TYPE + unsigned int is_write; //indicate write + unsigned long long offset; //flash r/w offset + unsigned long long size; //flash r/w size + unsigned long long partition_size; //flash partition size +} SCSIOP_FLASH_OP; +#define SCSIOP_OUT_FLASH_ACCESS 0x05 + + +/** +Ask if NVT Device + +No need to SCSIOP_IN_OPEN_DEVICE +CDB[2]~[15] shall follow checksum rule + +@DATA_PHASE: IN 4 bytes return; The value 0x81200000 woule be return for 98321. <8321 = 0x2081> If checksum fail, the 0x0 would be returned. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. + +*/ +#define SCSIOP_IN_IS_NVT 0x81 + + +/** +End USB ROM CODE. + +Exit USB ROM code after receiving this command. The checksum must be correct. +After SCSIOP_IN_WRLOADER is invoked, PC invoked this to confirm write loader is ok. + +CDB[2]~[15] shall follow checksum rule + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success and end usb rom. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_WAIT_DONE 0x82 + + +/** +Address READ WORD (DRAM/REG/SRAM dont care) + +The READ Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +CDB[6]~[15] shall follow checksum rule. Content is dont care. + +@DATA_PHASE: IN 8 bytes return. DATA[0]~[3] is repeat CDB address. Read out DATA is [4] ~[7]. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_ADDR_READ 0x83 + + +/** +The Read Starting Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +CDB[6]~[9] is read data size +CDB[10]~[15] shall follow checksum rule. Content is dont care. + +@DATA_PHASE: IN 8 bytes return. DATA[0]~[3] is repeat CDB address. Read out DATA is [3] ~[7]. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. + +*/ +#define SCSIOP_IN_MEM_READ 0x84 + + +/** +Get Temp Buffer Address + +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: Read out DATA is [3] ~[7]. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_GET_TMP_ADDR 0x85 + +/** +Notify fdt has send + +The fdt has sent into loader's temp buffer. notify loader to check its sanity. +CDB[2]~[5] is status result in word. +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_FDT 0x86 + + +/** +Notify uboot or nvtpack has send + +The uboot or nvtpack has sent into loader's temp buffer. notify loader to check its sanity. +CDB[2]~[5] is status result in word. +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) +*/ +#define SCSIOP_IN_UBOOT 0x87 + +#endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Include/signal.h b/board/novatek/ns02501/loader/Include/signal.h new file mode 100755 index 000000000000..3ece9caed166 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/signal.h @@ -0,0 +1,4 @@ +#ifndef _NVT_LIBC_SIGNAL_H__ +#define _NVT_LIBC_SIGNAL_H__ +int raise(int sig); +#endif diff --git a/board/novatek/ns02501/loader/Include/stdarg.h b/board/novatek/ns02501/loader/Include/stdarg.h new file mode 100755 index 000000000000..13c2717bc1bf --- /dev/null +++ b/board/novatek/ns02501/loader/Include/stdarg.h @@ -0,0 +1,19 @@ +#ifndef __NVT_STDARG_H__ +#define __NVT_STDARG_H__ + +typedef char *va_list; + +/* + * Storage alignment properties + */ +#define _AUPBND (sizeof (int) - 1) +#define _ADNBND (sizeof (int) - 1) + +/* + * Variable argument list macro definitions + */ +#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd))) +#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND)))) +#define va_end(ap) (void) 0 +#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND)))) +#endif diff --git a/board/novatek/ns02501/loader/Include/stdio.h b/board/novatek/ns02501/loader/Include/stdio.h new file mode 100755 index 000000000000..f0bd3cd3dd17 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/stdio.h @@ -0,0 +1,24 @@ +/** + STDIO header + + STDIO header + + @file stdio.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_STDIO_H__ +#define __NVT_STDIO_H__ + +/** \addtogroup mISYSClib */ +//@{ + +int sprintf(char * buf, const char *fmt, ...); +int snprintf(char * buf, int n, const char *fmt, ...); +int sscanf(const char * buf, const char * fmt, ...); + +//@} +#endif diff --git a/board/novatek/ns02501/loader/Include/stdlib.h b/board/novatek/ns02501/loader/Include/stdlib.h new file mode 100755 index 000000000000..f649e19676be --- /dev/null +++ b/board/novatek/ns02501/loader/Include/stdlib.h @@ -0,0 +1,4 @@ +#ifndef __NVT_LIBC_STDLIB_H__ +#define __NVT_LIBC_STDLIB_H__ +int atoi(const char *nptr); +#endif diff --git a/board/novatek/ns02501/loader/Include/string.h b/board/novatek/ns02501/loader/Include/string.h new file mode 100755 index 000000000000..640789ef7419 --- /dev/null +++ b/board/novatek/ns02501/loader/Include/string.h @@ -0,0 +1,47 @@ +/** + string header + + string header + + @file string.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_LIBC_STRING_H__ +#define __NVT_LIBC_STRING_H__ + +/** \addtogroup mISYSClib */ +//@{ + +/** + size_t data type + + data type to store value return by sizeof keyword +*/ +typedef unsigned int size_t; + +extern size_t strlen(const char *s); +extern size_t strnlen(const char *s, size_t count); +extern char *strncpy(char *dest, const char *src, size_t count); +extern char *strncat(char *dest, const char *src, size_t count); +extern char *strstr(const char *s1, const char *s2); +extern int strncmp(const char *cs, const char *ct, size_t count); +extern char *strrchr(const char *s, int c); +extern char *strcpy(char *dest, const char *src); +extern char *strcat(char *dest, const char *src); +extern char *strchr(const char *s, int c); +extern char* strtok(char *s, const char *delim); +extern int strcmp(const char *cs, const char *ct); + +extern void *utl_memset(void *s, int c, size_t count); +extern void *utl_memcpy(void *dest, const void *src, size_t count); +extern int memcmp(const void *cs, const void *ct, size_t count); +extern void *memmove(void *dest, const void *src, size_t count); +extern void *memchr(const void *ptr, int value, size_t count); +//@} + +#endif + diff --git a/board/novatek/ns02501/loader/Include/timer.h b/board/novatek/ns02501/loader/Include/timer.h new file mode 100755 index 000000000000..b683a65460ea --- /dev/null +++ b/board/novatek/ns02501/loader/Include/timer.h @@ -0,0 +1,31 @@ +/** + Public header file for timer module. + + This file is the header file that define the API and data type for timer + module. + + @file timer.h + @ingroup mIHALTimer + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _TIMER_H +#define _TIMER_H + +#include "IOReg.h" + +/** + @addtogroup mIHALTimer +*/ +//@{ + +extern UINT32 timer_getLdrElapse(void); +extern void timer_delay(UINT32 US); +#define timer_getLdrElapse() INREG32(0xF0040108) +#define timer_getSysTick() INREG32(0xF0040108) +//extern UINT32 timer_getSysTick(void) __attribute__ ((section (".part1"))); + //@} + +#endif diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.c new file mode 100644 index 000000000000..ac6812aac4d7 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.c @@ -0,0 +1,1033 @@ +/* LzmaDec.c -- LZMA Decoder +2009-09-20 : Igor Pavlov : Public domain */ + +/* + * OpenIPC: U-Boot's lib/lzma/LzmaDec.c for the loader, which has no + * libc: memcpy is the loader's, and there is no watchdog to feed. + */ +/* OpenIPC: small, in Thumb */ +#pragma GCC target("thumb") +#pragma GCC optimize("Os") + +#include "LzmaDec.h" +#include "string.h" + +#define memcpy utl_memcpy +#define WATCHDOG_RESET() do { } while (0) + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_INIT_SIZE 5 + +#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); } + +#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) +#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits)); +#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits)); +#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \ + { UPDATE_0(p); i = (i + i); A0; } else \ + { UPDATE_1(p); i = (i + i) + 1; A1; } +#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;) + +#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); } +#define TREE_DECODE(probs, limit, i) \ + { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; } + +/* OpenIPC: the loop form, smaller */ +#define _LZMA_SIZE_OPT + +#ifdef _LZMA_SIZE_OPT +#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i) +#else +#define TREE_6_DECODE(probs, i) \ + { i = 1; \ + TREE_GET_BIT(probs, i); \ + TREE_GET_BIT(probs, i); \ + TREE_GET_BIT(probs, i); \ + TREE_GET_BIT(probs, i); \ + TREE_GET_BIT(probs, i); \ + TREE_GET_BIT(probs, i); \ + i -= 0x40; } +#endif + +#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); } + +#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) +#define UPDATE_0_CHECK range = bound; +#define UPDATE_1_CHECK range -= bound; code -= bound; +#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \ + { UPDATE_0_CHECK; i = (i + i); A0; } else \ + { UPDATE_1_CHECK; i = (i + i) + 1; A1; } +#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;) +#define TREE_DECODE_CHECK(probs, limit, i) \ + { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 +#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp))) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +#define LZMA_DIC_MIN (1 << 12) + +/* First LZMA-symbol is always decoded. +And it decodes new LZMA-symbols while (buf < bufLimit), but "buf" is without last normalization +Out: + Result: + SZ_OK - OK + SZ_ERROR_DATA - Error + p->remainLen: + < kMatchSpecLenStart : normal remain + = kMatchSpecLenStart : finished + = kMatchSpecLenStart + 1 : Flush marker + = kMatchSpecLenStart + 2 : State Init Marker +*/ + +static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit) +{ + CLzmaProb *probs = p->probs; + + unsigned state = p->state; + UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3]; + unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1; + unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1; + unsigned lc = p->prop.lc; + + Byte *dic = p->dic; + SizeT dicBufSize = p->dicBufSize; + SizeT dicPos = p->dicPos; + + UInt32 processedPos = p->processedPos; + UInt32 checkDicSize = p->checkDicSize; + unsigned len = 0; + + const Byte *buf = p->buf; + UInt32 range = p->range; + UInt32 code = p->code; + + WATCHDOG_RESET(); + + do + { + CLzmaProb *prob; + UInt32 bound; + unsigned ttt; + unsigned posState = processedPos & pbMask; + + prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; + IF_BIT_0(prob) + { + unsigned symbol; + UPDATE_0(prob); + prob = probs + Literal; + if (checkDicSize != 0 || processedPos != 0) + prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) + + (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc)))); + + if (state < kNumLitStates) + { + state -= (state < 4) ? state : 3; + symbol = 1; + + WATCHDOG_RESET(); + + do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100); + } + else + { + unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; + unsigned offs = 0x100; + state -= (state < 10) ? 3 : 6; + symbol = 1; + + WATCHDOG_RESET(); + + do + { + unsigned bit; + CLzmaProb *probLit; + matchByte <<= 1; + bit = (matchByte & offs); + probLit = prob + offs + bit + symbol; + GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit) + } + while (symbol < 0x100); + } + dic[dicPos++] = (Byte)symbol; + processedPos++; + continue; + } + else + { + UPDATE_1(prob); + prob = probs + IsRep + state; + IF_BIT_0(prob) + { + UPDATE_0(prob); + state += kNumStates; + prob = probs + LenCoder; + } + else + { + UPDATE_1(prob); + if (checkDicSize == 0 && processedPos == 0) + return SZ_ERROR_DATA; + prob = probs + IsRepG0 + state; + IF_BIT_0(prob) + { + UPDATE_0(prob); + prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; + IF_BIT_0(prob) + { + UPDATE_0(prob); + dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; + dicPos++; + processedPos++; + state = state < kNumLitStates ? 9 : 11; + continue; + } + UPDATE_1(prob); + } + else + { + UInt32 distance; + UPDATE_1(prob); + prob = probs + IsRepG1 + state; + IF_BIT_0(prob) + { + UPDATE_0(prob); + distance = rep1; + } + else + { + UPDATE_1(prob); + prob = probs + IsRepG2 + state; + IF_BIT_0(prob) + { + UPDATE_0(prob); + distance = rep2; + } + else + { + UPDATE_1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = probs + RepLenCoder; + } + { + unsigned limit, offset; + CLzmaProb *probLen = prob + LenChoice; + IF_BIT_0(probLen) + { + UPDATE_0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + limit = (1 << kLenNumLowBits); + } + else + { + UPDATE_1(probLen); + probLen = prob + LenChoice2; + IF_BIT_0(probLen) + { + UPDATE_0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + limit = (1 << kLenNumMidBits); + } + else + { + UPDATE_1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + limit = (1 << kLenNumHighBits); + } + } + TREE_DECODE(probLen, limit, len); + len += offset; + } + + if (state >= kNumStates) + { + UInt32 distance; + prob = probs + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); + TREE_6_DECODE(prob, distance); + if (distance >= kStartPosModelIndex) + { + unsigned posSlot = (unsigned)distance; + int numDirectBits = (int)(((distance >> 1) - 1)); + distance = (2 | (distance & 1)); + if (posSlot < kEndPosModelIndex) + { + distance <<= numDirectBits; + prob = probs + SpecPos + distance - posSlot - 1; + { + UInt32 mask = 1; + unsigned i = 1; + + WATCHDOG_RESET(); + + do + { + GET_BIT2(prob + i, i, ; , distance |= mask); + mask <<= 1; + } + while (--numDirectBits != 0); + } + } + else + { + numDirectBits -= kNumAlignBits; + + WATCHDOG_RESET(); + + do + { + NORMALIZE + range >>= 1; + + { + UInt32 t; + code -= range; + t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */ + distance = (distance << 1) + (t + 1); + code += range & t; + } + /* + distance <<= 1; + if (code >= range) + { + code -= range; + distance |= 1; + } + */ + } + while (--numDirectBits != 0); + prob = probs + Align; + distance <<= kNumAlignBits; + { + unsigned i = 1; + GET_BIT2(prob + i, i, ; , distance |= 1); + GET_BIT2(prob + i, i, ; , distance |= 2); + GET_BIT2(prob + i, i, ; , distance |= 4); + GET_BIT2(prob + i, i, ; , distance |= 8); + } + if (distance == (UInt32)0xFFFFFFFF) + { + len += kMatchSpecLenStart; + state -= kNumStates; + break; + } + } + } + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + rep0 = distance + 1; + if (checkDicSize == 0) + { + if (distance >= processedPos) + return SZ_ERROR_DATA; + } + else if (distance >= checkDicSize) + return SZ_ERROR_DATA; + state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3; + } + + len += kMatchMinLen; + + if (limit == dicPos) + return SZ_ERROR_DATA; + { + SizeT rem = limit - dicPos; + unsigned curLen = ((rem < len) ? (unsigned)rem : len); + SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0); + + processedPos += curLen; + + len -= curLen; + if (pos + curLen <= dicBufSize) + { + Byte *dest = dic + dicPos; + ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos; + const Byte *lim = dest + curLen; + dicPos += curLen; + + WATCHDOG_RESET(); + + do + *(dest) = (Byte)*(dest + src); + while (++dest != lim); + } + else + { + + WATCHDOG_RESET(); + + do + { + dic[dicPos++] = dic[pos]; + if (++pos == dicBufSize) + pos = 0; + } + while (--curLen != 0); + } + } + } + } + while (dicPos < limit && buf < bufLimit); + + WATCHDOG_RESET(); + + NORMALIZE; + p->buf = buf; + p->range = range; + p->code = code; + p->remainLen = len; + p->dicPos = dicPos; + p->processedPos = processedPos; + p->reps[0] = rep0; + p->reps[1] = rep1; + p->reps[2] = rep2; + p->reps[3] = rep3; + p->state = state; + + return SZ_OK; +} + +static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit) +{ + if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart) + { + Byte *dic = p->dic; + SizeT dicPos = p->dicPos; + SizeT dicBufSize = p->dicBufSize; + unsigned len = p->remainLen; + UInt32 rep0 = p->reps[0]; + if (limit - dicPos < len) + len = (unsigned)(limit - dicPos); + + if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len) + p->checkDicSize = p->prop.dicSize; + + p->processedPos += len; + p->remainLen -= len; + while (len-- != 0) + { + dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; + dicPos++; + } + p->dicPos = dicPos; + } +} + +static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit) +{ + do + { + SizeT limit2 = limit; + if (p->checkDicSize == 0) + { + UInt32 rem = p->prop.dicSize - p->processedPos; + if (limit - p->dicPos > rem) + limit2 = p->dicPos + rem; + } + RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit)); + if (p->processedPos >= p->prop.dicSize) + p->checkDicSize = p->prop.dicSize; + LzmaDec_WriteRem(p, limit); + } + while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart); + + if (p->remainLen > kMatchSpecLenStart) + { + p->remainLen = kMatchSpecLenStart; + } + return 0; +} + +typedef enum +{ + DUMMY_ERROR, /* unexpected end of input stream */ + DUMMY_LIT, + DUMMY_MATCH, + DUMMY_REP +} ELzmaDummy; + +static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize) +{ + UInt32 range = p->range; + UInt32 code = p->code; + const Byte *bufLimit = buf + inSize; + CLzmaProb *probs = p->probs; + unsigned state = p->state; + ELzmaDummy res; + + { + CLzmaProb *prob; + UInt32 bound; + unsigned ttt; + unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1); + + prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK + + /* if (bufLimit - buf >= 7) return DUMMY_LIT; */ + + prob = probs + Literal; + if (p->checkDicSize != 0 || p->processedPos != 0) + prob += (LZMA_LIT_SIZE * + ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) + + (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc)))); + + if (state < kNumLitStates) + { + unsigned symbol = 1; + do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100); + } + else + { + unsigned matchByte = p->dic[p->dicPos - p->reps[0] + + ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)]; + unsigned offs = 0x100; + unsigned symbol = 1; + do + { + unsigned bit; + CLzmaProb *probLit; + matchByte <<= 1; + bit = (matchByte & offs); + probLit = prob + offs + bit + symbol; + GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit) + } + while (symbol < 0x100); + } + res = DUMMY_LIT; + } + else + { + unsigned len; + UPDATE_1_CHECK; + + prob = probs + IsRep + state; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK; + state = 0; + prob = probs + LenCoder; + res = DUMMY_MATCH; + } + else + { + UPDATE_1_CHECK; + res = DUMMY_REP; + prob = probs + IsRepG0 + state; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK; + prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK; + NORMALIZE_CHECK; + return DUMMY_REP; + } + else + { + UPDATE_1_CHECK; + } + } + else + { + UPDATE_1_CHECK; + prob = probs + IsRepG1 + state; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK; + } + else + { + UPDATE_1_CHECK; + prob = probs + IsRepG2 + state; + IF_BIT_0_CHECK(prob) + { + UPDATE_0_CHECK; + } + else + { + UPDATE_1_CHECK; + } + } + } + state = kNumStates; + prob = probs + RepLenCoder; + } + { + unsigned limit, offset; + CLzmaProb *probLen = prob + LenChoice; + IF_BIT_0_CHECK(probLen) + { + UPDATE_0_CHECK; + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + limit = 1 << kLenNumLowBits; + } + else + { + UPDATE_1_CHECK; + probLen = prob + LenChoice2; + IF_BIT_0_CHECK(probLen) + { + UPDATE_0_CHECK; + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + limit = 1 << kLenNumMidBits; + } + else + { + UPDATE_1_CHECK; + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + limit = 1 << kLenNumHighBits; + } + } + TREE_DECODE_CHECK(probLen, limit, len); + len += offset; + } + + if (state < 4) + { + unsigned posSlot; + prob = probs + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + + /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */ + + if (posSlot < kEndPosModelIndex) + { + prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + NORMALIZE_CHECK + range >>= 1; + code -= range & (((code - range) >> 31) - 1); + /* if (code >= range) code -= range; */ + } + while (--numDirectBits != 0); + prob = probs + Align; + numDirectBits = kNumAlignBits; + } + { + unsigned i = 1; + do + { + GET_BIT_CHECK(prob + i, i); + } + while (--numDirectBits != 0); + } + } + } + } + } + NORMALIZE_CHECK; + return res; +} + + +static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data) +{ + p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]); + p->range = 0xFFFFFFFF; + p->needFlush = 0; +} + +static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) +{ + p->needFlush = 1; + p->remainLen = 0; + p->tempBufSize = 0; + + if (initDic) + { + p->processedPos = 0; + p->checkDicSize = 0; + p->needInitState = 1; + } + if (initState) + p->needInitState = 1; +} + +void LzmaDec_Init(CLzmaDec *p) +{ + p->dicPos = 0; + LzmaDec_InitDicAndState(p, True, True); +} + +static void LzmaDec_InitStateReal(CLzmaDec *p) +{ + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp)); + UInt32 i; + CLzmaProb *probs = p->probs; + for (i = 0; i < numProbs; i++) + probs[i] = kBitModelTotal >> 1; + p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1; + p->state = 0; + p->needInitState = 0; +} + +SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, + ELzmaFinishMode finishMode, ELzmaStatus *status) +{ + SizeT inSize = *srcLen; + (*srcLen) = 0; + LzmaDec_WriteRem(p, dicLimit); + + *status = LZMA_STATUS_NOT_SPECIFIED; + + while (p->remainLen != kMatchSpecLenStart) + { + int checkEndMarkNow; + + if (p->needFlush != 0) + { + for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--) + p->tempBuf[p->tempBufSize++] = *src++; + if (p->tempBufSize < RC_INIT_SIZE) + { + *status = LZMA_STATUS_NEEDS_MORE_INPUT; + return SZ_OK; + } + if (p->tempBuf[0] != 0) + return SZ_ERROR_DATA; + + LzmaDec_InitRc(p, p->tempBuf); + p->tempBufSize = 0; + } + + checkEndMarkNow = 0; + if (p->dicPos >= dicLimit) + { + if (p->remainLen == 0 && p->code == 0) + { + *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK; + return SZ_OK; + } + if (finishMode == LZMA_FINISH_ANY) + { + *status = LZMA_STATUS_NOT_FINISHED; + return SZ_OK; + } + if (p->remainLen != 0) + { + *status = LZMA_STATUS_NOT_FINISHED; + return SZ_ERROR_DATA; + } + checkEndMarkNow = 1; + } + + if (p->needInitState) + LzmaDec_InitStateReal(p); + + if (p->tempBufSize == 0) + { + SizeT processed; + const Byte *bufLimit; + if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) + { + int dummyRes = LzmaDec_TryDummy(p, src, inSize); + if (dummyRes == DUMMY_ERROR) + { + memcpy(p->tempBuf, src, inSize); + p->tempBufSize = (unsigned)inSize; + (*srcLen) += inSize; + *status = LZMA_STATUS_NEEDS_MORE_INPUT; + return SZ_OK; + } + if (checkEndMarkNow && dummyRes != DUMMY_MATCH) + { + *status = LZMA_STATUS_NOT_FINISHED; + return SZ_ERROR_DATA; + } + bufLimit = src; + } + else + bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX; + p->buf = src; + if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0) + return SZ_ERROR_DATA; + processed = (SizeT)(p->buf - src); + (*srcLen) += processed; + src += processed; + inSize -= processed; + } + else + { + unsigned rem = p->tempBufSize, lookAhead = 0; + while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize) + p->tempBuf[rem++] = src[lookAhead++]; + p->tempBufSize = rem; + if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) + { + int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem); + if (dummyRes == DUMMY_ERROR) + { + (*srcLen) += lookAhead; + *status = LZMA_STATUS_NEEDS_MORE_INPUT; + return SZ_OK; + } + if (checkEndMarkNow && dummyRes != DUMMY_MATCH) + { + *status = LZMA_STATUS_NOT_FINISHED; + return SZ_ERROR_DATA; + } + } + p->buf = p->tempBuf; + if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0) + return SZ_ERROR_DATA; + lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf)); + (*srcLen) += lookAhead; + src += lookAhead; + inSize -= lookAhead; + p->tempBufSize = 0; + } + } + if (p->code == 0) + *status = LZMA_STATUS_FINISHED_WITH_MARK; + return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; +} + +SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status) +{ + SizeT outSize = *destLen; + SizeT inSize = *srcLen; + *srcLen = *destLen = 0; + for (;;) + { + SizeT inSizeCur = inSize, outSizeCur, dicPos; + ELzmaFinishMode curFinishMode; + SRes res; + if (p->dicPos == p->dicBufSize) + p->dicPos = 0; + dicPos = p->dicPos; + if (outSize > p->dicBufSize - dicPos) + { + outSizeCur = p->dicBufSize; + curFinishMode = LZMA_FINISH_ANY; + } + else + { + outSizeCur = dicPos + outSize; + curFinishMode = finishMode; + } + + res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status); + src += inSizeCur; + inSize -= inSizeCur; + *srcLen += inSizeCur; + outSizeCur = p->dicPos - dicPos; + memcpy(dest, p->dic + dicPos, outSizeCur); + dest += outSizeCur; + outSize -= outSizeCur; + *destLen += outSizeCur; + if (res != 0) + return res; + if (outSizeCur == 0 || outSize == 0) + return SZ_OK; + } +} + +void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) +{ + alloc->Free(alloc, p->probs); + p->probs = 0; +} + +static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) +{ + alloc->Free(alloc, p->dic); + p->dic = 0; +} + +void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc) +{ + LzmaDec_FreeProbs(p, alloc); + LzmaDec_FreeDict(p, alloc); +} + +SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) +{ + UInt32 dicSize; + Byte d; + + if (size < LZMA_PROPS_SIZE) + return SZ_ERROR_UNSUPPORTED; + else + dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24); + + if (dicSize < LZMA_DIC_MIN) + dicSize = LZMA_DIC_MIN; + p->dicSize = dicSize; + + d = data[0]; + if (d >= (9 * 5 * 5)) + return SZ_ERROR_UNSUPPORTED; + + p->lc = d % 9; + d /= 9; + p->pb = d / 5; + p->lp = d % 5; + + return SZ_OK; +} + +static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc) +{ + UInt32 numProbs = LzmaProps_GetNumProbs(propNew); + if (p->probs == 0 || numProbs != p->numProbs) + { + LzmaDec_FreeProbs(p, alloc); + p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb)); + p->numProbs = numProbs; + if (p->probs == 0) + return SZ_ERROR_MEM; + } + return SZ_OK; +} + +SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) +{ + CLzmaProps propNew; + RINOK(LzmaProps_Decode(&propNew, props, propsSize)); + RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); + p->prop = propNew; + return SZ_OK; +} + +SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) +{ + CLzmaProps propNew; + SizeT dicBufSize; + RINOK(LzmaProps_Decode(&propNew, props, propsSize)); + RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); + dicBufSize = propNew.dicSize; + if (p->dic == 0 || dicBufSize != p->dicBufSize) + { + LzmaDec_FreeDict(p, alloc); + p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize); + if (p->dic == 0) + { + LzmaDec_FreeProbs(p, alloc); + return SZ_ERROR_MEM; + } + } + p->dicBufSize = dicBufSize; + p->prop = propNew; + return SZ_OK; +} + +SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, + const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, + ELzmaStatus *status, ISzAlloc *alloc) +{ + CLzmaDec p; + SRes res; + SizeT inSize = *srcLen; + SizeT outSize = *destLen; + *srcLen = *destLen = 0; + if (inSize < RC_INIT_SIZE) + return SZ_ERROR_INPUT_EOF; + + LzmaDec_Construct(&p); + res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc); + if (res != 0) + return res; + p.dic = dest; + p.dicBufSize = outSize; + + LzmaDec_Init(&p); + + *srcLen = inSize; + res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status); + + if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT) + res = SZ_ERROR_INPUT_EOF; + + (*destLen) = p.dicPos; + LzmaDec_FreeProbs(&p, alloc); + return res; +} diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.h b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.h new file mode 100644 index 000000000000..8e9b4410a0b7 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaDec.h @@ -0,0 +1,223 @@ +/* LzmaDec.h -- LZMA Decoder +2009-02-07 : Igor Pavlov : Public domain */ + +#ifndef __LZMA_DEC_H +#define __LZMA_DEC_H + +#include "LzmaTypes.h" + +/* #define _LZMA_PROB32 */ +/* _LZMA_PROB32 can increase the speed on some CPUs, + but memory usage for CLzmaDec::probs will be doubled in that case */ + +#ifdef _LZMA_PROB32 +#define CLzmaProb UInt32 +#else +#define CLzmaProb UInt16 +#endif + + +/* ---------- LZMA Properties ---------- */ + +#define LZMA_PROPS_SIZE 5 + +typedef struct _CLzmaProps +{ + unsigned lc, lp, pb; + UInt32 dicSize; +} CLzmaProps; + +/* LzmaProps_Decode - decodes properties +Returns: + SZ_OK + SZ_ERROR_UNSUPPORTED - Unsupported properties +*/ + +SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size); + + +/* ---------- LZMA Decoder state ---------- */ + +/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case. + Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */ + +#define LZMA_REQUIRED_INPUT_MAX 20 + +typedef struct +{ + CLzmaProps prop; + CLzmaProb *probs; + Byte *dic; + const Byte *buf; + UInt32 range, code; + SizeT dicPos; + SizeT dicBufSize; + UInt32 processedPos; + UInt32 checkDicSize; + unsigned state; + UInt32 reps[4]; + unsigned remainLen; + int needFlush; + int needInitState; + UInt32 numProbs; + unsigned tempBufSize; + Byte tempBuf[LZMA_REQUIRED_INPUT_MAX]; +} CLzmaDec; + +#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } + +void LzmaDec_Init(CLzmaDec *p); + +/* There are two types of LZMA streams: + 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. + 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ + +typedef enum +{ + LZMA_FINISH_ANY, /* finish at any point */ + LZMA_FINISH_END /* block must be finished at the end */ +} ELzmaFinishMode; + +/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!! + + You must use LZMA_FINISH_END, when you know that current output buffer + covers last bytes of block. In other cases you must use LZMA_FINISH_ANY. + + If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK, + and output value of destLen will be less than output buffer size limit. + You can check status result also. + + You can use multiple checks to test data integrity after full decompression: + 1) Check Result and "status" variable. + 2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize. + 3) Check that output(srcLen) = compressedSize, if you know real compressedSize. + You must use correct finish mode in that case. */ + +typedef enum +{ + LZMA_STATUS_NOT_SPECIFIED, /* use main error code instead */ + LZMA_STATUS_FINISHED_WITH_MARK, /* stream was finished with end mark. */ + LZMA_STATUS_NOT_FINISHED, /* stream was not finished */ + LZMA_STATUS_NEEDS_MORE_INPUT, /* you must provide more input bytes */ + LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK /* there is probability that stream was finished without end mark */ +} ELzmaStatus; + +/* ELzmaStatus is used only as output value for function call */ + + +/* ---------- Interfaces ---------- */ + +/* There are 3 levels of interfaces: + 1) Dictionary Interface + 2) Buffer Interface + 3) One Call Interface + You can select any of these interfaces, but don't mix functions from different + groups for same object. */ + + +/* There are two variants to allocate state for Dictionary Interface: + 1) LzmaDec_Allocate / LzmaDec_Free + 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs + You can use variant 2, if you set dictionary buffer manually. + For Buffer Interface you must always use variant 1. + +LzmaDec_Allocate* can return: + SZ_OK + SZ_ERROR_MEM - Memory allocation error + SZ_ERROR_UNSUPPORTED - Unsupported properties +*/ + +SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc); +void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc); + +SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc); +void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc); + +/* ---------- Dictionary Interface ---------- */ + +/* You can use it, if you want to eliminate the overhead for data copying from + dictionary to some other external buffer. + You must work with CLzmaDec variables directly in this interface. + + STEPS: + LzmaDec_Constr() + LzmaDec_Allocate() + for (each new stream) + { + LzmaDec_Init() + while (it needs more decompression) + { + LzmaDec_DecodeToDic() + use data from CLzmaDec::dic and update CLzmaDec::dicPos + } + } + LzmaDec_Free() +*/ + +/* LzmaDec_DecodeToDic + + The decoding to internal dictionary buffer (CLzmaDec::dic). + You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! + +finishMode: + It has meaning only if the decoding reaches output limit (dicLimit). + LZMA_FINISH_ANY - Decode just dicLimit bytes. + LZMA_FINISH_END - Stream must be finished after dicLimit. + +Returns: + SZ_OK + status: + LZMA_STATUS_FINISHED_WITH_MARK + LZMA_STATUS_NOT_FINISHED + LZMA_STATUS_NEEDS_MORE_INPUT + LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK + SZ_ERROR_DATA - Data error +*/ + +SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, + const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); + + +/* ---------- Buffer Interface ---------- */ + +/* It's zlib-like interface. + See LzmaDec_DecodeToDic description for information about STEPS and return results, + but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need + to work with CLzmaDec variables manually. + +finishMode: + It has meaning only if the decoding reaches output limit (*destLen). + LZMA_FINISH_ANY - Decode just destLen bytes. + LZMA_FINISH_END - Stream must be finished after (*destLen). +*/ + +SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, + const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); + + +/* ---------- One Call Interface ---------- */ + +/* LzmaDecode + +finishMode: + It has meaning only if the decoding reaches output limit (*destLen). + LZMA_FINISH_ANY - Decode just destLen bytes. + LZMA_FINISH_END - Stream must be finished after (*destLen). + +Returns: + SZ_OK + status: + LZMA_STATUS_FINISHED_WITH_MARK + LZMA_STATUS_NOT_FINISHED + LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK + SZ_ERROR_DATA - Data error + SZ_ERROR_MEM - Memory allocation error + SZ_ERROR_UNSUPPORTED - Unsupported properties + SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src). +*/ + +SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, + const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, + ELzmaStatus *status, ISzAlloc *alloc); + +#endif diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaTypes.h b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaTypes.h new file mode 100644 index 000000000000..da502ffc2279 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/LzmaTypes.h @@ -0,0 +1,239 @@ +/* Types.h -- Basic types +2010-10-09 : Igor Pavlov : Public domain */ + +#ifndef __7Z_TYPES_H +#define __7Z_TYPES_H + +/* OpenIPC: the loader has no libc headers; size_t is its string.h's */ +#include "string.h" +typedef int ptrdiff_t; +#ifndef NULL +#define NULL ((void *)0) +#endif + +#ifdef _WIN32 +#include +#endif + +#define SZ_OK 0 + +#define SZ_ERROR_DATA 1 +#define SZ_ERROR_MEM 2 +#define SZ_ERROR_CRC 3 +#define SZ_ERROR_UNSUPPORTED 4 +#define SZ_ERROR_PARAM 5 +#define SZ_ERROR_INPUT_EOF 6 +#define SZ_ERROR_OUTPUT_EOF 7 +#define SZ_ERROR_READ 8 +#define SZ_ERROR_WRITE 9 +#define SZ_ERROR_PROGRESS 10 +#define SZ_ERROR_FAIL 11 +#define SZ_ERROR_THREAD 12 + +#define SZ_ERROR_ARCHIVE 16 +#define SZ_ERROR_NO_ARCHIVE 17 + +typedef int SRes; + +#ifdef _WIN32 +typedef DWORD WRes; +#else +typedef int WRes; +#endif + +#ifndef RINOK +#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; } +#endif + +typedef unsigned char Byte; +typedef short Int16; +typedef unsigned short UInt16; + +#ifdef _LZMA_UINT32_IS_ULONG +typedef long Int32; +typedef unsigned long UInt32; +#else +typedef int Int32; +typedef unsigned int UInt32; +#endif + +#ifdef _SZ_NO_INT_64 + +/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers. + NOTES: Some code will work incorrectly in that case! */ + +typedef long Int64; +typedef unsigned long UInt64; + +#else + +#if defined(_MSC_VER) || defined(__BORLANDC__) +typedef __int64 Int64; +typedef unsigned __int64 UInt64; +#define UINT64_CONST(n) n +#else +typedef long long int Int64; +typedef unsigned long long int UInt64; +#define UINT64_CONST(n) n ## ULL +#endif + +#endif + +#ifdef _LZMA_NO_SYSTEM_SIZE_T +typedef UInt32 SizeT; +#else +typedef size_t SizeT; +#endif + +typedef int Bool; +#define True 1 +#define False 0 + + +#ifdef _MSC_VER + +#if _MSC_VER >= 1300 +#define MY_NO_INLINE __declspec(noinline) +#else +#define MY_NO_INLINE +#endif + +#define MY_CDECL __cdecl +#define MY_FAST_CALL __fastcall + +#else + +#define MY_CDECL +#define MY_FAST_CALL + +#endif + + +/* The following interfaces use first parameter as pointer to structure */ + +typedef struct +{ + Byte (*Read)(void *p); /* reads one byte, returns 0 in case of EOF or error */ +} IByteIn; + +typedef struct +{ + void (*Write)(void *p, Byte b); +} IByteOut; + +typedef struct +{ + SRes (*Read)(void *p, void *buf, size_t *size); + /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. + (output(*size) < input(*size)) is allowed */ +} ISeqInStream; + +/* it can return SZ_ERROR_INPUT_EOF */ +SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size); +SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType); +SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf); + +typedef struct +{ + size_t (*Write)(void *p, const void *buf, size_t size); + /* Returns: result - the number of actually written bytes. + (result < size) means error */ +} ISeqOutStream; + +typedef enum +{ + SZ_SEEK_SET = 0, + SZ_SEEK_CUR = 1, + SZ_SEEK_END = 2 +} ESzSeek; + +typedef struct +{ + SRes (*Read)(void *p, void *buf, size_t *size); /* same as ISeqInStream::Read */ + SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); +} ISeekInStream; + +typedef struct +{ + SRes (*Look)(void *p, const void **buf, size_t *size); + /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. + (output(*size) > input(*size)) is not allowed + (output(*size) < input(*size)) is allowed */ + SRes (*Skip)(void *p, size_t offset); + /* offset must be <= output(*size) of Look */ + + SRes (*Read)(void *p, void *buf, size_t *size); + /* reads directly (without buffer). It's same as ISeqInStream::Read */ + SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); +} ILookInStream; + +SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size); +SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset); + +/* reads via ILookInStream::Read */ +SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType); +SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size); + +#define LookToRead_BUF_SIZE (1 << 14) + +typedef struct +{ + ILookInStream s; + ISeekInStream *realStream; + size_t pos; + size_t size; + Byte buf[LookToRead_BUF_SIZE]; +} CLookToRead; + +void LookToRead_CreateVTable(CLookToRead *p, int lookahead); +void LookToRead_Init(CLookToRead *p); + +typedef struct +{ + ISeqInStream s; + ILookInStream *realStream; +} CSecToLook; + +void SecToLook_CreateVTable(CSecToLook *p); + +typedef struct +{ + ISeqInStream s; + ILookInStream *realStream; +} CSecToRead; + +void SecToRead_CreateVTable(CSecToRead *p); + +typedef struct +{ + SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize); + /* Returns: result. (result != SZ_OK) means break. + Value (UInt64)(Int64)-1 for size means unknown value. */ +} ICompressProgress; + +typedef struct +{ + void *(*Alloc)(void *p, size_t size); + void (*Free)(void *p, void *address); /* address can be 0 */ +} ISzAlloc; + +#define IAlloc_Alloc(p, size) (p)->Alloc((p), size) +#define IAlloc_Free(p, a) (p)->Free((p), a) + +#ifdef _WIN32 + +#define CHAR_PATH_SEPARATOR '\\' +#define WCHAR_PATH_SEPARATOR L'\\' +#define STRING_PATH_SEPARATOR "\\" +#define WSTRING_PATH_SEPARATOR L"\\" + +#else + +#define CHAR_PATH_SEPARATOR '/' +#define WCHAR_PATH_SEPARATOR u'/' +#define STRING_PATH_SEPARATOR "/" +#define WSTRING_PATH_SEPARATOR u"/" + +#endif + +#endif diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile new file mode 100755 index 000000000000..7306f103647b --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile @@ -0,0 +1,82 @@ +#---------------------------------------------------------------------- +# include make config file +#---------------------------------------------------------------------- +include ../../../Project/Model/ModelConfig.txt +include ../../../Project/Model/ModelConfig_$(MODEL).txt +include ../../../Project/Model/MakeConfig.txt + +#---------------------------------------------------------------------- +# set the library name here +#---------------------------------------------------------------------- +PRJ_NAME = Ctrl_Flow + + +#---------------------------------------------------------------------- +# add/delete source files here +#---------------------------------------------------------------------- +SRC = \ + main.c \ + nand_ids.c \ + spi_nor_ids.c \ + time_util.c \ + bl_u2.c\ + bl_lowlevel_init.c \ + bl_func.c \ + bl_linux.c \ + arch_timer.c \ + bl_lzma.c \ + LzmaDec.c \ + +ASM = + +#---------------------------------------------------------------------- +# set the include directory here +#---------------------------------------------------------------------- +INC_DIR = . \ + ../../../Include + +#---------------------------------------------------------------------- +# set the image output directory here +#---------------------------------------------------------------------- +IMG_BASE_DIR = ../../../ARC/Lib + +#---------------------------------------------------------------------- +# add additional C and assembly flags here +#---------------------------------------------------------------------- +CFLAGS_D = -O2 +ASMFLAGS_D = + +CFLAGS_R = -O2 +ASMFLAGS_R = + +C_DEFINE_EXT = \ + $(EXTSTRG_PARAM) \ + $(SECURE_DECRYPT_UBOOT_PARAM) \ + $(SECURE_DECRYPT_OPTEE_PARAM) \ + $(OPTEE_UBOOT_SIGNATURE_PARAM) \ + $(SECURE_DECRYPT_RTOS_PARAM) \ + $(SECURE_DECRYPT_FDT_PARAM) \ + $(SECURE_DECRYPT_KERNEL_PARAM) \ + $(BL_STORAGEINT_PARAM) \ + $(SENSOR_PARAM) \ + $(NOR_DTR_PARAM) \ + $(FASTBOOT_PARAM) \ + $(Low_Pwr_PARAM) \ + $(DDR_SIZE_ALL_IN_ON_PARAM) \ + $(SPIPINMUX_PARAM) \ + $(EMMCPINMUX_PARAM) \ + $(DIRECT_BOOT_PARAM) \ + +# Flash Frequency provided externally (make parameter) +ifneq ($(FLASH_FREQ_MHZ),) +$(info Flash Frequency: $(shell echo -e "\033[1;33m$(FLASH_FREQ_MHZ) MHz\033[0m")) +C_DEFINE_EXT += -D_FLASH_FREQ_MHZ_=$(FLASH_FREQ_MHZ) +endif + +CFLAGS_R = $(C_DEFINE_EXT) + +#---------------------------------------------------------------------- +# include common parts of the makefile +#---------------------------------------------------------------------- +MAKE_COMMON_DIR = ../../../MakeCommon +include $(MAKE_COMMON_DIR)/OutputLib.txt diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/arch_timer.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/arch_timer.c new file mode 100755 index 000000000000..14694ac13dbd --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/arch_timer.c @@ -0,0 +1,110 @@ +#include "bl_func.h" +#include "arch_timer.h" + + +#define _THUMB2 __attribute__((target("thumb"))) +#define isb() asm volatile("isb" : : : "memory") + +#if (BOOT_LINUX_SUPPORT) + +_THUMB2 unsigned int read_cntfrq(void) +{ + unsigned int freq; + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); + return freq; +} + +_THUMB2 void write_cntfrq(unsigned int freq) +{ + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(freq)); + return; +} + +_THUMB2 unsigned int read_cntkctl(void) +{ + unsigned int cntkctl; + asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r"(cntkctl)); + return cntkctl; +} + +_THUMB2 void write_cntkctl(unsigned int cntkctl) +{ + asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r"(cntkctl)); + isb(); +} + +_THUMB2 unsigned long long read_cntvct(void) +{ + unsigned long long cval; + unsigned int cval_high; + unsigned int cval_low; + + asm volatile("mrrc p15, 3, %0, %1, c14" : "=r"(cval_low), "=r"(cval_high)); + + cval = cval_high; + cval <<= 32; + cval |= cval_low; + + return cval; +} + +_THUMB2 void write_cntv_cval(unsigned long long cval) +{ + unsigned int cval_high = (unsigned int)((cval) >> 32); + unsigned int cval_low = (unsigned int)((cval) & -1); + + asm volatile("mcrr p15, 3, %0, %1, c14" : : "r"(cval_low), "r"(cval_high)); +} + +_THUMB2 unsigned int read_cntv_ctl(void) +{ + unsigned int ctl; + + asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r"(ctl)); + + return ctl; +} + +_THUMB2 void write_cntv_ctl(unsigned int ctl) +{ + asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r"(ctl)); +} + +_THUMB2 unsigned long long read_cntpct(void) +{ + unsigned long long cval; + unsigned int cval_high; + unsigned int cval_low; + + asm volatile("mrrc p15, 0, %0, %1, c14" : "=r"(cval_low), "=r"(cval_high)); + + cval = cval_high; + cval <<= 32; + cval |= cval_low; + + return cval; +} + +_THUMB2 void write_cntp_cval(unsigned long long cval) +{ + unsigned int cval_high = (unsigned int)((cval) >> 32); + unsigned int cval_low = (unsigned int)((cval) & -1); + + asm volatile("mcrr p15, 2, %0, %1, c14" : : "r"(cval_low), "r"(cval_high)); +} + +_THUMB2 unsigned int read_cntp_ctl(void) +{ + unsigned int ctl; + + asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r"(ctl)); + + return ctl; +} + +_THUMB2 void write_cntp_ctl(unsigned int ctl) +{ + asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r"(ctl)); +} + +#endif // (BOOT_LINUX_SUPPORT) \ No newline at end of file diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/arch_timer.h b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/arch_timer.h new file mode 100755 index 000000000000..6e2b7c12e500 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/arch_timer.h @@ -0,0 +1,77 @@ +#ifndef _ARCH_TIMER_H +#define _ARCH_TIMER_H + +#if defined(__aarch64__) +#define configTIMER_NUMBER 26 +#else +#define configTIMER_NUMBER 29 +#endif + +/** + * arch timer, refre to RTOS + */ +#define configCPU_CLOCK_HZ 12000000 /* for arm32 reference */ +#define configTICK_RATE_HZ 1000 +#define SYSCNT_READ_BASE (0xFFE50000) +#define SYSCNT_CTRL_BASE (0xFFE60000) + +#define CNTCR_OFF 0x000 +#define CNTSR_OFF 0x004 +#define CNTCVL_OFF 0x008 +#define CNTCVU_OFF 0x00c +#define CNTFID_OFF 0x020 + +#define CNTCR_EN (1 << 0) /* Enables the counter */ +#define CNTCR_HDBG (1 << 1) /* Halt-on-debug */ +#define CNTCR_FCREQ(x) ((x) << 8) /* Frequency change request */ + +#define CNTP_CTL_ENABLE_SHIFT 0 +#define CNTP_CTL_IMASK_SHIFT 1 +#define CNTP_CTL_ISTATUS_SHIFT 2 +#define CNTP_CTL_ENABLE_MASK 1 +#define CNTP_CTL_IMASK_MASK 1 +#define CNTP_CTL_ISTATUS_MASK 1 + +#define CNTK_CTL_ACCESS_FROM_EL0 (1<<0) + +#if (configTIMER_NUMBER == 27) /* Virtual timer */ +#define READ_CNTxCT(m) read_cntvct() +#define WRITE_CNTx_CVAL(m) write_cntv_cval(m) +#define READ_CNTx_CTL() read_cntv_ctl() +#define WRITE_CNTx_CTL(m) write_cntv_ctl(m) +#elif(configTIMER_NUMBER == 29 || configTIMER_NUMBER == 30) /* Non sec timer */ +#define READ_CNTxCT(m) read_cntpct() +#define WRITE_CNTx_CVAL(m) write_cntp_cval(m) +#define READ_CNTx_CTL() read_cntp_ctl() +#define WRITE_CNTx_CTL(m) write_cntp_ctl(m) +#elif(configTIMER_NUMBER == 26) /* Non-secure EL2 physical timer */ +#define READ_CNTxCT(m) read_cntpct() +#define WRITE_CNTx_CVAL(m) write_cnthp_cval(m) +#define READ_CNTx_CTL() read_cnthp_ctl() +#define WRITE_CNTx_CTL(m) write_cnthp_ctl(m) +#endif + +unsigned int read_cntfrq(void); +void write_cntfrq(unsigned int freq); +unsigned int read_cntkctl(void); +void write_cntkctl(unsigned int cntkctl); + +//arm virtual timer +unsigned long long read_cntvct(void); +void write_cntv_cval(unsigned long long cval); +unsigned int read_cntv_ctl(void); +void write_cntv_ctl(unsigned int ctl); + +//arm physical timer +unsigned long long read_cntpct(void); +void write_cntp_cval(unsigned long long cval); +unsigned int read_cntp_ctl(void); +void write_cntp_ctl(unsigned int ctl); + +//arm el2 physical timer +unsigned int read_cnthctl(void); +void write_cnthctl(unsigned int cnthctl); +void write_cnthp_cval(unsigned long long cval); +unsigned int read_cnthp_ctl(void); +void write_cnthp_ctl(unsigned int ctl); +#endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c new file mode 100755 index 000000000000..3ebd3717d5d3 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c @@ -0,0 +1,3622 @@ +/* + Main control function + + This file is implement by user mode + + @file bl_func.c + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ + +#include "fuart.h" +#include "fat.h" +#include "rtc.h" +#include "timer.h" +#include "StorageDef.h" +#include "global.h" +#include "Clock.h" +#include "bl_func.h" +#include "Cache.h" +#include "string.h" +#include "lz.h" +#include "debug.h" +#include "CC.h" +#include "loader.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "emb_partition_info.h" +#include "modelext_parser.h" +#include "bin_info.h" +#include "shm_info.h" +#include "gic.h" +#include "libfdt.h" +#include +#include "bl_u2.h" +#include "crypto.h" +#include "nand.h" +#include "nor.h" +#include "bl_lzma.h" +#include "bl_lowlevel_init.h" +#include "at80c51.h" +#include "bl_linux.h" + + +#if (MULTI_CODE_FLOW) +//weak function mechanism to enable ddr config on core[1] +extern void multi_core_flow(void); +void multi_core_flow(void) {} +#endif + +PSTORAGE_OBJ int_strg_obj = NULL; + +#define FW_PART1_SIZE_OFFSET (CODE_SECTION_OFFSET + 0x04) //ref to CodeInfo.S on rtos (addr of _section_01_size) +#define FW_PART1_SIZE_OFFSET64 (CODE_SECTION_OFFSET64 + 0x08) //ref to CodeInfo.S on rtos (addr of _section_01_size) +//#define TEE_HEADER_SIZE 0x1C // refer to: optee_header_t + +#define _THUMB2 __attribute__((target("thumb"))) + +#define bl_memcpy utl_memcpy +#define bl_memset utl_memset +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#define SIZE_PRELOAD 0x400 +#define SIZE_PRESERVE_USB 0x2000 +#define IS_BIN_OVERLAP(addr1, size1, addr2, size2) (!(((addr1 + size1 - 1) < addr2) || (addr1 > (addr2 + size2 - 1)))) + +typedef enum _CORE_ID { + CORE_ID_0 = 0, + CORE_ID_1 +} CORE_ID; + + +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +extern void set_usb_suspend(void); +#endif + +#if (_ROM_PUBLIC_API_ == 1) +#define ROM_LZMA_POSITION 0xbfd0 +UINT8 lzma_temp_buffer[65536]; +int (*rom_lzma_inflate)(UINT8 *in_ptr, UINT32 in_size, UINT8 *out_ptr, UINT32 out_size, UINT8 *p_tmp, UINT32 tmp_size); +#endif + +extern char _loader_exec_compres_start[]; +//extern char _load_nand_table_start_base[]; +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base[]; +extern char _load_BOOT_EXEC_start_base[]; +extern void core1_reset(void); + +// Function from Timer.c +//extern UINT32 timer_getLdrElapse(void); + +// Define in MakeConfig.txt +static UINT8 UPDATE_FW_NAME[] = {"FW98520A.BIN"}; +static UINT8 UPDATE_LOADER_NAME[] = {"LD98520A.BIN"}; +static UINT8 RUN_FW_NAME[] = {"FW98520T.BIN"}; +static UINT8 *LOADER_START_STR = {(UINT8 *)"\r\nLoader Start ..."}; +//#if !USB_WRITELOADER +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +//static UINT8 *RUN_WRKEY_NAME = {(UINT8 *)"WRKEY.BIN"}; +#if UPDATE_SIM_CODE +static UINT8 *RUN_WRKEY_NAME = {(UINT8 *)"SIM.BIN"}; +#endif +#endif +static UINT8 RECOVERY_FW_NAME[] = {"FW98520R.BIN"}; +static UINT32 g_uiPartitionID = 2; + +static UINT32 g_uiVersion = 0; + +// Error message +static char FWErrorMsg[] = "\r\nFW check fail\r\n"; +static char RWErrorMsg[] = "\r\nR/W error\r\n"; +static char LoaderErrorMsg[] = "\r\nLoader check fail\r\n"; + +UINT32 TopOfStack; +UINT32 BaseOfStack; + +extern char _loader_heap_base[]; + +static BOOL g_is_flash_open = FALSE; // indicate flash is open for updating non-fully all-in-one bin. + +static LDR_SPECIAL_KEY_CB gSpecialKeyCallBack = NULL; +static LDR_CARD_DETECT_CB gCardDetectCallBack = NULL; +static STORAGEINT gStorageIntType = STORAGEINT_UNKNOWN; + +static LDR_RECOVERY_TRIGGER_CB gRecoveryTriggerCallBack = NULL; +//#if (!USB_WRITELOADER) +//#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +//static BOOL g_is_recovery_triggered = FALSE; // indicate recovery flow is triggered. +//#endif +_THUMB2 static int bl_is_smp(unsigned char *p_fdt); +static UINT32 g_uiStartBlkUpdateFW = 0; +static UINT32 g_uiStartBlkFastFdt = 0; +static UINT32 g_uiNandBlkSize = 0; +static UINT32 g_rtos_load_addr = 0; +static UINT32 g_rtos_target_addr = 0; +static UINT32 g_rtos_size = 0; +static UINT32 g_flash_dtr = 0; + +#if (FDT_SUPPORT) +#define PATH_MEM_DRAM "/nvt_memory_cfg/dram" +#define PATH_MEM_LOADER "/nvt_memory_cfg/loader" +#define PATH_MEM_UBOOT "/nvt_memory_cfg/uboot" +#define PATH_MEM_FDT "/nvt_memory_cfg/fdt" +#define PATH_MEM_SHMEM "/nvt_memory_cfg/shmem" +#define PATH_MEM_RTOS "/nvt_memory_cfg/rtos" +#define PATH_MEM_NUTTX "/nvt_memory_cfg/nuttx" +#define PATH_MEM_TEEOS "/nvt_memory_cfg/teeos" +#define PATH_MEM_BL31 "/nvt_memory_cfg/atf" +#define PATH_MEM_HDAL "/hdal-memory/media" +#define PATH_MEM_CORE2_ENTRY1 "/nvt_memory_cfg/core2entry1" +#define PATH_MEM_CORE2_ENTRY2 "/nvt_memory_cfg/core2entry2" +#define PATH_NVT_INFO "/nvt_info" +#define PATH_NVTPACK_INDEX "nvtpack/index" +#define PATH_PARTITION_LOADER "partition_loader" +#define PATH_PARTITION_FDT "partition_fdt" +#define PATH_PARTITION_UBOOT "partition_uboot" +#define PATH_PARTITION_NUTTX "partition_nuttx" +#define PATH_PARTITION_TEEOS "partition_teeos" +#define PATH_PARTITION_RTOS "partition_rtos" +#define PATH_PARTITION_BL31 "partition_atf" +#define PATH_PARTITION_KERNEL "partition_kernel" +#define PATH_PARTITION_ROOTFS "partition_rootfs" +#define PROPERTY_REG "reg" +#define PROPERTY_LABEL "label" +#define PROPERTY_PARTITION_NAME "partition_name" +#define PROPERTY_NVT_LINUX_SMP "NVT_LINUX_SMP" +static DRAM_PARTITION g_dram_partition = {0}; +static EMB_PARTITION g_emb_uboot = {0}; +static EMB_PARTITION g_emb_teeos = {0}; +static EMB_PARTITION g_emb_rtos = {0}; +#if (BOOT_LINUX_SUPPORT) +static EMB_PARTITION g_emb_kernel = {0}; +static EMB_PARTITION g_emb_rootfs = {0}; +#endif +#else // NO FDT_SUPPORT +// refer to met-tbl.dtsi /nvt_memory_cfg +static DRAM_PARTITION g_dram_partition = { + .dram_addr = 0x00000000, + .dram_size = 0x20000000, + .rev_addr = 0x00007E00, ///< shmem + .rev_size = 0x00000200, ///< shmem + .loader_addr = 0x01000000, + .loader_size = 0x00800000, + .fdt_addr = 0x01800000, + .fdt_size = 0x00040000, + .bl31_addr = 0x00000000, + .bl31_size = 0x00000000, + .uboot_addr = 0x1E000000, + .uboot_size = 0x01FC0000, + .rtos_addr = 0x01840000, ///< optional, only for fast-boot, + .rtos_size = 0x00780000, ///< optional, only for fast-boot + .core2_entry1_addr = 0x00000000, ///< optional, only for dual core IC (fixed here, and must be) + .core2_entry1_size = 0x00004000, ///< optional, only for dual core IC + .core2_entry2_addr = 0x1FFC0000, ///< optional, only for dual core IC (address better in the bottom of dram to avoid memory space overlap) + .core2_entry2_size = 0x00040000, ///< optional, only for dual core IC +}; +// refer to storage-partition.dtsi +static EMB_PARTITION g_emb_fdt = { ///< fdt, + .PartitionOffset = 0x40000, + .PartitionSize = 0x40000, +}; +static EMB_PARTITION g_emb_fdtfast = { ///< fdt, + .PartitionOffset = 0x80000, + .PartitionSize = 0x40000, +}; +static EMB_PARTITION g_emb_uboot = { + .PartitionOffset = 0x100000, + .PartitionSize = 0x1C0000, +}; +static EMB_PARTITION g_emb_rtos = { ///< optional, only for fast-boot, + .PartitionOffset = 0x2B40000, + .PartitionSize = 0xA00000, +}; +static EMB_PARTITION g_emb_teeos = { ///< optional, only for optee, + .PartitionOffset = 0, + .PartitionSize = 0, +}; +#if (BOOT_LINUX_SUPPORT) +static EMB_PARTITION g_emb_kernel = { + .PartitionOffset = 0, + .PartitionSize = 0, +}; +static EMB_PARTITION g_emb_rootfs = { + .PartitionOffset = 0, + .PartitionSize = 0, +}; +#endif +//following just for processing all-in-one bin (nvtpack) +//refer to nvtpack.dtsi +#define NVTPACK_IDX_UBOOT 3 +#define NVTPACK_IDX_TEEOS -1 +#define NVTPACK_IDX_RTOS 10 +#define NVTPACK_IDX_BL31 -1 +#define NVTPACK_IDX_KERNEL -1 +#define NVTPACK_IDX_ROOTFS -1 +#endif + +#if (UART_UPDATE_ == ENABLE) +static char g_strLength[80]; // buffer to store length string +#endif + + +//--------------------------------------------------------------------------- +// internal function +//--------------------------------------------------------------------------- +_THUMB2 static void *bl_get_rtos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/); + +//--------------------------------------------------------------------------- +// Static function +//--------------------------------------------------------------------------- +int bl_boot_uboot(unsigned char *p_fdt); + +/** + Display error message. + + Display error message. + CPU loop forever and LED is red. + + @param Msg: Message to display + @return void +*/ +_THUMB2 static void bl_displayErrMsg(char *Msg) +{ + // Display error message to UART + debug_msg(Msg); + // Loop forever + while (1) { + ; + } +} + + +/** + Invert endianess of input word + + + @param[in] a input word + + @return translated word +*/ +_THUMB2 static UINT32 invertEndian(UINT32 a) +{ + return __builtin_bswap32(a); +} + + +/** + Check FW code. + + Check FW code and file length. + The FW binary file must be post-proecessd by encrypt_bin.exe. + This function must sync to encrypt_bin.exe. + If FW checking is fail, the CPU will loop forever and LED is red. + + @param[in] uiAddress FW code in DRAM starting address + @param[in] uiFileLen FW code length + @return void +*/ +_THUMB2 static void bl_checkFW(UINT32 uiAddress, UINT32 uiFileLen) +{ + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)uiAddress; + mem.len = uiFileLen; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + bl_displayErrMsg(FWErrorMsg); + } +} + +/** + Check boot loader code. + + Check boot loader code. + + @return void +*/ +_THUMB2 static void bl_checkLoader(UINT32 uiAddr, UINT32 uiSize) +{ + UINT16 *puiValue, uiSum; + UINT32 i; + + puiValue = (UINT16 *)uiAddr; + uiSum = 0; + + for (i = 0; i < (uiSize >> 1); i++) { + uiSum += (*puiValue + i); + puiValue++; + } + + if ((*(UINT16 *)(uiAddr + LOADER_TAG_OFFSET) != LOADER_TAG_VALUE) || + (uiSum != 0)) { + bl_displayErrMsg(LoaderErrorMsg); + } +} +#if (SECURE_DECRYPT_UBOOT || SECURE_DECRYPT_OPTEE_OS || SECURE_DECRYPT_BL31 || SECURE_DECRYPT_RTOS || SECURE_DECRYPT_FDT) + + +_THUMB2 static void get_bininfo_size_offset(unsigned char *bininfo, unsigned int *size, unsigned int *offset) +{ + /****this headinfo is for encrypt header + BinInfo will set partition offset and size + BinInfo_1[0~3] public key offset + BinInfo_1[4~7] public key length + BinInfo_2[0~3] signature offset + BinInfo_2[4~7] signature length + BinInfo_3[0~3] encrypted offset + BinInfo_3[4~7] encrypted size + BinLength total bin size + Checksum total bin checksum + others parameters set 0 + */ + *size = bininfo[4] | bininfo[5] << 8 | bininfo[6] << 16 | bininfo[7] << 24; + *offset = bininfo[0] | bininfo[1] << 8 | bininfo[2] << 16 | bininfo[3] << 24; +} + + + + +_THUMB2 static int decrypt_aes_cbc(unsigned int input, unsigned int output, unsigned int len) +{ + + CRYPT_OP crypt_op_param; + if (len & 0x0f) { + debug_msg_var("enc size", len); + debug_err("not align 16\r\n"); + return -21; + } + if ((input & 0x03) || (output & 0x03) || (len & 0x03)) { //check word alignment + //debug_msg_var("input", input); + //debug_msg_var("output", output); + //debug_msg_var("len", len); + //debug_err("not word align\r\n"); + return -22; + } + crypt_op_param.op_mode = CRYPTO_CBC; + crypt_op_param.en_de_crypt = CRYPTO_DECRYPT; + crypt_op_param.src_addr = input; + crypt_op_param.dst_addr = output; + crypt_op_param.length = len; //Need align to 16bytes align + crypt_op_param.iv_init_en= 0; + //debug_msg_var("src",(unsigned int)crypt_op_param.src_addr); + //debug_msg_var("dst",(unsigned int)crypt_op_param.dst_addr); + +#if 0 + debug_msg_var("input", input); + debug_msg_var("output", output); + debug_msg_var("len", len); + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i = 0; + debug_msg_var("encrypted buf addr", (unsigned int)tmp); + for (i = 0; i < 16; i++) { + debug_msg_var("encrypted buf", (unsigned int)tmp[i]); + } +#endif + if (crypto_data_operation(EFUSE_OTP_1ST_KEY_SET_FIELD, crypt_op_param) != 0) { + //debug_err("aes dec fail\r\n"); + return -23; + } +#if 0 + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i = 0; + tmp = (unsigned char *) crypt_op_param.dst_addr; + debug_msg_var("decryped addr", (unsigned int)&tmp[0]); + for (i = 0; i < 16; i++) { + debug_msg_var("decryped buf", (unsigned int)tmp[i]); + } + +#endif + return 0; + +} +#if (SECURE_SIGNATURE_TYPE == 0 || SECURE_SIGNATURE_TYPE == 2) +_THUMB2 static void data_reverse(unsigned char *input_data, unsigned int size) +{ + unsigned int i = 0; + unsigned char tmp = 0; + for (i = 0; i < (size / 2); i++) { + tmp = input_data[size - 1 - i]; + input_data[size - 1 - i] = input_data[i]; + input_data[i] = tmp; + } + +} + + +#endif +_THUMB2 int do_decrypt_aes(unsigned int input_data, unsigned int output_data, unsigned int *output_size, unsigned int partition_size) +{ + + unsigned int encrypt_offset = 0; + unsigned int encrypt_size = 0; + unsigned int data_size = 0; + HEADINFO *p_headinfo = (HEADINFO *)input_data; + int er = 0; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_3, &encrypt_size, &encrypt_offset); + data_size = p_headinfo->BinLength - encrypt_offset; +#if 1 //for signature check + unsigned int signature_offset = 0; + unsigned int signature_size = 0; + UINT32 hash_buf[8]; + unsigned int sha256_align_size = 0; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_2, &signature_size, &signature_offset); + + + //hash encrypt data + unsigned int sha256_size = data_size; + if (p_headinfo->BinCtrl & SIGN_BINCTRL_LIMITED_SIZE) { + sha256_size = p_headinfo->Resv1[HEADINFO_SIGN_RESV_IDX_LIMITED_SIZE]; + } + if ((sha256_size & 0x3f) != 0) { + // hardware sha256 need align 64, need set pending 0 + sha256_align_size = ((sha256_size / 0x40) + 1) * 0x40; + bl_memset((unsigned char *)(input_data + encrypt_offset + sha256_size), 0, sha256_align_size - sha256_size); + } else { + sha256_align_size = sha256_size; + } + shahw((unsigned char *)(input_data + encrypt_offset), sha256_align_size, hash_buf); + + +#if (SECURE_SIGNATURE_TYPE == 0) // RSA + unsigned int key_offset = 0; + UINT32 *signature_buff = NULL; + unsigned int key_size = 0; + unsigned int n_size = 0; + unsigned int e_size = 0; + UINT32 sign_rsa_output[64]; + UINT32 *key_n = NULL; + UINT32 *key_e = NULL; + UINT32 *signature_addr = NULL; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_1, &key_size, &key_offset); + n_size = signature_size;// if rsa 2048 , signature_size should be 256 bytes + e_size = key_size - n_size; + key_n = (UINT32 *)(input_data + key_offset); + // now only support rsa 2048 + key_e = (UINT32 *)(input_data + key_offset + signature_size); // signature_size should be 256 bytes, n key should be 256 + data_reverse((unsigned char *)(key_n), n_size); + data_reverse((unsigned char *)(key_e), e_size); + + er = rsa_keycheck(key_n, 1);// check rsa n key in efuse 1 and 2 field, 0 field for aes key + if (er == 0) { + bl_displayErrMsg("key fail\r\n"); + return -20; + } + signature_addr = (UINT32 *)(input_data + signature_offset); + data_reverse((unsigned char *)signature_addr, signature_size); + + //decrypt signature + rsa_decrypt(signature_addr, signature_size, key_n, n_size, key_e, e_size, sign_rsa_output); + + data_reverse((unsigned char *)sign_rsa_output, signature_size); + + //remove pending data 0, the last 32 bytes will be signature data + signature_buff = (UINT32 *)&sign_rsa_output[(sizeof(sign_rsa_output) / 4) - (32 / 4)]; // offset need devided by 4, because of UINT32 type + + //compare signature and current hash + if (memcmp((void *)hash_buf, (void *)signature_buff, sizeof(hash_buf)) != 0) { + //bl_displayErrMsg("sig fail\r\n"); + return -20; + } +#elif (SECURE_SIGNATURE_TYPE == 1)// aes + //UINT32 sign_aes_output[8]; + + UINT32 *signature_buff = NULL; + er = decrypt_aes_cbc((UINT32)(input_data + signature_offset), output_data, signature_size); + if (er != 0) { + debug_err("decrypt_aes_cbc fail\r\n"); + return -20; + } + signature_buff = (UINT32 *)output_data; + + //compare signature and current hash + if (memcmp((void *)hash_buf, (void *)signature_buff, sizeof(hash_buf)) != 0) { + //bl_displayErrMsg("sig fail\r\n"); + return -20; + } +#elif (SECURE_SIGNATURE_TYPE == 2)//ecdsa + unsigned int key_offset = 0; + unsigned int key_size = 0; + unsigned int x_size = 0; + unsigned int y_size = 0; + unsigned int r_size = 0; + + UINT32 *key_x = NULL; + UINT32 *key_y = NULL; + UINT32 *sign_r = NULL; + UINT32 *sign_s= NULL; + UINT32 test_result=0; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_1, &key_size, &key_offset); + x_size = key_size/2;// if ecdas + y_size = x_size; + + key_x = (UINT32 *)(input_data + key_offset); + key_y = (UINT32 *)(input_data + key_offset + x_size); + + +#if 0 + debug_msg_var("y_size", y_size); + unsigned int i = 0; + for (i = 0; i < (y_size/4); i++) { + debug_msg_var("key_x", (unsigned int)key_x[i]); + debug_msg_var("key_y", (unsigned int)key_y[i]); + } +#endif + + + data_reverse((unsigned char *)(key_x), x_size); + data_reverse((unsigned char *)(key_y), y_size); +#if 0 + for (i = 0; i < (y_size/4); i++) { + debug_msg_var("key_x", (unsigned int)key_x[i]); + debug_msg_var("key_y", (unsigned int)key_y[i]); + } +#endif + r_size = signature_size/2; + sign_r = (UINT32 *)(input_data + signature_offset); + sign_s = (UINT32 *)(input_data + signature_offset + r_size); + + debug_msg_var("r_size", r_size); +#if 0 + for (i = 0; i < (r_size/4); i++) { + debug_msg_var("sign_r", (unsigned int)sign_r[i]); + debug_msg_var("sign_s", (unsigned int)sign_s[i]); + } +#endif + + data_reverse((unsigned char *)(sign_r), r_size); + data_reverse((unsigned char *)(sign_s), r_size); +#if 0 + for (i = 0; i < (r_size/4); i++) { + debug_msg_var("sign_r", (unsigned int)sign_r[i]); + debug_msg_var("sign_s", (unsigned int)sign_s[i]); + } + for (i = 0; i < 8; i++) { + debug_msg_var("hash_buf", (unsigned int)hash_buf[i]); + } +#endif + data_reverse((unsigned char *)(hash_buf), 32); + +#if 0 + for (i = 0; i < 8; i++) { + debug_msg_var("hash_buf", (unsigned int)hash_buf[i]); + } +#endif + test_result = ecdsa_verify(hash_buf, key_x, key_y, sign_r, sign_s); + if(test_result){ + debug_msg("ecdsa pass\r\n"); + } + else{ + debug_msg("ecdsa fail\r\n"); + return -20; + } +#else // type not support + debug_err("not support this SECURE_SIGNATURE_TYPE\r\n"); + return -20; +#endif + + +#endif + if (p_headinfo->BinCtrl & SIGN_BINCTRL_NO_ENCRYPTIONDATA) { + // for rtos partial load, the partition_size is part1 size. in this case, partition_size will smaller than data_size + *output_size = (partition_size < data_size)? partition_size: data_size; + utl_memcpy((unsigned char *)output_data, (unsigned char *)(input_data + encrypt_offset), *output_size); + } else { + //decrypt data + //dma addr should 4 alignment, input_data address is 4 alignment + if ((input_data + encrypt_offset) & 0x03) { + utl_memcpy((void *)input_data, (unsigned char *)(input_data + encrypt_offset), data_size); + er = decrypt_aes_cbc(input_data, output_data, encrypt_size); + } else { + er = decrypt_aes_cbc(input_data + encrypt_offset, output_data, encrypt_size); + } + if (er != 0) { + //bl_displayErrMsg("aes fail\r\n"); + return er; + } + + *output_size = data_size; + + //add plaintext data to output buf--> aes should 16 alignment, if data not alignment, the last bytes we will not encrypt data + int plaintext_size = data_size - encrypt_size; + unsigned char *p_output = (unsigned char *)output_data; + if (plaintext_size > 0) { + utl_memcpy(&p_output[encrypt_size], (unsigned char *)(input_data + encrypt_offset + encrypt_size), plaintext_size); + } + } + return 0; + +} +#endif + +//#NT#2013/04/25#Steven Wang -begin +//#NT#Show Duty calibration log +#if (_LOADER_DUTY_CALIBRATION_ == ENABLE && _LOADER_DUTY_CALIBRATION_LOG_ == ENABLE) +void BL_showROMLog(UINT32 buffer) +{ + UINT32 value; + UINT32 index; + UINT32 P_duty; + UINT32 N_duty; + UINT32 diff; + + index = 0; + diff = 0; + P_duty = 0; + N_duty = 0; + uart_putSystemUARTStr("\r\n"); + while (1) { + value = INREG32(buffer + index); + + if ((value & 0xF0000000) == 0xF0000000) { + value &= ~(0x40000000); + uart_putSystemUARTStr(Dec2HexStr(value)); + uart_putSystemUARTStr(" = "); + } + + else if ((value & 0xF0000000) == 0x50000000) { + uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr("\r\n"); + } + + else if ((value & 0xF0000000) == 0x20000000) { +// uart_putSystemUARTStr("P_duty = "); + P_duty = value & 0xFFFFFFF; + //uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr(Dec2HexStr(P_duty)); + uart_putSystemUARTStr("\r\n"); + } + + else if ((value & 0xF0000000) == 0x30000000) { +// uart_putSystemUARTStr("N_duty = "); + N_duty = value & 0xFFFFFFF; + //uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr(Dec2HexStr(N_duty)); + uart_putSystemUARTStr("\r\n"); + if (P_duty > N_duty) { + if (diff == 2) { + uart_putSystemUARTStr("============\r\n"); + P_duty = 0; + N_duty = 0; + diff = 0; +// diff = 3; + } else { + diff = 1; + } + } else { + if (diff == 1) { + uart_putSystemUARTStr("============\r\n"); + P_duty = 0; + N_duty = 0; + diff = 0; +// diff = 3; + } else { + diff = 2; + } + } + } else if ((value & 0xF0000000) == 0x60000000) { + uart_putSystemUARTStr("N+P = "); + uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr("\r\n"); + } else if ((value & 0xF0000000) == 0x70000000) { + if ((value & 0xFFFFFFF) == 0x0654321) { + break; + } + } else { + uart_putSystemUARTStr("Unknow \r\n"); + } + index += 4; + } + uart_putSystemUARTStr("\r\n[0xC0001000] = 0x"); + uart_putSystemUARTStr(Dec2HexStr(INREG32(0xC0001000))); + uart_putSystemUARTStr(" [0xC000101C] = 0x"); + uart_putSystemUARTStr(Dec2HexStr(INREG32(0xC000101C))); + uart_putSystemUARTStr("\r\n"); +} +#endif +//#NT#2013/04/25#Steven Wang -end + + +#if (DRAM_RANGE_SCAN_EN == ENABLE) +/** + Check Sram code. + + Check is dram scan code or not + + @param[in] uiAddress Scan FW code in DRAM starting address + @return void +*/ +static BOOL bl_checkDramScanFW(UINT32 uiAddress) +{ + if ((*(UINT32 *)uiAddress & SRAM_TAG) == SRAM_TAG) { + return TRUE; + } else { + return FALSE; + } +} +#endif + +#if 0 +static BOOL bl_spiIdentify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + // Sample to support SST25VF032 + if ((uiMfgID == 0xBF) && + (uiCapacityID == 0x4A)) { + pIdentify->bDualRead = FALSE; + pIdentify->bSupportAAI = TRUE; + pIdentify->bSupportEWSR = TRUE; + pIdentify->uiFlashSize = 4 * 1024 * 1024; + return TRUE; + } + + return FALSE; +} +#endif + +/* + Update multi-binary image + + + @param[in] uiFwBuf buffer store fw read from card + + @return + -@ b TRUE: success + -@ b FALSE: fail +*/ + +#if !REMOVED_FLASH +#if 0 +static void bl_interrupt_init(void) +{ + debug_msg("arm_gic_distif_setup\r\n"); + arm_gic_distif_setup(); + debug_msg("arm_gic_cpuif_setup\r\n"); + arm_gic_cpuif_setup(); + + // + //debug_dump_addr(0xF1500000+0x1000,0x500); + //debug_dump_addr(0xF1500000+0x2000,0x100); +} +#endif + +#endif +_THUMB2 int bl_flash_open(void) +{ + int er; + + if (g_is_flash_open) { + return 0; + } + + //========================================================================== + //= User define SPI-NAND id table sample code = + //= You can remove // to use it = + //========================================================================== + //int_strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_IDENTIFY_CB, (UINT32)nand_identify); + + //========================================================================== + //= User define SPI-NOR id table sample code = + //= You can remove // to use it = + //========================================================================== +#if (_NOR_DTR_PARAM_ == ENABLE) //DTR force enable + int_strg_obj->flash_installIdentifyCB(nor_identify); +#endif + +#if defined(_FLASH_FREQ_MHZ_) + int_strg_obj->flash_setFrequency(_FLASH_FREQ_MHZ_); +#endif + + if (!bl_lowlevel_is_flash_opened()) { +#if (_NOR_DTR_PARAM_ == ENABLE) //DTR force enable + int_strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_DTR, TRUE); + g_flash_dtr = 1; +#endif + er = int_strg_obj->flash_open(); + if (er < 0) { + debug_err("flash open fail\r\n"); + return -1; + } + } + + g_uiNandBlkSize = int_strg_obj->flash_getBlockSize(); + + +#if (FDT_SUPPORT) + if (g_uiNandBlkSize == 0x10000) { + debug_msg("SPI NOR\r\n"); + g_uiStartBlkUpdateFW = 1; + } else if (g_uiNandBlkSize == EMMC_BLOCK_SIZE) { + debug_msg("EMMC\r\n"); + g_uiStartBlkUpdateFW = FDT_OFFSET / EMMC_BLOCK_SIZE; + } else { + g_uiStartBlkUpdateFW = 2; + } + g_uiStartBlkFastFdt = FDTFAST_OFFSET / g_uiNandBlkSize; +#else + g_uiStartBlkUpdateFW = (UINT32)(g_emb_fdt.PartitionOffset/g_uiNandBlkSize); + g_uiStartBlkFastFdt = (UINT32)(g_emb_fdtfast.PartitionOffset/g_uiNandBlkSize); +#endif + + g_is_flash_open = TRUE; + return 0; +} + +#if 0 //[-Werror=unused-function] +static int bl_flash_close(void) +{ + if (!g_is_flash_open) { + return 0; + } + + flash_close(); + g_is_flash_open = FALSE; + return 0; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static const void *bl_get_fdt_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + int nodeoffset; /* next node offset from libfdt */ + const void *nodep; /* property node pointer */ + + nodeoffset = fdt_path_offset(p_dtb, p_path); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} + +_THUMB2 static const void *bl_get_fdt_nvt_memory_cfg_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + static int nodeoffset_nvt_memory_cfg = -FDT_ERR_NOTFOUND;; /* next node offset from libfdt */ + + int nodeoffset; + const void *nodep; /* property node pointer */ + + if (strncmp(p_path, "/nvt_memory_cfg/", 3) != 0) { + debug_err("path prefix must be /nvt_memory_cfg/\r\n"); + return NULL; + } + + if (nodeoffset_nvt_memory_cfg == -FDT_ERR_NOTFOUND) { + nodeoffset_nvt_memory_cfg = fdt_path_offset(p_dtb, "/nvt_memory_cfg"); + } + + nodeoffset = fdt_subnode_offset(p_dtb, nodeoffset_nvt_memory_cfg, &p_path[16]); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} +#endif + + +_THUMB2 static unsigned char *bl_get_fdt_cfg(const void *p_dtb, MODELEXT_TYPE type) +{ +#if (FDT_SUPPORT) + int len; + const int *nodep; + + UINT8 *p_rt = NULL; + + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_DRAM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get dram fail\r\n"); + return NULL; + } + g_dram_partition.dram_addr = be32_to_cpu(nodep[0]); + g_dram_partition.dram_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_LOADER, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get loader fail\r\n"); + return NULL; + } + g_dram_partition.loader_addr = be32_to_cpu(nodep[0]); + g_dram_partition.loader_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_UBOOT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get uboot fail\r\n"); + return NULL; + } + g_dram_partition.uboot_addr = be32_to_cpu(nodep[0]); + g_dram_partition.uboot_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_FDT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get fdt fail\r\n"); + return NULL; + } + g_dram_partition.fdt_addr = be32_to_cpu(nodep[0]); + g_dram_partition.fdt_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_RTOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.rtos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.rtos_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_NUTTX, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.nuttx_addr = be32_to_cpu(nodep[0]); + g_dram_partition.nuttx_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_TEEOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.teeos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.teeos_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_CORE2_ENTRY1, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.core2_entry1_addr = be32_to_cpu(nodep[0]); + g_dram_partition.core2_entry1_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_CORE2_ENTRY2, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.core2_entry2_addr = be32_to_cpu(nodep[0]); + g_dram_partition.core2_entry2_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_BL31, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.bl31_addr = be32_to_cpu(nodep[0]); + g_dram_partition.bl31_size = be32_to_cpu(nodep[1]); + } + + p_rt = (UINT8 *)&g_dram_partition; + break; + + case MODELEXT_TYPE_BIN_INFO: + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_SHMEM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get shmem fail\r\n"); + return NULL; + } + + if (sizeof(SHMINFO) > be32_to_cpu(nodep[1])) { + debug_err("shmem size mismatch\r\n"); + return NULL; + } + + p_rt = (UINT8 *)be32_to_cpu(nodep[0]); + break; + + default: + debug_err_var("not handle type\r\n", type); + return NULL; + } + return p_rt; +#else // NO FDT_SUPPORT + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + return (UINT8 *)&g_dram_partition; + case MODELEXT_TYPE_BIN_INFO: + return (UINT8 *)g_dram_partition.rev_addr; + default: + return NULL; + } +#endif +} + +_THUMB2 int bl_chk_valid_all_in_one(NVTPACK_MEM *p_mem_all_in_one) +{ + NVTPACK_ER er; + NVTPACK_VER ver; + + er = nvtpack_getver(p_mem_all_in_one, &ver); + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + if (ver == NVTPACK_VER_16072017) { + return 0; + } + + return -1; +} + + +#if !REMOVED_FLASH +_THUMB2 int bl_chk_fdt(unsigned int addr, unsigned int size) +{ + DRAM_PARTITION *p_dram_partition = NULL; + + if (bl_lowlevel_get_fdt() == 0) { + if (fdt_check_full((void *)addr, size) != 0) { + debug_err("invalid dtb\r\n"); + return -1; + } + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)addr, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("invalid dram_partition\r\n"); + return -1; + } + + // check tmp memory (file load) cannot overlap with uboot and teeos + // we allow to overlap with linux, root-fs because uboot will reload bin file later + debug_msg_var("tmp_addr", SDRAM_Start_FW); + + if (IS_BIN_OVERLAP(addr, size, p_dram_partition->uboot_addr, p_dram_partition->uboot_size)) { + debug_err_var("a", addr); + debug_err_var("s", size); + debug_err("uboot olp\r\n"); + return -1; + } + + if (p_dram_partition->teeos_size) { + if (IS_BIN_OVERLAP(addr, size, p_dram_partition->teeos_addr, p_dram_partition->teeos_size)) { + debug_err_var("a", addr); + debug_err_var("s", size); + debug_err("teeos olp\r\n"); + return -1; + } + } + + // check if memory size matched real size + #if (_FPGA_EMULATION_ == 1) + UINT32 ld_dram1_size = 0x80000000; + #else + UINT32 ld_dram1_size = dma_get_dram_capacity(DMA_ID_1); + #endif + if (p_dram_partition->dram_size > ld_dram1_size) { + debug_err_var("fw_d1_s", p_dram_partition->dram_size); + debug_err_var("ld_d1_s", ld_dram1_size); + debug_err("d1 s not matched\r\n"); + return -1; + } + return 0; +} +#endif + +#if !REMOVED_FLASH +_THUMB2 int bl_chk_uboot(unsigned int addr, unsigned int size) +{ +#if (_FPGA_EMULATION_ == 0) + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)addr; + mem.len = size; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + debug_err("uboot check sum fail\r\n"); + return -1; + } +#endif + return 0; +} + +_THUMB2 static int bl_entry_boot(unsigned char *p_fdt, UINT32 jump_entry, CORE_ID core_id) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + bl_lowlevel_cpu_timer_init(); + + debug_msg_var("fdt", (UINT32)p_fdt); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_fdt; + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + + // clear cc_core1_addr, cc_core2_addr +#if (USB_WRITELOADER || UART_UPDATE) + if (ROM_GetCurrBS() == BOOT_SOURCE_UART) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_UART; + } else if ((ROM_GetCurrBS() == BOOT_SOURCE_USB)||(ROM_GetCurrBS() == BOOT_SOURCE_USB_FULL)) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; + } else { + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; + } +#elif (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +#else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif + + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + { + debug_msg_var("jump", jump_entry); +#if (MULTI_CODE_FLOW) + if (core_id == 0) { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)jump_entry; + p_func(); + } else { + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + // pass timestamp list to rtos + unsigned long perf_addr = 0; + int perf_cnts = 0; + perf_get_buf(&perf_addr, &perf_cnts); + p_bininfo->comm.Resv[COMM_RESV_IDX_LD_TIME_ADDR] = perf_addr; + p_bininfo->comm.Resv[COMM_RESV_IDX_LD_TIME_CNTS] = perf_cnts; + + // to avoid optimize + volatile UINT32 *p_polling_linux_addr = &p_bininfo->comm.Resv[COMM_RESV_IDX_CORE1_LINUX_ADDR]; + volatile UINT32 *p_polling_fdt_addr = &p_bininfo->comm.Resv[COMM_RESV_IDX_CORE1_FDT_ADDR]; + + *p_polling_linux_addr = 0; + *p_polling_fdt_addr = 0; + + /** + * ife, ipe, ime sram will be replace on rtos + * here must release mmu first, because mmu table uses the ipe sram + */ + DISABLE_MMU(); + CLEAR_MMU(); + + bl_lowlevel_core2_setaddr(jump_entry); + debug_msg("wait core[0] addr\r\n"); + + while (*p_polling_linux_addr == 0) { + } + + unsigned int kernel_addr = *p_polling_linux_addr; + unsigned int r2 = *p_polling_fdt_addr; + //do not show anything, because ife sram switch from cpu to ife + //it will cause loader hang + //printf("jump = %X, fdt = %X\r\n", kernel_addr, r2); + *(volatile unsigned int *)0xF0290000 = '%'; + *(volatile unsigned int *)0xF0290000 = '%'; + + __asm__("cps #0x13"); + void (*kernel_entry)(int zero, int arch, unsigned int params); + kernel_entry = (void (*)(int, int, unsigned int))((kernel_addr)); + kernel_entry(0, 0, r2); // never returned + } +#else + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)jump_entry; + p_func(); +#endif + } + + return 0; +} + +_THUMB2 int bl_copy_fdt_to_fdt_addr(unsigned char *p_fdt /*IN*/, unsigned char **pp_fdt /*OUT*/) +{ + DRAM_PARTITION *p_dram_partition; + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("bl_copy_fdt_to_fdt_addr failed.\r\n"); + return -1; + } + + // load fdt to fdt buffer + utl_memcpy((void *)p_dram_partition->fdt_addr, p_fdt, fdt_totalsize(p_fdt)); + *pp_fdt = (unsigned char *)p_dram_partition->fdt_addr; + + //reset shminfo + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + bl_memset(p_bininfo, 0, sizeof(SHMINFO)); + return 0; +} + +_THUMB2 static int bl_load_fdt_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char **pp_fdt /*OUT*/) +{ + NVTPACK_ER er; + NVTPACK_MEM emb_fdt; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + debug_err("packbin verify failed.\r\n"); + return -1; + } + + np_get_input.id = 1; // fdt must always put in partition[1] + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt); + + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } else if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + debug_msg_var("fdt addr", (int)emb_fdt.p_data); + debug_msg_var("fdt size", (int)emb_fdt.len); + + if (IS_SECURE() == 0 || SECURE_DECRYPT_FDT == 0) { + if (bl_chk_fdt((unsigned int)emb_fdt.p_data, emb_fdt.len) == 0) { + if ((er = bl_copy_fdt_to_fdt_addr(emb_fdt.p_data, pp_fdt)) != 0) { + return er; + } + } + } else { +#if (SECURE_DECRYPT_FDT) + unsigned int plaintext_size = 0; + if (fdt_check_header((void *)emb_fdt.p_data) != 0) { + // encrypted + if ((er = do_decrypt_aes((unsigned int)emb_fdt.p_data, (unsigned int)emb_fdt.p_data, &plaintext_size, emb_fdt.len)) != 0) { + //debug_err("aes fail\r\n"); + return er; + } + } else { + debug_err("fdt not encrypted."); + return -1; + } + if (bl_chk_fdt((unsigned int)emb_fdt.p_data, emb_fdt.len) == 0) { + if ((er = bl_copy_fdt_to_fdt_addr(emb_fdt.p_data, pp_fdt)) != 0) { + return er; + } + } +#else + debug_err("pls enable SECURE_DECRYPT_FDT"); + return -1; +#endif + } + + np_get_input.id = 2; // fdt-fastboot must always put in partition[2] + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt); + if (er == NVTPACK_ER_NOT_FOUND) { + unsigned char *p_fdt_hdr = (unsigned char *)bl_lowlevel_get_fdtfast(); + if (p_fdt_hdr) { + DRAM_PARTITION *p_dram_partition; + int fdt_size = fdt_totalsize(*pp_fdt); + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)*pp_fdt, MODELEXT_TYPE_DRAM_PARTITION); + UINT32 fdt_fastboot_addr = (UINT32)(*pp_fdt) + ALIGN_CEIL(fdt_size, 64); + int fdtfast_size = fdt_totalsize(p_fdt_hdr); + UINT32 fdt_mempool_size_require = ALIGN_CEIL(fdt_size, 64) + fdtfast_size; + if (fdt_mempool_size_require <= p_dram_partition->fdt_size) { + utl_memcpy((void *)fdt_fastboot_addr, p_fdt_hdr, fdtfast_size); + g_flash_dtr = bl_lowlevel_is_dtr_tunned(); + debug_msg_var("fdt-fast ", fdt_fastboot_addr); + } else { + // fdtfast size too large or fdtfast not exist + // try to erase flash to clean previous fastboot firmware + debug_err_var("fdt-fast skip-3", fdt_mempool_size_require); + } + } else { + debug_msg("fdt-fast skip-1\r\n"); + } + return 0; + } else if (er != NVTPACK_ER_SUCCESS) { + debug_msg("fdt-fast skip-2\r\n"); + return 0; + } + + unsigned int forcc = *(unsigned int *)emb_fdt.p_data; + if (forcc == DTR_TUNNING_PATTERN_DATA1 || forcc == DTR_TUNNING_PATTERN_DATA2) { + if (emb_fdt.len <= DTR_TUNNING_PATTERN_SIZE) { + debug_msg("fdt-fast skip-3\r\n"); + return 0; + } else { + emb_fdt.p_data = (unsigned char *)emb_fdt.p_data + DTR_TUNNING_PATTERN_SIZE; + emb_fdt.len -= DTR_TUNNING_PATTERN_SIZE; + } + } + + if (fdt_check_full((void *)emb_fdt.p_data, emb_fdt.len) != 0) { + debug_msg("fdt-fast skip-4\r\n"); + return 0; + } + DRAM_PARTITION *p_dram_partition; + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)*pp_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + return -1; + } + UINT32 fdtsize = fdt_totalsize(*pp_fdt); + UINT32 fdt_fastboot_addr = (UINT32)(*pp_fdt) + ALIGN_CEIL(fdtsize, 64); + UINT32 fdt_mempool_size_require = ALIGN_CEIL(fdtsize, 64) + fdt_totalsize(emb_fdt.p_data); + if (fdt_mempool_size_require > p_dram_partition->fdt_size) { + debug_err_var("2 fdt size too large ", fdt_mempool_size_require); + return -1; + } + utl_memcpy((void *)fdt_fastboot_addr, emb_fdt.p_data, fdt_totalsize(emb_fdt.p_data)); + debug_msg_var("fdt-fast ", fdt_fastboot_addr); + return 0; +} + +_THUMB2 static unsigned int bl_load_rtos_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char *p_fdt, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int rtos_partition_id = 0; + UINT32 uItron_fw_addr = 0; + NVTPACK_ER er; + NVTPACK_MEM emb_rtos; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + debug_err("packbin verify failed.\r\n"); + return 0; + } + + EMB_PARTITION *p_emb_partition_rtos = bl_get_rtos_partition(p_fdt, &rtos_partition_id); + + if (p_emb_partition_rtos == NULL) { + debug_err("null p_emb_partition_rtos\r\n"); + return -1; + } + + np_get_input.id = rtos_partition_id; + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_rtos); + + if (er == NVTPACK_ER_NOT_FOUND) { + return 0; + } else if (er == NVTPACK_ER_SUCCESS) { + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + HEADINFO *p_headinfo = (HEADINFO *)(emb_rtos.p_data + BIN_INFO_OFFSET_RTOS); + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)emb_rtos.p_data; + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + *p_comp_addr = (UINT32)emb_rtos.p_data; + *p_comp_size = (UINT32)emb_rtos.len; + uItron_fw_addr = p_dram_partition->rtos_addr; + } else { + *p_comp_addr = 0; + *p_comp_size = 0; + uItron_fw_addr = p_headinfo->CodeEntry;// - CODE_SECTION_OFFSET; + utl_memcpy((void *)uItron_fw_addr, emb_rtos.p_data, emb_rtos.len); + CPUflushWriteCache(uItron_fw_addr, emb_rtos.len); + } + } + + debug_msg_var("uItron_fw_addr=", uItron_fw_addr); + return uItron_fw_addr; +} + +_THUMB2 static int bl_load_fdt_from_flash(unsigned char *p_tmp, unsigned int tmp_size, unsigned char **pp_fdt /*OUT*/) +{ + unsigned char *p_fdt_hdr = NULL; + + perf_mark("lfdt-b"); + + // read first block to get dtb size + int blk_size = (int)int_strg_obj->flash_getBlockSize(); + + int er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, blk_size, p_tmp, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash\r\n"); + return -1; + } + + if (IS_SECURE() == 0 || SECURE_DECRYPT_FDT == 0) { + p_fdt_hdr = (unsigned char *)bl_lowlevel_get_fdt(); + /* + * OpenIPC: the tree in a BCL1 LZMA container (openipc/ + * nvt-image.py). This SDK's trees are ~95 KiB, its clocks + * described in them; plain, one would not leave U-Boot a + * 128 KiB slot before the environment at 0x40000. + */ + NVTPACK_BFC_HDR *p_bfc = (NVTPACK_BFC_HDR *)p_tmp; + if (p_fdt_hdr == NULL && + p_bfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1') && + (cpu_to_be32(p_bfc->uiAlgorithm) & 0xFF) == 11) { + UINT32 size_comp = invertEndian(p_bfc->uiSizeComp); + UINT32 size_uncomp = invertEndian(p_bfc->uiSizeUnComp); + int total_size = ALIGN_CEIL(size_comp + sizeof(NVTPACK_BFC_HDR), blk_size); + unsigned char *p_out = p_tmp + total_size; + + if (tmp_size < total_size + size_uncomp) { + debug_err_var("tmp_size too small, require:", total_size + size_uncomp); + return -1; + } + if (total_size > blk_size) { + er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW + 1, total_size - blk_size, p_tmp + blk_size, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash\r\n"); + return -1; + } + } + if (bl_lzma_inflate(p_tmp + sizeof(NVTPACK_BFC_HDR), size_comp, p_out, size_uncomp) < 0) { + debug_err("fdt lzma\r\n"); + return -1; + } + p_fdt_hdr = p_out; + } + if (p_fdt_hdr == NULL) { + int fdt_size = fdt_totalsize(p_tmp); + int total_size = ALIGN_CEIL(fdt_size, blk_size); + if ((int)tmp_size < total_size) { + debug_err_var("tmp_size too small, require:", total_size); + return -1; + } + total_size -= blk_size; + if (total_size > 0) { + // read remain to get uboot starting addr on dram and offset in flash + er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW + 1, total_size, p_tmp + blk_size, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash\r\n"); + return -1; + } + } + p_fdt_hdr = p_tmp; + } + if (bl_chk_fdt((unsigned int)p_fdt_hdr, fdt_totalsize(p_fdt_hdr)) != 0) { + return -1; + } + if (bl_copy_fdt_to_fdt_addr(p_fdt_hdr, pp_fdt) != 0) { + return -1; + } + } else { +#if (SECURE_DECRYPT_FDT) + unsigned int plaintext_size = 0; + int bin_size = ((HEADINFO *)(p_tmp))->BinLength; + + if (bin_size > blk_size) { + if ((er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW + 1, ALIGN_CEIL(bin_size, blk_size) - blk_size, (UINT8 *)p_tmp + blk_size, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_fdt_from_flash,er=", er); // read bfc-bl31 failed + bl_displayErrMsg(RWErrorMsg); + } + } + if ((er = do_decrypt_aes((unsigned int)p_tmp, (unsigned int)p_tmp, &plaintext_size, bin_size)) != 0) { + debug_err("aes fail\r\n"); + return er; + } + if (bl_chk_fdt((unsigned int)p_tmp, fdt_totalsize(p_tmp)) == 0) { + if ((er = bl_copy_fdt_to_fdt_addr(p_tmp, pp_fdt)) != 0) { + return er; + } + } +#else + debug_err("pls enable SECURE_DECRYPT_FDT"); + return -1; +#endif + } + + p_fdt_hdr = (unsigned char *)bl_lowlevel_get_fdtfast(); + if (p_fdt_hdr) { + DRAM_PARTITION *p_dram_partition; + int fdt_size = fdt_totalsize(*pp_fdt); + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)*pp_fdt, MODELEXT_TYPE_DRAM_PARTITION); + UINT32 fdt_fastboot_addr = (UINT32)(*pp_fdt) + ALIGN_CEIL(fdt_size, 64); + int fdtfast_size = fdt_totalsize(p_fdt_hdr); + UINT32 fdt_mempool_size_require = ALIGN_CEIL(fdt_size, 64) + fdtfast_size; + if (fdt_mempool_size_require <= p_dram_partition->fdt_size) { + utl_memcpy((void *)fdt_fastboot_addr, p_fdt_hdr, fdtfast_size); + g_flash_dtr = bl_lowlevel_is_dtr_tunned(); + debug_msg_var("fdt-fast ", fdt_fastboot_addr); + + } else { + // fdtfast size too large or fdtfast not exist + // try to erase flash to clean previous fastboot firmware + debug_err_var("fdt-fast skip-3", fdt_mempool_size_require); + } + perf_mark("lfdt-e"); + return 0; + } else { +#if (FDTFAST_FROM_DRAM != ENABLE) + debug_msg("skip fdtfast\r\n"); + perf_mark("lfdt-e"); + return 0; +#endif + } + + perf_mark("lfdt-sys"); + +#if (FDTFAST_FROM_DRAM == ENABLE) + int fdt_size = fdt_totalsize(p_tmp); +#if 0// (_NOR_DTR_PARAM_ == ENABLE) auto tunning not ready yet + if(int_strg_obj->flash_auto_tune_read_block) { + if ((er = int_strg_obj->flash_auto_tune_read_block(g_uiStartBlkFastFdt, 0x1000, p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("tunning command fail, use original config,er=", er); + //bl_displayErrMsg(RWErrorMsg); // read bl31 failed + } else { + g_flash_dtr = 1; + debug_msg("auto tunning success\r\n"); + } + } +#endif + er = int_strg_obj->flash_readSectors(g_uiStartBlkFastFdt, blk_size, p_tmp, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash-2\r\n"); + return -1; + } + + unsigned int fdt_tunning_offset = 0; + unsigned int forcc = *(unsigned int *)p_tmp; + if (forcc == DTR_TUNNING_PATTERN_DATA1 || forcc == DTR_TUNNING_PATTERN_DATA2) { + fdt_tunning_offset += DTR_TUNNING_PATTERN_SIZE; + } + + p_fdt_hdr = p_tmp + fdt_tunning_offset; + + if (fdt_check_header(p_fdt_hdr) != 0) { + debug_msg("skip fdtfast\r\n"); + return 0; + } + + int fdtfast_size = fdt_totalsize(p_fdt_hdr); + fdtfast_size = ALIGN_CEIL(fdtfast_size + fdt_tunning_offset, blk_size); + if ((int)tmp_size < fdtfast_size) { + debug_err_var("tmp_size too small, require2:", fdtfast_size); + return -1; + } + + fdtfast_size -= blk_size; + if (fdtfast_size > 0) { + // read remain to get uboot starting addr on dram and offset in flash + er = int_strg_obj->flash_readSectors(g_uiStartBlkFastFdt + 1, fdtfast_size, p_tmp + blk_size, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash-2"); + return -1; + } + } + + if (fdt_check_full(p_fdt_hdr, fdt_totalsize(p_fdt_hdr)) != 0) { + debug_msg("skip fdtfast-2\r\n"); + return 0; + } + + if (p_fdt_hdr) { + DRAM_PARTITION *p_dram_partition; + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)*pp_fdt, MODELEXT_TYPE_DRAM_PARTITION); + UINT32 fdt_fastboot_addr = (UINT32)(*pp_fdt) + ALIGN_CEIL(fdt_size, 64); + int fdtfast_size = fdt_totalsize(p_fdt_hdr); + UINT32 fdt_mempool_size_require = ALIGN_CEIL(fdt_size, 64) + fdtfast_size; + if (fdt_mempool_size_require > p_dram_partition->fdt_size) { + debug_err_var("2nd fdt size too large ", fdt_mempool_size_require); + return -1; + } + + utl_memcpy((void *)fdt_fastboot_addr, p_fdt_hdr, fdtfast_size); + debug_msg_var("fdt-fast ", fdt_fastboot_addr); + +#if (FDTFAST_SENSOR==ENABLE) + if (bl_sensor_chgmode((void *)fdt_fastboot_addr, 1) != 0) { + debug_err("sen chgmode NG\r\n"); + return -1; + } +#endif + } +#endif + perf_mark("lfdt-e"); + return 0; +} + +#if (FDT_SUPPORT) +_THUMB2 static int bl_get_partition_fdt_offset(unsigned char *p_fdt) +{ + const char *name = NULL; + static int nodeoffset = -FDT_ERR_NOTFOUND; + + if (nodeoffset > 0) { + return nodeoffset; + } + + const static char *p_names[3] = { + "/nand", + "/nor", + "mmc2" + }; + +#if !defined(_STORAGEINT_NONE_) + switch (gStorageIntType) { + case STORAGEINT_SPI_NAND: + name = p_names[0]; + break; + case STORAGEINT_SPI_NOR: + name = p_names[1]; + break; + case STORAGEINT_EMMC: + name = p_names[2]; + break; + default: + debug_err("loader_setStorageIntType needs.\r\n"); + return NULL; + } + + +#else + int i; + const static char *p_pathes[3] = { + "/nand/partition_uboot", + "/nor/partition_uboot", + "/mmc2/partition_uboot" + }; + for (i = 0; i < 3; i++) { + nodeoffset = fdt_path_offset(p_fdt, p_pathes[i]); + if (nodeoffset > 0 ) { + name = p_names[i]; + break; + } + } + if (name == NULL) { + debug_err("E:bl_get_partition_name\r\n"); + return NULL; + } +#endif + nodeoffset = fdt_path_offset(p_fdt, name); + if (nodeoffset < 0) { + debug_err("E:bl_get_partition_name\r\n"); + } + return nodeoffset; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static const void *bl_get_fdt_partition_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + int nodeoffset_partition = bl_get_partition_fdt_offset((unsigned char *)p_dtb); + + int nodeoffset; + const void *nodep; /* property node pointer */ + + if (nodeoffset_partition < 0) { + debug_err("nodeoffset_partition invalid \r\n"); + return NULL; + } + + nodeoffset = fdt_subnode_offset(p_dtb, nodeoffset_partition, p_path); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static int bl_get_partition(unsigned char *p_fdt /*IN*/, char *p_emb_name /*IN*/, EMB_PARTITION *p_emb/*OUT*/, int *p_id) +{ + int len; + const unsigned long long *nodep; + + // get partition offset and size + nodep = (const unsigned long long *)bl_get_fdt_partition_property(p_fdt, p_emb_name, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("bl_get_partition-1\r\n"); + return -1; + } + + p_emb->PartitionOffset = be64_to_cpu(nodep[0]); + p_emb->PartitionSize = be64_to_cpu(nodep[1]); + + // get partition label + char *p_label_name = (char *)bl_get_fdt_partition_property(p_fdt, p_emb_name, PROPERTY_LABEL, &len); + if (p_label_name == NULL) { + debug_err("bl_get_partition-2\r\n"); + return -1; + } + + // get id + int nodeoffset_partition = bl_get_partition_fdt_offset(p_fdt); + int nodeoffset = fdt_subnode_offset(p_fdt, nodeoffset_partition, "nvtpack"); + nodeoffset = fdt_subnode_offset(p_fdt, nodeoffset, "index"); + + for (nodeoffset = fdt_first_subnode(p_fdt, nodeoffset); + (nodeoffset >= 0); + (nodeoffset = fdt_next_subnode(p_fdt, nodeoffset))) { + const struct fdt_property *prop; + + if (!(prop = fdt_get_property(p_fdt, nodeoffset, PROPERTY_PARTITION_NAME, &len))) { + break; + } + const char *p_id_name = fdt_get_name(p_fdt, nodeoffset, &len); + + if (strcmp(p_label_name, (char *)prop->data) == 0) { + *p_id = atoi(p_id_name + strlen("id")); + return 0; + } + } + + return -1; +} +#endif + +_THUMB2 static void *bl_get_uboot_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_UBOOT, &g_emb_uboot, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_UBOOT; +#endif + g_emb_uboot.EmbType = EMBTYPE_UBOOT; + return &g_emb_uboot; +} + +_THUMB2 static void *bl_get_rtos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_RTOS, &g_emb_rtos, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_RTOS; +#endif + g_emb_rtos.EmbType = EMBTYPE_RTOS; + return &g_emb_rtos; +} + +_THUMB2 static void *bl_get_teeos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_TEEOS, &g_emb_teeos, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_TEEOS; +#endif + g_emb_teeos.EmbType = EMBTYPE_TEEOS; + + return &g_emb_teeos; +} +#endif + +#if (BOOT_LINUX_SUPPORT) +_THUMB2 void *bl_get_kernel_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_KERNEL, &g_emb_kernel, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_KERNEL; +#endif + g_emb_kernel.EmbType = EMBTYPE_LINUX; + return &g_emb_kernel; +} +#endif + +#if (BOOT_LINUX_SUPPORT) +_THUMB2 void *bl_get_rootfs_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_ROOTFS, &g_emb_rootfs, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_ROOTFS; +#endif + g_emb_rootfs.EmbType = EMBTYPE_ROOTFS; + return &g_emb_rootfs; +} +#endif + +// return decompress_fw_size +_THUMB2 static unsigned int bl_decompress_rtos(UINT32 compress_addr, UINT32 compress_size, UINT32 fw_base_addr) +{ + UINT32 decoded_size; + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)compress_addr; + UINT32 algorithm = invertEndian(pBfc->uiAlgorithm) & 0xFF; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + + switch(algorithm) { + case 9: // LZ77 + size_comp_le = (compress_size < size_comp_le) ? compress_size : size_comp_le; + decoded_size = LZ_Un_compress((UINT8 *)compress_addr + sizeof(NVTPACK_BFC_HDR), (UINT8 *)fw_base_addr, size_comp_le); + break; +#if (_GZIP_ENABLE_API_ == 1) + case 12: // GZ + size_comp_le = (compress_size < size_comp_le) ? compress_size : size_comp_le; + decoded_size = GZ_Uncompress((UINT8 *)compress_addr + sizeof(NVTPACK_BFC_HDR), (UINT8 *)fw_base_addr, size_comp_le); + break; +#endif + default: + debug_err_var("unsupported comp", algorithm); + return 0; + } + + //because some padding bytes are decoded, we must return real rtos size + return (decoded_size < size_uncomp_le) ? decoded_size : size_uncomp_le; +} + +#if !REMOVED_FLASH +_THUMB2 static int bl_load_uboot_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_uboot; + int uboot_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)uboot_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_uboot); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + //debug_msg_var("uboot_size", p_dram_partition->uboot_size); + if (IS_SECURE() == 0 || SECURE_DECRYPT_UBOOT == 0) { + if (bl_chk_uboot((unsigned int)mem_uboot.p_data, mem_uboot.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_uboot.p_data + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_uboot.p_data; // describe compressed u-boot + + // load uboot bin to dram partiton location + //debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + //debug_msg_var("uboot_size", p_dram_partition->uboot_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + if ((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF) == 11) { +#if (_ROM_PUBLIC_API_ == 1) + UINT32 lzma_addr = *(UINT32 *)ROM_LZMA_POSITION; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + if(rom_public_api_available() < 0) { + debug_err("lzma API un-correct(overwrite by someone else)\r\n"); + return -1; + } + rom_lzma_inflate = (int (*)(UINT8 *, UINT32, UINT8 *, UINT32, UINT8 *, UINT32))((lzma_addr)); + rom_lzma_inflate(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), size_comp_le, (unsigned char *) p_dram_partition->uboot_addr, size_uncomp_le, (UINT8 *)lzma_temp_buffer, 65536); + debug_msg("lzma "); + +#else + debug_msg("Can not support LZMA\r\n"); +#endif + } else { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Un_compress(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->uboot_addr, size_comp_le); + debug_msg("lz"); + } + } else { + debug_msg("nml"); + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, p_headinfo->BinLength); + } + } else { +#if (SECURE_DECRYPT_UBOOT) + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, mem_uboot.len); + unsigned int plaintext_size = 0; + + if ((er = do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size)) != 0) { + debug_err_var("aes fail, er=", er); + return er; + } + if (bl_chk_uboot((unsigned int)p_dram_partition->uboot_addr, plaintext_size) != 0) { + return -1; + } +#else + debug_msg("please enable SECURE_DECRYPT_UBOOT\r\n"); + return -1; +#endif + } + + return 0; +} + +_THUMB2 static int bl_load_teeos_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_teeos; + int teeos_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_teeos = bl_get_teeos_partition(p_fdt, &teeos_partition_id); + HEADINFO *p_headinfo = NULL; + if (p_emb_partition_teeos == NULL) { + debug_err("null p_emb_partition_teeos\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)teeos_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_teeos); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + if (IS_SECURE() == 0 || SECURE_DECRYPT_OPTEE_OS == 0) { + p_headinfo = (HEADINFO *)(mem_teeos.p_data + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot + utl_memcpy((void *)p_dram_partition->teeos_addr, (unsigned char *)mem_teeos.p_data, p_headinfo->BinLength); + } else { +#if (SECURE_DECRYPT_OPTEE_OS) + unsigned int plaintext_size = 0; + utl_memcpy((void *)p_dram_partition->teeos_addr, mem_teeos.p_data, mem_teeos.len); + if ((er = do_decrypt_aes(p_dram_partition->teeos_addr, p_dram_partition->teeos_addr, &plaintext_size, p_dram_partition->teeos_size)) != 0) { + //debug_err("aes fail\r\n"); + return er; + } + + //this is the second headinfo information , not encrpyted headinfo + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); +#else + debug_err("please enable SECURE_DECRYPT_OPTEE_OS"); + return -1; +#endif + } + UINT32 teeos_addr = (UINT32)p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR]; + + //check addr matched or not + debug_msg_var("teeos_addr", p_dram_partition->teeos_addr); + if (teeos_addr != p_dram_partition->teeos_addr) { + debug_msg_var("teeos_addr(bin)", teeos_addr); + debug_err("teeos addr not matched.\r\n"); + return -1; + } + + // using check uboot's check sum is ok + if (bl_chk_uboot((unsigned int)teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } + + return 0; +} + +_THUMB2 static int bl_load_uboot_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int uboot_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + debug_msg("l_uboot\r\n"); + + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(BIN_INFO_OFFSET_UBOOT + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_uboot_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read uboot failed + return -1; + } + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + //debug_msg_var("uboot_size", p_dram_partition->uboot_size); + + if (IS_SECURE() == 0 || SECURE_DECRYPT_UBOOT == 0) { + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(size_comp_le + sizeof(NVTPACK_BFC_HDR), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_uboot_from_flash_comp,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + if ((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF) == 11) { + if (invertEndian(pBfc->uiSizeUnComp) > p_dram_partition->uboot_size) { + debug_err_var("uboot_size", invertEndian(pBfc->uiSizeUnComp)); + return -1; + } +#if (_ROM_PUBLIC_API_ == 1) + UINT32 lzma_addr = *(UINT32 *)ROM_LZMA_POSITION; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + rom_lzma_inflate = (int (*)(UINT8 *, UINT32, UINT8 *, UINT32, UINT8 *, UINT32))((lzma_addr)); + rom_lzma_inflate(p_tmp + sizeof(NVTPACK_BFC_HDR), size_comp_le, (unsigned char *) p_dram_partition->uboot_addr, size_uncomp_le, (UINT8 *)lzma_temp_buffer, 65536); + debug_msg("lzma "); +#else + /* OpenIPC: the loader's own decoder (bl_lzma.c) */ + if (bl_lzma_inflate(p_tmp + sizeof(NVTPACK_BFC_HDR), size_comp_le, + (unsigned char *)p_dram_partition->uboot_addr, + invertEndian(pBfc->uiSizeUnComp)) < 0) { + debug_err("lzma\r\n"); + return -1; + } + debug_msg("lzma "); +#endif + } else { + LZ_Un_compress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->uboot_addr, size_comp_le); + } + } else { + if (p_headinfo->BinLength > p_dram_partition->uboot_size) { + debug_err_var("uboot_size", p_headinfo->BinLength); + return -1; + } + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + } else { +#if (SECURE_DECRYPT_UBOOT) + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); // describe uncompressed u-boot + if (p_headinfo->BinLength > p_dram_partition->uboot_size) { + debug_err_var("encrypted_uboot_size", p_headinfo->BinLength); + return -1; + } + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + unsigned int plaintext_size = 0; + if ((er = do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size)) != 0) { + //debug_err("aes fail\r\n"); + return er; + } +#else + debug_msg("please enable SECURE_DECRYPT_UBOOT config\r\n"); + return -1; +#endif + } + + //uboot check sum + { + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->uboot_addr + BIN_INFO_OFFSET_UBOOT); + debug_msg_var("uboot_size", p_headinfo->BinLength); + if (bl_chk_uboot((unsigned int)p_dram_partition->uboot_addr, p_headinfo->BinLength) != 0) { + return -1; + } + } + return 0; +} + +_THUMB2 static int bl_load_rtos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp, int arrch64_mode) +{ + int er; + int rtos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_rtos = bl_get_rtos_partition(p_fdt, &rtos_partition_id); + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + perf_mark("lrtos-b"); + + if (p_emb_partition_rtos == NULL) { + debug_err("null p_emb_partition_rtos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + debug_msg("l_rtos\r\n"); + + // load 1st block of rtos to tmp dram (to detect compressed u-boot) + unsigned int bininfo_preload_size = ALIGN_CEIL(BIN_INFO_OFFSET_RTOS + sizeof(HEADINFO), blk_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, bininfo_preload_size, p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read rtos failed + } + + if (IS_SECURE() == 0 || SECURE_DECRYPT_RTOS == 0) { + // flow to handle compressed u-boot and uncompressed one. + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + // load rtos bin to dram partiton location + //debug_msg_var("rtos_addr", p_dram_partition->rtos_addr); + //debug_msg_var("rtos_size", p_dram_partition->rtos_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + + if ((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF) == 11) { + /* lzma compressed image*/ + debug_msg("lzma, use uboot\r\n"); + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { + UINT32 algorithm = invertEndian(pBfc->uiAlgorithm) & 0xFF; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, ALIGN_CEIL(size_comp_le + sizeof(NVTPACK_BFC_HDR), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_comp,er=", er); // read bfc-rtos failed + bl_displayErrMsg(RWErrorMsg); + } + switch(algorithm) { + case 9: // LZ77 + LZ_Un_compress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->rtos_addr, size_comp_le); + break; +#if (_GZIP_ENABLE_API_ == 1) + case 12: // GZ + GZ_Uncompress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->rtos_addr, size_comp_le); + break; +#endif + default: + debug_err_var("unsupported comp", algorithm); + return 0; + } + + } + } else { + BININFO *p_bininfo = (BININFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); // describe uncompressed u-boot + if (p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN) { + // copy bininfo_preload to rtos_addr + bl_memcpy((UINT8 *)p_dram_partition->rtos_addr, p_tmp, bininfo_preload_size); + // preload some to get part-1 size for partial load and partial compressed load + UINT32 preload_size = ALIGN_CEIL(FW_PART1_SIZE_OFFSET64, blk_size) - bininfo_preload_size; + + if (preload_size != 0) { + er = int_strg_obj->flash_readSectors( + (p_emb_partition_rtos->PartitionOffset + bininfo_preload_size) / blk_size, + preload_size, + (UINT8 *)(p_dram_partition->rtos_addr + bininfo_preload_size), NAND_RW_FIRMWARE + ); + + if (er < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + UINT32 part1_size = 0; + if (arrch64_mode) { + part1_size = *(UINT32 *)(p_dram_partition->rtos_addr + FW_PART1_SIZE_OFFSET64); + } else { + part1_size = *(UINT32 *)(p_dram_partition->rtos_addr + FW_PART1_SIZE_OFFSET); + } + debug_msg_var("part1_size", part1_size); + part1_size = ALIGN_CEIL(part1_size, blk_size); + //debug_msg_var("part1_size_aligned",part1_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, part1_size, (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = part1_size; + } else { + // full load + debug_msg_var("rtos_size", p_bininfo->head.BinLength); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, ALIGN_CEIL(p_bininfo->head.BinLength, blk_size), (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = p_bininfo->head.BinLength; + } + } + } else { +#if (SECURE_DECRYPT_RTOS) + unsigned int encrypt_offset = 0; + unsigned int encrypt_size = 0; + unsigned int is_partial_load = 0; + BININFO *p_bininfo = NULL; + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); + + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_3, &encrypt_size, &encrypt_offset); + // signature only + partial load + if (p_headinfo->BinCtrl & SIGN_BINCTRL_NO_ENCRYPTIONDATA) { + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)(p_tmp + encrypt_offset); + if (pBfc->uiFourCC != MAKEFOURCC('B', 'C', 'L', '1')) { + BININFO *p_bininfo = (BININFO *)(p_tmp + encrypt_offset + BIN_INFO_OFFSET_RTOS); // describe uncompressed u-boot + if (p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN) { + is_partial_load = 1; + } + } + } + if (is_partial_load) { + // copy bininfo_preload to rtos_addr + bl_memcpy((UINT8 *)p_dram_partition->rtos_addr, p_tmp, bininfo_preload_size); + // preload some to get part-1 size for partial load and partial compressed load + UINT32 preload_size = ALIGN_CEIL(FW_PART1_SIZE_OFFSET64+encrypt_offset, blk_size) - bininfo_preload_size; + if (preload_size != 0) { + er = int_strg_obj->flash_readSectors( + (p_emb_partition_rtos->PartitionOffset + bininfo_preload_size) / blk_size, + preload_size, + (UINT8 *)(p_dram_partition->rtos_addr + bininfo_preload_size), NAND_RW_FIRMWARE + ); + + if (er < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + UINT32 part1_size = 0; + if (arrch64_mode) { + part1_size = *(UINT32 *)(p_dram_partition->rtos_addr + FW_PART1_SIZE_OFFSET64 + encrypt_offset); + } else { + part1_size = *(UINT32 *)(p_dram_partition->rtos_addr + FW_PART1_SIZE_OFFSET + encrypt_offset); + } + debug_msg_var("part1_size", part1_size); + UINT32 decrypt_size = ALIGN_CEIL(part1_size + encrypt_offset, blk_size); + part1_size = decrypt_size - encrypt_offset; + //debug_msg_var("part1_size_aligned",part1_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, decrypt_size, (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); + bl_displayErrMsg(RWErrorMsg); + } + + unsigned int plaintext_size = 0; + if ((er = do_decrypt_aes(p_dram_partition->rtos_addr, p_dram_partition->rtos_addr, &plaintext_size, decrypt_size)) != 0) { + debug_err("aes fail\r\n"); + return er; + } + + p_bininfo = (BININFO *)(p_dram_partition->rtos_addr + BIN_INFO_OFFSET_RTOS); + // update loaded size + p_shminfo->boot.LdLoadSize = part1_size; + p_bininfo->Resv[0] = encrypt_offset; + } else { + int bin_size = ((HEADINFO *)(p_tmp))->BinLength; + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, ALIGN_CEIL(bin_size, blk_size), (UINT8 *)p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); // read bfc-bl31 failed + bl_displayErrMsg(RWErrorMsg); + } + + unsigned int plaintext_size = 0; + if ((er = do_decrypt_aes((unsigned int)p_tmp, (unsigned int)p_tmp, &plaintext_size, p_dram_partition->rtos_size)) != 0) { + debug_err("aes fail\r\n"); + return er; + } + + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + if ((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF) == 11) { + /* lzma compressed image*/ + debug_msg("lzma, use uboot\r\n"); + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else if ((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF) == 12) { +#if (_GZIP_ENABLE_API_ == 1) + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + GZ_Uncompress((UINT8 *)p_tmp + sizeof(NVTPACK_BFC_HDR), (UINT8 *)p_dram_partition->rtos_addr, size_comp_le); +#else + debug_err_var("unsupported comp", cpu_to_be32(pBfc->uiAlgorithm) & 0xFF); +#endif + } else { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Un_compress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->rtos_addr, size_comp_le); + } + } else { + p_bininfo = (BININFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); + bl_memcpy((unsigned char *)p_dram_partition->rtos_addr, p_tmp, p_bininfo->head.BinLength); + } + + p_bininfo = (BININFO *)(p_dram_partition->rtos_addr + BIN_INFO_OFFSET_RTOS); + if (p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN) { + // FW_TYPE_NORMAL or ENCRYPTIONDATA_NONE + SIGNATURE_SHASIZE(512) required + debug_err("ENCRYPTIONDATA_NONE + SIGNATURE_SHASIZ required\r\n"); + return -1; + } + // update loaded size + p_shminfo->boot.LdLoadSize = p_bininfo->head.BinLength; + } +#else + debug_err("please ENABLE SECURE_DECRYPT_RTOS config\n"); + return -1; +#endif + } + + // update boot.LdCtrl2 + if (g_flash_dtr) { + p_shminfo->boot.LdCtrl2 |= LDCF_DTR80_BOOT; + } + + if (bl_lowlevel_is_fast_sensor()) { + p_shminfo->boot.LdCtrl2 |= LDCF_FAST_SENSOR; + } + + debug_msg_var("LdCtrl2", p_shminfo->boot.LdCtrl2); + + perf_mark("lrtos-e"); + + return 0; +} + +_THUMB2 static int bl_load_teeos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int teeos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + int bin_size; + HEADINFO *p_headinfo = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_teeos = bl_get_teeos_partition(p_fdt, &teeos_partition_id); + + if (p_emb_partition_teeos == NULL) { + debug_err("null p_emb_partition_teeos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + debug_msg("l_tee\r\n"); + + // load 1st block of u-boot to tmp dram (to detect compressed u-boot) + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_teeos->PartitionOffset / blk_size, ALIGN_CEIL(BIN_INFO_OFFSET_TEEOS + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_teeos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read teeos failed + } + + // flow to handle compressed u-boot and uncompressed one. +#if (SECURE_DECRYPT_OPTEE_OS) + bin_size = ((HEADINFO *)(p_tmp))->BinLength; +#else + bin_size = ((HEADINFO *)(p_tmp + BIN_INFO_OFFSET_TEEOS))->BinLength; +#endif + + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_teeos->PartitionOffset / blk_size, ALIGN_CEIL(bin_size, blk_size), (UINT8 *)p_dram_partition->teeos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_teeos_from_flash,er=", er); // read bfc-teeos failed + bl_displayErrMsg(RWErrorMsg); + } + + if (IS_SECURE() == 0 || SECURE_DECRYPT_OPTEE_OS == 0) { + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); + } else { +#if (SECURE_DECRYPT_OPTEE_OS) + unsigned int plaintext_size = 0; + if ((er = do_decrypt_aes(p_dram_partition->teeos_addr, p_dram_partition->teeos_addr, &plaintext_size, p_dram_partition->teeos_size)) != 0) { + //debug_err("aes fail\r\n"); + return er; + } + + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot +#else + debug_err("please ENABLE SECURE_DECRYPT_OPTEE_OS config\n"); + return -1; +#endif + } + + // load teeos bin to dram partiton location + UINT32 teeos_addr = (UINT32)p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR]; + debug_msg_var("teeos_addr", p_dram_partition->teeos_addr); + if (teeos_addr != p_dram_partition->teeos_addr) { + debug_msg_var("teeos_addr(bin)", teeos_addr); + debug_err("teeos addr not matched.\r\n"); + return -1; + } + //check check sum + debug_msg_var("teeos_size", p_headinfo->BinLength); + if (bl_chk_uboot((unsigned int)teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } + return 0; +} +#endif + +#if !(USB_WRITELOADER || UART_UPDATE) +_THUMB2 static int bl_load_rtos_from_non_nvtpack(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + HEADINFO *p_headinfo = (HEADINFO *)(src_addr + BIN_INFO_OFFSET_RTOS); + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + // to avoid rtos_addr is overlapped by src_addr, we need extract some bits to get real rtos addr. + // compressed firmware + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr + SIZE_PRELOAD); + p_headinfo = (HEADINFO *)(src_addr + SIZE_PRELOAD + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //adjust src_addr that lay compressed f.w followed by uncompressed f.w + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = fat_read_rootfile((UINT8 *)src_addr, compress_size); + } else { + return -1; + } + } else if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + // uncompressed firmware + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + + src_size = fat_read_rootfile((UINT8 *)src_addr, uncompress_size); + src_addr = uncompress_addr; + src_size = uncompress_size; + debug_msg("uncompressed t.bin\r\n"); +#if (DRAM_RANGE_SCAN_EN == ENABLE) + } else if (utl_is_sram_fw(src_addr) == TRUE) { + debug_msg("detected as SRAM fw\r\n"); + src_size = fat_read_rootfile((UINT8 *)src_addr, FAT_READ_TOTAL_FILE_LENGTH); +#endif + } else { + return -1; + } + + *p_dst_addr = src_addr; + *p_dst_size = src_size; + return 0; +} +#endif + +_THUMB2 static void bl_update_uItron_headInfo(UINT32 fw_base_addr, DRAM_PARTITION *p_dram_partition) +{ + HEADINFO *pHeadInfo; +#if (UITRON_FW == ENABLE) + BININFO *pBinInfo; +#endif + pHeadInfo = (HEADINFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + if (p_dram_partition) { + pHeadInfo->ModelextAddr = p_dram_partition->fdt_addr; + pHeadInfo->Resv1[HEADINFO_RESV_IDX_DRAM_SIZE] = p_dram_partition->dram_size; + } else { + pHeadInfo->ModelextAddr = 0; +#if (UITRON_FW == ENABLE) + pBinInfo = (BININFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + pBinInfo->ld.Resv[0] = LoaderInternalInfo[1]; + pBinInfo->ld.LdPackage = (LoaderInternalInfo[3] & 0xFFFF); +#endif + } +} + +_THUMB2 static int bl_update_loader_bininfo(unsigned char *p_fdt, unsigned int ld_flag, unsigned int rtos_loaded_size) +{ + BOOTINFO *p_ld; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + BININFO *p_bininfo = (BININFO *)(p_dram_partition->rtos_addr + BIN_INFO_OFFSET_RTOS); + + p_ld = &p_shminfo->boot; + if (!(p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN)) { + // LdLoadSize updated on uboot or bl_load_rtos_from_flash(), if BOOT_FLAG_PARTLOAD_EN + p_ld->LdLoadSize = rtos_loaded_size; + } + p_ld->LdLoadTime = timer_getLdrElapse(); + p_ld->LdResvSize = 0; //unused + p_ld->FWResvSize = 0; //unused + return 0; +} + +_THUMB2 static int bl_is_smp(unsigned char *p_fdt) +{ +#if (FDT_SUPPORT) + int len; + const char *nodep; + nodep = (const char *)bl_get_fdt_property(p_fdt, PATH_NVT_INFO, PROPERTY_NVT_LINUX_SMP, &len); + if (nodep == NULL) { + return 0; + } + if (strcmp(nodep, "NVT_LINUX_SMP_ON") == 0) { + return 1; + } + return 0; +#else + return 1; +#endif +} + +#if !REMOVED_FLASH +_THUMB2 int bl_boot_uboot(unsigned char *p_fdt) +{ + UINT32 No_CPU; + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update shminfo + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + unsigned int *p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_shminfo->boot.LdPackage = p_param[3] & 0xFFFF; + p_shminfo->boot.LdStorage = (p_param[3] >> 16) & 0xFF; + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->uboot_addr + BIN_INFO_OFFSET_UBOOT); + + if (bl_chk_uboot(p_dram_partition->uboot_addr, p_headinfo->BinLength) != 0) { + return -1; + } + // start cpu2 + if (p_dram_partition->uboot_addr != p_headinfo->CodeEntry) { + debug_err_var("drampat-uboot_addr ", (int)p_dram_partition->uboot_addr); + debug_err_var("bin-uboot_addr ", (int)p_headinfo->CodeEntry); + return -1; + } + // for uboot to indicate this boot is all-in-one fw or non-all-in-one boot from uart or usb + // if boot from uart or usb with non-all-in-one fw, the uboot's ModelextAddr will be zero + p_headinfo->ModelextAddr = p_dram_partition->fdt_addr; + + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + + No_CPU = cc_getCoreCount(); + debug_msg_var("core_cnt=", No_CPU + 1); + + UINT32 isSMP = bl_is_smp(p_fdt); + if (!isSMP || !No_CPU || (!MULTI_CODE_FLOW)) { + debug_msg("!mp(uboot)\r\n"); + bl_entry_boot(p_fdt, p_headinfo->CodeEntry, CORE_ID_0); + } else { + if (p_dram_partition->rtos_addr) { + debug_msg("amp(uboot)\r\n"); + bl_entry_boot(p_fdt, p_headinfo->CodeEntry, CORE_ID_1); + } else { + debug_msg("smp(uboot)\r\n"); + bl_entry_boot(p_fdt, p_headinfo->CodeEntry, CORE_ID_0); + } + } + return 0; +} + +_THUMB2 static int bl_boot_teeos(unsigned char *p_fdt, int to_uboot) +{ + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); + + // do not checksum uboot or kernel here + // ,because teeos header has removed cause checksum failed + + if (to_uboot) { + // update uboot addr for teeos + p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_UBOOT_ADDR] = p_dram_partition->uboot_addr; + //flush uboot + CPUflushWriteCache(p_dram_partition->uboot_addr, p_dram_partition->uboot_size); + //flush teeos + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + } else { + // update fdt, kernel addr for teeos + unsigned long kernel_addr = 0; + unsigned long fdt_addr = 0; + if (linuxboot_go_info(&kernel_addr, &fdt_addr) == 0) { + printf("=> %08X %08X\r\n", kernel_addr, fdt_addr); + p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_KERNEL_ENTRY_ADDR] = kernel_addr; + p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_KERNEL_FDT_ADDR] = fdt_addr; + } else { + debug_err("kernel_addr NG\r\n"); + return -1; + } + + system_init_timer(); + } + + bl_entry_boot(p_fdt, p_headinfo->CodeEntry, CORE_ID_0); + // boot teeos and never return back to loader + return 0; +} + +_THUMB2 static int bl_update_loader_flag(unsigned char *p_fdt, UINT32 uiLoaderFunc) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + + p_bininfo->boot.LdCtrl2 = 0; + if (uiLoaderFunc & FUNC_UPDATE_FW) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_FW; + } + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_LD; + } + if (uiLoaderFunc & FUNC_RUN_CARD) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_CARD; + } + if (uiLoaderFunc & FUNC_RUN_FLASH) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_FLASH; + } + + if (IS_AT80C51_OPENED()) { + p_bininfo->boot.LdCtrl2 |= LDCF_8051_BOOT; + } + + //CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + debug_msg_var("LdCtrl2", p_bininfo->boot.LdCtrl2); + + unsigned int ver; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + BOOTINFO *p_ld = &p_shminfo->boot; + + utl_memset(p_ld->LdInfo_1, 0, sizeof(p_ld->LdInfo_1)); + utl_memcpy(p_ld->LdInfo_1, "LD_NVT", 6); + + ver = (((LoaderInternalInfo[1] >> 28) & 0xF) << 24) | + (((LoaderInternalInfo[1] >> 24) & 0xF) << 16) | + ((LoaderInternalInfo[1] >> 16) & 0xFF); + + if (g_uiVersion == 0) { + g_uiVersion = ver; + } + + utl_memcpy(&p_ld->LdInfo_1[8], &g_uiVersion, sizeof(g_uiVersion)); + unsigned int *p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_ld->LdPackage = p_param[3] & 0xFFFF; + p_ld->LdStorage = (p_param[3] >> 16) & 0xFF; + + return 0; +} + +// return uItron_fw_addr +_THUMB2 unsigned int bl_process_all_in_one(UINT32 uiFwBuf, UINT32 uiFwBufSize, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + + // load fdt + er = bl_load_fdt_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, &p_fdt); + if (er == -2) { // try to load from nand + debug_msg("fdt from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + er = bl_load_fdt_from_flash(p_tmp, 0x2000000, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + if (uiLoaderFunc & FUNC_UPDATE_FW) { + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + p_bininfo->comm.Resv[5] = uiFwBuf; // COMM_FW_UPD_ADDR + p_bininfo->comm.Resv[6] = uiFwBufSize; // COMM_FW_UPD_LEN + debug_msg_var("upd_src_addr=", uiFwBuf); + debug_msg_var("upd_src_size=", uiFwBufSize); + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + //check loader addr is matched with loader self. + extern char _loader_exec_compres_start[]; + if (p_dram_partition->loader_addr != (UINT32)_loader_exec_compres_start) { + debug_msg_var("p_dram_partition->loader_addr", p_dram_partition->loader_addr); + debug_msg_var("_loader_exec_compres_start", (UINT32)_loader_exec_compres_start); + bl_displayErrMsg("loader addr is not match."); + } + //when rtos boot from flash, the boot from loader directly, + //but when rtos need to burn image, the uboot is still required. + //so, any one need to burn image, uboot is always needed to boot. + //if ((uiLoaderFunc & FUNC_UPDATE_FW) || p_dram_partition->rtos_addr == 0) { + if (!RUN_UITRON_FW || p_dram_partition->rtos_addr == 0) { + // always use uboot to handle all-in-one bin + if (p_dram_partition->bl31_size == 0 && p_dram_partition->teeos_size == 0) { + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er == -2) { // try to load from nand + debug_msg("uboot from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + } + + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else if (p_dram_partition->teeos_size) { + // load teeos + er = bl_load_teeos_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load teeos failed\r\n"); + } + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr, 1); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } + } + return er; + } else { + // update rtos information + // the following is for uncompressed-rtos only, others needing uboot + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + *pOut_dram_partition = p_dram_partition; + return bl_load_rtos_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, p_fdt, p_comp_addr, p_comp_size); + } +} +#endif + +// return uItron_fw_addr, no need to fully decode +_THUMB2 static unsigned int bl_process_rtos_only(UINT32 uiFwBuf, UINT32 uiFwBufSize, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + UINT32 uItron_fw_addr; + NVTPACK_BFC_HDR *pBFC; + HEADINFO *p_headinfo; + + debug_msg("\r\nbl_process_rtos_only\r\n"); + pBFC = (NVTPACK_BFC_HDR *)uiFwBuf; + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 compressSize; + UINT32 algorithm = invertEndian(pBFC->uiAlgorithm) & 0xFF; + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + switch(algorithm) { + case 9: // LZ77 + LZ_Un_compress((UINT8 *)uiFwBuf + LDC_HEADER_SIZE, p_tmp, SIZE_PRELOAD); + break; +#if (_GZIP_ENABLE_API_ == 1) + case 12: // GZ + GZ_Uncompress((UINT8 *)uiFwBuf + LDC_HEADER_SIZE, p_tmp, SIZE_PRELOAD); + break; +#endif + default: + debug_err_var("unsupported comp", algorithm); + return 0; + } + + p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; +#if UITRON_FW + uItron_fw_addr = p_headinfo->CodeEntry - CODE_ENTRY_OFFSET; // cliff +#endif + + if ((uItron_fw_addr & 0x0000FFFF) != 0) { //cc engine's limitation + debug_err_var("rtos addr must match (&0x0000FFFF)==0", uItron_fw_addr); // but 660 allow + uItron_fw_addr = uItron_fw_addr & 0xFFFF0000; + } + compressSize = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //debug_dump_addr(tmpBuf,0x200); + debug_msg_var("F compress uItron_fw_addr", uItron_fw_addr); + // uiFwBuf has adjusted on bl_load_rtos_from_non_nvtpack() + *p_comp_addr = uiFwBuf; + *p_comp_size = compressSize; + } else { + p_headinfo = (HEADINFO *)(uiFwBuf + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; +#if UITRON_FW + uItron_fw_addr = p_headinfo->CodeEntry - CODE_ENTRY_OFFSET; // cliff +#endif + + if ((uItron_fw_addr & 0x0000FFFF) != 0) { //cc engine's limitation + debug_err_var("rtos addr must match (&0x0000FFFF)==0", uItron_fw_addr); // but 660 allow + uItron_fw_addr = uItron_fw_addr & 0xFFFF0000; + } + + debug_msg_var("Normal uItron_fw_addr", uItron_fw_addr); + *p_comp_addr = 0; + *p_comp_size = 0; + } + return uItron_fw_addr; +} +#if !UPDATE_EMU_CODE && !REMOVED_FLASH +_THUMB2 static unsigned int bl_process_flash_boot(unsigned char *p_tmp, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } +#if (FDT_SUPPORT) + // load fdt + er = bl_load_fdt_from_flash(p_tmp, SDRAM_Start_FW, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } +#endif + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition->teeos_size) { + // load teeos + er = bl_load_teeos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load teeos failed\r\n"); + } +#if (BOOT_LINUX_SUPPORT) + if (linuxboot_setup((unsigned char *)p_dram_partition->fdt_addr) !=0 ) { + bl_displayErrMsg("linuxboot_setup failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr, 0); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } +#else + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr, 1); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } +#endif + } else if (p_dram_partition->rtos_addr == 0 || DUAL_RTOS_SUPPORT) { // modify this condition to be true for booting uboot +#if (BOOT_LINUX_SUPPORT) + if (linuxboot_setup((unsigned char *)p_dram_partition->fdt_addr) !=0 ) { + bl_displayErrMsg("linuxboot_setup failed\r\n"); + } + linuxboot_go(); +#else + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } +#endif + } else { + // load rtos + er = bl_load_rtos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp, 0); + if (er != 0) { + bl_displayErrMsg("load rtos failed\r\n"); + } + } + + // update compressed rtos information + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((unsigned char *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + *p_comp_addr = p_bininfo->comm.Resv[3]; // COMM_UITRON_COMP_ADDR + *p_comp_size = p_bininfo->comm.Resv[4]; // COMM_UITRON_COMP_LEN + + *pOut_dram_partition = p_dram_partition; + return p_dram_partition->rtos_addr; +} +#endif + +/** + bl_process_update_loader. + + Write loader will update loader binary file + + @param[in] loader_addr loader in DRAM starting address + @param[in] loader_size loader code length (from loader header offset 0x24) + @return void +*/ +_THUMB2 static int bl_process_update_loader(unsigned int loader_addr, unsigned int loader_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card +#if (_FPGA_EMULATION_ == 1) + //For FPGA binary without efuse + bl_checkLoader(loader_addr, loader_size); +#else + if (IS_SECURE() == 0) { + bl_checkLoader(loader_addr, loader_size); + } +#endif + + if (int_strg_obj != NULL) { + debug_msg("update loader\r\n"); + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + if (int_strg_obj->flash_writeSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)loader_addr, NAND_RW_LOADER) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = loader_addr + loader_size; + if (int_strg_obj->flash_readSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)reload_addr, NAND_RW_LOADER) < 0) { + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)loader_addr, (void *)reload_addr, loader_size) != 0) { + bl_displayErrMsg("verify fail\r\n"); + } + } else { + debug_msg("skip update loader\r\n"); + return -1; + } + return 0; +} +#if UPDATE_EMU_CODE +_THUMB2 static int bl_process_update_emu_firmware(unsigned int emu_addr, unsigned int emu_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card +// bl_checkFW(emu_addr, emu_size); + debug_msg("update emu firmware size"); + uart_putSystemUARTStr(Dec2HexStr(emu_size)); + uart_putSystemUARTStr("\r\n"); + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // Program firmware + if (int_strg_obj->flash_writeSectors(g_uiStartBlkUpdateFW, emu_size, (UINT8 *)emu_addr, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = emu_addr + emu_size; + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, emu_size, (UINT8 *)reload_addr, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)emu_addr, (void *)reload_addr, emu_size) != 0) { + bl_displayErrMsg("verify fail\r\n"); + } + return 0; +} +#endif + +_THUMB2 void bl_read_rtos_addr(UINT32 *pLoadAddr, UINT32 *pTargetAddr, UINT32 *pSize) +{ + *pLoadAddr = g_rtos_load_addr; + *pTargetAddr = g_rtos_target_addr; + *pSize = g_rtos_size; +} + +#define FOURCC_BOOT 0x544F4F42 +#define FOURCC_LRDY 0x5944524C +#if 0 +_THUMB2 static int bl_process_ep(void) +{ + unsigned char *p_fdt = NULL; + volatile unsigned int *p_comm_reg = (volatile unsigned int *)CC_RC_EP_BOOT_COMM_REG; + // check fourcc BOOT + if (*p_comm_reg != FOURCC_BOOT) { + bl_displayErrMsg("ep boot not from uboot trigger\r\n"); + } + // notify rc-uboot loader ready (fourcc = LRDY) + *p_comm_reg = FOURCC_LRDY; + + // wait RC-uboot send fdt, atf, optee, u-boot here + debug_msg("wait rc send fw\r\n"); + while (*p_comm_reg == FOURCC_LRDY) { + // RC will write fdt address to *p_comm_reg + } + debug_msg("got fw\r\n"); + + // parse fdt + unsigned int fdt_addr = *p_comm_reg; + unsigned int fdt_size = fdt_totalsize(*p_comm_reg); + debug_msg_var("fdt adr", (int)fdt_addr); + debug_msg_var("fdt siz", (int)fdt_size); + if (bl_chk_fdt((unsigned int)fdt_addr, fdt_size) != 0) { + return -1; + } + + if (bl_copy_fdt_to_fdt_addr((void *)fdt_addr, &p_fdt) != 0) { + return -1; + } + + // boot bl31 + DRAM_PARTITION *p_dram_partition = NULL; + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + debug_msg_var("bl31 addr = ", (int)p_dram_partition->fdt_addr); + int er = bl_boot_bl31((unsigned char *)p_dram_partition->fdt_addr, 0); + if (er != 0) { + bl_displayErrMsg("boot bl31 fail\r\n"); + } + + return 0; +} +#endif +/** + main flow code + + If there is Calibration Firmware code store in NAND, running flow as follow + O's work flow + + @return fw base addr +*/ + +#if (CRYPTO_ENGINE_SAMPLE == ENABLE) +// 1. +// Key = 04030201080706051211100916151413 +// result = 5f 47 2c 96 2a 92 29 29 0d 20 4f a8 87 af 63 d8 +// 2. +// iv = 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 +// result = 75 70 e0 a6 bd d3 b2 62 c8 e6 68 68 5f 90 5f 67 +static UINT8 key_sample[16] __attribute__((aligned(4)))= {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16}; +//static UINT8 key_sample[16] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16}; +static UINT32 pRSAKeyCRC32[8]; + +static UINT32 hash_msg[8] = {0xfea52d8c, 0x759c346c, 0x78e4ba3f, 0x59bb9a39, 0x8cc1abc9, 0x9e9d0614, 0x3848160b, 0xd9462e71}; +static UINT32 pub_x[8] = {0x95819a9f, 0xdcd7f425, 0x1123c5d5, 0x27213e17, 0xd2358140, 0x7faddd85, 0x75c11f0b, 0xd2eccfd9}; +static UINT32 pub_y[8] = {0x3581eeb6, 0xbb047e6c, 0xd05ab038, 0xfdbcef70, 0x7515d11e, 0x733b285e, 0xe577a154, 0xe34680e8}; +static UINT32 sign_r[8] = {0x7f9fec0b, 0x876197a0, 0x62efb6c5, 0x076099de, 0xf88f3008, 0x680fa1a5, 0xafbb66c1, 0x28983ff3}; +static UINT32 sign_s[8] = {0x8132b864, 0xfeef53d3, 0xe08b7871, 0x92b1c9df, 0x7907ec8e, 0x54df54dc, 0xc6c84cc6, 0x46529e75}; + +#endif + +_THUMB2 UINT32 bl_mainFlow(void) +{ + UINT32 uiUpdateFileLen = 0; + UINT32 uiLoaderFunc = 0; + UINT32 uiLoaderSize = 32 * 1024; // pre-assume 32KB, actual size is parsed from loader + //Show Duty calibration log +#if (_LOADER_DUTY_CALIBRATION_ == ENABLE && _LOADER_DUTY_CALIBRATION_LOG_ == ENABLE) + UINT32 uiLoaderAddress; + UINT32 uiLogSramAddress; +#endif + +#if !(USB_WRITELOADER || UART_UPDATE) + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; +#endif + UINT32 uiFwBaseAddr = SDRAM_Start_FW; // FW base address + DRAM_PARTITION *p_dram_partition = NULL; + + // BaseOfStack is initialized at doRemapLZ.s + UINT32 uiheapBufferAddr = (UINT32)_loader_heap_base; +// UINT32 uiheapBufferAddr = BaseOfStack + 0x40000; // reserve 16KB for tmp buffer usage + UINT32 uiTmpBufferAddr = uiheapBufferAddr + FAT_HEAP_BUFFER_SIZE; + UINT32 uiUpdateBootloaderBufAddr = uiTmpBufferAddr + 0x4000; + UINT32 uiUpdateMainBinBufAddr = SDRAM_Start_FW; + + perf_mark("flow-b"); + + // UART initial sequence + //uart_openSystemUART(); + // rtc reset shutdown timer + // rtc_resetShutDownTimer(); + +#if 0 + // adjust PAD driving (if required) + bl_adjustDriving(); + /* + - @b RTC_PWR_SW_STS: Power on source is PWR_SW + - @b RTC_PWR_VBAT_STS: Power on source is PWR_VBAT + - @b RTC_PWR_VBUS_STS: Power on source is PWR_VBUS + */ + uiPowerOnSrc = rtc_getPWRONSource(); + + if (uiPowerOnSrc & RTC_PWR_SW_STS) { + uart_putSystemUARTStr("\r\nSW PON\r\n"); + } else if (uiPowerOnSrc & RTC_PWR_VBAT_STS) { + uart_putSystemUARTStr("\r\nVBAT PON\r\n"); + } else if (uiPowerOnSrc & RTC_PWR_VBUS_STS) { + uart_putSystemUARTStr("\r\nVBUS PON\r\n"); + } else if (rtc_getIsAlarmPowerOn()) { + uart_putSystemUARTStr("\r\nPwrAlarm PON\r\n"); + } else { + uart_putSystemUARTStr("\r\nPOR PON\r\n"); + } +#endif + // Display Loader Version + debug_msg((char *)LOADER_START_STR); + UTL_setDrvTmpBufferAddress(uiTmpBufferAddr); + +#if 0 + // Sample to hook spi flash extending function + flash_installIdentifyCB(bl_spiIdentify); +#endif + prj_main(); +#if 0 + if (!IS_RC()) { + bl_process_ep(); + return 0; //never return + } +#endif + +#if (_FPGA_EMULATION_ == 0) +#if !(USB_WRITELOADER) + set_usb_suspend(); +#endif +#endif + +#if defined(ROM_GetCurrBS) +#if (STORAGE_EXT_TYPE == STORAGE_EXT_USB) || (STORAGE_EXT_TYPE == STORAGE_EXT_UART) + if (ROM_GetCurrBS() == BOOT_SOURCE_UART) { + debug_msg("Boot from UART ...\r\n"); +#if UART_UPDATE + bl_uart();//never returned. +#else + bl_displayErrMsg("loader must be STORAGEEXT = Uart\r\n"); +#endif + } + + if ((ROM_GetCurrBS() == BOOT_SOURCE_USB)||(ROM_GetCurrBS() == BOOT_SOURCE_USB_FULL)) { + debug_msg("Boot from USB ...\r\n"); +#if USB_WRITELOADER + bl_usb(); //never returned. +#else + bl_displayErrMsg("loader must be STORAGEEXT = Usb\r\n"); +#endif + } +#endif +#endif + +#if !(USB_WRITELOADER || UART_UPDATE) + if (((gSpecialKeyCallBack == NULL) || gSpecialKeyCallBack()) && + ((gCardDetectCallBack == NULL) || gCardDetectCallBack())) { + if (card_open() == TRUE && fat_initFAT(uiheapBufferAddr, FAT_HEAP_BUFFER_SIZE) == TRUE) { +#if UPDATE_SIM_CODE + BOOL bWDTInit = UTL_canUpdateSecKey(); + if (bWDTInit && fat_open_rootfile(RUN_WRKEY_NAME) == TRUE) { + debug_msg("sim.bin exist\r\n"); // the others A or T are skipped. + // Read byte count specified in file directory entry + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_WRBIN; + } else { // exclude others update if FUNC_RUN_WRBIN is existing. +#elif (CRYPTO_ENGINE_SAMPLE == ENABLE) // Only for test flow + UINT32 index; + UINT32 timeElapse; + UINT32 output = uiUpdateMainBinBufAddr; + CRYPT_OP crypt_op_param; + UINT32 test_result = 0; + debug_msg("ENC test\r\n"); + crypt_op_param.op_mode = CRYPTO_CBC; + crypt_op_param.en_de_crypt = CRYPTO_ENCRYPT; + crypt_op_param.src_addr = (unsigned int)key_sample; + crypt_op_param.dst_addr = (unsigned int)output; + crypt_op_param.length = 16; + crypt_op_param.iv_init_en= 0; + + if(crypto_data_operation(EFUSE_OTP_1ST_KEY_SET_FIELD, crypt_op_param) != 0) { + debug_msg("ENC fail\r\n"); + } else { + debug_msg_var("output", (UINT32)output); + debug_msg_var("", *(UINT32 *)(output+0)); + debug_msg_var("", *(UINT32 *)(output+4)); + debug_msg_var("", *(UINT32 *)(output+8)); + debug_msg_var("", *(UINT32 *)(output+12)); + + debug_msg("OTP key\r\n"); + debug_msg_var("", *(UINT32 *)(CRYPTO_REG_BASE_ADDR+0x10)); + debug_msg_var("", *(UINT32 *)(CRYPTO_REG_BASE_ADDR+0x14)); + debug_msg_var("", *(UINT32 *)(CRYPTO_REG_BASE_ADDR+0x18)); + debug_msg_var("", *(UINT32 *)(CRYPTO_REG_BASE_ADDR+0x1C)); + } + + crypt_op_param.iv_init_en= 1; + bl_memcpy((void *)crypt_op_param.iv, (void *)key_sample, 16); + if(crypto_data_operation(EFUSE_OTP_1ST_KEY_SET_FIELD, crypt_op_param) != 0) { + debug_msg("ENC fail\r\n"); + } else { + debug_msg_var("IV", (UINT32)key_sample); + debug_msg_var("", *(UINT32 *)(key_sample+0)); + debug_msg_var("", *(UINT32 *)(key_sample+4)); + debug_msg_var("", *(UINT32 *)(key_sample+8)); + debug_msg_var("", *(UINT32 *)(key_sample+12)); + + debug_msg_var("IV output", (UINT32)output); + debug_msg_var("", *(UINT32 *)(output+0)); + debug_msg_var("", *(UINT32 *)(output+4)); + debug_msg_var("", *(UINT32 *)(output+8)); + debug_msg_var("", *(UINT32 *)(output+12)); + + debug_msg("OTP key\r\n"); + debug_msg_var("", *(UINT32 *)(CRYPTO_REG_BASE_ADDR+0x10)); + debug_msg_var("", *(UINT32 *)(CRYPTO_REG_BASE_ADDR+0x14)); + debug_msg_var("", *(UINT32 *)(CRYPTO_REG_BASE_ADDR+0x18)); + debug_msg_var("", *(UINT32 *)(CRYPTO_REG_BASE_ADDR+0x1C)); + } + + bl_memcpy((void *)uiUpdateMainBinBufAddr, (void *)_load_BOOT_EXEC_start_base, 32768); + + timeElapse = timer_getLdrElapse(); + shahw((const unsigned char *)uiUpdateMainBinBufAddr, 32768, pRSAKeyCRC32); + timeElapse = timer_getLdrElapse() - timeElapse; + debug_msg_var("HASH PIO 32K", timeElapse); + for(index = 0; index < 8; index ++) { + debug_msg_var("", pRSAKeyCRC32[index]); + } + + timeElapse = timer_getLdrElapse(); + shahw_dma((const unsigned char *)uiUpdateMainBinBufAddr, 32768, pRSAKeyCRC32); + timeElapse = timer_getLdrElapse() - timeElapse; + debug_msg_var("HASH DMA 32K", timeElapse); + for(index = 0; index < 8; index ++) { + debug_msg_var("", pRSAKeyCRC32[index]); + } + + /*ECDSA sample*/ + test_result = ecdsa_verify(hash_msg, pub_x, pub_y, sign_r, sign_s); + if(test_result) + debug_msg("ecdsa pass\r\n"); + else + debug_msg("ecdsa fail\r\n"); + + + //if(fat_open_rootfile(UPDATE_BURN_IMG_NAME) == TRUE) { + // uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + // bl_process_update_sim_burn_loader(uiUpdateMainBinBufAddr, uiUpdateFileLen); + // fat_close_rootfile(); + while(1){}; + //} +#endif + // Update loader or not, loader is fixed to 16 KB + if (fat_open_rootfile(UPDATE_LOADER_NAME) == TRUE) { + // Read byte count specified in file directory entry + fat_read_rootfile((UINT8 *)uiUpdateBootloaderBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_UPDATE_LOADER; + uiLoaderSize = *((UINT32 *)(uiUpdateBootloaderBufAddr + 0x24)); + } + // "Update FW" or "Run FW" function + // Update FW has higher priority + if (fat_open_rootfile(UPDATE_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + } else { + // only rtos + debug_msg("not all-in-one, force behavior as T bin.\r\n"); + adjusted_addr = 0; + adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) == 0) { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } else { + bl_displayErrMsg("invalid firmware"); + } +#if UPDATE_EMU_CODE + uiLoaderFunc |= FUNC_UPDATE_FW; +#else + uiLoaderFunc |= FUNC_RUN_CARD; +#endif + + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + } + // Run FW has lower priority + else if (fat_open_rootfile(RUN_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + } else { + // Read rtos + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) != 0) { + bl_displayErrMsg("invalid firmware"); + } else { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } + uiLoaderFunc |= FUNC_RUN_CARD; + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_CARD; + } +#if UPDATE_SIM_CODE + } +#endif + card_close(); + } else { + uiLoaderFunc |= FUNC_RUN_FLASH; + debug_msg("card open fail\r\n"); +// while (1); + } + } else if (((gSpecialKeyCallBack == NULL) || gSpecialKeyCallBack()) && + ((gCardDetectCallBack != NULL) || (gCardDetectCallBack() == FALSE))) { + uiLoaderFunc |= FUNC_RUN_FLASH; + debug_msg("No card inserted\r\n"); + } +#endif + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + bl_process_update_loader(uiUpdateBootloaderBufAddr, uiLoaderSize); + } + + // Run FW + UINT32 comp_addr = 0; + UINT32 comp_size = 0; + if (uiLoaderFunc & (FUNC_RUN_CARD | FUNC_UPDATE_FW)) { + debug_msg("RC\r\n"); + NVTPACK_MEM mem_in ; + int chk_valid_all_in_one; +#if (DRAM_RANGE_SCAN_EN == ENABLE) + // First word is code entry point address, once if entry address is 0xC000XXXX + // represent code is running on sram. + debug_msg("Check SRAM fw\r\n"); + if (bl_checkDramScanFW(uiUpdateMainBinBufAddr) == TRUE) { + + debug_msg("This fw is on SRAM\r\n"); + // Enable sram usage + SETREG32(0xF0900128, 0x00000002); + SETREG32(0xF0800128, 0x00000006); + SETREG32(0xF0020060, 0x00030002); + + debug_msg(Dec2HexStr(*((UINT32 *)SRAM_Start_FW))); + debug_msg("before jump\r\n"); +// while (b_debug_go == FALSE); + load_dram_scan(uiUpdateMainBinBufAddr, uiUpdateFileLen); + return *((UINT32 *)SRAM_Start_FW); + } +#endif + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + chk_valid_all_in_one = bl_chk_valid_all_in_one(&mem_in); + if (chk_valid_all_in_one == 0) { + // all-in-one flow + // File len got from fat_read_rootfile() may exceed actual file size. + // In such condition, we should use info in NVTPACK_FW_HDR2 + if (((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize < uiUpdateFileLen) { + uiUpdateFileLen = ((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize; + mem_in.len = uiUpdateFileLen; + } +#if (REMOVED_FLASH == ENABLE) + bl_displayErrMsg("cannot process all-in-one fw"); +#else + uiFwBaseAddr = bl_process_all_in_one(uiUpdateMainBinBufAddr, uiUpdateFileLen, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); +#endif + } else { + // non-all-in-one flow + // check valid + if (uiLoaderFunc & FUNC_UPDATE_FW) { +#if UPDATE_EMU_CODE + bl_process_update_emu_firmware(uiUpdateMainBinBufAddr, uiUpdateFileLen); +#else + bl_displayErrMsg("cannot write non-all-in-one fw"); +#endif + } + uiFwBaseAddr = bl_process_rtos_only(uiUpdateMainBinBufAddr, mem_in.len, uiLoaderFunc, &comp_addr, &comp_size); + } + + // here uiFwBaseAddr is ready to use. + if (comp_addr == 0) { + HEADINFO *p_headinfo = (HEADINFO *)(uiFwBaseAddr + BIN_INFO_OFFSET_RTOS); + debug_msg("Nrml\r\n"); + if (chk_valid_all_in_one == 0) { + uiUpdateFileLen = p_headinfo->BinLength; + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + // uiUpdateFileLen is already set when file is loaded + } + } else { + debug_msg("Fcompress\r\n"); + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + debug_msg_var("uiUpdateFileLen", uiUpdateFileLen); + //boot from flash or update fw is no need to check sanity because of ecc, turn on it just for debug + if (uiLoaderFunc & FUNC_RUN_CARD) { + bl_checkFW(uiUpdateMainBinBufAddr, uiUpdateFileLen); + } + if (chk_valid_all_in_one == 0) { + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); + } else { + debug_msg_var("fw load addr", uiUpdateMainBinBufAddr); + bl_update_uItron_headInfo(uiUpdateMainBinBufAddr, p_dram_partition); + } + } else { //boot from flash +#if (REMOVED_FLASH == DISABLE) +#if UPDATE_EMU_CODE +// UINT32 uiNandBlkSize; + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + debug_msg("RFlash\r\n"); + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, g_uiNandBlkSize, (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiUpdateFileLen = *(volatile UINT32 *)(SDRAM_Start_FW + 0x168); + + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW + 1, uiUpdateFileLen - g_uiNandBlkSize, (UINT8 *)(SDRAM_Start_FW + g_uiNandBlkSize), NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiFwBaseAddr = bl_process_rtos_only(SDRAM_Start_FW, uiUpdateFileLen, uiLoaderFunc, &comp_addr, &comp_size); + bl_checkFW(SDRAM_Start_FW, uiUpdateFileLen); + uiUpdateMainBinBufAddr = SDRAM_Start_FW; + if (comp_addr == 0) { + debug_msg("Nrml\r\n"); + } else { + debug_msg("Fcompress not support\r\n"); + } + +#else + if (int_strg_obj != NULL) { + uiFwBaseAddr = bl_process_flash_boot((UINT8 *)SDRAM_Start_FW, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); + if (comp_addr == 0) { + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + // no need to bl_checkFW, because check sanity in flash_read + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); + } else { + debug_msg("skip boot from flash.\r\n"); + } +#endif +#endif + } + + if (p_dram_partition) { + bl_update_loader_bininfo((unsigned char *)p_dram_partition->fdt_addr, uiLoaderFunc, uiUpdateFileLen); + if (bl_is_smp((unsigned char *)p_dram_partition->fdt_addr)) { + debug_msg("amp(rtos)\r\n"); + bl_entry_boot((unsigned char *)p_dram_partition->fdt_addr, uiFwBaseAddr, CORE_ID_1); + } + } + +#if UPDATE_EMU_CODE + debug_msg_var("emu fw len", uiUpdateFileLen); +#endif + g_rtos_load_addr = uiUpdateMainBinBufAddr; + g_rtos_target_addr = uiFwBaseAddr; + g_rtos_size = uiUpdateFileLen; + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + debug_msg_var("rtos start", uiFwBaseAddr); + return uiFwBaseAddr; + +} + +_THUMB2 void loader_setUpdateFwName(char *fileName) +{ + strncpy((char *)UPDATE_FW_NAME, fileName, sizeof(UPDATE_FW_NAME)); +} + +_THUMB2 void loader_setUpdateLdrName(char *fileName) +{ + strncpy((char *)UPDATE_LOADER_NAME, fileName, sizeof(UPDATE_LOADER_NAME)); +} + +_THUMB2 void loader_setRunFwName(char *fileName) +{ + strncpy((char *)RUN_FW_NAME, fileName, sizeof(RUN_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryFwName(char *fileName) +{ + strncpy((char *)RECOVERY_FW_NAME, fileName, sizeof(RECOVERY_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryPartitionID(UINT32 partition_id) +{ + g_uiPartitionID = partition_id; +} + +_THUMB2 void loader_setVersion(UINT32 version) +{ + g_uiVersion = version; +} + +_THUMB2 void loader_installSpecialKeyCB(LDR_SPECIAL_KEY_CB callback) +{ + gSpecialKeyCallBack = callback; +} + +_THUMB2 void loader_installCardDetectCB(LDR_CARD_DETECT_CB callback) +{ + gCardDetectCallBack = callback; +} + +_THUMB2 void loader_installRecoveryTriggerCB(LDR_RECOVERY_TRIGGER_CB callback) +{ + gRecoveryTriggerCallBack = callback; +} + +_THUMB2 void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj) +{ + gStorageIntType = type; + int_strg_obj = strg_obj; +} diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h new file mode 100755 index 000000000000..4e1e7988a2bb --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h @@ -0,0 +1,299 @@ +/** + @file bl_func.h + @brief Header file for main function + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ +#ifndef _BL_MAIN_H +#define _BL_MAIN_H + +#include "main.h" +#include "IOReg.h" +#include "GPIO.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "loader.h" +//------------------------------------------------------------------------------ +// Compiler option +// +// These compiler option are define in MakeConfig.txt +//!!!!!!!!!!!!!!!!!!! DO NOT MODIFY COMPILER OPTION HERE !!!!!!!!!!!!!!!!!!!! +//------------------------------------------------------------------------------ +#ifndef SECURE_DECRYPT_UBOOT +#define SECURE_DECRYPT_UBOOT 0 //Decrypt uboot sample code +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt + +#ifndef SECURE_DECRYPT_OPTEE_OS +#define SECURE_DECRYPT_OPTEE_OS 0 //Decrypt optee_os sample code +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt + +#ifndef SECURE_DECRYPT_BL31 +#define SECURE_DECRYPT_BL31 0 //Decrypt bl31 sample code +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt + +#ifndef SECURE_SIGNATURE_BY_AES +#define SECURE_SIGNATURE_BY_AES 0 //using aes to decrypt signature +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt + + +#if (SECURE_DECRYPT_UBOOT || SECURE_DECRYPT_OPTEE_OS || SECURE_DECRYPT_BL31) +#define SECURE_OFFSET 1024 //Decrypt uboot from which offset +#endif + +#if (_FPGA_EMULATION_ == 1) +#define IS_SECURE() (SECURE_DECRYPT_UBOOT || SECURE_DECRYPT_OPTEE_OS || SECURE_DECRYPT_BL31) +#define PCIE_SUPPORT DISABLE +#define AT80C51_SUPPORT DISABLE +#else +#define IS_SECURE() is_secure_enable() +#define PCIE_SUPPORT DISABLE +#define AT80C51_SUPPORT ENABLE +#endif + +#if (PCIE_SUPPORT) +#define IS_RC() utl_is_boot_as_rc() +#else +#define IS_RC() (1) +#endif + +#if (AT80C51_SUPPORT) +#define IS_AT80C51_OPENED() at80c51_is_opened() +#else +#define IS_AT80C51_OPENED() (0) +#endif + +// Define LED_FUNCTION == ENABLE will enable LED on/off in boot loader +#define LED_FUNCTION ENABLE//DISABLE + +// FW checking method, support checksum & CRC now +//#define FW_CHECK_NOCHECK 0 +//#define FW_CHECK_CHECKSUM 1 +//#define FW_CHECK_CRC 2 +#ifndef FW_CHECK_METHOD +#define FW_CHECK_METHOD FW_CHECK_CHECKSUM +#endif + +///#define FW_CHECK_INSTRUCTION0 0xE59FF018 + +// Optional pseudo string for checksum & CRC checking +#define FW_CHECK_PSEUDO_STR_EN DISABLE +#if (FW_CHECK_PSEUDO_STR_EN == ENABLE) +// Must sync to MakeConfig.txt +#define FW_CHECK_PSEUDO_STR "DSC_FW" +#endif + +// Determine if need to support compressable main code +#ifndef _MAINCODE_COMPRESS_ +#define _MAINCODE_COMPRESS_ 0 +#endif + +#ifndef STORAGEINT_SPI +#define STORAGEINT_SPI 0 +#endif + +#define FW_EXCEED_16MB_TEST DISABLE + +//------------------------------------------------------------------------------ +// Global definition +//------------------------------------------------------------------------------ +#define LOADER_CODE_SIZE 0x8000 // Reserve 32 KB + +#define RESERVED_DATA_SIZE 0x4000 // Fixed to 16 KB + +//Once if optee exist need modify to 0x02800000 +#define SDRAM_Start_FW 0x02800000 // DRAM uITRON starting address +//#define SDRAM_Start_FW 0x02000000 +//#endif + +#define SRAM_Start_FW 0xF07c0000 // SRAM FW starting address + +#define SRAM_TAG 0xF0000000 // SRAM tag + +#define CORE2_JUMP_ADDR 0x00000000 // Core2 entry code should put on 0, because when core2 reset is released, core2 will jump to 0 and run + +#define CPU_TIMER_FREQ 3000000 // 3MHz + +// Loader checking +#define LOADER_TAG_OFFSET 0x30 +#define LOADER_TAG_VALUE 0xAA55 +#define BOOTVER_SET(OutMaj,OutMin,InnMaj,InnMin) (((OutMaj)<<24)|((OutMin)<<16)|((InnMaj)<<8)|((InnMin))) + +#define BOOTVER_GETOuterMajor(Ver) (((Ver)&0xFF000000)>>24) +#define BOOTVER_GETOuterMinor(Ver) (((Ver)&0x00FF0000)>>16) +#define BOOTVER_GETInnerMajor(Ver) (((Ver)&0x0000FF00)>>8) +#define BOOTVER_GETInnerMinor(Ver) (((Ver)&0x000000FF)) + +// Define loader version (_LDR_VER_) in MakeConfig.txt +#define BOOTLOADER_OUTERMAJOR (((_LDR_VER_)&0xFF000000)>>24) +#define BOOTLOADER_OUTERMINOR (((_LDR_VER_)&0x00FF0000)>>16) +#define BOOTLOADER_INNERMAJOR (((_LDR_VER_)&0x0000FF00)>>8) +#define BOOTLOADER_INNERMINOR (((_LDR_VER_)&0x000000FF)) + +// spi-nand, spi-nor DTR tunning pattern +#define DTR_TUNNING_PATTERN_DATA1 0x0F0F0F0F //4bit +#define DTR_TUNNING_PATTERN_DATA2 0x00FF00FF //8bit +#define DTR_TUNNING_PATTERN_SIZE 0x1000 + +// Operation of boot loader +#define FUNC_UPDATE_FW 0x01 // Read FW code from card and update to NAND and run +#define FUNC_UPDATE_LOADER 0x02 // Read boot loader code from card and update to NAND +#define FUNC_RUN_CARD 0x04 // Read FW code from card and run +#define FUNC_RUN_FLASH 0x08 // Read FW code from internal flash and run +#define FUNC_UPDATE_CAL 0X10 // Update CAL data +#define FUNC_RUN_WRBIN 0X20 // RUN wrkey data +#define FUNC_RUN_UBOOT 0X40 // Read Uboot from card and run +#define FUNC_UPDATE_FW_DONE 0x0100 // update f/w to NAND/SPI done + +// API to turn on / off LED +#if (LED_FUNCTION == ENABLE) +// Red LED (DGPIO 6) +// Green LED (DGPIO 9) +#define TurnOff_RedLED() OUTREG32(CPE_GPIO_BASE + 0x4C, 0x00000040) +#define TurnOn_RedLED() OUTREG32(CPE_GPIO_BASE + 0x38, 0x00000040) +#define TurnOff_GreenLED() OUTREG32(CPE_GPIO_BASE + 0x4C, 0x00000200) +#define TurnOn_GreenLED() OUTREG32(CPE_GPIO_BASE + 0x38, 0x00000200) +#else +#define TurnOff_RedLED() +#define TurnOn_RedLED() +#define TurnOff_GreenLED() +#define TurnOn_GreenLED() +#endif + +//Configure build as USB write loader @ ModelConfig_EMU_EVB.txt +//UART & USB can enable at the same time. +#if (STORAGE_EXT_TYPE == STORAGE_EXT_USB) || (STORAGE_EXT_TYPE == STORAGE_EXT_UART) +#define USB_WRITELOADER ENABLE +#define UART_UPDATE ENABLE +#else +#define USB_WRITELOADER DISABLE +#define UART_UPDATE DISABLE +#endif +#define UART_UPDATE_ DISABLE +#define UPDATE_EMU_CODE DISABLE +#define REMOVED_FLASH DISABLE +#define UPDATE_SIM_CODE DISABLE +#define UITRON_FW DISABLE +#define CRYPTO_ENGINE_SAMPLE DISABLE +#define RUN_UITRON_FW DISABLE // for FPGA, boot rtos bypass u-boot +#define FDT_SUPPORT ENABLE +#define DUAL_RTOS_SUPPORT DISABLE // only for rtos-uvc project (no longer support) +#define MULTI_CODE_FLOW ENABLE +//#define _FLASH_FREQ_MHZ_ 120 // uncomment it to set flash frequency +#define DUMP_FLOW_TIMESTAMP DISABLE // shows flow timestamp for debugging fastboot + +#define NVT_CC_CORE2_START CC_CPU2_CPU1_CMDBUF_REG2 +#define CC_CPU1_WARM_RESET_REG2 CC_CORE2_WARM_RST_REG //Core1 warm reset entry +#define AARCH64_MODE DISABLE + +#define DDR_SCAN_REDUCE_CODE DISABLE + +#define EMUKIT 0 +#define DEMOKIT 0x1800000 +#define RESUME_ADDR DEMOKIT + +//#NT#2018/03/07#Ben Wang -begin +//#NT#Support EMMC boot flow +#define EMMC_BLOCK_SIZE 0x200 +//#NT#2018/03/07#Ben Wang -end + +/** + * @brief FdtFast Flash Offset + */ +#if defined(_STORAGEINT_NandSpi_) \ + || defined(_STORAGEINT_NandEccBCH_) \ + || defined(_STORAGEINT_EMMC_) \ + || defined(_STORAGEINT_EMMC_NAND_COMBO_) +#define FDT_OFFSET 0x40000 +#define FDTFAST_OFFSET 0x80000 +#elif defined(_STORAGEINT_SpiFlash_) +#define FDT_OFFSET 0x10000 +#define FDTFAST_OFFSET 0x50000 +#elif defined(_STORAGEINT_NONE_) +#define FDT_OFFSET 0x40000 +#define FDTFAST_OFFSET 0x80000 +#endif + + +#if defined(_DIRECT_BOOT_) +#define BOOT_LINUX_SUPPORT ENABLE +#else +#define BOOT_LINUX_SUPPORT DISABLE +#endif + +#if defined(_FASTBOOT_) +#define FDTFAST_SENSOR ENABLE +#else +#define FDTFAST_SENSOR DISABLE +#endif + +#if (BOOT_LINUX_SUPPORT) && (!FDT_SUPPORT) +/** + * because boot linux need fdt to pass chosen, + * ramdisk and other parameters to kernel, + */ +#error "BOOT_LINUX_SUPPORT need FDT_SUPPORT" +#endif + +/** + * if nvt-fastboot.bin is too large (> 128KB), + * nvt-fastboot.bin cannot be loaded to SRAM + * for this case, nvt-fastboot.bin only can be loaded to DRAM + * it will cause fastboot speed has a little down. + */ +#define FDTFAST_FROM_DRAM ENABLE + +#define StartNandBlkUpdateLoader 0 + +/** + @name Assert macros +*/ +//@{ +#define ASSERT_CONCAT_(a, b) a##b +#define ASSERT_CONCAT(a, b) ASSERT_CONCAT_(a, b) + +#if defined(__COUNTER__) + +#define STATIC_ASSERT(expr) \ + enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __COUNTER__) = 1/(expr) } + +#else + +// This might cause compile error when writing STATIC_ASSERT at the same line +// in two (or more) files and one file include another one. +#define STATIC_ASSERT(expr) \ + enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __LINE__) = 1/(expr) } + +#endif +//@} + +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[]; + +extern UINT32 LoaderInternalInfo[]; + +extern PSTORAGE_OBJ int_strg_obj; + +//------------------------------------------------------------------------------ +// internal functions +//------------------------------------------------------------------------------ +extern int bl_chk_valid_all_in_one(NVTPACK_MEM *p_mem_all_in_one); +extern int bl_chk_uboot(unsigned int addr, unsigned int size); +extern unsigned int bl_process_all_in_one(UINT32 uiFwBuf, UINT32 uiFwBufSize, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size); +extern int bl_boot_uboot(unsigned char *p_fdt); +extern int bl_chk_fdt(unsigned int addr, unsigned int size); +extern int bl_copy_fdt_to_fdt_addr(unsigned char *p_fdt /*IN*/, unsigned char **pp_fdt /*OUT*/); +extern int bl_flash_open(void); +// Exported functions +//------------------------------------------------------------------------------ +extern UINT32 bl_mainFlow(void); +extern UINT32 BaseOfStack; + +// project(customer) main function +extern void prj_main(void); +extern void bl_read_rtos_addr(UINT32 *pLoadAddr, UINT32 *pTargetAddr, UINT32 *pSize); +extern void *bl_get_kernel_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/); +extern void *bl_get_rootfs_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/); + +// decrypt +int do_decrypt_aes(unsigned int input_data, unsigned int output_data, unsigned int *output_size, unsigned int partition_size); + +#endif diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_linux.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_linux.c new file mode 100755 index 000000000000..e40f5088bb05 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_linux.c @@ -0,0 +1,908 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bl_func.h" +#include "bl_lowlevel_init.h" +#include "bl_linux.h" +#include "arch_timer.h" +#include "modelext_parser.h" +#include "bin_info.h" +#include "shm_info.h" + + + +#if (BOOT_LINUX_SUPPORT) + +#define CFG_INDEP_RAMDISK ENABLE +#if defined(__aarch64__) +#define CFG_LINUX_START_OFFSET 0x200000 /* MIN_KIMG_ALIGN SZ_2M */ +#else +#define CFG_LINUX_START_OFFSET 0x8000 +#endif +#define CFG_MULTI_MKIMAGE_LEN 0x8 //mkimage's multi image always comes 8 bytes for sub-image size +#define CFG_BOOTARG_MAX_LEN 0x1000 +#define CFG_LINUX_MAX_CODE_SIZE 0x01000000 /* for 64MB dram, assume linux (ro+rw+bss) limited on this size */ +#define CFG_LINUX_COMP_MAX_SIZE 0xA00000 /* max uImage size */ +#define CFG_RAMFS_COMP_MAX_SIZE 0x500000 /* max ramdisk size */ +#define CFG_GZ_WORK_SIZE 0x10000 /* 64KB are enough */ +#define CFG_CORE2_ENTRY_REG 0xF07F8000 +#ifndef CONFIG_SYS_FDT_PAD +#define CONFIG_SYS_FDT_PAD 0x3000 /* from uboot */ +#endif + +#define MEM_PATH_LINUX "/memory" +#define MEM_PATH_LINUXTMP "/nvt_memory_cfg/linuxtmp" +#define MEM_PATH_FDT "/nvt_memory_cfg/fdt" +#define MEM_PATH_ATF "/nvt_memory_cfg/atf" + +#define IS_BIN_OVERLAP(addr1, size1, addr2, size2) (!(((addr1 + size1 - 1) < addr2) || (addr1 > (addr2 + size2 - 1)))) + +#define _THUMB2 __attribute__((target("thumb"))) + +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#define ALIGN_CEIL_64(a) ALIGN_CEIL(a, 64) ///< Round Up to 64 + +#define DBG_ERR printf + +// sync from uboot +#if defined(__aarch64__) +#define CONFIG_BOOTARGS_COMMON "rootwait console=ttyS0,115200 debug_boot_weak_hash print-fatal-signals=1 " +#else +#define CONFIG_BOOTARGS_COMMON "rootwait nprofile_irq_duration=on " +#endif + +#define CONFIG_BOOTARGS_RAMDISK CONFIG_BOOTARGS_COMMON "root=/dev/ram0 rootfstype=ramfs rdinit=/linuxrc " +#if defined(_STORAGEINT_NandSpi_) +#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "root=ubi0:rootfs rootfstype=ubifs ubi.fm_autoconvert=1 init=/linuxrc " +#elif defined(_STORAGEINT_SpiFlash_) +#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "rootfstype=squashfs ro " +#elif defined(_STORAGEINT_EMMC_) +#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "rootfstype=ext4 rw " +#else //SD +#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "root=/dev/mmcblk0p2 noinitrd rootfstype=ext3 init=/linuxrc " +#endif /* _NVT_ROOTFS_TYPE_ */ + +/* + * Legacy format image header, + * all data in network byte order (aka natural aka bigendian). + */ +#define IH_MAGIC 0x27051956 /* Image Magic Number */ +#define IH_NMLEN 32 /* Image Name Length */ +typedef struct image_header { + unsigned int ih_magic; /* Image Header Magic Number */ + unsigned int ih_hcrc; /* Image Header CRC Checksum */ + unsigned int ih_time; /* Image Creation Timestamp */ + unsigned int ih_size; /* Image Data Size */ + unsigned int ih_load; /* Data Load Address */ + unsigned int ih_ep; /* Entry Point Address */ + unsigned int ih_dcrc; /* Image Data CRC Checksum */ + unsigned char ih_os; /* Operating System */ + unsigned char ih_arch; /* CPU architecture */ + unsigned char ih_type; /* Image Type */ + unsigned char ih_comp; /* Compression Type */ + unsigned char ih_name[IH_NMLEN]; /* Image Name */ +} image_header_t; + +typedef struct _LINUX_RESERVED_MEM { + char name[32]; + uintptr_t addr; + unsigned long size; +} LINUX_RESERVED_MEM; + +/** + *linuxtmp address must in range of linux memory + */ +typedef struct _FDT_INFO { + unsigned long linux_addr; + unsigned long linux_size; + unsigned long linuxtmp_addr; + unsigned long linuxtmp_size; + unsigned long fdt_addr; + unsigned long fdt_size; + unsigned long reserved_cnt; + LINUX_RESERVED_MEM reserved[8]; +} FDT_INFO; + +typedef struct _LINUXTMP_PARTITION { + unsigned long tmp_begin; + unsigned long tmp_curr; + unsigned long tmp_end; + unsigned long fdt_addr; + unsigned long fdt_size; + unsigned long ramfs_addr; + unsigned long ramfs_size; + unsigned long bootargs_addr; + unsigned long bootargs_size; + unsigned long lz_linux_addr; + unsigned long lz_linux_size; +} LINUXTMP_PARTITION; + +typedef struct _LINUXBOOT_INFO { + FDT_INFO fdt_info; + LINUXTMP_PARTITION linuxtmp; +} LINUXBOOT_INFO; + +static void *m_fdt = NULL; +static unsigned int m_timer_interval = 0; +static LINUXBOOT_INFO info = {0}; + +_THUMB2 static void *fdt_get_base(void) +{ + return m_fdt; +} + +_THUMB2 static int fdt_read_mem_node(const char *path, unsigned long *p_addr, unsigned long *p_size) +{ + unsigned char *p_fdt = (unsigned char *)fdt_get_base(); + + int len; + int nodeoffset; + const void *nodep; /* property node pointer */ + + // get linux space + nodeoffset = fdt_path_offset(p_fdt, path); + if (nodeoffset < 0) { + DBG_ERR("failed to offset for %s = %d \n", path, nodeoffset); + return -1; + } + +#if defined(__aarch64__) + if (strncmp(path, "/nvt_memory_cfg/", strlen("/nvt_memory_cfg/")) == 0) { + nodep = fdt_getprop(p_fdt, nodeoffset, "reg", &len); + if (len == 0 || nodep == NULL) { + DBG_ERR("failed to access reg.\n"); + return -1; + } else { + unsigned int *p_data = (unsigned int *)nodep; + *p_addr = be32_to_cpu(p_data[0]); + *p_size = be32_to_cpu(p_data[1]); + } + } else if (strncmp(path, "/memory", strlen("/memory")) == 0) { + nodep = fdt_getprop(p_fdt, nodeoffset, "reg", &len); + if (len == 0 || nodep == NULL) { + DBG_ERR("failed to access reg.\n"); + return -1; + } else { + unsigned long *p_data = (unsigned long *)nodep; + *p_addr = be64_to_cpu(p_data[0]); + *p_size = be64_to_cpu(p_data[1]); + } + } else if (strncmp(path, "/hdal-memory/", strlen("/hdal-memory/")) == 0) { + nodep = fdt_getprop(p_fdt, nodeoffset, "reg", &len); + if (len == 0 || nodep == NULL) { + DBG_ERR("failed to access reg.\n"); + return -1; + } else { + unsigned long *p_data = (unsigned long *)nodep; + *p_addr = be64_to_cpu(p_data[2]); + *p_size = be64_to_cpu(p_data[3]); + } + } else { + DBG_ERR("failed to parse %s\n", path); + return -1; + } +#else + if (strncmp(path, "/cpus/", strlen("/cpus/")) == 0) { + nodep = fdt_getprop(p_fdt, nodeoffset, "cpu-release-addr", &len); + if (len == 0 || nodep == NULL) { + DBG_ERR("failed to access cpu-release-addr.\n"); + return -1; + } else { + unsigned long *p_data = (unsigned long *)nodep; + *p_addr = be32_to_cpu(p_data[0]); + } + } else if (strncmp(path, "/hdal-memory/", strlen("/hdal-memory/")) == 0) { + nodep = fdt_getprop(p_fdt, nodeoffset, "reg", &len); + if (len == 0 || nodep == NULL) { + DBG_ERR("failed to access reg.\n"); + return -1; + } else { + unsigned long *p_data = (unsigned long *)nodep; + int addr_cells = fdt_address_cells(p_fdt, nodeoffset); + if (addr_cells == 2) { + //new, chip_id addr size + *p_addr = be64_to_cpu(p_data[1]); + *p_size = be64_to_cpu(p_data[2]); + } else { + //new, chip_id addr size + *p_addr = be64_to_cpu(p_data[0]); + *p_size = be64_to_cpu(p_data[1]); + } + } + } else { + nodep = fdt_getprop(p_fdt, nodeoffset, "reg", &len); + if (len == 0 || nodep == NULL) { + DBG_ERR("failed to access reg.\n"); + return -1; + } else { + unsigned int *p_data = (unsigned int *)nodep; + *p_addr = be32_to_cpu(p_data[0]); + *p_size = be32_to_cpu(p_data[1]); + } + } +#endif + return 0; +} + + +_THUMB2 static int fdt_read_reserved_mem_node(FDT_INFO *p_info) +{ + unsigned char *p_fdt = (unsigned char *)fdt_get_base(); + + int len; + int nodeoffset; + const char path[] = "/reserved-memory"; + nodeoffset = fdt_path_offset(p_fdt, path); + if (nodeoffset < 0) { + DBG_ERR("failed to offset for %s = %d \n", path, nodeoffset); + return -1; + } + + int child; + fdt_for_each_subnode(child, p_fdt, nodeoffset) { + LINUX_RESERVED_MEM *p = (LINUX_RESERVED_MEM *)&p_info->reserved[p_info->reserved_cnt]; + strncpy(p->name, fdt_get_name(p_fdt, child, &len), sizeof(p->name) - 1); + unsigned long *p_data = (unsigned long *)fdt_getprop(p_fdt, child, "reg", &len); + if (p_data) { +#if defined(__aarch64__) + p->addr = be64_to_cpu(p_data[0]); + p->size = be64_to_cpu(p_data[1]); +#else + p->addr = be32_to_cpu(p_data[0]); + p->size = be32_to_cpu(p_data[1]); +#endif + p_info->reserved_cnt++; + if (p_info->reserved_cnt > sizeof(p_info->reserved) / sizeof(p_info->reserved[0])) { + DBG_ERR("linux_reserved_mem_cnt too large: %ld\n", p_info->reserved_cnt); + return -1; + } + } + + } + return 0; +} + + +_THUMB2 static int fdt_get_info(FDT_INFO *p_info) +{ + int er; + if ((er = fdt_read_mem_node(MEM_PATH_LINUX, &p_info->linux_addr, &p_info->linux_size)) != 0) { + return er; + } + if ((er = fdt_read_mem_node(MEM_PATH_LINUXTMP, &p_info->linuxtmp_addr, &p_info->linuxtmp_size)) != 0) { + return er; + } + if ((er = fdt_read_mem_node(MEM_PATH_FDT, &p_info->fdt_addr, &p_info->fdt_size)) != 0) { + return er; + } +#if defined(__aarch64__) + if ((er = fdt_read_mem_node(MEM_PATH_ATF, &p_info->atf_addr, &p_info->atf_size)) != 0) { + return er; + } +#endif + if ((er = fdt_read_reserved_mem_node(p_info)) != 0) { + DBG_ERR("no reversed node\r\n"); + } + return 0; +} + +_THUMB2 static int create_new_fdt(LINUXTMP_PARTITION *p_linuxtmp) +{ + unsigned char *p_fdt = (unsigned char *)fdt_get_base(); + + int new_size = ALIGN_CEIL(fdt_totalsize(p_fdt) + CONFIG_SYS_FDT_PAD, 0x1000); + + p_linuxtmp->fdt_addr = p_linuxtmp->tmp_curr; + p_linuxtmp->fdt_size = new_size; + p_linuxtmp->tmp_curr += new_size; + + if (p_linuxtmp->tmp_curr >= p_linuxtmp->tmp_end) { + DBG_ERR("linuxtmp memory is too small, need more %d\n", p_linuxtmp->tmp_curr - p_linuxtmp->tmp_end); + return -1; + } + + int err = fdt_open_into(p_fdt, (void *)p_linuxtmp->fdt_addr, new_size); + if (err != 0) { + DBG_ERR("fdt move failed!"); + return -1; + } + + return 0; +} + + +#if (CFG_INDEP_RAMDISK) +_THUMB2 static int load_ramdisk(LINUXTMP_PARTITION *p_linuxtmp) +{ + int er = 0; + int rootfs_partition_id = -1; + unsigned long bfc_data = p_linuxtmp->tmp_curr; + + int blk_size = (int)int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_rootfs = bl_get_rootfs_partition(fdt_get_base(), &rootfs_partition_id); + + //load 1st block + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rootfs->PartitionOffset / blk_size, blk_size, (UINT8 *)bfc_data, NAND_RW_FIRMWARE)) < 0) { + DBG_ERR("NG ramdisk-1\r\n"); + return -1; + } + + NVTPACK_BFC_HDR *p_hdr = (NVTPACK_BFC_HDR *)bfc_data; + + if (p_hdr->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { +#if (_GZIP_ENABLE_API_ == 1) + //bfc compressed ramdisk + unsigned int bfc_size = be32_to_cpu(p_hdr->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + unsigned long comp_ramfs_addr = bfc_data + sizeof(NVTPACK_BFC_HDR); + unsigned int comp_ramfs_size = be32_to_cpu(p_hdr->uiSizeComp); + + p_linuxtmp->tmp_curr += ALIGN_CEIL_64(bfc_size); + p_linuxtmp->ramfs_addr = p_linuxtmp->tmp_curr; + p_linuxtmp->ramfs_size = be32_to_cpu(p_hdr->uiSizeUnComp); + p_linuxtmp->tmp_curr = p_linuxtmp->ramfs_addr + ALIGN_CEIL_64(p_linuxtmp->ramfs_size); + if (p_linuxtmp->tmp_curr >= p_linuxtmp->tmp_end) { + DBG_ERR("linuxtmp memory is too small, need more %d\n", p_linuxtmp->tmp_curr - p_linuxtmp->tmp_end); + return -1; + } + + unsigned int remain_blocks = ALIGN_CEIL(bfc_size - blk_size, blk_size) / blk_size; + if ((er = int_strg_obj->flash_readSectors((p_emb_partition_rootfs->PartitionOffset / blk_size) + 1, remain_blocks*blk_size, (UINT8 *)(bfc_data + blk_size), NAND_RW_FIRMWARE)) < 0) { + DBG_ERR("NG ramdisk-2\r\n"); + return -1; + } + //uncompress gzip + UINT32 algorithm = be32_to_cpu(p_hdr->uiAlgorithm) & 0xFF; + if (algorithm != 12) { + DBG_ERR("must gzip\r\n"); + return -1; + } + GZ_Uncompress((unsigned char *)comp_ramfs_addr, (unsigned char *)p_linuxtmp->ramfs_addr, comp_ramfs_size); +#else + DBG_ERR("ungzip is not supported in this build.\r\n"); + return -1; +#endif + } else { + p_linuxtmp->tmp_curr += ALIGN_CEIL_64(sizeof(image_header_t)); + p_linuxtmp->ramfs_addr = p_linuxtmp->tmp_curr; + + uintptr_t load_addr = p_linuxtmp->ramfs_addr - sizeof(image_header_t); + + //move 1st block + memmove((void *)(load_addr), (void *)bfc_data, blk_size); + + image_header_t *p_hdr = (image_header_t *)load_addr; + if (be32_to_cpu(p_hdr->ih_magic) != IH_MAGIC) { + DBG_ERR("ramdisk IH_MAGIC is wrong\r\n"); + return -1; + } + + //IH_TYPE_RAMDISK = 3 + if (p_hdr->ih_type != 3) { + DBG_ERR("ih_type (0x%X) != IH_TYPE_RAMDISK\r\n", (int)p_hdr->ih_type); + return -1; + } + // load rest of image data + unsigned int image_size = be32_to_cpu(p_hdr->ih_size) + sizeof(image_header_t); + p_linuxtmp->ramfs_size = be32_to_cpu(p_hdr->ih_size); + p_linuxtmp->tmp_curr = p_linuxtmp->ramfs_addr + ALIGN_CEIL_64(p_linuxtmp->ramfs_size); + + unsigned int remain_blocks = ALIGN_CEIL(image_size - blk_size, blk_size) / blk_size; + if ((er = int_strg_obj->flash_readSectors((p_emb_partition_rootfs->PartitionOffset / blk_size)+1, remain_blocks*blk_size, (UINT8 *)(load_addr + blk_size), NAND_RW_FIRMWARE)) < 0) { + DBG_ERR("NG ramdisk-2\r\n"); + return -1; + } + } + + return 0; +} +#endif + +_THUMB2 static int load_linux(LINUXTMP_PARTITION *p_linuxtmp, FDT_INFO *p_fdt_info) +{ + int er = 0; + int kernel_partition_id = -1; + uintptr_t bfc_data = p_linuxtmp->tmp_curr; + uintptr_t load_addr = p_fdt_info->linux_addr + CFG_LINUX_START_OFFSET - sizeof(image_header_t); + + int blk_size = (int)int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_kernel = bl_get_kernel_partition(fdt_get_base(), &kernel_partition_id); + + if (IS_SECURE() == 0 || SECURE_DECRYPT_RTOS == 0) { + //load 1st block + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_kernel->PartitionOffset / blk_size, blk_size, (UINT8 *)bfc_data, NAND_RW_FIRMWARE)) < 0) { + DBG_ERR("NG kernel-1\r\n"); + return -1; + } + + NVTPACK_BFC_HDR *p_hdr = (NVTPACK_BFC_HDR *)bfc_data; + + if (p_hdr->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { +#if (_GZIP_ENABLE_API_ == 1) + //bfc compressed kernel + unsigned int bfc_size = be32_to_cpu(p_hdr->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + unsigned long comp_kernel_addr = bfc_data + sizeof(NVTPACK_BFC_HDR); + unsigned int comp_kernel_size = be32_to_cpu(p_hdr->uiSizeComp); + + p_linuxtmp->tmp_curr += ALIGN_CEIL_64(bfc_size); + p_linuxtmp->lz_linux_addr = p_linuxtmp->tmp_curr; + p_linuxtmp->lz_linux_size = be32_to_cpu(p_hdr->uiSizeUnComp); + p_linuxtmp->tmp_curr = p_linuxtmp->lz_linux_addr + ALIGN_CEIL_64(p_linuxtmp->lz_linux_size); + if (p_linuxtmp->tmp_curr >= p_linuxtmp->tmp_end) { + DBG_ERR("linuxtmp memory is too small, need more %d\n", p_linuxtmp->tmp_curr - p_linuxtmp->tmp_end); + return -1; + } + + // check linux overlap with nvt_memory_cfg/fdt + if (IS_BIN_OVERLAP(load_addr, p_linuxtmp->lz_linux_size, p_fdt_info->fdt_addr, p_fdt_info->fdt_size)) { + DBG_ERR("OVERLAP: linux(0x%lX - 0x%lX) with fdt(0x%lX - 0x%lX)\n", load_addr, load_addr + p_linuxtmp->lz_linux_size, p_fdt_info->fdt_addr, p_fdt_info->fdt_addr + p_fdt_info->fdt_size); + return -1; + } + + unsigned int remain_blocks = ALIGN_CEIL(bfc_size - blk_size, blk_size) / blk_size; + if ((er = int_strg_obj->flash_readSectors((p_emb_partition_kernel->PartitionOffset / blk_size)+1, remain_blocks*blk_size, (UINT8 *)(bfc_data + blk_size), NAND_RW_FIRMWARE)) < 0) { + DBG_ERR("NG kernel-2\r\n"); + return -1; + } + + //uncompress gzip + UINT32 algorithm = be32_to_cpu(p_hdr->uiAlgorithm) & 0xFF; + if (algorithm != 12) { + DBG_ERR("must gzip\r\n"); + return -1; + } + // bfc has no image_header_t + UINT32 decoded_size = GZ_Uncompress((unsigned char *)comp_kernel_addr, (unsigned char *)(load_addr + sizeof(image_header_t)), comp_kernel_size); + return (decoded_size >= be32_to_cpu(p_hdr->uiSizeUnComp) ) ? 0 : -1; +#else + DBG_ERR("ungzip is not supported in this build.\r\n"); + return -1; +#endif + } else { + //move 1st block + memmove((void *)(load_addr), (void *)bfc_data, blk_size); + + image_header_t *p_hdr = (image_header_t *)load_addr; + if (be32_to_cpu(p_hdr->ih_magic) != IH_MAGIC) { + DBG_ERR("kernel IH_MAGIC is wrong\r\n"); + return -1; + } + +#if defined(__aarch64__) + //IH_TYPE_KERNEL = 2 + if (p_hdr->ih_type != 2) { + DBG_ERR("ih_type (0x%X) != IH_TYPE_KERNEL\r\n", (int)p_hdr->ih_type); + return -1; + } +#else + //IH_TYPE_MULTI = 4 + if (p_hdr->ih_type != 4 && p_hdr->ih_type != 2) { + DBG_ERR("ih_type (0x%X) != IH_TYPE_MULTI or IH_TYPE_KERNEL\r\n", (int)p_hdr->ih_type); + return -1; + } +#endif + if (p_hdr->ih_type == 4) { + memmove((void *)(load_addr - CFG_MULTI_MKIMAGE_LEN), (void *)load_addr, blk_size); + load_addr -= CFG_MULTI_MKIMAGE_LEN; + p_hdr = (image_header_t *)load_addr; + } + // load rest of image data + unsigned int image_size = be32_to_cpu(p_hdr->ih_size) + sizeof(image_header_t); + + // check linux overlap with nvt_memory_cfg/fdt + if (IS_BIN_OVERLAP(load_addr, image_size, p_fdt_info->fdt_addr, p_fdt_info->fdt_size)) { + DBG_ERR("OVERLAP: linux(0x%lX - 0x%lX) with fdt(0x%lX - 0x%lX)\n", load_addr, load_addr + image_size, p_fdt_info->fdt_addr, p_fdt_info->fdt_addr + p_fdt_info->fdt_size); + return -1; + } + + unsigned int remain_blocks = ALIGN_CEIL(image_size - blk_size, blk_size) / blk_size; + if ((er = int_strg_obj->flash_readSectors((p_emb_partition_kernel->PartitionOffset / blk_size)+1, remain_blocks*blk_size, (UINT8 *)(load_addr + blk_size), NAND_RW_FIRMWARE)) < 0) { + DBG_ERR("NG kernel-2\r\n"); + return -1; + } + return 0; + } + } else { +#if (SECURE_DECRYPT_KERNEL) + //load 1st block + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_kernel->PartitionOffset / blk_size, blk_size, (UINT8 *)bfc_data, NAND_RW_FIRMWARE)) < 0) { + DBG_ERR("NG kernel-1\r\n"); + return -1; + } + + // load rest of image data + int bin_size = ((HEADINFO *)(bfc_data))->BinLength; + + unsigned int remain_blocks = ALIGN_CEIL(bin_size - blk_size, blk_size) / blk_size; + if ((er = int_strg_obj->flash_readSectors((p_emb_partition_kernel->PartitionOffset / blk_size)+1, remain_blocks*blk_size, (UINT8 *)(bfc_data + blk_size), NAND_RW_FIRMWARE)) < 0) { + DBG_ERR("NG kernel-2\r\n"); + return -1; + } + + //decrypt + unsigned int plaintext_size = 0; + if ((er = do_decrypt_aes(bfc_data, bfc_data, &plaintext_size, bin_size)) != 0) { + debug_err_var("aes fail, er=", er); + return er; + } + + // uncompress + NVTPACK_BFC_HDR *p_hdr = (NVTPACK_BFC_HDR *)bfc_data; + if (p_hdr->uiFourCC != MAKEFOURCC('B', 'C', 'L', '1')) { + DBG_ERR("BCL1 header is wrong\r\n"); + return -1; + } + + //uncompress gzip + UINT32 algorithm = be32_to_cpu(p_hdr->uiAlgorithm) & 0xFF; + if (algorithm != 12) { + DBG_ERR("must gzip\r\n"); + return -1; + } + // bfc has no image_header_t + unsigned long comp_kernel_addr = bfc_data + sizeof(NVTPACK_BFC_HDR); + unsigned int comp_kernel_size = be32_to_cpu(p_hdr->uiSizeComp); + UINT32 decoded_size = GZ_Uncompress((unsigned char *)comp_kernel_addr, (unsigned char *)(load_addr + sizeof(image_header_t)), comp_kernel_size); + return (decoded_size >= be32_to_cpu(p_hdr->uiSizeUnComp) ) ? 0 : -1; +#else + debug_err("please ENABLE SECURE_DECRYPT_KERNEL config\n"); + return -1; +#endif + } + return 0; +} + +_THUMB2 static int make_bootargs(LINUXTMP_PARTITION *p_linuxtmp, FDT_INFO *p_fdt_info, unsigned int bootts_begin, int ramdisk) +{ + // read extend bootarg in fdt + unsigned char *p_fdt = (unsigned char *)fdt_get_base(); + if (p_fdt == NULL) { + DBG_ERR("p_fdt is NULL.\n"); + return -1; + } + + int len; + int nodeoffset = fdt_path_offset(p_fdt, "/chosen"); + const char *bootargs = (const char *)fdt_getprop(p_fdt, nodeoffset, "bootargs", &len); + + p_linuxtmp->bootargs_addr = p_linuxtmp->tmp_curr; + p_linuxtmp->bootargs_size = CFG_BOOTARG_MAX_LEN; + p_linuxtmp->tmp_curr += p_linuxtmp->bootargs_size; + + if (p_linuxtmp->tmp_curr >= p_linuxtmp->tmp_end) { + DBG_ERR("linuxtmp memory is too small, need more %d\n", p_linuxtmp->tmp_curr - p_linuxtmp->tmp_end); + return -1; + } + + int rootfs_partition_id = -1; + bl_get_rootfs_partition(fdt_get_base(), &rootfs_partition_id); + + utl_memset((char *)p_linuxtmp->bootargs_addr, 0, p_linuxtmp->bootargs_size); + + if (ramdisk) { + snprintf((char *)p_linuxtmp->bootargs_addr, CFG_BOOTARG_MAX_LEN - 1, CONFIG_BOOTARGS_RAMDISK "bootts=%u,%u user_debug=0xff %s", bootts_begin, (unsigned int)timer_getLdrElapse(), bootargs); + } else { +#if defined(_STORAGEINT_SpiFlash_) + snprintf((char *)p_linuxtmp->bootargs_addr, CFG_BOOTARG_MAX_LEN - 1, CONFIG_BOOTARGS "bootts=%u,%u user_debug=0xff %s root=/dev/mtdblock%d", bootts_begin, (unsigned int)timer_getLdrElapse(), bootargs, rootfs_partition_id); +#elif defined(_STORAGEINT_NandSpi_) + snprintf((char *)p_linuxtmp->bootargs_addr, CFG_BOOTARG_MAX_LEN - 1, CONFIG_BOOTARGS "bootts=%u,%u user_debug=0xff %s ubi.mtd=%d", bootts_begin, (unsigned int)timer_getLdrElapse(), bootargs, rootfs_partition_id); +#elif defined(_STORAGEINT_EMMC_) + snprintf((char *)p_linuxtmp->bootargs_addr, CFG_BOOTARG_MAX_LEN - 1, CONFIG_BOOTARGS "bootts=%u,%u user_debug=0xff %s", bootts_begin, (unsigned int)timer_getLdrElapse(), bootargs); +#endif + } + +#if (_NOR_DTR_PARAM_ == ENABLE) + strncat((char *)p_linuxtmp->bootargs_addr, " flash_dtr=on", CFG_BOOTARG_MAX_LEN - 1); +#endif + + return 0; +} + +_THUMB2 static int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name) +{ + int offset; + + offset = fdt_subnode_offset(fdt, parentoffset, name); + + if (offset == -FDT_ERR_NOTFOUND) { + offset = fdt_add_subnode(fdt, parentoffset, name); + } + + if (offset < 0) { + printf("%s: %s: %s\n", __func__, name, fdt_strerror(offset)); + } + + return offset; +} + +_THUMB2 static int chk_mem_overlap(FDT_INFO *p_fdt_info, const char *name, uintptr_t addr, unsigned long size) +{ + int i; + for (i = 0; i < (int)p_fdt_info->reserved_cnt; i++) { + LINUX_RESERVED_MEM *p = (LINUX_RESERVED_MEM *)&p_fdt_info->reserved[i]; + if (IS_BIN_OVERLAP(addr, size, p->addr, p->size)) { + + DBG_ERR("OVERLAP: %s(%lX - %lX) with %s(%lX - %lX)\n", + name, addr, addr + size, p->name, p->addr, p->addr + p->size); + DBG_ERR("Please move reserved memory in nvt-mem-tbl.dtsi\n"); + return -1; + } + } + return 0; +} + +_THUMB2 static int fdt_chosen(LINUXTMP_PARTITION *p_linuxtmp) +{ + int nodeoffset; + int err; + char *str; /* used to set string properties */ + + void *fdt = (void *)p_linuxtmp->fdt_addr; + + err = fdt_check_header(fdt); + if (err < 0) { + DBG_ERR("fdt_chosen: %s\n", fdt_strerror(err)); + return err; + } + + /* find or create "/chosen" node. */ + nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen"); + if (nodeoffset < 0) { + return nodeoffset; + } + + str = (char *)p_linuxtmp->bootargs_addr; + if (str) { + err = fdt_setprop(fdt, nodeoffset, "bootargs", str, + strlen(str) + 1); + if (err < 0) { + DBG_ERR("WARNING: could not set bootargs %s.\n", + fdt_strerror(err)); + return err; + } + } + + if (p_linuxtmp->ramfs_addr) { +#if defined(__aarch64__) + fdt64_t tmp = cpu_to_fdt64(p_linuxtmp->ramfs_addr); +#else + fdt32_t tmp = cpu_to_fdt32(p_linuxtmp->ramfs_addr); +#endif + err = fdt_setprop(fdt, nodeoffset, "linux,initrd-start", &tmp, sizeof(tmp)); + if (err < 0) { + DBG_ERR("WARNING: could not set initrd-start %s.\n", + fdt_strerror(err)); + return err; + } + +#if defined(__aarch64__) + tmp = cpu_to_fdt64(p_linuxtmp->ramfs_addr + p_linuxtmp->ramfs_size); +#else + tmp = cpu_to_fdt32(p_linuxtmp->ramfs_addr + p_linuxtmp->ramfs_size); +#endif + err = fdt_setprop(fdt, nodeoffset, "linux,initrd-end", &tmp, sizeof(tmp)); + if (err < 0) { + DBG_ERR("WARNING: could not set initrd-end %s.\n", + fdt_strerror(err)); + return err; + } + } + + return 0; +} + +_THUMB2 static void system_timer_stop(void) +{ + WRITE_CNTx_CTL(0); +} + +_THUMB2 static void system_timer_start(void) +{ + unsigned long long cval; + unsigned int ctl = 0; + + cval = READ_CNTxCT() + m_timer_interval; + // Counter-timer Physical Timer CompareValue register 4438 + WRITE_CNTx_CVAL(cval); + + ctl = READ_CNTx_CTL(); + ctl |= (1 << CNTP_CTL_ENABLE_SHIFT); + ctl |= (1 << CNTP_CTL_IMASK_SHIFT); // disable timer irq + WRITE_CNTx_CTL(ctl); +} + +_THUMB2 int system_init_timer(void) +{ + unsigned int CNTKCTL; + + /* Disable clock for timer */ + OUTREG32((SYSCNT_CTRL_BASE + CNTCR_OFF), 0); + + system_timer_stop(); + + // CNTKCTL, Counter-timer Kernel Control register @ arm-arm 4433 + CNTKCTL = read_cntkctl(); +#if (configTIMER_NUMBER == 27) //Virtual timer + CNTKCTL |= 0x02; +#elif(configTIMER_NUMBER == 29 || configTIMER_NUMBER == 26 || configTIMER_NUMBER == 30) //Non sec timer + CNTKCTL |= 0x01; +#endif + write_cntkctl(CNTKCTL); + +#if defined(__aarch64__) +#if (EXPECT_EL == EXCEPTION_LEVEL_2) + /* CNTHCTL_EL2.EL1PCEN: Set to 0 to enable traps to + * Hyp mode of Non-secure EL0 and EL1 accesses to the + * physical timer registers. + * + * CNTHCTL_EL2.EL1PCTEN: Set to 0 to enable traps to + * Hyp mode of Non-secure EL0 and EL1 accesses to the + * physical counter registers. + */ + unsigned int cnthctl = read_cnthctl(); + cnthctl &= ~(0x3); // + write_cnthctl(cnthctl); +#endif +#else + write_cntfrq(configCPU_CLOCK_HZ); +#endif + + m_timer_interval = read_cntfrq() / configTICK_RATE_HZ; + + system_timer_start(); + + /* Enable clock for timer, this is a global setting. */ + OUTREG32((SYSCNT_CTRL_BASE + CNTCR_OFF), (CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN)); + return 0; +} + +_THUMB2 int linuxboot_setup(unsigned char *p_fdt) +{ + int er; + int ramdisk = 0; + unsigned int bootts_begin = timer_getLdrElapse(); + + // initialize for fdt_get_base() + m_fdt = p_fdt; + + LINUXBOOT_INFO *p_info = &info; + LINUXTMP_PARTITION *p_linuxtmp = &p_info->linuxtmp; + FDT_INFO *p_fdt_info = &p_info->fdt_info; + + if ((er = fdt_get_info(p_fdt_info)) != 0) { + return er; + } + + p_linuxtmp->tmp_begin = p_fdt_info->linuxtmp_addr; + p_linuxtmp->tmp_curr = p_linuxtmp->tmp_begin; + p_linuxtmp->tmp_end = p_linuxtmp->tmp_begin + p_fdt_info->linuxtmp_size; + + // create new fdt for nodes of bootargs and ramdisk + if ((er = create_new_fdt(p_linuxtmp)) != 0) { + return er; + } + + // use fdt_get_base() use new fdt address, because old one will be destroyed on load_linux() + m_fdt = (void *)p_linuxtmp->fdt_addr; + +#if (CFG_INDEP_RAMDISK) + // load ramdisk into memory and reserved memory + if ((er = load_ramdisk(p_linuxtmp)) == 0) { + ramdisk = 1; + } else { + DBG_ERR("no ramdisk\r\n"); + } +#endif + + if ((er = load_linux(p_linuxtmp, p_fdt_info)) != 0) { + return er; + } + + // make bootargs + if ((er = make_bootargs(p_linuxtmp, p_fdt_info, bootts_begin, ramdisk)) != 0) { + return er; + } + + // insert bootargs and ramdisk into fdt + if ((er = fdt_chosen(p_linuxtmp)) != 0) { + return er; + } + + if ((er = chk_mem_overlap(p_fdt_info, "fdt", p_linuxtmp->fdt_addr, p_linuxtmp->fdt_size)) != 0) { + return er; + } +#if (CFG_INDEP_RAMDISK) + if ((er = chk_mem_overlap(p_fdt_info, "ramfs", p_linuxtmp->ramfs_addr, p_linuxtmp->ramfs_size)) != 0) { + return er; + } +#endif + if ((er = chk_mem_overlap(p_fdt_info, "bootargs", p_linuxtmp->bootargs_addr, p_linuxtmp->bootargs_size)) != 0) { + return er; + } + + return 0; +} + +_THUMB2 void linuxboot_go(void) +{ + LINUXBOOT_INFO *p_info = &info; + LINUXTMP_PARTITION *p_linuxtmp = &p_info->linuxtmp; + FDT_INFO *p_fdt_info = &p_info->fdt_info; + +#if 0 + printf("tmp_begin=0x%lX\n", p_linuxtmp->tmp_begin); + printf("tmp_curr=0x%lX\n", p_linuxtmp->tmp_curr); + printf("tmp_end=0x%lX\n", p_linuxtmp->tmp_end); + printf("fdt_addr=0x%lX\n", p_linuxtmp->fdt_addr); + printf("fdt_size=0x%lX\n", p_linuxtmp->fdt_size); + printf("ramfs_addr=0x%lX\n", p_linuxtmp->ramfs_addr); + printf("ramfs_size=0x%lX\n", p_linuxtmp->ramfs_size); + printf("lz_linux_addr=0x%lX\n", p_linuxtmp->lz_linux_addr); + printf("lz_linux_size=0x%lX\n", p_linuxtmp->lz_linux_size); + printf("bootargs_addr=0x%lX\n", p_linuxtmp->bootargs_addr); + printf("bootargs_size=0x%lX\n", p_linuxtmp->bootargs_size); +#endif + +#if defined(__aarch64__) + unsigned long x0 = p_linuxtmp->fdt_addr; +#else + unsigned int r2 = p_linuxtmp->fdt_addr; +#endif + unsigned long kernel_addr = p_fdt_info->linux_addr + CFG_LINUX_START_OFFSET; + + system_init_timer(); + +#if defined(__aarch64__) + { + void (*kernel_entry)(unsigned long fdt, unsigned long x1, unsigned long x2, unsigned long x3); + kernel_entry = (void (*)(unsigned long, unsigned long, unsigned long, unsigned long))((kernel_addr)); + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + DISABLE_DCACHE(); + DISABLE_ICACHE(); + DISABLE_MMU(); + CLEAR_MMU(); + kernel_entry(x0, 0, 0, 0); // never returned + } +#else + // disable both irq and fiq + __asm volatile ( "CPSID if" ::: "memory" ); + __asm volatile ( "DSB" ); + __asm volatile ( "ISB" ); + + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + DISABLE_DCACHE(); + DISABLE_ICACHE(); + DISABLE_MMU(); + CLEAR_MMU(); + + //alway enter #Mode_SVC before start linux + __asm__("cps #0x13"); + { + void (*kernel_entry)(int zero, int arch, unsigned int params); + kernel_entry = (void (*)(int, int, unsigned int))((kernel_addr)); + kernel_entry(0, 0, r2); // never returned + } +#endif +} + +_THUMB2 int linuxboot_go_info(unsigned long *p_kernel_addr, unsigned long *p_fdt_addr) +{ + LINUXBOOT_INFO *p_info = &info; + FDT_INFO *p_fdt_info = &p_info->fdt_info; + + *p_kernel_addr = p_fdt_info->linux_addr + CFG_LINUX_START_OFFSET; + *p_fdt_addr = p_info->linuxtmp.fdt_addr; + + return 0; +} + +#endif // (BOOT_LINUX_SUPPORT) \ No newline at end of file diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_linux.h b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_linux.h new file mode 100755 index 000000000000..fbcfbc8095f5 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_linux.h @@ -0,0 +1,9 @@ +#ifndef _BL_LINUX_H +#define _BL_LINUX_H + +extern int linuxboot_setup(unsigned char *p_fdt); +extern void linuxboot_go(void); +extern int linuxboot_go_info(unsigned long *p_kernel_addr, unsigned long *p_fdt_addr); +extern int system_init_timer(void); + +#endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lowlevel_init.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lowlevel_init.c new file mode 100755 index 000000000000..557bba88c35b --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lowlevel_init.c @@ -0,0 +1,368 @@ + +/** + * @brief This File is unable to use printf, + * because rom api not ready at this time. + */ +#include "constant.h" +#include "fuart.h" +#include "fat.h" +#include "StorageDef.h" +#include "global.h" +#include "bl_func.h" +#include "string.h" +#include "debug.h" +#include "loader.h" +#include +#include "nand.h" +#include "nor.h" +#include "Cache.h" +#include "libfdt.h" +#include "bl_lowlevel_init.h" +#include + +#define CFG_FDTFAST_BUF IPE_SRAM_BASE_ADDR +#define CFG_FDTFAST_BUF_SIZE IPE_SRAM_BASE_SIZE + +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) + +#if defined(_STORAGEINT_NandSpi_) +#define EMB_GETSTRGOBJ() nand_get_storage_object() +#elif defined(_STORAGEINT_NandEccBCH_) +#define EMB_GETSTRGOBJ() nand_bch_get_storage_object() +#elif defined(_STORAGEINT_SpiFlash_) +#define EMB_GETSTRGOBJ() nor_get_storage_object() +#elif defined(_STORAGEINT_EMMC_) +#define EMB_GETSTRGOBJ() emmc_get_storage_object() +#elif defined(_STORAGEINT_EMMC_NAND_COMBO_) +#elif defined(_STORAGEINT_NONE_) +#else +#error "unknown internal storage type" +#endif + +#define _THUMB2 __attribute__((target("thumb"))) + +typedef enum _CFE_TYPE { + CFE_TYPE_WRITE = 0, + CFE_TYPE_MASK_CLEAR, + CFE_TYPE_MASK_SET, + CFE_TYPE_DELAY, +} CFE_TYPE; + +typedef struct _CFE_CMD { + unsigned int type; + unsigned int addr; + unsigned int value; +} CFE_CMD; + +static volatile unsigned int *mp_core2_addr = (volatile unsigned int *)CC_CPU2_CPU1_CMDBUF_REG1; +static UINT32 g_flash_dtr = 0; +static uintptr_t g_fdtfast_addr = 0; +static uintptr_t g_fdt_addr = 0; +static UINT32 g_fast_sensor = 0; +static UINT32 g_is_flash_opened = 0; + +extern void config_dma_wait_done(void); + +#if (FDTFAST_SENSOR==ENABLE) +#define FDTFAST_SENSOR_CHK_STS DISABLE +#if (FDTFAST_SENSOR_CHK_STS==ENABLE) +_THUMB2 static void bl_DumpReg(UINT32 base, UINT32 size) +{ + UINT32 end = base + size; + printf("========== DumpReg 0x%08X ==========\r\n", base); + while (base < end) { + printf("0x%08X : 0x%08X 0x%08X 0x%08X 0x%08X\r\n", base, + *(volatile UINT32 *)(base + 0x0), *(volatile UINT32 *)(base + 0x4), + *(volatile UINT32 *)(base + 0x8), *(volatile UINT32 *)(base + 0xc)); + base += 0x10; + } +} +#define DelayT(x) do {for(volatile int t=0; t<(x); t++);} while(0) +_THUMB2 static void bl_CheckStatus(void) +{ + OUTREG32(0xf0280018, 0xffffffff); + OUTREG32(0xf028001c, 0xffffffff); + bl_DumpReg(0xF0280000, 0x100); + DelayT(100000); + bl_DumpReg(0xF0280000, 0x100); + bl_DumpReg(0xF0020000, 0x100); + bl_DumpReg(0xF00D0000, 0x100); +} +#endif +_THUMB2 static int bl_parse_preset_sub_dtsi(UINT8 *pfdt_addr, INT32 node_ofst, UINT32 *param_ptr, char *prop_name) +{ + const void *pfdt_node; + INT32 param_size; + UINT32 *pdata = NULL; + + pfdt_node = fdt_getprop(pfdt_addr, node_ofst, prop_name, (int *)¶m_size); + if ((pfdt_node != NULL) && (param_size != 0)) { + pdata = (UINT32 *)pfdt_node; + *param_ptr = be32_to_cpu(*pdata); + return 0; + } else { + return -1; + } +} + +_THUMB2 int bl_sensor_chgmode(unsigned char *p_fdt_hdr, int fdt_from_dram) +{ + int i, n, len; + int i2c_id = 0; + int nodeoffset; + const void *nodep; + UINT32 desc_addr; + UINT32 desc_size; + + nodeoffset = fdt_path_offset(p_fdt_hdr, "sensor0"); + if (nodeoffset< 0) { + debug_msg("sn: n/a\r\n"); + return 0; + } + + nodep = fdt_getprop(p_fdt_hdr, nodeoffset, "cmd", &len); + if (len == 0 || nodep == NULL) { + debug_err("sn: no cmd\r\n"); + return -1; + } + desc_addr = (UINT32)nodep; + desc_size = (UINT32)len; + + nodep = fdt_getprop(p_fdt_hdr, nodeoffset, "cfe", &len); + if (len == 0 || nodep == NULL) { + debug_err("sn: no cfe\r\n"); + return -1; + } + + bl_parse_preset_sub_dtsi((UINT8 *)p_fdt_hdr, (INT32)nodeoffset, (UINT32 *)&i2c_id, "i2c_id"); + + CFE_CMD *p_cfe = (CFE_CMD *)nodep; + n = len / sizeof(CFE_CMD); + cfe_open(0); + for (i = 0; i < n; i++) { + int type = be32_to_cpu(p_cfe->type); + unsigned int addr = be32_to_cpu(p_cfe->addr); + unsigned int value = be32_to_cpu(p_cfe->value); + switch (type) + { + case CFE_TYPE_WRITE: + cfe_write_reg(addr, value); + break; + case CFE_TYPE_MASK_CLEAR: + cfe_mask_clear(addr, value); + break; + case CFE_TYPE_MASK_SET: + cfe_mask_set(addr, value); + break; + case CFE_TYPE_DELAY: + cfe_delay(value); + break; + default: + debug_err_var("sn: un cmd: ", type); + return -1; + } + p_cfe++; + } + + if (fdt_from_dram) { + utl_memcpy((void *)CFG_FDTFAST_BUF, (void *)desc_addr, desc_size); + desc_addr = (UINT32)CFG_FDTFAST_BUF; + } + CPUflushWriteCache(desc_addr, desc_size); + cfe_auto_desc(desc_addr, I2C+i2c_id); + cfe_trig(); + +#if (FDTFAST_SENSOR_CHK_STS==ENABLE) + //---- check status + bl_CheckStatus(); +#endif + g_fast_sensor = 1; + return 0; +} +#endif + +#if (FDTFAST_FROM_DRAM != ENABLE) +_THUMB2 static int bl_lowlevel_load_fdtfast(void) +{ +#if (FDTFAST_SENSOR==ENABLE) +#if (MULTI_CODE_FLOW) && !defined(_STORAGEINT_NONE_) + PSTORAGE_OBJ strg_obj = EMB_GETSTRGOBJ(); +#if defined(_STORAGEINT_NandSpi_) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#elif defined(_STORAGEINT_EMMC_) + //strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, TRUE); + UINT32 high_speed = TRUE; + strg_obj->flash_setConfig(FLASH_CFG_ID_HIGH_SPEED, high_speed); + if (ROM_GetCurrBS() == BOOT_SOURCE_EMMC_8BIT) { + strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, TRUE); + } else if (ROM_GetCurrBS() == BOOT_SOURCE_EMMC_4BIT) { + strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, FALSE); + } else { +#if (EMMC_PINMUX_SETTING == EMMC_PINMUX_8BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, TRUE); +#else + strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, FALSE); +#endif + } +#endif +#if (_NOR_DTR_PARAM_ == ENABLE) //DTR force enable + strg_obj->flash_installIdentifyCB(nor_identify); +#endif +#if defined(_FLASH_FREQ_MHZ_) + strg_obj->flash_setFrequency(_FLASH_FREQ_MHZ_); +#endif + +#if (_NOR_DTR_PARAM_ == ENABLE) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_DTR, TRUE); + g_flash_dtr = 1; +#endif + + INT32 er = strg_obj->flash_open(); + if (er < 0) { + debug_msg("ll:flash o ng\r\n"); + } else { + int blk_size = strg_obj->flash_getBlockSize(); + int fdtfast_iblk = FDTFAST_OFFSET / blk_size; + unsigned char *p_tmp = (unsigned char *)CFG_FDTFAST_BUF; +#if 0// (_NOR_DTR_PARAM_ == ENABLE) auto tunning not ready yet + if(strg_obj->flash_auto_tune_read_block) { + if ((er = strg_obj->flash_auto_tune_read_block(fdtfast_iblk, 0x1000, p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_msg("tunning NG\r\n"); + //bl_displayErrMsg(RWErrorMsg); // read bl31 failed + } else { + g_flash_dtr = 1; + debug_msg("tunning OK\r\n"); + } + } +#endif + er = strg_obj->flash_readSectors(fdtfast_iblk, blk_size, p_tmp, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("r fdtfast NG-1\r\n"); + return -1; + } + + g_is_flash_opened = 1; + + unsigned int fdt_tunning_offset = 0; + unsigned int forcc = *(unsigned int *)p_tmp; + if (forcc == DTR_TUNNING_PATTERN_DATA1 || forcc == DTR_TUNNING_PATTERN_DATA2) { + fdt_tunning_offset += DTR_TUNNING_PATTERN_SIZE; + } + + unsigned char *p_fdt_hdr = p_tmp + fdt_tunning_offset; + + if (fdt_check_header(p_fdt_hdr) != 0) { + debug_msg("no fdtfast\r\n"); + return -1; + } + + int fdtfast_size = fdt_totalsize(p_fdt_hdr); + int total_size = ALIGN_CEIL(fdtfast_size + fdt_tunning_offset, blk_size); + if ((int)CFG_FDTFAST_BUF_SIZE < total_size) { + debug_err("CFG_FDTFAST_BUF_SIZE too small\r\n"); + return -1; + } + + total_size -= blk_size; + if (total_size > 0) { + // read remain to get uboot starting addr on dram and offset in flash + er = strg_obj->flash_readSectors(fdtfast_iblk + 1, total_size, p_tmp + blk_size, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("r fdtfast NG-2\r\n"); + return -1; + } + } + + if (fdt_check_full(p_fdt_hdr, fdt_totalsize(p_fdt_hdr)) != 0) { + debug_err("chk fdtfast NG\r\n"); + return -1; + } + + g_fdtfast_addr = (uintptr_t)p_fdt_hdr; + + #if (FDTFAST_SENSOR==ENABLE) + if (bl_sensor_chgmode(p_fdt_hdr, 0) != 0) { + debug_err("sen chgmode NG\r\n"); + return -1; + } + #endif + + return 0; + } +#endif +#endif + return -1; +} +#endif + +_THUMB2 void bl_lowlevel_init(void) +{ + *mp_core2_addr = 0; //clean core2 jump address + +#if (FDTFAST_FROM_DRAM != ENABLE) + bl_lowlevel_load_fdtfast(); +#endif + config_dma_wait_done(); + debug_msg("bl_lowlevel_init done\r\n"); +} + +_THUMB2 int bl_lowlevel_is_dtr_tunned(void) +{ + return g_flash_dtr; +} + + +_THUMB2 int bl_lowlevel_is_fast_sensor(void) +{ + return g_fast_sensor; +} + +_THUMB2 uintptr_t bl_lowlevel_get_fdtfast(void) +{ + return g_fdtfast_addr; +} + +_THUMB2 uintptr_t bl_lowlevel_get_fdt(void) +{ + return g_fdt_addr; +} + +_THUMB2 void bl_lowlevel_core2_jump(void) +{ + typedef void (*BRANCH_CB)(void); + + //must comes before while, because loader has been replaced then. + bl_lowlevel_cpu_timer_init(); + while(*mp_core2_addr == 0) { + } + + perf_mark("c2jp"); + +#if (DUMP_FLOW_TIMESTAMP) + perf_dump(); +#endif + +// printf("go to %08X\n", *mp_core2_addr); + DISABLE_MMU(); + CLEAR_MMU(); + + BRANCH_CB p_func = (BRANCH_CB)(*mp_core2_addr); + p_func(); +} + +_THUMB2 void bl_lowlevel_core2_setaddr(unsigned long core2_addr) +{ + *mp_core2_addr = core2_addr; +} + +_THUMB2 void bl_lowlevel_cpu_timer_init(void) +{ + UINT32 value = CPU_TIMER_FREQ; + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(value)); +} + +_THUMB2 int bl_lowlevel_is_flash_opened(void) +{ + return g_is_flash_opened; +} \ No newline at end of file diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lowlevel_init.h b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lowlevel_init.h new file mode 100755 index 000000000000..d002ea65e87f --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lowlevel_init.h @@ -0,0 +1,14 @@ +#ifndef _BL_LOWLEVEL_INIT_H +#define _BL_LOWLEVEL_INIT_H + +extern void bl_lowlevel_init(void); +extern void bl_lowlevel_core2_jump(void); +extern void bl_lowlevel_core2_setaddr(unsigned long core2_addr); +extern void bl_lowlevel_cpu_timer_init(void); +extern int bl_lowlevel_is_dtr_tunned(void); +extern unsigned long bl_lowlevel_get_fdt(void); +extern unsigned long bl_lowlevel_get_fdtfast(void); +extern int bl_lowlevel_is_fast_sensor(void); +extern int bl_lowlevel_is_flash_opened(void); +extern int bl_sensor_chgmode(unsigned char *p_fdt_hdr, int fdt_from_dram); +#endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.c new file mode 100644 index 000000000000..b6f60081b993 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.c @@ -0,0 +1,52 @@ +/* + * OpenIPC: LZMA for U-Boot's BCL1 container (algorithm 11). NA51089's + * mask ROM has a decoder the loader calls; the NS02501 loader is built + * without its ROM calls (MakeOption.txt: ROM_PUBLIC_API OFF; its + * ROM_LZMA_POSITION branch is the NA51089 one's, never enabled), so it + * carries its own, Igor Pavlov's public domain LzmaDec as U-Boot has it + * (lib/lzma). The input is an .lzma stream: 5 bytes of properties, the + * unpacked size as a 64-bit word, then the data. + */ +/* OpenIPC: small, in Thumb */ +#pragma GCC target("thumb") +#pragma GCC optimize("Os") + +#include "LzmaDec.h" +#include "bl_lzma.h" + +/* lc + lp <= 4: at most 1846 + 768 << 4 probabilities of 16 bits */ +static unsigned char lzma_heap[0x8000] __attribute__((aligned(8))); + +static void *lzma_alloc(void *p, size_t size) +{ + (void)p; + return size <= sizeof(lzma_heap) ? lzma_heap : NULL; +} + +static void lzma_free(void *p, void *address) +{ + (void)p; + (void)address; +} + +int bl_lzma_inflate(unsigned char *in, unsigned int in_size, + unsigned char *out, unsigned int out_size) +{ + ISzAlloc alloc = { lzma_alloc, lzma_free }; + SizeT src_len, dst_len = out_size; + ELzmaStatus status; + unsigned int len; + + if (in_size < LZMA_PROPS_SIZE + 8) + return -1; + len = in[LZMA_PROPS_SIZE] | in[LZMA_PROPS_SIZE + 1] << 8 | + in[LZMA_PROPS_SIZE + 2] << 16 | + (unsigned int)in[LZMA_PROPS_SIZE + 3] << 24; + if (len < dst_len) + dst_len = len; + src_len = in_size - LZMA_PROPS_SIZE - 8; + if (LzmaDecode(out, &dst_len, in + LZMA_PROPS_SIZE + 8, &src_len, in, + LZMA_PROPS_SIZE, LZMA_FINISH_END, &status, &alloc) != SZ_OK) + return -1; + return (int)dst_len; +} diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.h b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.h new file mode 100644 index 000000000000..3ba773801442 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_lzma.h @@ -0,0 +1,9 @@ +/* OpenIPC: LZMA for U-Boot's BCL1 container (bl_lzma.c) */ +#ifndef _BL_LZMA_H +#define _BL_LZMA_H + +/* Returns the unpacked length, or -1 */ +int bl_lzma_inflate(unsigned char *in, unsigned int in_size, + unsigned char *out, unsigned int out_size); + +#endif diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.c new file mode 100755 index 000000000000..cfbf7c16665f --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.c @@ -0,0 +1,404 @@ +#include "constant.h" +#include "fuart.h" +#include "fat.h" +#include "StorageDef.h" +#include "global.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "bl_func.h" +#include "string.h" +#include "lz.h" +#include "debug.h" +#include "loader.h" +#include "emb_partition_info.h" +#include "modelext_info.h" +#include "bin_info.h" +#include "shm_info.h" +#include "libfdt.h" +#include +//#include "mmc_api.h" +#include "Cache.h" +#include "Memory.h" +#include "timer.h" +#include "lz.h" +#include "bl_u2.h" +#include "nand.h" +#include "nor.h" + +#ifndef ALIGN_FLOOR +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#endif +#ifndef ALIGN_CEIL +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#endif + +#if (USB_WRITELOADER || UART_UPDATE) + +//u2: means usb and uart +#include "scsi_op.h" + +typedef enum _U2_FW_TYPE { + U2_FW_TYPE_UNKNOWN, + U2_FW_TYPE_NVTPACK, + U2_FW_TYPE_UBOOT, +} U2_FW_TYPE; + +#define MAKEUINT32(a, b, c, d) ((UINT32)((a)&0xFF)) | (((UINT32)((b)&0xFF)) << 8) | (((UINT32)((c)&0xFF)) << 16) | (((UINT32)((d)&0xFF)) << 24) + +static U2_FW_TYPE m_u2_fw_type = U2_FW_TYPE_UNKNOWN; +static unsigned int m_u2_fw_size = 0; +static unsigned char *m_fdt = NULL; +UINT32 m_tmp_addr = SDRAM_Start_FW; +static int m_uboot_status = -2; +static int m_fdt_status = -1; +static SCSIOP_FLASH_OP m_flash_op = {0}; + +__attribute__((target("thumb"))) static int u2_check_firmware(unsigned int addr) +{ + NVTPACK_FW_HDR2 *p_hdr = (NVTPACK_FW_HDR2 *)addr; + unsigned int size = p_hdr->TotalSize; + NVTPACK_MEM mem_in ; + mem_in.p_data = (void *)addr; + mem_in.len = size; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + m_u2_fw_type = U2_FW_TYPE_NVTPACK; + m_u2_fw_size = size; + return 0; + } + // uboot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)addr; // describe compressed u-boot + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = __builtin_bswap32(pBfc->uiSizeComp); + UINT32 addr_uncomp = ALIGN_CEIL(addr + size_comp_le, 4); + LZ_Uncompress((UINT8 *)addr + sizeof(NVTPACK_BFC_HDR), (unsigned char *)addr_uncomp, 1024); + addr = addr_uncomp; + } + HEADINFO *p_headinfo = (HEADINFO *)(addr + BIN_INFO_OFFSET_UBOOT); + if (p_headinfo->BinLength < 0x1000000 && bl_chk_uboot(addr, p_headinfo->BinLength) == 0) { + m_u2_fw_type = U2_FW_TYPE_UBOOT; + m_u2_fw_size = p_headinfo->BinLength; + if (m_fdt == NULL) { + //check fdt followed uboot + unsigned char *fdt = (unsigned char *)(addr + m_u2_fw_size); + if (fdt_check_header(fdt) != 0) { + debug_err("no fdt behind uboot\r\n"); + return -1; + } + } + return 0; + } + + return -1; +} + +__attribute__((target("thumb"))) static int u2_boot_uboot(unsigned int addr, unsigned int size, U2_FW_TYPE fw_type) +{ + if (fw_type == U2_FW_TYPE_NVTPACK) { + UINT32 comp_addr = 0; + UINT32 comp_size = 0; + DRAM_PARTITION *p_dram_partition = NULL; + return bl_process_all_in_one(addr, size, &p_dram_partition, FUNC_UPDATE_FW, &comp_addr, &comp_size); + } else { + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(addr + BIN_INFO_OFFSET_UBOOT); + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)addr; // describe compressed u-boot + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = __builtin_bswap32(pBfc->uiSizeComp); + UINT32 addr_uncomp = ALIGN_CEIL(addr + size_comp_le, 4); + LZ_Uncompress((UINT8 *)addr + sizeof(NVTPACK_BFC_HDR), (unsigned char *)addr_uncomp, 1024); + p_headinfo = (HEADINFO *)(addr_uncomp + BIN_INFO_OFFSET_UBOOT); + } + // check tmp memory (file load) cannot overlap with uboot + if ((addr < p_headinfo->CodeEntry && addr + size > p_headinfo->CodeEntry) || + (addr > p_headinfo->CodeEntry && addr + size < p_headinfo->CodeEntry + size)) { + debug_err_var("addr", addr); + debug_err_var("size", size); + debug_err_var("CodeEntry", p_headinfo->CodeEntry); + debug_err("uboot & tmp_addr are overlapped\r\n"); + return -1; + } + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = __builtin_bswap32(pBfc->uiSizeComp); + LZ_Uncompress((UINT8 *)addr + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_headinfo->CodeEntry, size_comp_le); + } else { + utl_memcpy((void *)p_headinfo->CodeEntry, (void *)addr, size); + } + + if (m_fdt != NULL) { + bl_boot_uboot(m_fdt); + } else { + //check fdt followed uboot + unsigned char *fdt = (unsigned char *)(addr + size); + if (fdt_check_header(fdt) != 0) { + debug_err("no fdt behind uboot\r\n"); + return -1; + } + utl_memcpy((void *)(p_headinfo->CodeEntry + size), fdt, fdt_totalsize(fdt)); + debug_msg_var("jump", p_headinfo->CodeEntry); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)p_headinfo->CodeEntry; + p_func(); + } + } + } + return 0; +} + +__attribute__((target("thumb"))) static int u2_on_verify(unsigned int p_cmd, unsigned int *p_data, unsigned int *in_size) +{ + NVT_SCSI_CBW *p_cbw = (NVT_SCSI_CBW *)p_cmd; + int cmd_id = p_cbw->CBWCB[1]; + + switch (cmd_id) { + case SCSIOP_OUT_MEM_WRITE: + *p_data = MAKEUINT32(p_cbw->CBWCB[2], p_cbw->CBWCB[3], p_cbw->CBWCB[4], p_cbw->CBWCB[5]); + *in_size = p_cbw->dCBWDataTransferLength; + break; + case SCSIOP_OUT_FLASH_ACCESS: + if (p_cbw->dCBWDataTransferLength != sizeof(m_flash_op)) { + debug_err_var("m_flash_op size not matched", *in_size); + return -1; + } + *p_data = (UINT32)&m_flash_op; + *in_size = p_cbw->dCBWDataTransferLength; + break; + case SCSIOP_IN_MEM_READ: + *p_data = MAKEUINT32(p_cbw->CBWCB[2], p_cbw->CBWCB[3], p_cbw->CBWCB[4], p_cbw->CBWCB[5]); + *in_size = p_cbw->dCBWDataTransferLength; + //debug_msg_var("p_data:", MAKEUINT32(p_cbw->CBWCB[2], p_cbw->CBWCB[3], p_cbw->CBWCB[4], p_cbw->CBWCB[5])); + break; + case SCSIOP_IN_GET_TMP_ADDR: + *p_data = (unsigned int)&m_tmp_addr; + *in_size = sizeof(m_tmp_addr); + break; + case SCSIOP_IN_FDT: + *p_data = (unsigned int)&m_fdt_status; + *in_size = sizeof(m_fdt_status); + if (bl_chk_fdt((unsigned int)SDRAM_Start_FW, fdt_totalsize(SDRAM_Start_FW)) == 0) { + m_fdt_status = bl_copy_fdt_to_fdt_addr((unsigned char *)SDRAM_Start_FW, &m_fdt); + } else { + m_fdt_status = -1; + } + break; + case SCSIOP_IN_UBOOT: + *p_data = (unsigned int)&m_uboot_status; + *in_size = sizeof(m_uboot_status); + if (u2_check_firmware(SDRAM_Start_FW) == 0) { + m_uboot_status = 0; + } else { + m_uboot_status = -1; + } + break; + default: + debug_err_var("unknown_cmd_id", cmd_id); + break; + } + return 0; +} + +__attribute__((target("thumb"))) static int u2_flash_open(unsigned int flash_type) +{ + static int is_opened[4] = {0}; + + if (flash_type >= 4) { + debug_err_var("flash_type", flash_type); + return -1; + } + + // open default and its related to + if (is_opened[0] == 0) { + if (bl_flash_open() != 0) { + return -1; + } + is_opened[0] = 1; +#if !defined(_STORAGEINT_EMMC_) + if (int_strg_obj == nand_get_storage_object()) { + is_opened[FLASH_ACCESS_TYPE_NAND] = 1; + } + if (int_strg_obj == nor_get_storage_object()) { + is_opened[FLASH_ACCESS_TYPE_NOR] = 1; + } +#endif + } + + if (is_opened[flash_type]) { + return 0; + } + +#if !defined(_STORAGEINT_EMMC_) + switch(flash_type) { + case FLASH_ACCESS_TYPE_NAND: +#if 0 + // User define SPI-NAND id table sample code + nand_get_storage_object()->flash_setConfig(FLASH_CFG_ID_SPI_IDENTIFY_CB, (UINT32)nand_identify); +#endif + nand_get_storage_object()->flash_open(); + is_opened[FLASH_ACCESS_TYPE_NAND] = 1; + break; + case FLASH_ACCESS_TYPE_NOR: +#if 0 + // User define SPI-NOR id table sample code + nor_get_storage_object()->flash_installIdentifyCB(nor_identify); +#endif + nor_get_storage_object()->flash_open(); + is_opened[FLASH_ACCESS_TYPE_NOR] = 1; + break; + default: + debug_err_var("unsupported flash_type", flash_type); + return -1; + } + return 0; +#else + debug_err("flash_type must be auto on emmc"); + return -1; +#endif +} + +__attribute__((target("thumb"))) static int u2_on_vendor(unsigned int p_cmd) +{ + int er; + PSTORAGE_OBJ p_strg = NULL; + NVT_SCSI_CBW *p_cbw = (NVT_SCSI_CBW *)p_cmd; + int cmd_id = p_cbw->CBWCB[1]; + + switch (cmd_id) { + case SCSIOP_OUT_MEM_WRITE: + break; + case SCSIOP_OUT_FLASH_ACCESS: + if (u2_flash_open(m_flash_op.type) != 0) { + return -1; + } + switch(m_flash_op.type) { + case FLASH_ACCESS_TYPE_AUTO: + p_strg = int_strg_obj; + break; +#if !defined(_STORAGEINT_EMMC_) + case FLASH_ACCESS_TYPE_NAND: + p_strg = nand_get_storage_object(); + break; + case FLASH_ACCESS_TYPE_NOR: + p_strg = nor_get_storage_object(); + break; +#endif + default: + debug_err_var("unsupport flash_type", m_flash_op.type); + return -1; + } + + if (m_flash_op.is_write) { + //write + unsigned int block_size = p_strg->flash_getBlockSize(); + unsigned int startblk = (unsigned int)(m_flash_op.offset / block_size); + unsigned int write_size = ALIGN_CEIL(m_flash_op.size, block_size); + if (startblk == 0) { + // write block 0 means update loader area + if ((er = p_strg->flash_writePartition(startblk, write_size, (unsigned int)(m_flash_op.partition_size), (UINT8 *)SDRAM_Start_FW, NAND_RW_LOADER)) != 0) { + debug_err_var("wr failed", er); + return -1; + } + } else { + if ((er = p_strg->flash_writePartition(startblk, write_size, (unsigned int)(m_flash_op.partition_size), (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE)) != 0) { + debug_err_var("wr failed", er); + return -1; + } + } + //Once write loader something wrong happen.. + //Can enable code bellow make sure data were program into SPI-NOR/NAND +#if 0 + else { //Read back and make checksum + unsigned int reload_addr; + UINT32 status = 0; + reload_addr = SDRAM_Start_FW + write_size; + + int_strg_obj->flash_getConfig(FLASH_CFG_ID_SPI_GET_STATUS_1,(UINT32)&status); + debug_msg_var( +"status1", status); + + if (int_strg_obj->flash_readSectors(startblk, write_size, (UINT8 *)reload_addr, NAND_RW_LOADER) < 0) { + debug_err("rd fail\r\n"); + } else { + debug_err("rd success\r\n"); + } + // Verify + if (memcmp((void *)SDRAM_Start_FW, (void *)reload_addr, write_size) != 0) { + debug_err("verify fail\r\n"); + } else { + debug_msg_var("read back 0x0",*(UINT32 *)(reload_addr+0x0)); + debug_msg_var("read back 0x4",*(UINT32 *)(reload_addr+0x4)); + debug_msg_var("read back 0x8",*(UINT32 *)(reload_addr+0x8)); + debug_msg_var("read back 0xc",*(UINT32 *)(reload_addr+0xc)); + } + + } +#endif + } else { + //read + unsigned int block_size = p_strg->flash_getBlockSize(); + unsigned int startblk = (unsigned int)(m_flash_op.offset / block_size); + unsigned int read_size = ALIGN_CEIL(m_flash_op.size, block_size); + if (startblk == 0) { + // read block 0 means update loader area + if ((er = p_strg->flash_readSectors(startblk, read_size, (UINT8 *)SDRAM_Start_FW, NAND_RW_LOADER)) != 0) { + debug_err_var("rd failed", er); + return -1; + } + } else { + if ((er = p_strg->flash_readSectors(startblk, read_size, (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE)) != 0) { + debug_err_var("rd failed", er); + return -1; + } + } + } + break; + case SCSIOP_IN_MEM_READ: + case SCSIOP_IN_GET_TMP_ADDR: + break; + case SCSIOP_IN_FDT: + break; + case SCSIOP_IN_UBOOT: + break; + default: + debug_err_var("unknown_cmd_id", cmd_id); + break; + } + return 0; +} + +__attribute__((target("thumb"))) int bl_usb(void) +{ + + typedef int (*MSDC_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); + typedef int (*MSDC_VenDone_CB)(unsigned int pCmdBuf); + extern void fLib_USB_Update_FW(void); + extern MSDC_Verify_CB guiU2MsdcCheck_cb; + extern MSDC_VenDone_CB guiU2MsdcVendorDone_cb; + guiU2MsdcCheck_cb = u2_on_verify; + guiU2MsdcVendorDone_cb = u2_on_vendor; + fLib_USB_Update_FW(); + u2_boot_uboot(SDRAM_Start_FW, m_u2_fw_size, m_u2_fw_type); + return 0; +} + +__attribute__((target("thumb"))) int bl_uart(void) +{ + + typedef int (*UART_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); + typedef int (*UART_Vendor_CB)(unsigned int pCmdBuf); + extern void uart_upgrade_procedure(void); + extern UART_Verify_CB guiUARTCheck_cb; + extern UART_Vendor_CB guiUARTVendor_cb; + guiUARTCheck_cb = u2_on_verify; + guiUARTVendor_cb = u2_on_vendor; + uart_upgrade_procedure(); + u2_boot_uboot(SDRAM_Start_FW, m_u2_fw_size, m_u2_fw_type); + return 0; +} + +#endif //USB_WRITELOADER diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.h b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.h new file mode 100755 index 000000000000..28ae6ee7c714 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.h @@ -0,0 +1,7 @@ +#ifndef _BL_USB_H +#define _BL_USB_H + +extern int bl_usb(void); +extern int bl_uart(void); + +#endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c new file mode 100755 index 000000000000..92e5b87214fe --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c @@ -0,0 +1,191 @@ +/* + Main control function + + This file is implement by user mode + + @file main.c + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ +#include "main.h" +#include "bl_func.h" +#include "Cache.h" +#include "global.h" +#include "fuart.h" +#include "debug.h" + +extern char _loader_exec_compres_start[]; +extern char _loader_exec_compress_load_cpu_addr[]; +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[]; +extern char _load_BOOT_EXEC_start_base[]; +extern char _loader_data_start_base[]; +#define _THUMB2 __attribute__((target("thumb"))) + +//--------------------------------------------------------------------------- +// Static function +//--------------------------------------------------------------------------- +/* + BL_RunPartOne + + Expend loader if use compress + + @return void +*/ +_THUMB2 static void BL_RunPartOne(void) +{ +#if (_LOADER_COMPRESSED_ == ENABLE) +#if (_PROCESS_2ND_CHECKSUM_ == 1) + NVTPACK_MEM mem = {0}; + UINT16 sum; + UINT16 src_sum; +#endif + UINT8 *in_addr = (UINT8 *)(_loader_exec_compress_load_cpu_addr); + UINT8 *out_addr = (UINT8 *)(_loader_exec_compres_start); + UINT32 uiCompressedOutSize; + + // Get decompress size within specific header + uiCompressedOutSize = (((UINT32)*(in_addr + 12)) << 24) + + (((UINT32)*(in_addr + 13)) << 16) + + (((UINT32)*(in_addr + 14)) << 8) + + ((UINT32)*(in_addr + 15)); + + // Decompress loader image +#if (_GZIP_ENABLE_API_ == 1) +#if (_PROCESS_2ND_CHECKSUM_ == 1) + *(UINT32 *)0xF0290000 = 'G'; +#endif + GZ_Uncompress((unsigned char *)(in_addr + LDC_HEADER_SIZE), (unsigned char *)(out_addr), uiCompressedOutSize); +#else +#if (_PROCESS_2ND_CHECKSUM_ == 1) + *(UINT32 *)0xF0290000 = 'L'; +#endif + LZ_Un_compress((unsigned char *)(in_addr + LDC_HEADER_SIZE), (unsigned char *)(out_addr), uiCompressedOutSize); +#endif +#if (_PROCESS_2ND_CHECKSUM_ == 1) + *(UINT32 *)0xF0290000 = 'Z'; +#endif + // Need to clean data cache + CPUInvalidateICacheAll(); +#if (_PROCESS_2ND_CHECKSUM_ == 1) + *(UINT32 *)0xF0290000 = 'I'; +#endif + CPUCleanInvalidateDCacheAll(); +#if (_PROCESS_2ND_CHECKSUM_ == 1) + *(UINT32 *)0xF0290000 = 'D'; +#endif + +#if (_PROCESS_2ND_CHECKSUM_ == 1) + // debug_msg_var("addr", (UINT32)(_load_BOOT_EXEC_start_base)); + mem.p_data = (void *)out_addr; + mem.len = *(UINT32 *)(_load_BOOT_EXEC_start_base + 0x1C); + src_sum = *(UINT16 *)(_load_BOOT_EXEC_start_base + 0x14); + sum = nvtpack_calc_nvt_sum(&mem); + if(src_sum == sum) { + debug_msg("\r\nCHKSUM UNZOK!"); + } else { + debug_msg_var("\r\nCHKSUM UNZNG!", sum); + debug_msg_var("calc_sum=",sum); + debug_msg_var(" bin_sum=",src_sum); + } +#else + debug_msg("\r\nUNZOK!"); +#endif +#else +#endif +} + +/* +void BL_PostHandle(void) +{ + UINT32 uiParamCnt; + UINT32 *pParamOffset; + UINT32 *pDramParam; + + pParamOffset = (UINT32*)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[5*4]); + pDramParam = (UINT32*)(*pParamOffset); + for (uiParamCnt=0; uiParamCnt < 7*2; uiParamCnt++) + { + OUTREG32(DDR_PARAM_LEVEL_0_ADDR + uiParamCnt*4, pDramParam[uiParamCnt]); + } + + // Disable IDE2 clock + CLRREG32(0xC0020070, 1<<17); + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); +} +*/ +_THUMB2 UINT32 main(void) +{ + UINT32 uiReturn; + UINT32 load_addr, target_addr, uitron_size; + UINT32 i; + UINT32 *pSrc, *pDst; + + perf_mark("main-b"); + + // Run part one loader + // If using compressed loader, just decompress the loader image at first! + BL_RunPartOne(); +#if (DDR_SCAN_REDUCE_CODE == ENABLE) + return 0; +#endif + + perf_mark("main-part1"); + + utl_dram_protect_enable((UINT32)_loader_exec_compres_start, (UINT32)(_loader_data_start_base - _loader_exec_compres_start)); + uiReturn = bl_mainFlow(); + utl_dram_protect_check(); + utl_dram_protect_disable(); + + bl_read_rtos_addr(&load_addr, &target_addr, &uitron_size); + if (load_addr != target_addr) { + printf("uitron target_addr=%08X\n", target_addr); + printf("uitron load_addr=%08X\n", load_addr); + uart_putSystemUARTStr("Copy from load to target by loader, this may has longer boot time\r\n"); + CPUflushReadCache(0, 128*1024); + CPUInvalidateICacheAll(); + +#if 1 + // disable MMU + { \ + __asm__ __volatile__( \ + "mrc p15, 0, r0, c1, c0, 0\n\t" \ + "bic r0, r0, #0x5\n\t" \ + "bic r0, r0, #0x1000\n\t" \ + "mcr p15, 0, r0, c1, c0, 0\n\t" \ + : \ + : \ + : "r0" \ + ); \ + } + asm volatile("dsb"); + asm volatile("isb"); + uart_putSystemUARTStr("disable MMU done\r\n"); +#endif + + pSrc = (UINT32*)load_addr; + pDst = (UINT32*)target_addr; + for (i=0; ipagesize = nvt_nand_ids[ui_nand_ids].pagesize; + pIdentify->erasesize= nvt_nand_ids[ui_nand_ids].erasesize; + pIdentify->qe_opt = nvt_nand_ids[ui_nand_ids].qe_opt; + pIdentify->plane_opt= nvt_nand_ids[ui_nand_ids].plane_opt; + nand_ids_found = TRUE; + break; + } + } + } + return nand_ids_found; +} diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c new file mode 100755 index 000000000000..257e1f850c81 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c @@ -0,0 +1,38 @@ +/* + * nand_ids.c + * + * nand id table + * + * Copyright (c) 2018 Novatek, ALL Rights Reserve + */ +#include "main.h" +#include "nor.h" +#include "constant.h" +#include "compiler.h" +#include "fuart.h" + +#define _THUMB2 __attribute__((target("thumb"))) + + +NOR_FLASH_DEV nvt_nor_ids[] = { + // manufactor ID device id capacity id flash size bus width + SPI_ID_NOR(0xEF, 0x40, 0x18, (16<<20), (SPI_BUSWIDTH_DUAL|SPI_BUSWIDTH_QUAD_TYPE2)), + SPI_ID_NOR(0xC8, 0x48, 0x1B, (16<<23), SPI_BUSWIDTH_OCTAL_TYPE1), // GD55X01GE, 8-bit +}; + +_THUMB2 BOOL nor_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + BOOL nor_ids_found = FALSE; + UINT32 ui_nor_ids; + for (ui_nor_ids = 0; ui_nor_ids < (sizeof(nvt_nor_ids) / sizeof(NOR_FLASH_DEV)); ui_nor_ids++) { + if (uiMfgID == nvt_nor_ids[ui_nor_ids].mfr_id && uiTypeID == nvt_nor_ids[ui_nor_ids].dev_id && uiCapacityID == nvt_nor_ids[ui_nor_ids].capacity_id) { + // For SPI Nor flash only + pIdentify->uiBusWidth = nvt_nor_ids[ui_nor_ids].uiBusWidth; + pIdentify->uiFlashSize = nvt_nor_ids[ui_nor_ids].uiFlashSize; + nor_ids_found = TRUE; + break; + } + } + + return nor_ids_found; +} diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/time_util.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/time_util.c new file mode 100755 index 000000000000..6dd3b82a03e5 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/time_util.c @@ -0,0 +1,69 @@ +#include "time_util.h" +#include "string.h" + +#define _THUMB2 __attribute__((target("thumb"))) +#define IS_LEAP_YEAR(year) ((((year % 4) == 0) && (((year % 100) != 0) || ((year % 400) == 0)))) + +_THUMB2 static int calc_month_day(int year, int month) +{ + int day = 31; + int year_ext = 0; + if (IS_LEAP_YEAR(year)) { + year_ext = 1; + } + if ((month == 4) || (month == 6) || (month == 9) || (month == 11)) { + day = 30; + } + if (month == 2) { + day = 28 + year_ext; + } + return day; +} + +_THUMB2 int time_util_add_sec(struct rtc_time *p_out, struct rtc_time *p_in, int sec) +{ + int maxday; + utl_memcpy(p_out, p_in, sizeof(struct rtc_time)); + + p_out->tm_sec += sec; /* seconds after the minute - [0,59] */ + + if (p_out->tm_sec >= 60) { + p_out->tm_min += p_out->tm_sec / 60; + p_out->tm_sec = p_out->tm_sec % 60; + } + if (p_out->tm_min >= 60) { + p_out->tm_hour += p_out->tm_min / 60; + p_out->tm_min = p_out->tm_min % 60; + } + if (p_out->tm_hour >= 24) { + p_out->tm_mday += p_out->tm_hour / 24; + p_out->tm_hour = p_out->tm_hour % 24; + } + maxday = calc_month_day(p_out->tm_year, p_out->tm_mon); + while (p_out->tm_mday > maxday) { + p_out->tm_mday -= maxday; + p_out->tm_mon ++; + //month range = [1,12] + if (p_out->tm_mon > 12) { + p_out->tm_year += (p_out->tm_mon - 1) / 12; + p_out->tm_mon = ((p_out->tm_mon - 1) % 12) + 1; + } + maxday = calc_month_day(p_out->tm_year, p_out->tm_mon); + } + //month range = [1,12] + if (p_out->tm_mon > 12) { + p_out->tm_year += (p_out->tm_mon - 1) / 12; + p_out->tm_mon = ((p_out->tm_mon - 1) % 12) + 1; + } + return 0; +} + +_THUMB2 int time_util_diff_sec(struct rtc_time *p_t2, struct rtc_time *p_t1) +{ + int day2 = calc_month_day(p_t2->tm_year, p_t2->tm_mon) + p_t2->tm_mday; + int day1 = calc_month_day(p_t1->tm_year, p_t1->tm_mon) + p_t1->tm_mday; + int sec2 = p_t2->tm_hour*60*60 + p_t2->tm_min*60 + p_t2->tm_sec; + int sec1 = p_t1->tm_hour*60*60 + p_t1->tm_min*60 + p_t1->tm_sec; + int diff = (day2-day1)*24*60*60 + (sec2-sec1); + return diff; +} \ No newline at end of file diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/time_util.h b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/time_util.h new file mode 100755 index 000000000000..47650c8a7a47 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/Ctrl_Flow/time_util.h @@ -0,0 +1,8 @@ +#ifndef _ADD_TIME_H +#define _ADD_TIME_H +#include "rtc.h" + +extern int time_util_add_sec(struct rtc_time *p_out, struct rtc_time *p_in, int sec); +extern int time_util_diff_sec(struct rtc_time *p_t2, struct rtc_time *p_t1); + +#endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/compress/Makefile b/board/novatek/ns02501/loader/LibExt/LIBExt_src/compress/Makefile new file mode 100755 index 000000000000..71e55b16f2f4 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/compress/Makefile @@ -0,0 +1,36 @@ + +#---------------------------------------------------------------------- +# set the library name here +#---------------------------------------------------------------------- +PRJ_NAME = Compress + +#---------------------------------------------------------------------- +# add/delete source files here +#---------------------------------------------------------------------- +SRC = \ + lz.c + +ASM = + +#---------------------------------------------------------------------- +# set the include directory here +#---------------------------------------------------------------------- +INC_DIR = . \ + ../../../Include + +#---------------------------------------------------------------------- +# set the image output directory here +#---------------------------------------------------------------------- +IMG_BASE_DIR = ../../../ARC/Lib + +#---------------------------------------------------------------------- +# add additional C and assembly flags here +#---------------------------------------------------------------------- +CFLAGS_R = +ASMFLAGS_R = + +#---------------------------------------------------------------------- +# include common parts of the makefile +#---------------------------------------------------------------------- +MAKE_COMMON_DIR = ../../../MakeCommon +include $(MAKE_COMMON_DIR)/OutputLib.txt diff --git a/board/novatek/ns02501/loader/LibExt/LIBExt_src/compress/lz.c b/board/novatek/ns02501/loader/LibExt/LIBExt_src/compress/lz.c new file mode 100755 index 000000000000..67b099787e38 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/LIBExt_src/compress/lz.c @@ -0,0 +1,682 @@ +/* + Decompress library source file + + Decompress library source file + + @file lz.c + @ingroup mISYSUtil + @note Nothing +*/ + +/************************************************************************* +* Name: lz.c +* Author: Marcus Geelnard +* Description: LZ77 coder/decoder implementation. +* Reentrant: Yes +* +* The LZ77 compression scheme is a substitutional compression scheme +* proposed by Abraham Lempel and Jakob Ziv in 1977. It is very simple in +* its design, and uses no fancy bit level compression. +* +* This is my first attempt at an implementation of a LZ77 code/decoder. +* +* The principle of the LZ77 compression algorithm is to store repeated +* occurrences of strings as references to previous occurrences of the same +* string. The point is that the reference consumes less space than the +* string itself, provided that the string is long enough (in this +* implementation, the string has to be at least 4 bytes long, since the +* minimum coded reference is 3 bytes long). Also note that the term +* "string" refers to any kind of byte sequence (it does not have to be +* an ASCII string, for instance). +* +* The coder uses a brute force approach to finding string matches in the +* history buffer (or "sliding window", if you wish), which is very, very +* slow. I recon the complexity is somewhere between O(n^2) and O(n^3), +* depending on the input data. +* +* There is also a faster implementation that uses a large working buffer +* in which a "jump table" is stored, which is used to quickly find +* possible string matches (see the source code for LZ_CompressFast() for +* more information). The faster method is an order of magnitude faster, +* but still quite slow compared to other compression methods. +* +* The upside is that decompression is very fast, and the compression ratio +* is often very good. +* +* The reference to a string is coded as a (length,offset) pair, where the +* length indicates the length of the string, and the offset gives the +* offset from the current data position. To distinguish between string +* references and literal strings (uncompressed bytes), a string reference +* is preceded by a marker byte, which is chosen as the least common byte +* symbol in the input data stream (this marker byte is stored in the +* output stream as the first byte). +* +* Occurrences of the marker byte in the stream are encoded as the marker +* byte followed by a zero byte, which means that occurrences of the marker +* byte have to be coded with two bytes. +* +* The lengths and offsets are coded in a variable length fashion, allowing +* values of any magnitude (up to 4294967295 in this implementation). +* +* With this compression scheme, the worst case compression result is +* (257/256)*insize + 1. +* +*------------------------------------------------------------------------- +* Copyright (c) 2003-2006 Marcus Geelnard +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would +* be appreciated but is not required. +* +* 2. Altered source versions must be plainly marked as such, and must not +* be misrepresented as being the original software. +* +* 3. This notice may not be removed or altered from any source +* distribution. +* +* Marcus Geelnard +* marcus.geelnard at home.se +*************************************************************************/ +#include "constant.h" + +#if (_GZIP_ENABLE_API_ == 1) +#include "Clock.h" +#include "timer.h" +#include "debug.h" +#include "Cache.h" +#include "nvtpack.h" + +#define GZIP_SETREG(ofs, value) OUTREG32(GZIP_REG_BASE_ADDR + (ofs),(value)) +#define GZIP_GETREG(ofs) INREG32(GZIP_REG_BASE_ADDR + ofs) + +#define GZIP_CTRL_REG_OFS 0x00 +#define GZIP_CFG_REG_OFS 0x04 +#define GZIP_INTEN_REG_OFS 0x10 +#define GZIP_INTSTS_REG_OFS 0x14 +#define GZIP_SRC_DMA_ADDRESS_REG_OFS 0x20 +#define GZIP_DST_DMA_ADDRESS_REG_OFS 0x28 +#define GZIP_SRC_SIZE_REG_OFS 0x30 +#define GZIP_DST_SIZE_REG_OFS 0x38 + +#define GZIP_EN (1<<0) +#define GZIP_TRIG (1<<1) +#define GZIP_DST_SIZE_LIMIT_EN (1<<2) + + +#else + +#endif +#include "lz.h" +/************************************************************************* +* Constants used for LZ77 coding +*************************************************************************/ +#if (_GZIP_ENABLE_API_ == 1) +__attribute__((target("thumb"))) unsigned int GZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize) +{ + UINT32 gz_size; + // check BFC's footer + UINT32 fourcc = *(UINT32 *)(in + insize - 4); + if (fourcc == MAKEFOURCC('F', 'O', 'O', 'T')) { + UINT8 padding_size = *(UINT8 *)(in + insize - 5); + insize -= padding_size; + } + + UINT32 uiReg; + enableGZReset(); + timer_delay(100); + disableGZReset(); + uiReg = INREG32(CLOCK_GEN_REG_BASE_ADDR + 0x28); + uiReg &= ~(GZ_CLOCK_RATE_MASK); + uiReg |= GZ_CLOCK_RATE_480_MHZ; + OUTREG32(CLOCK_GEN_REG_BASE_ADDR + 0x28, uiReg); + + enableGZClock(); + + GZIP_SETREG(GZIP_INTEN_REG_OFS, 0x00000000); + GZIP_SETREG(GZIP_INTSTS_REG_OFS, 0xFFFFFFFF); + + uiReg = GZIP_GETREG(GZIP_CTRL_REG_OFS); + uiReg |= GZIP_EN; + GZIP_SETREG(GZIP_CTRL_REG_OFS, uiReg); + + if ((UINT32)in & 0x3) { + debug_msg_var("in addr not word align", (UINT32)in); + } + if (((UINT32)in & 0xF0000000) == 0xF0000000) { + CLRREG32(DDR_CTRL_REG_BASE_ADDR + 0x8000 + 0x20, (1 << 26)); + CLRREG32(TOP_CTRL_REG_BASE_ADDR + 0x20, (0x3 << 20)); + SETREG32(TOP_CTRL_REG_BASE_ADDR + 0x20, (0x1 << 22)); + // dma_disableChannel(DMA_CH_GZIP); + // top_direct_mode_sel(FASTBOOT_DIRMODE_GZIP); + } else { + SETREG32(DDR_CTRL_REG_BASE_ADDR + 0x8000 + 0x20, (1 << 26)); + CLRREG32(TOP_CTRL_REG_BASE_ADDR + 0x20, (0x7 << 20)); + // dma_enableChannel(DMA_CH_GZIP); + // top_direct_mode_sel(FASTBOOT_DIRMODE_DISABLE); + } + + CPUflushWriteCache((UINT32)in, insize); + + //Out buffer need clean first + CPUflushWriteCache((UINT32)out, insize*3); + + GZIP_SETREG(GZIP_SRC_DMA_ADDRESS_REG_OFS, (UINT32)in); + GZIP_SETREG(GZIP_DST_DMA_ADDRESS_REG_OFS, (UINT32)out); + + GZIP_SETREG(GZIP_SRC_SIZE_REG_OFS, insize); + + // gzip_setConfig(GZIP_CFG_HEADER_DISABLE, gzip_info->bHeader_disable); + // gzip_setConfig(GZIP_CFG_FOOTER_DISABLE, gzip_info->bFooter_disable); + // gzip_setConfig(GZIP_CFG_IS1950, gzip_info->is1950); + // Header : disable + // Footer : disable + // is1950 : TRUE + GZIP_SETREG(GZIP_CFG_REG_OFS, 0x4); + + // Trigger + uiReg = GZIP_GETREG(GZIP_CTRL_REG_OFS); + uiReg |= GZIP_TRIG; + GZIP_SETREG(GZIP_CTRL_REG_OFS, uiReg); + + // Polling down + while (!(GZIP_GETREG(GZIP_INTSTS_REG_OFS) & (0x1 << 0))) + ; + + // gzip_platform_cache_sync_dma_to_dev(gzip_info->src_address, gzip_info->src_size); + + // gzip_setConfig(GZIP_CFG_TRIGGER, TRUE); + // gzip_platform_wai_flg(); + // gzip_close(); + + // gzip_platform_cache_sync_dma_from_dev(gzip_info->dst_address, GZIP_GETREG(GZIP_DST_SIZE_REG_OFS)); + gz_size = GZIP_GETREG(GZIP_DST_SIZE_REG_OFS); + CPUflushReadCache((UINT32)out, gz_size); + if (((UINT32)in & 0xF0000000) == 0xF0000000) { + SETREG32(DDR_CTRL_REG_BASE_ADDR + 0x8000 + 0x20, (1 << 26)); + CLRREG32(TOP_CTRL_REG_BASE_ADDR + 0x20, (0x3 << 20)); + } + + + + disableGZClock(); + + return gz_size; +} +#endif +/* Maximum offset (can be any size < 2^31). Lower values give faster + compression, while higher values gives better compression. The default + value of 100000 is quite high. Experiment to see what works best for + you. */ +#define LZ_MAX_OFFSET 100000 + +/** + @addtogroup mISYSUtil +*/ +//@{ + + + +/************************************************************************* +* INTERNAL FUNCTIONS * +*************************************************************************/ + + +/************************************************************************* +* _LZ_StringCompare() - Return maximum length string match. +*************************************************************************/ +#if 0 +static unsigned int _LZ_StringCompare( unsigned char * str1, + unsigned char * str2, unsigned int minlen, unsigned int maxlen ) +{ + unsigned int len; + + for( len = minlen; (len < maxlen) && (str1[len] == str2[len]); ++ len ); + + return len; +} +#endif + +/************************************************************************* +* _LZ_WriteVarSize() - Write unsigned integer with variable number of +* bytes depending on value. +*************************************************************************/ +#if 0 +static int _LZ_WriteVarSize( unsigned int x, unsigned char * buf ) +{ + unsigned int y; + int num_bytes, i, b; + + /* Determine number of bytes needed to store the number x */ + y = x >> 3; + for( num_bytes = 5; num_bytes >= 2; -- num_bytes ) + { + if( y & 0xfe000000 ) break; + y <<= 7; + } + + /* Write all bytes, seven bits in each, with 8:th bit set for all */ + /* but the last byte. */ + for( i = num_bytes-1; i >= 0; -- i ) + { + b = (x >> (i*7)) & 0x0000007f; + if( i > 0 ) + { + b |= 0x00000080; + } + *buf ++ = (unsigned char) b; + } + + /* Return number of bytes written */ + return num_bytes; +} +#endif + +/************************************************************************* +* _LZ_ReadVarSize() - Read unsigned integer with variable number of +* bytes depending on value. +*************************************************************************/ + +__attribute__((target("thumb"))) static UINT32 _LZ_ReadVarSize(UINT32 * x, UINT8 * buf ) +{ + UINT32 y, b, num_bytes; + + /* Read complete value (stop when byte contains zero in 8:th bit) */ + y = 0; + num_bytes = 0; + do + { + b = (UINT32) (*buf ++); + y = (y << 7) | (b & 0x0000007f); + ++ num_bytes; + } + while( b & 0x00000080 ); + + /* Store value in x */ + *x = y; + + /* Return number of bytes read */ + return num_bytes; +} + + + +/************************************************************************* +* PUBLIC FUNCTIONS * +*************************************************************************/ + + +/************************************************************************* +* LZ_Compress() - Compress a block of data using an LZ77 coder. +* in - Input (uncompressed) buffer. +* out - Output (compressed) buffer. This buffer must be 0.4% larger +* than the input buffer, plus one byte. +* insize - Number of input bytes. +* The function returns the size of the compressed data. +*************************************************************************/ +#if 0 +int LZ_Compress( unsigned char *in, unsigned char *out, + unsigned int insize ) +{ + unsigned char marker, symbol; + unsigned int inpos, outpos, bytesleft, i; + unsigned int maxoffset, offset, bestoffset; + unsigned int maxlength, length, bestlength; + unsigned int histogram[ 256 ]; + unsigned char *ptr1, *ptr2; + + /* Do we have anything to compress? */ + if( insize < 1 ) + { + return 0; + } + + /* Create histogram */ + for( i = 0; i < 256; ++ i ) + { + histogram[ i ] = 0; + } + for( i = 0; i < insize; ++ i ) + { + ++ histogram[ in[ i ] ]; + } + + /* Find the least common byte, and use it as the marker symbol */ + marker = 0; + for( i = 1; i < 256; ++ i ) + { + if( histogram[ i ] < histogram[ marker ] ) + { + marker = i; + } + } + + /* Remember the marker symbol for the decoder */ + out[ 0 ] = marker; + + /* Start of compression */ + inpos = 0; + outpos = 1; + + /* Main compression loop */ + bytesleft = insize; + do + { + /* Determine most distant position */ + if( inpos > LZ_MAX_OFFSET ) maxoffset = LZ_MAX_OFFSET; + else maxoffset = inpos; + + /* Get pointer to current position */ + ptr1 = &in[ inpos ]; + + /* Search history window for maximum length string match */ + bestlength = 3; + bestoffset = 0; + for( offset = 3; offset <= maxoffset; ++ offset ) + { + /* Get pointer to candidate string */ + ptr2 = &ptr1[ -(int)offset ]; + + /* Quickly determine if this is a candidate (for speed) */ + if( (ptr1[ 0 ] == ptr2[ 0 ]) && + (ptr1[ bestlength ] == ptr2[ bestlength ]) ) + { + /* Determine maximum length for this offset */ + maxlength = (bytesleft < offset ? bytesleft : offset); + + /* Count maximum length match at this offset */ + length = _LZ_StringCompare( ptr1, ptr2, 0, maxlength ); + + /* Better match than any previous match? */ + if( length > bestlength ) + { + bestlength = length; + bestoffset = offset; + } + } + } + + /* Was there a good enough match? */ + if( (bestlength >= 8) || + ((bestlength == 4) && (bestoffset <= 0x0000007f)) || + ((bestlength == 5) && (bestoffset <= 0x00003fff)) || + ((bestlength == 6) && (bestoffset <= 0x001fffff)) || + ((bestlength == 7) && (bestoffset <= 0x0fffffff)) ) + { + out[ outpos ++ ] = (unsigned char) marker; + outpos += _LZ_WriteVarSize( bestlength, &out[ outpos ] ); + outpos += _LZ_WriteVarSize( bestoffset, &out[ outpos ] ); + inpos += bestlength; + bytesleft -= bestlength; + } + else + { + /* Output single byte (or two bytes if marker byte) */ + symbol = in[ inpos ++ ]; + out[ outpos ++ ] = symbol; + if( symbol == marker ) + { + out[ outpos ++ ] = 0; + } + -- bytesleft; + } + } + while( bytesleft > 3 ); + + /* Dump remaining bytes, if any */ + while( inpos < insize ) + { + if( in[ inpos ] == marker ) + { + out[ outpos ++ ] = marker; + out[ outpos ++ ] = 0; + } + else + { + out[ outpos ++ ] = in[ inpos ]; + } + ++ inpos; + } + + return outpos; +} +#endif + +/************************************************************************* +* LZ_CompressFast() - Compress a block of data using an LZ77 coder. +* in - Input (uncompressed) buffer. +* out - Output (compressed) buffer. This buffer must be 0.4% larger +* than the input buffer, plus one byte. +* insize - Number of input bytes. +* work - Pointer to a temporary buffer (internal working buffer), which +* must be able to hold (insize+65536) unsigned integers. +* The function returns the size of the compressed data. +*************************************************************************/ +#if 0 +int LZ_CompressFast( unsigned char *in, unsigned char *out, + unsigned int insize, unsigned int *work ) +{ + unsigned char marker, symbol; + unsigned int inpos, outpos, bytesleft, i, index, symbols; + unsigned int offset, bestoffset; + unsigned int maxlength, length, bestlength; + unsigned int histogram[ 256 ], *lastindex, *jumptable; + unsigned char *ptr1, *ptr2; + + /* Do we have anything to compress? */ + if( insize < 1 ) + { + return 0; + } + + /* Assign arrays to the working area */ + lastindex = work; + jumptable = &work[ 65536 ]; + + /* Build a "jump table". Here is how the jump table works: + jumptable[i] points to the nearest previous occurrence of the same + symbol pair as in[i]:in[i+1], so in[i] == in[jumptable[i]] and + in[i+1] == in[jumptable[i]+1], and so on... Following the jump table + gives a dramatic boost for the string search'n'match loop compared + to doing a brute force search. The jump table is built in O(n) time, + so it is a cheap operation in terms of time, but it is expensice in + terms of memory consumption. */ + for( i = 0; i < 65536; ++ i ) + { + lastindex[ i ] = 0xffffffff; + } + for( i = 0; i < insize-1; ++ i ) + { + symbols = (((unsigned int)in[i]) << 8) | ((unsigned int)in[i+1]); + index = lastindex[ symbols ]; + lastindex[ symbols ] = i; + jumptable[ i ] = index; + } + jumptable[ insize-1 ] = 0xffffffff; + + /* Create histogram */ + for( i = 0; i < 256; ++ i ) + { + histogram[ i ] = 0; + } + for( i = 0; i < insize; ++ i ) + { + ++ histogram[ in[ i ] ]; + } + + /* Find the least common byte, and use it as the marker symbol */ + marker = 0; + for( i = 1; i < 256; ++ i ) + { + if( histogram[ i ] < histogram[ marker ] ) + { + marker = i; + } + } + + /* Remember the marker symbol for the decoder */ + out[ 0 ] = marker; + + /* Start of compression */ + inpos = 0; + outpos = 1; + + /* Main compression loop */ + bytesleft = insize; + do + { + /* Get pointer to current position */ + ptr1 = &in[ inpos ]; + + /* Search history window for maximum length string match */ + bestlength = 3; + bestoffset = 0; + index = jumptable[ inpos ]; + while( (index != 0xffffffff) && ((inpos - index) < LZ_MAX_OFFSET) ) + { + /* Get pointer to candidate string */ + ptr2 = &in[ index ]; + + /* Quickly determine if this is a candidate (for speed) */ + if( ptr2[ bestlength ] == ptr1[ bestlength ] ) + { + /* Determine maximum length for this offset */ + offset = inpos - index; + maxlength = (bytesleft < offset ? bytesleft : offset); + + /* Count maximum length match at this offset */ + length = _LZ_StringCompare( ptr1, ptr2, 2, maxlength ); + + /* Better match than any previous match? */ + if( length > bestlength ) + { + bestlength = length; + bestoffset = offset; + } + } + + /* Get next possible index from jump table */ + index = jumptable[ index ]; + } + + /* Was there a good enough match? */ + if( (bestlength >= 8) || + ((bestlength == 4) && (bestoffset <= 0x0000007f)) || + ((bestlength == 5) && (bestoffset <= 0x00003fff)) || + ((bestlength == 6) && (bestoffset <= 0x001fffff)) || + ((bestlength == 7) && (bestoffset <= 0x0fffffff)) ) + { + out[ outpos ++ ] = (unsigned char) marker; + outpos += _LZ_WriteVarSize( bestlength, &out[ outpos ] ); + outpos += _LZ_WriteVarSize( bestoffset, &out[ outpos ] ); + inpos += bestlength; + bytesleft -= bestlength; + } + else + { + /* Output single byte (or two bytes if marker byte) */ + symbol = in[ inpos ++ ]; + out[ outpos ++ ] = symbol; + if( symbol == marker ) + { + out[ outpos ++ ] = 0; + } + -- bytesleft; + } + } + while( bytesleft > 3 ); + + /* Dump remaining bytes, if any */ + while( inpos < insize ) + { + if( in[ inpos ] == marker ) + { + out[ outpos ++ ] = marker; + out[ outpos ++ ] = 0; + } + else + { + out[ outpos ++ ] = in[ inpos ]; + } + ++ inpos; + } + + return outpos; +} +#endif + +/** + LZ Uncompress + + Uncompress/decompress by LZ77 decoder + + @param[in] in Input buffer of compressed data + @param[out] out Output buffer to store decompressed data (Caller should maintain large enough buffer size to hold decompressed data) + @param[in] insize Length of input buffer in + + @return void +*/ +__attribute__((target("thumb"))) unsigned int LZ_Uncompress(UINT8 *in, UINT8 *out, + UINT32 insize ) +{ + UINT8 marker, symbol; + UINT32 i, inpos, outpos, length, offset; + + /* Do we have anything to uncompress? */ + if( insize < 1 ) + { + return 0; + } + + /* Get marker symbol from input stream */ + marker = in[ 0 ]; + inpos = 1; + + /* Main decompression loop */ + outpos = 0; + do + { + symbol = in[ inpos ++ ]; + if( symbol == marker ) + { + /* We had a marker byte */ + if( in[ inpos ] == 0 ) + { + /* It was a single occurrence of the marker byte */ + out[ outpos ++ ] = marker; + ++ inpos; + } + else + { + /* Extract true length and offset */ + inpos += _LZ_ReadVarSize( &length, &in[ inpos ] ); + inpos += _LZ_ReadVarSize( &offset, &in[ inpos ] ); + + /* Copy corresponding data from history window */ + for( i = 0; i < length; ++ i ) + { + out[ outpos ] = out[ outpos - offset ]; + ++ outpos; + } + } + } + else + { + /* No marker, plain copy */ + out[ outpos ++ ] = symbol; + } + } + while( inpos < insize ); + return outpos; +} +//#endif +//@} + diff --git a/board/novatek/ns02501/loader/LibExt/Makefile b/board/novatek/ns02501/loader/LibExt/Makefile new file mode 100755 index 000000000000..a768f07e0022 --- /dev/null +++ b/board/novatek/ns02501/loader/LibExt/Makefile @@ -0,0 +1,62 @@ +include ../MakeCommon/MakeOption.txt + +ifeq "$(shell uname)" "Linux" +MAKEFILE_SEARCH := $(sort $(dir $(shell find . -name 'Makefile'))) +else +MAKEFILE_SEARCH := $(sort $(dir $(shell find . -name \'Makefile\'))) +endif +mk_all := $(filter-out ./, $(MAKEFILE_SEARCH)) + +ifeq "$(ISOLATE_DEP)" "ON" +.PHONY: all $(mk_all) clean rebuild debug release dep + +all: + @make dep + @make debug + @make release +else +.PHONY: all $(mk_all) clean rebuild debug release + +all: rm_log $(mk_all) +endif + +$(mk_all): + @$(MAKE) --directory=$@ $(MAKECMDGOALS) + +rm_log: +ifeq "$(CLEAN_LOG)" "ON" + @-rm -f log*.txt +endif + +PRJ_NAME_ALL = $(shell find -name 'Makefile' -not -path "./Makefile" -print | xargs grep "PRJ_NAME" | sed 's/[[:digit:][:alpha:][:punct:]]*:PRJ_NAME[ ]*=[ ]*//g') +LIB_R = $(addprefix "../ARC/Lib/Release/", $(addsuffix ".a", $(PRJ_NAME_ALL))) +LIB_D = $(addprefix "../ARC/Lib/Debug/", $(addsuffix "_D.a", $(PRJ_NAME_ALL))) + +clean: + @-echo Clean LibExt ... \ + && find ./ -type d -name '*_Data' | xargs rm -rf --no-preserve-root $(LIB_D) $(LIB_R) log*.txt lint*.txt + +ifeq "$(ISOLATE_DEP)" "ON" +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: rm_log $(mk_all) +else +rebuild: rm_log $(mk_all) +endif + +debug: rm_log $(mk_all) + +release: rm_log $(mk_all) + +rm_lint_log: + @-rm -f lint*.txt + +lint: rm_lint_log $(mk_all) + +lintclean: + @-echo Clean LibExt lint data ... \ + && find ./ -type d -name 'CheckData' | xargs rm -rf --no-preserve-root lint*.txt \ No newline at end of file diff --git a/board/novatek/ns02501/loader/MakeCommon/InputSource.txt b/board/novatek/ns02501/loader/MakeCommon/InputSource.txt new file mode 100755 index 000000000000..631265678903 --- /dev/null +++ b/board/novatek/ns02501/loader/MakeCommon/InputSource.txt @@ -0,0 +1,177 @@ +#---------------------------------------------------------------------- +# get the source full path, convert upper case extension to lower case +#---------------------------------------------------------------------- +ifeq "$(shell uname)" "Linux" +SRC := $(addprefix $(shell pwd)/, $(SRC:.C=.c)) +ASM := $(addprefix $(shell pwd)/, $(ASM:.s=.S)) +CPP_SRC := $(addprefix $(shell pwd)/, $(CPP_SRC:.CPP=.cpp)) +else +SRC := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(SRC:.C=.c)) +ASM := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(ASM:.s=.S)) +CPP_SRC := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(CPP_SRC:.CPP=.cpp)) +endif + +#---------------------------------------------------------------------- +# set the basic include directories +#---------------------------------------------------------------------- +# Get working directory +MYPWD := $(shell pwd) +ALG_PATH := $(findstring /Alg/, $(MYPWD)) +APP_PATH := $(findstring /App/, $(MYPWD)) +APPEXT_PATH := $(findstring /AppExt/, $(MYPWD)) +LIB_PATH := $(findstring /Lib/, $(MYPWD)) +LIBEXT_PATH := $(findstring /LibExt/, $(MYPWD)) +DRV_PATH := $(findstring /Drv/, $(MYPWD)) +DRVEXT_PATH := $(findstring /DrvExt/, $(MYPWD)) +COM_PATH := $(findstring /Common/, $(MYPWD)) +UTIL_PATH := $(findstring /Common/Common_src/Utility, $(MYPWD)) +PRJ_PATH := $(shell find ./ -maxdepth 1 -name MakeConfig.txt) + +BASE_INC_DIR := $(filter %../../Include, $(INC_DIR)) +APPEXT_INC_DIR := -I$(BASE_INC_DIR)/AppExt +APP_INC_DIR := -I$(BASE_INC_DIR)/App +LIBEXT_INC_DIR := -I$(BASE_INC_DIR)/LibExt +LIB_INC_DIR := -I$(BASE_INC_DIR)/Lib +DRVEXT_INC_DIR := -I$(BASE_INC_DIR)/DrvExt +DRV_INC_DIR := -I$(BASE_INC_DIR)/Drv +LIBC_INC_DIR := -I$(BASE_INC_DIR)/Common/LibC + +#BASE_INC_ALG_DIR := $(BASE_INC_DIR)/../Alg/Include +#BASE_INC_PROTECT_DIR := $(subst Include,IncludeProtected,$(BASE_INC_DIR)) + +#change replace /Include/ to /IncludeProtected/ +define protected +$(subst ../../Include/,../../IncludeProtected/,$1) +endef + + +ifeq "$(USE_ECOS_KERNEL)" "ON" +#eCos include path like ThirdParty/eCos/Include ThirdParty/live555/Include +ECOS_INC_DIR := $(addprefix -I,$(addsuffix /include, $(shell find $(BASE_INC_DIR)/../ThirdParty/ -maxdepth 1 -mindepth 1 -type d))) +endif + +ifeq "$(shell uname)" "Linux" +INC_DIR := $(addprefix -I, $(sort $(dir $(shell find $(INC_DIR) -name '*.h')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_PROTECT_DIR) -name '*.h')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_ALG_DIR) -name '*.h')))) +else +INC_DIR := $(addprefix -I, $(sort $(dir $(shell find $(INC_DIR) -name \'\*\.h\')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_PROTECT_DIR) -name \'\*\.h\')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_ALG_DIR) -name \'\*\.h\')))) +endif + +# For uITRON (MIPS) platform, we use proprietary standard C library. +# We must filter out proprietary header file if we are in others platform (ARM or eCos...) +# Filter out standard C library header file +# ifeq "$(ARCH)" "ARM" +# INC_DIR := $(filter-out $(LIBC_INC_DIR)/%, $(INC_DIR)) +# endif + +ifeq "$(USE_ECOS_KERNEL)" "ON" + INC_DIR := $(filter-out $(LIBC_INC_DIR)/%, $(INC_DIR)) + INC_DIR += $(ECOS_INC_DIR) +endif + +ifeq "$(INCLUDE_RULE)" "ON" + +#---------------------------------------------------------------------- +# Filter out upper layer's include path +#---------------------------------------------------------------------- + + +# /Common can't access /App or /AppExt or /Lib or /LibExt or /Drv or /DrvExt +# except: /Common/Common_src/Utility can access /Drv +ifneq "$(COM_PATH)" "" +ifneq "$(UTIL_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)% $(DRVEXT_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%) $(call protected,$(DRVEXT_INC_DIR)%),$(INC_DIR)) +else +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)% $(DRVEXT_INC_DIR)% $(DRV_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%) $(call protected,$(DRVEXT_INC_DIR)%) $(call protected,$(DRV_INC_DIR)%),$(INC_DIR)) +endif +endif + +# /Drv can't access /App or /AppExt or /Lib or /LibExt +ifneq "$(DRV_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%),$(INC_DIR)) +endif + +# /DrvExt can't access /App or /AppExt or /Lib or /LibExt +ifneq "$(DRVEXT_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%), $(INC_DIR)) +endif + +# /Lib can't access /App or /AppExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%), $(INC_DIR)) +endif + +# /LibExt can't access /App or /AppExt +ifneq "$(LIBEXT_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%), $(INC_DIR)) +endif + +#---------------------------------------------------------------------- +# Filter out under layer's include path +#---------------------------------------------------------------------- + +# /App can't access /Drv +#ifneq "$(APP_PATH)" "" +#INC_DIR := $(filter-out $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +# /App can't access /DrvExt or /LibExt +ifneq "$(APP_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)% $(LIBEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /AppExt can't access /Drv +#ifneq "$(APPEXT_PATH)" "" +#INC_DIR := $(filter-out $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +# /Lib can't access /DrvExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /Prj can't access /Drv or /DrvExt +#ifneq "$(PRJ_PATH)" "" +#INC_DIR := $(filter-out $(DRVEXT_INC_DIR)% $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +ifneq "$(UI_STYLE)" "" +ifeq ($(filter $(UI_STYLE), $(UI_STYLE_ALL)),) +$(error add your style into $$UI_STYLE_ALL in MakeConfig.txt) +else +PRJ_FILT_OUT := $(filter-out $(UI_STYLE), $(UI_STYLE_ALL)) +endif +PRJ_FILT_OUT_DIR := $(addsuffix %,$(addprefix -I./SrcCode/UIWnd/, $(subst UI_STYLE_,,$(PRJ_FILT_OUT)))) +#INC_DIR := $(shell echo $(INC_DIR)|tr a-z A-Z) +INC_DIR := $(filter-out $(PRJ_FILT_OUT_DIR) , $(INC_DIR)) +endif + +#---------------------------------------------------------------------- +# Filter out external layer's include path +#---------------------------------------------------------------------- + +# /Drv can't access /DrvExt +ifneq "$(DRV_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /Lib can't access /LibExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(LIBEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /App can't access /AppExt +ifneq "$(APP_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)%, $(INC_DIR)) +endif + +endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/MakeCommon/MakeCommon.txt b/board/novatek/ns02501/loader/MakeCommon/MakeCommon.txt new file mode 100755 index 000000000000..8b3457f406d1 --- /dev/null +++ b/board/novatek/ns02501/loader/MakeCommon/MakeCommon.txt @@ -0,0 +1,680 @@ +#---------------------------------------------------------------------- +# Get the source full path, include directories +#---------------------------------------------------------------------- +# query SRC, ASM, INC_DIR +include $(MAKE_COMMON_DIR)/InputSource.txt + +#---------------------------------------------------------------------- +# set the basic ASM flags +# PLATFORM_AFLAGS := -march=armv7-a -mcpu=cortex-a9 -mabi=aapcs -msoft-float +# -mfloat-abi=softfp <==> -mfloat-abi=hard +#---------------------------------------------------------------------- +ifeq "$(FPU)" "hard" +PLATFORM_AFLAGS := -mcpu=$(CPU) -mfpu=neon -mfloat-abi=$(FPU) +else +PLATFORM_AFLAGS := -mcpu=$(CPU) -mfloat-abi=$(FPU) +endif + + + +#---------------------------------------------------------------------- +# set the basic C flags +# Reference +# http://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/ +# http://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/Option-Summary.html#Option-Summary +#---------------------------------------------------------------------- +#---------------------------------------------------------------------- +# Overall Options +#---------------------------------------------------------------------- +# -c : Compile the source files, but do not link +# -pipe : Use pipes rather than temporary files for communication between the various stages of compilation +PLATFORM_CFLAGS := -c -pipe + +#---------------------------------------------------------------------- +# Machine Dependent Options +#---------------------------------------------------------------------- +# -march=24kec : Generate code that will run on MIPS 24KEc +# -mtune=24kec : Optimize for MIPS 24KEc +# -mdsp : Use revision 1 of the MIPS DSP ASE +# -EL : Generate little-endian code +# -msoft-float : Do not use floating-point coprocessor instructions +# -marm : Tell compiler do not build c code as thumb2 instruction +#---------------------------------------------------------------------- +ifeq "$(USE_NEON)" "on" +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=softfp -mfpu=neon-fp-armv8 -ftree-vectorize +else +ifeq "$(FPU)" "hard" +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=$(FPU) -mfpu=neon -ftree-vectorize +else +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=$(FPU) +endif +endif +# PLATFORM_CFLAGS += -mtune=$(CPU) -march=armv7-a -marm -mhard-float -mfpu=neon-vfpv4 -mno-thumb-interwork -mno-sched-prolog +# PLATFORM_CFLAGS += -mtune=$(CPU) -march=armv7-a -marm -msoft-float -mno-thumb-interwork -mno-sched-prolog + +#---------------------------------------------------------------------- +# Warning Options +#---------------------------------------------------------------------- +# -Wall : This enables all the warnings about constructions that some users consider questionable, +# and that are easy to avoid (or modify to prevent the warning), even in conjunction with macros. +# NOTE: -Wall turns on the following warning flags: +# -Waddress +# -Warray-bounds (only with -O2) +# -Wc++11-compat +# -Wchar-subscripts +# -Wenum-compare (in C/ObjC; this is on by default in C++) +# -Wimplicit-int (C and Objective-C only) +# -Wimplicit-function-declaration (C and Objective-C only) +# -Wcomment +# -Wformat +# -Wmain (only for C/ObjC and unless -ffreestanding) +# -Wmaybe-uninitialized +# -Wmissing-braces (only for C/ObjC) +# -Wnonnull +# -Wparentheses +# -Wpointer-sign +# -Wreorder +# -Wreturn-type +# -Wsequence-point +# -Wsign-compare (only in C++) +# -Wstrict-aliasing +# -Wstrict-overflow=1 +# -Wswitch +# -Wtrigraphs +# -Wuninitialized +# -Wunknown-pragmas +# -Wunused-function +# -Wunused-label +# -Wunused-value +# -Wunused-variable +# -Wvolatile-register-var +# -Wundef : Warn if an undefined identifier is evaluated in an `#if' directive +# -Wsign-compare : Warn when a comparison between signed and unsigned values could produce an incorrect result when the signed value is converted to unsigned +# -Wno-missing-braces : Trun off "Warn if an aggregate or union initializer is not fully bracketed". For XXX = {0}; statement. +# -Wstrict-prototypes : Warn if a function is declared or defined without specifying the argument types +# -Wimplicit-function-declaration : Warn when a function is used before being declared +# -Wmissing-prototypes : Warn about global funcs without prototypes +# -Wmissing-declarations: Warn about global funcs without previous declarations +# -Werror : Warnning as error +#---------------------------------------------------------------------- +PLATFORM_CFLAGS += -Wall -Wundef -Wsign-compare -Wno-missing-braces -Wstrict-prototypes -Wno-unused-const-variable -Wno-misleading-indentation +ifeq "$(OUTPUT_FILE)" "BIN" +else +ifeq "$(INCLUDE_RULE)" "ON" +# PLATFORM_CFLAGS += -Werror=implicit-function-declaration -Werror=missing-prototypes -Werror=missing-declarations + PLATFORM_CFLAGS += -Wimplicit-function-declaration -Wmissing-prototypes -Wmissing-declarations +endif +endif + +ifeq "$(shell uname)" "Linux" +PLATFORM_CFLAGS += -Werror +endif + +#---------------------------------------------------------------------- +# C Language Options +#---------------------------------------------------------------------- +# -fno-builtin : Don't recognize built-in functions that do not begin with `__builtin_' as prefix +# -ffreestanding: Assert that compilation takes place in a freestanding environment +#---------------------------------------------------------------------- +# Code Generation Options +#---------------------------------------------------------------------- +# -fno-common : The compiler should place uninitialized global variables in the data section of the object file, rather than generating them as common blocks +# -fshort-wchar : Override the underlying type for `wchar_t' to be `short unsigned int' instead of the default for the target. +#---------------------------------------------------------------------- +# Optimization Options +#---------------------------------------------------------------------- +# -fno-strict-aliasing : Do not warn about code that breaks strict aliasing rules +# -fno-optimize-sibling-calls : Don't optimize sibling and tail recursive calls +# -fno-omit-frame-pointer : Keep the frame pointer in a register for functions that don't need one +#---------------------------------------------------------------------- +PLATFORM_CFLAGS += -fno-builtin -ffreestanding -fno-common -fshort-enums -fshort-wchar -fno-strict-aliasing -fno-optimize-sibling-calls -fno-omit-frame-pointer + +# C Language Options for eCos system +ifeq "$(USE_ECOS_KERNEL)" "ON" + PLATFORM_CFLAGS += -D__ECOS +else + PLATFORM_CFLAGS += -nostdinc -D__UITRON +# For make dep + GCCFLAGS +=-D__UITRON +endif + +# Remove -Otime (There is no such option in GCC, GCC default is optimize for time) +# Replace -OSpace (-Os in GCC) +CFLAGS_D := $(filter-out -Otime, $(CFLAGS_D)) +CFLAGS_D := $(CFLAGS_D:-Ospace=-Os) +CFLAGS_R := $(filter-out -Otime, $(CFLAGS_R)) +CFLAGS_R := $(CFLAGS_R:-Ospace=-Os) + +# Slove sub-folder cannot include parent folder header file +INC_DIR += -I$(CURDIR) + +# For Debug target +CFLAGS_D += $(INC_DIR) -g -ggdb -O0 $(PLATFORM_CFLAGS) +ASMFLAGS_D += -g $(INC_DIR) $(PLATFORM_AFLAGS) -D__ASSEMBLY__ + +# For Release target (use -Os instead of -O2, because loader is size dominant) +CFLAGS_R += $(INC_DIR) -Os $(PLATFORM_CFLAGS) +ASMFLAGS_R += $(INC_DIR) $(PLATFORM_AFLAGS) -D__ASSEMBLY__ + +# Generate debug symbol in release target +ifeq "$(RELEASE_SYMBOL)" "ON" + CFLAGS_R += -g -ggdb + ASMFLAGS_R += -L -g +endif + +# Generate debug callback of entry and exit to functions +ifeq "$(INSTRUMENT_FUNCTION)" "ON" + CFLAGS_R += -finstrument-functions -finstrument-functions-exclude-file-list=Common_src/LibC,Common_src/Kernel,Common_src/Debug,Common_src/OS,Include/Common/LibC,Include/Common/Kernel,Include/Common/Debug,Include/Common/OS,Drv_src/Driver,Include/Drv/Driver + CFLAGS_D += -finstrument-functions -finstrument-functions-exclude-file-list=Common_src/LibC,Common_src/Kernel,Common_src/Debug,Common_src/OS,Include/Common/LibC,Include/Common/Kernel,Include/Common/Debug,Include/Common/OS,Drv_src/Driver,Include/Drv/Driver + CFLAGS_R += -D_INSTRUMENT_FUNCTION_=1 + CFLAGS_D += -D_INSTRUMENT_FUNCTION_=1 +else + CFLAGS_R += -D_INSTRUMENT_FUNCTION_=0 + CFLAGS_D += -D_INSTRUMENT_FUNCTION_=0 +endif + +#---------------------------------------------------------------------- +# Generate one ELF section for each function +# Only apply to release target +# Note: -fdata-sections will generate larger code size +#---------------------------------------------------------------------- +ifeq "$(SECTION_BY_FUNC)" "ON" +# CFLAGS_R += -ffunction-sections -fdata-sections + CFLAGS_R += -ffunction-sections +endif + +#---------------------------------------------------------------------- +# Definition for source code check build debug or release +#---------------------------------------------------------------------- +CFLAGS_R += -DNDEBUG +CFLAGS_D += -D_DEBUG + +#---------------------------------------------------------------------- +# FPGA notification for drivers +#---------------------------------------------------------------------- +ifeq "$(EMULATION)" "ON" + ifeq "$(FPGA_EMULATION)" "ON" + CFLAGS_R += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + CFLAGS_D += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + GCCFLAGS += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + ASMFLAGS_R += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 + ASMFLAGS_D += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 + else + CFLAGS_R += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + CFLAGS_D += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + GCCFLAGS += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + ASMFLAGS_R += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + ASMFLAGS_D += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + endif +else + CFLAGS_R += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 + CFLAGS_D += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 + GCCFLAGS += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 + ASMFLAGS_R += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 + ASMFLAGS_D += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 +endif + +#---------------------------------------------------------------------- +# PM demo based on customized building way +#---------------------------------------------------------------------- +ifeq "$(PM_DEMO)" "ON" + CFLAGS_R += -D_PM_DEMO_=1 + CFLAGS_D += -D_PM_DEMO_=1 +else + CFLAGS_R += -D_PM_DEMO_=0 + CFLAGS_D += -D_PM_DEMO_=0 +endif + +#---------------------------------------------------------------------- +# GIC usage ON/OFF +#---------------------------------------------------------------------- +ifeq "$(ARM_GIC_400)" "ON" + CFLAGS_R += -D_ARM_GIC_USAGE_=1 + CFLAGS_D += -D_ARM_GIC_USAGE_=1 + ASMFLAGS_R += -D_ARM_GIC_USAGE_=1 + ASMFLAGS_D += -D_ARM_GIC_USAGE_=1 +else + CFLAGS_R += -D_ARM_GIC_USAGE_=0 + CFLAGS_D += -D_ARM_GIC_USAGE_=0 + ASMFLAGS_R += -D_ARM_GIC_USAGE_=0 + ASMFLAGS_D += -D_ARM_GIC_USAGE_=0 +endif + +#---------------------------------------------------------------------- +# Architecture definition +#---------------------------------------------------------------------- +CFLAGS_R += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 +CFLAGS_D += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 +GCCFLAGS += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 + +ifeq "$(ARCH)" "ARM" + CFLAGS_R += -D_ARCH_=_ARCH_ARM_ + CFLAGS_D += -D_ARCH_=_ARCH_ARM_ + GCCFLAGS += -D_ARCH_=_ARCH_ARM_ +else ifeq "$(ARCH)" "MIPS" + CFLAGS_R += -D_ARCH_=_ARCH_MIPS_ + CFLAGS_D += -D_ARCH_=_ARCH_MIPS_ + GCCFLAGS += -D_ARCH_=_ARCH_MIPS_ +endif + +ifeq "$(FPU)" "hard" +ASMFLAGS_D += -D_NEON_ON_=1 +ASMFLAGS_R += -D_NEON_ON_=1 +else +ASMFLAGS_D += -D_NEON_ON_=0 +ASMFLAGS_R += -D_NEON_ON_=0 +endif + +#---------------------------------------------------------------------- +# ROM Public API usage +#---------------------------------------------------------------------- +ifeq "$(ROM_PUBLIC_API)" "ON" + CFLAGS_R += -D_ROM_PUBLIC_API_=1 + CFLAGS_D += -D_ROM_PUBLIC_API_=1 + ASMFLAGS_R+= -D_ROM_PUBLIC_API_=1 + ASMFLAGS_D+= -D_ROM_PUBLIC_API_=1 +else + CFLAGS_R += -D_ROM_PUBLIC_API_=0 + CFLAGS_D += -D_ROM_PUBLIC_API_=0 + ASMFLAGS_R+= -D_ROM_PUBLIC_API_=0 + ASMFLAGS_D+= -D_ROM_PUBLIC_API_=0 +endif + +ifeq "$(GZIP_ENGINE_API)" "ON" + CFLAGS_R += -D_GZIP_ENABLE_API_=1 + CFLAGS_D += -D_GZIP_ENABLE_API_=1 + ASMFLAGS_R+= -D_GZIP_ENABLE_API_=1 + ASMFLAGS_D+= -D_GZIP_ENABLE_API_=1 +else + CFLAGS_R += -D_GZIP_ENABLE_API_=0 + CFLAGS_D += -D_GZIP_ENABLE_API_=0 + ASMFLAGS_R+= -D_GZIP_ENABLE_API_=0 + ASMFLAGS_D+= -D_GZIP_ENABLE_API_=0 +endif + +#---------------------------------------------------------------------- +# 2nd checksum usage +#---------------------------------------------------------------------- +ifeq "$(PROCESS_2ND_CHECKSUM)" "ON" + CFLAGS_R += -D_PROCESS_2ND_CHECKSUM_=1 + CFLAGS_D += -D_PROCESS_2ND_CHECKSUM_=1 + ASMFLAGS_R+= -D_PROCESS_2ND_CHECKSUM_=1 + ASMFLAGS_D+= -D_PROCESS_2ND_CHECKSUM_=1 +else + CFLAGS_R += -D_PROCESS_2ND_CHECKSUM_=0 + CFLAGS_D += -D_PROCESS_2ND_CHECKSUM_=0 + ASMFLAGS_R+= -D_PROCESS_2ND_CHECKSUM_=0 + ASMFLAGS_D+= -D_PROCESS_2ND_CHECKSUM_=0 +endif + +#---------------------------------------------------------------------- +# Definition from environment +#---------------------------------------------------------------------- +ifeq "$(NMAKE_DEF)" "" +CFLAGS_R += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +CFLAGS_D += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +else +CFLAGS_R += $(NMAKE_DEF) +CFLAGS_D += $(NMAKE_DEF) +endif +ifeq "$(NMAKE_DEF_ASM)" "" +ASMFLAGS_R += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +ASMFLAGS_D += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +else +ASMFLAGS_R += $(NMAKE_DEF_ASM) +ASMFLAGS_D += $(NMAKE_DEF_ASM) +endif +#---------------------------------------------------------------------- +# Set image base directory according to kernel type +# eCos : /ARC +# uITRON : /ARC_eCos +#---------------------------------------------------------------------- +ifeq "$(USE_ECOS_KERNEL)" "ON" + ifeq "$(OUTPUT_FILE)" "LIB" + # This is for library, project's image base directory is $(PRJ_NAME)_Data + # IMG_BASE_DIR looks like ../../ARC/Common (There is backslash succeeding to /ARC) + IMG_BASE_DIR := $(subst /ARC/,/ARC_eCos/,$(IMG_BASE_DIR)) + endif + ifeq "$(OUTPUT_FILE)" "BIN" + # This is for project, library doesn't have this variable + # ARC_BASE_DIR looks like ../../ARC (There is No backslash succeeding to /ARC) + ARC_BASE_DIR := $(subst /ARC,/ARC_eCos,$(ARC_BASE_DIR)) + endif + KERNEL_STR := eCos +else + KERNEL_STR := uITRON +endif + +#---------------------------------------------------------------------- +# Set branched project name +#---------------------------------------------------------------------- +ifneq "$(_BRANCH_PROJECT_)" "" + CFLAGS_R += -D_PROJECT_CODE_=$(_BRANCH_PROJECT_) + CFLAGS_D += -D_PROJECT_CODE_=$(_BRANCH_PROJECT_) +endif + +#---------------------------------------------------------------------- +# Set the directory for debug/release objects and images here +#---------------------------------------------------------------------- +OBJ_DEBUG = $(PRJ_NAME)_Data/Debug/ObjectCode +OBJ_RELEASE = $(PRJ_NAME)_Data/Release/ObjectCode +IMG_DEBUG = $(IMG_BASE_DIR)/Debug +IMG_RELEASE = $(IMG_BASE_DIR)/Release + + +#---------------------------------------------------------------------- +# Filter the GCC Command Options for debug/release mode +#---------------------------------------------------------------------- +FILTER_GCC_D = $(foreach v, $(CFLAGS_D), $(if $(findstring -D, $(v)), , $(v))) +GCC_OPT_D = $(filter-out $(INC_DIR), $(FILTER_GCC_D)) +FILTER_GCC_R = $(foreach v, $(CFLAGS_R), $(if $(findstring -D, $(v)), , $(v))) +GCC_OPT_R = $(filter-out $(INC_DIR), $(FILTER_GCC_R)) + + +#---------------------------------------------------------------------- +# Set the make outputs +#---------------------------------------------------------------------- +SRC_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(SRC:.c=.o))) +ASM_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(ASM:.S=.o))) +CPP_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(CPP_SRC:.cpp=.o))) +ALL_OBJ_D := $(ASM_OBJ_D) $(SRC_OBJ_D) $(CPP_OBJ_D) +DEPFILE_D := $(subst .o,.d,$(ALL_OBJ_D)) + +SRC_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(SRC:.c=.o))) +ASM_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(ASM:.S=.o))) +CPP_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(CPP_SRC:.cpp=.o))) +ALL_OBJ_R := $(ASM_OBJ_R) $(SRC_OBJ_R) $(CPP_OBJ_R) +DEPFILE_R := $(subst .o,.d,$(ALL_OBJ_R)) + +ifeq "$(ISOLATE_DEP)" "ON" + ALL_DEP := $(DEPFILE_D) $(DEPFILE_R) +endif + +LINT_ROOTDIR = $(PRJ_NAME)_Lint +LINT_DIR = $(PRJ_NAME)_Lint/LintData +LINT_FILE := $(addprefix $(LINT_DIR)/, $(notdir $(SRC:.c=.lob))) + +#---------------------------------------------------------------------- +# For dependency +#---------------------------------------------------------------------- +GCCFLAGS += $(INC_DIR) -c -w + +#---------------------------------------------------------------------- +# For coding rule +#---------------------------------------------------------------------- +PCLINTFLAGS = $(PCLINT_PARAMETER) $(C_DEFINE_EXT) $(INC_DIR) -i$(MAKE_COMMON_DIR)/LintRule std.lnt options.lnt $$(lintopt_file) + +#---------------------------------------------------------------------- +# define host environment is linux if we build on linux server +#---------------------------------------------------------------------- +ifeq ($(OS),Linux) +CFLAGS_R += -D_HOST_ENV_LINUX_ +CFLAGS_D += -D_HOST_ENV_LINUX_ +GCCFLAGS += -D_HOST_ENV_LINUX_ +endif + +#---------------------------------------------------------------------- +# CPP FLAGS derived from CFLAGS_R / CFLAGS_D +#---------------------------------------------------------------------- +CPPFLAGS_R = $(filter-out -Wstrict-prototypes -Wimplicit-function-declaration -Wmissing-prototypes, $(CFLAGS_R)) +CPPFLAGS_D = $(filter-out -Wstrict-prototypes -Wimplicit-function-declaration -Wmissing-prototypes, $(CFLAGS_D)) + +#---------------------------------------------------------------------- +# Set the make targets +#---------------------------------------------------------------------- +build_all: rm_log build_D build_R + +make_debug_begin: + @-echo \ + && echo Checking $(KERNEL_STR) - $(basename $(notdir $(IMAGE_D))) debug target ... \ + && mkdir -p $(IMG_DEBUG) $(OBJ_DEBUG) + +make_release_begin: + @-echo \ + && echo Checking $(KERNEL_STR) - $(basename $(notdir $(IMAGE_R))) release target ... \ + && mkdir -p $(IMG_RELEASE) $(OBJ_RELEASE) + +make_dep_begin: + @-echo Checking $(basename $(notdir $(IMAGE_R))) dependency ... \ + && mkdir -p $(OBJ_DEBUG) $(OBJ_RELEASE) + +make_lint_begin: + @-echo Checking \"$(basename $(notdir $(IMAGE_R)))\" with coding rules ... \ + && mkdir -p $(LINT_DIR) + +make_option_begin: + @-echo [GCC Command Options - Release] + @-echo $(GCC_OPT_R) + @-echo + @-echo [GCC Command Options - Debug ] + @-echo $(GCC_OPT_D) + +#---------------------------------------------------------------------- +# Compile rule functions +#---------------------------------------------------------------------- +BUILD_DATE = 20`date +'%y%m%d'` +ifeq "$(ISOLATE_DEP)" "ON" + + # $(call compile_rule,object,source,cflags) + define compile_rule + $1: $2 + @echo Compiling $(notdir $2)\ + && $(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_asm,object,source,asmflags) + define compile_rule_asm + $1: $2 + @echo Compiling $(notdir $2) \ + && $(CC) $(PLATFORM_AFLAGS) -c $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_cpp,object,source,cflags) + define compile_rule_cpp + $1: $2 + @echo Compiling $(notdir $2) \ + && $(CXX) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + +else + + # $(call compile_rule,object,source,cflags) + define compile_rule + $1: $2 + @-$(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_asm,object,source,asmflags) + define compile_rule_asm + $1: $2 + @-$(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_cpp,object,source,cflags) + define compile_rule_cpp + $1: $2 + @-$(CXX) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CXX) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + +endif + +# $(call get_obj,obj_dir,source) +get_obj = $(addprefix $1/, $(subst .c,.o,$(notdir $2))) + +# $(call get_obj_asm,obj_dir,source) +get_obj_asm = $(addprefix $1/, $(subst .S,.o,$(notdir $2))) + +# $(call get_obj,obj_dir,source) +get_obj_cpp = $(addprefix $1/, $(subst .cpp,.o,$(notdir $2))) + +# $(call compile_all,obj_dir,cflags) +define compile_all +$(foreach i, $(SRC), \ + $(call compile_rule,$(call get_obj,$1,$i),$i,$2)) +endef + +# $(call compile_all_asm,obj_dir,asmflags) +define compile_all_asm +$(foreach i, $(ASM), \ + $(call compile_rule_asm,$(call get_obj_asm,$1,$i),$i,$2)) +endef + +# $(call compile_all_cpp,obj_dir,cflags) +define compile_all_cpp +$(foreach i, $(CPP_SRC), \ + $(call compile_rule_cpp,$(call get_obj_cpp,$1,$i),$i,$2)) +endef + +#----------------------------------------------------------------- +# Dependency rule functions +#----------------------------------------------------------------- +# $(call depend_rule,depend,source) +define depend_rule +$1: $2 + @echo Depending $(notdir $2) \ + && $(GCC) -MM -MF $1 -MP -MT $(basename $1).o $(GCCFLAGS) $2 \ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) + +endef + +define depend_rule_asm +$1: $2 + @echo Depending $(notdir $2) \ + && $(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) \ + && rm -f $(basename $1).o + +endef + +define depend_rule_cpp +$1: $2 + @echo Depending $(notdir $2) \ + && $(CXX) -MM -MF $1 -MP -MT $(basename $1).o $(GCCFLAGS) $2\ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) + +endef + +# $(call get_dep,dep_dir,source) +get_dep = $(addprefix $1/, $(subst .c,.d,$(notdir $2))) + +# $(call get_dep_asm,dep_dir,source) +get_dep_asm = $(addprefix $1/, $(subst .S,.d,$(notdir $2))) + +# $(call get_dep_cpp,dep_dir,source) +get_dep_cpp = $(addprefix $1/, $(subst .cpp,.d,$(notdir $2))) + +define depend_all +$(foreach i, $(SRC), \ + $(call depend_rule,$(call get_dep,$1,$i),$i)) +endef + +# $(call dep_all_asm,dep_dir) +define depend_all_asm +$(foreach i, $(ASM), \ + $(call depend_rule_asm,$(call get_dep_asm,$1,$i),$i)) +endef + +define depend_all_cpp +$(foreach i, $(CPP_SRC), \ + $(call depend_rule_cpp,$(call get_dep_cpp,$1,$i),$i)) +endef + +#---------------------------------------------------------------------- +# LINT rule functions +#---------------------------------------------------------------------- +# $(call get_lint,lint_dir,source) +get_lint = $(addprefix $1/, $(subst .c,.lob,$(notdir $2))) + +# $(call lint_rule,output,source) +define lint_rule +$1: $2 + @-echo Review $(notdir $2) \ + && $(LT) $(PCLINTFLAGS) -u -zero -oo[$1] $2 >> $$(lint_file) + +endef + +# && $(LT) $(PCLINTFLAGS) $2 >> $$(lint_file) + +define lint_all +$1: +$(foreach i, $(SRC), \ + $(call lint_rule,$(call get_lint,$1,$i),$i)) + @-echo Review \(Internal Relation\) \ + && $(LT) $(PCLINTFLAGS) $(LINT_DIR)/"*.lob" >> $$(lint_file) + -rm -rf --no-preserve-root $(LINT_ROOTDIR) + +endef + +#---------------------------------------------------------------------- +# Goals +#---------------------------------------------------------------------- +ifeq "$(ISOLATE_DEP)" "ON" + + ifeq "$(MAKECMDGOALS)" "dep" + $(eval $(call depend_all,$(OBJ_RELEASE))) + $(eval $(call depend_all_asm,$(OBJ_RELEASE))) + $(eval $(call depend_all_cpp,$(OBJ_RELEASE))) + $(eval $(call depend_all,$(OBJ_DEBUG))) + $(eval $(call depend_all_asm,$(OBJ_DEBUG))) + $(eval $(call depend_all_cpp,$(OBJ_DEBUG))) + endif + + ifeq "$(MAKECMDGOALS)" "" + .DEFAULT_GOAL := all + endif + +else + + ifeq "$(MAKECMDGOALS)" "" + -include $(DEPFILE_D) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) + endif + + ifeq "$(MAKECMDGOALS)" "rebuild" + -include $(DEPFILE_D) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) + endif + +endif + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),debug build_pipe_D)) + -include $(DEPFILE_D) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) +endif + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),release build_pipe_R)) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) +endif + +ifeq "$(MAKECMDGOALS)" "lint" + $(eval $(call lint_all,$(LINT_DIR))) +endif diff --git a/board/novatek/ns02501/loader/MakeCommon/MakeOption.txt b/board/novatek/ns02501/loader/MakeCommon/MakeOption.txt new file mode 100755 index 000000000000..03d273ff0cb7 --- /dev/null +++ b/board/novatek/ns02501/loader/MakeCommon/MakeOption.txt @@ -0,0 +1,307 @@ +ifeq "$(OPTION_LOADED)" "" + +#---------------------------------------------------------------------- +# Set option file loaded +#---------------------------------------------------------------------- +export OPTION_LOADED := TRUE + +#---------------------------------------------------------------------- +# Set the target CPU architecture +# +# ARM : ARM CPU +# MIPS : MIPS CPU (24KEc) +#---------------------------------------------------------------------- +export ARCH := ARM +#export ARCH := MIPS + +#---------------------------------------------------------------------- +# Set the toolchain +# +# ARM : ARM ADS, RealView +# GNU : GNU C, ASM and linker +#---------------------------------------------------------------------- +#export TOOLCHAIN := ARM +export TOOLCHAIN := GNU + +#---------------------------------------------------------------------- +# Set the floating point +# +# SW/HW : soft or hard float point unit +#---------------------------------------------------------------------- +#export FPU := hard +export FPU := soft + +#---------------------------------------------------------------------- +# Set the CPU type +# +# cortex-a9 or a53 +#---------------------------------------------------------------------- +export CPU := cortex-a7 +#export CPU := cortex-a53 + + +#---------------------------------------------------------------------- +# Set branched project code +# +# The project code must be 4 characters, please refer to +# http://mynvt.novatek.com.tw/deptsites/IM/Shared%20Documents/VersionControl.doc +# for more detailed information. +# Leaves this variable empty if not branched yet. +#---------------------------------------------------------------------- +export _BRANCH_PROJECT_ := + +#---------------------------------------------------------------------- +# PClint parameters +#---------------------------------------------------------------------- +export PCLINT_PARAMETER := -b -v + +#---------------------------------------------------------------------- +# Set log file option +# +# ON : Save warning/error message to log files (Win32 Default) +# OFF : Just output warning/error message to stdout (Linux Default) +#---------------------------------------------------------------------- +ifeq "$(shell uname)" "Linux" +export LOG_ERR := OFF +else +export LOG_ERR := ON +endif + +#---------------------------------------------------------------------- +# Set clean log file option +# +# ON : Clean log files before make +# OFF : Don't clean log files before make +# (You should execute "make clean" to clean the log files) +#---------------------------------------------------------------------- +export CLEAN_LOG := ON +#export CLEAN_LOG := OFF + +#---------------------------------------------------------------------- +# Keep going when encounter error or not +# +# ON : Make will keep going when encounter error +# OFF : Make will stop when encounter error +#---------------------------------------------------------------------- +#export KEEP_GOING := ON +export KEEP_GOING := OFF + +#---------------------------------------------------------------------- +# Isolate creating dependency files process +# +# ON : You have to run "make dep" to create dependency files +# OFF : dependency file will be created when making the file +#---------------------------------------------------------------------- +export ISOLATE_DEP := ON +#export ISOLATE_DEP := OFF + +#---------------------------------------------------------------------- +# Generate debug symbol in release target +# Release target won't generate debug symbol by default, if you want to +# generate debug symbol in release target, please turn on this option +# +# ON : Generate debug symbol in release target +# OFF : Don't generate debug symbol in release target (default value) +#---------------------------------------------------------------------- +#export RELEASE_SYMBOL := ON +export RELEASE_SYMBOL := OFF + +#---------------------------------------------------------------------- +# Generate debug callback of entry and exit to functions +# Only support on MIPS (This is GCC Extension) +# Reference: http://blog.linux.org.tw/~jserv/archives/001870.html +# +# ON : Generate debug callback +# OFF : Don't generate debug callback (default value) +#---------------------------------------------------------------------- +#export INSTRUMENT_FUNCTION := ON +export INSTRUMENT_FUNCTION := OFF + +#---------------------------------------------------------------------- +# Generate one ELF section for each function +# Compiler will generate one ELF section for one .c file by default. +# If the .c file contains lots of function that are unused, turn on +# this function can reduce code size. +# (Linker will remove unused section by default) +# Valid only in release target +# +# ON : One ELF section for each function +# OFF : One ELF section for each .c file (default value of ADS/GNU C compiler) +#---------------------------------------------------------------------- +export SECTION_BY_FUNC := ON +#export SECTION_BY_FUNC := OFF + +#---------------------------------------------------------------------- +# Copy bin file to storage after bin file is created +# You have to set an environment variable named "NVT_STG_PATH" (without +# quote) to work with this function. +# Example: set "NVT_STG_PATH" to "H:/" (without quote). +# +# ON : Copy bin file to storage after bin file is created +# OFF : Don't copy bin file to storage after bin file is created +#---------------------------------------------------------------------- +export COPY_BIN_2_STG := ON +#export COPY_BIN_2_STG := OFF + +#---------------------------------------------------------------------- +# Select emulation or design-in (Release code) environment +# +# ON : Emulation environment +# OFF : Design-in environment +#---------------------------------------------------------------------- +#export EMULATION := ON +export EMULATION := OFF + +#---------------------------------------------------------------------- +# Select FPGA or Realchip platform for emulation. +# Valid only when EMULATION is ON +# +# ON : FPGA platform +# OFF : Realchip platform +#---------------------------------------------------------------------- +#export FPGA_EMULATION := ON +export FPGA_EMULATION := OFF + +#---------------------------------------------------------------------- +# Set PLL OSC frequency for FPGA EMULATION +# Valid only when FPGA_EMULATION is ON +# +# For example, you should set it to 27000000 if your FPGA is connected +# with a 27 MHz OSC. +#---------------------------------------------------------------------- +export FPGA_PLL_OSC := 24000000 + +#---------------------------------------------------------------------- +# Set INCLUDE RULE +# +# ON : Enable include rule checking of platform +# OFF : Disable include rule checking of platform +#---------------------------------------------------------------------- +export INCLUDE_RULE := ON +#export INCLUDE_RULE := OFF + +#---------------------------------------------------------------------- +# Use eCos kernel or uITRON kernel +# +# ON : Use eCos kernel and light weight uITRON kernel compatible wrapper +# OFF : Use light weight uITRON kernel +#---------------------------------------------------------------------- +#export USE_ECOS_KERNEL := ON +export USE_ECOS_KERNEL := OFF + +#---------------------------------------------------------------------- +# PM demo based on customized building way +# +# ON : compile rule depends on _PM_DEMO_ that is informal way. +# OFF : formal way to build code +#---------------------------------------------------------------------- +#export PM_DEMO := ON +export PM_DEMO := OFF + +#---------------------------------------------------------------------- +# Set the dump encrypt binary tool +# +# ARCH := ARM 'Use ARMv4 as target +# ARCH := MIPS 'Use MIPS24Ke as target +#---------------------------------------------------------------------- +export ENCRYPT_DUMP := ON +#export ENCRYPT_DUMP := OFF + +#---------------------------------------------------------------------- +# Use ARM GIC as interrupt controller +# +# ON : Use GIC +# OFF : Use Lagacy interrupt as interrupt controller +#---------------------------------------------------------------------- +export ARM_GIC_400 := ON +#export ARM_GIC_400 := OFF + +#---------------------------------------------------------------------- +# Use ROM public API +# +# ON : Use ROM LZMA etc public API +# OFF : Not use ROM LZMA etc public API +#---------------------------------------------------------------------- +export ROM_PUBLIC_API := OFF +#export ROM_PUBLIC_API := ON + +#---------------------------------------------------------------------- +# Enable 2nd checksum check +# +# ON : After lz uncompress, processing checksum first before jump to +# OFF : Not use checksum. +#---------------------------------------------------------------------- +export PROCESS_2ND_CHECKSUM := ON +#export PROCESS_2ND_CHECKSUM := OFF + +#---------------------------------------------------------------------- +# Use GZIP HW zip +# +# ON : Use HW gzip API +# OFF : Use lz or lzma API +#---------------------------------------------------------------------- +#export GZIP_ENGINE_API := OFF +export GZIP_ENGINE_API := ON + +#---------------------------------------------------------------------- +# Set the parameters of GNU toolchain +#---------------------------------------------------------------------- +ifeq "$(TOOLCHAIN)" "GNU" +ifeq "$(shell uname)" "Linux" + LOADER_CROSS_COMPILE ?= /opt/ivot/gcc-linaro-6.4.1-2018.05-x86_64_arm-eabi/bin/arm-eabi- + CROSS_COMPILE := $(LOADER_CROSS_COMPILE) + TOOLS_DIR = ../../Tools/Bin + TOOLS_SUFFIX = +else + CROSS_COMPILE := arm-eabi- + TOOLS_DIR = ../../Tools/Bin + TOOLS_SUFFIX = .exe +endif + export CC = $(CROSS_COMPILE)gcc + export AS = $(CROSS_COMPILE)as + export LD = $(CROSS_COMPILE)ld + export AR = $(CROSS_COMPILE)ar + export OBJDUMP = $(CROSS_COMPILE)objdump + export FE = $(CROSS_COMPILE)objcopy + export NM = $(CROSS_COMPILE)nm + export LT = "C:/lint/lint-nt.exe" + export GCC = $(CROSS_COMPILE)gcc + export CXX = $(CROSS_COMPILE)g++ + export EBIN = $(TOOLS_DIR)/encrypt_bin$(TOOLS_SUFFIX) + export BFC = $(TOOLS_DIR)/bfc$(TOOLS_SUFFIX) + export LDNVT = $(TOOLS_DIR)/nvt-ld-op$(TOOLS_SUFFIX) + export EBIN = $(TOOLS_DIR)/encrypt_boot_dump$(TOOLS_SUFFIX) + export CFGRAM = $(TOOLS_DIR)/Configram533$(TOOLS_SUFFIX) + export ARMINC_DIR := +endif + + +#---------------------------------------------------------------------- +# Set make flags +# +# Note: Don't modify this if you didn't add new option +#---------------------------------------------------------------------- +# Slient mode +MAKEFLAGS := s + +# Keep going or not +ifeq "$(KEEP_GOING)" "ON" + MAKEFLAGS := $(MAKEFLAGS)k +endif + +#---------------------------------------------------------------------- +# OS Type and Number of CPUs +#---------------------------------------------------------------------- +NPROCS=1 +export OS:=$(shell uname -s) + +ifeq ($(OS),Linux) + NPROCS:=$(shell grep -c ^processor /proc/cpuinfo) +endif +ifeq ($(findstring CYGWIN_NT,$(OS)),CYGWIN_NT) + NPROCS:=$(NUMBER_OF_PROCESSORS) +endif + +export JOB_FLAGS:= -j$(NPROCS) + +endif diff --git a/board/novatek/ns02501/loader/MakeCommon/Makefile b/board/novatek/ns02501/loader/MakeCommon/Makefile new file mode 100755 index 000000000000..58e56d19f7ff --- /dev/null +++ b/board/novatek/ns02501/loader/MakeCommon/Makefile @@ -0,0 +1,126 @@ +include MakeOption.txt + +module_Common := $(dir $(wildcard ../Common/Makefile)) +module_Drv := $(dir $(wildcard ../Drv/Makefile)) +module_DrvExt := $(dir $(wildcard ../DrvExt/Makefile)) +module_Lib := $(dir $(wildcard ../Lib/Makefile)) +module_LibExt := $(dir $(wildcard ../LibExt/Makefile)) +module_App := $(dir $(wildcard ../App/Makefile)) +module_AppExt := $(dir $(wildcard ../AppExt/Makefile)) +module_Alg := $(dir $(wildcard ../Alg/Makefile)) + +-include ../Project/ProjectConfig.txt + +ifneq "$(ACTIVE_PROJECT)" "" +module_Prj := ../Project/$(ACTIVE_PROJECT)/ +else +# Find the first folder in ../Project/ that contains "Makefile" +ifeq "$(shell uname)" "Linux" +module_Prj := $(dir $(firstword $(sort $(shell find ../Project -name 'Makefile')))) +else +module_Prj := $(dir $(firstword $(sort $(shell find ../Project -name \'Makefile\')))) +endif +endif +test_if_unix_file_fmt = $(shell cd $(1); ret=`if [ "$(OS)" == "Linux" ]; then tools/recursive_dir -t . --exclude-ext .o .a .bin .axf .7z --exclude-dir .svn .git; else tools/recursive_dir.exe -t . --exclude-ext .o .a .bin .axf .7z --exclude-dir .svn .git; fi`; echo "$$ret";) + +module_all := \ + $(module_Common) \ + $(module_Drv) \ + $(module_DrvExt) \ + $(module_Lib) \ + $(module_LibExt) \ + $(module_App) \ + $(module_AppExt) \ + $(module_Alg) + +ifeq "$(LOG_ERR)" "ON" +define copy_log + @-cp \ + $(module_Common)log*.txt \ + $(module_Drv)log*.txt \ + $(module_DrvExt)log*.txt \ + $(module_Lib)log*.txt \ + $(module_LibExt)log*.txt \ + $(module_App)log*.txt \ + $(module_AppExt)log*.txt \ + $(module_Alg)log*.txt \ + $(module_Prj)log*.txt \ + . +endef +else +define copy_log +endef +endif + +ifeq "$(ISOLATE_DEP)" "ON" +.PHONY: all rm_log $(module_all) $(module_Prj) clean rebuild debug release dep + +all: rm_log + @make dep + @make debug + @make release + $(call copy_log) +else +.PHONY: all rm_log $(module_all) $(module_Prj) clean rebuild debug release + +all: rm_log $(module_all) $(module_Prj) + $(call copy_log) +endif + +$(module_all): +ifeq ($(OS),Linux) + @$(MAKE) --directory=$@ $(MAKECMDGOALS) +else + @$(MAKE) --directory=$@ $(MAKECMDGOALS) $(JOB_FLAGS) +endif + +$(module_Prj):$(module_all) + @$(MAKE) --directory=$@ $(MAKECMDGOALS) + +rm_log: + @-rm -f log*.txt + +clean: rm_log $(module_all) $(module_Prj) + +ifeq "$(ISOLATE_DEP)" "ON" +rebuild: + @make clean + @make dep + @make debug + @make release + $(call copy_log) + +dep: $(module_all) $(module_Prj) +else +rebuild: rm_log $(module_all) $(module_Prj) + $(call copy_log) +endif + +debug: rm_log $(module_Prj) + $(call copy_log) + +release: rm_log $(module_Prj) + $(call copy_log) + +rm_chk_log: + @-rm -f chk*.txt + +chk: rm_chk_log $(module_all) $(module_Prj) + +chkclean: $(module_all) $(module_Prj) + +rm_lint_log: + @-rm -f lint*.txt + +lint: rm_lint_log $(module_all) $(module_Prj) + +lintclean: $(module_all) $(module_Prj) + +chk_unix: + @result="$(call test_if_unix_file_fmt, ../)"; if [ ! -z "$$result" ]; then \ + echo -e "\e[1;31mUNIX file format check failed:\e[0m" >&2; \ + for n in $$result; do \ + echo -e "\t$$n" >&2; \ + done; \ + exit 1; \ + fi \ No newline at end of file diff --git a/board/novatek/ns02501/loader/MakeCommon/OutputImg.txt b/board/novatek/ns02501/loader/MakeCommon/OutputImg.txt new file mode 100755 index 000000000000..386c1bc1f458 --- /dev/null +++ b/board/novatek/ns02501/loader/MakeCommon/OutputImg.txt @@ -0,0 +1,598 @@ +#---------------------------------------------------------------------- +# Local variable to determine create library or binary file +#---------------------------------------------------------------------- +OUTPUT_FILE = BIN + +#---------------------------------------------------------------------- +# include make common and make option files +#---------------------------------------------------------------------- +include $(MAKE_COMMON_DIR)/MakeOption.txt +include $(MAKE_COMMON_DIR)/MakeCommon.txt + +#---------------------------------------------------------------------- +# CHIPCFG parameters +#---------------------------------------------------------------------- +ifeq "$(CHIPCFG)" "" + CHIPCFG := CHIPCFG +endif + +#---------------------------------------------------------------------- +# get force link ThirdParty symbols for both debug and release +#---------------------------------------------------------------------- +ifeq "$(USE_ECOS_KERNEL)" "ON" +rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d)) +LIB_ECOS_RTK_WIFI_DIR = $(ROOT_DIR)/ThirdParty/devs_eCos-rtl +LIB_ECOS_SELECT_RTK_WIFI_DIR = $(ROOT_DIR)/ThirdParty/devs_eCos-rtl$(WIFIMDL)es +LIB_ECOS_BASE_DIR = $(ROOT_DIR)/ThirdParty +LIB_ECOS_TMP = $(call rwildcard,$(LIB_ECOS_BASE_DIR)/,*.a) +LIB_ECOS_WO_RTK_WIFI_LIB = $(filter-out $(LIB_ECOS_RTK_WIFI_DIR)%, $(LIB_ECOS_TMP)) +LIB_ECOS_RTK_WIFI_LIB = $(call rwildcard,$(LIB_ECOS_SELECT_RTK_WIFI_DIR)/,*.a) +LIB_ECOS = $(LIB_ECOS_WO_RTK_WIFI_LIB) $(LIB_ECOS_RTK_WIFI_LIB) +#There are two eCos .o not in archive +ALL_OBJ_R += $(wildcard $(LIB_ECOS_BASE_DIR)/eCos/lib/*.o) +ALL_OBJ_D += $(wildcard $(LIB_ECOS_BASE_DIR)/eCos/lib/*.o) +endif + +#---------------------------------------------------------------------- +# get force link IPL symbols for both debug and release +#---------------------------------------------------------------------- +SYMBOL_IPL := IPL_SetDZoomFCB IPL_SetSleepFCB IPL_SetWakeupFCB IPL_GetCapRawFCB IPL_SetPauseDMAFCB IPL_SetResumeDMAFCB IPL_SetImgInOutFCB IPL_SetVAFCB IPL_GetIMEHalIdxFCB IPL_GetIPLInfoFCB IPL_TrigFCB IPL_SetTrigInfoFCB IPL_Stream2PauseFCB IPL_Pause2StreamFCB DCE_D2D_CB IPE_D2D_CB IFE_D2D_CB IFE2_D2D_CB IME_D2D_CB DRE_D2D_CB RHEIME_D2D_IFECB RHEIME_D2D_DCECB RHEIME_D2D_IPECB RHEIME_D2D_IMECB RHEIME_D2D_RHECB IPL_GetCtrlFlowFCB IQUC_InitCtrlItem + +#---------------------------------------------------------------------- +# include the libraries +#---------------------------------------------------------------------- +# +# get Debug LIBs +# +LIB_ALG_DIR_D = $(ARC_BASE_DIR)/../Alg/ARC/Debug +LIB_APP_DIR_D = $(ARC_BASE_DIR)/App/Debug +LIB_COM_DIR_D = $(ARC_BASE_DIR)/Common/Debug +LIB_DRV_DIR_D = $(ARC_BASE_DIR)/Drv/Debug +LIB_LIB_DIR_D = $(ARC_BASE_DIR)/Lib/Debug + +# get Alg libraries +LIB_ALG_D := $(wildcard $(LIB_ALG_DIR_D)/*.a) + +# get App/AppExt libraries +LIB_APP_D := $(wildcard $(LIB_APP_DIR_D)/*.a) + +# get Common libraries +LIB_COM_D := $(wildcard $(LIB_COM_DIR_D)/*.a) + +# get Drv/DrvExt libraries +LIB_DRV_ALL_D := $(wildcard $(LIB_DRV_DIR_D)/*.a) + +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_DIR_D = $(ARC_BASE_DIR)/Lib/Debug +LIB_STRGEXT_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/STRGEXT_*.a) +LIB_STRGEXT_D := $(wildcard $(LIB_LIB_DIR_D)/STRGEXT_$(STORAGEEXT)_D.a) +LIB_STRGINT_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/STRGINT_*.a) +LIB_STRGINT_D := $(wildcard $(LIB_LIB_DIR_D)/STRGINT_$(STORAGEINT)_D.a) +LIB_REMAP_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/Remap_*.a) +LIB_REMAP_D := $(wildcard $(LIB_LIB_DIR_D)/Remap_$(RESETFLAG)_D.a) +LIB_RESET_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/Reset_*.a) +ifeq "$(ENLARGE_LD)" "ENABLE" +LIB_RESET_D := $(wildcard $(LIB_LIB_DIR_D)/Reset_$(RESETCHIP)_64K_D.a) +else +LIB_RESET_D := $(wildcard $(LIB_LIB_DIR_D)/Reset_$(RESETCHIP)_D.a) +endif +LIB_COMMON_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/Common_*.a) +LIB_COMMON_D := $(wildcard $(LIB_LIB_DIR_D)/Common_$(COMMON_LIB)_D.a) +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_ALL_D := $(filter-out $(LIB_PARSER_ALL_D) $(LIB_SLIDE_ALL_D), $(wildcard $(LIB_LIB_DIR_D)/*.a)) + +LIB_LIB_D := $(filter-out $(LIB_STRGEXT_ALL_D) $(LIB_STRGINT_ALL_D) $(LIB_REMAP_ALL_D) $(LIB_RESET_ALL_D) $(LIB_COMMON_ALL_D), $(LIB_LIB_ALL_D)) +ifeq ($(SIM_WRLDR), ENABLE) + REMAP_SUFFIX = _SIMWRLDR + RESET_SUFFIX = _SIMWRLDR +else + ifeq ($(FASTBOOT), ENABLE) + ifeq ($(SECUREBOOT), Secure) + ifeq ($(SPI_SETTING), SPI_4BITS) + RESET_SUFFIX = _FASTBOOT_SECURE_QUAD + else + RESET_SUFFIX = _FASTBOOT_SECURE + endif + else + ifeq ($(SPI_SETTING), SPI_4BITS) + RESET_SUFFIX = _FASTBOOT_QUAD + else + RESET_SUFFIX = _FASTBOOT + endif + endif + + ifeq ($(SPI_SETTING), SPI_4BITS) + RESET_SUFFIX = _FASTBOOT_QUAD + else + REMAP_SUFFIX = _FASTBOOT + endif + ifeq ($(STORAGEINT), EMMC) + SCATTER_SUFFIX = _FASTBOOT_EMMC + else + SCATTER_SUFFIX = _FASTBOOT + endif + endif +endif +# +# get Release LIBs +# +LIB_LIB_DIR_R = $(ARC_BASE_DIR)/Lib/Release +LIB_STRGEXT_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/STRGEXT_*.a) +LIB_STRGEXT_R := $(wildcard $(LIB_LIB_DIR_R)/STRGEXT_$(STORAGEEXT)$(STRGEXT_SUFFIX).a) +LIB_STRGINT_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/STRGINT_*.a) +LIB_STRGINT_R := $(wildcard $(LIB_LIB_DIR_R)/STRGINT_$(STORAGEINT).a) +LIB_REMAP_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/Remap_*.a) +LIB_REMAP_R := $(wildcard $(LIB_LIB_DIR_R)/Remap_$(RESETFLAG)$(REMAP_SUFFIX).a) +LIB_RESET_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/Reset_*.a) +ifeq "$(ENLARGE_LD)" "ENABLE" +LIB_RESET_R := $(wildcard $(LIB_LIB_DIR_R)/Reset_$(RESETCHIP)$(RESET_SUFFIX)_64K.a) +else +LIB_RESET_R := $(wildcard $(LIB_LIB_DIR_R)/Reset_$(RESETCHIP)$(RESET_SUFFIX).a) +endif +LIB_COMMON_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/Common_*.a) +LIB_COMMON_R := $(wildcard $(LIB_LIB_DIR_R)/Common_$(COMMON_LIB)$(COMMON_SUFFIX).a) +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_ALL_R := $(filter-out $(LIB_PARSER_ALL_R) $(LIB_SLIDE_ALL_R), $(wildcard $(LIB_LIB_DIR_R)/*.a)) + +#LIB_LIB_R := $(filter-out $(LIB_STRGEXT_ALL_R) $(LIB_STRGINT_ALL_R) $(LIB_REMAP_ALL_R), $(LIB_LIB_ALL_R)) +LIB_LIB_R := $(filter-out $(LIB_STRGEXT_ALL_R) $(LIB_REMAP_ALL_R) $(LIB_RESET_ALL_R) $(LIB_COMMON_ALL_R), $(LIB_LIB_ALL_R)) + + +# get total libraries for Debug & Release mode; note we cannot get string of LIB_R from LIB_D, or vice versa, +# because we may build Debug and Release output separately, the library of one mode maybe not exist, and cause +# the link problem. So, while adding/deleting libraries, please be patient to do it for Debug and Release mode both. + +LIB_R := \ + $(LIB_LIB_R) \ + $(LIB_STRGEXT_R) \ + $(LIB_STRGINT_R) \ + $(LIB_REMAP_R) \ + $(LIB_RESET_R) \ + $(LIB_COMMON_R) + +LIB_D := \ + $(LIB_LIB_D) \ + $(LIB_STRGEXT_D) \ + $(LIB_STRGINT_D) \ + $(LIB_REMAP_D) \ + $(LIB_RESET_D) \ + $(LIB_COMMON_D) + +# If some libraries only available in Release mode, add these libraries in Debug mode too. +LIB_D += $(filter-out $(subst Debug/,Release/,$(LIB_D:_D.a=.a)),$(LIB_R)) + +# Append eCos library to both Debug and Release mode +# (We don't have debug mode's eCos library) +LIB_R += $(LIB_ECOS) +LIB_D += $(LIB_ECOS) + +#---------------------------------------------------------------------- +# set the make outputs +#---------------------------------------------------------------------- +# for debug target +IMAGE_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.axf +BIN_D = $(IMG_DEBUG)/$(LDR_NAME).bin +MAP_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.txt +MAP2_D = $(IMG_DEBUG)/$(PRJ_NAME)_ldmap_D.txt +SYM_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.sym +DASM_D = $(IMG_DEBUG)/$(PRJ_NAME)_dasm_D.txt +ifeq "$(MODELEXT_BUILT_IN)" "MODELEXT_BUILT_IN_OFF" +MODELEXT_D = $(IMG_DEBUG)/$(BIN_NAME).ext.bin +endif + + +# for release target +IMAGE_R = $(IMG_RELEASE)/$(PRJ_NAME).axf +BIN_R = $(IMG_RELEASE)/$(LDR_NAME).bin +MAP_R = $(IMG_RELEASE)/$(PRJ_NAME).txt +MAP2_R = $(IMG_RELEASE)/$(PRJ_NAME)_ldmap.txt +SYM_R = $(IMG_RELEASE)/$(PRJ_NAME).sym +DASM_R = $(IMG_RELEASE)/$(PRJ_NAME)_dasm.txt +ifeq "$(MODELEXT_BUILT_IN)" "MODELEXT_BUILT_IN_OFF" +MODELEXT_R = $(IMG_RELEASE)/$(BIN_NAME).ext.bin +endif + +#---------------------------------------------------------------------- +# if enable LDS_MAP +#---------------------------------------------------------------------- +ifeq "$(LDS_MAP)" "ON" +LDMAP_D = -Map $(MAP2_D) +LDMAP_R = -Map $(MAP2_R) +endif + +#---------------------------------------------------------------------- +# set the warning/error log file option +#---------------------------------------------------------------------- +log_file = log_Prj.txt + +# 0: Standard input (stdin), 1: Standard output (stdout), 2: Standard error (stderr) +# 2>>$(log_file) means redirect standard error to $(log_file) +# 2>>/dev/null means redirect standard error to NULL (Don't display error message) +ifeq "$(LOG_ERR)" "ON" +LOG_OPTION = 2>>$(log_file) +endif + +#---------------------------------------------------------------------- +# set robustness checking log file +#---------------------------------------------------------------------- +lint_file = lint_Prj.txt +lintopt_file = options_Prj.lnt +lintsum_file = lintsum_Prj.txt + +#---------------------------------------------------------------------- +# set the make targets +#---------------------------------------------------------------------- +build_D: make_debug_begin prepare_log $(IMAGE_D) $(BIN_D) +build_R: make_release_begin prepare_log $(IMAGE_R) $(BIN_R) +build_pipe_D: $(IMAGE_D) $(BIN_D) +build_pipe_R: $(IMAGE_R) $(BIN_R) + +ifeq "$(ISOLATE_DEP)" "ON" +build_DEP: make_dep_begin $(SRC) $(ASM) $(CPP_SRC) $(ALL_DEP) +endif + +build_LINT: make_lint_begin $(LINT_FILE) + +prepare_log: + @$(LOG_OPTION) + +ifeq "$(ARCH)" "ARM" +#arm-none-eabi-gcc -march=armv7-a -mcpu=cortex-a9 -mfpu=neon -mfloat-abi=softfp -print-file-name=libm.a +ifeq "$(FPU)" "hard" +libgcc_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mabi=aapcs -mfpu=neon -mfloat-abi=$(FPU) -print-libgcc-file-name) +libgcc_dir_el = $(shell dirname "$(libgcc_path)") +libstdc_path = $(shell $(CC) -msoft-float -print-file-name=libstdc++.a) +libstdc_dir_el = $(shell dirname "$(libstdc_path)") +libm_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mfpu=neon -mfloat-abi=$(FPU) -print-file-name=libm.a) +libm_dir = $(shell dirname "$(libm_path)") +else +libgcc_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mabi=aapcs -mfloat-abi=$(FPU) -print-libgcc-file-name) +libgcc_dir_el = $(shell dirname "$(libgcc_path)") +libstdc_path = $(shell $(CC) -msoft-float -print-file-name=libstdc++.a) +libstdc_dir_el = $(shell dirname "$(libstdc_path)") +libm_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mfloat-abi=$(FPU) -print-file-name=libm.a) +libm_dir = $(shell dirname "$(libm_path)") +endif +endif + +define append_modelext + echo Append $1 into $4. \ + && $(AR) x $3 $1.o \ + && $(FE) --only-section=modelext_header.$1 -O binary -S -R .comment -R .note $1.o $2/$1.header \ + && cat $2/$1.header >> $4 \ + && $(FE) --only-section=modelext_data.$1 -O binary -S -R .comment -R .note $1.o $2/$1.data \ + && cat $2/$1.data >> $4 +endef + + +#Replace string existing in lds file +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_256" + BOARD_UITRON_ADDR = 0x8000000 +endif +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_512" + BOARD_UITRON_ADDR = 0x10000000 +endif +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_1024" + BOARD_UITRON_ADDR = 0x20000000 +endif +endif + +LD_REMAP_LIB = Remap_$(RESETFLAG)$(REMAP_SUFFIX) +LD_DOREMAP = doremap$(RESETFLAG) +ifeq "$(ENLARGE_LD)" "ENABLE" +LD_RESET_LIB = Reset_$(RESETCHIP)$(RESET_SUFFIX)_64K +else +LD_RESET_LIB = Reset_$(RESETCHIP)$(RESET_SUFFIX) +endif +LD_COMMON_LIB = Common_$(COMMON_LIB)$(COMMON_SUFFIX) +ifeq "$(BL_COMPRESS)" "ENABLE" +LD_CONFIGRAM = configramLZ +else +LD_CONFIGRAM = configramNM +endif +LD_REPLACE_VAR = sed \ + -e 's/$$LD_REMAP_LIB/$(LD_REMAP_LIB)/g' \ + -e 's/$$LD_DOREMAP/$(LD_DOREMAP)/g' \ + -e 's/$$LD_CONFIGRAM/$(LD_CONFIGRAM)/g' \ + -e 's/$$LD_BASE_ADDR/$(LD_BASE_ADDR)/g' \ + -e 's/$$LD_RESET_LIB/$(LD_RESET_LIB)/g' \ + -e 's/$$LD_COMMON_LIB/$(LD_COMMON_LIB)/g' \ + -e 's/$$STORAGEINT/$(STORAGEINT)/g' \ + $(SCATTER) + +#The folder, the working space to fill the full path into lds file +LD_DIR_WORKING_D= $(IMG_BASE_DIR)/Debug/ObjectLds +#Generate the working folder and temp lds file called replace.lds +LD_REPLACE_LDS_D= $(shell mkdir -p $(LD_DIR_WORKING_D)) $(shell $(OBJDUMP) -h $(LIB_D) | grep ".version.info" > tmp_awk1) $(shell $(LD_REPLACE_VAR) > $(LD_DIR_WORKING_D)/replace.lds) +#The real lds file replaced of using by linker +LD_PATH_LDS_D = $(LD_DIR_WORKING_D)/$(basename $(SCATTER))_D.lds +#Here have some steps as following to get a some files explained below, +#Step 1: Generate temp lds file +#Step 2: export the contents of $(LIB_D) into libs.txt +#Step 3: export the contents of $(ALL_OBJ_D) into objs.txt +#Step 4: Give mips-nvt.exe libs.txt, objs.txt and replace.lds to get ld_ext.d, ld_lib.txt, ld_lib_ban.txt and real lds file for linker. +# Where, +# ld_ext.d is a decency file depends on .o used in lds file +# ld_lib_ban is a list of .a files to ban, because linker should use the .a file after extracting .o. +# real lds file is replaced by full path. +LD_DFILE_D = $(LD_REPLACE_LDS_D) $(shell echo $(LIB_D) > $(LD_DIR_WORKING_D)/libs.txt ) $(shell echo $(ALL_OBJ_D) > $(LD_DIR_WORKING_D)/objs.txt ) $(shell $(LDNVT) --lds-dst=$(LD_PATH_LDS_D) --lds-dir=$(LD_DIR_WORKING_D) --lds-src=$(LD_DIR_WORKING_D)/replace.lds --libs-src=$(LD_DIR_WORKING_D)/libs.txt --objs-src=$(LD_DIR_WORKING_D)/objs.txt --objs-dir=$(OBJ_DEBUG)) $(LD_DIR_WORKING_D)/ld_ext.d +#Getting the contents of ld_lib.txt +LD_LIB_D = $(shell cat $(LD_DIR_WORKING_D)/ld_lib.txt 2>>/dev/null) +#Getting the contents of ld_lib_ban.txt +LD_LIB_BAN_D = $(shell cat $(LD_DIR_WORKING_D)/ld_lib_ban.txt 2>>/dev/null) +tmp_awk2 = $(shell awk -F" " '{print $$2}' tmp_awk1 | awk -F"." '{print $$5}') +tmp_awk3 = $(addsuffix _LIBRARY_VERSION_INFO, $(tmp_awk2)) + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),debug build_pipe_D)) +include $(LD_DFILE_D) +endif + +$(LD_LIB_D): $(MODELEXT_D) + +#$(MODELEXT_D): $(LIB_MODELEXT_D) +# @echo Creating modelext $@ ... \ +# && rm -f $@ \ +# && $(call append_modelext,modelext_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,bin_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,pinmux_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,intdir_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,emb_partition_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,gpio_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,dram_partition_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,model_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(EBIN) $(EBIN_METHOD) $@ 0x18 $(EBIN_MNAME) +# @BIN_SIZE=`ls -l $@ | cut -d ' ' -f 5`; \ +# RESIDUAL=$$(($${BIN_SIZE} % 4)); \ +# if [ "$${RESIDUAL}" -ne "0" ]; then \ +# echo "sizeof($@) is not 4-byte aligned"; \ +# exit 1; \ +# fi + +$(IMAGE_D): $(SRC) $(ASM) $(CPP_SRC) $(ALL_OBJ_D) $(LIB_D) $(LD_LIB_D) $(MODELEXT_D) + $(shell mv *.o $(IMG_BASE_DIR)/Debug/ObjectCode 2>>/dev/null) + @echo '-o $@ $(ALL_OBJ_D)'> ld_d.tmp + @echo '--start-group $(LD_LIB_D) $(filter-out $(LD_LIB_BAN_D),$(LIB_D)) --end-group -Bstatic -EL --no-wchar-size-warning --gc-sections -T $(LD_PATH_LDS_D) -L "$(libgcc_dir_el)" -L"$(libstdc_dir_el)" -L"$(libm_dir)" -lgcc $(LDMAP_D)' >> ld_d.tmp +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" + @echo "Linking CA53_core2...$(LD_PATH_LDS_D)" \ + && echo Creating image $@ ... \ + && $(LD) @ld_d.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_D) \ + && $(NM) -n $@ > tmp_sym_d \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_d > $(SYM_D) \ + && rm -f tmp_sym_d \ + && rm -f ld_d.tmp \ + && rm -f tmp_awk1 +else + @echo "Linking ..." \ + && echo Creating image $@ ... \ + && $(LD) @ld_d.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_D) \ + && $(NM) -n $@ > tmp_sym_d \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_d > $(SYM_D) \ + && rm -f tmp_sym_d \ + && rm -f ld_d.tmp \ + && rm -f tmp_awk1 +endif + + +$(BIN_D): $(IMAGE_D) +ifeq "$(MULTI_REGIONS)" "ON" + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ \ + && mv $(IMG_DEBUG)/SPECIAL_RO $(BIN_D) +else + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ +endif +ifeq "$(LDS_MAP)" "ON" + @echo Generate LDS map file $(MAP2_D): ok +endif +ifeq "$(AXF_DIS)" "ON" + @echo Translate AXF $< to disassembly... \ + && $(OBJDUMP) -D $(IMAGE_D) > $(DASM_D) +endif + +ifeq "$(BL_COMPRESS)" "ENABLE" + @echo Compressing file $(@)\ + && $(BFC) c lz $(BIN_D) tmp 2 $(UNCOMPRESSEDPART_SIZE_OFFSET) \ + && cp -f tmp $(BIN_D) \ + && rm -f tmp \ + && echo Encrypt binary file $@ for $(CHIP)... $(CHIP_VER) $(DMA_CLOCK) $(SDRAM_SIZE) $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE)\ + && $(EBIN) $@ $@ 680 + $(CFGRAM) $@ -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI_STR) -chip=660 -package=$(CHIP) -ldver=$(LOADER_VERSION) -gui=$(CONFIG_RAM_GUI_EN) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) +# $(CFGRAM) $@ ../../Tools/ConfigRam/$(CHIP)_$(CHIP_VER)_$(DMA_CLOCK)_$(SDRAM_SIZE)$(DDR_FILE_STR).ini 650 $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE) $(LV1_CLK) +else + @echo Encrypt binary file $@ for $(CHIP)...\ + && $(EBIN) $@ $@ 680 $(SECURE_BOOT) +endif + +ifeq "$(COPY_BIN_2_STG)" "ON" +ifneq "$(NVT_STG_PATH)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH) ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH)$(notdir $(BIN_D)) +endif +ifneq "$(NVT_STG_PATH_MIPS2)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin +endif + +ifneq "$(NVT_STG_PATH_CA532)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH_CA532)_FWCA532.bin ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH_CA532)_FWCA532.bin +endif +endif + +#Please refer LD_DIR_WORKING_D for getting explanation. Ohters are in the same way. +LD_DIR_WORKING_R= $(IMG_BASE_DIR)/Release/ObjectLds +LD_REPLACE_LDS_R= $(shell mkdir -p $(LD_DIR_WORKING_R)) $(shell $(OBJDUMP) -h $(LIB_R) | grep ".version.info" > tmp_awk1) $(shell $(LD_REPLACE_VAR) > $(LD_DIR_WORKING_R)/replace.lds) +LD_PATH_LDS_R = $(LD_DIR_WORKING_R)/$(basename $(SCATTER))_R.lds +LD_DFILE_R = $(LD_REPLACE_LDS_R) $(shell echo $(LIB_R) > $(LD_DIR_WORKING_R)/libs.txt ) $(shell echo $(ALL_OBJ_R) > $(LD_DIR_WORKING_R)/objs.txt ) $(shell $(LDNVT) --lds-dst=$(LD_PATH_LDS_R) --lds-dir=$(LD_DIR_WORKING_R) --lds-src=$(LD_DIR_WORKING_R)/replace.lds --libs-src=$(LD_DIR_WORKING_R)/libs.txt --objs-src=$(LD_DIR_WORKING_R)/objs.txt --objs-dir=$(OBJ_RELEASE)) $(LD_DIR_WORKING_R)/ld_ext.d +LD_LIB_R = $(shell cat $(LD_DIR_WORKING_R)/ld_lib.txt 2>>/dev/null) +LD_LIB_BAN_R = $(shell cat $(LD_DIR_WORKING_R)/ld_lib_ban.txt 2>>/dev/null) +tmp_awk2 = $(shell awk -F" " '{print $$2}' tmp_awk1 | awk -F"." '{print $$5}') +tmp_awk3 = $(addsuffix _LIBRARY_VERSION_INFO, $(tmp_awk2)) + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),release build_pipe_R)) +include $(LD_DFILE_R) +endif + +$(LD_LIB_R): $(MODELEXT_R) + +#$(MODELEXT_R): $(LIB_MODELEXT_R) +# @echo Creating modelext $@\ +# && rm -f $@ \ +# && $(call append_modelext,modelext_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,bin_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,pinmux_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,intdir_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,emb_partition_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,gpio_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,dram_partition_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,model_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(EBIN) $(EBIN_METHOD) $@ 0x18 $(EBIN_MNAME) +# @BIN_SIZE=`ls -l $@ | cut -d ' ' -f 5`; \ +# RESIDUAL=$$(($${BIN_SIZE} % 4)); \ +# if [ "$${RESIDUAL}" -ne "0" ]; then \ +# echo "sizeof($@) is not 4-byte aligned"; \ +# exit 1; \ +# fi + +$(IMAGE_R): $(SRC) $(ASM) $(CPP_SRC) $(ALL_OBJ_R) $(LIB_R) $(LD_LIB_R) $(MODELEXT_R) + $(shell mv *.o $(IMG_BASE_DIR)/Release/ObjectCode 2>>/dev/null) + @echo '-o $@ $(ALL_OBJ_R) '> ld_r.tmp + @echo '--start-group $(LD_LIB_R) $(filter-out $(LD_LIB_BAN_R),$(LIB_R)) --end-group -Bstatic -EL --no-wchar-size-warning --gc-sections -T $(LD_PATH_LDS_R) -L"$(libgcc_dir_el)" -L"$(libstdc_dir_el)" -lgcc $(LDMAP_R)' >> ld_r.tmp + +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" + @echo "Linking CA53_core2...$(LD_PATH_LDS_R)" \ + && echo Creating image $@ ... \ + && $(LD) @ld_r.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_R) \ + && $(NM) -n $@ > tmp_sym_r \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_r > $(SYM_R) \ + && rm -f tmp_sym_r \ + && rm -f ld_r.tmp \ + && rm -f tmp_awk1 +else + @echo "Linking ... " \ + && echo Creating image $@ ...\ + && $(LD) @ld_r.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t -marm $@ > $(MAP_R) \ + && $(NM) -n $@ > tmp_sym_r \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_r > $(SYM_R) \ + && rm -f tmp_sym_r \ + && rm -f ld_r.tmp \ + && rm -f tmp_awk1 +endif + +$(BIN_R): $(IMAGE_R) +ifeq "$(MULTI_REGIONS)" "ON" + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ \ + && mv $(IMG_RELEASE)/SPECIAL_RO $(BIN_R) +else + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ +endif + +ifeq "$(LDS_MAP)" "ON" + @echo Generate LDS map file $(MAP2_R): ok +endif +ifeq "$(AXF_DIS)" "ON" + @echo Translate AXF $< to disassembly... \ + && $(OBJDUMP) -D $(IMAGE_R) > $(DASM_R) +endif +ifeq "$(PROCESS_2ND_CHECKSUM)" "ON" + @echo Process compressing file $(@) checksum ...\ + && $(EBIN) $@ $@ $(CHIPID) 10 +endif +ifeq "$(BL_COMPRESS)" "ENABLE" + @echo Compressing file $(@)\ + && $(BFC) c $(COMPRESS_ALG) $(BIN_R) tmp 2 $(UNCOMPRESSEDPART_SIZE_OFFSET) \ + && cp -f tmp $(BIN_R) \ + && rm -f tmp \ + && echo Encrypt binary file $@ for $(CHIP)... $(CHIP_VER) $(DMA_CLOCK) $(SDRAM_SIZE) $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE)\ + && $(EBIN) $@ $@ $(CHIPID) + $(CFGRAM) $@ -freq=$(DRAM1_CLK) -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -chip=$(CHIPID) -package=$(CHIP) -ldver=$(LOADER_VERSION) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) -dram_ssc=$(DRAM_SSC_PARAM) -simp_chksum_skip=$(SIMPLE_CHKSUM_SKIP) -dram_wt=$(DDR_TREFI_PARAM) -dram_2nd_tlb=$(2ND_INI) -dram_2nd_tlb_gpio_no=$(GPIO_NUM) -2nd_ini=../../Tools/ConfigRam/$(DDR_INI_STR2) -odt_select=$(ODT_SELECT) -tx_drv=$(TX_DRV) -ddr_ldo=$(DDR_LDO) -pll_ldo=$(PLL_LDO) -rx_pad=$(RX_PAD) -fpga=$(FPGA_EMULATION) -storage_dir_mode=$(INT_STRG_DIR_MODE) + $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) $(ENCRYPT_DATA) $(SECUREBOOT_MSG) $(AES_KEY_FILE_DIR) $(RSA_PUB_KEY_FILE_DIR) $(RSA_PRV_KEY_FILE_DIR) $(ENCRYPTDATA_KEY_SET) $(_HEADER_SIGN_) $(SIGNATURE_FIRST) +ifeq "$(SIMPLE_CHKSUM_SKIP)" "ENABLE" + @echo Simple checksum skip enabled => re-gen simple chksum... + $(EBIN) $@ $@ $(CHIPID) +endif +# $(CFGRAM) $@ -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI_STR) -chip=660 -package=$(CHIP) -ldver=$(LOADER_VERSION) -gui=$(CONFIG_RAM_GUI_EN) -storage=$(STORAGEINT) +else +# No compress + @echo Encrypt binary file $@ for $(CHIP)...\ + && $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) \ + && $(CFGRAM) $@ -freq=$(DRAM1_CLK) -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI2_STR) -chip=$(CHIPID) -package=$(CHIP) -ldver=$(LOADER_VERSION) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) -dram_number=$(DRAM_NUMBER_DET_PARAM) -dram_ssc=$(DRAM_SSC_PARAM) +endif + +ifeq "$(COPY_BIN_2_STG)" "ON" +ifneq "$(NVT_STG_PATH)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH) ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH)$(notdir $(BIN_R)) +endif +ifneq "$(NVT_STG_PATH_MIPS2)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH_MIPS2) ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin +endif + +ifneq "$(NVT_STG_PATH_CA532)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH_CA532)_FWCA532.bin ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH_CA532)_FWCA532.bin +endif +endif + +.PHONY: +rm_log: +ifeq "$(CLEAN_LOG)" "ON" + @-rm -f $(log_file) +endif + +clean: + @-echo Clean $(basename $(notdir $(IMAGE_R))) ... \ + && rm -rf --no-preserve-root $(IMG_BASE_DIR) $(log_file) $(lint_file) + +ifeq "$(ISOLATE_DEP)" "ON" +all: rm_log + @make dep + @make debug + @make release + +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: build_DEP +else +rebuild: clean build_D build_R +endif + +debug: rm_log make_debug_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_D +else + $(MAKE) build_pipe_D $(JOB_FLAGS) +endif + +release: rm_log make_release_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_R +else + $(MAKE) build_pipe_R $(JOB_FLAGS) +endif + +#remove unused remap.a for sdk +remap: + rm -v $(filter-out $(LIB_REMAP_D), $(LIB_REMAP_ALL_D)) $(filter-out $(LIB_REMAP_R), $(LIB_REMAP_ALL_R)) + +codesize: $(IMAGE_R) + @$(OBJDUMP) -t $< > $<.sym && \ + $(LDNVT) -j $<.sym && \ + mv RO_RW.txt ZI.txt $(IMG_RELEASE) + diff --git a/board/novatek/ns02501/loader/MakeCommon/OutputLib.txt b/board/novatek/ns02501/loader/MakeCommon/OutputLib.txt new file mode 100755 index 000000000000..391f4c0cb572 --- /dev/null +++ b/board/novatek/ns02501/loader/MakeCommon/OutputLib.txt @@ -0,0 +1,155 @@ +#---------------------------------------------------------------------- +# Local variable to determine create library or binary file +#---------------------------------------------------------------------- +OUTPUT_FILE = LIB + +#---------------------------------------------------------------------- +# include make common and make option files +#---------------------------------------------------------------------- +ifeq "$(OPTION_LOADED)" "" + include $(MAKE_COMMON_DIR)/MakeOption.txt + LOCAL_CLEAN_LOG = $(CLEAN_LOG) +else + LOCAL_CLEAN_LOG = OFF +endif + +include $(MAKE_COMMON_DIR)/MakeCommon.txt + +#---------------------------------------------------------------------- +# set the make outputs +#---------------------------------------------------------------------- +IMAGE_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.a +IMAGE_R = $(IMG_RELEASE)/$(PRJ_NAME).a + +#---------------------------------------------------------------------- +# set the warning/error log file option +#---------------------------------------------------------------------- +# $(APP_PATH), $(APPEXT_PATH), $(LIB_PATH), $(LIBEXT_PATH) will be assigned value in MakeCommon.txt +ifneq "$(ALG_PATH)" "" + log_file := $(subst MakeCommon,Alg/log_Alg.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Alg/lint_Alg.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Alg.lnt + lintsum_file := $(subst MakeCommon,App/lintsum_Alg.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(APP_PATH)" "" + log_file := $(subst MakeCommon,App/log_App.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,App/lint_App.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_App.lnt + lintsum_file := $(subst MakeCommon,App/lintsum_App.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(APPEXT_PATH)" "" + log_file := $(subst MakeCommon,AppExt/log_AppExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,AppExt/lint_AppExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_AppExt.lnt + lintsum_file := $(subst MakeCommon,AppExt/lintsum_AppExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(LIB_PATH)" "" + log_file := $(subst MakeCommon,Lib/log_Lib.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Lib/lint_Lib.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Lib.lnt + lintsum_file := $(subst MakeCommon,Lib/lintsum_Lib.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(LIBEXT_PATH)" "" + log_file := $(subst MakeCommon,LibExt/log_LibExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,LibExt/lint_LibExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_LibExt.lnt + lintsum_file := $(subst MakeCommon,LibExt/lintsum_LibExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(DRV_PATH)" "" + log_file := $(subst MakeCommon,Drv/log_Drv.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Drv/lint_Drv.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Drv.lnt + lintsum_file := $(subst MakeCommon,Drv/lintsum_Drv.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(DRVEXT_PATH)" "" + log_file := $(subst MakeCommon,DrvExt/log_DrvExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,DrvExt/lint_DrvExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_DrvExt.lnt + lintsum_file := $(subst MakeCommon,DrvExt/lintsum_DrvExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(COM_PATH)" "" + log_file := $(subst MakeCommon,Common/log_Common.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Common/lint_Common.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Common.lnt + lintsum_file := $(subst MakeCommon,Common/lintsum_Common.txt,$(MAKE_COMMON_DIR)) +else + log_file := /dev/null + lint_file := /dev/null + lintopt_file := /dev/null + lintsum_file := /dev/null +endif + +ifeq "$(LOG_ERR)" "ON" + LOG_OPTION = 2>>$(log_file) + LOG_DATE = date >>$(log_file) + LOG_SPACE = echo >>$(log_file) +endif + +#---------------------------------------------------------------------- +# set the make targets +#---------------------------------------------------------------------- +build_D: make_debug_begin $(IMAGE_D) +build_R: make_release_begin $(IMAGE_R) +build_pipe_D: $(IMAGE_D) +build_pipe_R: $(IMAGE_R) + +ifeq "$(ISOLATE_DEP)" "ON" +build_DEP: make_dep_begin $(ALL_DEP) +endif + +build_LINT: make_lint_begin $(LINT_FILE) + +$(IMAGE_D): $(ALL_OBJ_D) + @echo Creating library $(notdir $@) ... \ + && rm -f $(IMAGE_D) \ + && $(AR) -cru $@ $^ + +$(IMAGE_R): $(ALL_OBJ_R) + @echo Creating library $(notdir $@) ... \ + && rm -f $(IMAGE_R) \ + && $(AR) -cru $@ $^ + +.PHONY: +rm_log: +ifeq "$(LOCAL_CLEAN_LOG)" "ON" + @-rm -f $(log_file) +endif + +clean: + @-echo Clean $(basename $(notdir $(IMAGE_R))) ... \ + && rm -rf --no-preserve-root $(PRJ_NAME)_Data $(log_file) $(lint_file) + +ifeq "$(ISOLATE_DEP)" "ON" +all: rm_log + @make dep + @make debug + @make release + +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: build_DEP +else +rebuild: clean build_D build_R +endif + +debug: rm_log make_debug_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_D +else + $(MAKE) build_pipe_D $(JOB_FLAGS) +endif + +release: rm_log make_release_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_R +else + $(MAKE) build_pipe_R $(JOB_FLAGS) +endif + +rm_lint_log: +ifeq "$(LOCAL_CLEAN_LOG)" "ON" + @-rm -f $(lint_file) +endif + +lint: rm_lint_log build_LINT + +lintclean: + @-echo Clean Lint $(basename $(notdir $(IMAGE_R))) checking data ... \ + && rm -rf --no-preserve-root $(LINT_DIR) $(lint_file) diff --git a/board/novatek/ns02501/loader/MakeCommon/dump_tmp b/board/novatek/ns02501/loader/MakeCommon/dump_tmp new file mode 100755 index 000000000000..e69de29bb2d1 diff --git a/board/novatek/ns02501/loader/Project/Model/LDS_LZ.lds b/board/novatek/ns02501/loader/Project/Model/LDS_LZ.lds new file mode 100755 index 000000000000..16b1c730cea0 --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/LDS_LZ.lds @@ -0,0 +1,182 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xF07C0000|0x00000000: + AT (0) + { + _load_BOOT_EXEC_start_base = .; + KEEP($LD_RESET_LIB/reset.o(.data*)); + $LD_RESET_LIB/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xF07C0000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP($LD_RESET_LIB/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + } + .LOADER_CONFIGRAM2 (0xF07C0000|0x00000000) + 0x400: + AT (0x400) + { + _config_dram_tbl_start_base = .; + KEEP($LD_RESET_LIB/config_dram1_tbl.o(.rodata*)); + config_dram1_tbl_2_start_base = .; + KEEP($LD_RESET_LIB/config_dram1_2_tbl.o(.rodata*)); + . = ALIGN(32); /* vector table aligned */ + } + .LOADER_CORE2_ENTRY_PROGRAM (0xF07C0000|0x00000000) + 0x600: + AT (0x600) + { + _load_core2_entry_program_start_base = .; + KEEP($LD_RESET_LIB/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + .LOADER_REMAP (0xF07C0000|0x00000000) + 0x700: + AT (0x700) + { + _load_LOADER_REMAP_start_base = .; + $LD_REMAP_LIB/$LD_DOREMAP.o(.text* .data*); + _load_LOADER_REMAP_end_base = .; + _load_vector_exp_table_start_base = .; + KEEP($LD_RESET_LIB/exp.o(.text*)); + _load_vector_exp_table_end_base = .; + KEEP(Ctrl_Flow/bl_lowlevel_init.o(.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/configDDR.o(.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/ddr_basic.o (.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/Delayline_K.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/ddr_io.o (.text* .rodata* .data* .bss*)); + KEEP(Driver/fuart.o(.text* .data* .rodata*)); + KEEP(Driver/cc.o (.text* .data* .bss* .rodata*)); + KEEP(Debug/debug.o (.text* .data* .bss* .rodata*)); + KEEP($LD_COMMON_LIB/global.o (.text* .data* .bss* .rodata*)); + KEEP($LD_COMMON_LIB/utility.o (.text* .data* .bss* .rodata*)); + KEEP($LD_COMMON_LIB/string.o (.text* .data* .bss* .rodata*)); /* for low level use memcmp by fdt lib */ + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + + . = ALIGN(4); + .LOADER_EXEC ADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP) : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + KEEP(Driver/rtc.o(.part1*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .text $LD_BASE_ADDR: + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _loader_exec_compres_end = .; + } + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + } + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(8); /* This is MUST. Ensure ro size is 2 word aligned. */ + } + .dram_text : + AT (LOADADDR(.rodata) + SIZEOF(.rodata)) + { + _loader_dram_text_start_base = .; + * (.dram_text) + } + _loader_dram_text_cpu_addr = LOADADDR(.dram_text) + ADDR(.BOOT_EXEC); + _loader_dram_text_size = SIZEOF(.dram_text); + .data : + AT (LOADADDR(.dram_text) + SIZEOF(.dram_text)) + { + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + *(.data*) + _image_general_var_limit = .; + } + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got) } + . = ALIGN(4); + .bss : { /* locate bss at DRAM end */ + _image_general_zi_zi_base = .; + *(.bss) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + . = ALIGN(0x400); + _ttb_lv2 = .; + . = . + 0x400; + } + .common : + { + __common_base = ABSOLUTE(.); + /* collect "small" un-initialized global data (mark "C" in sym file) */ + *(.scommon*) + /* collect "large" un-initialized global data (mark "B" in sym file) */ + *(COMMON) + __common_limit = ABSOLUTE(.); + } + . = ALIGN(64); + _image_general_zi_zi_limit = ABSOLUTE(.); + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; + +} + +EXTERN("main" "config_dma" "Dec2HexStr") \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Project/Model/LDS_LZ_FASTBOOT.lds b/board/novatek/ns02501/loader/Project/Model/LDS_LZ_FASTBOOT.lds new file mode 100755 index 000000000000..33d05315e1c3 --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/LDS_LZ_FASTBOOT.lds @@ -0,0 +1,188 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xF07C0000|0x00000000: + AT (0) + { + _load_BOOT_EXEC_start_base = .; + KEEP($LD_RESET_LIB/reset.o(.data*)); + $LD_RESET_LIB/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xF07C0000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP($LD_RESET_LIB/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + } + .LOADER_CONFIGRAM2 (0xF07C0000|0x00000000) + 0x400: + AT (0x400) + { + _config_dram_tbl_start_base = .; + KEEP($LD_RESET_LIB/config_dram1_tbl.o(.rodata*)); + config_dram1_tbl_2_start_base = .; + KEEP($LD_RESET_LIB/config_dram1_2_tbl.o(.rodata*)); + . = ALIGN(32); /* vector table aligned */ + } + .LOADER_CORE2_ENTRY_PROGRAM (0xF07C0000|0x00000000) + 0x600: + AT (0x600) + { + _load_core2_entry_program_start_base = .; + KEEP($LD_RESET_LIB/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + .LOADER_REMAP (0xF07C0000|0x00000000) + 0x700: + AT (0x700) + { + _load_LOADER_REMAP_start_base = .; + $LD_REMAP_LIB/$LD_DOREMAP.o(.text* .data*); + _load_LOADER_REMAP_end_base = .; + _load_vector_exp_table_start_base = .; + KEEP($LD_RESET_LIB/exp.o(.text*)); + _load_vector_exp_table_end_base = .; + KEEP(Ctrl_Flow/bl_lowlevel_init.o(.text* .rodata* .data* .bss*)); + KEEP(Ctrl_Flow/spi_nor_ids.o(.text* .rodata* .data* .bss*)); + KEEP(Ctrl_Flow/nand_ids.o(.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/configDDR.o(.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/ddr_basic.o (.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/Delayline_K.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/ddr_io.o (.text* .rodata* .data* .bss*)); + KEEP(Driver/fuart.o(.text* .data* .rodata*)); + KEEP(Driver/cc.o (.text* .data* .bss* .rodata*)); + KEEP(Debug/debug.o (.text* .data* .bss* .rodata*)); + KEEP($LD_COMMON_LIB/global.o (.text* .data* .bss* .rodata*)); + KEEP($LD_COMMON_LIB/utility.o (.text* .data* .bss* .rodata*)); + KEEP($LD_COMMON_LIB/string.o (.text* .data* .bss* .rodata*)); /* for low level use memcmp by fdt lib */ + KEEP(Driver/cfe.o (.text* .data* .bss* .rodata*)); /* for low level use cfe */ + KEEP(STRGINT_$STORAGEINT.a (.text* .data* .bss* .rodata*)); + KEEP(CA9.a (.text* .data* .bss* .rodata*)); + KEEP(fdt.a (.text* .data* .bss* .rodata*)); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + + . = ALIGN(4); + .LOADER_EXEC ADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP) : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + KEEP(Driver/rtc.o(.part1*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .text $LD_BASE_ADDR: + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _loader_exec_compres_end = .; + } + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + } + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(8); /* This is MUST. Ensure ro size is 2 word aligned. */ + } + .dram_text : + AT (LOADADDR(.rodata) + SIZEOF(.rodata)) + { + _loader_dram_text_start_base = .; + * (.dram_text) + } + _loader_dram_text_cpu_addr = LOADADDR(.dram_text) + ADDR(.BOOT_EXEC); + _loader_dram_text_size = SIZEOF(.dram_text); + .data : + AT (LOADADDR(.dram_text) + SIZEOF(.dram_text)) + { + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + *(.data*) + _image_general_var_limit = .; + } + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got) } + . = ALIGN(4); + .bss : { /* locate bss at DRAM end */ + _image_general_zi_zi_base = .; + *(.bss) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + . = ALIGN(0x400); + _ttb_lv2 = .; + . = . + 0x400; + } + .common : + { + __common_base = ABSOLUTE(.); + /* collect "small" un-initialized global data (mark "C" in sym file) */ + *(.scommon*) + /* collect "large" un-initialized global data (mark "B" in sym file) */ + *(COMMON) + __common_limit = ABSOLUTE(.); + } + . = ALIGN(64); + _image_general_zi_zi_limit = ABSOLUTE(.); + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; + +} + +EXTERN("main" "config_dma" "Dec2HexStr") \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Project/Model/LDS_LZ_FASTBOOT_EMMC.lds b/board/novatek/ns02501/loader/Project/Model/LDS_LZ_FASTBOOT_EMMC.lds new file mode 100755 index 000000000000..4e8c8a46299e --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/LDS_LZ_FASTBOOT_EMMC.lds @@ -0,0 +1,187 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xF07C0000|0x00000000: + AT (0) + { + _load_BOOT_EXEC_start_base = .; + KEEP($LD_RESET_LIB/reset.o(.data*)); + $LD_RESET_LIB/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xF07C0000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP($LD_RESET_LIB/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + } + .LOADER_CONFIGRAM2 (0xF07C0000|0x00000000) + 0x400: + AT (0x400) + { + _config_dram_tbl_start_base = .; + KEEP($LD_RESET_LIB/config_dram1_tbl.o(.rodata*)); + config_dram1_tbl_2_start_base = .; + KEEP($LD_RESET_LIB/config_dram1_2_tbl.o(.rodata*)); + . = ALIGN(32); /* vector table aligned */ + } + .LOADER_CORE2_ENTRY_PROGRAM (0xF07C0000|0x00000000) + 0x600: + AT (0x600) + { + _load_core2_entry_program_start_base = .; + KEEP($LD_RESET_LIB/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + .LOADER_REMAP (0xF07C0000|0x00000000) + 0x700: + AT (0x700) + { + _load_LOADER_REMAP_start_base = .; + $LD_REMAP_LIB/$LD_DOREMAP.o(.text* .data*); + _load_LOADER_REMAP_end_base = .; + _load_vector_exp_table_start_base = .; + KEEP($LD_RESET_LIB/exp.o(.text*)); + _load_vector_exp_table_end_base = .; + KEEP(Ctrl_Flow/bl_lowlevel_init.o(.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/configDDR.o(.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/ddr_basic.o (.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/Delayline_K.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/ddr_io.o (.text* .rodata* .data* .bss*)); + KEEP(Driver/fuart.o(.text* .data* .rodata*)); + KEEP(Driver/cc.o (.text* .data* .bss* .rodata*)); + KEEP(Driver/pad.o (.text* .data* .bss* .rodata*)); /* pad_setDrivingSink */ + KEEP(Debug/debug.o (.text* .data* .bss* .rodata*)); + KEEP($LD_COMMON_LIB/global.o (.text* .data* .bss* .rodata*)); + KEEP($LD_COMMON_LIB/utility.o (.text* .data* .bss* .rodata*)); + KEEP($LD_COMMON_LIB/string.o (.text* .data* .bss* .rodata*)); /* for low level use memcmp by fdt lib */ + KEEP(Driver/cfe.o (.text* .data* .bss* .rodata*)); /* for low level use cfe */ + KEEP(STRGINT_$STORAGEINT.a (.text* .data* .bss* .rodata*)); + KEEP(CA9.a (.text* .data* .bss* .rodata*)); + KEEP(fdt.a (.text* .data* .bss* .rodata*)); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + + . = ALIGN(4); + .LOADER_EXEC ADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP) : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + KEEP(Driver/rtc.o(.part1*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .text $LD_BASE_ADDR: + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _loader_exec_compres_end = .; + } + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + } + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(8); /* This is MUST. Ensure ro size is 2 word aligned. */ + } + .dram_text : + AT (LOADADDR(.rodata) + SIZEOF(.rodata)) + { + _loader_dram_text_start_base = .; + * (.dram_text) + } + _loader_dram_text_cpu_addr = LOADADDR(.dram_text) + ADDR(.BOOT_EXEC); + _loader_dram_text_size = SIZEOF(.dram_text); + .data : + AT (LOADADDR(.dram_text) + SIZEOF(.dram_text)) + { + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + *(.data*) + _image_general_var_limit = .; + } + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got) } + . = ALIGN(4); + .bss : { /* locate bss at DRAM end */ + _image_general_zi_zi_base = .; + *(.bss) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + . = ALIGN(0x400); + _ttb_lv2 = .; + . = . + 0x400; + } + .common : + { + __common_base = ABSOLUTE(.); + /* collect "small" un-initialized global data (mark "C" in sym file) */ + *(.scommon*) + /* collect "large" un-initialized global data (mark "B" in sym file) */ + *(COMMON) + __common_limit = ABSOLUTE(.); + } + . = ALIGN(64); + _image_general_zi_zi_limit = ABSOLUTE(.); + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; + +} + +EXTERN("main" "config_dma" "Dec2HexStr") \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Project/Model/LDS_LZ_HDR_SIGN.lds b/board/novatek/ns02501/loader/Project/Model/LDS_LZ_HDR_SIGN.lds new file mode 100755 index 000000000000..e340bd1ea8d7 --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/LDS_LZ_HDR_SIGN.lds @@ -0,0 +1,178 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xF07C0000|0x00000000: + AT (0) + { + _load_BOOT_EXEC_start_base = .; + KEEP($LD_RESET_LIB/reset.o(.data*)); + $LD_RESET_LIB/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xF07C0000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP($LD_RESET_LIB/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + } + .LOADER_CONFIGRAM2 (0xF07C0000|0x00000000) + 0x400: + AT (0x400) + { + KEEP($LD_RESET_LIB/config_dram1_tbl.o(.rodata*)); + config_dram1_tbl_2_start_base = .; + KEEP($LD_RESET_LIB/config_dram1_2_tbl.o(.rodata*)); + } + .LOADER_CORE2_ENTRY_PROGRAM (0xF07C0000|0x00000000) + 0x600: + AT (0x600) + { + _load_core2_entry_program_start_base = .; + KEEP($LD_RESET_LIB/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + .LOADER_REMAP (0xF07C0000|0x00000000) + 0x700: + AT (0x700) + { + _load_LOADER_REMAP_start_base = .; + $LD_REMAP_LIB/$LD_DOREMAP.o(.text*); + _load_LOADER_REMAP_end_base = .; + _load_vector_exp_table_start_base = .; + KEEP($LD_RESET_LIB/exp.o(.text*)); + _load_vector_exp_table_end_base = .; + KEEP(Ctrl_Flow/bl_lowlevel_init.o(.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/configDDR.o(.text* .rodata* .data* .bss*)); + KEEP($LD_RESET_LIB/ddr_basic.o (.text* .data* .bss*)); + KEEP($LD_RESET_LIB/Delayline_K.o (.text* .rodata*)); + KEEP($LD_RESET_LIB/ddr_io.o (.text* .rodata* .data* .bss*)); + KEEP(Driver/fuart.o(.text* .data* .rodata*)); + KEEP(Driver/cc.o (.text* .data* .bss*)); + KEEP(Debug/debug.o (.text* .data* .bss*)); + KEEP($LD_COMMON_LIB/global.o (.text* .data* .bss* .rodata*)); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + + . = ALIGN(4); + .LOADER_EXEC ADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP) : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + KEEP(Driver/rtc.o(.part1*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .text $LD_BASE_ADDR: + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _loader_exec_compres_end = .; + } + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + } + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(8); /* This is MUST. Ensure ro size is 2 word aligned. */ + } + .dram_text : + AT (LOADADDR(.rodata) + SIZEOF(.rodata)) + { + _loader_dram_text_start_base = .; + * (.dram_text) + } + _loader_dram_text_cpu_addr = LOADADDR(.dram_text) + ADDR(.BOOT_EXEC); + _loader_dram_text_size = SIZEOF(.dram_text); + .data : + AT (LOADADDR(.dram_text) + SIZEOF(.dram_text)) + { + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + *(.data*) + _image_general_var_limit = .; + } + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got) } + . = ALIGN(4); + .bss : { /* locate bss at DRAM end */ + _image_general_zi_zi_base = .; + *(.bss) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + . = ALIGN(0x400); + _ttb_lv2 = .; + . = . + 0x400; + } + .common : + { + __common_base = ABSOLUTE(.); + /* collect "small" un-initialized global data (mark "C" in sym file) */ + *(.scommon*) + /* collect "large" un-initialized global data (mark "B" in sym file) */ + *(COMMON) + __common_limit = ABSOLUTE(.); + } + . = ALIGN(64); + _image_general_zi_zi_limit = ABSOLUTE(.); + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; + +} + +EXTERN("main" "config_dma" "Dec2HexStr") \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Project/Model/LDS_NM.lds b/board/novatek/ns02501/loader/Project/Model/LDS_NM.lds new file mode 100755 index 000000000000..586d5e9998ab --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/LDS_NM.lds @@ -0,0 +1,161 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xF07C0000|0x00000000: + AT (0) + { + _load_BOOT_EXEC_start_base = .; + KEEP(Reset/reset.o(.data*)); + Reset/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xF07C0000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP(Reset/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + KEEP(Reset/config_dram1_tbl.o(.rodata*)); + } + .LOADER_CONFIGRAM2 (0xF07C0000|0x00000000) + 0x200: + AT (0x200) + { + KEEP(Reset/config_dram2_tbl.o(.rodata*)); + } + .LOADER_CORE2_ENTRY_PROGRAM (0xF07C0000|0x00000000) + 0x300: + AT (0x300) + { + _load_core2_entry_program_start_base = .; + KEEP(Reset/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + .internal_stg_type (0xF07C0000|0x00000000) + 0x420: { LONG (0x46495053) } + .internal_stg_version : + AT (LOADADDR(.internal_stg_type) + SIZEOF(.internal_stg_type)) + { + _load_nand_table_start_base = .; + _load_nand_table_end_base = .; + } + .LOADER_REMAP (0xF07C0000|0x00000000) + 0x430: + AT (0x430) + { + _load_vector_int_table_start_base = .; + KEEP(Reset/isr.o(.text)); + _load_vector_int_table_end_base = .; + $LD_REMAP_LIB/$LD_DOREMAP.o(.text*); + _load_LOADER_REMAP_end_base = .; + _load_vector_exp_table_start_base = .; + KEEP(Reset/exp.o(.text*)); + _load_vector_exp_table_end_base = .; + KEEP(Reset/configDDR.o(.text*)); + KEEP(Reset/configDDR.o(.rodata*)); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + + . = ALIGN(4); + .LOADER_EXEC : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + KEEP(Driver/rtc.o(.part1*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .text : + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _loader_exec_compres_end = .; + } + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(4); /* This is MUST. Ensure ro size is word aligned. */ + } + .data 0xFF00000: + AT (LOADADDR(.rodata) + SIZEOF(.rodata)) + { + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + *(.data*) + _image_general_var_limit = .; + } + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got) } + . = ALIGN(4); + .bss : { /* locate bss at DRAM end */ + _image_general_zi_zi_base = .; + *(.bss) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + } + .common : + { + __common_base = ABSOLUTE(.); + /* collect "small" un-initialized global data (mark "C" in sym file) */ + *(.scommon*) + /* collect "large" un-initialized global data (mark "B" in sym file) */ + *(COMMON) + __common_limit = ABSOLUTE(.); + } + . = ALIGN(64); + _image_general_zi_zi_limit = ABSOLUTE(.); + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; + +} diff --git a/board/novatek/ns02501/loader/Project/Model/MakeConfig.txt b/board/novatek/ns02501/loader/Project/Model/MakeConfig.txt new file mode 100755 index 000000000000..77a1e1f7d539 --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/MakeConfig.txt @@ -0,0 +1,1254 @@ +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +#------------------------------------------------------------------------------ +# Loader version : unsigned long loader version definition +#------------------------------------------------------------------------------ +LOADER_VERSION = 0x01000001 +BL_LOADER_VER_PARAM = \ + -D_LDR_VER_="$(LOADER_VERSION)" + +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +# +# Hardware device selection +# +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#------------------------------------------------------------------------------ +# Select main chip ID +#------------------------------------------------------------------------------ +#CHIP = 520 + +#------------------------------------------------------------------------------ +# Select chip version +#------------------------------------------------------------------------------ +#CHIP_VER = A +#CHIP_VER = B + +#------------------------------------------------------------------------------ +# Select LV1 clock rate +# LV1: 491MHz / 593MHz +#------------------------------------------------------------------------------ +#LV1_CLK = 491 +#LV1_CLK = 593 + +#------------------------------------------------------------------------------ +# Select DMA clock rate +#------------------------------------------------------------------------------ +#DMA_CLOCK = LV0 +#DMA_CLOCK = LV1 + +#ifeq "$(DMA_CLOCK)" "LV1" +#ifeq "$(LV1_CLK)" "491" +#DMA_CLOCK = LV1_4 +#else +#DMA_CLOCK = LV1_5 +#endif +#endif + +ifeq "$(CHIP)" "566" + +ifeq "$(DRAM1_CLK)" "933" +DRAM1_CLK = 933 +else ifeq "$(DRAM1_CLK)" "507" +DRAM1_CLK = 507 +else ifeq "$(DRAM1_CLK)" "760" +DRAM1_CLK = 760 +else ifeq "$(DRAM1_CLK)" "400" +DRAM1_CLK = 400 +else +DRAM1_CLK = 507 +endif + +SDRAM_SIZE = 1024 + +else ifeq "$(CHIP)" "562" + +ifeq "$(DRAM1_CLK)" "666" +DRAM1_CLK = 666 +else ifeq "$(DRAM1_CLK)" "400" +DRAM1_CLK = 400 +else +DRAM1_CLK = 522 +endif + +SDRAM_SIZE = 512 + +else ifeq "$(CHIP)" "561" + +ifeq "$(DRAM1_CLK)" "400" +DRAM1_CLK = 400 +else +DRAM1_CLK = 522 +endif +SDRAM_SIZE = 512 + +else ifeq "$(CHIP)" "563" + +ifeq "$(DRAM1_CLK)" "666" +DRAM1_CLK = 666 +else ifeq "$(DRAM1_CLK)" "400" +DRAM1_CLK = 400 +else +DRAM1_CLK = 522 +endif +SDRAM_SIZE = 512 + +else ifeq "$(CHIP)" "565" + +ifeq "$(DRAM1_CLK)" "933" +DRAM1_CLK = 933 +else ifeq "$(DRAM1_CLK)" "507" +DRAM1_CLK = 507 +else ifeq "$(DRAM1_CLK)" "760" +DRAM1_CLK = 760 +else ifeq "$(DRAM1_CLK)" "400" +DRAM1_CLK = 400 +else +DRAM1_CLK = 507 +endif + +SDRAM_SIZE = 1024 + +else +endif + +#------------------------------------------------------------------------------ +# Select DRAM Size (unit: Giga bit) +#------------------------------------------------------------------------------ +#SDRAM_SIZE = 1024 +#SDRAM_SIZE = 2048 +#SDRAM_SIZE = 4096 + +#------------------------------------------------------------------------------ +# Select DRAM Type (DDR3L curruently NOT available) +#------------------------------------------------------------------------------ +#DRAM_TYPE = DDR3 +#DRAM_TYPE = DDR3L + +#------------------------------------------------------------------------------ +# Select Phy analog block LV / HV +# (Don't modify this item) +#------------------------------------------------------------------------------ +PHY_ANALOG_HV = HV + +#------------------------------------------------------------------------------ +# CPU Core version configuration +# (Don't modify this item) +#------------------------------------------------------------------------------ +#CA53_ARCH32 +#CA9 +CPU_CORE = CA9 + +#------------------------------------------------------------------------------ +# Select internal storage device +#------------------------------------------------------------------------------ +#STORAGEINT = NandEccRS +#STORAGEINT = NandSpi +#STORAGEINT = SpiFlash + +#------------------------------------------------------------------------------ +# Select external storage device +#------------------------------------------------------------------------------ +#STORAGEEXT = Sdio1 +#STORAGEEXT = Sdio2 +#STORAGEEXT = Usb + +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +# +# Software function selection +# +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#------------------------------------------------------------------------------ +# Dram range scan loader support enable +# (Don't modify this item) +#------------------------------------------------------------------------------ +DRAM_RANGE_SCAN_SUPPORT_EN = ENABLE +#DRAM_RANGE_SCAN_SUPPORT_EN = DISABLE + +#------------------------------------------------------------------------------ +# Select GUI interface display or not +#------------------------------------------------------------------------------ +# [CONFIG_RAM_GUI_EN] +# ENABLE +# DISABLE +CONFIG_RAM_GUI_EN = DISABLE + +#------------------------------------------------------------------------------ +# Set binary file build name +#------------------------------------------------------------------------------ +CHIP_SHORT = $(shell echo $(CHIP)|awk '{print substr($$0,1,3)}') +ifeq "$(CHIP)" "532QB" +BIN_NAME = LD98532A +else ifeq "$(CHIP)" "532QC" +BIN_NAME = LD98532A +else ifeq "$(CHIP)" "532QD" +BIN_NAME = LD98532A +else ifeq "$(CHIP)" "533QB" +BIN_NAME = LD98533A +else ifeq "$(CHIP)" "533QC" +BIN_NAME = LD98533A +else ifeq "$(CHIP)" "533QD" +BIN_NAME = LD98533A +else ifeq "$(CHIP)" "532BC" +BIN_NAME = LD98532A +else ifeq "$(CHIP)" "532BD" +BIN_NAME = LD98532A +else ifeq "$(CHIP)" "532BE" +BIN_NAME = LD98532A +else ifeq "$(CHIP)" "533BC" +BIN_NAME = LD98533A +else ifeq "$(CHIP)" "533BD" +BIN_NAME = LD98533A +else ifeq "$(CHIP)" "533BE" +BIN_NAME = LD98533A +endif +ifeq "$(STORAGEEXT)" "Eth" +LDR_NAME = loader +else +LDR_NAME = $(BIN_NAME) +endif +BL_UPDATE_CALNAME = FW96$(CHIP_SHORT)C.BIN +BL_CALIBRATION_FWNAME = CALFW680.BIN +TMP_NAME = LD96$(CHIP)1 + +#------------------------------------------------------------------------------ +# 1st NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_1st)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_1st_ = default_1 +else +ifeq "$(LOADER_SUPPORT_NAND_1st)" "" + _LOADER_NAND_SUPPORT_NAND_1st_ = default_1 +else + _LOADER_NAND_SUPPORT_NAND_1st_ = $(LOADER_SUPPORT_NAND_1st) +endif +endif +#------------------------------------------------------------------------------ +# 1st NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# 2nd NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_2nd)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_2nd_=default_2 +else +ifeq "$(LOADER_SUPPORT_NAND_2nd)" "" + _LOADER_NAND_SUPPORT_NAND_2nd_ = default_2 +else + _LOADER_NAND_SUPPORT_NAND_2nd_ = $(LOADER_SUPPORT_NAND_2nd) +endif +endif +#------------------------------------------------------------------------------ +# 2nd NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# 3rd NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_3rd)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_3rd_ = default_3 +else +ifeq "$(LOADER_SUPPORT_NAND_3rd)" "" + _LOADER_NAND_SUPPORT_NAND_3rd_ = default_3 +else + _LOADER_NAND_SUPPORT_NAND_3rd_ = $(LOADER_SUPPORT_NAND_3rd) +endif +endif + +#------------------------------------------------------------------------------ +# 3rd NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# Set bootloader specific strings +#------------------------------------------------------------------------------ +STR_MODEL = $(MODEL_DESC) +STR_DATE = $(shell date +%m/%d/%Y) +STR_TIME = $(shell date +%H:%M:%S) + +BL_START = "Loader NT98$(CHIP) Start ..." +BL_UPDATE_LOADERNAME = $(BIN_NAME).BIN +ifeq "$(CHIP)" "575" +BL_UPDATE_FWNAME := FW96575A.BIN +BL_UPDATE_CALNAME := FW96575C.BIN +BL_RUN_FWNAME := FW96575T.BIN +BL_CALIBRATION_FWNAME := CALFW575.BIN +BL_START = "Loader NT96$(CHIP) Start ..." +else ifeq "$(CHIP)" "570" +BL_UPDATE_FWNAME := FW96570A.BIN +BL_UPDATE_CALNAME := FW96570C.BIN +BL_RUN_FWNAME := FW96570T.BIN +BL_CALIBRATION_FWNAME := CALFW570.BIN +BL_START = "Loader NT96$(CHIP) Start ..." +else ifeq "$(CHIP)" "580" +BL_UPDATE_FWNAME := FW96580A.BIN +BL_UPDATE_CALNAME := FW96580C.BIN +BL_RUN_FWNAME := FW96580T.BIN +BL_CALIBRATION_FWNAME := CALFW580.BIN +BL_START = "Loader NT96$(CHIP) Start ..." +endif +ifeq "$(CHIP)" "523_A" +BL_UPDATE_FWNAME := FW523_AA.BIN +BL_UPDATE_CALNAME := FW523_AC.BIN +BL_RUN_FWNAME := FW523_AT.BIN +BL_CALIBRATION_FWNAME := CALFW523.BIN +BL_START = "Loader NT98$(CHIP) Start ..." +endif + +BL_WRKEY_FWNAME := WRKEY.BIN +BL_UBOOT_FWNAME := UBOOTBIN.BIN + +ifeq "$(CHIP)" "532QB" +SDRAM_SIZE = 512 +else ifeq "$(CHIP)" "532QC" +SDRAM_SIZE = 1024 +else ifeq "$(CHIP)" "532QD" +SDRAM_SIZE = 2048 +else ifeq "$(CHIP)" "533QB" +SDRAM_SIZE = 512 +else ifeq "$(CHIP)" "533QC" +SDRAM_SIZE = 1024 +else ifeq "$(CHIP)" "533QD" +SDRAM_SIZE = 2048 +else ifeq "$(CHIP)" "532BC" +SDRAM_SIZE = 1024 +else ifeq "$(CHIP)" "532BD" +SDRAM_SIZE = 2048 +else ifeq "$(CHIP)" "532BE" +SDRAM_SIZE = 4096 +else ifeq "$(CHIP)" "533BC" +SDRAM_SIZE = 1024 +else ifeq "$(CHIP)" "533BD" +SDRAM_SIZE = 2048 +else ifeq "$(CHIP)" "533BE" +SDRAM_SIZE = 4096 +endif +ifneq "$(DRAM_2ND_TBL_DETECT)" "Normal" +MODEL_DESC2 = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_2ND_CLK)_$(SDRAM_2ND_SIZE)Mb" +BL_VERSION2 = "$(MODEL_DESC2) $(STR_DATE) $(STR_TIME)" +endif + +ifeq "$(NC520_525_COMBO)" "ON" +MODEL_DESC = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE)Mb_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE)Mb_combo_NC520_DRAM1_$(NC520_COMBO_DRAM1_CLK)_$(NC520_COMBO_SDRAM_SIZE)Mb_DRAM2_NULL" +else +MODEL_DESC = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE)Mb" +endif +BL_VERSION = "$(MODEL_DESC) $(STR_DATE) $(STR_TIME)" + +#------------------------------------------------------------------------------ +# Select bootloader compression +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [BL_COMPRESS] +# ENABLE +# DISABLE +BL_COMPRESS = ENABLE + +# ------------------------------------------------------------------------------ +# Calibration part compress +# ------------------------------------------------------------------------------ +# [CALIBRTION_COMPRESS] +# ENABLE +# DISABLE +CALIBRTION_COMPRESS = DISABLE + +# ------------------------------------------------------------------------------ +# Compress part checksum after uncompress +# ------------------------------------------------------------------------------ +# [PROCESS_2ND_CHECKSUM] +# ENABLE +# DISABLE +PROCESS_2ND_CHKSUM_EN = ENABLE + + +#Do not modify this parameter 0x08 if loader compress enabled +# [UNCOMPRESSEDPART_SIZE_OFFSET] +# 0x60 +# 0x08 +UNCOMPRESSEDPART_SIZE_OFFSET = 0x08 + +#------------------------------------------------------------------------------ +# Select compressable f/w (main code) +#------------------------------------------------------------------------------ +# [MAINCODE_COMPRESS] +# ENABLE +# DISABLE +MAINCODE_COMPRESS = DISABLE + +#------------------------------------------------------------------------------ +# Select firmware image checksum validation +#------------------------------------------------------------------------------ +# [CHKFWIMAGE] +# NOCHECK +# CHECKSUM +# CRC +CHKFWIMAGE = CHECKSUM + +#------------------------------------------------------------------------------ +# Select loader flow +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [LOADER_FLOW ] +# NORMAL_LDR_FLOW +# MODULE_TST_FLOW +LOADER_FLOW = NORMAL_LDR_FLOW + +ifeq "$(LOADER_FLOW)" "NORMAL_LDR_FLOW" +BL_LOADER_FLOW = 0 +else +BL_LOADER_FLOW = 1 +endif + +BL_LOADER_FLOW_PARAM = \ +-D_BL_MAIN_SPECIAL_FLOW_=$(BL_LOADER_FLOW) + +#------------------------------------------------------------------------------ +# Select Duty calibration ENABLE / DISABLE +#------------------------------------------------------------------------------ +DUTY_CALIBRATION = DISABLE + +#------------------------------------------------------------------------------ +# Select Duty calibration type +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [DUTY_CALIBRATION_TYPE ] +# AUTO +# MANUAL +DUTY_CALIBRATION_TYPE = AUTO + +ifeq "$(DUTY_CALIBRATION_TYPE)" "AUTO" +BL_DUTY_CALIBRATION_TYPE = 0 +else +BL_DUTY_CALIBRATION_TYPE = 1 +endif + +BL_DUTY_CALIBRATION_TYPE_PARAM = \ +-D_LOADER_DUTY_CALIBRATION_TYPE_=$(BL_DUTY_CALIBRATION_TYPE) + +#------------------------------------------------------------------------------ +# Select Duty calibration LOG ENABLE / DISABLE +#------------------------------------------------------------------------------ +# [DUTY_CALIBRATION_LOG] +# ENABLE +# DISABLE +DUTY_CALIBRATION_LOG = DISABLE + +ifeq "$(LOADER_FLOW)" "MODULE_TST_FLOW" +DUTY_CALIBRATION = DISABLE +endif + +ifeq "$(DUTY_CALIBRATION)" "DISABLE" +DUTY_CALIBRATION_LOG = DISABLE +else +ifeq "$(DUTY_CALIBRATION_TYPE)" "MANUAL" +DUTY_CALIBRATION_LOG = DISABLE +endif +endif + +ifeq "$(DUTY_CALIBRATION)" "ENABLE" +BL_DUTY_CALIBRATION = 1 +else +BL_DUTY_CALIBRATION = 0 +endif + +ifeq "$(DUTY_CALIBRATION_LOG)" "ENABLE" +BL_DUTY_CALIBRATION_LOG = 1 +else +BL_DUTY_CALIBRATION_LOG = 0 +endif + +BL_DUTY_CALIBRATION_PARAM = \ +-D_LOADER_DUTY_CALIBRATION_LOG_=$(BL_DUTY_CALIBRATION_LOG)\ +-D_LOADER_DUTY_CALIBRATION_=$(BL_DUTY_CALIBRATION) + + +#------------------------------------------------------------------------------ +# Bootloader update image file name parameters +#------------------------------------------------------------------------------ +BL_UPDATE_NAME_PARAM = \ + -D_UPDATE_FW_NAME_=\"$(BL_UPDATE_FWNAME)\" \ + -D_UPDATE_LOADER_NAME_=\"$(BL_UPDATE_LOADERNAME)\" \ + -D_RUN_FW_NAME_=\"$(BL_RUN_FWNAME)\" \ + -D_UPDATE_CALFW_NAME_=\"$(BL_UPDATE_CALNAME)\"\ + -D_RUN_CAL_FW_NAME_=\"$(BL_CALIBRATION_FWNAME)\" \ + -D_WR_KEY_FW_NAME_=\"$(BL_WRKEY_FWNAME)\" \ + -D_RUN_UBOOT_NAME_=\"$(BL_UBOOT_FWNAME)\" + + +#------------------------------------------------------------------------------ +# Bootloader specific strings parameters +#------------------------------------------------------------------------------ +BL_STRINGS_PARAM = \ +-D_LOADER_VERSION_STR_=\"\\\r\\\n$(BL_VERSION)\\\r\\\n\\\r\\\n\" \ +-D_LOADER_VERSION_STR2_=\"\\\r\\\n$(BL_VERSION2)\\\r\\\n\\\r\\\n\" \ +-D_LOADER_START_STR_=\"\\\r\\\n$(BL_START)\\\r\\\n\" + +#------------------------------------------------------------------------------ +# Bootloader compression parameters +#------------------------------------------------------------------------------ +ifeq "$(BL_COMPRESS)" "ENABLE" + BL_COMPRESS_CFG = 1 + ifeq "$(CHIP)" "532QB" + RESETFLAG = LZ532 + else ifeq "$(CHIP)" "532QC" + RESETFLAG = LZ532 + else ifeq "$(CHIP)" "532QD" + RESETFLAG = LZ532 + else ifeq "$(CHIP)" "532BC" + RESETFLAG = LZ532 + else ifeq "$(CHIP)" "532BD" + RESETFLAG = LZ532 + else ifeq "$(CHIP)" "532BE" + RESETFLAG = LZ532 + else ifeq "$(CHIP)" "533QB" + RESETFLAG = LZ533 + else ifeq "$(CHIP)" "533QC" + RESETFLAG = LZ533 + else ifeq "$(CHIP)" "533QD" + RESETFLAG = LZ533 + else ifeq "$(CHIP)" "533BC" + RESETFLAG = LZ533 + else ifeq "$(CHIP)" "533BD" + RESETFLAG = LZ533 + else ifeq "$(CHIP)" "533BE" + RESETFLAG = LZ533 + else + RESETFLAG = LZ + endif + + ifeq "$(CHIP)" "532QB" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "532QC" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "532QD" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "532BC" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "532BD" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "532BE" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "533QB" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "533QC" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "533QD" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "533BC" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "533BD" + RESETCHIP = 533 + SCATTER_EXT= + else ifeq "$(CHIP)" "533BE" + RESETCHIP = 533 + SCATTER_EXT= + else + RESETCHIP = 533 + SCATTER_EXT= + endif + + ifeq "$(EXFAT_FILESYSTEM_SUPPORT)" "EXFAT" + COMMON_LIB = exFAT + else + COMMON_LIB = normal + endif + +else + BL_COMPRESS_CFG = 0 + ifeq "$(CHIP)" "560" + RESETFLAG = NM560 + else + RESETFLAG = NM + endif + + ifeq "$(CHIP)" "560" + RESETCHIP = 560 + else + RESETCHIP = 56x + endif + + ifeq "$(EXFAT_FILESYSTEM_SUPPORT)" "EXFAT" + COMMON_LIB = exFAT + else + COMMON_LIB = normal + endif +endif + +ifeq "$(MAINCODE_COMPRESS)" "ENABLE" + FWCOMPRESS_PARAM = -D_MAINCODE_COMPRESS_=1 +else + FWCOMPRESS_PARAM = -D_MAINCODE_COMPRESS_=0 +endif + +BL_COMPRESS_PARAM = \ +-D_LOADER_COMPRESSED_=$(BL_COMPRESS_CFG) + +BL_COMPRESS_PARAM_ASM = +#\ +#-PD "_LOADER_COMPRESSED_ SETA $(BL_COMPRESS_CFG)" + +#------------------------------------------------------------------------------ +# Firmware image checksum validation parameters +#------------------------------------------------------------------------------ +ifeq "$(CHKFWIMAGE)" "NOCHECK" + CHKFWIMAGE_CFG = FW_CHECK_NOCHECK +endif + +ifeq "$(CHKFWIMAGE)" "CHECKSUM" + CHKFWIMAGE_CFG = FW_CHECK_CHECKSUM +endif + +ifeq "$(CHKFWIMAGE)" "CRC" + CHKFWIMAGE_CFG = FW_CHECK_CRC +endif + +CHKFWIMAGE_PARAM = \ + -DFW_CHECK_NOCHECK=0 \ + -DFW_CHECK_CHECKSUM=1 \ + -DFW_CHECK_CRC=2 \ + -DFW_CHECK_METHOD=$(CHKFWIMAGE_CFG) + +#------------------------------------------------------------------------------ +# External Storage define +#------------------------------------------------------------------------------ + +ifeq "$(STORAGEINT)" "EMMC_NAND_COMBO" +ifeq "$(STORAGEEXT)" "NONE" +else +$(error STORAGEEXT MUST = [NONE] if STORAGEINT= [EMMC_NAND_COMBO]=>Please check [ModelConfig_EMU_EVB.txt] configuration) +endif +endif + + +ifeq "$(STORAGEEXT)" "Sdio1" + STORAGE_EXT_TYPE = STORAGE_EXT_SDIO1 +else ifeq "$(STORAGEEXT)" "Sdio2" + STORAGE_EXT_TYPE = STORAGE_EXT_SDIO2 +else ifeq "$(STORAGEEXT)" "Usb" + STORAGE_EXT_TYPE = STORAGE_EXT_USB +else ifeq "$(STORAGEEXT)" "Eth" + STORAGE_EXT_TYPE = STORAGE_EXT_ETH +else ifeq "$(STORAGEEXT)" "Uart" + STORAGE_EXT_TYPE = STORAGE_EXT_UART +else ifeq "$(STORAGEEXT)" "NONE" + STORAGE_EXT_TYPE = STORAGE_EXT_NONE +else + STORAGE_EXT_TYPE = STORAGE_EXT_UNKOWN +endif + +EXTSTRG_PARAM = \ + -DSTORAGE_EXT_UNKOWN=0 \ + -DSTORAGE_EXT_SDIO1=1 \ + -DSTORAGE_EXT_SDIO2=2 \ + -DSTORAGE_EXT_UART=3 \ + -DSTORAGE_EXT_USB=4 \ + -DSTORAGE_EXT_ETH=5 \ + -DSTORAGE_EXT_NONE=6\ + -DSTORAGE_EXT_TYPE=$(STORAGE_EXT_TYPE) + +#------------------------------------------------------------------------------ +# SPI define +#------------------------------------------------------------------------------ +ifeq "$(STORAGEINT)" "SpiFlash" + STORAGE_INT_TYPE = -DSTORAGEINT_SPI=1 +else + STORAGE_INT_TYPE = +endif + +ifeq "$(SPI_SETTING)" "SPI_4BITS" + SPI_PINMUX = SPI_PINMUX_4BITS +endif + +ifeq "$(SPI_SETTING)" "SPI_NORMAL" + SPI_PINMUX = SPI_PINMUX_NORMAL +endif + +ifeq "$(SPI_SETTING)" "SPI_8BITS" + SPI_PINMUX = SPI_PINMUX_NORMAL +endif + +SPIPINMUX_PARAM = \ + -DSPI_PINMUX_NORMAL=0 \ + -DSPI_PINMUX_4BITS=1 \ + -DSPI_PINMUX_SETTING=$(SPI_PINMUX) + +#------------------------------------------------------------------------------ +# EMMC define +#------------------------------------------------------------------------------ +ifeq "$(EMMC_SETTING)" "EMMC_8BITS" + EMMC_PINMUX = EMMC_PINMUX_8BITS +endif + +ifeq "$(EMMC_SETTING)" "EMMC_4BITS" + EMMC_PINMUX = EMMC_PINMUX_4BITS +endif + +ifeq "$(EMMC_SETTING)" "" + EMMC_PINMUX = EMMC_PINMUX_8BITS +endif + +EMMCPINMUX_PARAM = \ + -DEMMC_PINMUX_4BITS=0 \ + -DEMMC_PINMUX_8BITS=1 \ + -DEMMC_PINMUX_SETTING=$(EMMC_PINMUX) + +#------------------------------------------------------------------------------ +# Dram range scan support enable parameters +#------------------------------------------------------------------------------ +ifeq "$(DRAM_RANGE_SCAN_SUPPORT_EN)" "ENABLE" + DRAM_SCAN_EN = 1 +else + DRAM_SCAN_EN = 0 +endif + +DRAMSCAN_PARAM = -DDRAM_RANGE_SCAN_EN=$(DRAM_SCAN_EN) + +#------------------------------------------------------------------------------ +# Chip ID related parameters +#------------------------------------------------------------------------------ +ifeq "$(CHIP)" "532QB" + CHIPID = 533 + else ifeq "$(CHIP)" "532QC" + CHIPID = 533 + else ifeq "$(CHIP)" "532QD" + CHIPID = 533 + else ifeq "$(CHIP)" "532BC" + CHIPID = 533 + else ifeq "$(CHIP)" "532BD" + CHIPID = 533 + else ifeq "$(CHIP)" "532BE" + CHIPID = 533 + else ifeq "$(CHIP)" "533QB" + CHIPID = 533 + else ifeq "$(CHIP)" "533QC" + CHIPID = 533 + else ifeq "$(CHIP)" "533QD" + CHIPID = 533 + else ifeq "$(CHIP)" "533BC" + CHIPID = 533 + else ifeq "$(CHIP)" "533BD" + CHIPID = 533 + else ifeq "$(CHIP)" "533BE" + CHIPID = 533 +else +CHIPID = 533 +endif + +#------------------------------------------------------------------------------ +# Secure boot parameters +#------------------------------------------------------------------------------ +ifeq "$(SECUREBOOT)" "Secure" +SECUREBOOT_MSG = 0 +KMS_SERVER_MODEL = 0 +ifeq "$(SIGNATUREMETHOD)" "AES128" + #Secure enable + AES signature + SECURE_BOOT = 1 +else + #Secure enable + RSA signature + ifeq "$(SIGNATUREMETHOD)" "RSA2048" + SECURE_BOOT = 2 + ifeq "$(HSM_SIMULATOR)" "HSM_SIMULATOR" + KMS_SERVER_MODEL = 1 + else + KMS_SERVER_MODEL = 0 + endif + else + ifeq "$(SIGNATUREMETHOD)" "RSA2048PSS" + SECURE_BOOT = 3 + else + ifeq "$(SIGNATUREMETHOD)" "ECDSA256" + SECURE_BOOT = 4 + else + ifeq "$(SIGNATUREMETHOD)" "RSA2048PKCS1P5" + SECURE_BOOT = 6 + else + SECURE_BOOT = 5 + endif + endif + endif + endif +endif + +ifeq "$(ENCRYPTDATA)" "AES128" +ENCRYPT_DATA = 1 +#Determine encrypt data key usage(1~5) +ifeq "$(ENCRYPTDATA_KEY_SEL)" "1st_key_set" +ENCRYPTDATA_KEY_SET = 0 +endif +ifeq "$(ENCRYPTDATA_KEY_SEL)" "2nd_key_set" +ENCRYPTDATA_KEY_SET = 1 +endif +ifeq "$(ENCRYPTDATA_KEY_SEL)" "3rd_key_set" +ENCRYPTDATA_KEY_SET = 2 +endif +ifeq "$(ENCRYPTDATA_KEY_SEL)" "4th_key_set" +ENCRYPTDATA_KEY_SET = 3 +endif +ifeq "$(ENCRYPTDATA_KEY_SEL)" "5th_key_set" +ENCRYPTDATA_KEY_SET = 4 +endif +else +ENCRYPT_DATA = 0 +ENCRYPTDATA_KEY_SET = 0 +endif + +else +SECURE_BOOT = 0 +ENCRYPTDATA_KEY_SET = 0 +endif + +ifeq "$(BYPASS_SIMPLE_CHKSUM)" "ENABLE" +SIMPLE_CHKSUM_SKIP = ENABLE +else +SIMPLE_CHKSUM_SKIP = DISABLE +endif + + +ifeq "$(CIPHER_ENCRYPT_SEQ)" "ENABLE" +SIGNATURE_FIRST = 1 +else +SIGNATURE_FIRST = 0 +endif + +#------------------------------------------------------------------------------ +# DRAM ini file name generation +#------------------------------------------------------------------------------ +#ifeq "$(DRAM_TYPE)" "DDR3L" +# ifeq "$(DMA_CLOCK)" "LV0" +# $(error DDR3L only support DMA_CLOCK = LV1) +# endif +# ifeq "$(LV1_CLK)" "373" +# $(error DDR3L only support LV1_CLK = 400) +# endif +# DDR_FILE_STR = _DDR3L +#else +# DDR_FILE_STR = +#endif + +ifeq "$(DMA_CLOCK)" "LV0" + +DDR_INI_STR = $(CHIP)/51055A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE).ini +#DDR_INI2_STR = $(CHIP)/51055A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE).ini +#DDR_INI_STR = 680_$(CHIP_VER)_LV0_$(SDRAM_SIZE).ini +ifeq "$(LV1_CLK)" "491" +#DDR_INI2_STR = 680_$(CHIP_VER)_LV1_4_$(SDRAM_SIZE).ini +else +#DDR_INI2_STR = 680_$(CHIP_VER)_LV1_5_$(SDRAM_SIZE).ini +endif + +else + +ifneq "$(DRAM_2ND_TBL_DETECT)" "Normal" + +DDR_INI_STR = $(CHIP)/02501A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE).ini +#DDR_INI2_STR = $(CHIP)/02501A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE).ini + +DDR_INI_STR2 = $(CHIP)/02501A_DRAM1_$(DRAM1_2ND_CLK)_$(SDRAM_2ND_SIZE).ini +#DDR_INI2_STR2 = $(CHIP)/02501A_DRAM2_$(DRAM2_2ND_CLK)_$(SDRAM2_2ND_SIZE).ini + +2ND_INI = $(DRAM_2ND_TBL_DETECT) +GPIO_NUM = $(DRAM_2ND_TBL_DETECT_GPIO_NO) + +else + +DDR_INI_STR = $(CHIP)/02501A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE).ini +#DR_INI2_STR = $(CHIP)/02501A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE).ini + + +2ND_INI = "" +GPIO_NUM = 0 + +endif +endif + +ifeq "$(DRAM1_POWEROFF_S3)" "Enabled" +DRAM1_RST_PARAM = 1 +else +DRAM1_RST_PARAM = 0 +endif + + +ifeq "$(DRAM_SSC_ENABLE)" "Normal" +DRAM_SSC_PARAM = 0 +else ifeq "$(DRAM_SSC_ENABLE)" "1" +DRAM_SSC_PARAM = 1 +else ifeq "$(DRAM_SSC_ENABLE)" "2" +DRAM_SSC_PARAM = 2 +else ifeq "$(DRAM_SSC_ENABLE)" "3" +DRAM_SSC_PARAM = 3 +else ifeq "$(DRAM_SSC_ENABLE)" "4" +DRAM_SSC_PARAM = 4 +else ifeq "$(DRAM_SSC_ENABLE)" "5" +DRAM_SSC_PARAM = 5 +else +DRAM_SSC_PARAM = 0 +endif + +ifeq "$(DRAM_ODT)" "Normal" +ODT_SELECT = "" +else ifeq "$(DRAM_ODT)" "Enable" +ODT_SELECT = "ENABLE" +else ifeq "$(DRAM_ODT)" "Disable" +ODT_SELECT = "DISABLE" +else +ODT_SELECT = "" +endif + +ifeq "$(DRAM_TX_DRV)" "Normal" +TX_DRV = "" +else ifeq "$(DRAM_TX_DRV)" "Enable" +TX_DRV = "ENABLE" +else +TX_DRV = "" +endif + +ifeq "$(DRAM_LDO)" "Normal" +DDR_LDO = "" +else ifeq "$(DRAM_LDO)" "Enable" +DDR_LDO = "ENABLE" +else +DDR_LDO = "" +endif + +ifeq "$(MPLL_LDO)" "Normal" +PLL_LDO = "" +else ifeq "$(MPLL_LDO)" "Enable" +PLL_LDO = "ENABLE" +else +PLL_LDO = "" +endif + +ifeq "$(DRAM_RX_PAD)" "Normal" +RX_PAD = "" +else ifeq "$(DRAM_RX_PAD)" "Enable" +RX_PAD = "ENABLE" +else +RX_PAD = "" +endif + +#------------------------------------------------------------------------------- +# set the scatter file name here +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT)" "Normal" +HEADER_SIGNATURE = DISABLE +endif + +#ifeq "$(BL_COMPRESS)" "ENABLE" +#SCATTER = LDS_LZ$(SCATTER_EXT)$(SCATTER_SUFFIX).lds +#else +#SCATTER = LDS_NM.lds +#endif + +ifeq "$(BL_COMPRESS)" "ENABLE" + ifeq "$(CALIBRTION_COMPRESS)" "ENABLE" + _CALIBRATION_COMPRESS_ = 1 + _PROCESS_2ND_CHKSUM_ = 0 + ifeq "$(HEADER_SIGNATURE)" "ENABLE" + _HEADER_SIGN_ = 1 + SCATTER = LDS_LZ_CALI_HDR_SIGN.lds + else + _HEADER_SIGN_ = 0 + SCATTER = LDS_LZ_CALI.lds + endif + else + _CALIBRATION_COMPRESS_ = 0 + ifeq "$(HEADER_SIGNATURE)" "ENABLE" + _HEADER_SIGN_ = 1 + SCATTER = LDS_LZ$(SCATTER_EXT)_HDR_SIGN.lds + else + _HEADER_SIGN_ = 0 + SCATTER = LDS_LZ$(SCATTER_EXT)$(SCATTER_SUFFIX).lds + endif + + ifeq "$(PROCESS_2ND_CHKSUM_EN)" "ENABLE" + _PROCESS_2ND_CHKSUM_ = 1 + else + _PROCESS_2ND_CHKSUM_ = 0 + endif + endif +else +_CALIBRATION_COMPRESS_ = 0 +SCATTER = LDS_NM.lds +endif + +CALIBRATION_COMPRESS_PARAM = \ + -DCOMPRESS_CALIBRATION_EN=$(_CALIBRATION_COMPRESS_) + +PROCESS_2ND_CHKSUM_EN_PARAM = \ + -D_PROCESS_2ND_CHECKSUM_=$(_PROCESS_2ND_CHKSUM_) + +#------------------------------------------------------------------------------- +# set loader execution DRAM address +#------------------------------------------------------------------------------- +# 255MB +ifeq "$(SDRAM_SIZE)" "512" +LD_BASE_ADDR = 0x3C00000 +else ifeq "$(SDRAM_SIZE)" "1024" +LD_BASE_ADDR = 0x7C00000 +else ifeq "$(SDRAM_SIZE)" "2048" +LD_BASE_ADDR = 0xFC00000 +else +LD_BASE_ADDR = 0xFC00000 +endif +BL_LDADDR_PARAM = \ +-DLD_BASE_ADDR=$(LD_BASE_ADDR) + +#------------------------------------------------------------------------------- +# set loader internal storage type +#------------------------------------------------------------------------------- +BL_STORAGEINT_PARAM = \ +-D_STORAGEINT_$(STORAGEINT)_ + +#------------------------------------------------------------------------------- +# Model parameters +#------------------------------------------------------------------------------- +ifeq "$(MODEL)" "EMU_EVB" + MODEL_TYPE = _MODEL_EMU_EVB_ +endif + +ifeq "$(MODEL)" "DEMO1_EVB" + MODEL_TYPE = _MODEL_DEMO1_EVB_ +endif + +ifeq "$(MODEL)" "ARTOSYN_EVB" + MODEL_TYPE = _MODEL_ARTOSYN_EVB_ +endif +MODEL_PARAM = \ + -D_MODEL_EMU_EVB_=0 \ + -D_MODEL_DEMO1_EVB_=1 \ + -D_MODEL_ARTOSYN_EVB_=2 \ + -D_MODEL_DSC_=$(MODEL_TYPE) + +#------------------------------------------------------------------------------- +# uboot encrypt binary or not parameters +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT_DECRYPT_UBOOT)" "Normal" + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_DISABLE_ +else ifeq "$(SECUREBOOT_DECRYPT_UBOOT)" "Secure" + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_ENABLE_ +else + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_DISABLE_ +endif + +SECURE_DECRYPT_UBOOT_PARAM = \ + -D_SECURE_DECRYPT_UBOOT_DISABLE_=0 \ + -D_SECURE_DECRYPT_UBOOT_ENABLE_=1 \ + -DSECURE_DECRYPT_UBOOT=$(UBOOT_DECRYPT_TYPE) + +#------------------------------------------------------------------------------- +# optee parameters +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT_DECRYPT_OPTEE)" "Normal" + OPTEE_DECRYPT_TYPE = _SECURE_DECRYPT_OPTEE_DISABLE_ +else ifeq "$(SECUREBOOT_DECRYPT_OPTEE)" "Secure" + OPTEE_DECRYPT_TYPE = _SECURE_DECRYPT_OPTEE_ENABLE_ +else + OPTEE_DECRYPT_TYPE = _SECURE_DECRYPT_OPTEE_DISABLE_ +endif + + +SECURE_DECRYPT_OPTEE_PARAM = \ + -D_SECURE_DECRYPT_OPTEE_DISABLE_=0 \ + -D_SECURE_DECRYPT_OPTEE_ENABLE_=1 \ + -DSECURE_DECRYPT_OPTEE_OS=$(OPTEE_DECRYPT_TYPE) + + +#------------------------------------------------------------------------------- +# optee or uboot digital signature parameters +#------------------------------------------------------------------------------- +ifeq "$(SIGNATUREMETHOD)" "AES128" +# => AES signature +OPTEE_UBOOT_DIGITAL_SIGNATURE_TYPE = _UBOOT_OPTEE_SIGNATURE_USE_AES128_ +else ifeq "$(SIGNATUREMETHOD)" "ECDSA256" +# => ecdsa signature +OPTEE_UBOOT_DIGITAL_SIGNATURE_TYPE = _UBOOT_OPTEE_SIGNATURE_USE_ECDSA_ +else +# => RSA signature +OPTEE_UBOOT_DIGITAL_SIGNATURE_TYPE = _UBOOT_OPTEE_SIGNATURE_USE_RSA_ +endif + +OPTEE_UBOOT_SIGNATURE_PARAM = \ + -D_UBOOT_OPTEE_SIGNATURE_USE_RSA_=0 \ + -D_UBOOT_OPTEE_SIGNATURE_USE_AES128_=1 \ + -D_UBOOT_OPTEE_SIGNATURE_USE_ECDSA_=2 \ + -DSECURE_SIGNATURE_TYPE=$(OPTEE_UBOOT_DIGITAL_SIGNATURE_TYPE) + +#------------------------------------------------------------------------------- +# DTR support +#------------------------------------------------------------------------------- +ifeq "$(SPINOR_DTR)" "ENABLE" +SPINOR_USE_DTR = 1 +else +SPINOR_USE_DTR = 0 +endif + +NOR_DTR_PARAM = \ + -D_NOR_DTR_PARAM_=$(SPINOR_USE_DTR) + +#------------------------------------------------------------------------------- +# optee or uboot digital signature parameters +#------------------------------------------------------------------------------- +ifeq "$(CHIP)" "532QB" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_0_ +else ifeq "$(CHIP)" "532QC" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_0_ +else ifeq "$(CHIP)" "532QD" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_0_ +else ifeq "$(CHIP)" "533QB" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_2_ +else ifeq "$(CHIP)" "533QC" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_2_ +else ifeq "$(CHIP)" "533QD" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_2_ +else ifeq "$(CHIP)" "532BC" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_1_ +else ifeq "$(CHIP)" "532BD" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_1_ +else ifeq "$(CHIP)" "532BE" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_1_ +else ifeq "$(CHIP)" "533BC" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_1_ +else ifeq "$(CHIP)" "533BD" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_1_ +else ifeq "$(CHIP)" "533BE" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_1_ +endif + +CARDDET_PIN_PARAM = \ + -D_CARD_DETECT_TYPE_0_=0 \ + -D_CARD_DETECT_TYPE_1_=1 \ + -D_CARD_DETECT_TYPE_2_=2 \ + -DCARD_DETECT_PIN=$(CARD_DETECT_PIN_TYPE) + +ifeq "$(DDR_TREFI)" "Extend" +DDR_TREFI_PARAM = 1 +else +DDR_TREFI_PARAM = 0 +endif + +#------------------------------------------------------------------------------- +# rtos parameters +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT_DECRYPT_RTOS)" "Normal" + RTOS_DECRYPT_TYPE = _SECURE_DECRYPT_RTOS_DISABLE_ +else ifeq "$(SECUREBOOT_DECRYPT_RTOS)" "Secure" + RTOS_DECRYPT_TYPE = _SECURE_DECRYPT_RTOS_ENABLE_ +else + RTOS_DECRYPT_TYPE = _SECURE_DECRYPT_RTOS_DISABLE_ +endif + +SECURE_DECRYPT_RTOS_PARAM = \ + -D_SECURE_DECRYPT_RTOS_DISABLE_=0 \ + -D_SECURE_DECRYPT_RTOS_ENABLE_=1 \ + -DSECURE_DECRYPT_RTOS=$(RTOS_DECRYPT_TYPE) + +#------------------------------------------------------------------------------- +# fdt parameters +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT_DECRYPT_FDT)" "Normal" + FDT_DECRYPT_TYPE = _SECURE_DECRYPT_FDT_DISABLE_ +else ifeq "$(SECUREBOOT_DECRYPT_FDT)" "Secure" + FDT_DECRYPT_TYPE = _SECURE_DECRYPT_FDT_ENABLE_ +else + FDT_DECRYPT_TYPE = _SECURE_DECRYPT_FDT_DISABLE_ +endif + +SECURE_DECRYPT_FDT_PARAM = \ + -D_SECURE_DECRYPT_FDT_DISABLE_=0 \ + -D_SECURE_DECRYPT_FDT_ENABLE_=1 \ + -DSECURE_DECRYPT_FDT=$(FDT_DECRYPT_TYPE) + +#------------------------------------------------------------------------------- +# linux-kernel parameters +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT_DECRYPT_KERNEL)" "Normal" + KERNEL_DECRYPT_TYPE = _SECURE_DECRYPT_KERNEL_DISABLE_ +else ifeq "$(SECUREBOOT_DECRYPT_KERNEL)" "Secure" + KERNEL_DECRYPT_TYPE = _SECURE_DECRYPT_KERNEL_ENABLE_ +else + KERNEL_DECRYPT_TYPE = _SECURE_DECRYPT_KERNEL_DISABLE_ +endif + +SECURE_DECRYPT_KERNEL_PARAM = \ + -D_SECURE_DECRYPT_KERNEL_DISABLE_=0 \ + -D_SECURE_DECRYPT_KERNEL_ENABLE_=1 \ + -DSECURE_DECRYPT_KERNEL=$(KERNEL_DECRYPT_TYPE) + +#------------------------------------------------------------------------------- +# sensor parameters +#------------------------------------------------------------------------------- +SENSOR_PARAM = \ + -D_$(SENSOR1)_ \ + -D_SENSOR1_=$(SENSOR1) + +#------------------------------------------------------------------------------- +# fastboot support +#------------------------------------------------------------------------------- +ifeq "$(FASTBOOT)" "ENABLE" +FASTBOOT_PARAM = -D_FASTBOOT_ +endif + +#------------------------------------------------------------------------------- +# direct boot support +#------------------------------------------------------------------------------- +ifeq "$(DIRECT_BOOT)" "ENABLE" +DIRECT_BOOT_PARAM = -D_DIRECT_BOOT_ +endif + +#------------------------------------------------------------------------------- +# Low Power support +#------------------------------------------------------------------------------- +ifeq "$(Low_Pwr)" "ENABLE" +Low_Pwr_PARAM = -D_Low_Pwr_ +endif + +#------------------------------------------------------------------------------- +# DDR SIZE All in one support +#------------------------------------------------------------------------------- +ifeq "$(DDR_SIZE_ALL_IN_ON)" "ENABLE" +DDR_SIZE_ALL_IN_ON_PARAM = -D_DDR_SIZE_ALL_IN_ON_ +endif + +#------------------------------------------------------------------------------- +# dbg address scan loader support +#------------------------------------------------------------------------------- +ifeq "$(DBG_LD)" "DISABLE" +DBG_LOADER_ON = 0 +RESETCHIP = 533 +else +DBG_LOADER_ON = 1 +RESETCHIP = 533_dbg +endif + +DBG_LD_PARAM = \ + -D_DBG_LOADER_ON_=$(DBG_LD) + +#------------------------------------------------------------------------------- +# loader size select +#------------------------------------------------------------------------------- + + +ENLARGE_LD_PARAM = \ + -D_ENLARGE_LOADER_ON_=$(ENLARGE_LD) + + +ifeq "$(GZIP_ENGINE_API)" "ON" +COMPRESS_ALG = gz +else +COMPRESS_ALG = lz +endif \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Project/Model/Makefile b/board/novatek/ns02501/loader/Project/Model/Makefile new file mode 100755 index 000000000000..fb1c46c95d0f --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/Makefile @@ -0,0 +1,135 @@ +#---------------------------------------------------------------------- +# set the ROOT directory here +#---------------------------------------------------------------------- +ROOT_DIR = ../.. + +#---------------------------------------------------------------------- +# include make config file +#---------------------------------------------------------------------- +include ModelConfig.txt +include ModelConfig_$(MODEL).txt +include MakeConfig.txt + +#---------------------------------------------------------------------- +# set the project name here +#---------------------------------------------------------------------- +PRJ_NAME = Loader$(CHIP) + +#---------------------------------------------------------------------- +# set loader execution DRAM address +#---------------------------------------------------------------------- +ifeq "$(SDRAM_SIZE)" "1024" +# 1Gb*2 => 256MB => 0x1000_0000 +LD_BASE_ADDR = 0xF000000 +else ifeq "$(SDRAM_SIZE)" "2048" +# 2Gb*2 => 512MB => 0x2000_0000 +LD_BASE_ADDR = 0x1F000000 +else +# 4Gb*2 => 1024MB => 0x4000_0000 +LD_BASE_ADDR = 0x3F000000 +endif + +ifeq "$(LOADER_DRAM_ADDR)" "" +LD_BASE_ADDR = 0x1000000 +else +LD_BASE_ADDR = $(LOADER_DRAM_ADDR) +endif + +#---------------------------------------------------------------------- +# set the include directory here +#---------------------------------------------------------------------- +INC_DIR = . \ + ../../Include + +#---------------------------------------------------------------------- +# add/delete the project assembly files here +#---------------------------------------------------------------------- +#ASM = Src/reset.S \ +#Src/remap.S + + + + +#---------------------------------------------------------------------- +# add/delete the project C source files here +#---------------------------------------------------------------------- +SRC = \ + Src/prj_main.c \ + Src/USB/usb_update.c \ + Src/UART/uart_upgrade.c \ + +#---------------------------------------------------------------------- +# set the image output directory here +#---------------------------------------------------------------------- +IMG_BASE_DIR = $(PRJ_NAME)_Data + +#---------------------------------------------------------------------- +# set the library directory here +#---------------------------------------------------------------------- +LIB_BASE_DIR = ../../LIB + +#---------------------------------------------------------------------- +# set the library directory here +#---------------------------------------------------------------------- +ARC_BASE_DIR = $(ROOT_DIR)/ARC + +#---------------------------------------------------------------------- +# add additional C and assembly flags here, for example, -O2 +#---------------------------------------------------------------------- +C_DEFINE_EXT = \ + $(MODEL_PARAM) \ + $(BL_UPDATE_NAME_PARAM) \ + $(BL_STRINGS_PARAM) \ + $(BL_COMPRESS_PARAM) \ + $(CHKFWIMAGE_PARAM) \ + $(FWCOMPRESS_PARAM) \ + $(BL_LOADER_VER_PARAM) \ + $(BL_LDADDR_PARAM) \ + $(EXTSTRG_PARAM) \ + $(STORAGE_INT_TYPE)\ + $(SPIPINMUX_PARAM)\ + $(EMMCPINMUX_PARAM)\ + $(DRAMSCAN_PARAM)\ + $(BL_DUTY_CALIBRATION_PARAM)\ + $(BL_DUTY_CALIBRATION_TYPE_PARAM)\ + $(BL_LOADER_FLOW_PARAM) \ + $(BL_STORAGEINT_PARAM) \ + $(SECURE_DECRYPT_UBOOT_PARAM) \ + $(SECURE_DECRYPT_OPTEE_PARAM) \ + $(CARDDET_PIN_PARAM) \ + $(SENSOR_PARAM) \ + $(NOR_DTR_PARAM) \ + $(FASTBOOT_PARAM) \ + $(Low_Pwr_PARAM) \ + $(DDR_SIZE_ALL_IN_ON_PARAM) \ + $(ENLARGE_LD_PARAM) \ + $(DIRECT_BOOT_PARAM) \ + +CFLAGS_R = $(C_DEFINE_EXT) +CFLAGS_D = $(C_DEFINE_EXT) + +ASMFLAGS_R = \ + $(BL_COMPRESS_PARAM_ASM) + +ASMFLAGS_D = \ + $(BL_COMPRESS_PARAM_ASM) + +GCCFLAGS = \ + $(MODEL_PARAM) \ + $(BL_UPDATE_NAME_PARAM) \ + $(BL_STRINGS_PARAM) \ + $(BL_COMPRESS_PARAM) \ + $(CHKFWIMAGE_PARAM) \ + $(FWCOMPRESS_PARAM) \ + $(BL_LOADER_VER_PARAM) \ + $(STORAGE_INT_TYPE)\ + $(DRAMSCAN_PARAM)\ + $(BL_DUTY_CALIBRATION_PARAM)\ + $(BL_DUTY_CALIBRATION_TYPE_PARAM)\ + $(BL_LOADER_FLOW_PARAM) + +#---------------------------------------------------------------------- +# include common parts of the makefile +#---------------------------------------------------------------------- +MAKE_COMMON_DIR = ../../MakeCommon +include $(MAKE_COMMON_DIR)/OutputImg.txt diff --git a/board/novatek/ns02501/loader/Project/Model/ModelConfig.txt b/board/novatek/ns02501/loader/Project/Model/ModelConfig.txt new file mode 100755 index 000000000000..1ccf9d20aee3 --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/ModelConfig.txt @@ -0,0 +1,5 @@ +#---------------------------------------------------------------------- +# Set model here +#---------------------------------------------------------------------- +# EMU_EVB => Model config as NT9856x +MODEL = EMU_EVB \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Project/Model/ModelConfig_EMU_EVB.txt b/board/novatek/ns02501/loader/Project/Model/ModelConfig_EMU_EVB.txt new file mode 100755 index 000000000000..fc9754982789 --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/ModelConfig_EMU_EVB.txt @@ -0,0 +1,349 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN + +# Ext => DRAM is external die => Need user configuration +# KGD => DRAM is internal die => Depend on specific chip (force fixed dram size) +#============+====================+=========================+ +# chip_name |DDR1 size | DDR1 clock | +#============+====================+=========================+ +# 532/533QB |512(Mb) | 666 | +#============+====================+=========================+ +# 532QC/QD |1024/2048(Mb) | 400,507,666,793,933,1066| +#============+====================+=========================+ +# 533QC/QD |1024/2048(Mb) | 400,507,666,793,933,1066| +#============+====================+=========================+ +# 532BC/BD/BE|1024/2048/4096(Mb) | 400,507,666,793,933,1066| +#============+====================+=========================+ +# 533BC/BD/BE|1024/2048/4096(Mb) | 400,507,666,793,933,1066| +#============+====================+=========================+ +# [CHIP] : main chip ID +#532QB +#532QC +#532QD +#533QB +#533QC +#533QD +#532BC +#532BD +#532BE +#533BC +#533BD +#533BE +CHIP = 533QD + +# [CHIP_VER] : chip version +# A +# B +# CHIP_VER = A + +# [DRAM1_CLK] : DRAM1(16-bit) clock rate +# 400 +# 507 +# 666 +# 793 +# 933 +# 1066 +DRAM1_CLK = 1066 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit)(Auto Calculate) +# 512(Mb) +# 1024 +# 2048 +# 4096 +# SDRAM_SIZE = 4096 + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +# DRAM1_POWEROFF_S3 = Normal + +# [DRAM_TYPE] : DRAM Type(Auto recognize) +# DDR2 +# DDR3 +# DDR3L +# DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO(Not support) +# Normal (No GPIO detected) +# 0 (C_GPIO) +# 1 (HSI_GPI0) +# 2 (S_GPIO) +# 3 (P_GPIO) +# 4 (DSI_GPIO) +# 5 (L_GPIO) +# 6 (D_GPIO) +# 7 (A_GPI0) +# 8 (Reserved) +#DRAM_2ND_TBL_DETECT = Normal + +# [DRAM_2ND_TBL_DETECT_GPIO_NO] : enable DRAM 2nd table detect by X_GPIO_n(Not support) +# where +# C_GPIO --> n=0~24 +# HSI_GPI0 --> n=0~11 +# S_GPIO --> n=0~8 +# P_GPIO --> n=0~25 +# DSI_GPIO --> n=0~10 +# L_GPIO --> n=0~9 +# D_GPIO --> n=0~7 +# A_GPIO --> n=0~3 +#DRAM_2ND_TBL_DETECT_GPIO_NO = 0 + +# [DRAM1_2ND_CLK] : DRAM1(16-bit) 2nd table clock rate(Not support) +# 400 +# 507 +# 522 +# 666 +# 760 +# 933 +# 1066 +#DRAM1_2ND_CLK = 933 + +# [SDRAM_2ND_SIZE] : 2nd table DRAM Size (unit: Giga bit)(Not support) +# 1024 +# 2048 +# 4096 +# SDRAM_2ND_SIZE = 4096 + +# [DDR_TREFI] : ddr refresh time select by temparature range +# Normal(3.9 us) +# Extend(1.95 us) +DDR_TREFI = Normal + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum(Not support Yet) +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_ODT] : enable DRAM ODT or not +# Normal +# Enable +# Disable +DRAM_ODT = Normal + +# [STORAGEINT] : internal storage device +# NandSpi >>>[Use SPI-NAND flash ondie ECC] +# NandEccBCH >>>[Use SPI-NAND and SoC BCH ECC] +# SpiFlash >>>[Use SPI NOR flash] +# EMMC +# EMMC_NAND_COMBO >>>[eMMC & NandSpi 2 in 1 & STORAGEEXT must choose NONE]<<< +STORAGEINT = SpiFlash + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [EMMC_SETTING] : EMMC pinmux setting (Valid when STORAGEINT is EMMC) +# EMMC_4BITS +# EMMC_8BITS +EMMC_SETTING = EMMC_8BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth >>>[During this option => STORAGEINT MUST not choose @EMMC_NAND_COMBO]<<< +# Uart +STORAGEEXT = Sdio1 + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# ECDSA256 +# RSA2048 +# RSA2048PSS +# RSA2048PKCS1P5 +SIGNATUREMETHOD = ECDSA256 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal + +# [Bypass simple checksum] : During SIGNATUREMETHOD == RSA or AES and ENCRYPTDATA == Normal +# Choose ENABLE will let cypher loader(data area MUST be plan text) can run both in normal IC and secure enable IC +# at the same time +# DISABLE +# ENABLE +BYPASS_SIMPLE_CHKSUM = DISABLE + +# [ENCRYPTIONDATA key selection] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure && ENCRYPTDATA == AES128) +# 1st_key_set (default) +# 2nd_key_set +# 3rd_key_set +# 4th_key_set +# 5th_key_set +ENCRYPTDATA_KEY_SEL = 1st_key_set + +# [Header signature selection] : Is processing header signature verify? +# DISABLE(default) +# ENABLE +HEADER_SIGNATURE = DISABLE + +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +ifeq "$(SIGNATUREMETHOD)" "RSA2048" +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else + ifeq "$(SIGNATUREMETHOD)" "RSA2048PSS" + RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt + RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt + else + ifeq "$(SIGNATUREMETHOD)" "RSA2048PKCS1P5" + RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt + RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt + else + RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/ecdsa_pub.key + RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/ecdsa_priv.key + endif + endif + endif +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x1000000 +LOADER_DRAM_ADDR = 0x1000000 + +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader decrypt optee option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_OPTEE] : Loader decrypt optee or not (Depend on optee build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_OPTEE = Normal + +#==============================================================================# +# loader decrypt rtos option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_RTOS] : Loader decrypt rtos or not +# Normal +# Secure +SECUREBOOT_DECRYPT_RTOS = Normal + +#==============================================================================# +# loader decrypt fdt option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_FDT] : Loader decrypt fdt or not +# Normal +# Secure +SECUREBOOT_DECRYPT_FDT = Normal + +#==============================================================================# +# loader decrypt linux-kernel option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_KERNEL] : Loader decrypt linux-kernel or not +# Normal +# Secure +SECUREBOOT_DECRYPT_KERNEL = Normal + +#==============================================================================# +# exFAT support(Once customer want to use exFAT, need get license from $MS ) # +#==============================================================================# +# [exFAT] : Loader support exFAT or not +# NONE +# EXFAT +EXFAT_FILESYSTEM_SUPPORT = NONE + +#==============================================================================# +# NOR DTR support(only available while STORAGEINT = SpiFlash && FASTBOOT = ENABLE ENABLE) # +# !!!!! WARNING !!!!! flash, ddr hardware spec must meet requirement !!!!! # +#==============================================================================# +# [NOR_DTR] : use NOR DTR support for fast boot +# DISABLE +# ENABLE +SPINOR_DTR = DISABLE + + +#==============================================================================# +# SPI-NAND(NOR)/eMMC use direct mode # +#==============================================================================# +# [DIRECT MODE] : Internal storage use direct mode +# DISABLE : PIO mode +# ENABLE : Direct mode +INT_STRG_DIR_MODE = DISABLE + +#==============================================================================# +# fastboot support (with fast sensor) # +#==============================================================================# +# DISABLE +# ENABLE +FASTBOOT = DISABLE + +#==============================================================================# +# direct boot support # +#==============================================================================# +# [DIRECT_BOOT] : Loader boots Linux directly but conflicts with fastboot +# DISABLE +# ENABLE +DIRECT_BOOT = DISABLE + +#==============================================================================# +# Low Power support(only support DDR3-800 and use PLL11) # +#==============================================================================# +# DISABLE +# ENABLE +Low_Pwr = DISABLE + +#==============================================================================# +# DDR SIZE All in one support(auto check 1G/2G/4G size) # +#==============================================================================# +# DISABLE +# ENABLE +DDR_SIZE_ALL_IN_ON = DISABLE + +#==============================================================================# +# debug loader support # +#==============================================================================# +# [DBG_LD] : enlarge loader size for scan address and dq +# DISABLE +# ENABLE +DBG_LD = DISABLE + + +#==============================================================================# +# loader size select # +#==============================================================================# +# [ENLARGE_LD] : enlarge loader size for user coding usage, (the boot time will increase) +# DISABLE(Origin Size) +# ENABLE(64KB Max Size) +ENLARGE_LD = DISABLE + +#==============================================================================# +# [Cipher text encrypt sequence] : (just option for back up) # +# Caution Once selection ENABLE -> Specific SoC's fuse bit need programmed # +#==============================================================================# +# DISABLE(default): signature -> encrypt data as cypher text(general usage) +# ENABLE : encrypt data as cypher text -> signature +CIPHER_ENCRYPT_SEQ = DISABLE \ No newline at end of file diff --git a/board/novatek/ns02501/loader/Project/Model/Src/UART/uart_upgrade.c b/board/novatek/ns02501/loader/Project/Model/Src/UART/uart_upgrade.c new file mode 100755 index 000000000000..2c1371014a46 --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/Src/UART/uart_upgrade.c @@ -0,0 +1,212 @@ +#include +#include "constant.h" +#include "uart_upgrade.h" +#include "scsi_op.h" +#include "debug.h" +#include "debug.h" +#include "global.h" + + +#define _THUMB2 __attribute__((target("thumb"))) + +UART_Verify_CB guiUARTCheck_cb; +UART_Vendor_CB guiUARTVendor_cb; +static int uartrom_exit = 0; +static unsigned int chipid = 0; +static CONSOLE_OBJ *m_console = NULL; +static INT32U nvtuart_opened = 1; + +_THUMB2 static INT32U calc_sum(INT32U dat0, INT32U dat1, INT32U dat2, INT32U dat3) +{ + INT32U sum = 0; + + sum = (dat0 & 0xFFFF) + ((dat0 >> 16)) + (dat1 & 0xFFFF) + ((dat1 >> 16)) + + (dat2 & 0xFFFF) + ((dat2 >> 16)) + (dat3 & 0xFFFF) + ((dat3 >> 16)) + 28; + + return sum & 0xFFFF; +} + +_THUMB2 static INT32U make_sum(INT32U dat0, INT32U dat1, INT32U dat2, INT32U dat3) +{ + INT32U sum = 0; + + sum = (dat0 & 0xFFFF) + ((dat0 >> 16)) + (dat1 & 0xFFFF) + ((dat1 >> 16)) + + (dat2 & 0xFFFF) + ((dat2 >> 16)) + (dat3 & 0xFFFF) + ((dat3 >> 16)) + 28; + + sum = (~sum + 1) & 0xFFFF; + + return sum; +} + +_THUMB2 static int recv_data(char *p, unsigned int len) +{ + while (len) { + *p = m_console->getc(); + p++; + len--; + } + return 0; +} + +_THUMB2 static int send_data(char *p, unsigned int len) +{ + while (len) { + m_console->putc(*p); + p++; + len--; + } + return 0; +} + +_THUMB2 static void uart_send_csw(INT32U *cdb, int er) +{ + char *p_cdb = (char *)cdb; + p_cdb[IDX_CDB_UART_STATUS_ER] = er; + + unsigned int sum = make_sum(cdb[0], cdb[1], cdb[2], (cdb[3] & 0xFFFF)); + cdb[3] |= sum << 16; + + send_data((char *)cdb, sizeof(INT32U) * 4); +} + + +_THUMB2 static int uart_cmd(INT32U *cdb) +{ + unsigned int cmd_id = ((cdb[0] >> 8) & 0xFF); + unsigned int insize = ((cdb[1] >> 16) & 0xFFFF) + ((cdb[2] & 0xFFFF) << 16); + unsigned int tmp1, tmp2; + + switch (cmd_id) { + case SCSIOP_OUT_OPEN_DEVICE: + nvtuart_opened = 1; + uart_send_csw(cdb, 0); + break; + + case SCSIOP_IN_WAIT_DONE: + uartrom_exit = 1; + uart_send_csw(cdb, 0); + break; + + case SCSIOP_IN_IS_NVT: + chipid = uart_read_reg(TOP_CTRL_VERSION_REG); + uart_send_csw(cdb, 0); + send_data((char *)&chipid, sizeof(chipid)); + break; + + case SCSIOP_OUT_ADDR_WRITE: + tmp1 = ((cdb[0] >> 16) & 0xFFFF) + ((cdb[1] & 0xFFFF) << 16); //addr + tmp2 = ((cdb[1] >> 16) & 0xFFFF) + ((cdb[2] & 0xFFFF) << 16); //data + *(INT32U *)tmp1 = tmp2; + __asm__ __volatile__("dsb\n\t"); + uart_send_csw(cdb, 0); + break; + + case SCSIOP_IN_ADDR_READ: + tmp1 = ((cdb[0] >> 16) & 0xFFFF) + ((cdb[1] & 0xFFFF) << 16); //addr + tmp2 = *(INT32U *)tmp1; + __asm__ __volatile__("dsb\n\t"); + uart_send_csw(cdb, 0); + send_data((char *)&tmp1, sizeof(tmp2)); //repeat addr + send_data((char *)&tmp2, sizeof(tmp2)); //reply data + break; + + default: + if (guiUARTCheck_cb != NULL) { + NVT_SCSI_CBW cbw; + unsigned int OutDataBuf = 0; + utl_memset(&cbw, 0, sizeof(cbw)); + cbw.dCBWDataTransferLength = insize; + utl_memcpy(cbw.CBWCB, cdb, 4 * sizeof(unsigned int)); + int er = guiUARTCheck_cb((unsigned int)&cbw, (unsigned int *)&OutDataBuf, (unsigned int *)&insize); + utl_memcpy(cdb, cbw.CBWCB, 4 * sizeof(unsigned int)); + if (er != 0) { + uart_send_csw(cdb, 1); + return -1; + } else { + uart_send_csw(cdb, 0); + } + if ((cmd_id & 0x80)) { + //dir-in + guiUARTVendor_cb((unsigned int)&cbw); + if (insize) { + send_data((char *)OutDataBuf, insize); + } + } else { + //dir-out + if (insize) { + recv_data((char *)OutDataBuf, insize); + } + guiUARTVendor_cb((unsigned int)&cbw); + } + } + break; + + } + return 0; +} + +_THUMB2 static void uart_upgrade_routine(void) +{ + static int idx_cdb = 0; + static INT32U cdb[4] = {0}; + + char *p_cdb = (char *)cdb; + + p_cdb[idx_cdb++] = m_console->getc(); + + // loop to cdb fill 16 bytes + if (idx_cdb < 16) { + return ; + } + + idx_cdb = 0; // reset idx + + // Parse SCSI command + if (!(((cdb[0] & 0xFF) == SCSI_OP_SET0) || ((cdb[0] & 0xFF) == SCSI_OP_SET1) || ((cdb[0] & 0xFF) == SCSI_OP_SET2))) { + uart_send_csw(cdb, 1); + debug_err("uart opset ng.\r\n"); + } + + if (calc_sum(cdb[0], cdb[1], cdb[2], cdb[3]) != 0) { + uart_send_csw(cdb, 1); + debug_err("uart cmd sum ng.\r\n"); + return; + } + + uart_cmd(cdb); +} + +_THUMB2 void uart_upgrade_procedure() +{ + //if(utl_get_chipversion() != CHIPVER_A) { + m_console = get_uart_object(CONSOLE_UART0); + // } else { + // m_console = get_uart_object(CONSOLE_UART1); + //} + + m_console->hook(); + + while (1) { + + if (uartrom_exit > 0) { + break; + } + + uart_upgrade_routine(); + } + + uartrom_exit = 0; + +} + +_THUMB2 void loader_installUART_Verify_CB(UART_Verify_CB callback) +{ + guiUARTCheck_cb = callback; +} + +_THUMB2 void loader_installUART_Vendor_CB(UART_Vendor_CB callback) +{ + guiUARTVendor_cb = callback; +} + + diff --git a/board/novatek/ns02501/loader/Project/Model/Src/UART/uart_upgrade.h b/board/novatek/ns02501/loader/Project/Model/Src/UART/uart_upgrade.h new file mode 100755 index 000000000000..499f05d303b1 --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/Src/UART/uart_upgrade.h @@ -0,0 +1,101 @@ +#ifndef __UART_UPGRADE_H +#define __UART_UPGRADE_H + +/** + Open NVT Device + + The commands except SCSIOP_IN_IS_NVT can be run if open device success. + If not open first, the operation commands got CSW Status 0x1 means command failed. + + @DATA_PHASE: None. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_OUT_OPEN_DEVICE 0x01C0 + + +/** + Send Write Loader + + The Write Address @ CDB[2]~[5]; + For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE + CDB[6]~[16] shall follow checksum rule. Content is dont care. + + @DATA_PHASE: OUT. Size is at CBW[8]~[11] DataTransferLength. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_OUT_WRLOADER 0x02C0 + +/** + Address WRITE WORD (DRAM/REG/SRAM dont care) + + The Write Address @ CDB[2]~[5]; + For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE + The Write DATA @ CDB[6]~[9]. + For example address 0x12345678 shall fill CDB[6]=0x78 CDB[7]=0x56 CDB[8]=0x34 CDB[9]=0x12 + CDB[10]~[15] shall follow checksum rule. Content is dont care. + + @DATA_PHASE: None. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_OUT_ADDR_WRITE 0x03C0 + +/** + Address READ WORD (DRAM/REG/SRAM dont care) + + The READ Address @ CDB[2]~[5]; + For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE + CDB[6]~[15] shall follow checksum rule. Content is dont care. + + @DATA_PHASE: IN 8 bytes return. DATA[0]~[3] is repeat CDB address. Read out DATA is [3] ~[7]. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_IN_ADDR_READ 0x83C0 + + +/** + Ask if NVT Device + + CDB[2]~[15] shall follow checksum rule + + @DATA_PHASE: IN 4 bytes return; The value 0x81200000 woule be return for 98321. <8321 = 0x2081> If checksum fail, the 0x0 would be returned. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. + +*/ +#define UARTOP_IN_IS_NVT 0x81C0 // ???O???O???a?? device (?o?????n?? SCSIOP_IN_OPEN_DEVICE) + + +/** + End USB ROM CODE. + + Exit USB ROM code after receiving this command. The checksum must be correct. + + CDB[2]~[15] shall follow checksum rule + + @DATA_PHASE: None. + @CSW_PHASE status code: 0 is success and end usb rom. 0x1 means checksum failed. +*/ +#define UARTOP_IN_WAIT_DONE 0x82C0 + +#define TOP_CTRL_VERSION_REG (0xF00100F0) + + +typedef int (*UART_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); ///< Callback for verify the Vendor Command is supported or not +typedef int (*UART_Vendor_CB)(unsigned int pCmdBuf); ///< Callback for Vendor Command processing + + +extern void loader_installUARTCB(UART_Verify_CB callback); +extern void uart_upgrade_procedure(void); + +static __inline unsigned int uart_read_reg(unsigned int reg) +{ + return *((volatile unsigned int *)reg); +} + +static __inline void uart_write_reg(unsigned int reg, unsigned int value) +{ + *((volatile unsigned int *)reg) = value; +} + + + +#endif diff --git a/board/novatek/ns02501/loader/Project/Model/Src/USB/usb_update.c b/board/novatek/ns02501/loader/Project/Model/Src/USB/usb_update.c new file mode 100755 index 000000000000..3f75984c656c --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/Src/USB/usb_update.c @@ -0,0 +1,1231 @@ + +//#include "board.h" +#include "fuart.h" +#include "usb_update.h" +#include "debug.h" +#include "timer.h" + +#define IOADDR_USB_REG_BASE (0xFF600000) +#define _THUMB2 __attribute__((target("thumb"))) + + +_THUMB2 void fLib_USB_Update_FW(void); + +int usbrom_exit = 0; +volatile DEV *ptusbdev; +#define ptotg ((volatile OTG200 *)IOADDR_USB_REG_BASE) + +#define FUSB200_MAX_EP 8 // 1..10 +#define FUSB200_MAX_FIFO 4 // 0.. 9 + +#define mUsbEPMap(EPn, MAP) (ptusbdev->ep_map[EPn-1] = MAP) +#define mUsbEPMapRd(EPn) (ptusbdev->ep_map[EPn-1]) + +#define mUsbFIFOMap(FIFOn, MAP) (ptusbdev->fifo_map[FIFOn] = MAP) +#define mUsbFIFOMapRd(FIFOn) (ptusbdev->fifo_map[FIFOn]) +#define mUsbFIFOConfigRd(FIFOn) (ptusbdev->fifo_cfg[FIFOn]) + +static USB_st tusb; +static MassStorageState eUsbMassStorageState = MS_STATE_CBW; +CBW tCBW; +CSW tCSW; +SCSISense tSCSIsense; +SCSIDeviceResp tSCSIDeviceResp; + +MSDC_Verify_CB guiU2MsdcCheck_cb; +MSDC_VenDone_CB guiU2MsdcVendorDone_cb; + +int trigger_done_cb = 0; + +static const unsigned char u8RequestSenseData[DATA_LENGTH_REQUEST_SENSE] __attribute__((aligned(4))) = +{ + 0x70, // 0, response code + 0x00, // 1, obsolete + 0x00, // 2, sense key + 0x00, // 3-6, information + + 0x00, + 0x00, + 0x00, + 0x0A, // 7, additional length (n - 7), n = 17 + + 0x00, // 8-11, information + 0x00, + 0x00, + 0x00, + + 0x00, // 12, additional sense code + 0x00, // 13, additional sense code qualifier + 0x00, // 14, field replaceable unit code + 0x00, // 15-17, sense-key specific + + 0x00, + 0x00 +}; + + +static const unsigned char u8ModeSenseData[DATA_LENGTH_MODE_SENSE] __attribute__((aligned(4))) = +{ + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + + +#define USB_BUFF_SZ 128 +unsigned int u32Usb_buffer[USB_BUFF_SZ/4]; // may less than USB_BUFF_SZ + +static INT32U nvtdev_opened = 1; +#define mCxType(cmd) ((cmd[0] & (BIT6 | BIT5)) >> 5) +#define mCxRequest(cmd) ((unsigned char)(cmd[0] >> 8)) +#define mCxValue(cmd) ((unsigned short)(cmd[0] >> 16)) // get 3rd byte, 4th byte +#define mCxIndex(cmd) ((unsigned short)(cmd[1])) // get 5th byte, 6th byte +#define mCxLength(cmd) ((unsigned short)(cmd[1] >> 16)) // get 7th byte, 8th byte + + +#define mUsbRmWkupST() (ptusbdev->main_ctl & BIT0) +#define mUsbRmWkupClr() (ptusbdev->main_ctl &= ~BIT0) +#define mUsbRmWkupSet() (ptusbdev->main_ctl |= BIT0) +#define mUsbTsMdWr(item) (ptusbdev->phy_tms = item) +#define mUsbIntF2OUTDis() (ptusbdev->int_mgrp1 |= (BIT5 | BIT4)) +#define mUsbIntF2OUTEn() (ptusbdev->int_mgrp1 &= ~(BIT5 | BIT4)) +#define mUsbIntF0INDis() (ptusbdev->int_mgrp1 |= BIT16) +#define mUsbIntF0INEn() (ptusbdev->int_mgrp1 &= ~BIT16) +// Endpoint & FIFO Configuration +#define mUsbEPMxPtSz(EPn, dir, size) (ptusbdev->ep_xpsz[dir][EPn - 1] = size) +#define mUsbEPStallST(EPn, dir) (((ptusbdev->ep_xpsz[dir][EPn - 1]) & BIT11) >> 11) +#define mUsbEPRsTgSet(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] |= BIT12) +#define mUsbEPRsTgClr(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] &= ~BIT12) +#define mUsbEPStallClr(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] &= ~BIT11) +#define mUsbEPStallSet(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] |= BIT11) + +extern void CPUflushReadCache(UINT32 uiStartAddr, UINT32 uiLength); +extern void CPUflushWriteCache(UINT32 uiStartAddr, UINT32 uiLength); + +INT32S my_SCSICmd(CBW * ptcbw); + +_THUMB2 signed int usb_DxFifoRdWr(unsigned char * buf, unsigned int count, unsigned int Rd) +{ + signed int ret = -1; // assume fail + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: enter usb_DxFifoRdWr\r\n"); + //#endif + + CPUflushWriteCache((UINT32) buf, (UINT32) count); + CPUflushReadCache((UINT32) buf, (UINT32) count); + + //#ifdef __FREERTOS + //if(buf == (unsigned char *)0xFE080000) + // ptusbdev->dma_addr = (INT32U)buf; + //else + // ptusbdev->dma_addr = dma_getPhyAddr(buf); + + //dma_flushWriteCache((UINT32)buf, count); + //dma_flushReadCache((UINT32)buf, count); + //#else + ptusbdev->dma_addr = (INT32U)buf;//dma_getPhyAddr(buf); + + __asm__ __volatile__("dsb\n\t"); + //#endif + + + if (Rd) { + // fifo select + ptusbdev->dma_fifo = BIT2; + // ctrl setting + ptusbdev->dma_ctl = (count << 8) | // dma byte count + (0 << 2) | // not dma io to io + (0 << 1); // fifo 2 memory + + #ifdef USBROM_RTOS_DBG + debug_msg("MSG: count = %d, Read CTRL = %x\r\n", count, ptusbdev->dma_ctl); + #endif + + } else { + // fifo select + ptusbdev->dma_fifo = BIT0; + // ctrl setting + ptusbdev->dma_ctl = (count << 8) | // dma byte count + (0 << 2) | // not dma io to io + (1 << 1); // memory 2 fifo + + #ifdef USBROM_RTOS_DBG + debug_msg("MSG: Write count = %d, Write CTRL = %x\r\n", count, ptusbdev->dma_ctl); + #endif + } + + // dma start + ptusbdev->dma_ctl |= BIT0; + + while (1) { + INT32U temp; + + temp = ptusbdev->int_grp2 & ~ ptusbdev->int_mgrp2; + + if (temp & BIT7) { // dma completion + ret = 0; // ok + break; + } + if (temp & (BIT2 | BIT1)) { // bus condiction + // clear cx fifo + ptusbdev->cx_cf |= BIT3; + break; + } + if (temp & BIT8) { // dma error + // clear cx fifo + ptusbdev->cx_cf |= BIT3; + break; + } + } + + // clear (dma error & dma completion) interrupt + ptusbdev->int_grp2 |= (BIT8 | BIT7); + CPUflushReadCache((UINT32) buf, (UINT32) count); + + //debug_msg("done\r\n"); + + //#ifdef __FREERTOS + //dma_flushReadCache((UINT32)buf, count); + //#endif + + return ret; +} + +_THUMB2 void vSCSIHWError(void) +{ + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + if ((tCBW.CB0_cblen_lun_flag&0xFF) == CBW_FLAG_OUT) { + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + } else { + //debug_msg("S1\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + } + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: vSCSIHWError\r\n"); + //#endif + + tSCSIsense.u8Key = KEY_NOT_READY; + tSCSIsense.u8KeyAdd = ADDKEY_MEDIUM_NOT_PRESENT; +} + + +////////////////////////////////////////////////////////////////////////////////// +_THUMB2 MassStorageState eScsiIn(void) +{ + + switch (tSCSIDeviceResp.u8MemIndex) { + case CARD_INDEX_SRAM: + // unit: byte + if (usb_DxFifoRdWr((INT8U *)u32Usb_buffer, tSCSIDeviceResp.u16DataResidue, 0) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + if (tCSW.u32DataResidue) { + // wait for fifo empty + while ((ptusbdev->cx_cf & (BIT8 | BIT9)) != (BIT8 | BIT9)) { + // if (VBUS == 0) + // return MS_STATE_CSW; + } + //debug_msg("S2\r\n"); + //mUsbEPStallSet(IN_EP, DIRECTION_IN); // case MS13Case_5: + } + return MS_STATE_CSW; + } + break; + + case CARD_INDEX_FSM_SS: + if (usb_DxFifoRdWr((INT8U *)tSCSIDeviceResp.u32IOAddr, tSCSIDeviceResp.u16DataResidue, 0) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + return MS_STATE_CSW; + } else { + mUsbEPStallSet(OUT_EP, DIRECTION_IN); // case MS13Case_11: + } + break; + + + default: + break; + } + vSCSIHWError(); + return MS_STATE_CSW; +} + + +////////////////////////////////////////////////////////////////////////////////// +_THUMB2 MassStorageState eScsiOut(void) +{ + switch (tSCSIDeviceResp.u8MemIndex) { + case CARD_INDEX_SRAM: + if (usb_DxFifoRdWr((INT8U *)u32Usb_buffer, tSCSIDeviceResp.u16DataResidue, 1) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + if (tCSW.u32DataResidue) + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); // case MS13Case_11: + return MS_STATE_CSW; + } + break; + + case CARD_INDEX_FSM_SS: + if (usb_DxFifoRdWr((INT8U *)tSCSIDeviceResp.u32IOAddr, tSCSIDeviceResp.u16DataResidue, 1) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + return MS_STATE_CSW; + } else { + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); // case MS13Case_11: + } + break; + default: + break; + } + vSCSIHWError(); + return MS_STATE_CSW; +} + +typedef unsigned int size_t; +extern void *utl_memcpy(void *dest, const void *src, size_t count); + +_THUMB2 void vSCSICmd_RequestSense(void) +{ + // Device intend to send data + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + tSCSIDeviceResp.u16DataResidue = sizeof(u8RequestSenseData); + + // copy response to sram + utl_memcpy ((UINT32 *)u32Usb_buffer, (UINT32 *)u8RequestSenseData, (UINT32)sizeof(u8RequestSenseData)); + + *((unsigned int *)u32Usb_buffer + (SENSE_OFFSET_KEY>>2)) += (tSCSIsense.u8Key&0xFF)<<16; + *((unsigned int *)u32Usb_buffer + (SENSE_OFFSET_ADD>>2)) += (tSCSIsense.u8KeyAdd&0xFF); + + // all key disappear + tSCSIsense.u8Key = KEY_NO_SENSE; + tSCSIsense.u8KeyAdd = ADDKEY_NO_ADDITIONAL; +} + +_THUMB2 void vSCSICmd_ModeSense(void) +{ + + //switch (tCBW.u8CB[2]) { + switch ((tCBW.CB1_CB15[0]>>8)&0xFF) { + case 0x00: // return mode parameter header and block descriptor + //debug_msg("MODE_SENSE 00\r\n"); + tSCSIDeviceResp.u16DataResidue = 0x0C; + break; + case 0x3F: // all pages + //debug_msg("MODE_SENSE 3F\r\n"); + tSCSIDeviceResp.u16DataResidue = sizeof(u8ModeSenseData); + break; + default: + //debug_msg("MODE_SENSE ERR\r\n"); + tSCSIsense.u8Key = KEY_ILLEGAL_REQUEST; + tSCSIsense.u8KeyAdd = ADDKEY_INVALID_FIELD_IN_CMD; + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + return; + } + // Device intend to send data + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + + // copy response to sram + utl_memcpy((UINT32 *)u32Usb_buffer, (UINT32 *)u8ModeSenseData, (UINT32)tSCSIDeviceResp.u16DataResidue); +} + + + +_THUMB2 void vSCSICmd_Unsupport(void) +{ + // Device intend to transfer no data + tSCSIsense.u8Key = KEY_ILLEGAL_REQUEST; + tSCSIsense.u8KeyAdd = ADDKEY_INVALID_CMD_OP_CODE; + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + + //#ifdef DISPLAY_USB_INFORMATION + //DBG_DUMP("MSG: UnSupported SCSI Command (op code = 0x%x)\r\n", tCBW.u8CB[0]); + //#endif +} + +_THUMB2 MassStorageState eMassStorage13case(void) +{ + MassStorage13Case eCase = 0x0; + MassStorageState estate; + INT32U u32DeviceRespDataLength = 0x0; + + switch(tSCSIDeviceResp.u8MemIndex) { + case CARD_INDEX_SRAM: + u32DeviceRespDataLength = tSCSIDeviceResp.u16DataResidue; + tSCSIDeviceResp.u32IOAddr += tSCSIDeviceResp.u16TfSzCurrent; + break; + case CARD_INDEX_FSM_SS: + u32DeviceRespDataLength = tSCSIDeviceResp.u16DataResidue; + break; + default:// SPI + u32DeviceRespDataLength = tSCSIDeviceResp.u16DataResidue * 2112; + break; + } + + // Mass Storage the thirteen case + if (tCBW.u32DataTransferLength == u32DeviceRespDataLength) { + // normal case + if (tCBW.u32DataTransferLength == 0) + eCase = MS13Case_1; // MassStorage case (1) + else { + if ((tCBW.CB0_cblen_lun_flag&0xFF) == tSCSIDeviceResp.u8Flags) { + if ((tCBW.CB0_cblen_lun_flag&0xFF) == CBW_FLAG_IN) + eCase = MS13Case_6; // MassStorage case (6) + else + eCase = MS13Case_12; // MassStorage case (12) + } + } + + //#ifdef DISPLAY_USB_INFORMATION + // vShowSCSI(); + //#endif + + } else { + if (tCBW.u32DataTransferLength == 0) + eCase = MS13Case_2_3; // MassStorage case (2)(3) + else if ((tCBW.CB0_cblen_lun_flag&0xFF) == CBW_FLAG_IN) { + if (u32DeviceRespDataLength == 0) + eCase = MS13Case_4; // MassStorage case (4) + else if (tSCSIDeviceResp.u8Flags == CBW_FLAG_IN) { + if (tCBW.u32DataTransferLength > u32DeviceRespDataLength) + eCase = MS13Case_5; // MassStorage case (5) + else + eCase = MS13Case_7_8; // MassStorage case (7)(8) + } + } + else { //tCBW.u8Flags == CBW_FLAG_OUT + if (u32DeviceRespDataLength == 0) + eCase = MS13Case_9; // MassStorage case (9) + else if (tSCSIDeviceResp.u8Flags == CBW_FLAG_OUT) { + if (tCBW.u32DataTransferLength > u32DeviceRespDataLength) + eCase = MS13Case_11; // MassStorage case (11) + else + eCase = MS13Case_10_13; // MassStorage case (10)(13) + } + } + +//#ifdef DISPLAY_USB_INFORMATION +// { + //vShowUsb(); +// DBG_DUMP("MSG: MS13Case = 0x%x\r\n", eCase); +// DBG_DUMP("MSG: , u32DeviceRespDataLength = 0x%x\r\n", u32DeviceRespDataLength); +// } +//#endif + + } + + // assume the next state is STATE_CSW + estate = MS_STATE_CSW; + switch (eCase) { + case MS13Case_2_3: + //debug_msg("S3\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + tCSW.u8Status = CSW_STATUS_PHASE_ERROR; + break; + case MS13Case_4: + //debug_msg("S4\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + break; + case MS13Case_5: + case MS13Case_6: + estate = eScsiIn(); + break; + case MS13Case_11: + case MS13Case_12: + estate = eScsiOut(); + break; + case MS13Case_7_8: + //debug_msg("S5\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + tCSW.u8Status = CSW_STATUS_PHASE_ERROR; + break; + case MS13Case_9: + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + break; + case MS13Case_10_13: + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + tCSW.u8Status = CSW_STATUS_PHASE_ERROR; + //debug_msg("S6\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + break; + default: // MS13Case_1; + // do nothing here + break; + } + return estate; +} + + +_THUMB2 MassStorageState eSCSI_CmdDecode(void) //trace, different from FUSB100-CardReader +{ + //debug_msg("eSCSI_CmdDecode\r\n"); + // Assume SCSI Response data length will be 0 + tSCSIDeviceResp.u16DataResidue = 0; + if (((tCBW.CB0_cblen_lun_flag >> 8)&0xFF) >= CARD_TYPE_MAX_REPORT) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + tSCSIsense.u8Key = KEY_NOT_READY; + tSCSIsense.u8KeyAdd = ADDKEY_LOGICAL_UNIT_NOT_SUPPORT; + } else { + // Parse SCSI command + //switch (tCBW.u8CB[0]) { // Operation Code + switch ((tCBW.CB0_cblen_lun_flag >> 24)&0xFF) { // Operation Code + case SCSI_OP_REQUEST_SENSE: + vSCSICmd_RequestSense(); + //debug_msg("vSCSICmd_RequestSense\r\n"); + break; + case SCSI_OP_MEDIUM_REMOVAL: + //vSCSICmd_MediumRemoval(); + debug_msg("SCSI_OP_MEDIUM_REMOVAL\r\n"); + break; + case SCSI_OP_INQUIRY: + //vSCSICmd_Inquiry(); + debug_msg("SCSI_OP_INQUIRY\r\n"); + break; + case SCSI_OP_MODE_SENSE: + vSCSICmd_ModeSense(); + //debug_msg("SCSI_OP_MODE_SENSE 22\r\n"); + break; + + case SCSI_OP_TEST_UNIT_READY: + case SCSI_OP_READ_CAPACITY: + case SCSI_OP_READ_10: + case SCSI_OP_WRITE_10: + case SCSI_OP_VERIFY: + //debug_msg("SCSI_OP_TEST_UNIT_READY\r\n"); + tSCSIsense.u8Key = KEY_NOT_READY; + tSCSIsense.u8KeyAdd = ADDKEY_MEDIUM_NOT_PRESENT; + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + break; + + default: + if (my_SCSICmd(&tCBW) < 0) { + //#ifdef USBROM_RTOS_DBG + debug_msg("MSG: SCSI cmd: UNSUPPOR\r\n"); + //#endif + vSCSICmd_Unsupport(); + } + break; + } + } + return eMassStorage13case(); +} + + + + + +_THUMB2 MassStorageState eUsbProessCBW(void) +{ + usb_DxFifoRdWr((unsigned char *)&tCBW, 31, 1); + + if(tCBW.u32Signature != CBW_SIGNATE) { + return MS_STATE_CBW; + } else { + // pass u32DataTransferLength to u32DataResidue + tCSW.u32DataResidue = tCBW.u32DataTransferLength; + + #ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: tCSW.u32DataResidue = %d, dir = %d\r\n", tCBW.u32DataTransferLength, tCBW.u8Flags); + #endif + + // pass Tag from CBW to CSW + tCSW.u32Tag = tCBW.u32Tag; + // Assume Status is CMD_PASS + tCSW.u8Status = CSW_STATUS_CMD_PASS; + + return eSCSI_CmdDecode(); + } +} + +_THUMB2 void vUsbUnplug(void) +{ + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: Unplug.. pls check\r\n"); + //#endif + // mUsbUnPlug(); + ptusbdev->phy_tms |= BIT0; +} + +_THUMB2 void vUsb_BulkIntOnOff(void) +{ + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: st 0x%x", eUsbMassStorageState); + //#endif + + switch(eUsbMassStorageState) + { + case MS_STATE_CBW: + mUsbIntF2OUTEn(); + mUsbIntF0INDis(); + break; + case MS_STATE_CB_DMA_IN: + if (mUsbEPStallST (IN_EP, DIRECTION_IN)) { + // wait for clear feature, and then enable F0 + } + else + mUsbIntF0INEn(); + break; + case MS_STATE_CB_DMA_OUT: + mUsbIntF2OUTEn(); + break; + case MS_STATE_CSW: + mUsbIntF2OUTDis(); + if (mUsbEPStallST (IN_EP, DIRECTION_IN)) { + // wait for clear feature, and then enable F0 + } + else { + mUsbIntF0INEn(); + } + break; + case MS_STATE_BGD: + mUsbIntF2OUTDis(); + mUsbIntF0INDis(); + break; + default: + //#ifdef USBROM_RTOS_DBG + debug_msg("MSG: Error MS_STATE\r\n"); + //#endif + vUsbUnplug(); + break; + } +} + +_THUMB2 void vUsb_F0_In(void) +{ + switch(eUsbMassStorageState) + { + case MS_STATE_CSW: + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP1 IN CSW\r\n"); + //#endif + + if (trigger_done_cb) { + trigger_done_cb = 0; + + if (guiU2MsdcVendorDone_cb != NULL) { + if (guiU2MsdcVendorDone_cb((unsigned int)&tCBW) != 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } + } + } + + usb_DxFifoRdWr((unsigned char *)&tCSW, 13, 0); + + //mUsbFIFODone(FIFO0); + eUsbMassStorageState = MS_STATE_CBW; + if(usbrom_exit == 1) + usbrom_exit = 2; + break; + case MS_STATE_CB_DMA_IN: + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP1 CS DMA IN\r\n"); + //#endif + eUsbMassStorageState = eScsiOut(); + break; + default: + //#ifdef USBROM_RTOS_DBG + debug_msg("MSG: Error FIFO0_IN interrupt.\r\n"); + //#endif + + break; + } + vUsb_BulkIntOnOff(); +} + +_THUMB2 void vUsb_F2_Out(unsigned int u32FIFOByteCount) +{ + switch(eUsbMassStorageState) { + case MS_STATE_CBW: + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP2 Out CBW\r\n"); + //#endif + + if (u32FIFOByteCount == 31) { + eUsbMassStorageState = eUsbProessCBW(); + } + else{ + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP out STAL SET\r\n"); + //#endif + + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + } + break; + case MS_STATE_CB_DMA_OUT: + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP2 Out CB DMA Out\r\n"); + //#endif + + eUsbMassStorageState = eScsiOut(); + break; + default: + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: Error FIFO2_OUT interrupt.\r\n"); + //#endif + + break; + } + + vUsb_BulkIntOnOff(); +} + + + + +/////////////////////////////////////////////////////////////////////////////// +// bClear_feature() +// Description: +// 1. Send 2 bytes status to host. +// input: none +// output: TRUE or FALSE (BOOLEAN) +/////////////////////////////////////////////////////////////////////////////// +_THUMB2 signed int usb_Clear_feature(void) +{ + unsigned int ep_n; + unsigned int fifo_n; + signed int bdir; + + switch (mCxValue (tusb.u32UsbCmd)) { // FeatureSelector + case 0: // ENDPOINT_HALE + // Clear "Endpoint_Halt", Turn off the "STALL" bit in Endpoint Control Function Register + if(mCxIndex (tusb.u32UsbCmd) == 0x00) + tusb.bUsbEP0HaltSt = FALSE; + else { + ep_n = mCxIndex (tusb.u32UsbCmd) & 0x7F; // which ep will be clear + // over the Max. ep count ? + if (ep_n > FUSB200_MAX_EP) + return -1; + // the direction of this ep + // bdir =0 if OUT + bdir = mCxIndex (tusb.u32UsbCmd) & BIT7;; + // get the relatived FIFO number + if (bdir) + fifo_n = mUsbEPMapRd(ep_n) & 0x0F; + else + fifo_n = mUsbEPMapRd(ep_n) >> 4; + // over the Max. fifo count ? + if (fifo_n >= FUSB200_MAX_FIFO) + return -1; + + // Check the FIFO had been enable ? + if ((mUsbFIFOConfigRd(fifo_n) & BIT5) == 0) + return -1; + // bdir =0 if IN, 1 if OUT + bdir = bdir ? 0: 1; + mUsbEPRsTgSet(ep_n, bdir); // Set Rst_Toggle Bit + mUsbEPRsTgClr(ep_n, bdir); // Clear Rst_Toggle Bit + mUsbEPStallClr(ep_n, bdir); // Clear Stall Bit + vUsb_BulkIntOnOff(); + } + break; + case 1 : // Device Remote Wakeup + // Clear "Device_Remote_Wakeup", Turn off the"RMWKUP" bit in Main Control Register + mUsbRmWkupClr(); + break; + case 2 : // Test Mode + // do not break here + default : + return -1; + } + tusb.eUsbCxAction = ACT_DONE; + return 0; +} + + + +_THUMB2 signed int usb_StandardCommand(void) +{ + switch (mCxRequest (tusb.u32UsbCmd)) { // by Standard Request codes + //case 0: // get status + // return (usb_Get_status()); + + case 1: // clear feature + return (usb_Clear_feature()); + + //case 3: // set feature + // return (usb_Set_feature()); + + //case 5: // set address + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Set_address()); + // break; + + //case 6: // get descriptor + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Get_descriptor()); + // break; + + //case 8: // get configuration + // if (!tusb.bUsbEP0HaltSt) + // vGet_configuration(); + // return 0; + + //case 9: // set configuration + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Set_configuration()); + // break; + + //case 10: // get interface + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Get_interface()); + // break; + + // case 11: // set interface + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Set_interface()); + // break; + + case 2: // Reserved for further use + case 4: // Reserved for further use + case 7: // set descriptor, not support + case 12: // synch frame, not support + default: + break; + } + return -1; +} + +/////////////////////////////////////////////////////////////////////////////// +// vUsb_ep0setup() +// Description: +// 1. Read 8-byte setup packet. +// 2. Decode command as Standard, Class, Vendor or NOT support command +// input: none +// output: none +/////////////////////////////////////////////////////////////////////////////// +_THUMB2 void vUsb_ep0setup(void) +{ + /* + if(tusb.bUsbChirpFinish == 0) + { + // first ep0 command after usb reset, means we can check usb speed right now. + tusb.bUsbChirpFinish = 1; + + if (ptusbdev->main_ctl & BIT6) { + tusb.bHighSpeed = 1; + //DBG_DUMP("MSG: L%x, high speed mode\r\n", tusb.u8LineCount ++); + } + else { + tusb.bHighSpeed = 0; + //DBG_DUMP("MSG: L%x, full speed mode\r\n", tusb.u8LineCount ++); + } + // Init AP + vUsbMassStorageInit(); + } + */ + + // select dma target fifo no.: + //ptusbdev->dma_fifo = BIT4; + + // Read 8-byte setup packet from FIFO + tusb.u32UsbCmd[0] = ptusbdev->dma_data; + tusb.u32UsbCmd[1] = ptusbdev->dma_data; + + #if 0//def USBROM_RTOS_DBG + DBG_DUMP("MSG: L%x, EP0Cmd: %x %x %x %x %x %x %x %x\r\n", + tusb.u8LineCount ++, (INT8U)(tusb.u32UsbCmd[0] >> 0) + , (INT8U)(tusb.u32UsbCmd[0] >> 8) + , (INT8U)(tusb.u32UsbCmd[0] >> 16) + , (INT8U)(tusb.u32UsbCmd[0] >> 24) + , (INT8U)(tusb.u32UsbCmd[1] >> 0) + , (INT8U)(tusb.u32UsbCmd[1] >> 8) + , (INT8U)(tusb.u32UsbCmd[1] >> 16) + , (INT8U)(tusb.u32UsbCmd[1] >> 24)); + #endif + + // Command Decode + switch (mCxType(tusb.u32UsbCmd)) { + case 0: // standard command + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: Standard command\r\n"); + //#endif + + if (usb_StandardCommand() < 0) + tusb.eUsbCxAction = ACT_STALL; + break; +/* + case 1: // class command + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("MSG: class command\r\n"); + #endif + + if (usb_ClassCommand() < 0) + tusb.eUsbCxAction = ACT_STALL; + break; + + case 2: // vendor command + #ifdef USBROM_RTOS_DBG + DBG_DUMP("MSG: vendor command\r\n"); + #endif +// if (usb_UsbVendorCommand() < 0 + tusb.eUsbCxAction = ACT_STALL; + break; +*/ + default: + // Invalid(bad) command, Return EP0_STALL flag + tusb.eUsbCxAction = ACT_STALL; + break; + } +} + + + + +_THUMB2 void vUsbInit(void) +{ + ptusbdev = ((volatile DEV *)(IOADDR_USB_REG_BASE + 0x100)); + + // init variables + tusb.eUsbCxAction = ACT_IDLE; + tusb.bUsbChirpFinish = 0; + + tusb.u16TxRxCounter = 0; + tusb.eUsbCxCommand = CMD_VOID; + tusb.u8UsbConfigValue = 0; + tusb.u8UsbInterfaceValue = 0; + tusb.u8UsbInterfaceAlternateSetting = 0; + tusb.bUsbEP0HaltSt = FALSE; + + // init hardware + //vFUSB200Init(); + tusb.u8LineCount = 1; + + tCSW.u32Signature = CSW_SIGNATE; + eUsbMassStorageState = MS_STATE_CBW; + mUsbIntF2OUTEn (); + mUsbIntF0INDis(); + +} + + + +_THUMB2 void vUsbIsr2(void) +{ + INT32U level1; + INT32U level2; + + level1 = ptusbdev->int_grp & ~ ptusbdev->int_mgrp; + + if (0 == level1) + return; + + if (level1 & BIT2) { //Group 2 + + level2 = ptusbdev->int_grp2 & ~ ptusbdev->int_mgrp2; + + if (level2) { + + //debug_msg("MSG: IntSCR2\r\n"); + + if (level2 & BIT0) { + //debug_msg("MSG: BUS RST\r\n"); + } + + if (level2 & BIT1) { + //debug_msg("MSG: BUS SUSPEND\r\n"); + ptusbdev->int_grp2 |= BIT1; + } + + if (level2 & BIT2) { + //debug_msg("MSG: BUS RESUME\r\n"); + ptusbdev->int_grp2 |= BIT2; + } + + if (level2 & BIT5) { + //debug_msg("MSG: TX0B\r\n"); + + ptusbdev->tx0byte |= 0; + ptusbdev->int_grp2 |= BIT5; + } + + if (level2 & BIT6) { + //debug_msg("MSG: RX0B\r\n"); + ptusbdev->rx0byte |= 0; + ptusbdev->int_grp2 |= BIT6; + } + + } + } + + + if (level1 & BIT0) { //Group 0 + level2 = ptusbdev->int_grp0 & ~ ptusbdev->int_mgrp0; + if (level2) { + //debug_msg("MSG: IntSCR0\r\n"); + + if (level2 & BIT0) { + //debug_msg("MSG: USB ep0 Setup\r\n"); + vUsb_ep0setup(); + } + else if (level2 & BIT3) { + //debug_msg("MSG: USB ep0 end\r\n"); + //vUsb_ep0end(); + } + if (level2 & BIT1) { + //debug_msg("MSG: USB ep0 TX\r\n"); + //vUsb_ep0tx(); + } + if (level2 & BIT2) { + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: USB ep0 RX\r\n"); + //#endif + //vUsb_ep0rx(); + } + if (level2 & BIT4) { + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: USB ep0 fail\r\n"); + //#endif + // stall cx: mUsbEP0StallSet(); + //ptusbdev->cx_cf |= BIT2; + } + if (level2 & BIT5) { + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: cmd abort\r\n"); + //#endif + ptusbdev->int_grp0 |= BIT5; + } + } + + + if (tusb.eUsbCxAction == ACT_STALL) { + ptusbdev->cx_cf |= BIT2; + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: EP0 STALL\r\n"); + //#endif + } + else if (tusb.eUsbCxAction == ACT_DONE) { + ptusbdev->cx_cf |= BIT0; + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: EP0 DONE\r\n"); + //#endif + } + // Clear Action + tusb.eUsbCxAction = ACT_IDLE; + + + } + + if (level1 & BIT1) { //Group Byte 1 + level2 = ptusbdev->int_grp1 & ~ ptusbdev->int_mgrp1; + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: IntSCR1\r\n"); + //#endif + + if (level2 & (BIT5 | BIT4)) { // F2 out (full or short) + vUsb_F2_Out(ptusbdev->fifo_bc[2]); + } + + if (level2 & BIT16) // F0 in + vUsb_F0_In(); + } +} + + + +_THUMB2 static INT32U calc_sum_v2(INT32U dat0, INT32U dat1, INT32U dat2, INT32U dat3) +{ + INT32U sum=0; + + sum = (dat0&0xFFFF)+((dat0>>16))+(dat1&0xFFFF)+((dat1>>16)) + + (dat2&0xFFFF)+((dat2>>16))+(dat3&0xFFFF)+((dat3>>16)) + 28; + + //DBG_DUMP("SUM = 0x%08X\r\n",sum); + return sum&0xFFFF; +} + +_THUMB2 INT32S my_SCSICmd(CBW * ptcbw) +{ + INT32U temp1, temp2; + INT32U CDB[4]; + + CDB[0] = ((ptcbw->CB0_cblen_lun_flag >> 24) & 0xFF) + ((ptcbw->CB1_CB15[0]&0xFFFFFF)<<8); + CDB[1] = ((ptcbw->CB1_CB15[0] >> 24) & 0xFF) + ((ptcbw->CB1_CB15[1]&0xFFFFFF)<<8); + CDB[2] = ((ptcbw->CB1_CB15[1] >> 24) & 0xFF) + ((ptcbw->CB1_CB15[2]&0xFFFFFF)<<8); + CDB[3] = ((ptcbw->CB1_CB15[2] >> 24) & 0xFF) + ((ptcbw->CB1_CB15[3]&0xFFFFFF)<<8); + + // Parse SCSI command + if (!(((CDB[0]&0xFF) == SCSI_OP_SET0)||((CDB[0]&0xFF) == SCSI_OP_SET1)||((CDB[0]&0xFF) == SCSI_OP_SET2))) + return -1; + + // check sum + if(calc_sum_v2(CDB[0],CDB[1],CDB[2],CDB[3])) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + u32Usb_buffer[0] = 0; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("CHKSUM FAILED\r\n"); + #endif + return -1; + } + + tCSW.u8Status = CSW_STATUS_CMD_PASS; + + switch (((CDB[0] >> 8) &0xFF)) { + + case SCSIOP_OUT_OPEN_DEVICE: { + nvtdev_opened = 1; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_OUT_OPEN_DEVICE\r\n"); + #endif + } + break; + + case SCSIOP_IN_WAIT_DONE: { + usbrom_exit = 1; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_IN_WAIT_DONE\r\n"); + #endif + } + break; + + + case SCSIOP_IN_IS_NVT: { + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + tSCSIDeviceResp.u16DataResidue = 4; + + tCSW.u8Status = CSW_STATUS_CMD_PASS; + u32Usb_buffer[0] = 0x70210000; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_IN_IS_NVT\r\n"); + #endif + } + break; + + case SCSIOP_OUT_ADDR_WRITE: { + + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + // address + temp1 = ((CDB[0]>>16)&0xFFFF)+((CDB[1]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[2]); + // data + temp2 = ((CDB[1]>>16)&0xFFFF)+((CDB[2]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[6]); + + *(INT32U *)temp1 = temp2; + __asm__ __volatile__("dsb\n\t"); + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_OUT_ADDR_WRITE 0x%08X 0x%08X\r\n", temp1, temp2); + #endif + } + } + break; + + case SCSIOP_IN_ADDR_READ: { + + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + // address + temp1 = ((CDB[0]>>16)&0xFFFF)+((CDB[1]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[2]); + + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + tSCSIDeviceResp.u16DataResidue = 8; + u32Usb_buffer[0] = temp1; + u32Usb_buffer[1] = *((INT32U *)temp1); + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_IN_ADDR_READ 0x%08X 0x%08X\r\n", temp1, u32Usb_buffer[1]); + #endif + } + } + break; +#if 0 //only rom code support + case SCSIOP_OUT_WRLOADER: { + + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + // address + temp1 = ((CDB[0]>>16)&0xFFFF)+((CDB[1]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[2]); + + tSCSIDeviceResp.u32IOAddr = temp1; + tSCSIDeviceResp.u8Flags = CBW_FLAG_OUT; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_FSM_SS; + tSCSIDeviceResp.u16DataResidue = ptcbw->u32DataTransferLength; + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_OUT_WRLOADER 0x%08X 0x%08X\r\n", temp1, tSCSIDeviceResp.u16DataResidue); + #endif + + } + } + break; +#endif + default: { + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + int ret = -1; + unsigned int OutDataBuf=0, insize=0; + + if (guiU2MsdcCheck_cb != NULL) { + ret = guiU2MsdcCheck_cb((unsigned int)ptcbw, (unsigned int *) &OutDataBuf, (unsigned int *)&insize); + } else { + ret = -1; + } + + if(ret == 0) { + + if (ptcbw->CB0_cblen_lun_flag & CBW_FLAG_IN) { + tSCSIDeviceResp.u32IOAddr = OutDataBuf; + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_FSM_SS; + tSCSIDeviceResp.u16DataResidue = insize; + + } else { + tSCSIDeviceResp.u32IOAddr = OutDataBuf; + tSCSIDeviceResp.u8Flags = CBW_FLAG_OUT; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_FSM_SS; + tSCSIDeviceResp.u16DataResidue = ptcbw->u32DataTransferLength; + } + + trigger_done_cb = 1; + } else { + return ret; + } + } + } + break; + + } + + return 0; + +} + + + +_THUMB2 void fLib_USB_Update_FW(void) +{ + debug_msg("USBFW UPDATE\r\n"); + + vUsbInit(); + + while (1) { + + vUsbIsr2(); + + if(usbrom_exit > 1) { + //mdelay(300); //make sure that pc recevie scsi status + timer_delay(300000); + vUsbUnplug(); + timer_delay(300000); + //mdelay(300); //make sure that pc recevie usb plug-out single + break; + } + + } + + usbrom_exit = 0; + +} + diff --git a/board/novatek/ns02501/loader/Project/Model/Src/USB/usb_update.h b/board/novatek/ns02501/loader/Project/Model/Src/USB/usb_update.h new file mode 100755 index 000000000000..dde4570782d9 --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/Src/USB/usb_update.h @@ -0,0 +1,323 @@ + +#ifndef __USB_UPDATE_H +#define __USB_UPDATE_H +#include "scsi_op.h" + + +#define BIT0 0x00000001L +#define BIT1 0x00000002L +#define BIT2 0x00000004L +#define BIT3 0x00000008L +#define BIT4 0x00000010L +#define BIT5 0x00000020L +#define BIT6 0x00000040L +#define BIT7 0x00000080L +#define BIT8 0x00000100L +#define BIT9 0x00000200L +#define BIT10 0x00000400L +#define BIT11 0x00000800L +#define BIT12 0x00001000L +#define BIT13 0x00002000L +#define BIT14 0x00004000L +#define BIT15 0x00008000L +#define BIT16 0x00010000L +#define BIT17 0x00020000L +#define BIT18 0x00040000L +#define BIT19 0x00080000L +#define BIT20 0x00100000L +#define BIT21 0x00200000L +#define BIT22 0x00400000L +#define BIT23 0x00800000L + + +typedef int (*MSDC_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); ///< Callback for verify the Vendor Command is supported or not +typedef int (*MSDC_VenDone_CB)(unsigned int pCmdBuf); ///< Callback for verify the Vendor Command is supported or not + + +// KEY_ILLEGAL_REQUEST: Additional key +#define ADDKEY_INVALID_CMD_OP_CODE 0x20 +#define ADDKEY_INVALID_FIELD_IN_CMD 0x24 + +#define CBW_FLAG_IN 0x80 +#define CBW_FLAG_OUT 0x00 + +// Endpoint or FIFO direction define +#define DIRECTION_IN 0 ///1 +#define DIRECTION_OUT 1 ///0 + +#define EP0 0x00 +#define EP1 0x01 +#define EP2 0x02 +#define EP3 0x03 + +// FIFO number define +#define FIFO0 0x0 +#define FIFO1 0x1 +#define FIFO2 0x2 +#define FIFO3 0x3 +#define FIFO4 0x4 +#define FIFO5 0x5 +#define FIFO6 0x6 +#define FIFO7 0x7 +#define FIFO8 0x8 +#define FIFO9 0x9 + +#define OUT_EP EP2 +#define IN_EP EP1 +#define OUT_FIFO FIFO2 +#define IN_FIFO FIFO0 + +typedef enum { + MS13Case_1 = 0, + MS13Case_2_3, + MS13Case_4, + MS13Case_5, + MS13Case_6, + MS13Case_7_8, + MS13Case_9, + MS13Case_10_13, + MS13Case_11, + MS13Case_12 +} MassStorage13Case; + +#define CBW_SIGNATE 0x43425355 +#define CSW_SIGNATE 0x53425355 +#define CSW_STATUS_CMD_PASS 0x00 +#define CSW_STATUS_CMD_FAIL 0x01 +#define CSW_STATUS_PHASE_ERROR 0x02 + +// Request Sense data format +#define SENSE_OFFSET_KEY 0x02 +#define SENSE_OFFSET_ADD 0x0C +#define SENSE_OFFSET_ADD_QUALIFIER 0x0D + +// KEY_NO_SENSE: Additional key +#define ADDKEY_NO_ADDITIONAL 0x00 + +// all response data length +#define DATA_LENGTH_INQUIRY 36 +#define DATA_LENGTH_REQUEST_SENSE 18 +#define DATA_LENGTH_MODE_SENSE 8 + +// SCSI command operation code +#define SCSI_OP_TEST_UNIT_READY 0x00 +#define SCSI_OP_REQUEST_SENSE 0x03 +#define SCSI_OP_INQUIRY 0x12 +#define SCSI_OP_MODE_SELECT 0x15 +#define SCSI_OP_MODE_SENSE 0x1A +#define SCSI_OP_MEDIUM_REMOVAL 0x1E +#define SCSI_OP_READ_FORMAT_CAPACITY 0x23 // unsupported +#define SCSI_OP_READ_CAPACITY 0x25 +#define SCSI_OP_READ_10 0x28 +#define SCSI_OP_WRITE_10 0x2A +#define SCSI_OP_VERIFY 0x2F + +#define CARD_INDEX_SRAM 7 +#define CARD_INDEX_FSM_SS 3 +#define CARD_TYPE_MAX_REPORT 1 + +// KEY_NOT_READY: Additional key +#define ADDKEY_LOGICAL_UNIT_NOT_READY 0x04 +#define ADDKEY_LOGICAL_UNIT_NOT_SUPPORT 0x25 +#define ADDKEY_MEDIUM_NOT_PRESENT 0x3A + +// Sense key +#define KEY_NO_SENSE 0x00 +#define KEY_RECOVERED_ERROR 0x01 +#define KEY_NOT_READY 0x02 +#define KEY_MEDIUM_ERROR 0x03 +#define KEY_HARDWARE_ERROR 0x04 +#define KEY_ILLEGAL_REQUEST 0x05 +#define KEY_UNIT_ATTENTION 0x06 +#define KEY_DATA_PROTECT 0x07 +#define KEY_BLANK_CHECK 0x08 +#define KEY_VENDOR_SPECIFIC 0x09 +#define KEY_COPY_ABORTED 0x0A +#define KEY_ABORTED_CMD 0x0B +#define KEY_OBSOLETE 0x0C +#define KEY_VOLUMN_OVERFLOW 0x0D +#define KEY_MISCOMPARE 0x0E +#define KEY_RESERVED 0x0F + +typedef struct // SCSI device response +{ + unsigned int u8MemIndex; // current access memory type + unsigned int u8Flags; // In or Out + unsigned int u32IOAddr; // block addr in Card controller + unsigned int u16DataResidue; // residue (block count for card content, or byte count for information) + unsigned int u16TfSzCurrent; // current transfer length (block count for card content, or byte count for information) +} SCSIDeviceResp; + +typedef struct SCSI_Sense_Data +{ + unsigned int u8Key; + unsigned int u8KeyAdd; +} SCSISense; + +typedef enum { + MS_STATE_IDLE = 0, + MS_STATE_CBW = 1, + MS_STATE_CB_DMA_IN = 2, + MS_STATE_CB_DMA_OUT = 3, + MS_STATE_CSW = 4, + MS_STATE_STALL = 5, + MS_STATE_BGD = 6 +} MassStorageState; + + +typedef struct CommandBlockWrapper +{ + unsigned int u32Signature; + unsigned int u32Tag; + unsigned int u32DataTransferLength; + unsigned int CB0_cblen_lun_flag; + unsigned int CB1_CB15[4]; + //unsigned char u8Flags; + //unsigned char u8LUN; + //unsigned char u8CBLength; + //unsigned char u8CB[16]; +} CBW; + +typedef struct CommandStatusWrapper +{ + unsigned int u32Signature; + unsigned int u32Tag; + unsigned int u32DataResidue; + unsigned int u8Status; +} CSW; + +// Host Controller (HC) +typedef struct { + INT32U cap; // 0x00: capability + INT32U ports; // 0x04: Structural Parameter + INT32U capp; // 0x08: capability Parameter + INT32U reserved1; // 0X0c + INT32U cmd; // 0x10: USB command + INT32U status; // 0X14: status + INT32U int_en; // 0X18: interrupt enable + INT32U fm_idx; // 0X1c: frame Index + INT32U reserved2; // 0x20 + INT32U periodic; // 0X24: periodic Frame List Base Address. must 4KB align. + INT32U asynch; // 0X28: Current Asynchronous List Address, must 32B align. + INT32U reserved3; // 0X2c + INT32U port; // 0x30: port status and Control + INT32U reserved4[3]; // 0X34 ~ 0X3c + INT32U misc; // 0x40 + INT32U reserved5[15]; // 0x44 ~ 0x7C +} HC; + +// OTG Controller (OTG) +typedef struct { + INT32U ctl_st; // 0x80: control/status + INT32U int_st; // 0x84: interrupt status + INT32U int_en; // 0x88: interrupt enable + INT32U reserved[13]; // 0x8C ~ 0xBC +} OTG; + +// Global Controller (GL) +typedef struct { + INT32U int_st; // 0xC0: interrupt status + INT32U interrupt; // 0xC4: interrupt mask + INT32U reserved[14]; // 0xC8 ~ 0xFC +} GL; + +// Device Controller (DEV) +typedef struct { + INT32U main_ctl; // 0x100: device main control + INT32U dev_adr; // 0x104: device address + INT32U tst_ep; // 0x108: device test + INT32U frm_no; // 0x10C: device SOF [13: 11] SOF micro frame number, [10: 0] SOF frame number + INT32U sof_tmsk; // 0x110: device SOF mask timer [15: 0] SOF mask timer + INT32U phy_tms; // 0x114: PHY test mode selector + INT32U vnd_ctl; // 0x118: vendor specific IO control + INT32U cx_cs; // 0x11C: CX configuration and status + INT32U cx_cf; // 0x120: CX configuration and FIFO empty status + INT32U idle_cnt; // 0x124: Device idel counter + INT32U cx_dataport; // 0x128: device cx data register + INT32U reserved1[1]; // 0x128 ~ 0x12C + INT32U int_mgrp; // 0x130: mask of interrupt group + INT32U int_mgrp0; // 0x134: mask of interrupt source group 0 + INT32U int_mgrp1; // 0x138: mask of interrupt source group 1 + INT32U int_mgrp2; // 0x13C: mask of interrupt source group 2 + INT32U int_grp; // 0x140: interrupt group + INT32U int_grp0; // 0x144: interrupt group 0 + INT32U int_grp1; // 0x148: interrupt group 1 + INT32U int_grp2; // 0x14C: interrupt group 2 + INT32U rx0byte; // 0x150: receive zero-length data packet + INT32U tx0byte; // 0x154: rtransfer zero-length data packet + INT32U iso_seq_err; // 0x158: iso. sequential error/abort + INT32U reserved2; // 0x15C + INT32U ep_xpsz[2][8]; // 0x160: IN endpoint x MaxPacketSize Reg + // 0x170: IN endpoint x MaxPacketSize Reg + // 0x180: OUT endpoint x MaxPacketSize Reg + // 0x190: OUT endpoint x MaxPacketSize Reg + INT8U ep_map[8]; // 0x1A0: endpoint 1 ~ 8 map Reg + INT8U fifo_map[4]; // 0x1A8: FIFO 0 ~ 3 map Reg + INT8U fifo_cfg[4]; // 0x1AC: FIFO 0 ~ 3 configuration + INT32U fifo_bc[4]; // 0x1B0: FIFO x instruction and byte count + INT32U dma_fifo; // 0x1C0: dma target FIFO number + INT32U reserved3; // 0x1C4 + INT32U dma_ctl; // 0x1C8: DMA controller parameter setting 1 + INT32U dma_addr; // 0x1CC: DMA controller parameter setting 2, address + INT32U dma_data; // 0x1D0: DMA controller parameter setting 3, Cx data +} DEV; + +// OTG Controller +typedef struct { + HC hc; // 0x00 ~ 0x7F + OTG otg; // 0x80 ~ 0xBF + GL gl; // 0xC0 ~ 0xFF + DEV dev; // 0x100 ~ 0x1FF +} OTG200; + + + +typedef enum +{ + ACT_IDLE, + ACT_DONE, + ACT_STALL, + + ACT_DUMMY = 0x80000000 +} Action; + +typedef enum +{ + CMD_VOID, // No command + CMD_GET_DESCRIPTOR, // Get_Descriptor command + CMD_SET_DESCRIPTOR, // Set_Descriptor command + + CommandType_dummy = 0x80000000 +} CommandType; + +typedef struct USB_s +{ + // end pointer 0 information + unsigned int u32UsbCmd[8/4]; + unsigned int bUsbChirpFinish; + Action eUsbCxAction; + unsigned int u16TxRxCounter; + unsigned char * pu8Descriptor; + unsigned int u8UsbConfigValue; + unsigned int u8UsbInterfaceValue; + unsigned int u8UsbInterfaceAlternateSetting; + unsigned int bUsbEP0HaltSt; + unsigned int bHighSpeed; // high speed + CommandType eUsbCxCommand; + // for display + unsigned int u8LineCount; +} USB_st; + + + + + + + +#endif /* __USB_OTG_H */ + + + + + + diff --git a/board/novatek/ns02501/loader/Project/Model/Src/prj_main.c b/board/novatek/ns02501/loader/Project/Model/Src/prj_main.c new file mode 100755 index 000000000000..b1101e7d0d5e --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/Src/prj_main.c @@ -0,0 +1,251 @@ +/* + Project layer Main control function + + This file is implement by user mode + + @file prj_main.c + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ + +#include "fuart.h" +#include "fat.h" +#include "rtc.h" +#include "timer.h" +#include "StorageDef.h" +#include "global.h" +#include "Clock.h" +#include "string.h" +#include "prj_main.h" +#include "debug.h" + +#define _THUMB2 __attribute__((target("thumb"))) + +#if defined(_STORAGEINT_EMMC_NAND_COMBO_) +#if (CHECK_CARD_EXIST == ENABLE) +#undef CHECK_CARD_EXIST +#define CHECK_CARD_EXIST DISABLE +#endif + +#endif + +extern UINT32 LoaderInternalInfo[]; + +#if (DEBUG_MSG == DISABLE) +//weak function mechanism for debug msg output +extern void debug_disable_msg(void); +void debug_disable_msg(void) {} +#endif + +#if defined(_Low_Pwr_) +//weak function mechanism for debug msg output +extern void Low_pwr(void); +void Low_pwr(void) {} +#endif + +#if defined(_DDR_SIZE_ALL_IN_ON_) +//weak function mechanism for debug msg output +extern void DDR_SIZE_ALL_IN_ON(void); +void DDR_SIZE_ALL_IN_ON(void) {} +#endif +#if (SPECIAL_KEY_UPDATE == ENABLE) +/** + Check special key1(s) is(are) pressed. + + Check special key1(s) is(are) pressed or not. + + @return Key pressed status + - @b TRUE: Special key(s) is(are) pressed + - @b FALSE: Otherwise +*/ +static BOOL prj_isSpecialKeyPressed(void) +{ + // Detect key example, must press shutter2 and playback mode keys + // OUT_0: DGPIO 0 + // OUT_1: DGPIO 14 + // OUT_2: DGPIO 2 + // OUT_3: DGPIO 3 + // OUT_4: DGPIO 4 + // IN_0 : DGPIO 5 + // IN_1 : DGPIO 6 + // IN_2 : DGPIO 7 + // IN_3 : DGPIO 8 + // KEY_IN_0 KEY_IN_1 KEY_IN_2 KEY_IN_3 + // KEY_OUT_0 MENU SET PLAYBACK DISPLAY + // KEY_OUT_1 WIDE LEFT MOVIE + // KEY_OUT_2 TELE DOWN TRASH + // KEY_OUT_3 SHUTTER2 RIGHT CAPTURE + // KEY_OUT_4 SHUTTER1 UP + // Add the necessary code.. + return TRUE; +} +#endif + +#if (CHECK_CARD_EXIST == ENABLE) +// MC16 default is config as input and pull up +_THUMB2 static BOOL prj_checkCardExist(void) +{ +#if (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + return TRUE; // force ethernet probe DHCP server +#else + return TRUE; //(gpio_getPin(DGPIO_CARD_DETECT) == 0 ? TRUE : FALSE); +#endif +} +#endif + +#if 0 +static BOOL bl_spiIdentify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + // Sample to support SST25VF032 + if ((uiMfgID == 0xBF) && + (uiCapacityID == 0x4A)) { + pIdentify->bDualRead = FALSE; + pIdentify->bSupportAAI = TRUE; + pIdentify->bSupportEWSR = TRUE; + pIdentify->uiFlashSize = 4 * 1024 * 1024; + return TRUE; + } + + return FALSE; +} + +static void bl_flashLED(void) +{ + // use GPIO to control LED +} +#endif + +// main entry of project layer code +_THUMB2 void prj_main(void) +{ +#if !defined(_STORAGEINT_NONE_) + PSTORAGE_OBJ strg_obj = NULL; +#endif + +#if defined(_STORAGEINT_EMMC_) +#if !((STORAGE_EXT_TYPE == STORAGE_EXT_USB) || (STORAGE_EXT_TYPE == STORAGE_EXT_UART)) + UINT32 high_speed = FALSE; +#endif +#endif + + printf("\r\nLD_VER %X.%X.%X %s", + (LoaderInternalInfo[1] >> 28) & 0xF, + (LoaderInternalInfo[1] >> 24) & 0xF, + (LoaderInternalInfo[1] >> 16) & 0xF, + _LOADER_VERSION_STR_); + + + loader_setVersion(_LDR_VER_); + // Print project layer info + if((LoaderInternalInfo[6] & 0x100000) == 0x100000) { + if(gpio_getPin((((LoaderInternalInfo[6]>>12)&0x7)*32) + ((LoaderInternalInfo[6]>>15)&0x1f))) { + debug_msg(_LOADER_VERSION_STR2_); + } else { + debug_msg(_LOADER_VERSION_STR_); + } + } else { + debug_msg(_LOADER_VERSION_STR_); + } + + // Setup loader/fw file names + loader_setUpdateFwName(_UPDATE_FW_NAME_); + loader_setUpdateLdrName(_UPDATE_LOADER_NAME_); + loader_setRunFwName(_RUN_FW_NAME_); + // Setup FW_MAC_CODE_SIZE (i.e. FWResvSize in RTOS) + +#if 0 + // Sample to hook spi flash extending function + flash_installIdentifyCB(bl_spiIdentify); +#endif + +#if 0 + // Sample to hook flash programming LED callback + flash_installAccessCB(bl_flashLED); +#endif + +#if defined(_STORAGEINT_EMMC_) +#if defined(_FASTBOOT_) || defined(_DIRECT_BOOT_) + high_speed = TRUE; +#endif +#endif + +#if (SPECIAL_KEY_UPDATE == ENABLE) + loader_installSpecialKeyCB(prj_isSpecialKeyPressed); +#endif + +#if (CHECK_CARD_EXIST == ENABLE) + loader_installCardDetectCB(prj_checkCardExist); +#endif + + +#if defined(_STORAGEINT_NandSpi_) + strg_obj = nand_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NAND, strg_obj); + +#elif defined(_STORAGEINT_NandEccBCH_) + strg_obj = nand_bch_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NAND, strg_obj); + // set Nand Flash speed to 96MHz + //strg_obj->flash_setFrequency(96); +#elif defined(_STORAGEINT_SpiFlash_) + strg_obj = nor_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NOR, strg_obj); +#elif defined(_STORAGEINT_EMMC_) + strg_obj = emmc_get_storage_object(); + if (top_get_bs() == BOOT_SOURCE_EMMC_8BIT) { + strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, TRUE); + debug_msg("[8bit]\r\n"); + } else if (top_get_bs() == BOOT_SOURCE_EMMC_4BIT) { + debug_msg("[4bit]\r\n"); + } else { +#if (EMMC_PINMUX_SETTING == EMMC_PINMUX_8BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, TRUE); + debug_msg("CFG[8bit]\r\n"); +#else + debug_msg("CFG[4bit]\r\n"); +#endif + } +#if !((STORAGE_EXT_TYPE == STORAGE_EXT_USB) || (STORAGE_EXT_TYPE == STORAGE_EXT_UART)) + strg_obj->flash_setConfig(FLASH_CFG_ID_HIGH_SPEED, high_speed); +#endif + loader_setStorageIntType(STORAGEINT_EMMC, strg_obj); +#elif defined(_STORAGEINT_EMMC_NAND_COMBO_) + if (top_get_bs() == BOOT_SOURCE_SPI_NAND_2K || top_get_bs() == BOOT_SOURCE_SPI_NAND_4K) { + debug_msg_var("NAND,BS=", top_get_bs()); + strg_obj = nand_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NAND, strg_obj); + } else if (top_get_bs() == BOOT_SOURCE_EMMC_4BIT || top_get_bs() == BOOT_SOURCE_EMMC_8BIT) { + debug_msg("eMMC"); + strg_obj = emmc_get_storage_object(); + if (top_get_bs() == BOOT_SOURCE_EMMC_8BIT) { + strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, TRUE); + debug_msg("[8bit]\r\n"); + } else { + debug_msg("[4bit]\r\n"); + } + loader_setStorageIntType(STORAGEINT_EMMC, strg_obj); + } else if (top_get_bs() == BOOT_SOURCE_SPI) { + debug_msg("NOR\r\n"); + strg_obj = nor_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NOR, strg_obj); + } else { + debug_msg_var("unknow BS=", top_get_bs()); + } +#endif +} + diff --git a/board/novatek/ns02501/loader/Project/Model/Src/prj_main.h b/board/novatek/ns02501/loader/Project/Model/Src/prj_main.h new file mode 100755 index 000000000000..d1b08f8e9002 --- /dev/null +++ b/board/novatek/ns02501/loader/Project/Model/Src/prj_main.h @@ -0,0 +1,80 @@ +/** + Loader project header file + + Loader project header file + + @file prj_main.h + @note Nothing +*/ + +#ifndef _PRJ_MAIN_H +#define _PRJ_MAIN_H + +#include "constant.h" +#include "loader.h" +#include "GPIO.h" + +// Define SPECIAL_KEY_UPDATE == ENABLE will require user to press special key +// to update firmware +#ifndef SPECIAL_KEY_UPDATE +#define SPECIAL_KEY_UPDATE DISABLE +#endif + +#ifndef SPI_PINMUX_NORMAL +#define SPI_PINMUX_NORMAL (0) +#endif + +#ifndef SPI_PINMUX_4BITS +#define SPI_PINMUX_4BITS (1) +#endif + +#ifndef SPI_PINMUX_SETTING +#define SPI_PINMUX_SETTING (SPI_PINMUX_4BITS) +#endif + +// Define MACROs for external storage +// +#ifndef STORAGE_EXT_UNKOWN +#define STORAGE_EXT_UNKOWN (0) +#endif + +#ifndef STORAGE_EXT_SDIO1 +#define STORAGE_EXT_SDIO1 (1) +#endif + +#ifndef STORAGE_EXT_SDIO2 +#define STORAGE_EXT_SDIO2 (2) +#endif + +#ifndef STORAGE_EXT_UART +#define STORAGE_EXT_UART (3) +#endif + +#ifndef STORAGE_EXT_USB +#define STORAGE_EXT_USB (4) +#endif + +#ifndef STORAGE_EXT_ETH +#define STORAGE_EXT_ETH (5) +#endif + +#ifndef STORAGE_EXT_NONE +#define STORAGE_EXT_NONE (6) +#endif + +#ifndef STORAGE_EXT_TYPE +#define STORAGE_EXT_TYPE (STORAGE_EXT_SDIO1) +#endif + + + +// Card detect GPIO offset +#define DGPIO_CARD_DETECT (D_GPIO_1) + + +#define CHECK_CARD_EXIST (ENABLE) + +// disable debug msg +#define DEBUG_MSG (ENABLE) + +#endif diff --git a/board/novatek/ns02501/loader/Tools/Bin/Configram533 b/board/novatek/ns02501/loader/Tools/Bin/Configram533 new file mode 100755 index 000000000000..a1cc52984189 Binary files /dev/null and b/board/novatek/ns02501/loader/Tools/Bin/Configram533 differ diff --git a/board/novatek/ns02501/loader/Tools/Bin/bfc b/board/novatek/ns02501/loader/Tools/Bin/bfc new file mode 100755 index 000000000000..5c85fdafce2a Binary files /dev/null and b/board/novatek/ns02501/loader/Tools/Bin/bfc differ diff --git a/board/novatek/ns02501/loader/Tools/Bin/encrypt_boot b/board/novatek/ns02501/loader/Tools/Bin/encrypt_boot new file mode 100755 index 000000000000..899da5df7a16 Binary files /dev/null and b/board/novatek/ns02501/loader/Tools/Bin/encrypt_boot differ diff --git a/board/novatek/ns02501/loader/Tools/Bin/encrypt_boot_dump b/board/novatek/ns02501/loader/Tools/Bin/encrypt_boot_dump new file mode 100755 index 000000000000..7feb8582c19b Binary files /dev/null and b/board/novatek/ns02501/loader/Tools/Bin/encrypt_boot_dump differ diff --git a/board/novatek/ns02501/loader/Tools/Bin/nvt-ld-op b/board/novatek/ns02501/loader/Tools/Bin/nvt-ld-op new file mode 100755 index 000000000000..99cf292f35b3 Binary files /dev/null and b/board/novatek/ns02501/loader/Tools/Bin/nvt-ld-op differ diff --git a/build.sh b/build.sh index 26c73a441360..2cee2b724de1 100755 --- a/build.sh +++ b/build.sh @@ -9,6 +9,8 @@ cd "$(dirname "$0")" export ARCH=arm export CROSS_COMPILE=${CROSS_COMPILE:-arm-linux-gnueabi-} +# The NVR dies' U-Boot is an AArch64 one (Debian/Ubuntu: gcc-aarch64-linux-gnu) +CROSS_COMPILE_A64=${CROSS_COMPILE_A64:-aarch64-linux-gnu-} # The loader is bare-metal code linked against Novatek's libraries: # a bare-metal toolchain if there is one, else U-Boot's if [ -z "${LOADER_CROSS_COMPILE}" ]; then @@ -20,7 +22,6 @@ if [ -z "${LOADER_CROSS_COMPILE}" ]; then fi BOOT_SRCDIR=$(pwd) -LOADER_SRCDIR=${BOOT_SRCDIR}/board/novatek/na51089/loader mkdir -p output @@ -33,33 +34,41 @@ mkconfig() { cat "$@" > "${builddir}/.config" } -# The SDK's loader, built in a copy: its make system writes into its tree +# The SDK's loader of a die (board/novatek//loader), built in a copy: +# its make system writes into its tree. The rest are its make variables +# (CHIP=, DRAM1_CLK=, ...). build_loader() { loaderdir=$1 - chip=$2 - dram_clk=$3 + die=$2 + shift 2 rm -rf "${loaderdir}" - cp -a "${LOADER_SRCDIR}" "${loaderdir}" + cp -a "${BOOT_SRCDIR}/board/novatek/${die}/loader" "${loaderdir}" if ! make -C "${loaderdir}/MakeCommon" release \ - CROSS_COMPILE="${LOADER_CROSS_COMPILE}" \ - CHIP="${chip}" DRAM1_CLK="${dram_clk}" \ + CROSS_COMPILE="${LOADER_CROSS_COMPILE}" "$@" \ >"${loaderdir}.log" 2>&1 &2 return 1 fi } -# Novatek NA51089: the mask ROM starts the loader, which trains the DDR, -# reads the device tree at 0x10000 and unpacks U-Boot from 0x20000 to its -# link address. +# Novatek NA51089, NA51055 / NA51084, NA51068, +# NS02501: the mask ROM starts the loader, which trains the DDR, reads the device tree at 0x10000 and +# unpacks U-Boot from 0x20000 to its link address. The NS02501 trees are +# packed too (nvt-image.py --fdt-lzma). +# build_nvt [loader make variables...] build_nvt() { soc=$1 - chip=$2 - dram_clk=$3 + die=$2 + chip=$3 + shift 3 builddir=${BOOT_SRCDIR}/output/build-${soc}-nor loaderdir=${BOOT_SRCDIR}/output/build-${soc}-loader - loader=${loaderdir}/Project/Model/Loader${chip}_Data/Release/LD98${chip}A.bin + # The binary is named after the part (LD98533A for CHIP 533QD) + part=$(echo "${chip}" | cut -c1-3) + loader=${loaderdir}/Project/Model/Loader${chip}_Data/Release/LD98${part}A.bin + image_opts= + [ "${die}" = ns02501 ] && image_opts=--fdt-lzma make_opts="-C ${BOOT_SRCDIR} O=${builddir} -j$(nproc)" rm -rf "${builddir}" @@ -70,32 +79,137 @@ build_nvt() { "${builddir}/scripts/dtc/dtc" -q -I dts -O dtb \ -o "${builddir}/${soc}.dtb" "openipc/${soc}.dts" || return 1 - build_loader "${loaderdir}" "${chip}" "${dram_clk}" || return 1 + build_loader "${loaderdir}" "${die}" CHIP="${chip}" "$@" || return 1 text=$(sed -n 's/^CONFIG_SYS_TEXT_BASE=//p' "${builddir}/.config") - python3 openipc/nvt-image.py "${loader}" "${builddir}/${soc}.dtb" \ - "${builddir}/u-boot.bin" "${text}" "output/u-boot-${soc}-nor.bin" + python3 openipc/nvt-image.py ${image_opts} "${loader}" \ + "${builddir}/${soc}.dtb" "${builddir}/u-boot.bin" "${text}" \ + "output/u-boot-${soc}-nor.bin" +} + +# Novatek NVR dies, AArch64: the board's loader and BL31 stay, the image +# is U-Boot's slot alone (openipc/nvt-nvr-image.py). FLASH is nor or nand, +# LAYOUT where the boards have their tree and U-Boot, and the boot area. +build_nvr() { + soc=$1 + flash=$2 + layout=$3 + builddir=${BOOT_SRCDIR}/output/build-${soc}-${flash} + make_opts="-C ${BOOT_SRCDIR} O=${builddir} -j$(nproc) CROSS_COMPILE=${CROSS_COMPILE_A64}" + + rm -rf "${builddir}" + mkconfig "${builddir}" openipc/openipc_config openipc/${soc}_config && \ + make ${make_opts} olddefconfig /dev/null && \ + make ${make_opts} /dev/null && + "${builddir}/scripts/dtc/dtc" -q -I dts -O dtb \ + -o "${builddir}/${soc}.dtb" "openipc/${soc}.dts" || return 1 + python3 - "${builddir}/${soc}.dtb" "output/u-boot-${soc}-${flash}.bin" \ + "output/u-boot-${soc}-qemu.bin" ${layout} <<'EOF' +import sys +fdt, slot, size = (int(x, 0) for x in sys.argv[4:7]) +img = bytearray(b'\xff' * size) +dtb = open(sys.argv[1], 'rb').read() +ub = open(sys.argv[2], 'rb').read() +if fdt + len(dtb) > slot or slot + len(ub) > size: + sys.exit('qemu image: tree %d B at 0x%x, U-Boot %d B at 0x%x, in 0x%x' + % (len(dtb), fdt, len(ub), slot, size)) +img[fdt:fdt + len(dtb)] = dtb +img[slot:slot + len(ub)] = ub +open(sys.argv[3], 'wb').write(img) +EOF } build_soc() { soc=$1 case "${soc}" in - # The DDR clocks of Xiongmai's loaders for these parts. The DDR is - # in the package: Configram560 writes its parameters from its own - # tables for -package=562/566, and the ConfigRam//*.ini path - # the make system names, which does not exist, is not read (a 560 - # profile of any clock and size gives the same loader). + # The DDR clocks of Xiongmai's loaders for the NT98562 / NT98566, + # and of the SDK's prebuilt LD98560A / LD98561A. The DDR of the + # 561/562/566 is in the package: Configram560 writes its + # parameters from its own tables for -package=561/562/566, and the + # ConfigRam//*.ini path the make system names, which does not + # exist, is not read (a 560 profile of any clock and size gives + # the same loader). The NT98560's DDR is on the board: its profile + # is ConfigRam/560/51089A_DRAM1__.ini, the + # SDK's 933 MHz, 4 Gbit. + nt98560) + build_nvt "${soc}" na51089 560 DRAM1_CLK=933 SDRAM_SIZE=4096 ;; + nt98561) + build_nvt "${soc}" na51089 561 DRAM1_CLK=522 ;; nt98562) - build_nvt "${soc}" 562 666 ;; + build_nvt "${soc}" na51089 562 DRAM1_CLK=666 ;; nt98566) - build_nvt "${soc}" 566 933 ;; + build_nvt "${soc}" na51089 566 DRAM1_CLK=933 ;; + # The NT9852x loader (MakeConfig.txt's tables). The NT98522 and + # NT98523 have their DDR1 in the package (512 Mbit, 1 Gbit, at + # 933 MHz), and no DDR2 here: the SDK board's external one is not + # every board's. The others' DDR is on the board: the SDK + # boards' 4 Gbit dies, DDR3 at 933 MHz (NT98520: DDR1 only; + # NT98525: DDR1 and DDR2) or 1066 MHz (NT98528/529, the 528 model). + # The 528 model's loader fills its 64 KiB with the LZMA decoder + # only without its own SD card update (FW98528A.bin from a card); + # U-Boot's recovery from SD is OpenIPC's. + nt98520) + build_nvt "${soc}" na51055 520 DRAM1_CLK=933 SDRAM_SIZE=4096 ;; + nt98522|nt98523) + build_nvt "${soc}" na51055 "${soc#nt98}" DRAM2_CLK=0 \ + SDRAM2_SIZE=0 ;; + nt98525) + build_nvt "${soc}" na51055 525 DRAM1_CLK=933 SDRAM_SIZE=4096 \ + DRAM2_CLK=933 SDRAM2_SIZE=4096 ;; + nt98528|nt98529) + # A Linux toolchain's build of the 528 flow stops after the + # DDR training (arm-linux-gnueabi 12/13 under qemu-hisilicon's + # nt98528); a bare-metal one's (arm-none-eabi 13.2, the SDK's + # Linaro 6.4 arm-eabi) boots. + case "${LOADER_CROSS_COMPILE}" in + *-linux-*) + echo "${soc}: its loader needs a bare-metal toolchain" \ + "(arm-none-eabi-), not ${LOADER_CROSS_COMPILE}" >&2 + return 1 ;; + esac + build_nvt "${soc}" na51055 "${soc#nt98}" MODEL=EMU_EVB_528 \ + DRAM1_CLK=1066 SDRAM_SIZE=4096 DRAM2_CLK=1066 \ + SDRAM2_SIZE=4096 STORAGEEXT=NONE ;; + # The NS02501 loader (ns02501_ldr). CHIP is the package + # (ModelConfig_EMU_EVB.txt): QB..QD, BC..BE, the last letter the + # DDR's size (B 512 Mbit, C 1 Gbit, D 2 Gbit, E 4 Gbit), whose + # parameters Configram533 has itself (there is no ConfigRam + # directory). The SDK's boards are the 532BD and 533QD, 2 Gbit at + # its default 1066 MHz. Another package is the same U-Boot with a + # loader built for its CHIP (and NVT_DDR_SIZE to match). + nt98532) + build_nvt "${soc}" ns02501 532BD DRAM1_CLK=1066 ;; + nt98533) + build_nvt "${soc}" ns02501 533QD DRAM1_CLK=1066 ;; + # The NVRs: NA51103 on SPI NOR (Xiongmai's layout, OpenIPC's from + # 0x40000), NA51090 on SPI NAND (the SDK's, env and UBI after it) + nt98332) + build_nvr "${soc}" nor "0x10000 0x20000 0x40000" ;; + nt98633) + build_nvr "${soc}" nand "0x40000 0xc0000 0x1a0000" ;; + # NA51068: the SDK's NAND models with the SPI NOR, its own DDR + # profile each (board/novatek/na51068/loader/Project/Model): + # NT98321 one 4 Gb DDR3 die at 1066 MHz, NT98323 one 4 Gb DDR4 + # die at 1200 MHz, as the SDK's cfg_98323_DDR4_4GX1_NOR_EVB. + nt98321) + build_nvt "${soc}" na51068 321 MODEL=321_DDR3_4GX1_NOR_EVB ;; + nt98323) + build_nvt "${soc}" na51068 323 MODEL=323_DDR4_4GX1_NOR_EVB ;; *) echo "unsupported SoC: ${soc}" >&2 return 1 ;; esac } -ALL_SOCS="nt98562 nt98566" +ALL_SOCS="nt98560 nt98561 nt98562 nt98566 nt98520 nt98522 nt98523 nt98525 nt98528 nt98529 nt98532 nt98533 nt98321 nt98323 nt98332 nt98633" SOCS="$@" [ -z "${SOCS}" ] && SOCS="${ALL_SOCS}" diff --git a/cmd/Kconfig b/cmd/Kconfig index cd51bf832aad..ba6bbda51147 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1412,7 +1412,7 @@ config CMD_SDRAM config CMD_SF bool "sf" - depends on DM_SPI_FLASH || SPI_FLASH || NVT_SFLASH + depends on DM_SPI_FLASH || SPI_FLASH || NVT_SFLASH || NVT_SPI020 default y if DM_SPI_FLASH help SPI Flash support diff --git a/common/openipc.c b/common/openipc.c index 002a3206f14f..8abcd2ec7a7b 100644 --- a/common/openipc.c +++ b/common/openipc.c @@ -749,7 +749,7 @@ static void altbootcmd_migrate(void) { int openipc_helper(void) { char msize[16]; - sprintf(msize, "%ldM", gd->ram_size / 1024 / 1024); + sprintf(msize, "%luM", (ulong)(gd->ram_size >> 20)); env_set("totalmem", msize); firmware_recovery(); firmware_scan(); diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index cf661a445cb3..b43bbbe4ecea 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -78,11 +78,12 @@ config MMC_SPI_CRC_ON If unsure, say N. config MMC_NVT - bool "Novatek NA51089 SD card (SDIO1)" - depends on ARCH_NOVATEK && MMC && !DM_MMC + bool "Novatek NA51089 / NT9852x / NS02501 SD card (SDIO1)" + depends on (NVT_NA51089 || NVT_NA51055 || NVT_NS02501) && MMC && !DM_MMC help - SDIO1 of the Novatek NA51089 (NT98562, NT98566), 4-bit, PIO - through its FIFO. + SDIO1 of the Novatek NA51089 (NT98560/561/562/566), of the + NT9852x dies, NA51055 and NA51084 (NT98520/522/523/525/528/529), + and of NS02501 (NT98532/533), 4-bit, PIO through its FIFO. config ARM_PL180_MMCI bool "ARM AMBA Multimedia Card Interface and compatible support" diff --git a/drivers/mmc/nvt_mmc.c b/drivers/mmc/nvt_mmc.c index 581ef686d555..09c3291a4852 100644 --- a/drivers/mmc/nvt_mmc.c +++ b/drivers/mmc/nvt_mmc.c @@ -1,6 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * SD card on SDIO1 of the Novatek NA51089 (NT98562, NT98566), non-DM. + * SD card on SDIO1 of the Novatek NA51089, NA51055, NA51084 and NS02501, + * non-DM. The first three take the same set-up (the vendor driver's + * default branch), but for the sampling clock; NS02501 its own pins, + * clock source code and pad drive (the NS02501 SDK's U-Boot 2021.10, + * nvt_ivot_mmc_a64.c and nvt_ivot_mmc_ns02501.h). * * Software sets a data phase up first (block size, DATA_LENGTH, DATA_EN, * the FIFO's direction, then FIFO_EN), then writes the command with @@ -49,6 +53,8 @@ #define SDIO_FIFO_STS (NVT_SDIO1_BASE + 0x108) #define SDIO_FIFO_CTRL (NVT_SDIO1_BASE + 0x10C) #define SDIO_FIFO_SWITCH (NVT_SDIO1_BASE + 0x1B0) +#define SDIO_AXI0 (NVT_SDIO1_BASE + 0x160) /* NS02501 */ +#define AXI_CH_DIS BIT(16) /* CMD */ #define CMD_NEED_RSP BIT(6) @@ -81,6 +87,7 @@ #define BUS_READY BIT(0) /* card not busy */ #define PHY_SW_RST BIT(0) #define PHY_BLK_FIFO_EN BIT(4) +#define DLY0_SRC_CLK_SEL BIT(13) /* the internal clock */ #define DLY0_PAD_CLK_SEL BIT(14) /* sample before the pad */ #define DLY1_READ_DLY_MASK (0xf << 28) #define DLY1_READ_DLY (0xa << 28) /* DATA/DET_READ_DLY = 2 */ @@ -97,14 +104,27 @@ #define TOP_PINMUX (NVT_TOP_BASE + 0x04) #define TOP_SDIO_EN BIT(14) #define TOP_PGPIO_C (NVT_TOP_BASE + 0xA0) -#define TOP_CGPIO11_16 (0x3f << 11) /* clock, command, data 0-3 */ +#ifdef CONFIG_NVT_NS02501 +#define TOP_SDIO1_PINS (0x3f << 13) /* CGPIO13-18 */ +#define SDIO_CLKSEL_192 (1 << 4) /* 0 is 480 MHz there */ +#else +#define TOP_SDIO1_PINS (0x3f << 11) /* clock, command, data 0-3 */ +#define SDIO_CLKSEL_192 0 +#endif #define CG_CLKSEL (NVT_CG_BASE + 0x20) -#define CG_SDIO_CLKSEL (3 << 4) /* 0: 192 MHz */ +#define CG_SDIO_CLKSEL (3 << 4) #define CG_SDIO_DIV (NVT_CG_BASE + 0x3C) #define CG_SDIO_DIV_MASK 0x7ff #define CG_SDIO1 BIT(2) /* in CLKEN0 and RSTN0 */ #define PAD_DS10 (NVT_PAD_BASE + 0x68) #define PAD_DS_SDIO1 0x222222 /* 15 mA, 3 bits per pin */ +/* + * NS02501: four bits per pin from PAD+0x50, CGPIO13-15 in [31:20] of + * +0x54 and 16-18 in [11:0] of +0x58; the SDK tree's default-speed + * driving, 2 on every pin + */ +#define PAD_DS_02501_C13 (NVT_PAD_BASE + 0x54) +#define PAD_DS_02501_C16 (NVT_PAD_BASE + 0x58) #define SDIO_SRC_CLK 192000000 #define SDIO_F_MIN 400000 @@ -171,20 +191,37 @@ static void nvt_mmc_set_clock(uint hz) static int nvt_mmc_init(struct mmc *mmc) { setbits_le32(TOP_PINMUX, TOP_SDIO_EN); - clrbits_le32(TOP_PGPIO_C, TOP_CGPIO11_16); + clrbits_le32(TOP_PGPIO_C, TOP_SDIO1_PINS); clrbits_le32(NVT_CG_RSTN0, CG_SDIO1); udelay(10); setbits_le32(NVT_CG_RSTN0, CG_SDIO1); - clrbits_le32(CG_CLKSEL, CG_SDIO_CLKSEL); + clrsetbits_le32(CG_CLKSEL, CG_SDIO_CLKSEL, SDIO_CLKSEL_192); clrsetbits_le32(CG_SDIO_DIV, CG_SDIO_DIV_MASK, DIV_ROUND_UP(SDIO_SRC_CLK, SDIO_F_MIN) - 1); setbits_le32(NVT_CG_CLKEN0, CG_SDIO1); - clrsetbits_le32(PAD_DS10, 0xffffff, PAD_DS_SDIO1); + if (IS_ENABLED(CONFIG_NVT_NS02501)) { + clrsetbits_le32(PAD_DS_02501_C13, 0xfff00000, 0x22200000); + clrsetbits_le32(PAD_DS_02501_C16, 0xfff, 0x222); + } else { + clrsetbits_le32(PAD_DS10, 0xffffff, PAD_DS_SDIO1); + } udelay(10); clrbits_le32(SDIO_CLK_CTRL, CLK_DIS); - /* Sample from the pad side, positive edge (neg-sample-edge = 0) */ - clrsetbits_le32(SDIO_DLY0, BIT(12) | BIT(13), DLY0_PAD_CLK_SEL); + /* NS02501's host has an AXI channel the vendor enables (for DMA) */ + if (IS_ENABLED(CONFIG_NVT_NS02501)) + clrbits_le32(SDIO_AXI0, AXI_CH_DIS); + /* + * Positive edge (neg-sample-edge = 0). The sampling clock: on + * NA51089, NA51084 and NS02501 from the pad, before it; on NA51055 + * the internal one, after the pad (the vendor's setphysample()). + */ + if (nvt_chip_id() == NVT_CHIP_NA51055) + clrsetbits_le32(SDIO_DLY0, BIT(12) | DLY0_PAD_CLK_SEL, + DLY0_SRC_CLK_SEL); + else + clrsetbits_le32(SDIO_DLY0, BIT(12) | DLY0_SRC_CLK_SEL, + DLY0_PAD_CLK_SEL); nvt_mmc_reset_data(); nvt_mmc_clock = SDIO_F_MIN; nvt_mmc_set_clock(SDIO_F_MIN); diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index ce67d1abde25..4af269c72a20 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -412,6 +412,16 @@ config NAND_MXC This enables the NAND driver for the NAND flash controller on the i.MX27 / i.MX31 / i.MX5 processors. +config NAND_NVT_SPI + bool "Novatek NA51090 SPI NAND" + depends on NVT_NA511XX + select SYS_NAND_SELF_INIT + imply CMD_NAND + help + The SPI NAND the Novatek NA51090 boots from, on its flash + controller run as a plain SPI master, with the chip's on-die + ECC. Non-DM. + config NAND_MXS bool "MXS NAND support" depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index a398aa9d8864..7300aa0645da 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o +obj-$(CONFIG_NAND_NVT_SPI) += nvt_spinand.o obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o obj-$(CONFIG_NAND_OCTEONTX) += octeontx_nand.o obj-$(CONFIG_NAND_OCTEONTX_HW_ECC) += octeontx_bch.o diff --git a/drivers/mtd/nand/raw/nvt_spinand.c b/drivers/mtd/nand/raw/nvt_spinand.c new file mode 100644 index 000000000000..ed21dcdd991b --- /dev/null +++ b/drivers/mtd/nand/raw/nvt_spinand.c @@ -0,0 +1,651 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SPI NAND behind the flash controller of the Novatek NA51090 (and + * NA51103, NA51089: the same controller). + * + * The controller is run as for SPI NOR (drivers/mtd/spi/nvt_sflash.c): + * one operation at a time, a command with up to four address bytes, then + * N bytes in or out, the chip held selected by hand across the two. The + * SPI NAND commands go out that way, byte for byte: PAGE DATA READ (0x13) + * into the chip's cache, GET FEATURE (0x0F) for its status, READ (0x03) + * of the cache, PROGRAM LOAD (0x02) and PROGRAM EXECUTE (0x10), BLOCK + * ERASE (0xD8). The controller's NAND mode, which the vendor U-Boot + * uses (drivers/mtd/nvt_flash_spi), folds these into page operations of + * its own; the plain path needs nothing chip-specific from it. + * + * The chip's on-die ECC is on, as the vendor runs it: a page read reports + * corrected and uncorrectable errors in the status register (C0 [5:4]), + * which this driver hands to the MTD layer. A whole page and its spare + * area go through one buffer, by DMA. The raw NAND framework sees a + * large-page chip with hardware ECC; bad blocks are marked as on any + * large-page NAND (spare byte 0). + * + * Non-DM, SYS_NAND_SELF_INIT: board_nand_init() registers nand0. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FL_MODULE0 (NVT_FLASH_BASE + 0x00) +#define FL_DLL1 (NVT_FLASH_BASE + 0x08) +#define FL_DLL2 (NVT_FLASH_BASE + 0x0C) +#define FL_SPI_CFG (NVT_FLASH_BASE + 0x14) +#define FL_CTRL0 (NVT_FLASH_BASE + 0x20) +#define FL_TIME2 (NVT_FLASH_BASE + 0x24) +#define FL_TIME0 (NVT_FLASH_BASE + 0x2C) +#define FL_TIME1 (NVT_FLASH_BASE + 0x30) +#define FL_COMMAND (NVT_FLASH_BASE + 0x34) +#define FL_COLADDR (NVT_FLASH_BASE + 0x38) +#define FL_ROWADDR (NVT_FLASH_BASE + 0x3C) +#define FL_INTMASK (NVT_FLASH_BASE + 0x44) +#define FL_CTRL_STS (NVT_FLASH_BASE + 0x48) +#define FL_DATAPORT (NVT_FLASH_BASE + 0x100) +#define FL_DATALEN (NVT_FLASH_BASE + 0x104) +#define FL_FIFO_STS (NVT_FLASH_BASE + 0x108) +#define FL_FIFO_CTRL (NVT_FLASH_BASE + 0x10C) +#define FL_DMASTART (NVT_FLASH_BASE + 0x110) + +#define MOD_CYC_MASK 0xf +#define MOD_ROW_CYC(n) (((n) - 1) << 2) +#define MOD_COL_CYC(n) ((n) - 1) +#define MOD_NOR (BIT(19) | BIT(20)) /* plain SPI */ +#define DLL1_SW_RESET BIT(0) +#define DLL1_SAMPCLK_INV BIT(2) +#define DLL1_SRC_CLK_SEL BIT(3) +#define DLL1_PAD_CLK_SEL BIT(20) +#define DLL2_INDLY(n) ((n) << 24) +#define DLL2_INDLY_MASK DLL2_INDLY(0x3f) +#define CFG_CS_MANUAL BIT(1) +#define CFG_CS_SEL BIT(3) +#define CFG_CS_HIGH BIT(4) +#define CFG_BUS_WIDTH_MASK (0x3 << 9) +#define CFG_PULL_WPHLD BIT(12) +#define CTRL0_OPER_EN BIT(12) +#define CTRL0_WP_EN BIT(13) +#define STS_COMP BIT(12) +#define FIFO_EN BIT(0) +#define FIFO_DMA BIT(1) +#define FIFO_WRITE BIT(2) +#define FIFO_CNT_MASK 0x1f +#define FIFO_EMPTY BIT(8) +#define FIFO_FULL BIT(9) +#define FIFO_BYTES 64 + +#define OP_CMD 0x07 +#define OP_CMD_ADDR 0x0C +#define OP_READ_N 0x18 +#define OP_WRITE_N 0x19 + +#define OP_TIMEOUT_MS 4500 + +#ifdef CONFIG_NVT_NA511XX +#define NVT_CG_FLASH_CLKEN (NVT_CG_BASE + 0x74) +#define CG_FLASH_CLKEN BIT(10) +#define NVT_CG_FLASH_RSTN (NVT_CG_BASE + 0x98) +#define CG_FLASH_RSTN BIT(1) +#define NVT_CG_FLASH_DIV (NVT_CG_BASE + 0x48) /* [21:16] */ +#define CG_FLASH_DIV_SHIFT 16 +#define NVT_PAD_FLASH_DRV (NVT_PAD_BASE + 0x50) +#define NVT_TOP_FLASH_EN (NVT_TOP_BASE + 0x04) +#define NVT_TOP_GPIO_C (NVT_TOP_BASE + 0xA0) +#endif +#define NVT_FLASH_SRC_HZ 480000000 +/* The NT98633 NVR's tree: /nand clock-frequency 24 MHz */ +#define SNAND_HZ 24000000 + +/* SPI NAND commands */ +#define SN_RESET 0xFF +#define SN_READ_ID 0x9F +#define SN_GET_FEATURE 0x0F +#define SN_SET_FEATURE 0x1F +#define SN_WREN 0x06 +#define SN_PAGE_READ 0x13 +#define SN_READ_CACHE 0x03 +#define SN_PROG_LOAD 0x02 +#define SN_PROG_EXEC 0x10 +#define SN_BLOCK_ERASE 0xD8 + +#define FEAT_PROT 0xA0 +#define FEAT_CFG 0xB0 +#define FEAT_STATUS 0xC0 +#define CFG_ECC_EN BIT(4) +#define CFG_BUF BIT(3) /* Winbond: buffer read mode */ +#define STS_OIP BIT(0) +#define STS_E_FAIL BIT(2) +#define STS_P_FAIL BIT(3) +#define STS_ECC_MASK (3 << 4) +#define STS_ECC_CORRECTED (1 << 4) +#define STS_ECC_FAILED (2 << 4) + +#define MFR_WINBOND 0xEF + +/* The parts the NVRs and their SDK list, 2 KiB pages, one plane */ +static struct nand_flash_dev nvt_spinand_ids[] = { + {"W25N01GV", {.id = {0xef, 0xaa, 0x21} }, SZ_2K, 128, SZ_128K, 0, 3, + 64, NAND_ECC_INFO(1, SZ_512) }, + {"W25N02KV", {.id = {0xef, 0xaa, 0x22} }, SZ_2K, 256, SZ_128K, 0, 3, + 128, NAND_ECC_INFO(8, SZ_512) }, + {"GD5F1GQ4UB", {.id = {0xc8, 0xd1} }, SZ_2K, 128, SZ_128K, 0, 2, + 128, NAND_ECC_INFO(8, SZ_512) }, + {"GD5F1GQ5UE", {.id = {0xc8, 0x51} }, SZ_2K, 128, SZ_128K, 0, 2, + 128, NAND_ECC_INFO(4, SZ_512) }, + {"MX35LF1GE4AB", {.id = {0xc2, 0x12} }, SZ_2K, 128, SZ_128K, 0, 2, + 64, NAND_ECC_INFO(4, SZ_512) }, + {"XT26G01C", {.id = {0x0b, 0x11} }, SZ_2K, 128, SZ_128K, 0, 2, + 128, NAND_ECC_INFO(8, SZ_512) }, + {NULL} +}; + +static struct { + struct nand_chip chip; + u8 *buf; /* a page and its spare area */ + unsigned int pos, len; /* what read_byte/read_buf/write_buf use */ + int page; /* in the chip's cache, or -1 */ + int prog_page; /* SEQIN's page */ + u8 status; /* NAND_CMD_STATUS: the last program/erase */ + u8 ecc; /* STS_ECC_* of the last page read */ + u8 id[8]; +} sn; + +/* ---- the controller, as nvt_sflash.c runs it ---- */ + +static void fl_addr_cycles(unsigned int n) +{ + clrsetbits_le32(FL_MODULE0, MOD_CYC_MASK, + MOD_ROW_CYC(n) | MOD_COL_CYC(1)); +} + +static void fl_setup(u32 op, u32 row, u32 len, u32 fifo) +{ + clrbits_le32(FL_INTMASK, STS_COMP); + writel(fifo, FL_FIFO_CTRL); + writel(0, FL_CTRL0); + writel(0, FL_COLADDR); + writel(row, FL_ROWADDR); + writel(len, FL_DATALEN); + writel(op | (fifo & FIFO_WRITE ? 0 : CTRL0_WP_EN), FL_CTRL0); + writel(STS_COMP, FL_CTRL_STS); + if (len) + writel(fifo | FIFO_EN, FL_FIFO_CTRL); + setbits_le32(FL_INTMASK, STS_COMP); +} + +static void fl_start(u32 cmd) +{ + writel(cmd, FL_COMMAND); + setbits_le32(FL_CTRL0, CTRL0_OPER_EN); +} + +static int fl_wait(void) +{ + ulong start = get_timer(0); + + while (!(readl(FL_CTRL_STS) & STS_COMP)) { + if (get_timer(start) > OP_TIMEOUT_MS) { + printf("NAND: the flash controller timed out\n"); + return -ETIMEDOUT; + } + } + writel(STS_COMP, FL_CTRL_STS); + return 0; +} + +/* A command and @n address bytes (MSB first), then nothing */ +static int fl_cmd(u8 cmd, unsigned int n, u32 addr) +{ + if (n) { + fl_addr_cycles(n); + fl_setup(OP_CMD_ADDR, addr, 0, 0); + } else { + fl_setup(OP_CMD, 0, 0, 0); + } + fl_start(cmd); + return fl_wait(); +} + +static int fl_fifo_wait(u32 bits, unsigned int words) +{ + ulong start = get_timer(0); + u32 sts; + + for (;;) { + sts = readl(FL_FIFO_STS); + if (bits ? sts & bits : sts & FIFO_FULL || + (sts & FIFO_CNT_MASK) >= words) + return 0; + if (get_timer(start) > OP_TIMEOUT_MS) { + printf("NAND: the flash FIFO timed out\n"); + return -ETIMEDOUT; + } + } +} + +static int fl_pio_in(u8 *buf, unsigned int len) +{ + while (len) { + unsigned int n = min_t(unsigned int, len, FIFO_BYTES), i; + + if (fl_fifo_wait(0, DIV_ROUND_UP(n, 4))) + return -ETIMEDOUT; + for (i = 0; i < n; i += 4) { + u32 w = readl(FL_DATAPORT); + + memcpy(buf + i, &w, min(4U, n - i)); + } + buf += n; + len -= n; + } + return fl_wait(); +} + +static int fl_pio_out(const u8 *buf, unsigned int len) +{ + bool tail = len % 4; + + while (len) { + unsigned int n = min_t(unsigned int, len, FIFO_BYTES), i; + + if (fl_fifo_wait(FIFO_EMPTY, 0)) + return -ETIMEDOUT; + for (i = 0; i < n; i += 4) { + u32 w = 0; + + memcpy(&w, buf + i, min(4U, n - i)); + writel(w, FL_DATAPORT); + } + buf += n; + len -= n; + } + if (tail) { + mdelay(1); + clrbits_le32(FL_FIFO_CTRL, FIFO_EN); + } + return fl_wait(); +} + +static void fl_cs(bool on) +{ + if (on) { + setbits_le32(FL_SPI_CFG, CFG_CS_HIGH); + setbits_le32(FL_SPI_CFG, CFG_CS_MANUAL); + clrbits_le32(FL_SPI_CFG, CFG_CS_HIGH); + } else { + setbits_le32(FL_SPI_CFG, CFG_CS_HIGH); + clrbits_le32(FL_SPI_CFG, CFG_CS_MANUAL); + } +} + +/* + * A command and @n address bytes, then @len bytes in (@out NULL) or out, + * the chip selected throughout. Whole cache lines go by DMA. + */ +static int fl_xfer(u8 cmd, unsigned int n, u32 addr, u8 *in, const u8 *out, + unsigned int len) +{ + bool dma = len >= ARCH_DMA_MINALIGN && !(len % ARCH_DMA_MINALIGN) && + !((ulong)(in ? in : out) % ARCH_DMA_MINALIGN); + ulong b = (ulong)(in ? in : out); + int ret; + + fl_cs(true); + ret = fl_cmd(cmd, n, addr); + if (!ret && in) { + if (dma) { + invalidate_dcache_range(b, b + len); + writel(b, FL_DMASTART); + fl_setup(OP_READ_N, 0, len, FIFO_DMA); + fl_start(cmd); + ret = fl_wait(); + invalidate_dcache_range(b, b + len); + } else { + fl_setup(OP_READ_N, 0, len, 0); + fl_start(cmd); + ret = fl_pio_in(in, len); + } + } else if (!ret && out) { + if (dma) { + flush_dcache_range(b, b + len); + writel(b, FL_DMASTART); + fl_setup(OP_WRITE_N, 0, len, FIFO_DMA | FIFO_WRITE); + fl_start(cmd); + ret = fl_wait(); + } else { + fl_setup(OP_WRITE_N, 0, len, FIFO_WRITE); + fl_start(cmd); + ret = fl_pio_out(out, len); + } + } + fl_cs(false); + return ret; +} + +/* ---- the SPI NAND chip ---- */ + +static u8 sn_get_feature(u8 reg) +{ + u8 v; + + if (fl_xfer(SN_GET_FEATURE, 1, reg, &v, NULL, 1)) + return 0xff; + return v; +} + +static int sn_set_feature(u8 reg, u8 val) +{ + return fl_cmd(SN_SET_FEATURE, 2, reg << 8 | val); +} + +/* Wait for the operation in progress; its status, or -ETIMEDOUT */ +static int sn_wait(void) +{ + ulong start = get_timer(0); + u8 sts; + + do { + sts = sn_get_feature(FEAT_STATUS); + if (sts != 0xff && !(sts & STS_OIP)) + return sts; + } while (get_timer(start) < OP_TIMEOUT_MS); + printf("NAND: the chip stays busy (status %02x)\n", sts); + return -ETIMEDOUT; +} + +/* PAGE DATA READ, then the cache: the page and its spare area */ +static int sn_read_page(int page) +{ + struct mtd_info *mtd = nand_to_mtd(&sn.chip); + unsigned int len = mtd->writesize + mtd->oobsize; + int sts; + + sn.page = -1; + if (fl_cmd(SN_PAGE_READ, 3, page)) + return -EIO; + sts = sn_wait(); + if (sts < 0) + return sts; + sn.ecc = sts & STS_ECC_MASK; + /* Column 0, then a dummy byte */ + if (fl_xfer(SN_READ_CACHE, 3, 0, sn.buf, NULL, len)) + return -EIO; + sn.page = page; + return 0; +} + +/* WRITE ENABLE, PROGRAM LOAD of the whole buffer, PROGRAM EXECUTE */ +static int sn_program(int page) +{ + struct mtd_info *mtd = nand_to_mtd(&sn.chip); + unsigned int len = mtd->writesize + mtd->oobsize; + int sts; + + sn.page = -1; + if (fl_cmd(SN_WREN, 0, 0) || + fl_xfer(SN_PROG_LOAD, 2, 0, NULL, sn.buf, len) || + fl_cmd(SN_PROG_EXEC, 3, page)) + return -EIO; + sts = sn_wait(); + if (sts < 0) + return sts; + return sts & STS_P_FAIL ? -EIO : 0; +} + +static int sn_erase(int page) +{ + int sts; + + sn.page = -1; + if (fl_cmd(SN_WREN, 0, 0) || fl_cmd(SN_BLOCK_ERASE, 3, page)) + return -EIO; + sts = sn_wait(); + if (sts < 0) + return sts; + return sts & STS_E_FAIL ? -EIO : 0; +} + +/* ---- the raw NAND framework's hooks ---- */ + +static void sn_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int column, + int page) +{ + int ret; + + switch (cmd) { + case NAND_CMD_RESET: + fl_cmd(SN_RESET, 0, 0); + mdelay(1); + sn_wait(); + sn.page = -1; + break; + case NAND_CMD_READID: + /* No ONFI or JEDEC parameter page here: 0x20, 0x40 read 0 */ + memset(sn.id, 0, sizeof(sn.id)); + if (column == 0) + fl_xfer(SN_READ_ID, 1, 0, sn.id, NULL, sizeof(sn.id)); + sn.pos = 0; + sn.len = sizeof(sn.id); + break; + case NAND_CMD_READ0: + case NAND_CMD_READOOB: + if (cmd == NAND_CMD_READOOB) + column += mtd->writesize; + ret = page == sn.page ? 0 : sn_read_page(page); + if (ret) { + /* What a failed read leaves: an erased-looking page */ + memset(sn.buf, 0xff, mtd->writesize + mtd->oobsize); + sn.ecc = STS_ECC_FAILED; + } + sn.pos = column; + sn.len = mtd->writesize + mtd->oobsize; + break; + case NAND_CMD_SEQIN: + memset(sn.buf, 0xff, mtd->writesize + mtd->oobsize); + sn.prog_page = page; + sn.pos = column; + sn.len = mtd->writesize + mtd->oobsize; + break; + case NAND_CMD_PAGEPROG: + ret = sn_program(sn.prog_page); + sn.status = NAND_STATUS_READY | NAND_STATUS_WP | + (ret ? NAND_STATUS_FAIL : 0); + break; + case NAND_CMD_ERASE1: + ret = sn_erase(page); + sn.status = NAND_STATUS_READY | NAND_STATUS_WP | + (ret ? NAND_STATUS_FAIL : 0); + break; + case NAND_CMD_ERASE2: + break; + case NAND_CMD_STATUS: + sn.id[0] = sn.status; + sn.pos = 0; + sn.len = 1; + break; + default: + printf("NAND: command %#x not handled\n", cmd); + } +} + +/* Bytes come from the ID or status, else from the page buffer */ +static u8 *sn_src(void) +{ + return sn.len <= sizeof(sn.id) ? sn.id : sn.buf; +} + +static u8 sn_read_byte(struct mtd_info *mtd) +{ + if (sn.pos >= sn.len) + return 0xff; + return sn_src()[sn.pos++]; +} + +static void sn_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + int n = min_t(int, len, sn.len - sn.pos); + + if (n > 0) { + memcpy(buf, sn_src() + sn.pos, n); + sn.pos += n; + } else { + n = 0; + } + memset(buf + n, 0xff, len - n); +} + +static void sn_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + int n = min_t(int, len, sn.len - sn.pos); + + if (n > 0) { + memcpy(sn.buf + sn.pos, buf, n); + sn.pos += n; + } +} + +static int sn_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) +{ + return sn.status; +} + +static void sn_select_chip(struct mtd_info *mtd, int cs) +{ +} + +/* The page is in the buffer: what the on-die ECC said of it */ +static int sn_read_page_ecc(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + chip->read_buf(mtd, buf, mtd->writesize); + if (oob_required) + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + if (sn.ecc == STS_ECC_FAILED) { + mtd->ecc_stats.failed++; + return 0; + } + if (sn.ecc) { + mtd->ecc_stats.corrected++; + return chip->ecc.strength; + } + return 0; +} + +static int sn_write_page_ecc(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int oob_required, int page) +{ + chip->write_buf(mtd, buf, mtd->writesize); + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + return 0; +} + +/* A u32 property of the loader's device tree */ +static u32 sn_fdt_u32(const char *path, const char *prop, u32 def) +{ + const void *fdt = nvt_loader_fdt(); + const fdt32_t *val = NULL; + int node; + + if (fdt) { + node = fdt_path_offset(fdt, path); + if (node >= 0) + val = fdt_getprop(fdt, node, prop, NULL); + } + return val ? fdt32_to_cpu(*val) : def; +} + +/* + * Clock, reset, pins and PHY, as the vendor's spinand.c drv_nand_reset() + * and nand_phy_config() do on NA51090, at the tree's clock + */ +static void sn_hw_init(void) +{ + u32 hz = sn_fdt_u32("/nand", "clock-frequency", SNAND_HZ); + u32 pins = 3, drv; + + hz = clamp_t(u32, hz, NVT_FLASH_SRC_HZ / 64, 80000000); + setbits_le32(NVT_CG_FLASH_CLKEN, CG_FLASH_CLKEN); + setbits_le32(NVT_CG_FLASH_RSTN, CG_FLASH_RSTN); + writel(0x06002222, FL_TIME0); + writel(0x7f0f, FL_TIME1); + if (sn_fdt_u32("/top/spi", "pinmux", 0) & 0x20) + pins |= BIT(2); + setbits_le32(NVT_TOP_FLASH_EN, pins); + clrbits_le32(NVT_TOP_GPIO_C, 0x3f | (pins & BIT(2) ? BIT(6) : 0)); + clrsetbits_le32(NVT_CG_FLASH_DIV, 0x3f << CG_FLASH_DIV_SHIFT, + (NVT_FLASH_SRC_HZ / hz - 1) << CG_FLASH_DIV_SHIFT); + drv = hz <= 24000000 ? 0x0111101 : hz <= 60000000 ? 0x0222202 : + 0x0222203; + clrsetbits_le32(NVT_PAD_FLASH_DRV, 0xfffffff, drv); + setbits_le32(FL_MODULE0, MOD_NOR); + writel(0x5f51, FL_TIME2); + + clrsetbits_le32(FL_DLL1, DLL1_SRC_CLK_SEL, + DLL1_SAMPCLK_INV | DLL1_PAD_CLK_SEL); + clrsetbits_le32(FL_DLL2, DLL2_INDLY_MASK, DLL2_INDLY(8)); + setbits_le32(FL_DLL1, DLL1_SW_RESET); + while (readl(FL_DLL1) & DLL1_SW_RESET) + ; + clrsetbits_le32(FL_SPI_CFG, CFG_BUS_WIDTH_MASK | CFG_CS_SEL, + CFG_PULL_WPHLD); +} + +void board_nand_init(void) +{ + struct nand_chip *chip = &sn.chip; + struct mtd_info *mtd = nand_to_mtd(chip); + u8 cfg; + int ret; + + sn_hw_init(); + sn.page = -1; + /* Nothing failed yet; the framework also reads WP from here */ + sn.status = NAND_STATUS_READY | NAND_STATUS_WP; + sn.buf = memalign(ARCH_DMA_MINALIGN, + ALIGN(SZ_4K + 256, ARCH_DMA_MINALIGN)); + if (!sn.buf) + return; + + chip->cmdfunc = sn_cmdfunc; + chip->read_byte = sn_read_byte; + chip->read_buf = sn_read_buf; + chip->write_buf = sn_write_buf; + chip->waitfunc = sn_waitfunc; + chip->select_chip = sn_select_chip; + chip->chip_delay = 0; + chip->options = NAND_NO_SUBPAGE_WRITE; + + ret = nand_scan_ident(mtd, 1, nvt_spinand_ids); + if (ret) { + printf("NAND: no SPI NAND known here (ID %02x %02x %02x)\n", + sn.id[0], sn.id[1], sn.id[2]); + return; + } + + /* Writable everywhere; the on-die ECC on, Winbond's buffer mode */ + sn_set_feature(FEAT_PROT, 0); + cfg = sn_get_feature(FEAT_CFG) | CFG_ECC_EN; + if (sn.id[0] == MFR_WINBOND) + cfg |= CFG_BUF; + sn_set_feature(FEAT_CFG, cfg); + + chip->ecc.mode = NAND_ECC_HW; + chip->ecc.size = mtd->writesize; + chip->ecc.bytes = 0; + chip->ecc.strength = chip->ecc_strength_ds ?: 1; + chip->ecc.read_page = sn_read_page_ecc; + chip->ecc.write_page = sn_write_page_ecc; + + ret = nand_scan_tail(mtd); + if (!ret) + ret = nand_register(0, mtd); + if (ret) + printf("NAND: cannot register (%d)\n", ret); +} diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index b59a15f9eae3..0e77ac428642 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -37,16 +37,24 @@ config SPI_FLASH If unsure, say N config NVT_SFLASH - bool "Novatek NA51089 SPI NOR" - depends on ARCH_NOVATEK && !SPI_FLASH && !DM_SPI_FLASH + bool "Novatek SPI NOR (NA51089, NT9852x, NS02501, NA51103, NA51090)" + depends on ARCH_NOVATEK && !NVT_NA51068 && !SPI_FLASH && !DM_SPI_FLASH help - The SPI NOR the Novatek NA51089 boots from, on its flash - controller. The driver provides spi_flash_probe() directly, - without the SPI and spi-nor layers. + The SPI NOR the Novatek camera dies and the NA51103 boot from, on + their flash controller (NA51090's too). The driver provides + spi_flash_probe() directly, without the SPI and spi-nor layers. + +config NVT_SPI020 + bool "Novatek NA51068 SPI NOR (FTSPI020)" + depends on ARCH_NOVATEK && NVT_NA51068 && !SPI_FLASH && !DM_SPI_FLASH + help + The SPI NOR the Novatek NA51068 (NT98321, NT98323) boots from, on + its Faraday FTSPI020 flash controller. The driver provides + spi_flash_probe() directly, without the SPI and spi-nor layers. config SF_DEFAULT_BUS int "SPI Flash default bus identifier" - depends on SPI_FLASH || DM_SPI_FLASH || NVT_SFLASH + depends on SPI_FLASH || DM_SPI_FLASH || NVT_SFLASH || NVT_SPI020 default 0 help The default bus may be provided by the platform @@ -55,7 +63,7 @@ config SF_DEFAULT_BUS config SF_DEFAULT_CS int "SPI Flash default Chip-select" - depends on SPI_FLASH || DM_SPI_FLASH || NVT_SFLASH + depends on SPI_FLASH || DM_SPI_FLASH || NVT_SFLASH || NVT_SPI020 default 0 help The default chip select may be provided by the platform @@ -64,7 +72,7 @@ config SF_DEFAULT_CS config SF_DEFAULT_MODE hex "SPI Flash default mode (see include/spi.h)" - depends on SPI_FLASH || DM_SPI_FLASH || NVT_SFLASH + depends on SPI_FLASH || DM_SPI_FLASH || NVT_SFLASH || NVT_SPI020 default 0x0 help The default mode may be provided by the platform @@ -76,7 +84,7 @@ config SF_DEFAULT_MODE config SF_DEFAULT_SPEED int "SPI Flash default speed in Hz" - depends on SPI_FLASH || DM_SPI_FLASH || NVT_SFLASH + depends on SPI_FLASH || DM_SPI_FLASH || NVT_SFLASH || NVT_SPI020 default 1000000 help The default speed may be provided by the platform diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 066c64033526..5d1a070780e6 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_MTD) += sf_mtd.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o obj-$(CONFIG_NVT_SFLASH) += nvt_sflash.o +obj-$(CONFIG_NVT_SPI020) += nvt_spi020.o diff --git a/drivers/mtd/spi/nvt_sflash.c b/drivers/mtd/spi/nvt_sflash.c index c71617b0743d..b9490b040960 100644 --- a/drivers/mtd/spi/nvt_sflash.c +++ b/drivers/mtd/spi/nvt_sflash.c @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * SPI NOR behind the flash controller of the Novatek NA51089. + * SPI NOR behind the flash controller of the Novatek NA51089 (and the + * NT9852x dies), NS02501, NA51103 and NA51090 (the same controller; only + * its clock, reset, pins and PHY timing differ, and the NVR dies' FIFO is + * 128 bytes, not 64). * * The controller runs one operation at a time: software loads COMMAND, * ROWADDR (sent MSB first, as many bytes as MODULE0 says) and DATALEN, @@ -10,8 +13,8 @@ * command with an address, a block erase that polls the status itself, * an automatic status poll, and N bytes in or out. Reads and programs * hold the chip selected by hand across the command-and-address operation - * and the data one. Data goes through a 64-byte FIFO, a word at a time, - * or by DMA. + * and the data one. Data goes through the FIFO, a word at a time, or by + * DMA. * * After the vendor U-Boot 2019.04 (drivers/mtd/nvt_flash_spi/ and * drivers/mtd/spiflash/spinor.c), single lane, as it reads at 48 MHz. @@ -28,9 +31,10 @@ #include #include #include -#include +#include #include #include +#include #include #define FL_MODULE0 (NVT_FLASH_BASE + 0x00) @@ -64,6 +68,8 @@ #define DLL1_SRC_CLK_SEL BIT(3) #define DLL1_PAD_CLK_SEL BIT(20) /* DLL2 */ +#define DLL2_OUTDLY(n) ((n) << 16) +#define DLL2_OUTDLY_MASK DLL2_OUTDLY(0x3f) #define DLL2_INDLY(n) ((n) << 24) #define DLL2_INDLY_MASK DLL2_INDLY(0x3f) /* SPI_CFG */ @@ -86,6 +92,7 @@ #define FIFO_CNT_MASK 0x1f /* words */ #define FIFO_EMPTY BIT(8) #define FIFO_FULL BIT(9) +/* What a PIO transfer moves per FIFO check: the smaller FIFO, NA51089's */ #define FIFO_BYTES 64 /* Operations */ @@ -98,17 +105,39 @@ #define OP_WRITE_N 0x19 #define OP_AUTO_STATUS 0x1D -/* The clock gate that would stop the controller with the chip selected */ -#define NVT_CG_AUTOGATE (NVT_CG_BASE + 0xB0) -#define CG_AUTOGATE_FLASH BIT(19) -#define NVT_CG_FLASH_DIV (NVT_CG_BASE + 0x40) /* [17:12] */ +#ifdef CONFIG_NVT_NS02501 +/* 480 MHz / 2 (the NS02501 U-Boot's nvt_flash_spi_int.h) */ +#define NVT_FLASH_SRC_HZ 240000000 +#else #define NVT_FLASH_SRC_HZ 480000000 +#endif #define NVT_TOP_FLASH_EN (NVT_TOP_BASE + 0x04) #define NVT_TOP_GPIO_C (NVT_TOP_BASE + 0xA0) /* pads as GPIO */ +#ifdef CONFIG_NVT_NA511XX +#define NVT_CG_FLASH_CLKEN (NVT_CG_BASE + 0x74) +#define CG_FLASH_CLKEN BIT(10) +#define NVT_CG_FLASH_RSTN (NVT_CG_BASE + 0x98) +#define CG_FLASH_RSTN BIT(1) +#define NVT_CG_FLASH_DIV (NVT_CG_BASE + 0x48) /* [21:16] */ +#define CG_FLASH_DIV_SHIFT 16 +#define NVT_PAD_FLASH_DRV (NVT_PAD_BASE + 0x50) +/* The boards' trees ask for 12 MHz (/nor clock-frequency), as the vendor */ +#define SF_HZ 12000000 +#else +#ifdef CONFIG_NVT_NS02501 +#define NVT_PAD_FLASH_DRV (NVT_PAD_BASE + 0x50) /* 4 bits a pin */ +#else +/* The clock gate that would stop the controller with the chip selected */ +#define NVT_CG_AUTOGATE (NVT_CG_BASE + 0xB0) +#define CG_AUTOGATE_FLASH BIT(19) #define NVT_TOP_SRAM_SD (NVT_TOP_BASE + 0x1000) /* SRAM shut down */ #define NVT_PAD_FLASH_DRV (NVT_PAD_BASE + 0x40) +#endif +#define NVT_CG_FLASH_DIV (NVT_CG_BASE + 0x40) /* [17:12] */ +#define CG_FLASH_DIV_SHIFT 12 #define SF_HZ 48000000 +#endif #define SZ_PAGE 256 #define SZ_SECTOR SZ_64K /* The vendor U-Boot gives every operation this long */ @@ -198,6 +227,26 @@ static int fl_wait_fifo(u32 bits, u32 val) return 0; } +/* + * Wait for at least @n bytes in the FIFO. A full one counts: the count + * field holds 31 words, and the NVR dies' FIFO takes 32. + */ +static int fl_wait_fifo_in(unsigned int n) +{ + ulong start = get_timer(0); + u32 sts; + + for (;;) { + sts = readl(FL_FIFO_STS); + if (sts & FIFO_FULL || (sts & FIFO_CNT_MASK) >= DIV_ROUND_UP(n, 4)) + return 0; + if (get_timer(start) > OP_TIMEOUT_MS) { + printf("SF: the flash FIFO timed out\n"); + return -ETIMEDOUT; + } + } +} + /* The words of a PIO read, as the FIFO fills */ static int fl_pio_in(u8 *buf, unsigned int len) { @@ -207,10 +256,7 @@ static int fl_pio_in(u8 *buf, unsigned int len) unsigned int n = min_t(unsigned int, len, FIFO_BYTES); unsigned int i; - if (n == FIFO_BYTES) - ret = fl_wait_fifo(FIFO_FULL, FIFO_FULL); - else - ret = fl_wait_fifo(FIFO_CNT_MASK, DIV_ROUND_UP(n, 4)); + ret = fl_wait_fifo_in(n); if (ret) return ret; for (i = 0; i < n; i += 4) { @@ -264,14 +310,18 @@ static int fl_pio_out(const u8 *buf, unsigned int len) static void fl_cs_manual(bool on) { if (on) { +#ifdef NVT_CG_AUTOGATE clrbits_le32(NVT_CG_AUTOGATE, CG_AUTOGATE_FLASH); +#endif setbits_le32(FL_SPI_CFG, CFG_CS_HIGH); setbits_le32(FL_SPI_CFG, CFG_CS_MANUAL); clrbits_le32(FL_SPI_CFG, CFG_CS_HIGH); } else { setbits_le32(FL_SPI_CFG, CFG_CS_HIGH); clrbits_le32(FL_SPI_CFG, CFG_CS_MANUAL); +#ifdef NVT_CG_AUTOGATE setbits_le32(NVT_CG_AUTOGATE, CG_AUTOGATE_FLASH); +#endif } } @@ -506,6 +556,111 @@ static int nvt_sf_erase(struct mtd_info *mtd, struct erase_info *instr) return 0; } +#if defined(CONFIG_NVT_NA511XX) || defined(CONFIG_NVT_NS02501) +/* A u32 property of the loader's device tree */ +static u32 fl_fdt_u32(const char *path, const char *prop, u32 def) +{ + const void *fdt = nvt_loader_fdt(); + const fdt32_t *val = NULL; + int node; + + if (fdt) { + node = fdt_path_offset(fdt, path); + if (node >= 0) + val = fdt_getprop(fdt, node, prop, NULL); + } + return val ? fdt32_to_cpu(*val) : def; +} +#endif + +#ifdef CONFIG_NVT_NA511XX +/* + * Clock, reset, pins, timing and PHY, as the vendor's nvt_spinor_reset() + * and nand_phy_config() do on the NVR dies, at the clock the board's + * tree asks for + */ +static void fl_hw_init(void) +{ + u32 hz = fl_fdt_u32("/nor", "clock-frequency", SF_HZ); + u32 pins = 3, drv = 0, time2 = 0x5f51; + + if (hz < NVT_FLASH_SRC_HZ / 64) + hz = NVT_FLASH_SRC_HZ / 64; + if (IS_ENABLED(CONFIG_NVT_NA51090) && hz > 80000000) + hz = 80000000; + setbits_le32(NVT_CG_FLASH_CLKEN, CG_FLASH_CLKEN); + setbits_le32(NVT_CG_FLASH_RSTN, CG_FLASH_RSTN); + writel(0x06002222, FL_TIME0); + writel(0x7f0f, FL_TIME1); + /* The pins, and the second chip select's if the tree says so */ + if (fl_fdt_u32("/top/spi", "pinmux", 0) & 0x20) + pins |= BIT(2); + setbits_le32(NVT_TOP_FLASH_EN, pins); + clrbits_le32(NVT_TOP_GPIO_C, 0x3f | (pins & BIT(2) ? BIT(6) : 0)); + clrsetbits_le32(NVT_CG_FLASH_DIV, 0x3f << CG_FLASH_DIV_SHIFT, + (NVT_FLASH_SRC_HZ / hz - 1) << CG_FLASH_DIV_SHIFT); + if (IS_ENABLED(CONFIG_NVT_NA51090)) + drv = hz <= 24000000 ? 0x0111101 : + hz <= 60000000 ? 0x0222202 : 0x0222203; + else if (hz > 48000000) + drv = 0x0111101; + clrsetbits_le32(NVT_PAD_FLASH_DRV, 0xfffffff, drv); + setbits_le32(FL_MODULE0, MOD_NOR); + /* NA51103 wants a CS low to clock time (TSLCH) of 3 at least */ + if (IS_ENABLED(CONFIG_NVT_NA51103)) + time2 = (time2 & ~0xf) | 3; + writel(time2, FL_TIME2); + + clrsetbits_le32(FL_DLL1, DLL1_SRC_CLK_SEL, + DLL1_SAMPCLK_INV | DLL1_PAD_CLK_SEL); + clrsetbits_le32(FL_DLL2, DLL2_INDLY_MASK, + DLL2_INDLY(IS_ENABLED(CONFIG_NVT_NA51090) ? 8 : 0)); + setbits_le32(FL_DLL1, DLL1_SW_RESET); + while (readl(FL_DLL1) & DLL1_SW_RESET) + ; + /* Chip select 0 (SPI_CFG bit 3 selects the second) */ + clrsetbits_le32(FL_SPI_CFG, CFG_BUS_WIDTH_MASK | BIT(3), CFG_PULL_WPHLD); +} +#elif defined(CONFIG_NVT_NS02501) +/* + * NS02501, as its vendor U-Boot's nvt_flash_spi.c (built without its + * pinctrl driver, as the SDK's NOR config is) and nand_phy_config(): the + * flash pins in TOP+0x04 [13:12] (1: SPI NOR) and off GPIO, the clock + * the tree asks for (the SDK's: 12 MHz) from 240 MHz, the pads' fixed + * drive (data level 3, clock 5, chip select 3), and from 48 MHz an + * output delay of 3. No SRAM shut-down bit, no clock auto-gating here. + */ +static void fl_hw_init(void) +{ + u32 hz = fl_fdt_u32("/nor", "clock-frequency", SF_HZ); + + if (hz < NVT_FLASH_SRC_HZ / 64) + hz = NVT_FLASH_SRC_HZ / 64; + if (hz > SF_HZ) + hz = SF_HZ; + setbits_le32(NVT_CG_CLKEN0, NVT_CG_FLASH); + setbits_le32(NVT_CG_RSTN0, NVT_CG_FLASH); + writel(0x06002222, FL_TIME0); + writel(0x7f0f, FL_TIME1); + clrsetbits_le32(NVT_TOP_FLASH_EN, 3 << 12, 1 << 12); + clrbits_le32(NVT_TOP_GPIO_C, 0x140f); + clrsetbits_le32(NVT_CG_FLASH_DIV, 0x3f << CG_FLASH_DIV_SHIFT, + (NVT_FLASH_SRC_HZ / hz - 1) << CG_FLASH_DIV_SHIFT); + writel(0x33333333, NVT_PAD_FLASH_DRV); + clrsetbits_le32(NVT_PAD_FLASH_DRV + 4, 0xf0f00, 0x30500); + setbits_le32(FL_MODULE0, MOD_NOR); + writel(0x9f51, FL_TIME2); + + clrsetbits_le32(FL_DLL1, DLL1_SRC_CLK_SEL, + DLL1_SAMPCLK_INV | DLL1_PAD_CLK_SEL); + clrsetbits_le32(FL_DLL2, DLL2_INDLY_MASK | DLL2_OUTDLY_MASK, + DLL2_OUTDLY(hz >= 48000000 ? 3 : 0)); + setbits_le32(FL_DLL1, DLL1_SW_RESET); + while (readl(FL_DLL1) & DLL1_SW_RESET) + ; + clrsetbits_le32(FL_SPI_CFG, CFG_BUS_WIDTH_MASK, CFG_PULL_WPHLD); +} +#else /* Clock, reset, pins, timing and PHY, as the vendor's nvt_spinor_reset() */ static void fl_hw_init(void) { @@ -515,8 +670,8 @@ static void fl_hw_init(void) writel(0x7f0f, FL_TIME1); setbits_le32(NVT_TOP_FLASH_EN, BIT(13)); clrbits_le32(NVT_TOP_GPIO_C, 0x50f); - clrsetbits_le32(NVT_CG_FLASH_DIV, 0x3f << 12, - (NVT_FLASH_SRC_HZ / SF_HZ - 1) << 12); + clrsetbits_le32(NVT_CG_FLASH_DIV, 0x3f << CG_FLASH_DIV_SHIFT, + (NVT_FLASH_SRC_HZ / SF_HZ - 1) << CG_FLASH_DIV_SHIFT); clrbits_le32(NVT_TOP_SRAM_SD, BIT(17)); clrsetbits_le32(NVT_PAD_FLASH_DRV, 0x3f00ff, 0x150055); setbits_le32(FL_MODULE0, MOD_NOR); @@ -530,6 +685,7 @@ static void fl_hw_init(void) ; clrsetbits_le32(FL_SPI_CFG, CFG_BUS_WIDTH_MASK, CFG_PULL_WPHLD); } +#endif static struct spi_flash nvt_flash; static int nvt_announced; diff --git a/drivers/mtd/spi/nvt_spi020.c b/drivers/mtd/spi/nvt_spi020.c new file mode 100644 index 000000000000..91bbf24d4aa2 --- /dev/null +++ b/drivers/mtd/spi/nvt_spi020.c @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SPI NOR behind the Faraday FTSPI020 flash controller of the Novatek + * NA51068 (NT98321, NT98323). + * + * Each command is four register writes: the flash address (CMD0), its + * length with the dummy cycles and the instruction length (CMD1), the + * data length (CMD2), then the instruction with its mode bits (CMD3), + * which starts it. Data goes through the 32-byte FIFO at DATA, a word at + * a time, gated by STATUS; INT_STS bit 0 says the command is done. A + * status read either returns one SR byte in READ_STS, or, polled by the + * controller, ends only once the busy bit (CTRL RD_STS_LOC, bit 0) is + * clear, which is how a program or an erase is waited for. + * + * After the vendor U-Boot 2016.07 of the NT9832x SDK + * (drivers/mtd/nvt_flash_spi/nvt_flash_spi020*.c, spiflash/spi020_nor.c), + * single lane and PIO, as it runs (its DMA and FIFO checksum paths are + * compiled out). Like nvt_sflash, this driver provides spi_flash_probe() + * itself, so mainline's non-DM spi_flash_*() wrappers, the sf command and + * the environment in SPI flash work without the SPI and spi-nor layers. + * Parts over 16 MiB take the 4-byte address opcodes, as the vendor's do. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FC(off) (NVT_FLASH_BASE + (off)) +#define FC_CMD0 FC(0x00) /* flash address */ +#define FC_CMD1 FC(0x04) +#define CMD1_ALEN(n) (n) +#define CMD1_DUMMY(n) ((n) << 16) +#define CMD1_INST_LEN1 (1 << 24) +#define FC_CMD2 FC(0x08) /* data length */ +#define FC_CMD3 FC(0x0C) /* writing it starts the command */ +#define CMD3_WRITE BIT(1) +#define CMD3_RD_STS BIT(2) +#define CMD3_RD_STS_SW BIT(3) /* one read, else polled */ +#define CMD3_INST(c) ((u32)(c) << 24) +#define FC_CTRL FC(0x10) +#define CTRL_CLK_DIV(n) (n) /* /2, /4, /6, /8 */ +#define FC_STATUS FC(0x18) +#define STATUS_TXFIFO_EMPTY BIT(0) +#define STATUS_RXFIFO_READY BIT(1) +#define FC_INT_CTRL FC(0x20) +#define INT_CTRL_DMA_EN BIT(0) +#define FC_INT_STS FC(0x24) +#define INT_STS_DONE BIT(0) +#define FC_READ_STS FC(0x28) +#define FC_DLY FC(0x60) +#define DLY_RX_SAMPLE_EDGE BIT(17) +#define FC_DATA FC(0x100) +#define FC_FIFO 32 + +/* CG: the controller's reset and clock gate */ +#define CG_FLASH_RSTN (NVT_CG_BASE + 0x54) +#define CG_FLASH_RSTN_BIT BIT(11) +#define CG_FLASH_GATE (NVT_CG_BASE + 0x68) +#define CG_FLASH_GATE_BIT BIT(9) + +#define SZ_PAGE 256 +#define SZ_SECTOR SZ_64K + +#define CMD_WRSR 0x01 +#define CMD_PP 0x02 +#define CMD_READ 0x03 +#define CMD_WRDI 0x04 +#define CMD_RDSR 0x05 +#define CMD_WREN 0x06 +#define CMD_PP_4B 0x12 +#define CMD_READ_4B 0x13 +#define CMD_RDSR2 0x35 +#define CMD_RDID 0x9F +#define CMD_SE_64K 0xD8 +#define CMD_SE_64K_4B 0xDC + +#define SR1_WEL BIT(1) +#define SR1_BP 0x7C /* GigaDevice/Winbond and alikes: BP0-4 */ +#define SR1_BP_OTHER 0x3C /* BP0-3 */ + +#define MFR_GIGADEVICE 0xc8 +#define MFR_WINBOND 0xef +#define MFR_XMC 0x20 +#define MFR_ZBIT 0x5e +#define MFR_BOYA 0x68 + +enum { XFER_NORMAL, XFER_STATUS, XFER_POLL }; + +static struct { + struct spi_flash flash; + u32 ctrl; /* the clock divider */ + u8 alen; /* 3, or 4 past 16 MiB */ + bool protect; /* block protection stays: refuse writes */ + bool announced; +} sf; + +static int fc_wait(ulong reg, u32 mask, ulong ms) +{ + ulong start = get_timer(0); + + while (!(readl(reg) & mask)) { + if (get_timer(start) > ms) + return -ETIMEDOUT; + } + return 0; +} + +static int fc_pio_in(u8 *buf, unsigned int len) +{ + while (len) { + unsigned int n = min(len, (unsigned int)FC_FIFO); + + if (fc_wait(FC_STATUS, STATUS_RXFIFO_READY, 1000)) + return -ETIMEDOUT; + len -= n; + while (n) { + u32 w = readl(FC_DATA); + unsigned int i, k = min(n, 4u); + + for (i = 0; i < k; i++, w >>= 8) + *buf++ = w; + n -= k; + } + } + return 0; +} + +/* + * Whole words: the caller pads the data to them. The controller sends + * only the data length (CMD2) of what the last word holds. + */ +static int fc_pio_out(const u8 *buf, unsigned int len) +{ + len = ALIGN(len, 4); + while (len) { + unsigned int n = min(len, (unsigned int)FC_FIFO); + + if (fc_wait(FC_STATUS, STATUS_TXFIFO_EMPTY, 1000)) + return -ETIMEDOUT; + len -= n; + for (; n; n -= 4, buf += 4) + writel(get_unaligned_le32(buf), FC_DATA); + } + return 0; +} + +/* + * One command: @alen address bytes, @len data bytes in (@out NULL) or + * out; XFER_STATUS returns SR1 in *@sts, XFER_POLL waits until the flash + * is no longer busy, for up to @ms. + */ +static int fc_xfer(u8 cmd, u32 addr, unsigned int alen, void *in, + const void *out, unsigned int len, int mode, u8 *sts, + ulong ms) +{ + u32 cmd3 = CMD3_INST(cmd); + int ret = 0; + + writel(sf.ctrl, FC_CTRL); + writel(DLY_RX_SAMPLE_EDGE, FC_DLY); + if (alen) + writel(addr, FC_CMD0); + if (mode == XFER_NORMAL) { + writel(len, FC_CMD2); + if (!in) + cmd3 |= CMD3_WRITE; + } else { + writel(0, FC_CMD2); + cmd3 |= CMD3_RD_STS | (mode == XFER_STATUS ? CMD3_RD_STS_SW : 0); + } + writel(CMD1_ALEN(alen) | CMD1_INST_LEN1, FC_CMD1); + writel(cmd3, FC_CMD3); + + if (len && mode == XFER_NORMAL) + ret = in ? fc_pio_in(in, len) : fc_pio_out(out, len); + if (!ret) + ret = fc_wait(FC_INT_STS, INT_STS_DONE, ms); + writel(INT_STS_DONE, FC_INT_STS); + if (ret) + printf("SF: command %02x timed out\n", cmd); + else if (sts) + *sts = readl(FC_READ_STS); + return ret; +} + +/* A status register, or the transfer's error: *v is left alone on one */ +static int sf_read_reg(u8 cmd, u8 *v) +{ + return fc_xfer(cmd, 0, 0, NULL, NULL, 0, XFER_STATUS, v, 100); +} + +/* Until the flash is no longer busy: the controller polls SR1 */ +static int sf_wait_ready(ulong ms) +{ + return fc_xfer(CMD_RDSR, 0, 0, NULL, NULL, 0, XFER_POLL, NULL, ms); +} + +static int sf_write_enable(void) +{ + int ret = fc_xfer(CMD_WREN, 0, 0, NULL, NULL, 0, XFER_NORMAL, NULL, 100); + u8 sr; + + if (!ret) + ret = sf_read_reg(CMD_RDSR, &sr); + if (ret) + return ret; + if (!(sr & SR1_WEL)) { + printf("SF: write enable does not stick\n"); + return -EIO; + } + return 0; +} + +static int sf_write_sr(const u8 *sr, unsigned int len) +{ + u8 buf[4] = { sr[0], len > 1 ? sr[1] : 0xff, 0xff, 0xff }; + int ret = sf_write_enable(); + + if (!ret) + ret = fc_xfer(CMD_WRSR, 0, 0, NULL, buf, len, XFER_NORMAL, + NULL, 100); + return ret ? ret : sf_wait_ready(1000); +} + +/* + * Clear the block protection a vendor loader or firmware may have left + * set, and check that it went: a program or erase of a protected block + * is accepted and dropped, which would pass for success. + */ +static int sf_unprotect(u8 mfr) +{ + u8 sr[2]; + u8 bp = SR1_BP_OTHER; + int ret = sf_read_reg(CMD_RDSR, &sr[0]); + + if (ret) + return ret; + if (sr[0] == 0xff) + return 0; + if (mfr == MFR_GIGADEVICE || mfr == MFR_WINBOND || mfr == MFR_XMC || + mfr == MFR_ZBIT || mfr == MFR_BOYA) + bp = SR1_BP; + if (!(sr[0] & bp)) + return 0; + + printf("SF: block protection (SR1 %02x), clearing\n", sr[0]); + sr[0] &= ~bp; + if (bp == SR1_BP) { + /* QE lives in SR2, written as WRSR's second byte: keep it */ + ret = sf_read_reg(CMD_RDSR2, &sr[1]); + if (!ret) + ret = sf_write_sr(sr, 2); + } else { + ret = sf_write_sr(sr, 1); + } + if (!ret) + ret = sf_read_reg(CMD_RDSR, &sr[0]); + if (ret || sr[0] & bp) { + printf("SF: block protection stays (SR1 %02x): writes refused\n", + sr[0]); + return -EROFS; + } + return 0; +} + +static int nvt_sf_read(struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, u_char *buf) +{ + int ret = 0; + + *retlen = 0; + if (from > mtd->size || len > mtd->size - from) + return -EINVAL; + /* In pieces, so that a timeout stays a timeout */ + while (len && !ret) { + unsigned int n = min_t(size_t, len, SZ_1M); + + ret = fc_xfer(sf.alen == 4 ? CMD_READ_4B : CMD_READ, from, + sf.alen, buf, NULL, n, XFER_NORMAL, NULL, 1000); + from += n; + buf += n; + len -= n; + if (!ret) + *retlen += n; + } + return ret; +} + +/* PAGE PROGRAM within a page, from a copy padded to whole words */ +static int sf_program(u32 addr, const u8 *buf, unsigned int len) +{ + u8 page[SZ_PAGE + 4] __aligned(4); + int ret; + + memcpy(page, buf, len); + memset(page + len, 0xff, 4); + ret = sf_write_enable(); + if (!ret) + ret = fc_xfer(sf.alen == 4 ? CMD_PP_4B : CMD_PP, addr, sf.alen, + NULL, page, len, XFER_NORMAL, NULL, 100); + return ret ? ret : sf_wait_ready(100); +} + +static int nvt_sf_write(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) +{ + int ret; + + *retlen = 0; + if (to > mtd->size || len > mtd->size - to) + return -EINVAL; + if (sf.protect) + return -EROFS; + while (len) { + unsigned int n = min_t(size_t, len, + SZ_PAGE - (to & (SZ_PAGE - 1))); + + ret = sf_program(to, buf, n); + if (ret) + return ret; + to += n; + buf += n; + len -= n; + *retlen += n; + } + return 0; +} + +static int nvt_sf_erase(struct mtd_info *mtd, struct erase_info *instr) +{ + u32 addr, end; + int ret; + + /* Checked in 64 bits, before anything can wrap */ + if (instr->addr % SZ_SECTOR || instr->len % SZ_SECTOR || + instr->addr > mtd->size || instr->len > mtd->size - instr->addr) + return -EINVAL; + if (sf.protect) { + instr->state = MTD_ERASE_FAILED; + return -EROFS; + } + instr->state = MTD_ERASING; + addr = instr->addr; + end = instr->addr + instr->len; + for (; addr < end; addr += SZ_SECTOR) { + ret = sf_write_enable(); + if (!ret) + ret = fc_xfer(sf.alen == 4 ? CMD_SE_64K_4B : CMD_SE_64K, + addr, sf.alen, NULL, NULL, 0, XFER_NORMAL, + NULL, 100); + /* A 64 KiB erase takes up to 2 s on the usual parts */ + if (!ret) + ret = sf_wait_ready(5000); + if (ret) { + instr->fail_addr = addr; + instr->state = MTD_ERASE_FAILED; + return ret; + } + } + instr->state = MTD_ERASE_DONE; + return 0; +} + +/* + * The controller's clock and reset, as the vendor's nvt_spinor_reset(); + * the pins are the loader's, which booted from this flash. The clock + * divider follows the loader's device tree, /nor@fa900000 + * clock-frequency, 48 MHz on the SDK's boards. + */ +static void fc_hw_init(void) +{ + const void *fdt = nvt_loader_fdt(); + const fdt32_t *val = NULL; + u32 hz = 12000000; + int node; + + if (fdt) { + node = fdt_path_offset(fdt, "/nor@fa900000"); + if (node >= 0) + val = fdt_getprop(fdt, node, "clock-frequency", NULL); + if (val) + hz = fdt32_to_cpu(*val); + } + sf.ctrl = CTRL_CLK_DIV(hz < 25000000 ? 3 : hz < 37500000 ? 2 : + hz < 75000000 ? 1 : 0); + + setbits_le32(CG_FLASH_RSTN, CG_FLASH_RSTN_BIT); + clrbits_le32(CG_FLASH_GATE, CG_FLASH_GATE_BIT); + clrbits_le32(FC_INT_CTRL, INT_CTRL_DMA_EN); + writel(INT_STS_DONE, FC_INT_STS); +} + +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_flash *flash = &sf.flash; + struct mtd_info *mtd = &flash->mtd; + u8 id[4]; + u32 jedec, size; + + fc_hw_init(); + if (fc_xfer(CMD_RDID, 0, 0, id, NULL, sizeof(id), XFER_NORMAL, NULL, + 100)) { + printf("SF: the flash controller does not answer\n"); + return NULL; + } + jedec = id[0] << 16 | id[1] << 8 | id[2]; + if (!jedec || jedec == 0xffffff) { + printf("SF: no flash (JEDEC id %06x)\n", jedec); + return NULL; + } + /* + * The last ID byte is log2 of the size, as the vendor driver takes it + * (trace-stdtable in the SDK's trees) + */ + if (id[2] >= 0x10 && id[2] <= 0x1c) { + size = 1 << id[2]; + } else { + size = SZ_8M; + if (!sf.announced) + printf("SF: JEDEC %06x: size unknown, taking 8 MiB\n", jedec); + } + sf.alen = size > SZ_16M ? 4 : 3; + sf.protect = sf_unprotect(id[0]) < 0; + + memset(flash, 0, sizeof(*flash)); + flash->name = "nvt-spi020"; + flash->size = size; + flash->page_size = SZ_PAGE; + flash->sector_size = SZ_SECTOR; + flash->erase_size = SZ_SECTOR; + flash->erase_opcode = sf.alen == 4 ? CMD_SE_64K_4B : CMD_SE_64K; + flash->read_opcode = sf.alen == 4 ? CMD_READ_4B : CMD_READ; + flash->program_opcode = sf.alen == 4 ? CMD_PP_4B : CMD_PP; + + mtd->name = "nvt-spi020"; + mtd->type = MTD_NORFLASH; + mtd->flags = MTD_CAP_NORFLASH; + mtd->size = size; + mtd->erasesize = SZ_SECTOR; + mtd->writesize = 1; + mtd->writebufsize = SZ_PAGE; + mtd->_read = nvt_sf_read; + mtd->_write = nvt_sf_write; + mtd->_erase = nvt_sf_erase; + mtd->priv = flash; + + /* Once: the environment and common/openipc.c probe again and again */ + if (!sf.announced) { + sf.announced = true; + printf("SF: Detected JEDEC %06x with page size %u Bytes, erase size %u KiB, total %u MiB\n", + jedec, SZ_PAGE, SZ_SECTOR >> 10, size >> 20); + } + return flash; +} + +void spi_flash_free(struct spi_flash *flash) +{ +} diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 03687f02d12f..bce2a152b6ba 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -226,13 +226,14 @@ config DWC_ETH_QOS_TEGRA186 configuration used in NVIDIA's Tegra186 chip. config NVT_EQOS - bool "Novatek NA51089 Ethernet" + bool "Novatek Ethernet (NA51089, NT9852x, NS02501, NA51068, NA51103, NA51090)" depends on ARCH_NOVATEK && !DM_ETH select PHYLIB help - The Synopsys DWC Ethernet QoS MAC of the Novatek NA51089 - (NT98562, NT98566), non-DM. Board code brings up its clocks, pins - and the embedded PHY, and calls nvt_eqos_initialize(). + The Synopsys DWC Ethernet QoS MAC of the Novatek camera and NVR + dies (two on NA51068), non-DM. Board code brings up their clocks, + pins and the embedded PHY, and calls nvt_eqos_initialize() or + nvt_eqos_register(). config E1000 bool "Intel PRO/1000 Gigabit Ethernet support" diff --git a/drivers/net/nvt_eqos.c b/drivers/net/nvt_eqos.c index f0d5fcfefb14..d04af603cc23 100644 --- a/drivers/net/nvt_eqos.c +++ b/drivers/net/nvt_eqos.c @@ -1,14 +1,16 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Ethernet MAC of the Novatek NA51089: a Synopsys DWC Ethernet QoS - * (GMAC 4.x) core, run polled with one Tx and one Rx descriptor ring. + * Ethernet MACs of the Novatek dies: one on NA51089, NA51055, NA51084, + * NS02501, NA51103 and NA51090, two on NA51068 (at 0xFCC00000 and + * 0xFCD00000): a Synopsys DWC Ethernet QoS (GMAC 4.x) core, run polled + * with one Tx and one Rx descriptor ring each. * * The block has the MAC at 0x0000, the MTL (the FIFOs) at 0x0D00 and the * DMA, channel 0 from 0x1100, at 0x1000; Novatek's glue (interface and * clock selection, LEDs) at 0x3000 and the embedded PHY's analog part at * 0x3800. Board code sets those last two up before this driver runs - * (board/novatek/na51089), and the order matters: the DMA software reset - * only completes once the PHY feeds the MAC its Rx clock. + * (board/novatek/na51089, na51068, na511xx), and the order matters: the DMA + * software reset only completes once the PHY feeds the MAC its Rx clock. * * Descriptors are four words, OWN in DES3 bit 31, each padded to a cache * line; the DMA skips the padding (DSL). The DMA works through a ring up @@ -30,10 +32,10 @@ #include #include #include -#include #include +#include -#define EQ(off) (NVT_ETH_BASE + (off)) +#define EQ(off) (eqos->base + (off)) /* MAC */ #define MAC_CFG EQ(0x000) @@ -95,6 +97,7 @@ #define DMA_SWR BIT(0) /* DMA_SYSBUS_MODE: outstanding AXI reads, as the vendor driver */ #define SYSBUS_RD_OSR_LMT(n) ((n) << 16) +#define SYSBUS_AALE BIT(10) /* automatic AXI low-power entry */ /* DMA_CH_CTRL */ #define CH_PBLX8 BIT(16) #define CH_DSL(n) ((n) << 18) /* skip, in 8-byte units */ @@ -111,10 +114,29 @@ #define DES3_ES BIT(15) /* write-back, Rx */ #define DES3_LEN(v) ((v) & 0x7fff) -/* The core's own descriptor, padded to a cache line */ +/* + * The core's own descriptor, padded to a cache line on NA51089. The DMA + * skips the padding (DSL) in units of its bus width, 3 bits' worth: 8 + * bytes on NA51089, NA51084 and NS02501, but 4 on NA51055 (the vendor's + * eth_na51055.c), where no skip reaches a 64-byte line. The NT9852x + * targets therefore pack the descriptors, no skip: this port runs with + * the data cache off (SYS_DCACHE_OFF), so no cache line is shared with + * the DMA. + */ +#ifdef CONFIG_NVT_NA51055 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) +#error "packed descriptors need the data cache off" +#endif +#define DESC_SIZE 16 +#else +#define DESC_SIZE ARCH_DMA_MINALIGN +#endif + struct eqos_desc { u32 des0, des1, des2, des3; - u8 pad[ARCH_DMA_MINALIGN - 16]; +#if DESC_SIZE > 16 + u8 pad[DESC_SIZE - 16]; +#endif }; #define TX_DESCS 4 @@ -122,28 +144,24 @@ struct eqos_desc { /* A frame with a VLAN tag fits, a cache-line multiple */ #define PKT_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) -/* What the CSR clock (CG+0x10 [9:8]) is, as an MDC divider (CR) */ -#define NVT_CG_SYSCLK (NVT_CG_BASE + 0x10) -static const u8 mdio_cr[4] = { - 3, /* 48 MHz: CR 35-60 MHz, /26 */ - 0, /* 60 MHz: CR 60-100 MHz, /42 */ - 0, /* 80 MHz */ - 1, /* 120 MHz: CR 100-150 MHz, /62 */ -}; +#define NVT_EQOS_MAX 2 -static struct eqos_desc tx_descs[TX_DESCS] __aligned(ARCH_DMA_MINALIGN); -static struct eqos_desc rx_descs[RX_DESCS] __aligned(ARCH_DMA_MINALIGN); -static u8 tx_buf[PKT_SIZE] __aligned(ARCH_DMA_MINALIGN); -static u8 rx_bufs[RX_DESCS][PKT_SIZE] __aligned(ARCH_DMA_MINALIGN); - -static struct { +struct nvt_eqos { + struct eqos_desc tx_descs[TX_DESCS]; + struct eqos_desc rx_descs[RX_DESCS]; + u8 tx_buf[PKT_SIZE]; + u8 rx_bufs[RX_DESCS][PKT_SIZE]; struct eth_device dev; struct mii_dev *mii; struct phy_device *phy; phy_interface_t intf; + ulong base; u32 cr; int tx_idx, rx_idx; -} eqos; +} __aligned(ARCH_DMA_MINALIGN); + +static struct nvt_eqos eqos_devs[NVT_EQOS_MAX]; +static int eqos_count; static void eqos_flush(void *p, size_t len) { @@ -167,16 +185,18 @@ static int eqos_wait(ulong reg, u32 mask, ulong ms) return 0; } -static int eqos_mdio(int addr, int reg, u32 goc) +static int eqos_mdio(struct nvt_eqos *eqos, int addr, int reg, u32 goc) { - writel(MDIO_PA(addr) | MDIO_RDA(reg) | MDIO_CR(eqos.cr) | goc | MDIO_GB, + writel(MDIO_PA(addr) | MDIO_RDA(reg) | MDIO_CR(eqos->cr) | goc | MDIO_GB, MAC_MDIO_ADDR); return eqos_wait(MAC_MDIO_ADDR, MDIO_GB, 10); } static int eqos_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { - if (eqos_mdio(addr, reg, MDIO_GOC_READ)) + struct nvt_eqos *eqos = bus->priv; + + if (eqos_mdio(eqos, addr, reg, MDIO_GOC_READ)) return -ETIMEDOUT; return readl(MAC_MDIO_DATA) & 0xffff; } @@ -184,12 +204,15 @@ static int eqos_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) static int eqos_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val) { + struct nvt_eqos *eqos = bus->priv; + writel(val, MAC_MDIO_DATA); - return eqos_mdio(addr, reg, MDIO_GOC_WRITE); + return eqos_mdio(eqos, addr, reg, MDIO_GOC_WRITE); } static int eqos_write_hwaddr(struct eth_device *dev) { + struct nvt_eqos *eqos = dev->priv; const u8 *a = dev->enetaddr; writel(a[4] | a[5] << 8, MAC_ADDR0_HI); @@ -199,18 +222,21 @@ static int eqos_write_hwaddr(struct eth_device *dev) static int eqos_start(struct eth_device *dev, struct bd_info *bis) { + struct nvt_eqos *eqos = dev->priv; + struct eqos_desc *tx_descs = eqos->tx_descs; + struct eqos_desc *rx_descs = eqos->rx_descs; struct phy_device *phy; u32 cfg, hwf1; int i, ret; - if (!eqos.phy) { - phy = phy_connect(eqos.mii, -1, dev, eqos.intf); + if (!eqos->phy) { + phy = phy_connect(eqos->mii, -1, dev, eqos->intf); if (!phy) return -ENODEV; phy_config(phy); - eqos.phy = phy; + eqos->phy = phy; } - phy = eqos.phy; + phy = eqos->phy; ret = phy_startup(phy); if (ret) return ret; @@ -247,23 +273,30 @@ static int eqos_start(struct eth_device *dev, struct bd_info *bis) writel(RXQ0_EN, MAC_RXQ_CTRL0); eqos_write_hwaddr(dev); - /* Bursts of 16 x 8 beats, as the vendor driver */ - writel(CH_PBLX8 | CH_DSL((ARCH_DMA_MINALIGN - 16) / 8), DMA_CH_CTRL); + /* + * Bursts of 16 x 8 beats, as the vendor drivers; the NT9852x and + * NS02501 ones also let the AXI master idle into low power (AALE). + */ + writel(CH_PBLX8 | CH_DSL((DESC_SIZE - 16) / 8), DMA_CH_CTRL); writel(CH_PBL(16) | CH_TX_OSP, DMA_CH_TX_CTRL); writel(CH_PBL(16) | CH_RBSZ(PKT_SIZE), DMA_CH_RX_CTRL); - writel(SYSBUS_RD_OSR_LMT(2), DMA_SYSBUS_MODE); - - memset(tx_descs, 0, sizeof(tx_descs)); - memset(rx_descs, 0, sizeof(rx_descs)); + /* The NT9852x vendor driver also sets AALE */ + writel(SYSBUS_RD_OSR_LMT(2) | + (IS_ENABLED(CONFIG_NVT_NA51055) || + IS_ENABLED(CONFIG_NVT_NS02501) ? SYSBUS_AALE : 0), + DMA_SYSBUS_MODE); + + memset(tx_descs, 0, sizeof(eqos->tx_descs)); + memset(rx_descs, 0, sizeof(eqos->rx_descs)); for (i = 0; i < RX_DESCS; i++) { - rx_descs[i].des0 = (ulong)rx_bufs[i]; + rx_descs[i].des0 = (ulong)eqos->rx_bufs[i]; rx_descs[i].des3 = DES3_OWN | DES3_BUF1V; } - eqos_flush(tx_descs, sizeof(tx_descs)); - eqos_flush(rx_descs, sizeof(rx_descs)); - eqos_inval(rx_bufs, sizeof(rx_bufs)); - eqos.tx_idx = 0; - eqos.rx_idx = 0; + eqos_flush(tx_descs, sizeof(eqos->tx_descs)); + eqos_flush(rx_descs, sizeof(eqos->rx_descs)); + eqos_inval(eqos->rx_bufs, sizeof(eqos->rx_bufs)); + eqos->tx_idx = 0; + eqos->rx_idx = 0; writel((ulong)tx_descs, DMA_CH_TXDESC_LIST); writel(TX_DESCS - 1, DMA_CH_TXDESC_RING_LEN); writel((ulong)rx_descs, DMA_CH_RXDESC_LIST); @@ -282,6 +315,8 @@ static int eqos_start(struct eth_device *dev, struct bd_info *bis) static void eqos_halt(struct eth_device *dev) { + struct nvt_eqos *eqos = dev->priv; + /* Let what is queued go out, and what came in drain */ clrbits_le32(DMA_CH_TX_CTRL, CH_ST_SR); eqos_wait(MTL_TXQ0_DEBUG, TXQ_BUSY, 10); @@ -292,21 +327,22 @@ static void eqos_halt(struct eth_device *dev) static int eqos_send(struct eth_device *dev, void *packet, int len) { - struct eqos_desc *d = &tx_descs[eqos.tx_idx]; + struct nvt_eqos *eqos = dev->priv; + struct eqos_desc *d = &eqos->tx_descs[eqos->tx_idx]; ulong start; - memcpy(tx_buf, packet, len); - eqos_flush(tx_buf, ALIGN(len, ARCH_DMA_MINALIGN)); + memcpy(eqos->tx_buf, packet, len); + eqos_flush(eqos->tx_buf, ALIGN(len, ARCH_DMA_MINALIGN)); - d->des0 = (ulong)tx_buf; + d->des0 = (ulong)eqos->tx_buf; d->des1 = 0; d->des2 = len; mb(); d->des3 = DES3_OWN | DES3_FD | DES3_LD | len; eqos_flush(d, sizeof(*d)); - eqos.tx_idx = (eqos.tx_idx + 1) % TX_DESCS; - writel((ulong)&tx_descs[eqos.tx_idx], DMA_CH_TXDESC_TAIL); + eqos->tx_idx = (eqos->tx_idx + 1) % TX_DESCS; + writel((ulong)&eqos->tx_descs[eqos->tx_idx], DMA_CH_TXDESC_TAIL); /* The buffer is reused: wait for the DMA to have read it */ start = get_timer(0); @@ -321,8 +357,9 @@ static int eqos_send(struct eth_device *dev, void *packet, int len) static int eqos_recv(struct eth_device *dev) { - struct eqos_desc *d = &rx_descs[eqos.rx_idx]; - u8 *buf = rx_bufs[eqos.rx_idx]; + struct nvt_eqos *eqos = dev->priv; + struct eqos_desc *d = &eqos->rx_descs[eqos->rx_idx]; + u8 *buf = eqos->rx_bufs[eqos->rx_idx]; u32 des3; int len; @@ -346,34 +383,44 @@ static int eqos_recv(struct eth_device *dev) d->des3 = DES3_OWN | DES3_BUF1V; eqos_flush(d, sizeof(*d)); writel((ulong)d, DMA_CH_RXDESC_TAIL); - eqos.rx_idx = (eqos.rx_idx + 1) % RX_DESCS; + eqos->rx_idx = (eqos->rx_idx + 1) % RX_DESCS; return len; } /* - * Register the MAC; the board has its clocks running, the pins muxed and - * the PHY powered, @intf says which PHY that is. + * Register the MAC at @base as @name; the board has its clocks running, + * the pins muxed and the PHY powered, @intf says which PHY that is, @cr + * is the MDC divider for the CSR clock (MAC_MDIO_ADDR CR). */ -int nvt_eqos_initialize(phy_interface_t intf) +int nvt_eqos_register(const char *name, ulong base, phy_interface_t intf, + u32 cr) { - struct eth_device *dev = &eqos.dev; + struct nvt_eqos *eqos; + struct eth_device *dev; struct mii_dev *mii; - eqos.intf = intf; - eqos.cr = mdio_cr[(readl(NVT_CG_SYSCLK) >> 8) & 3]; + if (eqos_count >= NVT_EQOS_MAX) + return -ENOSPC; + eqos = &eqos_devs[eqos_count++]; + dev = &eqos->dev; + eqos->base = base; + eqos->intf = intf; + eqos->cr = cr; mii = mdio_alloc(); if (!mii) return -ENOMEM; - strcpy(mii->name, "eqos"); + strlcpy(mii->name, name, sizeof(mii->name)); mii->read = eqos_mdio_read; mii->write = eqos_mdio_write; + mii->priv = eqos; if (mdio_register(mii)) return -EIO; - eqos.mii = mii; + eqos->mii = mii; - strcpy(dev->name, "eqos"); - dev->iobase = NVT_ETH_BASE; + strlcpy(dev->name, name, sizeof(dev->name)); + dev->iobase = base; + dev->priv = eqos; dev->init = eqos_start; dev->halt = eqos_halt; dev->send = eqos_send; @@ -381,3 +428,23 @@ int nvt_eqos_initialize(phy_interface_t intf) dev->write_hwaddr = eqos_write_hwaddr; return eth_register(dev); } + +#ifndef CONFIG_NVT_NA51068 +#ifndef NVT_ETH_MDIO_CR +/* What the CSR clock (CG+0x10 [9:8]) is, as an MDC divider (CR) */ +#define NVT_CG_SYSCLK (NVT_CG_BASE + 0x10) +static const u8 mdio_cr[4] = { + 3, /* 48 MHz: CR 35-60 MHz, /26 */ + 0, /* 60 MHz: CR 60-100 MHz, /42 */ + 0, /* 80 MHz */ + 1, /* 120 MHz: CR 100-150 MHz, /62 */ +}; +#define NVT_ETH_MDIO_CR mdio_cr[(readl(NVT_CG_SYSCLK) >> 8) & 3] +#endif + +/* The one MAC of the other dies */ +int nvt_eqos_initialize(phy_interface_t intf) +{ + return nvt_eqos_register("eqos", NVT_ETH_BASE, intf, NVT_ETH_MDIO_CR); +} +#endif diff --git a/env/Kconfig b/env/Kconfig index 461db4049991..c65bfcc24826 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -330,7 +330,7 @@ config ENV_IS_IN_REMOTE config ENV_IS_IN_SPI_FLASH bool "Environment is in SPI flash" - depends on !CHAIN_OF_TRUST && (SPI || NVT_SFLASH) + depends on !CHAIN_OF_TRUST && (SPI || NVT_SFLASH || NVT_SPI020) default y if ARMADA_XP default y if INTEL_BAYTRAIL default y if INTEL_BRASWELL diff --git a/include/configs/novatek.h b/include/configs/novatek.h index 7df436cc8f0b..2d880167fc8e 100644 --- a/include/configs/novatek.h +++ b/include/configs/novatek.h @@ -1,20 +1,56 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Novatek NA51089: memory map, console and timer. The environment and the - * rest of the OpenIPC configuration come from openipc-common.h. + * Novatek NA51089, NA51055 / NA51084, NS02501, NA51068, NA51103, NA51090: memory + * map, console and timer. The environment and the rest of the OpenIPC + * configuration come from openipc-common.h. */ #ifndef __NOVATEK_H #define __NOVATEK_H -#include +#include #define CONFIG_SYS_SDRAM_BASE NVT_DDR_BASE -/* The DDR in the package */ -#ifdef CONFIG_TARGET_NT98566 -#define PHYS_SDRAM_1_SIZE 0x08000000 -#else -#define PHYS_SDRAM_1_SIZE 0x04000000 +/* The DDR in the package, or on the board */ +#define PHYS_SDRAM_1_SIZE CONFIG_NVT_DDR_SIZE + +/* Linux's share of the DDR by default (mem=) */ +#define OPENIPC_OSMEM CONFIG_NVT_OSMEM + +#ifdef CONFIG_NVT_NA511XX +/* + * Staging buffer for kernels and images: past the loader's areas and + * BL31 (0x1F00000, secure), where the vendor U-Boot stages them + */ +#define OPENIPC_BASEADDR 0x02000000 +#ifdef CONFIG_NVT_NA51090 +/* + * The board's loader, tree and BL31 stay in the first 768 KiB of the NAND + * (loader 0, tree 0x40000, BL31 0x80000); ${ubfile} is U-Boot's slot + * alone, 0xC0000..0x1A0000. The environment is the board's uenv + * partition (0x1A0000), UBI follows (0x1E0000). + */ +#define OPENIPC_UBWRITE "nand erase 0xc0000 0xe0000; nand write ${baseaddr} 0xc0000 ${filesize}" +#define OPENIPC_NAND_MTDPARTS "1664k(boot),256k(env),-(ubi)" +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#endif +#ifdef CONFIG_NVT_NA51103 +/* + * The board's loader and device tree stay in the first 128 KiB of the + * NOR: ${ubfile} is U-Boot's slot alone, 0x20000..0x40000 + * (openipc/nvt-nvr-image.py) + */ +#define OPENIPC_UBWRITE "sf probe 0; sf erase 0x20000 0x20000; sf write ${baseaddr} 0x20000 ${filesize}" +#endif +#endif + +#ifdef CONFIG_NVT_NA51068 +/* + * The device tree and an initrd stay in the first 128 MiB: the SDK's + * kernel 4.9 hangs before its first message with them just below + * mem=192M, where bootm would put them + */ +#define CONFIG_SYS_BOOTMAPSZ 0x08000000 #endif /* The loader starts U-Boot at its link address */ @@ -24,16 +60,26 @@ #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_TEXT_BASE - 0x100000) #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -/* Console: UART0, a 16550 with 32-bit registers, at 24 MHz */ +/* Console: UART0, a 16550 with 32-bit registers */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_MEM32 +#ifdef CONFIG_NVT_NA511XX +#define CONFIG_SYS_NS16550_CLK NVT_UART_HZ +#elif defined(CONFIG_NVT_NA51068) || defined(CONFIG_NVT_NS02501) +/* NA51068, and NS02501 (the SDK's tree and its U-Boot's soc.c): 48 MHz */ +#define CONFIG_SYS_NS16550_CLK 48000000 +#else #define CONFIG_SYS_NS16550_CLK 24000000 +#endif #define CONFIG_SYS_NS16550_COM1 NVT_UART0_BASE +#if !defined(CONFIG_ARM64) && !defined(CONFIG_NVT_NA51068) /* Timer 0 of the timer block, free running at 1 MHz */ #define CONFIG_SYS_TIMER_RATE NVT_TIMER_HZ #define CONFIG_SYS_TIMER_COUNTER NVT_TIMER0_COUNT +#endif +/* NA51068: the A9 global timer (arch/arm/mach-novatek/na51068.c) */ #include "openipc-common.h" diff --git a/include/configs/openipc-common.h b/include/configs/openipc-common.h index 159998815d65..f1f12c3f6d45 100644 --- a/include/configs/openipc-common.h +++ b/include/configs/openipc-common.h @@ -26,12 +26,17 @@ /* * Kernel memory (mem=): the rest of the DDR is the media pool, which * ft_board_setup() hands to the vendor modules (/hdal-memory/media). - * What OpenIPC's install guide sets on the vendor U-Boot. + * What OpenIPC's install guide sets on the vendor U-Boot, unless the + * target says otherwise (NVT_OSMEM). */ +#ifndef OPENIPC_OSMEM #define OPENIPC_OSMEM "32M" +#endif /* Clear of the kernel at 0x8000 as it unpacks, below U-Boot */ +#ifndef OPENIPC_BASEADDR #define OPENIPC_BASEADDR 0x01000000 +#endif /* NOR layout, shared with every OpenIPC NOR camera */ #define OPENIPC_KERNADDR 0x50000 @@ -90,6 +95,7 @@ "fwrecovery=if env exists bootfail; then run fwupd; sleep 5; reset; fi\0" \ "bootflash=run fwrecovery; setenv setargs setenv bootargs ${bootargs}; run setargs; run loadkernel; bootm ${baseaddr}; reset\0" +#ifndef CONFIG_ENV_IS_IN_NAND /* * The flash's MTD name in the vendor kernels: the nor node's * nvt-devname in the loader's device tree @@ -102,6 +108,10 @@ #define OPENIPC_FWUPD "fwupd=run ur; run uk\0" #define OPENIPC_LOADKERNEL "sf probe 0; sf read ${baseaddr} ${kernaddr} ${kernsize}" +/* The boot image goes at 0, unless the SoC's config says otherwise */ +#ifndef OPENIPC_UBWRITE +#define OPENIPC_UBWRITE "sf probe 0; sf erase 0x0 ${kernaddr}; sf write ${baseaddr} 0x0 ${filesize}" +#endif #define OPENIPC_ENV_MEDIUM \ "ubfile=u-boot-" CONFIG_PRODUCT_SOC "-nor.bin\0" \ "urfile=rootfs.squashfs." CONFIG_PRODUCT_SOC "\0" \ @@ -111,7 +121,7 @@ "rootsize=" __stringify(OPENIPC_ROOTSIZE) "\0" \ "mtdslite=setenv kernsize 0x200000; setenv rootaddr 0x250000; setenv rootsize 0x500000\0" \ "mtdsultimate=setenv kernsize 0x300000; setenv rootaddr 0x350000; setenv rootsize 0xa00000\0" \ - "ubwrite=sf probe 0; sf erase 0x0 ${kernaddr}; sf write ${baseaddr} 0x0 ${filesize}\0" \ + "ubwrite=" OPENIPC_UBWRITE "\0" \ "ukwrite=sf probe 0; sf erase ${kernaddr} ${kernsize}; sf write ${baseaddr} ${kernaddr} ${filesize}\0" \ "urwrite=sf probe 0; if itest ${filesize} -gt 500000; then run mtdsultimate; fi; sf erase ${rootaddr} ${rootsize}; sf write ${baseaddr} ${rootaddr} ${filesize}\0" \ "fwwrite=sf probe 0; sf erase ${kernaddr} ${filesize}; sf write ${baseaddr} ${kernaddr} ${filesize}\0" \ @@ -121,6 +131,35 @@ "mtdparts=" SFC ":" OPENIPC_MTDPARTS "\0" \ "bootargs=" CONFIG_BOOTARGS +#else /* CONFIG_ENV_IS_IN_NAND */ + +/* + * SPI NAND, as on openipc-hisilicon: one UBI device after the boot area + * and the environment (CONFIG_ENV_OFFSET), holding the UBIFS rootfs with + * the kernel inside it (/boot/fitImage or /boot/uImage) and rootfs_data + * on the rest. The boot area is the SoC's (OPENIPC_NAND_MTDPARTS), its + * MTD name the nand node's nvt-devname. + */ +#define SFC "spi_nand.0" + +#define CONFIG_BOOTARGS "mem=\\${osmem} console=ttyS0,115200 panic=20 init=/init root=ubi0:rootfs rootfstype=ubifs ubi.mtd=2,2048 mtdparts=\\${mtdparts} \\${extras}" + +#define OPENIPC_FWUPD "fwupd=run ur\0" + +#define OPENIPC_LOADKERNEL "ubi part ubi; ubifsmount ubi0:rootfs; ubifsload ${baseaddr} /boot/fitImage || ubifsload ${baseaddr} /boot/uImage" +#define OPENIPC_ENV_MEDIUM \ + "ubfile=u-boot-" CONFIG_PRODUCT_SOC "-nand.bin\0" \ + "urfile=rootfs.ubifs." CONFIG_PRODUCT_SOC "\0" \ + "ubwrite=" OPENIPC_UBWRITE "\0" \ + "urwrite=ubi part ubi; ubi check rootfs && ubi remove rootfs; if ubi create rootfs ${filesize} d; then ubi check rootfs; else ubi remove rootfs_data; ubi create rootfs ${filesize} d; fi; ubi check rootfs_data || ubi create rootfs_data 0 d; ubi write ${baseaddr} rootfs ${filesize}\0" \ + "loadkernel=" OPENIPC_LOADKERNEL "\0" \ + "mtdids=nand0=" SFC "\0" \ + "mtds=" OPENIPC_NAND_MTDPARTS "\0" \ + "mtdparts=" SFC ":" OPENIPC_NAND_MTDPARTS "\0" \ + "bootargs=" CONFIG_BOOTARGS + +#endif /* CONFIG_ENV_IS_IN_NAND */ + #define CONFIG_BOOTCOMMAND "run bootflash" #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/openipc/na51055.dtsi b/openipc/na51055.dtsi new file mode 100644 index 000000000000..340e1c6f1a3f --- /dev/null +++ b/openipc/na51055.dtsi @@ -0,0 +1,1027 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Novatek NA51055 (NT98520/522/523/525): the device tree of the NT9852x + * SDK's NT98525 NOR board (cfg_IPCAM1_NOR_EVB, flattened), with the + * OpenIPC boot chain in the nor node: the loader at 0, this tree at + * 0x10000, U-Boot at 0x20000. U-Boot runs at 0x03900000, below 64 MiB as + * on NA51089, and the loader's scratch (linuxtmp) ends there. + * + * The loader reads /nvt_memory_cfg (where U-Boot runs, where this tree + * and SHMINFO go) and /nor/partition_uboot. U-Boot hands the tree on to + * the kernel, with /memory and /hdal-memory/media split at ${osmem}; a + * second DDR die's range in media (0x40000000) stays the pool's + * (board/novatek/na51089/na51089.c). + */ + +/ { + model = "Novatek NA51055"; + compatible = "novatek,na51055", "nvt,ca9"; + interrupt-parent = <&gic>; + #address-cells = <0x01>; + #size-cells = <0x01>; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x00>; + next-level-cache = <&L2>; + clock-frequency = <0x39387000>; + apb-frequency = <0x7270e00>; + phandle = <0x04>; + }; + }; + + cg@f0020000 { + compatible = "nvt,core_clk"; + reg = <0xf0020000 0x1000>; + }; + + periph_clk: periph_clk { + compatible = "nvt,periph_clk"; + #clock-cells = <0x00>; + clock-output-names = "periph_clk"; + phandle = <0x03>; + }; + + global_timer@ffd00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xffd00200 0x20>; + interrupts = <0x01 0x0b 0xf01>; + clocks = <&periph_clk>; + }; + + private_timer@ffd00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xffd00600 0x20>; + interrupts = <0x01 0x0d 0xf01>; + clocks = <&periph_clk>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0x00 0x50 0x04>; + interrupt-affinity = <&cpu0>; + }; + + L2: cache-controller@ffe00000 { + compatible = "arm,pl310-cache"; + reg = <0xffe00000 0x1000>; + interrupts = <0x00 0x60 0x04>; + cache-unified; + arm,shared-override; + cache-level = <0x02>; + arm,data-latency = <0x02 0x02 0x02>; + arm,tag-latency = <0x02 0x02 0x02>; + phandle = <0x02>; + }; + + gic: interrupt-controller@0xffd00000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <0x03>; + interrupt-controller; + reg = <0xffd01000 0x1000>, <0xffd00100 0x1000>; + phandle = <0x01>; + }; + + chosen { + bootargs = " "; + }; + + aliases { + mmc0 = "/mmc@f0420000"; + mmc1 = "/mmc@f0500000"; + }; + + uart@f0290000 { + compatible = "ns16550a"; + reg = <0xf0290000 0x1000>; + interrupts = <0x00 0x2b 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x16e3600>; + fifo-size = <0x10>; + uart_id = <0x00>; + }; + + uart@f0300000 { + compatible = "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <0x00 0x2c 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + hw_flowctrl = <0x00>; + rx_trig_level = <0x03>; + uart_id = <0x01>; + }; + + uart@f0310000 { + compatible = "ns16550a"; + reg = <0xf0310000 0x1000>; + interrupts = <0x00 0x2d 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + hw_flowctrl = <0x00>; + rx_trig_level = <0x03>; + uart_id = <0x02>; + }; + + kdrv_rpc: cc@f0090000 { + compatible = "kdrv_rpc"; + reg = <0xf0090000 0x300>; + interrupts = <0x00 0x3b 0x04>; + }; + + mmc0: mmc@f0420000 { + compatible = "nvt,nvt_mmc"; + reg = <0xf0420000 0x1000>; + interrupts = <0x00 0x1e 0x04>; + max-frequency = <0x2dc6c00>; + voltage-switch = <0x00>; + max-voltage = <0xce4>; + bus-width = <0x04>; + neg-sample-edge = <0x00>; + driving = <0x0a 0x0a 0x0a 0x19 0x19 0x19 0x19 0x19 0x19 0x19 0x19 0x19>; + cd_gpio = <0x31 0x00 0x00>; + }; + + mmc1: mmc@f0500000 { + compatible = "nvt,nvt_mmc2"; + reg = <0xf0500000 0x1000>; + interrupts = <0x00 0x1f 0x04>; + max-frequency = <0x2dc6c00>; + voltage-switch = <0x00>; + max-voltage = <0xce4>; + bus-width = <0x04>; + neg-sample-edge = <0x00>; + driving = <0x0a 0x06 0x06 0x0f 0x06 0x06 0x0f 0x06 0x06 0x0f 0x06 0x06>; + cd_gpio = <0x00 0x00 0x01>; + }; + + nand: nand@f0400000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "nvt,nvt_spinand"; + reg = <0xf0400000 0x1000>; + interrupts = <0x00 0x1d 0x04>; + clock-frequency = <0x4c4b400>; + nvt-devname = "spi_nand.0"; + }; + + nor: nor@f0400000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "nvt,nvt_spinor"; + reg = <0xf0400000 0x1000>; + interrupts = <0x00 0x1d 0x04>; + clock-frequency = <0x2dc6c00>; + nvt-devname = "spi_nor.0"; + trace-stdtable = <0x01>; + + + partition_loader { + label = "loader"; + reg = <0x00 0x00 0x00 0x10000>; + }; + + partition_fdt { + label = "fdt"; + reg = <0x00 0x10000 0x00 0x10000>; + }; + + partition_uboot { + label = "uboot"; + reg = <0x00 0x20000 0x00 0x20000>; + }; + + /* The loader looks a partition up here by its label */ + nvtpack { + ver = "NVTPACK_FW_INI_16072017"; + method = <0x01>; + + index { + + id0 { + partition_name = "loader"; + }; + + id1 { + partition_name = "fdt"; + }; + + id2 { + partition_name = "uboot"; + }; + }; + }; + }; + + gpio: gpio@f0070000 { + compatible = "nvt,nvt_gpio"; + reg = <0xf0070000 0x10000>; + interrupts = <0x00 0x18 0x04>; + #gpio-cells = <0x02>; + }; + + eth@f02b0000 { + compatible = "nvt,synopsys_eth"; + reg = <0xf02b0000 0x200 0xf02b0208 0x35f8>; + interrupts = <0x00 0x22 0x04>; + sp-clk = <0x00>; + ref-clk-out = <0x00>; + }; + + mdio0: mdio@f02b0200 { + compatible = "nvt,eth_mdio"; + reg = <0xf02b0200 0x08>; + }; + + phy@f02b3800 { + compatible = "nvt,eth_phy"; + reg = <0xf02b3800 0x400>; + }; + + wdt@f0050000 { + compatible = "nvt,nvt_wdt"; + reg = <0xf0050000 0x10000>; + interrupts = <0x00 0x39 0x04>; + }; + + pwm: pwm@f0210000 { + compatible = "nvt,nvt_pwm"; + reg = <0xf0210000 0x2000>; + interrupts = <0x00 0x1a 0x04>; + }; + + adc@f0260000 { + compatible = "nvt,nvt_adc"; + reg = <0xf0260000 0x1000>; + interrupts = <0x00 0x2f 0x04>; + #io-channel-cells = <0x01>; + }; + + rtc@f0060000 { + compatible = "nvt,nvt_rtc"; + reg = <0xf0060000 0x100>; + interrupts = <0x00 0x38 0x04>; + }; + + drtc@f00b0000 { + compatible = "nvt,nvt_drtc"; + reg = <0xf00b0000 0x100>; + }; + + crypto: crypto@f0620000 { + compatible = "nvt,nvt_crypto"; + reg = <0xf0620000 0x100>; + interrupts = <0x00 0x26 0x04>; + mclk = <0x01>; + }; + + hash: hash@f0700000 { + compatible = "nvt,nvt_hash"; + reg = <0xf0700000 0x100>; + interrupts = <0x00 0x1c 0x04>; + mclk = <0x01>; + }; + + rsa: rsa@f06a0000 { + compatible = "nvt,nvt_rsa"; + reg = <0xf06a0000 0x100>; + interrupts = <0x00 0x14 0x04>; + mclk = <0x01>; + }; + + top: top@f0010000 { + compatible = "nvt,nvt_top"; + reg = <0xf0010000 0x2000 0xf0030000 0x2000 0xf0070000 0x10000>; + + sdio { + pinmux = <0x01>; + }; + + sdio2 { + pinmux = <0x01>; + }; + + sdio3 { + pinmux = <0x00>; + }; + + nand { + pinmux = <0x05>; + }; + + sensor { + pinmux = <0x00>; + }; + + sensor2 { + pinmux = <0x00>; + }; + + mipi_lvds { + pinmux = <0x00>; + }; + + i2c { + pinmux = <0x00>; + }; + + sif { + pinmux = <0x08>; + }; + + uart { + pinmux = <0x01>; + }; + + spi { + pinmux = <0x00>; + }; + + sdp { + pinmux = <0x00>; + }; + + remote { + pinmux = <0x00>; + }; + + pwm { + pinmux = <0x00>; + }; + + pwm2 { + pinmux = <0x00>; + }; + + ccnt { + pinmux = <0x00>; + }; + + audio { + pinmux = <0x00>; + }; + + lcd { + pinmux = <0x10000000>; + }; + + tv { + pinmux = <0x00>; + }; + + eth { + pinmux = <0x12>; + }; + + misc { + pinmux = <0x00>; + }; + }; + + sie@f0c00000 { + compatible = "nvt,drv_sie"; + reg = <0xf0c00000 0x900 0xf0d20000 0x900 0xf0d30000 0x900 0xf0d40000 0x900 0xf0d80000 0x900>; + interrupts = <0x00 0x01 0x04 0x00 0x02 0x04 0x00 0x03 0x04 0x00 0x3b 0x04 0x00 0x3d 0x04>; + power_saving = <0x00>; + }; + + tge@f0cc0000 { + compatible = "nvt,kdrv_tge"; + reg = <0xf0cc0000 0x150>; + interrupts = <0x00 0x16 0x04>; + }; + + rhe@f0ce0000 { + compatible = "nvt,kdrv_rhe"; + reg = <0xf0ce0000 0x900>; + interrupts = <0x00 0x0d 0x04>; + }; + + ime@f0c40000 { + compatible = "nvt,kdrv_ime"; + reg = <0xf0c40000 0x1000>; + interrupts = <0x00 0x06 0x04>; + }; + + ife2@f0d00000 { + compatible = "nvt,kdrv_ife2"; + reg = <0xf0d00000 0x100>; + interrupts = <0x00 0x09 0x04>; + }; + + ise@f0c90000 { + compatible = "nvt,kdrv_ise"; + reg = <0xf0c90000 0x100>; + interrupts = <0x00 0x15 0x04 0x00 0x55 0x04>; + }; + + ipe@f0c30000 { + compatible = "nvt,kdrv_ipe"; + reg = <0xf0c30000 0x900>; + interrupts = <0x00 0x05 0x04>; + }; + + ife@f0c70000 { + compatible = "nvt,kdrv_ife"; + reg = <0xf0c70000 0x800>; + interrupts = <0x00 0x08 0x04>; + }; + + vpe@f0cd0000 { + compatible = "nvt,kdrv_vpe"; + reg = <0xf0cd0000 0x1040>; + interrupts = <0x00 0x3e 0x04>; + }; + + ai@f0c60000 { + compatible = "nvt,kdrv_ai"; + reg = <0xf0c60000 0x1cc 0xf0d50000 0x94 0xf0d60000 0x200 0xf0cb0000 0x200>; + interrupts = <0x00 0x0e 0x04 0x00 0x0d 0x04 0x00 0x31 0x04 0x00 0x0b 0x04>; + }; + + md@f0c10000 { + compatible = "nvt,kdrv_md"; + reg = <0xf0c10000 0x150>; + interrupts = <0x00 0x2e 0x04>; + }; + + dis@f0c50000 { + compatible = "nvt,kdrv_dis"; + reg = <0xf0c50000 0x114>; + interrupts = <0x00 0x0a 0x04>; + }; + + coe@f0a11000 { + compatible = "nvt,nvt_coe"; + reg = <0xf0a11000 0x2c0>; + }; + + dce@f0c20000 { + compatible = "nvt,kdrv_dce"; + reg = <0xf0c20000 0x650>; + interrupts = <0x00 0x07 0x04>; + }; + + ive@f0d70000 { + compatible = "nvt,kdrv_ive"; + reg = <0xf0d70000 0x6c>; + interrupts = <0x00 0x35 0x04>; + }; + + sde@f0d90000 { + compatible = "nvt,kdrv_sde"; + reg = <0xf0d90000 0x90>; + interrupts = <0x00 0x4a 0x04>; + }; + + ide@f0800000 { + compatible = "nvt,nvt_ide"; + reg = <0xf0800000 0x1000>; + interrupts = <0x00 0x30 0x04>; + }; + + dsi@f0840000 { + compatible = "nvt,nvt_dsi"; + reg = <0xf0840000 0x1000>; + interrupts = <0x00 0x32 0x04>; + }; + + csi@f0280000 { + compatible = "nvt,nvt_csi"; + reg = <0xf0280000 0x100 0xf0330000 0x100>; + interrupts = <0x00 0x36 0x04 0x00 0x37 0x04>; + }; + + lvds@f0270000 { + compatible = "nvt,nvt_lvds"; + reg = <0xf0270000 0x200 0xf0370000 0x200>; + interrupts = <0x00 0x36 0x04 0x00 0x37 0x04>; + }; + + senphy@f06b0000 { + compatible = "nvt,nvt_senphy"; + reg = <0xf06b0000 0x100>; + }; + + ssenif@f0xx0000 { + compatible = "nvt,nvt_ssenif"; + reg = <0xf02c0000 0x2000>; + interrupts = <0x00 0x3d 0x04>; + }; + + sif@f0240000 { + compatible = "nvt,nvt_sif"; + reg = <0xf0240000 0x200>; + interrupts = <0x00 0x28 0x04>; + clock-frequency = <0xf4240>; + }; + + graphic@f0c80000 { + compatible = "nvt,nvt_graphic"; + reg = <0xf0c80000 0x300 0xf0d10000 0x100>; + interrupts = <0x00 0x12 0x04 0x00 0x13 0x04>; + }; + + affine@f0ca0000 { + compatible = "nvt,nvt_affine"; + reg = <0xf0ca0000 0x100>; + interrupts = <0x00 0x34 0x04>; + }; + + h26x@f0a10000 { + compatible = "nvt,nvt_h26x"; + reg = <0xf0a10000 0xa00>; + interrupts = <0x00 0x10 0x04>; + power_saving = <0x00>; + }; + + clocksource@f0040000 { + compatible = "nvt,nvt_clk_src"; + reg = <0xf0040000 0x300>; + interrupts = <0x00 0x00 0x04>; + clock-frequency1 = <0x2dc6c0>; + clock-frequency2 = <0x2dc6c0>; + clksrc = <0x01>; + bits = <0x20>; + clock-names = "f0040000.timer"; + }; + + ptp: ptp-dte@f0040000 { + compatible = "nvt,ptp-dte"; + reg = <0xf0040000 0x300>; + clock-frequency = <0x2dc6c0>; + interrupts = <0x00 0x00 0x04>; + }; + + timer@f0040000 { + compatible = "nvt,nvt_timer"; + reg = <0xf0040000 0x300>; + interrupts = <0x00 0x00 0x04>; + }; + + eac@f0640000 { + compatible = "nvt,nvt_eac"; + reg = <0xf0640000 0x200>; + }; + + jpg@f0a00000 { + compatible = "nvt,nvt_jpg"; + reg = <0xf0a00000 0x100>; + interrupts = <0x00 0x11 0x04>; + }; + + nvt_usb2host@f0600000 { + compatible = "nvt,ehci-nvtivot"; + reg = <0xf0600000 0x10000>; + interrupts = <0x00 0x1b 0x04>; + }; + + nvt_usb2dev@f0600000 { + compatible = "nvt,fotg200_udc"; + reg = <0xf0600000 0x10000>; + interrupts = <0x00 0x1b 0x04>; + }; + + nvt_usb_chrg@f0600000 { + compatible = "nvt,nvt_usb_chrgdet"; + reg = <0xf0600000 0x10000>; + }; + + dai@f0630000 { + compatible = "nvt,nvt_dai"; + reg = <0xf0630000 0xbc>; + interrupts = <0x00 0x0f 0x04>; + }; + + rotate@f0cf0000 { + compatible = "nvt,nvt_rotation"; + reg = <0xf0cf0000 0x100>; + interrupts = <0x00 0x51 0x04>; + }; + + drvdump@0 { + compatible = "nvt,nvt_drvdump"; + }; + + dsp@f1430000 { + compatible = "nvt,nvt_dsp"; + reg = <0xf1430000 0x200 0xf2000000 0x1000000 0xf1440000 0x200 0xf3000000 0x1000000>; + interrupts = <0x00 0x4c 0x04 0x00 0x4d 0x04>; + }; + + spi0: spi@f0230000 { + compatible = "nvt,nvt_spi"; + reg = <0xf0230000 0x10000>; + interrupts = <0x00 0x23 0x04>; + dma-support = <0x00>; + nvt-devname = <0x00>; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + spi1: spi@f0320000 { + compatible = "nvt,nvt_spi"; + reg = <0xf0320000 0x10000>; + interrupts = <0x00 0x24 0x04>; + dma-support = <0x00>; + nvt-devname = <0x01>; + status = "okay"; + }; + + spi2: spi@f0340000 { + compatible = "nvt,nvt_spi"; + reg = <0xf0340000 0x10000>; + interrupts = <0x00 0x25 0x04>; + dma-support = <0x00>; + nvt-devname = <0x02>; + status = "okay"; + }; + + sdp@f0390000 { + compatible = "nvt,nvt_sdp"; + reg = <0xf0390000 0x28>; + interrupts = <0x00 0x0c 0x04>; + }; + + tse@f0650000 { + compatible = "nvt,nvt_tse"; + reg = <0xf0650000 0x90>; + interrupts = <0x00 0x17 0x04>; + }; + + remote@f0250000 { + compatible = "nvt,nvt_remote"; + reg = <0xf0250000 0x28>; + interrupts = <0x00 0x19 0x04>; + }; + + rng: rng@f0680000 { + compatible = "nvt,nvt_rng"; + reg = <0xf0680000 0x100>; + }; + + nvt_arb@f0000000 { + compatible = "nvt,nvt_arb"; + reg = <0xf0000000 0xa000 0xf0100000 0xa000 0xf0fe0000 0x300 0xf0fd0000 0x300>; + interrupts = <0x00 0x21 0x04 0x00 0x33 0x04>; + }; + + nvt_otp@f0660000 { + compatible = "nvt,nvt_otp"; + reg = <0xf0660000 0x70>; + }; + + pll_preset@0 { + + pll3 { + pll_config = <0x03 0x00 0x00>; + }; + + pll4 { + pll_config = <0x04 0x00 0x00>; + }; + + pll5 { + pll_config = <0x05 0x00 0x01>; + }; + + pll6 { + pll_config = <0x06 0x00 0x00>; + }; + + pll7 { + pll_config = <0x07 0x00 0x00>; + }; + + pll8 { + pll_config = <0x08 0x00 0x00>; + }; + + pll9 { + pll_config = <0x09 0x00 0x00>; + }; + + pll10 { + pll_config = <0x0a 0x00 0x01>; + }; + + pll11 { + pll_config = <0x0b 0x00 0x00>; + }; + + pll12 { + pll_config = <0x0c 0x00 0x01>; + }; + + pll13 { + pll_config = <0x0d 0x10b07600 0x01>; + }; + + pll14 { + pll_config = <0x0e 0x00 0x00>; + }; + + pll15 { + pll_config = <0x0f 0x5b8d800 0x01>; + }; + + pll16 { + pll_config = <0x10 0x00 0x00>; + }; + + pll17 { + pll_config = <0x11 0x00 0x00>; + }; + + pll18 { + pll_config = <0x12 0x00 0x00>; + }; + + pllf320 { + pll_config = <0x18 0x1312d000 0x01>; + }; + }; + + i2c0: i2c@f0220000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf0220000 0x100>; + interrupts = <0x00 0x29 0x04>; + clock-frequency = <0x61a80>; + id = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + i2c1: i2c2@f0350000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf0350000 0x100>; + interrupts = <0x00 0x2a 0x04>; + clock-frequency = <0x61a80>; + id = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + i2c2: i2c3@f03a0000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf03a0000 0x100>; + interrupts = <0x00 0x3c 0x04>; + clock-frequency = <0x61a80>; + id = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + audio@1 { + type = "none"; + i2s_ctrl = <0x00>; + sif_channel = <0x00>; + gpio_cold_reset = <0x00>; + gpio_data = <0x00>; + gpio_clk = <0x00>; + gpio_cs = <0x00>; + adc_zero = <0x00>; + }; + + audio@2 { + type = "embedded"; + i2s_ctrl = <0x04>; + sif_channel = <0x00>; + gpio_cold_reset = <0x00>; + gpio_data = <0x00>; + gpio_clk = <0x00>; + gpio_cs = <0x00>; + adc_zero = <0x00>; + }; + + display { + type = "lcd"; + lcd_ctrl = <0x00>; + sif_channel = <0x02>; + gpio_cs = <0x76>; + gpio_clk = <0x77>; + gpio_data = <0x78>; + }; + + nvtmpp { + compatible = "nvt,nvtmpp"; + }; + + isf_stream { + compatible = "nvt,isf_stream"; + }; + + isf_flow { + compatible = "nvt,isf_flow"; + }; + + isf_vdocap { + compatible = "nvt,isf_vdocap"; + }; + + isf_vdoprc { + compatible = "nvt,isf_vdoprc"; + }; + + isf_dummy { + compatible = "nvt,isf_dummy"; + }; + + isf_vdoenc { + compatible = "nvt,isf_vdoenc"; + }; + + isf_vdodec { + compatible = "nvt,isf_vdodec"; + }; + + isf_vdoout { + compatible = "nvt,isf_vdoout"; + }; + + dispobj { + compatible = "nvt,nvt_dispobj"; + }; + + dispdev { + compatible = "nvt,nvt_dispdev"; + }; + + audio { + compatible = "nvt,nvt_audio"; + }; + + msdcnvt { + compatible = "nvt,msdcnvt"; + }; + + msdcnvt_adj { + compatible = "nvt,msdcnvt_adj"; + }; + + msdcnvt_custom_si { + compatible = "nvt,msdcnvt_custom_si"; + }; + + wavstudio { + compatible = "nvt,wavstudio"; + }; + + isf_audenc { + compatible = "nvt,isf_audenc"; + }; + + isf_auddec { + compatible = "nvt,isf_auddec"; + }; + + isf_audcap { + compatible = "nvt,isf_audcap"; + }; + + isf_audout { + compatible = "nvt,isf_audout"; + }; + + nvt_ipc { + compatible = "nvt,nvt_ipc"; + }; + + nvt_disflow { + compatible = "nvt,nvt_disflow"; + }; + + nvt_memory_cfg { + #address-cells = <0x01>; + #size-cells = <0x01>; + + dram { + reg = <0x00 0x20000000>; + }; + + core2entry1 { + reg = <0x00 0x100000>; + }; + + fdt { + reg = <0x100000 0x100000>; + }; + + shmem { + reg = <0x200000 0x100000>; + }; + + loader { + reg = <0x1000000 0x100000>; + }; + + linuxtmp { + reg = <0x1100000 0x2800000>; + }; + + uboot { + reg = <0x3900000 0x6c0000>; + }; + + core2entry2 { + reg = <0x1ffc0000 0x40000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00 0x12800000>; + }; + + reserved-memory { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + cma0: cma0@0x05000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x5000000 0x3000000>; + alignment = <0x400000>; + status = "okay"; + phandle = <0x05>; + }; + }; + + nvt_cma { + compatible = "nvt,nvt_cma"; + memory-region = <&cma0>; + id = <0x00>; + }; + + hdal-memory { + #address-cells = <0x01>; + #size-cells = <0x01>; + + media { + reg = <0x12800000 0xd800000 0x40000000 0x20000000>; + }; + }; + + hdal-maxpath-cfg { + vdocap_active_list = <0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00>; + vdoprc_maxdevice = <0x02>; + vdoenc_maxpath = <0x04>; + vdodec_maxpath = <0x02>; + vdoout_maxdevice = <0x01>; + adocap_maxdevice = <0x01>; + adoout_maxdevice = <0x01>; + adoenc_maxpath = <0x01>; + adodec_maxpath = <0x01>; + gfx_maxjob = <0x02>; + stamp_maximg = <0x10>; + vdoprc_maxstamp = <0x04 0x10>; + vdoprc_maxmask = <0x08 0x40>; + vdoenc_maxstamp = <0x20 0x10>; + vdoenc_maxmask = <0x00 0x40>; + vdoout_maxstamp = <0x00 0x10>; + vdoout_maxmask = <0x00 0x40>; + }; + + nvt_info { + BIN_NAME = "FW98525A"; + BIN_NAME_T = "FW98525T"; + RTOS_APP_MAIN = "test"; + EMBMEM_BLK_SIZE = "0x10000"; + EMBMEM = "EMBMEM_SPI_NOR"; + NVT_CFG_APP_EXTERNAL = "dhd_priv iperf-3"; + NVT_CFG_APP = "hfs lviewd nvtrtspd nvtipcd nvteventd uctrl fslinux ugxstrg nvtsystem camctrlcgi nvtweb nvtrecordManagerd msdcnvt arm_neon_perf mem ucmd isp_demon mem_hotplug memcpy drystone-2.0"; + NVT_ROOTFS_ETC = ""; + NVT_BINARY_FILE_STRIP = "no"; + NVT_CFG_KERNEL_CFG = ""; + NVT_LINUX_SMP = "NVT_LINUX_SMP_OFF"; + NVT_DEFAULT_NETWORK_BOOT_PROTOCOL = "NVT_DEFAULT_NETWORK_BOOT_PROTOCOL_STATIC_IP"; + NVT_ROOTFS_TYPE = "NVT_ROOTFS_TYPE_SQUASH"; + NVT_ETHERNET = "NVT_ETHERNET_EQOS"; + NVT_SDIO_WIFI = "NVT_SDIO_WIFI_NONE"; + NVT_USB_WIFI = "NVT_USB_WIFI_NONE"; + NVT_USB_4G = "NVT_USB_4G_NONE"; + WIFI_RTK_MDL = "WIFI_RTK_MDL_8189"; + WIFI_BRCM_MDL = "WIFI_BRCM_MDL_43438a1_ampk6212axtal26"; + WIFI_NVT_MDL = "WIFI_NVT_MDL_18211"; + NVT_CURL_SSL = "NVT_CURL_SSL_OPENSSL"; + NVT_UBOOT_ENV_IN_STORG_SUPPORT = "NVT_UBOOT_ENV_IN_STORG_SUPPORT_OFF"; + }; +}; diff --git a/openipc/na51068.dtsi b/openipc/na51068.dtsi new file mode 100644 index 000000000000..c43b9c76d934 --- /dev/null +++ b/openipc/na51068.dtsi @@ -0,0 +1,925 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * The device tree of the NT9832x SDK's NT98323 NOR EVB + * (cfg_98323_DDR4_4GX1_NOR_EVB: one 4 Gb DDR4 die, 512 MiB), with the + * OpenIPC boot chain in the nor node: the loader at 0, this tree at + * 0x10000, U-Boot at 0x20000. + * + * The loader reads /nvt_memory_cfg (where U-Boot runs, where this tree + * and SHMINFO go) and /nor/partition_uboot. U-Boot hands the tree on to + * the kernel, with /memory and /hdal-memory/media split at ${osmem} + * (board/novatek/na51068/na51068.c), and takes the Ethernet wiring from + * /top@fe030000/eth. + */ + +/ { + model = "Novatek NA51068"; + compatible = "novatek,na51068", "nvt,ca9"; + interrupt-parent = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x01>; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x00>; + next-level-cache = <0x02>; + clock-frequency = <0x53724e00>; + phandle = <0x04>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x01>; + cpu-release-addr = <0xfe0b9000>; + next-level-cache = <0x02>; + clock-frequency = <0x53724e00>; + phandle = <0x05>; + }; + }; + + cg@fe000000 { + compatible = "nvt,core_clk"; + reg = <0xfe000000 0x1000>; + }; + + periph_clk { + compatible = "nvt,periph_clk"; + #clock-cells = <0x00>; + clock-output-names = "periph_clk"; + phandle = <0x03>; + }; + + global_timer@F9C00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf9c00200 0x20>; + interrupts = <0x01 0x0b 0xf01>; + clocks = <0x03>; + }; + + private_timer@f9c00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf9c00600 0x20>; + interrupts = <0x01 0x0d 0xf01>; + clocks = <0x03>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0x00 0x70 0x04 0x00 0x71 0x04>; + interrupt-affinity = <0x04 0x05>; + }; + + cache-controller@F9C20000 { + compatible = "arm,pl310-cache"; + reg = <0xf9c20000 0x1000>; + interrupts = <0x00 0x61 0x04>; + cache-unified; + arm,shared-override; + cache-level = <0x02>; + arm,data-latency = <0x02 0x02 0x02>; + arm,tag-latency = <0x02 0x02 0x02>; + phandle = <0x02>; + }; + + interrupt-controller@0xF9C00000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <0x03>; + #address-cells = <0x01>; + interrupt-controller; + reg = <0xf9c01000 0x1000 0xf9c00100 0x100>; + phandle = <0x01>; + }; + + snoop-control-unit@0xf9c00000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xf9c00000 0x100>; + }; + + chosen { + bootargs = " "; + }; + + aliases { + mmc0 = "/mmc@fa600000"; + }; + + timer@fe8c0000 { + compatible = "faraday,fttmr010"; + reg = <0xfe8c0000 0x1000>; + interrupts = <0x00 0x23 0x01>; + clock-frequency = <0xb71b00>; + ext_clk = <0x01>; + }; + + uart@fe200000 { + compatible = "ns16550a"; + reg = <0xfe200000 0x1000>; + interrupts = <0x00 0x1d 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + rx_trig_level = <0x00>; + hw_flowctrl = <0x00>; + }; + + uart@fe220000 { + compatible = "ns16550a"; + reg = <0xfe220000 0x1000>; + interrupts = <0x00 0x1e 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + rx_trig_level = <0x00>; + }; + + uart@fe240000 { + compatible = "ns16550a"; + reg = <0xfe240000 0x1000>; + interrupts = <0x00 0x38 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + rx_trig_level = <0x00>; + }; + + uart@fe260000 { + compatible = "ns16550a"; + reg = <0xfe260000 0x1000>; + interrupts = <0x00 0x43 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + rx_trig_level = <0x00>; + }; + + sata@f9e00000 { + compatible = "novatech,nvt_sata100"; + reg = <0xf9e00000 0x1000 0xfdc00000 0x1000>; + interrupts = <0x00 0x0f 0x04>; + device-id = <0x00>; + }; + + sata@f9f00000 { + compatible = "novatech,nvt_sata100"; + reg = <0xf9f00000 0x1000 0xfdd00000 0x1000>; + interrupts = <0x00 0x10 0x04>; + device-id = <0x01>; + }; + + gpio@fe400000 { + compatible = "faraday,ftgpio010"; + reg = <0xfe400000 0x1000>; + interrupts = <0x00 0x1f 0x04>; + pin_base = <0x00>; + status = "okay"; + gpio-controller; + #gpio-cells = <0x02>; + }; + + gpio@fe420000 { + compatible = "faraday,ftgpio010"; + reg = <0xfe420000 0x1000>; + interrupts = <0x00 0x36 0x04>; + pin_base = <0x20>; + status = "okay"; + gpio-controller; + #gpio-cells = <0x02>; + }; + + gpio@fe440000 { + compatible = "faraday,ftgpio010"; + reg = <0xfe440000 0x1000>; + interrupts = <0x00 0x37 0x04>; + pin_base = <0x40>; + status = "okay"; + gpio-controller; + #gpio-cells = <0x02>; + }; + + gpio@fe640000 { + compatible = "faraday,ftgpio010"; + reg = <0xfe640000 0x1000>; + interrupts = <0x00 0x57 0x04>; + pin_base = <0x60>; + status = "okay"; + gpio-controller; + #gpio-cells = <0x02>; + }; + + irdet@fe540000 { + compatible = "nvt,nvt_irdet"; + reg = <0xfe540000 0x1000>; + interrupts = <0x00 0x41 0x04>; + }; + + pwm@fe6c0000 { + compatible = "nvt,nvt_pwm"; + reg = <0xfe6c0000 0x1000>; + interrupts = <0x00 0x2b 0x04>; + }; + + pwr@0x0 { + compatible = "nvt,nvt_pwr"; + }; + + pwr@0x1 { + compatible = "nvt,nvt_pwr"; + }; + + dma030@fca00000 { + compatible = "nvt,ftdmac030"; + reg = <0xfca00000 0x1000>; + interrupts = <0x00 0x0e 0x04>; + device-id = <0x00>; + nvt,dma-channel-mask = <0x1f>; + #dma-cells = <0x03>; + }; + + cc@f8900000 { + compatible = "kdrv_rpc"; + reg = <0xf8900000 0x300>; + interrupts = <0x00 0x00 0x04>; + }; + + mmc@fa600000 { + compatible = "nvt,nvt_ivot_sdc-sdhci"; + reg = <0xfa600000 0x1000>; + interrupts = <0x00 0x40 0x04>; + max-frequency = <0xb71b00>; + driving = <0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08>; + pulse-latch = <0x01>; + no-1-8-v; + }; + + nor@fa900000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "nvt,nvt_spi020_nor"; + reg = <0xfa900000 0x1000>; + interrupts = <0x00 0x20 0x04>; + clock-frequency = <0x2dc6c00>; + chip-select = <0x00>; + nvt-devname = "spi_nor.0"; + trace-stdtable = <0x01>; + + partition_loader { + label = "loader"; + reg = <0x00 0x00 0x00 0x10000>; + }; + + partition_fdt { + label = "fdt"; + reg = <0x00 0x10000 0x00 0x10000>; + }; + + partition_uboot { + label = "uboot"; + reg = <0x00 0x20000 0x00 0x20000>; + }; + + /* The loader looks a partition up here by its label */ + nvtpack { + ver = "NVTPACK_FW_INI_16072017"; + method = <0x01>; + + index { + + id0 { + partition_name = "loader"; + }; + + id1 { + partition_name = "fdt"; + }; + + id2 { + partition_name = "uboot"; + }; + }; + }; + }; + + top@fe030000 { + compatible = "nvt,nvt_top"; + reg = <0xfe030000 0x1000 0xfe040000 0x1000 0xfe400000 0x10000>; + + uart { + pinmux = <0x01>; + }; + + i2c { + pinmux = <0x10011>; + }; + + sdio { + pinmux = <0x20>; + }; + + spi { + pinmux = <0x02>; + }; + + extclk { + pinmux = <0x00>; + }; + + ssp { + pinmux = <0x11>; + }; + + lcd { + pinmux = <0x00>; + }; + + remote { + pinmux = <0x00>; + }; + + vcap { + pinmux = <0x00>; + }; + + eth { + pinmux = <0x1201>; + }; + + misc { + pinmux = <0x100066>; + }; + + pwm { + pinmux = <0x11>; + }; + + vcapint { + pinmux = <0x00>; + }; + }; + + u2host@f9100000 { + compatible = "nvt,ehci-nvtivot"; + reg = <0xf9100000 0x1000>; + phy_reg = <0xfcf00000>; + interrupts = <0x00 0x3d 0x04>; + channel = <0x00>; + }; + + gm2d@faa00000 { + compatible = "nvt,gm2d"; + reg = <0xfaa00000 0x2000>; + interrupts = <0x00 0x16 0x04>; + }; + + ssca@fd500000 { + compatible = "nvt,ssca"; + reg = <0xfd500000 0x100>; + interrupts = <0x00 0x1c 0x04>; + }; + + nvt_arb@fc400000 { + compatible = "nvt,nvt_arb"; + reg = <0xfc400000 0xa000 0xfd600000 0xa000>; + interrupts = <0x00 0x53 0x04>; + }; + + u2host@f9200000 { + compatible = "nvt,ehci-nvtivot"; + reg = <0xf9200000 0x1000>; + phy_reg = <0xfd000000>; + interrupts = <0x00 0x3e 0x04>; + channel = <0x01>; + }; + + ahbc@0xfe840000 { + compatible = "nvt,nvt_ahbc"; + reg = <0xfe840000 0x1000>; + }; + + dsp@f8800000 { + compatible = "nvt,nvt_dsp"; + reg = <0xf8800000 0x200 0xfb000000 0x800000>; + interrupts = <0x00 0x01 0x04>; + }; + + eth0@fcc00000 { + compatible = "nvt,synopsys_eth"; + reg = <0xfcc00000 0x10000>; + interrupts = <0x00 0x3b 0x04>; + sp-clk = <0x01>; + ref-clk-out = <0x00>; + phy-rst = <0x55>; + }; + + eth1@fcd00000 { + compatible = "nvt,synopsys_eth"; + reg = <0xfcd00000 0x10000>; + interrupts = <0x00 0x3c 0x04>; + sp-clk = <0x00>; + ref-clk-out = <0x00>; + phy-rst = <0x31>; + }; + + rtc@fe880000 { + compatible = "nvt,nvt_rtc"; + reg = <0xfe880000 0x100>; + interrupts = <0x00 0x5f 0x04>; + }; + + wdt@fe8a0000 { + compatible = "nvt,nvt_wdt"; + reg = <0xfe8a0000 0x10000>; + }; + + vcap316@f9d00000 { + compatible = "nvt,vcap316"; + reg = <0xf9d00000 0x18000>; + interrupts = <0x00 0x05 0x04>; + host-id = <0x00>; + }; + + dei321@fd800000 { + compatible = "nvt,dei321"; + reg = <0xfd800000 0x18000>; + interrupts = <0x00 0x12 0x04>; + host-id = <0x00>; + }; + + vpe321@fe2a0000 { + compatible = "nvt,vpe321"; + reg = <0xfe2a0000 0x18000>; + interrupts = <0x00 0x04 0x04>; + host-id = <0x00>; + }; + + osg@FD100000 { + compatible = "nvt,nvt_osg"; + reg = <0xfd100000 0x300>; + interrupts = <0x00 0x17 0x04>; + }; + + jpg@fac00000 { + compatible = "nvt,nvt_jpg"; + reg = <0xfac00000 0x100000>; + interrupts = <0x00 0x1a 0x04>; + }; + + ai@fecc0000 { + compatible = "nvt,kdrv_ai"; + reg = <0xfecc0000 0x1f8 0xfec20000 0xf4 0xfec40000 0x218>; + interrupts = <0x00 0x03 0x04 0x00 0x5e 0x04 0x00 0x02 0x04>; + }; + + crypto@fec60000 { + compatible = "nvt,nvt_crypto"; + reg = <0xfec60000 0x100>; + interrupts = <0x00 0x2c 0x04>; + mclk = <0x00>; + }; + + hash@fec80000 { + compatible = "nvt,nvt_hash"; + reg = <0xfec80000 0x100>; + interrupts = <0x00 0x2d 0x04>; + mclk = <0x00>; + }; + + rsa@feca0000 { + compatible = "nvt,nvt_rsa"; + reg = <0xfeca0000 0x100>; + interrupts = <0x00 0x2e 0x04>; + mclk = <0x00>; + }; + + drvdump@0 { + compatible = "nvt,nvt_drvdump"; + }; + + regulator@0x0 { + compatible = "nvt,nvt_regulator"; + }; + + thmal@fe2c0000 { + compatible = "nvt,thermal"; + reg = <0xfe2c0000 0x1000>; + default_trim = <0xe7>; + }; + + nvt_otp@fece0000 { + compatible = "nvt,nvt_otp"; + reg = <0xfece0000 0x70>; + }; + + busmon@fe000000 { + compatible = "nvt,nvt_busmon"; + reg = <0xfe000000 0x100>; + }; + + tse@fe6e0000 { + compatible = "nvt,nvt_tse"; + reg = <0xfe6e0000 0x300>; + interrupts = <0x00 0x0d 0x04>; + }; + + pll_preset@0 { + + pll0 { + pll_config = <0x00 0x1dcd6500 0x00>; + }; + + pll1 { + pll_config = <0x01 0x00 0x00>; + }; + + pll2 { + pll_config = <0x02 0x23c34600 0x00>; + }; + + pll3 { + pll_config = <0x03 0x00 0x00>; + }; + + pll4 { + pll_config = <0x04 0x00 0x00>; + }; + + pll5 { + pll_config = <0x05 0x00 0x00>; + }; + + pll6 { + pll_config = <0x06 0x00 0x00>; + }; + + pll7 { + pll_config = <0x07 0x00 0x00>; + }; + + pll8 { + pll_config = <0x08 0x1bb75640 0x00>; + }; + + pll9 { + pll_config = <0x09 0x00 0x00>; + }; + + pll10 { + pll_config = <0x0a 0x1017df80 0x00>; + }; + + pll11 { + pll_config = <0x0b 0x00 0x00>; + }; + + pll12 { + pll_config = <0x0c 0x00 0x00>; + }; + + pll13 { + pll_config = <0x0d 0x00 0x00>; + }; + + pll14 { + pll_config = <0x0e 0x00 0x00>; + }; + + pll15 { + pll_config = <0x0f 0x00 0x00>; + }; + + pll16 { + pll_config = <0x10 0x00 0x00>; + }; + + pll17 { + pll_config = <0x11 0x00 0x00>; + }; + + pll18 { + pll_config = <0x12 0x00 0x00>; + }; + }; + + i2c0@fe300000 { + compatible = "nvt,ftiic010"; + reg = <0xfe300000 0x100>; + interrupts = <0x00 0x15 0x04>; + clock-frequency = <0x186a0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + i2c1@fe320000 { + compatible = "nvt,ftiic010"; + reg = <0xfe320000 0x100>; + interrupts = <0x00 0x24 0x04>; + clock-frequency = <0x186a0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + i2c2@fe340000 { + compatible = "nvt,ftiic010"; + reg = <0xfe340000 0x100>; + interrupts = <0x00 0x3f 0x04>; + clock-frequency = <0x186a0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + i2c3@fe360000 { + compatible = "nvt,ftiic010"; + reg = <0xfe360000 0x100>; + interrupts = <0x00 0x42 0x04>; + clock-frequency = <0x186a0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + i2c4@fe380000 { + compatible = "nvt,ftiic010"; + reg = <0xfe380000 0x100>; + interrupts = <0x00 0x56 0x04>; + clock-frequency = <0x186a0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + i2c5@fe3a0000 { + compatible = "nvt,ftiic010"; + reg = <0xfe3a0000 0x100>; + interrupts = <0x00 0x13 0x04>; + clock-frequency = <0x186a0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + audio_in_part { + ssp = <0x00 0x01 0x10 0x10 0x1f40 0xbb8000 0x1f4000 0x00 0xffffffff 0x06 0x00 0x01 0x10 0x1f40 0xbb8000 0x2ee000 0x01 0xffffffff 0xffffffff 0x00 0x01 0x10 0x1f40 0xbb8000 0x7d000 0x01 0xffffffff 0xffffffff 0x00 0x01 0x10 0x1f40 0xbb8000 0x7d000 0x01 0xffffffff>; + }; + + audio_out_part { + ssp = <0x01 0x01 0xffffffff 0x01 0x06 0xffffffff 0x00 0x01 0xffffffff 0x00 0x01 0xffffffff>; + }; + + lcd200@fdb00000 { + compatible = "nvt,lcd200"; + reg = <0xfdb00000 0x10000>; + interrupts = <0x00 0x0c 0x04>; + device-id = <0x00>; + }; + + lcd300@fda00000 { + compatible = "nvt,lcd300"; + reg = <0xfda00000 0x10000>; + interrupts = <0x00 0x0a 0x04>; + device-id = <0x00>; + }; + + hdmi20@0 { + compatible = "nvt,hdmi_top"; + reg = <0xfd900000 0x1000>; + interrupts = <0x00 0x08 0x04>; + device-id = <0x00>; + }; + + tve100@0 { + compatible = "nvt,tve100"; + reg = <0xfad00000 0x1000>; + interrupts = <0x00 0x21 0x04>; + device-id = <0x00>; + }; + + nvtmpp { + compatible = "nvt,nvtmpp"; + }; + + isf_stream { + compatible = "nvt,isf_stream"; + }; + + isf_flow { + compatible = "nvt,isf_flow"; + }; + + isf_vdocap { + compatible = "nvt,isf_vdocap"; + }; + + isf_vdoprc { + compatible = "nvt,isf_vdoprc"; + }; + + isf_dummy { + compatible = "nvt,isf_dummy"; + }; + + isf_vdoenc { + compatible = "nvt,isf_vdoenc"; + }; + + isf_vdodec { + compatible = "nvt,isf_vdodec"; + }; + + isf_vdoout { + compatible = "nvt,isf_vdoout"; + }; + + dispobj { + compatible = "nvt,nvt_dispobj"; + }; + + dispdev { + compatible = "nvt,nvt_dispdev"; + }; + + audio { + compatible = "nvt,nvt_audio"; + }; + + msdcnvt { + compatible = "nvt,msdcnvt"; + }; + + msdcnvt_adj { + compatible = "nvt,msdcnvt_adj"; + }; + + msdcnvt_custom_si { + compatible = "nvt,msdcnvt_custom_si"; + }; + + wavstudio { + compatible = "nvt,wavstudio"; + }; + + isf_audenc { + compatible = "nvt,isf_audenc"; + }; + + isf_auddec { + compatible = "nvt,isf_auddec"; + }; + + isf_audcap { + compatible = "nvt,isf_audcap"; + }; + + isf_audout { + compatible = "nvt,isf_audout"; + }; + + nvt_ipc { + compatible = "nvt,nvt_ipc"; + }; + + h26xd@fcb00000 { + compatible = "nvt,h26xdec"; + reg = <0xfcb00000 0x4000>; + interrupts = <0x00 0x1b 0x04>; + device-id = <0x00>; + }; + + h26xenc@fc600000 { + compatible = "nvt,h26xenc"; + reg = <0xfc600000 0x10000>; + interrupts = <0x00 0x07 0x04>; + device-id = <0x00>; + }; + + /* + * What the loader reads: where this tree and SHMINFO go, where it + * runs (loader, up to 0xA00000) and where U-Boot is unpacked and + * stays (uboot, the SDK's, past Linux and its CMA pools). + * core2entry1/2 park the second core for Linux (U-Boot's HEADINFO + * asks for SMP). As the SDK's boards, but for the tree's size. + */ + nvt_memory_cfg { + #address-cells = <0x01>; + #size-cells = <0x01>; + + dram { + reg = <0x00 0x20000000>; + }; + + core2entry1 { + reg = <0x00 0x80000>; + }; + + fdt { + reg = <0x80000 0x80000>; + }; + + loader { + reg = <0x100000 0x900000>; + }; + + shmem { + reg = <0xa00000 0x100000>; + }; + + linuxtmp { + reg = <0xb00000 0x1d500000>; + }; + + uboot { + reg = <0x1e000000 0x1f80000>; + }; + + core2entry2 { + reg = <0x1ff80000 0x80000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00 0xc000000>; + }; + + reserved-memory { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + cma0@0x03000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x3000000 0x1800000>; + alignment = <0x400000>; + status = "okay"; + phandle = <0x06>; + }; + + dsp_cma@0x02000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x2000000 0x1000000>; + alignment = <0x400000>; + status = "okay"; + phandle = <0x07>; + }; + }; + + nvt_cma { + compatible = "nvt,nvt_cma"; + memory-region = <0x06>; + id = <0x00>; + }; + + nvt_dsp_cma { + compatible = "nvt,nvt_cma"; + memory-region = <0x07>; + id = <0x01>; + }; + + hdal-memory { + #address-cells = <0x01>; + #size-cells = <0x01>; + + media { + reg = <0xc000000 0x14000000>; + }; + }; + + ddr_chip_mapping { + mapping = <0x00 0x00 0x00 0x20000000>; + }; + + nvt_info { + BIN_NAME = "FW98323A"; + BIN_NAME_T = "FW98323T"; + RTOS_APP_MAIN = "test"; + EMBMEM_BLK_SIZE = "0x10000"; + EMBMEM = "EMBMEM_SPI_NOR"; + NVT_CFG_APP_EXTERNAL = "iperf-3 e2fsprogs"; + NVT_CFG_APP = "arm_neon_perf mem sw_dbg i2c_access memcpy drystone-2.0"; + NVT_ROOTFS_ETC = "COMMON"; + NVT_BINARY_FILE_STRIP = "yes"; + NVT_CFG_KERNEL_CFG = "na51068_evb_defconfig_nor_release"; + NVT_CFG_UBOOT_CFG = "nvt-na51068_evb_nor_defconfig"; + NVT_LINUX_SMP = "NVT_LINUX_SMP_ON"; + NVT_DEFAULT_NETWORK_BOOT_PROTOCOL = "NVT_DEFAULT_NETWORK_BOOT_PROTOCOL_STATIC_IP"; + NVT_ROOTFS_TYPE = "NVT_ROOTFS_TYPE_NOR_SQUASH"; + NVT_ETHERNET = "NVT_ETHERNET_EQOS"; + NVT_CURL_SSL = "NVT_CURL_SSL_OPENSSL"; + NVT_UBOOT_ENV_IN_STORG_SUPPORT = "NVT_UBOOT_ENV_IN_STORG_SUPPORT_OFF"; + }; +}; diff --git a/openipc/na51084.dtsi b/openipc/na51084.dtsi new file mode 100644 index 000000000000..a9a0beabb9ec --- /dev/null +++ b/openipc/na51084.dtsi @@ -0,0 +1,1187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Novatek NA51084 (NT98528/529): the device tree of the NT9852x SDK's + * NT98528 NOR board (cfg_528_IPCAM1_NOR_EVB, flattened), with the + * OpenIPC boot chain in the nor node: the loader at 0, this tree at + * 0x10000, U-Boot at 0x20000. U-Boot runs at 0x03900000, below 64 MiB as + * on NA51089, and the loader's scratch (linuxtmp) ends there. + * + * The loader reads /nvt_memory_cfg (where U-Boot runs, where this tree + * and SHMINFO go) and /nor/partition_uboot. U-Boot hands the tree on to + * the kernel, with /memory and /hdal-memory/media split at ${osmem}; a + * second DDR die's range in media (0x40000000) stays the pool's + * (board/novatek/na51089/na51089.c). + */ + +/ { + model = "Novatek NA51084"; + compatible = "novatek,na51084", "novatek,na51055", "nvt,ca9"; + interrupt-parent = <&gic>; + #address-cells = <0x01>; + #size-cells = <0x01>; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x00>; + next-level-cache = <&L2>; + clock-frequency = <0x39387000>; + apb-frequency = <0x7270e00>; + phandle = <0x04>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x01>; + cpu-release-addr = <0xf07f8000>; + next-level-cache = <&L2>; + clock-frequency = <0x39387000>; + apb-frequency = <0x7270e00>; + phandle = <0x05>; + }; + }; + + cg@f0020000 { + compatible = "nvt,core_clk"; + reg = <0xf0020000 0x1000>; + }; + + periph_clk: periph_clk { + compatible = "nvt,periph_clk"; + #clock-cells = <0x00>; + clock-output-names = "periph_clk"; + phandle = <0x03>; + }; + + global_timer@ffd00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xffd00200 0x20>; + interrupts = <0x01 0x0b 0xf01>; + clocks = <&periph_clk>; + }; + + private_timer@ffd00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xffd00600 0x20>; + interrupts = <0x01 0x0d 0xf01>; + clocks = <&periph_clk>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0x00 0x70 0x04>, <0x00 0x71 0x04>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + L2: cache-controller@ffe00000 { + compatible = "arm,pl310-cache"; + reg = <0xffe00000 0x1000>; + interrupts = <0x00 0x60 0x04>; + cache-unified; + arm,shared-override; + cache-level = <0x02>; + arm,data-latency = <0x02 0x02 0x02>; + arm,tag-latency = <0x02 0x02 0x02>; + phandle = <0x02>; + }; + + gic: interrupt-controller@0xffd00000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <0x03>; + interrupt-controller; + reg = <0xffd01000 0x1000>, <0xffd00100 0x1000>; + phandle = <0x01>; + }; + + scu: snoop-control-unit@0xffd00000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xffd00000 0x100>; + }; + + chosen { + bootargs = " "; + }; + + aliases { + mmc0 = "/mmc@f0420000"; + mmc1 = "/mmc@f0500000"; + }; + + uart@f0290000 { + compatible = "ns16550a"; + reg = <0xf0290000 0x1000>; + interrupts = <0x00 0x2b 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x16e3600>; + fifo-size = <0x40>; + uart_id = <0x00>; + }; + + uart@f0300000 { + compatible = "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <0x00 0x2c 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + hw_flowctrl = <0x00>; + rx_trig_level = <0x03>; + uart_id = <0x01>; + }; + + uart@f0310000 { + compatible = "ns16550a"; + reg = <0xf0310000 0x1000>; + interrupts = <0x00 0x2d 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + hw_flowctrl = <0x00>; + rx_trig_level = <0x03>; + uart_id = <0x02>; + }; + + uart@f0380000 { + compatible = "ns16550a"; + reg = <0xf0380000 0x1000>; + interrupts = <0x00 0x3f 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + hw_flowctrl = <0x00>; + rx_trig_level = <0x03>; + uart_id = <0x03>; + }; + + uart@f03e0000 { + compatible = "ns16550a"; + reg = <0xf03e0000 0x1000>; + interrupts = <0x00 0x40 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + hw_flowctrl = <0x00>; + rx_trig_level = <0x03>; + uart_id = <0x04>; + }; + + uart@f03f0000 { + compatible = "ns16550a"; + reg = <0xf03f0000 0x1000>; + interrupts = <0x00 0x41 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + hw_flowctrl = <0x00>; + rx_trig_level = <0x03>; + uart_id = <0x05>; + }; + + kdrv_rpc: cc@f0090000 { + compatible = "kdrv_rpc"; + reg = <0xf0090000 0x300>; + interrupts = <0x00 0x3b 0x04>; + }; + + mmc0: mmc@f0420000 { + compatible = "nvt,nvt_mmc"; + reg = <0xf0420000 0x1000>; + interrupts = <0x00 0x1e 0x04>; + max-frequency = <0x2dc6c00>; + voltage-switch = <0x00>; + max-voltage = <0xce4>; + bus-width = <0x04>; + neg-sample-edge = <0x00>; + driving = <0x0f 0x0f 0x0f 0x14 0x0f 0x0f 0x19 0x19 0x19 0x19 0x19 0x19>; + cd_gpio = <0x31 0x00 0x00>; + }; + + mmc1: mmc@f0500000 { + compatible = "nvt,nvt_mmc2"; + reg = <0xf0500000 0x1000>; + interrupts = <0x00 0x1f 0x04>; + max-frequency = <0x2dc6c00>; + voltage-switch = <0x00>; + max-voltage = <0xce4>; + bus-width = <0x04>; + neg-sample-edge = <0x00>; + driving = <0x0f 0x08 0x08 0x0f 0x08 0x08 0x0f 0x08 0x08 0x0f 0x08 0x08>; + cd_gpio = <0x00 0x00 0x01>; + }; + + nand: nand@f0400000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "nvt,nvt_spinand"; + reg = <0xf0400000 0x1000>; + interrupts = <0x00 0x1d 0x04>; + clock-frequency = <0x4c4b400>; + nvt-devname = "spi_nand.0"; + }; + + nor: nor@f0400000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "nvt,nvt_spinor"; + reg = <0xf0400000 0x1000>; + interrupts = <0x00 0x1d 0x04>; + clock-frequency = <0x2dc6c00>; + nvt-devname = "spi_nor.0"; + trace-stdtable = <0x01>; + + + partition_loader { + label = "loader"; + reg = <0x00 0x00 0x00 0x10000>; + }; + + partition_fdt { + label = "fdt"; + reg = <0x00 0x10000 0x00 0x10000>; + }; + + partition_uboot { + label = "uboot"; + reg = <0x00 0x20000 0x00 0x20000>; + }; + + /* The loader looks a partition up here by its label */ + nvtpack { + ver = "NVTPACK_FW_INI_16072017"; + method = <0x01>; + + index { + + id0 { + partition_name = "loader"; + }; + + id1 { + partition_name = "fdt"; + }; + + id2 { + partition_name = "uboot"; + }; + }; + }; + }; + + gpio: gpio@f0070000 { + compatible = "nvt,nvt_gpio"; + reg = <0xf0070000 0x10000>; + interrupts = <0x00 0x18 0x04>; + #gpio-cells = <0x02>; + }; + + eth@f02b0000 { + compatible = "nvt,synopsys_eth"; + reg = <0xf02b0000 0x200 0xf02b0208 0x35f8>; + interrupts = <0x00 0x22 0x04>; + sp-clk = <0x00>; + ref-clk-out = <0x00>; + }; + + mdio0: mdio@f02b0200 { + compatible = "nvt,eth_mdio"; + reg = <0xf02b0200 0x08>; + }; + + phy@f02b3800 { + compatible = "nvt,eth_phy"; + reg = <0xf02b3800 0x400>; + }; + + wdt@f0050000 { + compatible = "nvt,nvt_wdt"; + reg = <0xf0050000 0x10000>; + interrupts = <0x00 0x39 0x04>; + }; + + pwm: pwm@f0210000 { + compatible = "nvt,nvt_pwm"; + reg = <0xf0210000 0x2000>; + interrupts = <0x00 0x1a 0x04>; + }; + + adc@f0260000 { + compatible = "nvt,nvt_adc"; + reg = <0xf0260000 0x1000>; + interrupts = <0x00 0x2f 0x04>; + #io-channel-cells = <0x01>; + }; + + rtc@f0060000 { + compatible = "nvt,nvt_rtc"; + reg = <0xf0060000 0x100>; + interrupts = <0x00 0x38 0x04>; + }; + + drtc@f00b0000 { + compatible = "nvt,nvt_drtc"; + reg = <0xf00b0000 0x100>; + }; + + crypto: crypto@f0620000 { + compatible = "nvt,nvt_crypto"; + reg = <0xf0620000 0x100>; + interrupts = <0x00 0x26 0x04>; + mclk = <0x01>; + }; + + hash: hash@f0700000 { + compatible = "nvt,nvt_hash"; + reg = <0xf0700000 0x100>; + interrupts = <0x00 0x1c 0x04>; + mclk = <0x01>; + }; + + rsa: rsa@f06a0000 { + compatible = "nvt,nvt_rsa"; + reg = <0xf06a0000 0x100>; + interrupts = <0x00 0x14 0x04>; + mclk = <0x01>; + }; + + top: top@f0010000 { + compatible = "nvt,nvt_top"; + reg = <0xf0010000 0x2000 0xf0030000 0x2000 0xf0070000 0x10000>; + + sdio { + pinmux = <0x01>; + }; + + sdio2 { + pinmux = <0x01>; + }; + + sdio3 { + pinmux = <0x00>; + }; + + nand { + pinmux = <0x05>; + }; + + sensor { + pinmux = <0x00>; + }; + + sensor2 { + pinmux = <0x00>; + }; + + mipi_lvds { + pinmux = <0x00>; + }; + + i2c { + pinmux = <0x00>; + }; + + sif { + pinmux = <0x08>; + }; + + uart { + pinmux = <0x01>; + }; + + spi { + pinmux = <0x00>; + }; + + sdp { + pinmux = <0x00>; + }; + + remote { + pinmux = <0x00>; + }; + + pwm { + pinmux = <0x00>; + }; + + pwm2 { + pinmux = <0x00>; + }; + + ccnt { + pinmux = <0x00>; + }; + + audio { + pinmux = <0x00>; + }; + + lcd { + pinmux = <0x10000000>; + }; + + tv { + pinmux = <0x00>; + }; + + eth { + pinmux = <0x12>; + }; + + misc { + pinmux = <0x00>; + }; + }; + + sie@f0c00000 { + compatible = "nvt,drv_sie"; + reg = <0xf0c00000 0x900 0xf0d20000 0x900 0xf0d30000 0x900 0xf0d40000 0x900 0xf0d80000 0x900>; + interrupts = <0x00 0x01 0x04 0x00 0x02 0x04 0x00 0x03 0x04 0x00 0x3b 0x04 0x00 0x3d 0x04>; + power_saving = <0x00>; + }; + + tge@f0cc0000 { + compatible = "nvt,kdrv_tge"; + reg = <0xf0cc0000 0x150>; + interrupts = <0x00 0x16 0x04>; + }; + + rhe@f0ce0000 { + compatible = "nvt,kdrv_rhe"; + reg = <0xf0ce0000 0x900>; + interrupts = <0x00 0x0d 0x04>; + }; + + ime@f0c40000 { + compatible = "nvt,kdrv_ime"; + reg = <0xf0c40000 0x1000>; + interrupts = <0x00 0x06 0x04>; + }; + + ife2@f0d00000 { + compatible = "nvt,kdrv_ife2"; + reg = <0xf0d00000 0x100>; + interrupts = <0x00 0x09 0x04>; + }; + + ise@f0c90000 { + compatible = "nvt,kdrv_ise"; + reg = <0xf0c90000 0x100>; + interrupts = <0x00 0x15 0x04 0x00 0x55 0x04>; + }; + + ipe@f0c30000 { + compatible = "nvt,kdrv_ipe"; + reg = <0xf0c30000 0x900>; + interrupts = <0x00 0x05 0x04>; + }; + + ife@f0c70000 { + compatible = "nvt,kdrv_ife"; + reg = <0xf0c70000 0x800>; + interrupts = <0x00 0x08 0x04>; + }; + + vpe@f0cd0000 { + compatible = "nvt,kdrv_vpe"; + reg = <0xf0cd0000 0x1040>; + interrupts = <0x00 0x3e 0x04>; + }; + + ai@f0c60000 { + compatible = "nvt,kdrv_ai"; + reg = <0xf0c60000 0x1cc 0xf0d50000 0x94 0xf0d60000 0x200 0xf0cb0000 0x200>; + interrupts = <0x00 0x0e 0x04 0x00 0x0d 0x04 0x00 0x31 0x04 0x00 0x0b 0x04>; + }; + + md@f0c10000 { + compatible = "nvt,kdrv_md"; + reg = <0xf0c10000 0x150>; + interrupts = <0x00 0x2e 0x04>; + }; + + dis@f0c50000 { + compatible = "nvt,kdrv_dis"; + reg = <0xf0c50000 0x114>; + interrupts = <0x00 0x0a 0x04>; + }; + + coe@f0a11000 { + compatible = "nvt,nvt_coe"; + reg = <0xf0a11000 0x2c0>; + }; + + dce@f0c20000 { + compatible = "nvt,kdrv_dce"; + reg = <0xf0c20000 0x650>; + interrupts = <0x00 0x07 0x04>; + }; + + ive@f0d70000 { + compatible = "nvt,kdrv_ive"; + reg = <0xf0d70000 0x6c>; + interrupts = <0x00 0x35 0x04>; + }; + + sde@f0d90000 { + compatible = "nvt,kdrv_sde"; + reg = <0xf0d90000 0x90>; + interrupts = <0x00 0x4a 0x04>; + }; + + ide@f0800000 { + compatible = "nvt,nvt_ide"; + reg = <0xf0800000 0x1000>; + interrupts = <0x00 0x30 0x04>; + }; + + dsi@f0840000 { + compatible = "nvt,nvt_dsi"; + reg = <0xf0840000 0x1000>; + interrupts = <0x00 0x32 0x04>; + }; + + csi@f0280000 { + compatible = "nvt,nvt_csi"; + reg = <0xf0280000 0x100 0xf0330000 0x100>; + interrupts = <0x00 0x36 0x04 0x00 0x37 0x04>; + }; + + lvds@f0270000 { + compatible = "nvt,nvt_lvds"; + reg = <0xf0270000 0x200 0xf0370000 0x200>; + interrupts = <0x00 0x36 0x04 0x00 0x37 0x04>; + }; + + senphy@f06b0000 { + compatible = "nvt,nvt_senphy"; + reg = <0xf06b0000 0x100>; + }; + + ssenif@f0xx0000 { + compatible = "nvt,nvt_ssenif"; + reg = <0xf02c0000 0x2000>; + interrupts = <0x00 0x3d 0x04>; + }; + + sif@f0240000 { + compatible = "nvt,nvt_sif"; + reg = <0xf0240000 0x200>; + interrupts = <0x00 0x28 0x04>; + clock-frequency = <0xf4240>; + }; + + graphic@f0c80000 { + compatible = "nvt,nvt_graphic"; + reg = <0xf0c80000 0x300 0xf0d10000 0x100>; + interrupts = <0x00 0x12 0x04 0x00 0x13 0x04>; + }; + + affine@f0ca0000 { + compatible = "nvt,nvt_affine"; + reg = <0xf0ca0000 0x100>; + interrupts = <0x00 0x34 0x04>; + }; + + h26x@f0a10000 { + compatible = "nvt,nvt_h26x"; + reg = <0xf0a10000 0xa00>; + interrupts = <0x00 0x10 0x04>; + power_saving = <0x00>; + }; + + clocksource@f0040000 { + compatible = "nvt,nvt_clk_src"; + reg = <0xf0040000 0x300>; + interrupts = <0x00 0x00 0x04>; + clock-frequency1 = <0x2dc6c0>; + clock-frequency2 = <0x2dc6c0>; + clksrc = <0x01>; + bits = <0x20>; + clock-names = "f0040000.timer"; + }; + + ptp: ptp-dte@f0040000 { + compatible = "nvt,ptp-dte"; + reg = <0xf0040000 0x300>; + clock-frequency = <0x2dc6c0>; + interrupts = <0x00 0x00 0x04>; + }; + + timer@f0040000 { + compatible = "nvt,nvt_timer"; + reg = <0xf0040000 0x300>; + interrupts = <0x00 0x00 0x04>; + }; + + eac@f0640000 { + compatible = "nvt,nvt_eac"; + reg = <0xf0640000 0x200>; + }; + + jpg@f0a00000 { + compatible = "nvt,nvt_jpg"; + reg = <0xf0a00000 0x100>; + interrupts = <0x00 0x11 0x04>; + }; + + nvt_usb2host@f0600000 { + compatible = "nvt,ehci-nvtivot"; + reg = <0xf0600000 0x10000>; + interrupts = <0x00 0x1b 0x04>; + }; + + nvt_usb2dev@f0600000 { + compatible = "nvt,fotg200_udc"; + reg = <0xf0600000 0x10000>; + interrupts = <0x00 0x1b 0x04>; + }; + + nvt_usb_chrg@f0600000 { + compatible = "nvt,nvt_usb_chrgdet"; + reg = <0xf0600000 0x10000>; + }; + + dai@f0630000 { + compatible = "nvt,nvt_dai"; + reg = <0xf0630000 0xbc>; + interrupts = <0x00 0x0f 0x04>; + }; + + rotate@f0cf0000 { + compatible = "nvt,nvt_rotation"; + reg = <0xf0cf0000 0x100>; + interrupts = <0x00 0x51 0x04>; + }; + + drvdump@0 { + compatible = "nvt,nvt_drvdump"; + }; + + dsp@f1430000 { + compatible = "nvt,nvt_dsp"; + reg = <0xf1430000 0x200 0xf2000000 0x1000000 0xf1440000 0x200 0xf3000000 0x1000000>; + interrupts = <0x00 0x4c 0x04 0x00 0x4d 0x04>; + }; + + spi0: spi@f0230000 { + compatible = "nvt,nvt_spi"; + reg = <0xf0230000 0x10000>; + interrupts = <0x00 0x23 0x04>; + dma-support = <0x00>; + nvt-devname = <0x00>; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + spi1: spi@f0320000 { + compatible = "nvt,nvt_spi"; + reg = <0xf0320000 0x10000>; + interrupts = <0x00 0x24 0x04>; + dma-support = <0x00>; + nvt-devname = <0x01>; + status = "okay"; + }; + + spi2: spi@f0340000 { + compatible = "nvt,nvt_spi"; + reg = <0xf0340000 0x10000>; + interrupts = <0x00 0x25 0x04>; + dma-support = <0x00>; + nvt-devname = <0x02>; + status = "okay"; + }; + + spi3: spi@f0360000 { + compatible = "nvt,nvt_spi"; + reg = <0xf0360000 0x10000>; + interrupts = <0x00 0x42 0x04>; + dma-support = <0x00>; + nvt-devname = <0x03>; + }; + + spi4: spi@f03d0000 { + compatible = "nvt,nvt_spi"; + reg = <0xf03d0000 0x10000>; + interrupts = <0x00 0x43 0x04>; + dma-support = <0x00>; + nvt-devname = <0x04>; + }; + + sdp@f0390000 { + compatible = "nvt,nvt_sdp"; + reg = <0xf0390000 0x28>; + interrupts = <0x00 0x0c 0x04>; + }; + + tse@f0650000 { + compatible = "nvt,nvt_tse"; + reg = <0xf0650000 0x90>; + interrupts = <0x00 0x17 0x04>; + }; + + remote@f0250000 { + compatible = "nvt,nvt_remote"; + reg = <0xf0250000 0x28>; + interrupts = <0x00 0x19 0x04>; + }; + + rng: rng@f0680000 { + compatible = "nvt,nvt_rng"; + reg = <0xf0680000 0x100>; + }; + + nvt_arb@f0000000 { + compatible = "nvt,nvt_arb"; + reg = <0xf0000000 0xa000 0xf0100000 0xa000 0xf0fe0000 0x300 0xf0fd0000 0x300>; + interrupts = <0x00 0x21 0x04 0x00 0x33 0x04>; + }; + + nvt_otp@f0660000 { + compatible = "nvt,nvt_otp"; + reg = <0xf0660000 0x70>; + }; + + pll_preset@0 { + + pll3 { + pll_config = <0x03 0x00 0x00>; + }; + + pll4 { + pll_config = <0x04 0x00 0x00>; + }; + + pll5 { + pll_config = <0x05 0x00 0x01>; + }; + + pll6 { + pll_config = <0x06 0x00 0x00>; + }; + + pll7 { + pll_config = <0x07 0x00 0x00>; + }; + + pll8 { + pll_config = <0x08 0x00 0x00>; + }; + + pll9 { + pll_config = <0x09 0x00 0x00>; + }; + + pll10 { + pll_config = <0x0a 0x00 0x01>; + }; + + pll11 { + pll_config = <0x0b 0x00 0x00>; + }; + + pll12 { + pll_config = <0x0c 0x00 0x01>; + }; + + pll13 { + pll_config = <0x0d 0x15752a00 0x01>; + }; + + pll14 { + pll_config = <0x0e 0x00 0x00>; + }; + + pll15 { + pll_config = <0x0f 0x5b8d800 0x01>; + }; + + pll16 { + pll_config = <0x10 0x00 0x00>; + }; + + pll17 { + pll_config = <0x11 0x17d78400 0x01>; + }; + + pll18 { + pll_config = <0x12 0x00 0x01>; + }; + + pllf320 { + pll_config = <0x18 0x1312d000 0x01>; + }; + }; + + i2c0: i2c@f0220000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf0220000 0x100>; + interrupts = <0x00 0x29 0x04>; + clock-frequency = <0x61a80>; + id = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + sen_imx290@1 { + compatible = "nvt,sen_imx290"; + reg = <0x7f>; + path = <0x01>; + + PRESET { + expt_time = <0x2710>; + gain_ratio = <0x3e8>; + }; + + DIRECTION { + mirror = <0x00>; + flip = <0x00>; + }; + + POWER { + mclk = <0x00>; + pwdn_pin = <0xffffffff>; + rst_pin = <0x44>; + rst_time = <0x01>; + stable_time = <0x01>; + }; + + I2C { + i2c_id = <0x00>; + i2c_addr = <0x1a>; + }; + }; + }; + + i2c1: i2c2@f0350000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf0350000 0x100>; + interrupts = <0x00 0x2a 0x04>; + clock-frequency = <0x61a80>; + id = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + sen_imx290@0 { + compatible = "nvt,sen_imx290"; + reg = <0x7f>; + path = <0x00>; + + PRESET { + expt_time = <0x2710>; + gain_ratio = <0x3e8>; + }; + + DIRECTION { + mirror = <0x00>; + flip = <0x00>; + }; + + POWER { + mclk = <0x00>; + pwdn_pin = <0xffffffff>; + rst_pin = <0x44>; + rst_time = <0x01>; + stable_time = <0x01>; + }; + + I2C { + i2c_id = <0x01>; + i2c_addr = <0x1a>; + }; + }; + }; + + i2c2: i2c3@f03a0000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf03a0000 0x100>; + interrupts = <0x00 0x3c 0x04>; + clock-frequency = <0x61a80>; + id = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + i2c3: i2c4@f03b0000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf03b0000 0x100>; + interrupts = <0x00 0x44 0x04>; + clock-frequency = <0x61a80>; + id = <0x03>; + }; + + i2c4: i2c5@f03c0000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf03c0000 0x100>; + interrupts = <0x00 0x45 0x04>; + clock-frequency = <0x61a80>; + id = <0x04>; + }; + + audio@1 { + type = "none"; + i2s_ctrl = <0x00>; + sif_channel = <0x00>; + gpio_cold_reset = <0x00>; + gpio_data = <0x00>; + gpio_clk = <0x00>; + gpio_cs = <0x00>; + adc_zero = <0x00>; + }; + + audio@2 { + type = "embedded"; + i2s_ctrl = <0x04>; + sif_channel = <0x00>; + gpio_cold_reset = <0x00>; + gpio_data = <0x00>; + gpio_clk = <0x00>; + gpio_cs = <0x00>; + adc_zero = <0x00>; + }; + + display { + type = "lcd"; + lcd_ctrl = <0x00>; + sif_channel = <0x02>; + gpio_cs = <0x76>; + gpio_clk = <0x77>; + gpio_data = <0x78>; + }; + + nvtmpp { + compatible = "nvt,nvtmpp"; + }; + + isf_stream { + compatible = "nvt,isf_stream"; + }; + + isf_flow { + compatible = "nvt,isf_flow"; + }; + + isf_vdocap { + compatible = "nvt,isf_vdocap"; + }; + + isf_vdoprc { + compatible = "nvt,isf_vdoprc"; + }; + + isf_dummy { + compatible = "nvt,isf_dummy"; + }; + + isf_vdoenc { + compatible = "nvt,isf_vdoenc"; + }; + + isf_vdodec { + compatible = "nvt,isf_vdodec"; + }; + + isf_vdoout { + compatible = "nvt,isf_vdoout"; + }; + + dispobj { + compatible = "nvt,nvt_dispobj"; + }; + + dispdev { + compatible = "nvt,nvt_dispdev"; + }; + + audio { + compatible = "nvt,nvt_audio"; + }; + + msdcnvt { + compatible = "nvt,msdcnvt"; + }; + + msdcnvt_adj { + compatible = "nvt,msdcnvt_adj"; + }; + + msdcnvt_custom_si { + compatible = "nvt,msdcnvt_custom_si"; + }; + + wavstudio { + compatible = "nvt,wavstudio"; + }; + + isf_audenc { + compatible = "nvt,isf_audenc"; + }; + + isf_auddec { + compatible = "nvt,isf_auddec"; + }; + + isf_audcap { + compatible = "nvt,isf_audcap"; + }; + + isf_audout { + compatible = "nvt,isf_audout"; + }; + + nvt_ipc { + compatible = "nvt,nvt_ipc"; + }; + + nvt_disflow { + compatible = "nvt,nvt_disflow"; + }; + + nvt_memory_cfg { + #address-cells = <0x01>; + #size-cells = <0x01>; + + dram { + reg = <0x00 0x20000000>; + }; + + core2entry1 { + reg = <0x00 0x100000>; + }; + + fdt { + reg = <0x100000 0x100000>; + }; + + shmem { + reg = <0x200000 0x100000>; + }; + + loader { + reg = <0x1000000 0x100000>; + }; + + linuxtmp { + reg = <0x1100000 0x2800000>; + }; + + uboot { + reg = <0x3900000 0x6c0000>; + }; + + core2entry2 { + reg = <0x1ffc0000 0x40000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00 0x10000000>; + }; + + reserved-memory { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + cma0: cma0@0x05000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x5000000 0x3000000>; + alignment = <0x400000>; + status = "okay"; + phandle = <0x06>; + }; + }; + + nvt_cma { + compatible = "nvt,nvt_cma"; + memory-region = <&cma0>; + id = <0x00>; + }; + + hdal-memory { + #address-cells = <0x01>; + #size-cells = <0x01>; + + media { + reg = <0x10000000 0xd800000 0x40000000 0x20000000>; + }; + }; + + hdal-maxpath-cfg { + vdocap_active_list = <0x01 0x01 0x01 0x01 0x01 0x00 0x00 0x00>; + vdoprc_maxdevice = <0x04>; + vdoenc_maxpath = <0x08>; + vdodec_maxpath = <0x02>; + vdoout_maxdevice = <0x01>; + adocap_maxdevice = <0x01>; + adoout_maxdevice = <0x01>; + adoenc_maxpath = <0x01>; + adodec_maxpath = <0x01>; + gfx_maxjob = <0x02>; + stamp_maximg = <0x10>; + vdoprc_maxstamp = <0x04 0x10>; + vdoprc_maxmask = <0x08 0x40>; + vdoenc_maxstamp = <0x20 0x10>; + vdoenc_maxmask = <0x00 0x40>; + vdoout_maxstamp = <0x00 0x10>; + vdoout_maxmask = <0x00 0x40>; + }; + + ai-memory { + #address-cells = <0x01>; + #size-cells = <0x01>; + + dram1 { + reg = <0x1d800000 0x2800000>; + }; + }; + + nvt_info { + BIN_NAME = "FW98528A"; + BIN_NAME_T = "FW98528T"; + EMBMEM_BLK_SIZE = "0x10000"; + EMBMEM = "EMBMEM_SPI_NOR"; + NVT_CFG_APP_EXTERNAL = "dhd_priv iperf-3"; + NVT_CFG_APP = "hfs lviewd nvtrtspd msdcnvt arm_neon_perf mem mem_hotplug memcpy drystone-2.0"; + NVT_ROOTFS_ETC = "IPCAM1_NOR_EVB"; + NVT_BINARY_FILE_STRIP = "yes"; + NVT_CFG_KERNEL_CFG = ""; + NVT_LINUX_SMP = "NVT_LINUX_SMP_ON"; + NVT_CHIP_ID = "CHIP_NA51084"; + NVT_DEFAULT_NETWORK_BOOT_PROTOCOL = "NVT_DEFAULT_NETWORK_BOOT_PROTOCOL_STATIC_IP"; + NVT_ROOTFS_TYPE = "NVT_ROOTFS_TYPE_SQUASH"; + NVT_ETHERNET = "NVT_ETHERNET_EQOS"; + NVT_SDIO_WIFI = "NVT_SDIO_WIFI_NONE"; + NVT_USB_WIFI = "NVT_USB_WIFI_NONE"; + NVT_USB_4G = "NVT_USB_4G_NONE"; + WIFI_RTK_MDL = "WIFI_RTK_MDL_8189"; + WIFI_BRCM_MDL = "WIFI_BRCM_MDL_43438a1_ampk6212axtal26"; + WIFI_NVT_MDL = "WIFI_NVT_MDL_18211"; + NVT_CURL_SSL = "NVT_CURL_SSL_OPENSSL"; + NVT_UBOOT_ENV_IN_STORG_SUPPORT = "NVT_UBOOT_ENV_IN_STORG_SUPPORT_OFF"; + }; +}; diff --git a/openipc/ns02501.dtsi b/openipc/ns02501.dtsi new file mode 100644 index 000000000000..e57734286ad7 --- /dev/null +++ b/openipc/ns02501.dtsi @@ -0,0 +1,6000 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Novatek NS02501 (NT98532/533): the device tree of the NS02501 SDK's + * NT98532 NOR board (cfg_532_IPC_NOR_SQUASHFS_BD_EVB, flattened), with + * the OpenIPC boot chain in the nor node: the loader at 0, this tree at + * 0x10000, U-Boot at 0x20000. U-Boot runs at 0x03900000, below 64 MiB as + * on NA51089, and the loader's scratch (linuxtmp) ends there; SHMINFO + * stays at the SDK's 0xA00000. + * + * The tree is ~95 KiB, its clocks described in it (nvt-clk), more than + * its 64 KiB slot: openipc/nvt-image.py stores it in an LZMA BCL1 + * container, which the loader unpacks (board/novatek/ns02501/loader). + * + * The loader reads /nvt_memory_cfg (where U-Boot runs, where this tree + * and SHMINFO go) and /nor/partition_uboot. U-Boot hands the tree on to + * the kernel, with /memory and /hdal-memory/media split at ${osmem} + * (board/novatek/na51089/na51089.c). + */ + +/ { + model = "Novatek NS02501"; + compatible = "novatek,ns02501", "nvt,ca32"; + interrupt-parent = <&gic>; + #address-cells = <0x01>; + #size-cells = <0x01>; + + cpu_opp_table: opp_table { + compatible = "operating-points-v2"; + opp-shared; + phandle = <0x02>; + + opp-80000000 { + opp-hz = /bits/ 64 <0x4c4b400>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <0xe4e1c00>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <0x1c9c3800>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <0x2faf0800>; + }; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a32"; + reg = <0x00>; + clock-frequency = <0x2faf0800>; + operating-points-v2 = <&cpu_opp_table>; + phandle = <0x03>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a32"; + reg = <0x01>; + cpu-release-addr = <0xf0090100>; + clock-frequency = <0x2faf0800>; + operating-points-v2 = <&cpu_opp_table>; + phandle = <0x04>; + }; + }; + + cg@f0020000 { + compatible = "nvt,core_clk"; + reg = <0xf0020000 0x10000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0x308>, <0x01 0x0e 0x308>, <0x01 0x0b 0x308>, <0x01 0x0a 0x308>; + clock-frequency = <0xb71b00>; + arm,cpu-registers-not-fw-configured; + always-on; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <0x00 0x74 0x04>, <0x00 0x75 0x04>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + gic: interrupt-controller@0xfff00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <0x03>; + interrupt-controller; + reg = <0xfff01000 0x1000>, <0xfff02000 0x1000>; + phandle = <0x01>; + }; + + scu: snoop-control-unit@0xf0620000 { + compatible = "arm,cortex-a7-scu"; + reg = <0xf0620000 0x100>; + }; + + aliases { + mmc0 = "/mmc@f0420000"; + }; + + uart@f0290000 { + compatible = "ns16550a"; + reg = <0xf0290000 0x1000>; + clocks = <&clk_uart0>; + clock-names = "f0290000.uart"; + interrupts = <0x00 0x2b 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + uart_id = <0x00>; + }; + + uart@f0300000 { + compatible = "ns16550a"; + reg = <0xf0300000 0x1000>; + clocks = <&clk_uart1>; + clock-names = "f0300000.uart"; + interrupts = <0x00 0x2c 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + hw_flowctrl = <0x00>; + rx_trig_level = <0x03>; + uart_id = <0x01>; + }; + + uart@f0310000 { + compatible = "ns16550a"; + reg = <0xf0310000 0x1000>; + clocks = <&clk_uart2>; + clock-names = "f0310000.uart"; + interrupts = <0x00 0x2d 0x04>; + baud = <0x1c200>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + no-loopback-test = <0x01>; + clock-frequency = <0x2dc6c00>; + fifo-size = <0x40>; + hw_flowctrl = <0x00>; + rx_trig_level = <0x03>; + uart_id = <0x02>; + }; + + kdrv_rpc: cc@f0090000 { + compatible = "kdrv_rpc"; + reg = <0xf0090000 0x300>; + interrupts = <0x00 0x3b 0x04>; + }; + + mmc0: mmc@f0420000 { + compatible = "nvt,nvt_mmc"; + reg = <0xf0420000 0x1000>; + clocks = <&clk_mmc0>; + clock-names = "f0420000.mmc"; + interrupts = <0x00 0x1e 0x04>; + max-frequency = <0x2dc6c00>; + voltage-switch = <0x00>; + max-voltage = <0xce4>; + bus-width = <0x04>; + neg-sample-edge = <0x00>; + driving = <0x02 0x02 0x02 0x02 0x02 0x02 0x04 0x04 0x04 0x04 0x04 0x04>; + cd_gpio = <0x66 0x00 0x00>; + no-sdio; + no-mmc; + }; + + nand: nand@f0400000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "nvt,nvt_spinand"; + reg = <0xf0400000 0x1000>; + interrupts = <0x00 0x1d 0x04>; + clock-frequency = <0xb71b00>; + nvt-devname = "spi_nand.0"; + }; + + nor: nor@f0400000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + clocks = <&clk_nand>; + clock-names = "f0400000.nor"; + compatible = "nvt,nvt_spinor"; + reg = <0xf0400000 0x1000>; + interrupts = <0x00 0x1d 0x04>; + clock-frequency = <0xb71b00>; + nvt-devname = "spi_nor.0"; + trace-stdtable = <0x01>; + + + partition_loader { + label = "loader"; + reg = <0x00 0x00 0x00 0x10000>; + }; + + partition_fdt { + label = "fdt"; + reg = <0x00 0x10000 0x00 0x10000>; + }; + + partition_uboot { + label = "uboot"; + reg = <0x00 0x20000 0x00 0x20000>; + }; + + /* The loader looks a partition up here by its label */ + nvtpack { + ver = "NVTPACK_FW_INI_16072017"; + method = <0x01>; + + index { + + id0 { + partition_name = "loader"; + }; + + id1 { + partition_name = "fdt"; + }; + + id2 { + partition_name = "uboot"; + }; + }; + }; + }; + + gpio: gpio@f0070000 { + compatible = "nvt,nvt_gpio"; + reg = <0xf0070000 0x10000>; + interrupts = <0x00 0x18 0x04 0x00 0x31 0x04>; + #interrupt-cells = <0x03>; + interrupt-controller; + interrupt-parent = <&gic>; + #gpio-cells = <0x02>; + }; + + eth0@f02b0000 { + compatible = "nvt,synopsys_eth"; + reg = <0xf02b0000 0x3800>; + interrupts = <0x00 0x22 0x04>; + sp-clk = <0x00>; + ref-clk-out = <0x00>; + }; + + phy@f02b3800 { + compatible = "nvt,eth_phy"; + reg = <0xf02b3800 0x400>; + }; + + wdt@f0050000 { + compatible = "nvt,nvt_wdt"; + reg = <0xf0050000 0x1000>; + clocks = <&clk_wdt>; + clock-names = "f0050000.wdt"; + interrupts = <0x00 0x4b 0x04>; + }; + + pwm@f0210000 { + compatible = "nvt,nvt_pwm"; + reg = <0xf0210000 0x1000>; + interrupts = <0x00 0x1a 0x04>; + clocks = <&clk_pwm0>, <&clk_pwm1>, <&clk_pwm2>, <&clk_pwm3>, <&clk_pwm4>, <&clk_pwm5>, <&clk_pwm6>, <&clk_pwm7>, <&clk_pwm8>, <&clk_pwm9>, <&clk_pwm10>, <&clk_pwm11>; + clock-names = "f0210000.pwm0", "f0210000.pwm1", "f0210000.pwm2", "f0210000.pwm3", "f0210000.pwm4", "f0210000.pwm5", "f0210000.pwm6", "f0210000.pwm7", "f0210000.pwm8", "f0210000.pwm9", "f0210000.pwm10", "f0210000.pwm11"; + nums = <0x0c>; + src_freq = <0x7270e00>; + status = "okay"; + bypass_pm = <0x00>; + }; + + adc@2,f01D0000 { + compatible = "nvt,nvt_adc"; + reg = <0xf01d0000 0x1000>; + clocks = <&clk_adc>; + clock-names = "f01d0000.adc"; + interrupts = <0x00 0x49 0x04>; + clock-frequency = <0xf42400>; + #io-channel-cells = <0x01>; + }; + + rtc@f0060000 { + compatible = "nvt,nvt_rtc"; + reg = <0xf0060000 0x100>; + interrupts = <0x00 0x4c 0x04>; + }; + + drtc@f00b0000 { + compatible = "nvt,nvt_drtc"; + reg = <0xf00b0000 0x100>; + clocks = <&clk_drtc>; + interrupts = <0x00 0x04 0x04>; + }; + + cypt: cypt@f0620000 { + compatible = "nvt,nvt_crypto"; + reg = <0xf0620000 0x100>; + interrupts = <0x00 0x26 0x04>; + mclk = <0x01>; + }; + + hash: hash@f0670000 { + compatible = "nvt,nvt_hash"; + reg = <0xf0670000 0x100>; + interrupts = <0x00 0x1c 0x04>; + mclk = <0x01>; + }; + + rsa: rsa@f06a0000 { + compatible = "nvt,nvt_rsa"; + reg = <0xf06a0000 0x100>; + interrupts = <0x00 0x14 0x04>; + mclk = <0x01>; + }; + + top: top@f0010000 { + compatible = "nvt,nvt_top"; + reg = <0xf0010000 0x2000 0xf0030000 0x2000 0xf0070000 0x10000 0xf0110000 0x2000 0xf0130000 0x2000 0xf0170000 0x2000>; + + sdio { + pinmux = <0x01>; + }; + + nand { + pinmux = <0x01>; + }; + + eth { + pinmux = <0x00>; + }; + + i2c { + pinmux = <0x00>; + }; + + pwm { + pinmux = <0x00>; + }; + + pwmII { + pinmux = <0x00>; + }; + + pwmIII { + pinmux = <0x00>; + }; + + ccnt { + pinmux = <0x00>; + }; + + sensor { + pinmux = <0x00>; + }; + + sensor2 { + pinmux = <0x00>; + }; + + sensormisc { + pinmux = <0x00>; + }; + + sensorsync { + pinmux = <0x00>; + }; + + audio { + pinmux = <0x00>; + }; + + uart { + pinmux = <0x01>; + }; + + csi { + pinmux = <0x00>; + }; + + remote { + pinmux = <0x00>; + }; + + sdp { + pinmux = <0x00>; + }; + + spi { + pinmux = <0x00>; + }; + + sif { + pinmux = <0x00>; + }; + + misc { + pinmux = <0x00>; + }; + + lcd { + pinmux = <0x00>; + }; + + tv { + pinmux = <0x00>; + }; + + sel_lcd { + pinmux = <0x00>; + }; + + weigand { + pinmux = <0x00>; + }; + + pgpio0 { + pad_config = <0x180 0x00 0x40 0x00>; + }; + + pgpio1 { + pad_config = <0x182 0x00 0x42 0x00>; + }; + + nvt_sen_os04c10@0 { + pinctrl = <0x0e 0x01 0x03 0x01>; + }; + + nvt_sen_os04e10@0 { + pinctrl = <0x0e 0x01 0x03 0x01>; + }; + + nvt_sen_sc450ai@0 { + pinctrl = <0x0e 0x01 0x03 0x01>; + }; + + nvt_sen_nt99436@0 { + pinctrl = <0x0e 0x01 0x03 0x01>; + }; + + nvt_sen_os05a10@0 { + pinctrl = <0x0e 0x01 0x03 0x01>; + }; + + nvt_sen_gc4103@0 { + pinctrl = <0x0e 0x01 0x03 0x01>; + }; + }; + + sie: sie@f0c00000 { + compatible = "nvt,nvt_sie"; + reg = <0xf0c00000 0xb00 0xf0d20000 0xb00 0xf0d30000 0xb00 0xf0d40000 0xb00>; + interrupts = <0x00 0x01 0x04 0x00 0x02 0x04 0x00 0x03 0x04 0x00 0x51 0x04>; + clocks = <&clk_sie1>, <&clk_sie2>, <&clk_sie3>, <&clk_sie4>, <&sie1_pclk>, <&sie2_pclk>, <&sie3_pclk>, <&sie4_pclk>, <&sie1_pxclk>, <&sie2_pxclk>, <&sie3_pxclk>, <&sie4_pxclk>, <&sie2_intclk>, <&sn_mclk1>, <&sn_mclk2>, <&sn_mclk3>; + clock-names = "f0c00000.sie1", "f0d20000.sie2", "f0d30000.sie3", "f0d40000.sie4", "sie1_pclk", "sie2_pclk", "sie3_pclk", "sie4_pclk", "sie1_pxclk", "sie2_pxclk", "sie3_pxclk", "sie4_pxclk", "sie2_intclk", "sn_mclk1", "sn_mclk2", "sn_mclk3"; + }; + + tge: tge@f0cc0000 { + compatible = "nvt,kdrv_tge"; + reg = <0xf0cc0000 0x140>; + clocks = <&clk_tge>, <&clk_tgeflashA>, <&clk_tgemshA>, <&tge_pclk>, <&sn_mclk1>, <&sn_mclk2>; + clock-names = "f0cc0000.tge", "clk_tgeflashA", "clk_tgemshA", "tge_pclk", "sn_mclk1", "sn_mclk2"; + interrupts = <0x00 0x16 0x04>; + }; + + rhe@f0ce0000 { + compatible = "nvt,kdrv_rhe"; + reg = <0xf0ce0000 0x900>; + interrupts = <0x00 0x0d 0x04>; + }; + + ime@f0c40000 { + compatible = "nvt,kdrv_ime"; + reg = <0xf0c40000 0xbfc>; + clocks = <&clk_ime>; + clock-names = "f0c40000.ime"; + interrupts = <0x00 0x06 0x04>; + }; + + ife2@f0d00000 { + compatible = "nvt,kdrv_ife2"; + reg = <0xf0d00000 0x100>; + interrupts = <0x00 0x09 0x04>; + }; + + ise@f0c90000 { + compatible = "nvt,kdrv_ise"; + reg = <0xf0c90000 0x154>; + clocks = <&clk_ise>; + clock-names = "f0c90000.ise"; + interrupts = <0x00 0x15 0x04>; + }; + + ipe@f0c30000 { + compatible = "nvt,kdrv_ipe"; + reg = <0xf0c30000 0xa4c>; + clocks = <&clk_ipe>; + clock-names = "f0c30000.ipe"; + interrupts = <0x00 0x05 0x04>; + }; + + ife@f0c70000 { + compatible = "nvt,kdrv_ife"; + reg = <0xf0c70000 0xd3c>; + clocks = <&clk_ife>; + clock-names = "f0c70000.ife"; + interrupts = <0x00 0x08 0x04>; + }; + + vpe@f0cd0000 { + compatible = "nvt,kdrv_vpe"; + reg = <0xf0cd0000 0x808>; + clocks = <&clk_vpe>; + clock-names = "f0cd0000.vpe"; + interrupts = <0x00 0x07 0x04>; + }; + + ai@f0cb0000 { + compatible = "nvt,kdrv_ai"; + reg = <0xf0cb0000 0x1000 0xf0d50000 0x1000 0xf0c60000 0x1000>; + interrupts = <0x00 0x0b 0x04 0x00 0x0d 0x04 0x00 0x0e 0x04>; + clock-frequency = <0x23c34600 0x1c9c3800 0x23c34600>; + }; + + mdbc@f0c10000 { + compatible = "nvt,kdrv_mdbc"; + reg = <0xf0c10000 0x15c>; + clocks = <&clk_mdbc>; + clock-names = "0xf0c10000.mdbc"; + interrupts = <0x00 0x2e 0x04>; + }; + + dis@f0c50000 { + compatible = "nvt,kdrv_dis"; + reg = <0xf0c50000 0x114>; + interrupts = <0x00 0x0a 0x04>; + }; + + coe@f0a11000 { + compatible = "nvt,nvt_coe"; + reg = <0xf0a11000 0x2c0>; + }; + + dce@f0c20000 { + compatible = "nvt,kdrv_dce"; + reg = <0xf0c20000 0x650>; + interrupts = <0x00 0x07 0x04>; + }; + + ive@f0d70000 { + compatible = "nvt,kdrv_ive"; + reg = <0xf0d70000 0x1d0>; + clocks = <&clk_ive>; + clock-names = "f0d70000.ive"; + interrupts = <0x00 0x35 0x04>; + }; + + sde@f0d90000 { + compatible = "nvt,kdrv_sde"; + reg = <0xf0d90000 0x90>; + interrupts = <0x00 0x4a 0x04>; + }; + + ide@f0800000 { + compatible = "nvt,nvt_ide"; + clocks = <&clk_ide>; + reg = <0xf0800000 0x1000>; + interrupts = <0x00 0x30 0x04>; + }; + + dsi@f0120000 { + compatible = "nvt,nvt_dsi"; + reg = <0xf0120000 0x1000>; + interrupts = <0x00 0x47 0x04>; + }; + + dsiphy@f0130000 { + compatible = "nvt,nvt_dsiphy"; + reg = <0xf0130000 0x1000>; + }; + + csi@f0280000 { + compatible = "nvt,nvt_csi"; + reg = <0xf0280000 0x100 0xf0330000 0x100>; + interrupts = <0x00 0x36 0x04 0x00 0x37 0x04>; + }; + + lvds@f0270000 { + compatible = "nvt,nvt_lvds"; + clocks = <&clk_csi0>, <&clk_csi1>; + clock-names = "f0270000.lvds1", "f0370000.lvds2"; + reg = <0xf0270000 0x200 0xf0370000 0x200>; + interrupts = <0x00 0x36 0x04 0x00 0x37 0x04>; + }; + + senphy@f06b0000 { + compatible = "nvt,nvt_senphy"; + reg = <0xf06b0000 0x100>; + }; + + ssenif@f0xx0000 { + compatible = "nvt,nvt_ssenif"; + reg = <0xf02c0000 0x2000>; + interrupts = <0x00 0x3d 0x04>; + }; + + thmal@2,f0260000 { + compatible = "nvt,thermal"; + reg = <0xf0260000 0x100>; + clocks = <&clk_thmal>; + clock-names = "f0260000.thmal"; + clock-frequency = <0xb71b00>; + default_trim = <0xbf>; + }; + + sif@f0240000 { + compatible = "nvt,nvt_sif"; + reg = <0xf0240000 0x200>; + interrupts = <0x00 0x28 0x04>; + clocks = <&clk_sif>; + clock-names = "f0240000.sif"; + clock-frequency = <0x5b8d800>; + }; + + graphic@f0c80000 { + compatible = "nvt,nvt_graphic"; + clocks = <&clk_grph>, <&clk_grph2>; + reg = <0xf0c80000 0x300 0xf0d10000 0x100>; + interrupts = <0x00 0x12 0x04 0x00 0x13 0x04>; + }; + + affine@f0ca0000 { + compatible = "nvt,nvt_affine"; + reg = <0xf0ca0000 0x100>; + interrupts = <0x00 0x34 0x04>; + }; + + h26x@f0a10000 { + compatible = "nvt,nvt_venc"; + reg = <0xf0a10000 0xc00>; + interrupts = <0x00 0x10 0x04>; + power_saving = <0x00>; + }; + + timer@f0040000 { + compatible = "nvt,nvt_timer"; + reg = <0xf0040000 0x300>; + interrupts = <0x00 0x00 0x04>; + }; + + nvt_hr_hwtimer@f00c0000 { + compatible = "nvt,nvt_hwtimer"; + reg = <0xf00c0000 0x1000>; + clocks = <&clk_hrtimer1>; + interrupts = <0x00 0x3d 0x04>; + index = <0x00>; + }; + + nvt_hr_hwtimer@f0150000 { + compatible = "nvt,nvt_hwtimer"; + reg = <0xf0150000 0x1000>; + clocks = <&clk_hrtimer2>; + interrupts = <0x00 0x3e 0x04>; + index = <0x01>; + }; + + nvt_hr_hwtimer@f0160000 { + compatible = "nvt,nvt_hwtimer"; + reg = <0xf0160000 0x1000>; + clocks = <&clk_hrtimer3>; + interrupts = <0x00 0x3f 0x04>; + index = <0x02>; + }; + + nvt_hr_hwtimer@f0170000 { + compatible = "nvt,nvt_hwtimer"; + reg = <0xf0170000 0x1000>; + clocks = <&clk_hrtimer4>; + interrupts = <0x00 0x40 0x04>; + index = <0x03>; + }; + + nvt_hr_hwtimer@f0180000 { + compatible = "nvt,nvt_hwtimer"; + reg = <0xf0180000 0x1000>; + clocks = <&clk_hrtimer5>; + interrupts = <0x00 0x41 0x04>; + index = <0x04>; + }; + + nvt_hr_hwtimer@f0190000 { + compatible = "nvt,nvt_hwtimer"; + reg = <0xf0190000 0x1000>; + clocks = <&clk_hrtimer6>; + interrupts = <0x00 0x42 0x04>; + index = <0x05>; + }; + + nvt_hr_hwtimer@f01a0000 { + compatible = "nvt,nvt_hwtimer"; + reg = <0xf01a0000 0x1000>; + clocks = <&clk_hrtimer7>; + interrupts = <0x00 0x43 0x04>; + index = <0x06>; + }; + + clocksource@f01c0000 { + compatible = "nvt,nvt_clk_src"; + reg = <0xf01c0000 0x1000>; + clock-frequency = <0x7270e00>; + clocks = <&clk_hrtimer8>; + interrupts = <0x00 0x44 0x04>; + }; + + nvt_hr_hwtimer@f01e0000 { + compatible = "nvt,nvt_hwtimer"; + reg = <0xf01e0000 0x1000>; + clocks = <&clk_hrtimer9>; + interrupts = <0x00 0x48 0x04>; + index = <0x07>; + }; + + eac@f0640000 { + compatible = "nvt,nvt_eac"; + reg = <0xf0640000 0x200>; + }; + + jpeg_1: jpeg_1@f0a00000 { + compatible = "nvt,jpeg"; + reg = <0xf0a00000 0x10000>; + interrupts = <0x00 0x11 0x04>; + clocks = <&jpeg1_clk>; + clock-names = "jpeg1_clk"; + device-id = <0x00>; + }; + + usb20host@ff600000 { + compatible = "nvt,ehci-nvtivot"; + reg = <0xff600000 0x1000 0xf0601000 0x1000 0xf0600000 0x1000>; + interrupts = <0x00 0x1b 0x04>; + channel = <0x00>; + clocks = <&clk_usb20>; + clock-names = "ff600000.usb20host"; + use_top = <0x01>; + }; + + usb20@ff600000 { + compatible = "nvt,fotg200_udc"; + reg = <0xff600000 0x1000 0xf0601000 0x1000 0xf0600000 0x1000>; + interrupts = <0x00 0x1b 0x04>; + channel = <0x00>; + clocks = <&clk_usb20>; + clock-names = "ff600000.usb20"; + use_top = <0x01>; + }; + + nvt_usb_chrg@ff600000 { + compatible = "nvt,nvt_usb_chrgdet"; + reg = <0xff600000 0x1000>; + }; + + dai@f0630000 { + compatible = "nvt,nvt_dai"; + reg = <0xf0630000 0x1000>; + interrupts = <0x00 0x0f 0x04>; + }; + + rotate@f0cf0000 { + compatible = "nvt,nvt_rotation"; + reg = <0xf0cf0000 0x100>; + interrupts = <0x00 0x51 0x04>; + }; + + drvdump@0 { + compatible = "nvt,nvt_drvdump"; + }; + + dsp@f1430000 { + compatible = "nvt,nvt_dsp"; + reg = <0xf1430000 0x200 0xf2000000 0x1000000 0xf1440000 0x200 0xf3000000 0x1000000>; + interrupts = <0x00 0x4c 0x04 0x00 0x4d 0x04>; + }; + + spi0: spi@f0230000 { + compatible = "nvt,nvt_spi"; + reg = <0xf0230000 0x1000>; + interrupts = <0x00 0x23 0x04>; + dma-support = <0x00>; + nvt-devname = <0x00>; + clock-frequency = <0x2dc6c00>; + clocks = <&clk_spi0>; + clock-names = "f0230000.spi"; + }; + + spi1: spi@f0320000 { + compatible = "nvt,nvt_spi"; + reg = <0xf0320000 0x1000>; + interrupts = <0x00 0x24 0x04>; + dma-support = <0x00>; + nvt-devname = <0x01>; + clock-frequency = <0x2dc6c00>; + clocks = <&clk_spi1>; + clock-names = "f0320000.spi"; + }; + + spi2: spi@f0340000 { + compatible = "nvt,nvt_spi"; + reg = <0xf0340000 0x1000>; + interrupts = <0x00 0x25 0x04>; + dma-support = <0x00>; + nvt-devname = <0x02>; + clock-frequency = <0x2dc6c00>; + clocks = <&clk_spi2>; + clock-names = "f0340000.spi"; + }; + + sdp@f0390000 { + compatible = "nvt,nvt_sdp"; + reg = <0xf0390000 0x200>; + interrupts = <0x00 0x0c 0x04>; + clocks = <&clk_sdp>; + clock-names = "f0390000.sdp"; + }; + + tse@f0650000 { + compatible = "nvt,nvt_tse"; + reg = <0xf0650000 0x90>; + interrupts = <0x00 0x17 0x04>; + clocks = <&clk_tse>; + clock-names = "f0650000.tse"; + max-frequency = <0x1312d000>; + }; + + remote@f0250000 { + compatible = "nvt,nvt_remote"; + reg = <0xf0250000 0x28>; + clocks = <&remote_clk>; + clock-names = "remote_clk"; + interrupts = <0x00 0x19 0x04>; + }; + + rng: rng@f0680000 { + compatible = "nvt,nvt_rng"; + reg = <0xf0680000 0x100>; + }; + + nvt_arb@f0000000 { + compatible = "nvt,nvt_arb"; + reg = <0xf0000000 0xa000 0xf0fe0000 0x300>; + interrupts = <0x00 0x21 0x04>; + }; + + nvt_otp@f0660000 { + compatible = "nvt,nvt_otp"; + reg = <0xf0660000 0x70>; + }; + + nvt_gzip@f0100000 { + compatible = "nvt,nvt_gzip"; + reg = <0xf0100000 0x50 0xf0000000 0x8100>; + interrupts = <0x00 0x3c 0x04>; + clocks = <&clk_gzip>; + clock-names = "clk_gzip"; + nvt-devname = "nvt_gzip.0"; + }; + + kdrv_ipp { + clock-frequency = <0xe4e1c00>; + }; + + uvcp: uvcp@f0690000 { + compatible = "nvt,nvt_uvcp"; + reg = <0xf0690000 0x200>; + clocks = <&clk_uvcp>; + clock-names = "f0690000.uvcp"; + interrupts = <0x00 0x3b 0x04>; + }; + + nvt_ddr_slow@f00d0000 { + compatible = "nvt,nvt_ddr_slow"; + reg = <0xf00d0000 0x9000>; + clocks = <&clk_cfe>; + clock-names = "cfe_clk"; + interrupts = <0x00 0x38 0x04>; + }; + + nvt_at80c51@f00a0000 { + compatible = "nvt,nvt_at80c51"; + reg = <0xf00a0000 0x200 0xf0140000 0x4000>; + clocks = <&prfll>, <&clk_apb>, <&clk_uart2>; + clock-names = "clk_prmcu"; + }; + + pll_preset@0 { + + pll3 { + pll_config = <0x03 0x00 0x00>; + }; + + pll4 { + pll_config = <0x04 0x00 0x00>; + }; + + pll5 { + pll_config = <0x05 0x11b3dc40 0x01>; + }; + + pll6 { + pll_config = <0x06 0x00 0x00>; + }; + + pll7 { + pll_config = <0x07 0x00 0x00>; + }; + + pll8 { + pll_config = <0x08 0x00 0x00>; + }; + + pll9 { + pll_config = <0x09 0x00 0x00>; + }; + + pll11 { + pll_config = <0x0b 0x00 0x00>; + }; + + pll12 { + pll_config = <0x0c 0x00 0x01>; + }; + }; + + i2c: i2c@f0220000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf0220000 0x100>; + interrupts = <0x00 0x0a 0x04>; + clock-frequency = <0x61a80>; + id = <0x00>; + clocks = <&clk_i2c>; + clock-names = "f0220000.i2c"; + }; + + i2c2: i2c2@f0350000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf0350000 0x100>; + interrupts = <0x00 0x29 0x04>; + clock-frequency = <0x61a80>; + id = <0x01>; + clocks = <&clk_i2c2>; + clock-names = "f0350000.i2c2"; + }; + + i2c3: i2c3@f0360000 { + compatible = "nvt,nvt_i2c"; + reg = <0xf0360000 0x100>; + interrupts = <0x00 0x2a 0x04>; + clock-frequency = <0x61a80>; + id = <0x02>; + clocks = <&clk_i2c3>; + clock-names = "f0360000.i2c3"; + }; + + display { + type = "lcd"; + lcd_ctrl = <0x01>; + sif_channel = <0x02>; + gpio_cs = <0x63>; + gpio_clk = <0x64>; + gpio_data = <0x65>; + }; + + nvtvos { + bIstrylock = <0x01>; + trylock_timeout = <0x1388>; + }; + + nvtmpp { + compatible = "nvt,nvtmpp"; + }; + + isf_stream { + compatible = "nvt,isf_stream"; + }; + + isf_flow { + compatible = "nvt,isf_flow"; + }; + + isf_vdocap { + compatible = "nvt,isf_vdocap"; + }; + + isf_vdoprc { + compatible = "nvt,isf_vdoprc"; + }; + + isf_dummy { + compatible = "nvt,isf_dummy"; + }; + + isf_vdoenc { + compatible = "nvt,isf_vdoenc"; + }; + + isf_vdodec { + compatible = "nvt,isf_vdodec"; + }; + + isf_vdoout { + compatible = "nvt,isf_vdoout"; + }; + + dispobj { + compatible = "nvt,nvt_dispobj"; + }; + + dispdev { + compatible = "nvt,nvt_dispdev"; + }; + + audio { + compatible = "nvt,nvt_audio"; + }; + + wavstudio { + compatible = "nvt,wavstudio"; + }; + + isf_audenc { + compatible = "nvt,isf_audenc"; + }; + + isf_auddec { + compatible = "nvt,isf_auddec"; + }; + + isf_audcap { + compatible = "nvt,isf_audcap"; + }; + + isf_audout { + compatible = "nvt,isf_audout"; + }; + + nvt_ipc { + compatible = "nvt,nvt_ipc"; + }; + + nvt_gfx { + compatible = "nvt,nvt_gfx"; + }; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200 rootfstype=squashfs ro "; + }; + + nvt_memory_cfg { + #address-cells = <0x01>; + #size-cells = <0x01>; + + dram { + reg = <0x00 0x10000000>; + }; + + core2entry1 { + reg = <0x00 0x10000>; + }; + + core2entry2 { + reg = <0x10000 0x10000>; + }; + + fdt { + reg = <0x100000 0x100000>; + }; + + shmem { + reg = <0xa00000 0x100000>; + }; + + loader { + reg = <0x1000000 0x100000>; + }; + + linuxtmp { + reg = <0x1100000 0x2800000>; + }; + + all_in_one { + reg = <0x6640000 0x9000000>; + }; + + kernel_img { + reg = <0xf640000 0x300000>; + }; + + uboot { + reg = <0x3900000 0x6c0000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00 0x2400000>; + }; + + reserved-memory { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + }; + + nvt_os_mem { + compatible = "nvt,nvt_os_mem"; + }; + + nvtfmem { + compatible = "nvt,nvt_fmem"; + }; + + hdal-memory { + #address-cells = <0x02>; + #size-cells = <0x01>; + + media { + reg = <0x00 0x2400000 0xdc00000>; + }; + + cfgs { + max_pools_cnt = <0x100>; + }; + }; + + hdal-maxpath-cfg { + vdocap_active_list = <0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + vdoprc_maxdevice = <0x04>; + vdoenc_maxpath = <0x08>; + vdodec_maxpath = <0x02>; + vdoout_maxdevice = <0x02>; + adocap_maxdevice = <0x01>; + adoout_maxdevice = <0x02>; + adoenc_maxpath = <0x01>; + adodec_maxpath = <0x01>; + gfx_maxjob = <0x02>; + stamp_maximg = <0x40>; + vdoprc_maxstamp = <0x00 0x10>; + vdoprc_maxmask = <0x08 0x40>; + vdoenc_maxstamp = <0x20 0x10>; + vdoenc_maxmask = <0x10 0x40>; + vdoout_maxstamp = <0x00 0x10>; + vdoout_maxmask = <0x00 0x40>; + }; + + nvt_chip_mapping { + #address-cells = <0x03>; + #size-cells = <0x01>; + + dram_map { + reg = <0x00 0x00 0x00 0x10000000>; + }; + }; + + max-resolution { + vdoenc_maxresolution = <0x1000 0x1000>; + }; + + nvt_info { + BIN_NAME = "FW98532A"; + BIN_NAME_T = "FW98532T"; + EMBMEM_BLK_SIZE = "0x10000"; + EMBMEM = "EMBMEM_SPI_NOR"; + NVT_CFG_APP_EXTERNAL = "dhd_priv iperf-3"; + NVT_CFG_APP = "mem"; + NVT_ROOTFS_ETC = "COMMON"; + NVT_BINARY_FILE_STRIP = "yes"; + NVT_CFG_KERNEL_CFG = "ns02501_ipc_a32_evb_defconfig_nor_release"; + NVT_CFG_UBOOT_CFG = "nvt-ns02501_a32_nor_defconfig"; + NVT_OPTEE_INSTALL = "DISABLE"; + NVT_LINUX_SMP = "NVT_LINUX_SMP_OFF"; + NVT_FPGA_EMULATION = "NVT_FPGA_EMULATION_OFF"; + NVT_DEFAULT_NETWORK_BOOT_PROTOCOL = "NVT_DEFAULT_NETWORK_BOOT_PROTOCOL_STATIC_IP"; + NVT_ROOTFS_TYPE = "NVT_ROOTFS_TYPE_NOR_SQUASH"; + NVT_ETHERNET = "NVT_ETHERNET_EQOS"; + NVT_SDIO_WIFI = "NVT_SDIO_WIFI_NONE"; + NVT_USB_WIFI = "NVT_USB_WIFI_NONE"; + NVT_USB_4G = "NVT_USB_4G_NONE"; + WIFI_RTK_MDL = "WIFI_RTK_MDL_8189"; + WIFI_BRCM_MDL = "WIFI_BRCM_MDL_43438a1_ampk6212axtal26"; + WIFI_NVT_MDL = "WIFI_NVT_MDL_18211"; + NVT_CURL_SSL = "NVT_CURL_SSL_OPENSSL"; + NVT_UBOOT_ENV_IN_STORG_SUPPORT = "NVT_UBOOT_ENV_IN_STORG_SUPPORT_OFF"; + }; + + nvt-clk { + + reserved: reserved { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "reserved"; + phandle = <0x60>; + }; + + PAUTOGATING: PAUTOGATING { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "PAUTOGATING"; + phandle = <0x5c>; + }; + + ext: ext { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "ext"; + }; + + ext2: ext2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "ext2"; + }; + + pre_sram_cpu: pre_sram_cpu { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "pre_sram_cpu"; + phandle = <0x6f>; + }; + + pre_sram_pre: pre_sram_pre { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "pre_sram_pre"; + phandle = <0x70>; + }; + + preife_sram_ife: preife_sram_ife { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "preife_sram_ife"; + phandle = <0x71>; + }; + + preife_sram_pre: preife_sram_pre { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "preife_sram_pre"; + phandle = <0x72>; + }; + + dne_sram_cpu: dne_sram_cpu { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "dne_sram_cpu"; + phandle = <0x73>; + }; + + dne_sram_ime: dne_sram_ime { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "dne_sram_ime"; + phandle = <0x74>; + }; + + dne_sram_dne: dne_sram_dne { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "dne_sram_dne"; + phandle = <0x75>; + }; + + ife_sram_cpu: ife_sram_cpu { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "ife_sram_cpu"; + phandle = <0x76>; + }; + + ife_sram_ife: ife_sram_ife { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "ife_sram_ife"; + phandle = <0x77>; + }; + + cnn_sram_dce: cnn_sram_dce { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "cnn_sram_dce"; + }; + + ipe_sram_cpu: ipe_sram_cpu { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "ipe_sram_cpu"; + phandle = <0x78>; + }; + + ipe_sram_ipe: ipe_sram_ipe { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "ipe_sram_ipe"; + phandle = <0x79>; + }; + + ime_sram_cpu: ime_sram_cpu { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "ime_sram_cpu"; + phandle = <0x7a>; + }; + + ime_sram_ime: ime_sram_ime { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "ime_sram_ime"; + phandle = <0x7b>; + }; + + sie3_sram_sie3: sie3_sram_sie3 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "sie3_sram_sie3"; + phandle = <0x61>; + }; + + sie3_sram_sie4: sie3_sram_sie4 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "sie3_sram_sie4"; + phandle = <0x62>; + }; + + osc_in: osc_in { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0xb71b00>; + clock-output-names = "osc_in"; + phandle = <0x58>; + }; + + osc_rtc: osc_rtc { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x8000>; + clock-output-names = "osc_rtc"; + phandle = <0x59>; + }; + + fix850m: fix850m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x32a9f880>; + clock-output-names = "fix850m"; + }; + + fix480m: fix480m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x1c9c3800>; + clock-output-names = "fix480m"; + phandle = <0x54>; + }; + + fix360m: fix360m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x15752a00>; + clock-output-names = "fix360m"; + }; + + fix320m: fix320m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x1312d000>; + clock-output-names = "fix320m"; + phandle = <0x5f>; + }; + + fix240m: fix240m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0xe4e1c00>; + clock-output-names = "fix240m"; + phandle = <0x57>; + }; + + fix196m: fix196m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0xbaeb900>; + clock-output-names = "fix196m"; + }; + + fix192m: fix192m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0xb71b000>; + clock-output-names = "fix192m"; + phandle = <0x63>; + }; + + fix160m: fix160m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x9896800>; + clock-output-names = "fix160m"; + phandle = <0x81>; + }; + + fix150m: fix150m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x8f0d180>; + clock-output-names = "fix150m"; + }; + + fix120m: fix120m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x7270e00>; + clock-output-names = "fix120m"; + phandle = <0x66>; + }; + + fix96m: fix96m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x5b8d800>; + clock-output-names = "fix96m"; + phandle = <0x5d>; + }; + + fix80m: fix80m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x4c4b400>; + clock-output-names = "fix80m"; + phandle = <0x55>; + }; + + fix60m: fix60m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x3938700>; + clock-output-names = "fix60m"; + phandle = <0x86>; + }; + + fix48m: fix48m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x2dc6c00>; + clock-output-names = "fix48m"; + phandle = <0x5a>; + }; + + fix30m: fix30m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x1c9c380>; + clock-output-names = "fix30m"; + phandle = <0x5b>; + }; + + fix24m: fix24m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x16e3600>; + clock-output-names = "fix24m"; + }; + + fix16m: fix16m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0xf42400>; + clock-output-names = "fix16m"; + phandle = <0x5e>; + }; + + fix12m: fix12m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0xb71b00>; + clock-output-names = "fix12m"; + phandle = <0x6d>; + }; + + fix3m: fix3m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x2dc6c0>; + clock-output-names = "fix3m"; + phandle = <0x65>; + }; + + fix32768: fix32768 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x8000>; + clock-output-names = "fix32768"; + phandle = <0x6b>; + }; + + fix32k: fix32k { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x7d00>; + clock-output-names = "fix32k"; + phandle = <0x6c>; + }; + + clk_nand_fac: clk_nand_fac { + #clock-cells = <0x00>; + compatible = "nvt,nvt-factor-clock"; + clocks = <&fix480m>; + clock-div = <0x02>; + clock-mult = <0x01>; + phandle = <0x7c>; + }; + + clkout_normal: clkout_normal { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "clkout_normal"; + phandle = <0x83>; + }; + + clkout_invert: clkout_invert { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "clkout_invert"; + phandle = <0x84>; + }; + + siex_pxclkpad1: siex_pxclkpad1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "siex_pxclkpad1"; + phandle = <0x89>; + }; + + siex_pxclkpad2: siex_pxclkpad2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "siex_pxclkpad2"; + phandle = <0x8a>; + }; + + siex_intclk0: siex_intclk0 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "siex_intclk0"; + phandle = <0x87>; + }; + + siex_intclk1: siex_intclk1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "siex_intclk1"; + phandle = <0x88>; + }; + + tge_clksrc: tge_clksrc { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "tge_clksrc"; + phandle = <0x85>; + }; + + csi_hsclk: csi_hsclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "csi_hsclk"; + phandle = <0x67>; + }; + + cpu_clk: cpu_clk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix80m>, <&pll8>, <&fix480m>, <&fix240m>; + current_rate = <0x2faf0800>; + parent_idx = <0x01>; + mux_reg_offset = <0x10>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x02>; + clock-output-names = "cpu_clk"; + keep_rate = <0x01>; + }; + + pll3: pll3 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-pll"; + clocks = <&osc_in>; + default_value = <0x20000>; + pll_ratio = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x03>; + rate_reg_offset = <0x4460>; + rate_bit_idx = <0x00>; + rate_bit_width = <0x08>; + clock-output-names = "pll3"; + }; + + pll5: pll5 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-pll"; + clocks = <&osc_in>; + default_value = <0x20000>; + pll_ratio = <0x280000>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x05>; + rate_reg_offset = <0x4560>; + rate_bit_idx = <0x00>; + rate_bit_width = <0x08>; + clock-output-names = "pll5"; + phandle = <0x82>; + }; + + pll6: pll6 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-pll"; + clocks = <&osc_in>; + default_value = <0x20000>; + pll_ratio = <0x320000>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x06>; + rate_reg_offset = <0x44e0>; + rate_bit_idx = <0x00>; + rate_bit_width = <0x08>; + clock-output-names = "pll6"; + phandle = <0x6e>; + }; + + pll7: pll7 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-pll"; + clocks = <&osc_in>; + default_value = <0x20000>; + pll_ratio = <0x3d70a4>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x07>; + rate_reg_offset = <0x45e0>; + rate_bit_idx = <0x00>; + rate_bit_width = <0x08>; + clock-output-names = "pll7"; + phandle = <0x7d>; + }; + + pll8: pll8 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-pll"; + clocks = <&osc_in>; + default_value = <0x20000>; + pll_ratio = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x08>; + rate_reg_offset = <0x4420>; + rate_bit_idx = <0x00>; + rate_bit_width = <0x08>; + clock-output-names = "pll8"; + phandle = <0x56>; + }; + + pll9: pll9 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-pll"; + clocks = <&osc_in>; + default_value = <0x20000>; + pll_ratio = <0x640000>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x09>; + rate_reg_offset = <0x4520>; + rate_bit_idx = <0x00>; + rate_bit_width = <0x08>; + clock-output-names = "pll9"; + phandle = <0x64>; + }; + + pll11: pll11 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-pll"; + clocks = <&osc_in>; + default_value = <0x20000>; + pll_ratio = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x0b>; + rate_reg_offset = <0x44a0>; + rate_bit_idx = <0x00>; + rate_bit_width = <0x08>; + clock-output-names = "pll11"; + phandle = <0x68>; + }; + + pll12: pll12 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-pll"; + clocks = <&osc_in>; + default_value = <0x20000>; + pll_ratio = <0x42aaaa>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x0c>; + rate_reg_offset = <0x45a0>; + rate_bit_idx = <0x00>; + rate_bit_width = <0x08>; + clock-output-names = "pll12"; + phandle = <0x69>; + }; + + pll13: pll13 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-pll"; + clocks = <&osc_in>; + default_value = <0x20000>; + pll_ratio = <0x500000>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x0d>; + rate_reg_offset = <0x4620>; + rate_bit_idx = <0x00>; + rate_bit_width = <0x08>; + clock-output-names = "pll13"; + phandle = <0x6a>; + }; + + prfll: prfll { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&osc_rtc>, <&osc_in>; + parent_idx = <0x01>; + current_rate = <0x00>; + gate_reg_offset = <0x110>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x8c>; + reset_bit_idx = <0x06>; + do_reset = <0x00>; + clock-output-names = "prfll"; + phandle = <0x4f>; + }; + + clk_uart0: clk_uart0 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix48m>, <&fix30m>; + current_rate = <0x2dc6c00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x0a>; + do_enable = <0x01>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x0a>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0290000.uart"; + max_rate = <0x2dc6c00>; + phandle = <0x05>; + }; + + clk_uart1: clk_uart1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix48m>, <&fix30m>, <&prfll>; + current_rate = <0x2dc6c00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x0b>; + do_enable = <0x01>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x0b>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0300000.uart"; + max_rate = <0x2dc6c00>; + phandle = <0x06>; + }; + + clk_uart2: clk_uart2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix48m>, <&fix30m>, <&prfll>; + current_rate = <0x2dc6c00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x16>; + do_enable = <0x01>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x16>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0310000.uart"; + max_rate = <0x2dc6c00>; + phandle = <0x07>; + }; + + uart_pclk: uart_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x1c>; + do_autogating = <0x01>; + clock-output-names = "uart_pclk"; + }; + + uart2_pclk: uart2_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x1d>; + do_autogating = <0x01>; + clock-output-names = "uart2_pclk"; + }; + + uart3_pclk: uart3_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x10>; + do_autogating = <0x01>; + clock-output-names = "uart3_pclk"; + }; + + pre_pclk: pre_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc8>; + autogating_bit_idx = <0x0c>; + do_autogating = <0x01>; + clock-output-names = "pre_pclk"; + }; + + dne_pclk: dne_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc8>; + autogating_bit_idx = <0x08>; + do_autogating = <0x01>; + clock-output-names = "dne_pclk"; + }; + + ife_pclk: ife_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x07>; + do_autogating = <0x01>; + clock-output-names = "ife_pclk"; + }; + + dce_pclk: dce_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&osc_in>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "dce_pclk"; + }; + + ipe_pclk: ipe_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x02>; + do_autogating = <0x01>; + clock-output-names = "ipe_pclk"; + }; + + ime_pclk: ime_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x03>; + do_autogating = <0x01>; + clock-output-names = "ime_pclk"; + }; + + pre_bnr_clk_en: pre_bnr_clk_en { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x1e>; + do_autogating = <0x01>; + clock-output-names = "pre_bnr_clk_en"; + }; + + ife_2dnr_clk_en: ife_2dnr_clk_en { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x1e>; + do_autogating = <0x01>; + clock-output-names = "ife_2dnr_clk_en"; + }; + + ife_wdr_clk_en: ife_wdr_clk_en { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x1f>; + do_autogating = <0x01>; + clock-output-names = "ife_wdr_clk_en"; + }; + + ime_nr_pclk: ime_nr_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x04>; + do_autogating = <0x01>; + clock-output-names = "ime_nr_pclk"; + }; + + ime_lca_pclk: ime_lca_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x05>; + do_autogating = <0x01>; + clock-output-names = "ime_lca_pclk"; + }; + + ime_h264_pclk: ime_h264_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x06>; + do_autogating = <0x01>; + clock-output-names = "ime_h264_pclk"; + }; + + clk_sif: clk_sif { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix96m>; + current_rate = <0x5b8d800>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x09>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x09>; + do_reset = <0x00>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x1b>; + do_autogating = <0x01>; + clock-output-names = "f0240000.sif"; + max_rate = <0x5b8d800>; + phandle = <0x38>; + }; + + sif_pclk: sif_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x1c>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x1b>; + do_autogating = <0x01>; + clock-output-names = "sif_pclk"; + }; + + clk_adc: clk_adc { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix16m>, <&osc_rtc>; + current_rate = <0xf42400>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x10>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x15>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f01d0000.adc"; + max_rate = <0xf42400>; + phandle = <0x17>; + }; + + adc_pclk: adc_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x0f>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x0f>; + do_autogating = <0x00>; + clock-output-names = "adc_pclk"; + }; + + clk_thmal: clk_thmal { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&osc_in>; + current_rate = <0xb71b00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x0d>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x0d>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0260000.thmal"; + max_rate = <0xb71b00>; + phandle = <0x37>; + }; + + thmal_pclk: thmal_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x18>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x1f>; + do_autogating = <0x01>; + clock-output-names = "thmal_pclk"; + }; + + wdt_pclk: wdt_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x00>; + clock-output-names = "wdt_pclk"; + }; + + gpio_pclk: gpio_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x19>; + do_reset = <0x00>; + autogating_reg_offset = <0xc8>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "gpio_pclk"; + }; + + prspi_pclk: prspi_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x1c>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x1c>; + do_autogating = <0x00>; + clock-output-names = "prspi_pclk"; + }; + + prwg_pclk: prwg_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x0c>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x0c>; + do_autogating = <0x00>; + clock-output-names = "prwg_pclk"; + }; + + clk_spi0: clk_spi0 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix96m>; + current_rate = <0xb71b00>; + div_reg_offset = <0x44>; + div_bit_idx = <0x00>; + div_bit_width = <0x0b>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x06>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x06>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x18>; + do_autogating = <0x01>; + clock-output-names = "f0230000.spi"; + max_rate = <0x2dc6c00>; + phandle = <0x46>; + }; + + clk_spi1: clk_spi1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix96m>; + current_rate = <0xb71b00>; + div_reg_offset = <0x44>; + div_bit_idx = <0x10>; + div_bit_width = <0x0b>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x07>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x07>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x19>; + do_autogating = <0x01>; + clock-output-names = "f0320000.spi"; + max_rate = <0x2dc6c00>; + phandle = <0x47>; + }; + + clk_spi2: clk_spi2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix96m>; + current_rate = <0xb71b00>; + div_reg_offset = <0x48>; + div_bit_idx = <0x00>; + div_bit_width = <0x0b>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x08>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x08>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x1a>; + do_autogating = <0x01>; + clock-output-names = "f0340000.spi"; + max_rate = <0x2dc6c00>; + phandle = <0x48>; + }; + + spi0_pclk: spi0_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x1d>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x18>; + do_autogating = <0x01>; + clock-output-names = "spi0_pclk"; + }; + + spi1_pclk: spi1_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x1e>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x19>; + do_autogating = <0x01>; + clock-output-names = "spi1_pclk"; + }; + + spi2_pclk: spi2_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x1f>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x1a>; + do_autogating = <0x01>; + clock-output-names = "spi2_pclk"; + }; + + clk_sdp: clk_sdp { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix96m>; + current_rate = <0x5b8d800>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x10>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x14>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0390000.sdp"; + max_rate = <0x5b8d800>; + phandle = <0x49>; + }; + + sdp_pclk: sdp_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x1b>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc8>; + autogating_bit_idx = <0x07>; + do_autogating = <0x01>; + clock-output-names = "sdp_pclk"; + }; + + clk_tse: clk_tse { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&reserved>, <&reserved>; + current_rate = <0x1312d000>; + parent_idx = <0x01>; + mux_reg_offset = <0x24>; + mux_bit_idx = <0x04>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x0d>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x0d>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x19>; + do_autogating = <0x01>; + clock-output-names = "f0650000.tse"; + max_rate = <0x1312d000>; + phandle = <0x4a>; + }; + + tse_pclk: tse_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe4>; + gate_bit_idx = <0x0c>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x19>; + do_autogating = <0x01>; + clock-output-names = "tse_pclk"; + }; + + nue_pclk: nue_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe4>; + gate_bit_idx = <0x15>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x01>; + clock-output-names = "nue_pclk"; + }; + + nue2_pclk: nue2_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe4>; + gate_bit_idx = <0x16>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x0c>; + do_autogating = <0x01>; + clock-output-names = "nue2_pclk"; + }; + + cnn_pclk: cnn_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe4>; + gate_bit_idx = <0x19>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x01>; + do_autogating = <0x01>; + clock-output-names = "cnn_pclk"; + }; + + ise_pclk: ise_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x08>; + do_autogating = <0x01>; + clock-output-names = "ise_pclk"; + }; + + vpe_pclk: vpe_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x13>; + do_autogating = <0x01>; + clock-output-names = "vpe_pclk"; + }; + + tge_pclk: tge_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe4>; + gate_bit_idx = <0x12>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x14>; + do_autogating = <0x00>; + clock-output-names = "tge_pclk"; + phandle = <0x2c>; + }; + + sie1_pclk: sie1_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe4>; + gate_bit_idx = <0x0f>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sie1_pclk"; + phandle = <0x1d>; + }; + + sie2_pclk: sie2_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe4>; + gate_bit_idx = <0x10>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x09>; + do_autogating = <0x00>; + clock-output-names = "sie2_pclk"; + phandle = <0x1e>; + }; + + sie3_pclk: sie3_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe4>; + gate_bit_idx = <0x11>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x0a>; + do_autogating = <0x00>; + clock-output-names = "sie3_pclk"; + phandle = <0x1f>; + }; + + sie4_pclk: sie4_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe8>; + gate_bit_idx = <0x0f>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc8>; + autogating_bit_idx = <0x12>; + do_autogating = <0x00>; + clock-output-names = "sie4_pclk"; + phandle = <0x20>; + }; + + sie3_share_sram: sie3_share_sram { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&sie3_sram_sie3>, <&sie3_sram_sie4>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x0e>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sie3_share_sram"; + }; + + clk_mmc0: clk_mmc0 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&fix192m>, <&fix320m>, <&pll9>; + current_rate = <0x4c4b4>; + parent_idx = <0x01>; + mux_reg_offset = <0x20>; + mux_bit_idx = <0x04>; + mux_bit_width = <0x02>; + div_reg_offset = <0x3c>; + div_bit_idx = <0x00>; + div_bit_width = <0x0b>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x02>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x02>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x14>; + do_autogating = <0x00>; + clock-output-names = "f0420000.mmc"; + max_rate = <0x5b8d800>; + phandle = <0x08>; + }; + + clk_mmc1: clk_mmc1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&fix192m>, <&fix320m>, <&pll9>; + current_rate = <0x4c4b4>; + parent_idx = <0x01>; + mux_reg_offset = <0x20>; + mux_bit_idx = <0x08>; + mux_bit_width = <0x02>; + div_reg_offset = <0x3c>; + div_bit_idx = <0x10>; + div_bit_width = <0x0b>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x03>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x03>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x15>; + do_autogating = <0x00>; + clock-output-names = "f0500000.mmc"; + max_rate = <0x5b8d800>; + }; + + clk_mmc2: clk_mmc2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&fix192m>, <&fix320m>, <&pll9>; + current_rate = <0x4c4b4>; + parent_idx = <0x00>; + mux_reg_offset = <0x24>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x02>; + div_reg_offset = <0x40>; + div_bit_idx = <0x00>; + div_bit_width = <0x0b>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x0e>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x0e>; + do_reset = <0x01>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0f>; + do_autogating = <0x00>; + clock-output-names = "f0510000.mmc"; + max_rate = <0x9896800>; + }; + + clk_timer: clk_timer { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix3m>; + current_rate = <0x2dc6c0>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x12>; + do_enable = <0x01>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x12>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x00>; + do_autogating = <0x01>; + clock-output-names = "f0040000.timer"; + }; + + clk_i2c: clk_i2c { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix48m>; + current_rate = <0x2dc6c00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x04>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x04>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0220000.i2c"; + max_rate = <0x2dc6c00>; + phandle = <0x51>; + }; + + clk_i2c2: clk_i2c2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix48m>; + current_rate = <0x2dc6c00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x05>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x05>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0350000.i2c2"; + max_rate = <0x2dc6c00>; + phandle = <0x52>; + }; + + clk_i2c3: clk_i2c3 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix48m>; + current_rate = <0x2dc6c00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x0f>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x14>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0360000.i2c3"; + max_rate = <0x2dc6c00>; + phandle = <0x53>; + }; + + i2c_pclk: i2c_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x16>; + do_autogating = <0x01>; + clock-output-names = "i2c_pclk"; + }; + + i2c2_pclk: i2c2_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x17>; + do_autogating = <0x01>; + clock-output-names = "i2c2_pclk"; + }; + + i2c3_pclk: i2c3_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x07>; + do_autogating = <0x01>; + clock-output-names = "i2c3_pclk"; + }; + + pri2c_pclk: pri2c_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "pri2c_pclk"; + }; + + clk_hrtimer1: clk_hrtimer1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>; + current_rate = <0x7270e00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x0e>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x03>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x01>; + do_autogating = <0x01>; + phandle = <0x3b>; + }; + + clk_hrtimer2: clk_hrtimer2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>; + current_rate = <0x7270e00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x0f>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x04>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x02>; + do_autogating = <0x01>; + phandle = <0x3c>; + }; + + clk_hrtimer3: clk_hrtimer3 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>; + current_rate = <0x7270e00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x10>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x05>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x03>; + do_autogating = <0x01>; + phandle = <0x3d>; + }; + + clk_hrtimer4: clk_hrtimer4 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>; + current_rate = <0x7270e00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x11>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x06>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x04>; + do_autogating = <0x01>; + phandle = <0x3e>; + }; + + clk_hrtimer5: clk_hrtimer5 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>; + current_rate = <0x7270e00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x12>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x07>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x05>; + do_autogating = <0x01>; + phandle = <0x3f>; + }; + + clk_hrtimer6: clk_hrtimer6 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>; + current_rate = <0x7270e00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x13>; + do_enable = <0x00>; + reset_reg_offset = <0x8c>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0c>; + do_autogating = <0x01>; + phandle = <0x40>; + }; + + clk_hrtimer7: clk_hrtimer7 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>; + current_rate = <0x7270e00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x14>; + do_enable = <0x00>; + reset_reg_offset = <0x8c>; + reset_bit_idx = <0x09>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0d>; + do_autogating = <0x01>; + phandle = <0x41>; + }; + + clk_hrtimer8: clk_hrtimer8 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>; + current_rate = <0x7270e00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x15>; + do_enable = <0x00>; + reset_reg_offset = <0x8c>; + reset_bit_idx = <0x0a>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0e>; + do_autogating = <0x01>; + phandle = <0x42>; + }; + + clk_hrtimer9: clk_hrtimer9 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x7270e00>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x0f>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x13>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x17>; + do_reset = <0x00>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x1c>; + do_autogating = <0x01>; + phandle = <0x43>; + }; + + clk_hrtimer10: clk_hrtimer10 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x7270e00>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x10>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x14>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x18>; + do_reset = <0x00>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x1d>; + do_autogating = <0x01>; + }; + + hrtimer1_pclk: hrtimer1_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x01>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x0c>; + do_autogating = <0x00>; + clock-output-names = "hrtimer1_pclk"; + }; + + hrtimer2_pclk: hrtimer2_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x02>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x0d>; + do_autogating = <0x00>; + clock-output-names = "hrtimer2_pclk"; + }; + + hrtimer3_pclk: hrtimer3_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x03>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x0e>; + do_autogating = <0x00>; + clock-output-names = "hrtimer3_pclk"; + }; + + hrtimer4_pclk: hrtimer4_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x04>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x11>; + do_autogating = <0x00>; + clock-output-names = "hrtimer4_pclk"; + }; + + hrtimer5_pclk: hrtimer5_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe0>; + gate_bit_idx = <0x05>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x12>; + do_autogating = <0x00>; + clock-output-names = "hrtimer5_pclk"; + }; + + hrtimer6_pclk: hrtimer6_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe8>; + gate_bit_idx = <0x09>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc8>; + autogating_bit_idx = <0x0f>; + do_autogating = <0x00>; + clock-output-names = "hrtimer6_pclk"; + }; + + hrtimer7_pclk: hrtimer7_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe8>; + gate_bit_idx = <0x0a>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc8>; + autogating_bit_idx = <0x10>; + do_autogating = <0x00>; + clock-output-names = "hrtimer7_pclk"; + }; + + hrtimer8_pclk: hrtimer8_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe8>; + gate_bit_idx = <0x0b>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc8>; + autogating_bit_idx = <0x11>; + do_autogating = <0x00>; + clock-output-names = "hrtimer8_pclk"; + }; + + hrtimer9_pclk: hrtimer9_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe8>; + gate_bit_idx = <0x0c>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x05>; + do_autogating = <0x00>; + clock-output-names = "hrtimer9_pclk"; + }; + + csi_ck0d4: csi_ck0d4 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&csi_hsclk>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x1d>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "csi_ck0d4"; + }; + + csi_ck1d4: csi_ck1d4 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&csi_hsclk>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x1e>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "csi_ck1d4"; + }; + + csi2_ck1d4: csi2_ck1d4 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&osc_in>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x1f>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "csi2_ck1d4"; + }; + + clk_pre: clk_pre { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&pll11>, <&pll12>, <&pll13>, <&fix480m>, <&fix96m>, <&reserved>; + current_rate = <0x17d78400>; + parent_idx = <0x03>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x03>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x12>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x0c>; + do_reset = <0x01>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x1d>; + do_autogating = <0x01>; + clock-output-names = "f0c71000.pre"; + max_rate = <0x17d78400>; + }; + + clk_dne: clk_dne { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&pll11>, <&pll12>, <&pll13>, <&fix480m>, <&fix96m>, <&reserved>; + current_rate = <0x17d78400>; + parent_idx = <0x03>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x14>; + mux_bit_width = <0x03>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x13>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x12>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0ca0000.dne"; + max_rate = <0x17d78400>; + }; + + clk_ife: clk_ife { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&pll11>, <&pll12>, <&pll13>, <&fix480m>, <&fix96m>, <&reserved>; + current_rate = <0x17d78400>; + parent_idx = <0x03>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x04>; + mux_bit_width = <0x03>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x0d>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x0d>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x07>; + do_autogating = <0x01>; + clock-output-names = "f0c70000.ife"; + max_rate = <0x17d78400>; + phandle = <0x30>; + }; + + clk_ipe: clk_ipe { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&pll11>, <&pll12>, <&pll13>, <&fix480m>, <&fix96m>, <&reserved>; + current_rate = <0x17d78400>; + parent_idx = <0x03>; + mux_reg_offset = <0x14>; + mux_bit_idx = <0x04>; + mux_bit_width = <0x03>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x07>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x07>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x02>; + do_autogating = <0x01>; + clock-output-names = "f0c30000.ipe"; + max_rate = <0x17d78400>; + phandle = <0x2f>; + }; + + clk_ime: clk_ime { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&pll11>, <&pll12>, <&pll13>, <&fix480m>, <&fix96m>, <&reserved>; + current_rate = <0x17d78400>; + parent_idx = <0x03>; + mux_reg_offset = <0x14>; + mux_bit_idx = <0x0c>; + mux_bit_width = <0x03>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x09>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x09>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x03>; + do_autogating = <0x01>; + clock-output-names = "f0c40000.ime"; + max_rate = <0x17d78400>; + phandle = <0x2d>; + }; + + clk_ise: clk_ise { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&fix240m>, <&fix320m>; + current_rate = <0x1c9c3800>; + parent_idx = <0x00>; + mux_reg_offset = <0x14>; + mux_bit_idx = <0x18>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x0b>; + do_enable = <0x01>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x0b>; + do_reset = <0x01>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x08>; + do_autogating = <0x01>; + clock-output-names = "f0c90000.ise"; + max_rate = <0x1c9c3800>; + phandle = <0x2e>; + }; + + remote_pclk: remote_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x1e>; + do_autogating = <0x01>; + clock-output-names = "remote_pclk"; + }; + + remote_clk: remote_clk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix32768>, <&fix32k>, <&reserved>, <&fix3m>; + current_rate = <0x7d00>; + parent_idx = <0x01>; + mux_reg_offset = <0x24>; + mux_bit_idx = <0x15>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x0c>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x0c>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "remote_clk"; + max_rate = <0x2dc6c0>; + phandle = <0x4b>; + }; + + clk_wdt: clk_wdt { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&osc_in>, <&prfll>; + parent_idx = <0x00>; + current_rate = <0xb71b00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x18>; + mux_bit_width = <0x01>; + div_reg_offset = <0x64>; + div_bit_idx = <0x14>; + div_bit_width = <0x02>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x13>; + do_enable = <0x01>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0050000.wdt"; + phandle = <0x0a>; + }; + + clk_cfe: clk_cfe { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&osc_in>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x14>; + do_enable = <0x01>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x15>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "cfe_clk"; + phandle = <0x4e>; + }; + + clk_uvcp: clk_uvcp { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&fix120m>; + current_rate = <0xe4e1c00>; + parent_idx = <0x00>; + mux_reg_offset = <0x1c>; + mux_bit_idx = <0x0e>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x15>; + do_enable = <0x01>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x15>; + do_reset = <0x01>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x1e>; + do_autogating = <0x00>; + clock-output-names = "f0690000.uvcp"; + max_rate = <0x1312d000>; + phandle = <0x4d>; + }; + + clk_usb20: clk_usb20 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix12m>; + current_rate = <0x1c9c380>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x13>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "u2ctrl"; + phandle = <0x45>; + }; + + clk_u2phy: clk_u2phy { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix12m>; + current_rate = <0xb71b00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x13>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "u2phy"; + }; + + clk_rtc: clk_rtc { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&osc_rtc>; + current_rate = <0x8000>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x10>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0060000.rtc"; + max_rate = <0x8000>; + }; + + clk_drtc: clk_drtc { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&osc_in>, <&osc_rtc>; + current_rate = <0xb71b00>; + parent_idx = <0x00>; + mux_reg_offset = <0x24>; + mux_bit_idx = <0x14>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x16>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x16>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f00b0000.drtc"; + max_rate = <0xb71b00>; + phandle = <0x18>; + }; + + drtc_pclk: drtc_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x02>; + do_autogating = <0x01>; + clock-output-names = "drtc_pclk"; + }; + + clk_grph: clk_grph { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&fix480m>; + current_rate = <0x1c9c3800>; + parent_idx = <0x02>; + mux_reg_offset = <0x1c>; + mux_bit_idx = <0x08>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x1b>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x1b>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x08>; + do_autogating = <0x01>; + clock-output-names = "f0c80000.grph"; + max_rate = <0x1c9c3800>; + phandle = <0x39>; + }; + + clk_grph2: clk_grph2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&fix480m>; + current_rate = <0x1c9c3800>; + parent_idx = <0x02>; + mux_reg_offset = <0x1c>; + mux_bit_idx = <0x0c>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x1c>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x1c>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x09>; + do_autogating = <0x01>; + clock-output-names = "f0d10000.grph"; + max_rate = <0x1c9c3800>; + phandle = <0x3a>; + }; + + grph_pclk: grph_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe4>; + gate_bit_idx = <0x1b>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x08>; + do_autogating = <0x00>; + clock-output-names = "grph_pclk"; + }; + + grph2_pclk: grph2_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0xe4>; + gate_bit_idx = <0x1c>; + do_enable = <0x01>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x09>; + do_autogating = <0x00>; + clock-output-names = "grph2_pclk"; + }; + + clk_vpe: clk_vpe { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&pll11>, <&pll12>, <&pll13>, <&fix480m>, <&reserved>, <&pll6>; + current_rate = <0x17d78400>; + parent_idx = <0x03>; + mux_reg_offset = <0x24>; + mux_bit_idx = <0x0c>; + mux_bit_width = <0x03>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x11>; + do_enable = <0x01>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x0e>; + do_reset = <0x01>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x1a>; + do_autogating = <0x01>; + clock-output-names = "f0cd0000.vpe"; + max_rate = <0x17d78400>; + phandle = <0x31>; + }; + + pwm_pclk: pwm_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "pwm_pclk"; + }; + + clk_pwm0: clk_pwm0 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x04>; + mux_bit_width = <0x01>; + div_reg_offset = <0x50>; + div_bit_idx = <0x00>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm0"; + max_rate = <0x1c9c380>; + phandle = <0x0b>; + }; + + clk_pwm1: clk_pwm1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x04>; + mux_bit_width = <0x01>; + div_reg_offset = <0x50>; + div_bit_idx = <0x00>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x01>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm1"; + max_rate = <0x1c9c380>; + phandle = <0x0c>; + }; + + clk_pwm2: clk_pwm2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x04>; + mux_bit_width = <0x01>; + div_reg_offset = <0x50>; + div_bit_idx = <0x00>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x02>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm2"; + max_rate = <0x1c9c380>; + phandle = <0x0d>; + }; + + clk_pwm3: clk_pwm3 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x04>; + mux_bit_width = <0x01>; + div_reg_offset = <0x50>; + div_bit_idx = <0x00>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x03>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm3"; + max_rate = <0x1c9c380>; + phandle = <0x0e>; + }; + + clk_pwm4: clk_pwm4 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x05>; + mux_bit_width = <0x01>; + div_reg_offset = <0x50>; + div_bit_idx = <0x10>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x04>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm4"; + max_rate = <0x1c9c380>; + phandle = <0x0f>; + }; + + clk_pwm5: clk_pwm5 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x05>; + mux_bit_width = <0x01>; + div_reg_offset = <0x50>; + div_bit_idx = <0x10>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x05>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm5"; + max_rate = <0x1c9c380>; + phandle = <0x10>; + }; + + clk_pwm6: clk_pwm6 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x05>; + mux_bit_width = <0x01>; + div_reg_offset = <0x50>; + div_bit_idx = <0x10>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x06>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm6"; + max_rate = <0x1c9c380>; + phandle = <0x11>; + }; + + clk_pwm7: clk_pwm7 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x05>; + mux_bit_width = <0x01>; + div_reg_offset = <0x50>; + div_bit_idx = <0x10>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x07>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm7"; + max_rate = <0x1c9c380>; + phandle = <0x12>; + }; + + clk_pwm8: clk_pwm8 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x06>; + mux_bit_width = <0x01>; + div_reg_offset = <0x54>; + div_bit_idx = <0x00>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x08>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm8"; + max_rate = <0x1c9c380>; + phandle = <0x13>; + }; + + clk_pwm9: clk_pwm9 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x07>; + mux_bit_width = <0x01>; + div_reg_offset = <0x54>; + div_bit_idx = <0x10>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x09>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm9"; + max_rate = <0x1c9c380>; + phandle = <0x14>; + }; + + clk_pwm10: clk_pwm10 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x08>; + mux_bit_width = <0x01>; + div_reg_offset = <0x58>; + div_bit_idx = <0x00>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x0a>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm10"; + max_rate = <0x1c9c380>; + phandle = <0x15>; + }; + + clk_pwm11: clk_pwm11 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix120m>, <&prfll>; + current_rate = <0x1c9c380>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x09>; + mux_bit_width = <0x01>; + div_reg_offset = <0x58>; + div_bit_idx = <0x10>; + div_bit_width = <0x0e>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x0b>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.pwm11"; + max_rate = <0x1c9c380>; + phandle = <0x16>; + }; + + clk_ccnt0: clk_ccnt0 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix3m>; + current_rate = <0x2dc6c0>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x08>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.ccnt0"; + max_rate = <0x2dc6c0>; + }; + + clk_ccnt1: clk_ccnt1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix3m>; + current_rate = <0x2dc6c0>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x09>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.ccnt1"; + max_rate = <0x2dc6c0>; + }; + + clk_ccnt2: clk_ccnt2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&fix3m>; + current_rate = <0x2dc6c0>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x0a>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x08>; + do_reset = <0x00>; + autogating_shared = <&clk_pwm0>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x0b>; + do_autogating = <0x01>; + clock-output-names = "f0210000.ccnt2"; + max_rate = <0x2dc6c0>; + }; + + pre_shared_sram: pre_shared_sram { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&pre_sram_cpu>, <&pre_sram_pre>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x1c>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "pre_shared_sram"; + }; + + p_f_shared_sram: p_f_shared_sram { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&preife_sram_ife>, <&preife_sram_pre>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x1d>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "p_f_shared_sram"; + }; + + dne_shared_sram: dne_shared_sram { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&dne_sram_cpu>, <&dne_sram_ime>, <&dne_sram_dne>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "dne_shared_sram"; + }; + + ife_shared_sram: ife_shared_sram { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&ife_sram_cpu>, <&ife_sram_ife>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x1a>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "ife_shared_sram"; + }; + + ipe_shared_sram: ipe_shared_sram { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&ipe_sram_cpu>, <&ipe_sram_ipe>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x02>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "ipe_shared_sram"; + }; + + ime_shared_sram: ime_shared_sram { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&ime_sram_cpu>, <&ime_sram_ime>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x03>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "ime_shared_sram"; + }; + + clk_nand: clk_nand { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&clk_nand_fac>; + current_rate = <0x2dc6c00>; + div_reg_offset = <0x40>; + div_bit_idx = <0x0c>; + div_bit_width = <0x06>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x13>; + do_autogating = <0x01>; + clock-output-names = "f0400000.nand"; + max_rate = <0x9896800>; + phandle = <0x09>; + }; + + nand_pclk: nand_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x13>; + do_autogating = <0x01>; + clock-output-names = "nand_pclk"; + }; + + clk_gzip: clk_gzip { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&fix480m>, <&reserved>; + current_rate = <0x1c9c3800>; + parent_idx = <0x02>; + mux_reg_offset = <0x28>; + mux_bit_idx = <0x0c>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x0b>; + do_enable = <0x00>; + reset_reg_offset = <0x8c>; + reset_bit_idx = <0x07>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x1f>; + do_autogating = <0x01>; + clock-output-names = "clk_gzip"; + max_rate = <0x1c9c3800>; + phandle = <0x4c>; + }; + + clk_gli_mux: clk_gli_mux { + #clock-cells = <0x00>; + clocks = <&prfll>; + compatible = "nvt,nvt-clk-gate"; + gate_reg_offset = <0x120>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + clock-output-names = "clk_gli_mux"; + }; + + fll_aud_m: fll_aud_m { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&prfll>; + parent_idx = <0x00>; + current_rate = <0xbb8000>; + div_reg_offset = <0x130>; + div_bit_idx = <0x00>; + div_bit_width = <0x11>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + clock-output-names = "fll_aud_m"; + phandle = <0x7e>; + }; + + clk_eacdac: clk_eacdac { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&pll7>, <&fll_aud_m>; + current_rate = <0xbb8000>; + parent_idx = <0x00>; + mux_reg_offset = <0x28>; + mux_bit_idx = <0x18>; + mux_bit_width = <0x01>; + div_reg_offset = <0x38>; + div_bit_idx = <0x18>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x1f>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x1e>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "clk_eacdac"; + max_rate = <0xbb8000>; + phandle = <0x7f>; + }; + + clk_eacadc: clk_eacadc { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&clk_eacdac>; + current_rate = <0xbb8000>; + parent_idx = <0x00>; + mux_reg_offset = <0x00>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x1e>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "clk_eacadc"; + max_rate = <0xbb8000>; + }; + + clk_eac: clk_eac { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&clk_eacdac>; + current_rate = <0xbb8000>; + parent_idx = <0x00>; + mux_reg_offset = <0x00>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x14>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x1e>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "clk_eac"; + max_rate = <0xbb8000>; + }; + + clk_cypt: clk_crpt { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix320m>, <&fix240m>, <&pll6>; + current_rate = <0x1312d000>; + parent_idx = <0x00>; + mux_reg_offset = <0x1c>; + mux_bit_idx = <0x14>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x17>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x17>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0620000.cypt"; + max_rate = <0x1312d000>; + }; + + clk_hash: clk_hash { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix320m>, <&fix240m>, <&pll6>; + current_rate = <0x1312d000>; + parent_idx = <0x00>; + mux_reg_offset = <0x24>; + mux_bit_idx = <0x10>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x1b>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x1b>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0670000.hash"; + max_rate = <0x1312d000>; + }; + + clk_rsa: clk_rsa { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix320m>, <&fix240m>, <&pll6>; + current_rate = <0x1312d000>; + parent_idx = <0x00>; + mux_reg_offset = <0x1c>; + mux_bit_idx = <0x16>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x1a>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x1a>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f06a0000.rsa"; + max_rate = <0x1312d000>; + }; + + crypto_pclk: crypto_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x16>; + do_autogating = <0x00>; + clock-output-names = "crypto_pclk"; + }; + + hash_pclk: hash_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x1a>; + do_autogating = <0x00>; + clock-output-names = "hash_pclk"; + }; + + rsa_pclk: rsa_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x17>; + do_autogating = <0x00>; + clock-output-names = "rsa_pclk"; + }; + + ecdsa_pclk: ecdsa_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x15>; + do_autogating = <0x00>; + clock-output-names = "ecdsa_pclk"; + }; + + jpeg1_clk: jpeg1_clk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix120m>, <&fix320m>, <&fix480m>; + current_rate = <0x1c9c3800>; + parent_idx = <0x02>; + mux_reg_offset = <0x1c>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x1a>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x1a>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x0f>; + do_autogating = <0x00>; + clock-output-names = "jpeg1_clk"; + max_rate = <0x1c9c3800>; + phandle = <0x44>; + }; + + dai_pclk: dai_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x11>; + do_autogating = <0x01>; + clock-output-names = "dai_pclk"; + }; + + clk_dai: clk_dai { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&clk_eacdac>; + current_rate = <0xbb8000>; + parent_idx = <0x00>; + mux_reg_offset = <0x00>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x00>; + div_reg_offset = <0x38>; + div_bit_idx = <0x10>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x1d>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x1d>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "clk_dai"; + max_rate = <0xea6000>; + phandle = <0x80>; + }; + + dai_mclk: dai_mclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&clk_dai>, <&pll12>; + current_rate = <0xbb8000>; + parent_idx = <0x01>; + mux_reg_offset = <0x20>; + mux_bit_idx = <0x16>; + mux_bit_width = <0x01>; + div_reg_offset = <0x60>; + div_bit_idx = <0x18>; + div_bit_width = <0x08>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "dai_mclk"; + max_rate = <0x1770000>; + }; + + prdai_pclk: prdai_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x1d>; + do_autogating = <0x01>; + clock-output-names = "prdai_pclk"; + }; + + clk_rng: clk_rng { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix160m>, <&fix240m>; + current_rate = <0x9896800>; + parent_idx = <0x00>; + mux_reg_offset = <0x00>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x00>; + div_reg_offset = <0x34>; + div_bit_idx = <0x18>; + div_bit_width = <0x08>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x19>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x19>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0680000.rng"; + }; + + clk_rngro: clk_rngro { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&osc_in>, <&pll9>; + current_rate = <0x16e3600>; + parent_idx = <0x00>; + mux_reg_offset = <0x00>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x00>; + div_reg_offset = <0x60>; + div_bit_idx = <0x00>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x15>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0680000.rngro"; + }; + + sn_mclk1: sn_mclk1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&pll5>, <&prfll>, <&pll12>; + current_rate = <0x7270e00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x08>; + mux_bit_width = <0x02>; + div_reg_offset = <0x30>; + div_bit_idx = <0x00>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x02>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sn_mclk1"; + max_rate = <0x8f0d180>; + phandle = <0x26>; + }; + + sn_mclk2: sn_mclk2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&pll5>, <&reserved>, <&pll12>; + current_rate = <0x7270e00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x0a>; + mux_bit_width = <0x02>; + div_reg_offset = <0x30>; + div_bit_idx = <0x08>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x03>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sn_mclk2"; + max_rate = <0x8f0d180>; + phandle = <0x27>; + }; + + sn_mclk3: sn_mclk3 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&pll5>, <&reserved>, <&pll12>; + current_rate = <0x7270e00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x0c>; + mux_bit_width = <0x02>; + div_reg_offset = <0x34>; + div_bit_idx = <0x10>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x0a>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sn_mclk3"; + max_rate = <0x8f0d180>; + phandle = <0x28>; + }; + + sn_mclk1out: sn_mclk1out { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&clkout_normal>, <&clkout_invert>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x13>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sn_mclk1out"; + }; + + sn_mclk2out: sn_mclk2out { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&clkout_normal>, <&clkout_invert>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x18>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sn_mclk2out"; + }; + + sn_mclk3out: sn_mclk3out { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&clkout_normal>, <&clkout_invert>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x19>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sn_mclk3out"; + }; + + clk_tge: clk_tge { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&tge_clksrc>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x00>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x06>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x06>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0cc0000.tge"; + phandle = <0x29>; + }; + + clk_tgeflashA: clk_tgeflashA { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&sn_mclk1>, <&sn_mclk2>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x14>; + mux_bit_idx = <0x10>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "clk_tgeflashA"; + phandle = <0x2a>; + }; + + clk_tgemshA: clk_tgemshA { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&sn_mclk1>, <&sn_mclk2>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x14>; + mux_bit_idx = <0x08>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "clk_tgemshA"; + phandle = <0x2b>; + }; + + clk_csi0: clk_csi0 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix60m>, <&fix120m>, <&fix240m>; + current_rate = <0x3938700>; + parent_idx = <0x00>; + mux_reg_offset = <0x20>; + mux_bit_idx = <0x0c>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x01>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x01>; + do_reset = <0x01>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x03>; + do_autogating = <0x01>; + clock-output-names = "f0280000.csi"; + phandle = <0x35>; + }; + + clk_csi1: clk_csi1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix60m>, <&fix120m>, <&fix240m>; + current_rate = <0x3938700>; + parent_idx = <0x00>; + mux_reg_offset = <0x20>; + mux_bit_idx = <0x0e>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x02>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x02>; + do_reset = <0x01>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x04>; + do_autogating = <0x01>; + clock-output-names = "f0330000.csi2"; + phandle = <0x36>; + }; + + clk_sie1: clk_sie1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&reserved>, <&pll5>, <&reserved>, <&pll12>, <&fix320m>, <&fix192m>, <&reserved>; + current_rate = <0x1312d000>; + parent_idx = <0x05>; + mux_reg_offset = <0x1c>; + mux_bit_idx = <0x18>; + mux_bit_width = <0x03>; + div_reg_offset = <0x30>; + div_bit_idx = <0x10>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x04>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x04>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x11>; + do_autogating = <0x00>; + clock-output-names = "f0c00000.sie1"; + max_rate = <0x17d78400>; + phandle = <0x19>; + }; + + clk_sie2: clk_sie2 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&reserved>, <&pll5>, <&reserved>, <&pll12>, <&fix320m>, <&fix192m>, <&reserved>; + current_rate = <0x1312d000>; + parent_idx = <0x05>; + mux_reg_offset = <0x1c>; + mux_bit_idx = <0x1c>; + mux_bit_width = <0x03>; + div_reg_offset = <0x30>; + div_bit_idx = <0x18>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x05>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x05>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x16>; + do_autogating = <0x00>; + clock-output-names = "f0d20000.sie2"; + max_rate = <0x17d78400>; + phandle = <0x1a>; + }; + + clk_sie3: clk_sie3 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&reserved>, <&pll5>, <&reserved>, <&pll12>, <&fix320m>, <&fix192m>, <&reserved>; + current_rate = <0x1312d000>; + parent_idx = <0x05>; + mux_reg_offset = <0x1c>; + mux_bit_idx = <0x10>; + mux_bit_width = <0x03>; + div_reg_offset = <0x38>; + div_bit_idx = <0x08>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x11>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x09>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x17>; + do_autogating = <0x00>; + clock-output-names = "f0d30000.sie3"; + max_rate = <0x17d78400>; + phandle = <0x1b>; + }; + + clk_sie4: clk_sie4 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&reserved>, <&pll5>, <&reserved>, <&pll12>, <&fix320m>, <&fix192m>, <&reserved>; + current_rate = <0x1312d000>; + parent_idx = <0x05>; + mux_reg_offset = <0x1c>; + mux_bit_idx = <0x10>; + mux_bit_width = <0x03>; + div_reg_offset = <0x38>; + div_bit_idx = <0x08>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x19>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x0a>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "f0d40000.sie4"; + max_rate = <0x17d78400>; + phandle = <0x1c>; + }; + + sie2_intclk: sie2_intclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&siex_intclk0>, <&siex_intclk1>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x1b>; + mux_bit_width = <0x01>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sie2_intclk"; + phandle = <0x25>; + }; + + sie1_pxclk: sie1_pxclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&siex_pxclkpad1>, <&reserved>, <&sn_mclk1>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x28>; + mux_bit_idx = <0x1c>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x04>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sie1_pxclk"; + phandle = <0x21>; + }; + + sie2_pxclk: sie2_pxclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&siex_pxclkpad1>, <&siex_pxclkpad2>, <&sn_mclk1>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x28>; + mux_bit_idx = <0x0e>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x05>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sie2_pxclk"; + phandle = <0x22>; + }; + + sie3_pxclk: sie3_pxclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&siex_pxclkpad1>, <&siex_pxclkpad2>, <&sn_mclk1>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x28>; + mux_bit_idx = <0x10>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x06>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sie3_pxclk"; + phandle = <0x23>; + }; + + sie4_pxclk: sie4_pxclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&siex_pxclkpad1>, <&siex_pxclkpad2>, <&sn_mclk1>; + current_rate = <0x00>; + parent_idx = <0x00>; + mux_reg_offset = <0x28>; + mux_bit_idx = <0x12>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x03>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "sie4_pxclk"; + phandle = <0x24>; + }; + + mmc0_pclk: mmc0_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x14>; + do_autogating = <0x00>; + clock-output-names = "mmc0_pclk"; + }; + + mmc1_pclk: mmc1_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x15>; + do_autogating = <0x00>; + clock-output-names = "mmc1_pclk"; + }; + + mmc2_pclk: mmc2_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x0f>; + do_autogating = <0x00>; + clock-output-names = "mmc2_pclk"; + }; + + eac_pclk: eac_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x12>; + do_autogating = <0x00>; + clock-output-names = "eac_pclk"; + }; + + clk_eth0: clk_eth0 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&pll6>; + current_rate = <0x11e1a300>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x74>; + gate_bit_idx = <0x1d>; + do_enable = <0x00>; + reset_reg_offset = <0x84>; + reset_bit_idx = <0x1d>; + do_reset = <0x00>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x1b>; + do_autogating = <0x01>; + clock-output-names = "f02b0000.eth0"; + max_rate = <0x11e1a300>; + }; + + eth0_extphy_clk: eth0_extphy_clk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&pll6>; + current_rate = <0x11e1a300>; + parent_idx = <0x00>; + mux_reg_offset = <0x24>; + mux_bit_idx = <0x1a>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x78>; + gate_bit_idx = <0x18>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "eth0_extphy_clk"; + max_rate = <0x11e1a300>; + }; + + clk_ide_src: clk_ide_src { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&pll6>, <&fix192m>, <&pll9>, <&pll11>; + current_rate = <0x8f0d180>; + parent_idx = <0x03>; + mux_reg_offset = <0x20>; + mux_bit_idx = <0x10>; + mux_bit_width = <0x03>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x01>; + clock-output-names = "ide_clk_src"; + phandle = <0x8b>; + }; + + clk_ide: clk_ide { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&clk_ide_src>; + current_rate = <0x8f0d180>; + parent_idx = <0x00>; + mux_reg_offset = <0x00>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x00>; + div_reg_offset = <0x34>; + div_bit_idx = <0x00>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x10>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x10>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x0a>; + do_autogating = <0x01>; + clock-output-names = "f0800000.ide"; + max_rate = <0x8f0d180>; + phandle = <0x34>; + }; + + clk_ideif: clk_ideif { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&clk_ide_src>; + current_rate = <0x8f0d180>; + parent_idx = <0x00>; + mux_reg_offset = <0x00>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x00>; + div_reg_offset = <0x34>; + div_bit_idx = <0x08>; + div_bit_width = <0x08>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x01>; + clock-output-names = "clk_ideif"; + max_rate = <0x8f0d180>; + }; + + clk_dsi: clk_dsi { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix60m>, <&fix80m>, <&fix120m>, <&pll11>; + current_rate = <0x3938700>; + parent_idx = <0x00>; + mux_reg_offset = <0x28>; + mux_bit_idx = <0x08>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x0e>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x0e>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x01>; + do_autogating = <0x01>; + clock-output-names = "f0120000.dsi"; + max_rate = <0x7270e00>; + }; + + clk_dsi_reset: clk_dsi_reset { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix60m>, <&fix80m>, <&fix120m>, <&pll11>; + current_rate = <0x3938700>; + parent_idx = <0x00>; + mux_reg_offset = <0x00>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x0e>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x0e>; + do_reset = <0x01>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "dsi_reset"; + }; + + clk_mi: clk_mi { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix192m>, <&fix320m>; + current_rate = <0x5b8d800>; + parent_idx = <0x00>; + mux_reg_offset = <0x2c>; + mux_bit_idx = <0x0b>; + mux_bit_width = <0x01>; + div_reg_offset = <0x64>; + div_bit_idx = <0x0c>; + div_bit_width = <0x08>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x12>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x11>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x0a>; + do_autogating = <0x01>; + clock-output-names = "f0110000.mi"; + max_rate = <0x5b8d800>; + }; + + venc_clk: venc_clk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix240m>, <&fix320m>, <&pll11>, <&pll12>, <&pll13>, <&fix192m>, <&fix96m>; + current_rate = <0x1312d000>; + parent_idx = <0x01>; + mux_reg_offset = <0x28>; + mux_bit_idx = <0x14>; + mux_bit_width = <0x03>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x18>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x18>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x10>; + do_autogating = <0x01>; + clock-output-names = "venc_clk"; + max_rate = <0x1312d000>; + power_saving = <0x00>; + }; + + venc_pclk: venc_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x10>; + do_autogating = <0x01>; + clock-output-names = "venc_pclk"; + }; + + ive_pclk: ive_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc4>; + autogating_bit_idx = <0x1c>; + do_autogating = <0x01>; + clock-output-names = "ive_pclk"; + }; + + clk_ive: clk_ive { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&fix240m>, <&fix320m>; + current_rate = <0x1c9c3800>; + parent_idx = <0x00>; + mux_reg_offset = <0x14>; + mux_bit_idx = <0x02>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x19>; + do_enable = <0x01>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x0c>; + do_reset = <0x01>; + autogating_reg_offset = <0xb4>; + autogating_bit_idx = <0x1c>; + do_autogating = <0x01>; + clock-output-names = "f0d70000.ive"; + max_rate = <0x1c9c3800>; + phandle = <0x33>; + }; + + mdbc_pclk: mdbc_pclk { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-gate"; + clocks = <&PAUTOGATING>; + current_rate = <0x00>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x00>; + gate_bit_idx = <0x00>; + do_enable = <0x00>; + reset_reg_offset = <0x00>; + reset_bit_idx = <0x00>; + do_reset = <0x00>; + autogating_reg_offset = <0xc0>; + autogating_bit_idx = <0x0d>; + do_autogating = <0x01>; + clock-output-names = "mdbc_pclk"; + }; + + clk_mdbc: clk_mdbc { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix192m>, <&fix240m>, <&fix96m>, <&fix320m>; + current_rate = <0xe4e1c00>; + parent_idx = <0x01>; + mux_reg_offset = <0x14>; + mux_bit_idx = <0x14>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x16>; + do_enable = <0x01>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x10>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x0d>; + do_autogating = <0x01>; + clock-output-names = "f0c10000.mdbc"; + max_rate = <0x1312d000>; + phandle = <0x32>; + }; + + clk_mcu: clk_mcu { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix120m>, <&osc_rtc>, <&osc_in>, <&prfll>; + current_rate = <0x2dc6c00>; + parent_idx = <0x03>; + mux_reg_offset = <0x10>; + mux_bit_idx = <0x1c>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x70>; + gate_bit_idx = <0x08>; + do_enable = <0x00>; + reset_reg_offset = <0x80>; + reset_bit_idx = <0x19>; + do_reset = <0x00>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "clk_mcu"; + max_rate = <0x7270e00>; + }; + + clk_ai0: clk_ai0 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&fix320m>, <&pll12>, <&pll9>; + current_rate = <0x23c34600>; + parent_idx = <0x00>; + mux_reg_offset = <0x14>; + mux_bit_idx = <0x00>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x17>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x11>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x01>; + do_autogating = <0x01>; + clock-output-names = "f0cb0000.ai"; + max_rate = <0x23c34600>; + }; + + clk_ai1: clk_ai1 { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&fix480m>, <&fix320m>, <&pll12>, <&pll9>; + current_rate = <0x1c9c3800>; + parent_idx = <0x00>; + mux_reg_offset = <0x18>; + mux_bit_idx = <0x1e>; + mux_bit_width = <0x02>; + div_reg_offset = <0x00>; + div_bit_idx = <0x00>; + div_bit_width = <0x00>; + gate_reg_offset = <0x7c>; + gate_bit_idx = <0x15>; + do_enable = <0x00>; + reset_reg_offset = <0x88>; + reset_bit_idx = <0x0f>; + do_reset = <0x01>; + autogating_reg_offset = <0xb0>; + autogating_bit_idx = <0x0c>; + do_autogating = <0x01>; + clock-output-names = "f0d50000.ai"; + max_rate = <0x23c34600>; + }; + + clk_apb: clk_apb { + #clock-cells = <0x00>; + compatible = "nvt,nvt-clk-mux"; + clocks = <&prfll>, <&fix60m>, <&fix80m>, <&fix120m>; + current_rate = <0x7270e00>; + parent_idx = <0x03>; + keep_rate = <0x01>; + mux_reg_offset = <0x10>; + mux_bit_idx = <0x08>; + mux_bit_width = <0x02>; + autogating_reg_offset = <0x00>; + autogating_bit_idx = <0x00>; + do_autogating = <0x00>; + clock-output-names = "apb_clk"; + phandle = <0x50>; + }; + }; + + audio_i2s_part { + i2s = <0x00>, <0x01>, <0x02>, <0x01>, <0x10>, <0x1f40>, <0x3e800>, <0x01>, <0x01>, <0x01>; + }; + + audio_mclk_part { + mclk = <0x00>, <0xbb8000>; + }; +}; diff --git a/openipc/nt98321.dts b/openipc/nt98321.dts new file mode 100644 index 000000000000..74c86152e38e --- /dev/null +++ b/openipc/nt98321.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +/include/ "na51068.dtsi" + +/* + * What the SDK's NT98321 EVB (cfg_98321_DDR3_4GX1_NAND_EVB, one 4 Gb DDR3 + * die, 512 MiB) changes, but for its NAND: Linux gets 160 MiB, and the + * audio input's first SSP port is enabled. The flash is OpenIPC's NOR. + */ +/ { + audio_in_part { + ssp = <0x01 0x01 0x10 0x10 0x1f40 0xbb8000 0x1f4000 0x00 0xffffffff 0x06 0x00 0x01 0x10 0x1f40 0xbb8000 0x2ee000 0x01 0xffffffff 0xffffffff 0x00 0x01 0x10 0x1f40 0xbb8000 0x7d000 0x01 0xffffffff 0xffffffff 0x00 0x01 0x10 0x1f40 0xbb8000 0x7d000 0x01 0xffffffff>; + }; + + memory { + reg = <0x00 0xa000000>; + }; + + hdal-memory { + media { + reg = <0xa000000 0x16000000>; + }; + }; + + nvt_info { + BIN_NAME = "FW98321A"; + BIN_NAME_T = "FW98321T"; + }; +}; diff --git a/openipc/nt98321_config b/openipc/nt98321_config new file mode 100644 index 000000000000..3a8c15ba4831 --- /dev/null +++ b/openipc/nt98321_config @@ -0,0 +1,11 @@ +CONFIG_TARGET_NT98321=y +CONFIG_PRODUCT_SOC="nt98321" +# NA51068: the SPI NOR on the FTSPI020, the SD card on a standard SDHCI +CONFIG_NVT_SPI020=y +CONFIG_MMC_SDHCI=y +# The loader jumps here with its MMU on, its page tables in DDR (in its +# region, 0x100000-0xA00000): cpu_init_cp15 turns the MMU off +# CONFIG_SKIP_LOWLEVEL_INIT is not set +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +# /nvt_memory_cfg/uboot in openipc/na51068.dtsi, the SDK boards' +CONFIG_SYS_TEXT_BASE=0x1E000000 diff --git a/openipc/nt98323.dts b/openipc/nt98323.dts new file mode 100644 index 000000000000..93e2cc852af3 --- /dev/null +++ b/openipc/nt98323.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +/include/ "na51068.dtsi" diff --git a/openipc/nt98323_config b/openipc/nt98323_config new file mode 100644 index 000000000000..3ed916fa71ae --- /dev/null +++ b/openipc/nt98323_config @@ -0,0 +1,11 @@ +CONFIG_TARGET_NT98323=y +CONFIG_PRODUCT_SOC="nt98323" +# NA51068: the SPI NOR on the FTSPI020, the SD card on a standard SDHCI +CONFIG_NVT_SPI020=y +CONFIG_MMC_SDHCI=y +# The loader jumps here with its MMU on, its page tables in DDR (in its +# region, 0x100000-0xA00000): cpu_init_cp15 turns the MMU off +# CONFIG_SKIP_LOWLEVEL_INIT is not set +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +# /nvt_memory_cfg/uboot in openipc/na51068.dtsi, the SDK boards' +CONFIG_SYS_TEXT_BASE=0x1E000000 diff --git a/openipc/nt98332.dts b/openipc/nt98332.dts new file mode 100644 index 000000000000..8f7616faed46 --- /dev/null +++ b/openipc/nt98332.dts @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98332 (NA51103) NVR: the part of the board's device tree U-Boot + * reads, after Xiongmai's NBD80N36RA-KL (FW98332A). Not flashed to boards: + * there the board's own tree stays at 0x10000, behind its loader's + * "XMFDT32G" tag, LZMA-packed, and the vendor kernels need all of it. + * This one is for the emulator's stand-in loader (qemu-hisilicon + * nt98332 with -smp 2), which reads a plain tree at 0x10000 and unpacks + * U-Boot from partition_boot: CI's smoke test. + */ + +/dts-v1/; + +/ { + model = "Novatek NA51103"; + compatible = "novatek,na51103"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x15e00000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf@0x01F00000 { + reg = <0x0 0x1f00000 0x0 0x100000>; + no-map; + }; + }; + + hdal-memory { + #address-cells = <4>; + #size-cells = <2>; + + media { + reg = <0x0 0x0 0x0 0x15e00000 0x0 0x2a200000>; + }; + }; + + nvt_memory_cfg { + #address-cells = <1>; + #size-cells = <1>; + + dram { + reg = <0x00000000 0x40000000>; + }; + + fdt { + reg = <0x00100000 0x00100000>; + }; + + loader { + reg = <0x00200000 0x00800000>; + }; + + shmem { + reg = <0x00a00000 0x00100000>; + }; + + atf { + reg = <0x01f00000 0x00100000>; + }; + + linuxtmp { + reg = <0x02000000 0x1c000000>; + }; + + uboot { + reg = <0x1e000000 0x02000000>; + }; + }; + + uart@2,f0280000 { + compatible = "ns16550a"; + reg = <0x2 0xf0280000 0x0 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <48000000>; + }; + + top@2,f0010000 { + compatible = "nvt,nvt_top"; + reg = <0x2 0xf0010000 0x0 0x2000>; + + spi { + pinmux = <0x11>; + }; + + eth { + pinmux = <0x701>; + }; + }; + + eth0@2,f0440000 { + compatible = "nvt,synopsys_eth"; + reg = <0x2 0xf0440000 0x0 0x10000>; + sp-clk = <1>; + ref-clk-out = <1>; + }; + + nor@2,f0180000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "nvt,nvt_spinor"; + reg = <0x2 0xf0180000 0x0 0x1000>; + clock-frequency = <12000000>; + nvt-devname = "spi_nor.0"; + + /* OpenIPC's NOR layout; the loader reads only these two */ + partition_loader { + label = "loader"; + reg = <0x0 0x0 0x0 0x20000>; + }; + + partition_boot { + label = "boot"; + reg = <0x0 0x20000 0x0 0x20000>; + }; + + nvtpack { + ver = "NVTPACK_FW_INI_16072017"; + method = <1>; + + index { + id0 { + partition_name = "loader"; + source_file = ""; + }; + + id1 { + partition_name = "boot"; + source_file = "u-boot.bin"; + }; + }; + }; + }; + + nvt_info { + BIN_NAME = "FW98332A"; + EMBMEM = "EMBMEM_SPI_NOR"; + NVT_LINUX_SMP = "NVT_LINUX_SMP_ON"; + }; +}; diff --git a/openipc/nt98332_config b/openipc/nt98332_config new file mode 100644 index 000000000000..4ce9f0f57f60 --- /dev/null +++ b/openipc/nt98332_config @@ -0,0 +1,16 @@ +CONFIG_TARGET_NT98332=y +CONFIG_PRODUCT_SOC="nt98332" +# Where the loader's device tree (/nvt_memory_cfg/uboot) has U-Boot +# unpacked and BL31 starts it: the HEADINFO's CodeEntry says the same +CONFIG_SYS_TEXT_BASE=0x1E000000 +# AArch64 runs with the MMU and caches on (arch/arm/mach-novatek/soc.c) +# CONFIG_SYS_DCACHE_OFF is not set +# Past BL31 (0x1F00000, secure) and the loader's areas, as the vendor +CONFIG_SYS_LOAD_ADDR=0x02000000 +# DRAM + 0x1e20000: the other families' 0x1f20000 is in BL31 here +CONFIG_SYS_BOOTCOUNT_ADDR=0x01E20000 +# No SD slot on the NVRs (and no SDIO driver for these dies) +# CONFIG_MMC is not set +# CONFIG_CMD_MMC is not set +# CONFIG_CMD_FAT is not set +# CONFIG_FS_FAT is not set diff --git a/openipc/nt98520.dts b/openipc/nt98520.dts new file mode 100644 index 000000000000..e0f7d81160af --- /dev/null +++ b/openipc/nt98520.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98520: the NA51055 die with one external DDR3 die (the loader's + * table has no second), 512 MiB as the loader is built; otherwise the + * NT98525's tree. + */ +/dts-v1/; + +/include/ "na51055.dtsi" + +/ { + hdal-memory { + media { + reg = <0x12800000 0xd800000>; + }; + }; + + nvt_info { + BIN_NAME = "FW98520A"; + BIN_NAME_T = "FW98520T"; + }; +}; diff --git a/openipc/nt98520_config b/openipc/nt98520_config new file mode 100644 index 000000000000..26e52193f076 --- /dev/null +++ b/openipc/nt98520_config @@ -0,0 +1,2 @@ +CONFIG_TARGET_NT98520=y +CONFIG_PRODUCT_SOC="nt98520" diff --git a/openipc/nt98522.dts b/openipc/nt98522.dts new file mode 100644 index 000000000000..271d9c41ca26 --- /dev/null +++ b/openipc/nt98522.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98522: the NA51055 die with 64 MiB of DDR in the package (the + * loader's table: 512 Mbit), no SDK board. The NT98523's tree with the + * NT98562's split: Linux 32 MiB, its CMA at its top, the media pool the + * rest. + */ +/dts-v1/; + +/include/ "na51055.dtsi" + +/ { + top@f0010000 { + i2c { + pinmux = <0x51>; + }; + }; + + nvt_memory_cfg { + dram { + reg = <0x00 0x4000000>; + }; + + core2entry2 { + reg = <0x3fc0000 0x40000>; + }; + }; + + memory { + reg = <0x00 0x2000000>; + }; + + reserved-memory { + cma0@0x05000000 { + reg = <0x1c00000 0x400000>; + }; + }; + + hdal-memory { + media { + reg = <0x2000000 0x2000000>; + }; + }; + + nvt_info { + BIN_NAME = "FW98522A"; + BIN_NAME_T = "FW98522T"; + }; +}; diff --git a/openipc/nt98522_config b/openipc/nt98522_config new file mode 100644 index 000000000000..cdbd5694b549 --- /dev/null +++ b/openipc/nt98522_config @@ -0,0 +1,2 @@ +CONFIG_TARGET_NT98522=y +CONFIG_PRODUCT_SOC="nt98522" diff --git a/openipc/nt98523.dts b/openipc/nt98523.dts new file mode 100644 index 000000000000..db62c17c4dd1 --- /dev/null +++ b/openipc/nt98523.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98523: the NA51055 die with 128 MiB of DDR in the package, as the + * SDK's cfg_IPCAM1_523_NOR_EVB: Linux the first 64 MiB, its CMA at + * 48 MiB. That board also has an external DDR2 die; the loader here is + * built without one, so the media pool is the rest of the package's. + */ +/dts-v1/; + +/include/ "na51055.dtsi" + +/ { + top@f0010000 { + i2c { + pinmux = <0x51>; + }; + }; + + nvt_memory_cfg { + dram { + reg = <0x00 0x8000000>; + }; + + core2entry2 { + reg = <0x7fc0000 0x40000>; + }; + }; + + memory { + reg = <0x00 0x4000000>; + }; + + reserved-memory { + cma0@0x05000000 { + reg = <0x3000000 0x400000>; + }; + }; + + hdal-memory { + media { + reg = <0x4000000 0x4000000>; + }; + }; + + hdal-maxpath-cfg { + vdoenc_maxpath = <0x08>; + }; + + nvt_info { + BIN_NAME = "FW98523A"; + BIN_NAME_T = "FW98523T"; + }; +}; diff --git a/openipc/nt98523_config b/openipc/nt98523_config new file mode 100644 index 000000000000..06b333262829 --- /dev/null +++ b/openipc/nt98523_config @@ -0,0 +1,2 @@ +CONFIG_TARGET_NT98523=y +CONFIG_PRODUCT_SOC="nt98523" diff --git a/openipc/nt98525.dts b/openipc/nt98525.dts new file mode 100644 index 000000000000..2b58919bf268 --- /dev/null +++ b/openipc/nt98525.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98525: the NA51055 tree as the SDK's cfg_IPCAM1_NOR_EVB has it, two + * external DDR3 dies of 512 MiB, the second the media pool's. + */ +/dts-v1/; + +/include/ "na51055.dtsi" diff --git a/openipc/nt98525_config b/openipc/nt98525_config new file mode 100644 index 000000000000..22dc155aa9c8 --- /dev/null +++ b/openipc/nt98525_config @@ -0,0 +1,2 @@ +CONFIG_TARGET_NT98525=y +CONFIG_PRODUCT_SOC="nt98525" diff --git a/openipc/nt98528.dts b/openipc/nt98528.dts new file mode 100644 index 000000000000..67a824fc5695 --- /dev/null +++ b/openipc/nt98528.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98528: the NA51084 tree as the SDK's cfg_528_IPCAM1_NOR_EVB has it, + * two external DDR3 dies of 512 MiB, the second the media pool's. + */ +/dts-v1/; + +/include/ "na51084.dtsi" diff --git a/openipc/nt98528_config b/openipc/nt98528_config new file mode 100644 index 000000000000..591ea398cb40 --- /dev/null +++ b/openipc/nt98528_config @@ -0,0 +1,2 @@ +CONFIG_TARGET_NT98528=y +CONFIG_PRODUCT_SOC="nt98528" diff --git a/openipc/nt98529.dts b/openipc/nt98529.dts new file mode 100644 index 000000000000..fbfa008f32e0 --- /dev/null +++ b/openipc/nt98529.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98529: the NT98528's tree with what the SDK's NT98529 board + * (cfg_529_IPCAM1_RAMDISK_EVB) changes for the part: the CPUs at + * 1.2 GHz, PLL15 at 400 MHz. + */ +/dts-v1/; + +/include/ "na51084.dtsi" + +/ { + cpus { + cpu@0 { + clock-frequency = <0x47868c00>; + }; + + cpu@1 { + clock-frequency = <0x47868c00>; + }; + }; + + pll_preset@0 { + pll15 { + pll_config = <0x0f 0x17d78400 0x01>; + }; + }; + + nvt_info { + BIN_NAME = "FW98529A"; + BIN_NAME_T = "FW98529T"; + }; +}; diff --git a/openipc/nt98529_config b/openipc/nt98529_config new file mode 100644 index 000000000000..1810b3e69684 --- /dev/null +++ b/openipc/nt98529_config @@ -0,0 +1,2 @@ +CONFIG_TARGET_NT98529=y +CONFIG_PRODUCT_SOC="nt98529" diff --git a/openipc/nt98532.dts b/openipc/nt98532.dts new file mode 100644 index 000000000000..c0bfce2bc4ca --- /dev/null +++ b/openipc/nt98532.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98532: the NS02501 tree as the SDK's cfg_532_IPC_NOR_SQUASHFS_BD_EVB + * has it, 256 MiB of DDR. + */ +/dts-v1/; + +/include/ "ns02501.dtsi" diff --git a/openipc/nt98532_config b/openipc/nt98532_config new file mode 100644 index 000000000000..afbcaef9418f --- /dev/null +++ b/openipc/nt98532_config @@ -0,0 +1,2 @@ +CONFIG_TARGET_NT98532=y +CONFIG_PRODUCT_SOC="nt98532" diff --git a/openipc/nt98533.dts b/openipc/nt98533.dts new file mode 100644 index 000000000000..0058edd04918 --- /dev/null +++ b/openipc/nt98533.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98533: the NS02501 tree with what the SDK's 533QD boards + * (cfg_533_IPC_NAND_UBIFS_QD_EVB, its memory split the NT98532 NOR + * board's) change past their storage: the engines the NT98533 has more + * of (DNE, PRE, MI; IME, IPE and IFE's register ranges), its sensor list, + * the I2C auto reset, the EIS and gyro modules, SDIO3's clock source. + */ +/dts-v1/; + +/include/ "ns02501.dtsi" + +/ { + top@f0010000 { + nvt_sen_os02k10@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_os04a10@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_os04c10@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_os04d10@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_os04e10@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_os05a10@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_os05a10@1 { + pinctrl = <0x0a 0x10 0x0e 0x01 0x03 0x01>; + }; + + nvt_sen_ov64b_pdaf@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_sc450ai@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_sc485sl@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_sc835hai@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_sc850sl@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_nt99436@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_gc4103@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_imx123@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_imx290@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_imx415@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + + nvt_sen_imx678@0 { + pinctrl = <0x0e 0x01 0x03 0x01 0x0a 0x01>; + }; + }; + + ime@f0c40000 { + reg = <0xf0c40000 0xebc>; + }; + + ipe@f0c30000 { + reg = <0xf0c30000 0xaa0>; + }; + + ife@f0c70000 { + reg = <0xf0c70000 0xffc>; + }; + + dne@f0ca0000 { + compatible = "nvt,kdrv_dne"; + reg = <0xf0ca0000 0xffc>; + clocks = <&clk_dne>; + clock-names = "f0ca0000.dne"; + interrupts = <0x00 0x4f 0x04>; + }; + + pre@f0c71000 { + compatible = "nvt,kdrv_pre"; + reg = <0xf0c71000 0xffc>; + clocks = <&clk_pre>; + clock-names = "f0c71000.pre"; + interrupts = <0x00 0x4e 0x04>; + }; + + mi@f0110000 { + compatible = "nvt,nvt_mi"; + clocks = <&clk_mi>; + reg = <0xf0110000 0x1000>; + interrupts = <0x00 0x2f 0x04>; + }; + + nvt_eis { + compatible = "nvt,nvt_eis"; + }; + + nvt_gyro_common { + compatible = "nvt,nvt_gyro_comm"; + }; + + nvt_hr_hwtimer@f01e0000 { + stbc_en = <0x01>; + }; + + i2c@f0220000 { + auto_rst = <0x01>; + }; + + i2c2@f0350000 { + auto_rst = <0x01>; + }; + + i2c3@f0360000 { + auto_rst = <0x01>; + }; + + nvt-clk { + clk_mmc2 { + parent_idx = <0x02>; + }; + }; + + nvt_info { + BIN_NAME = "FW98533A"; + BIN_NAME_T = "FW98533T"; + }; +}; diff --git a/openipc/nt98533_config b/openipc/nt98533_config new file mode 100644 index 000000000000..3d09f11b0bf5 --- /dev/null +++ b/openipc/nt98533_config @@ -0,0 +1,2 @@ +CONFIG_TARGET_NT98533=y +CONFIG_PRODUCT_SOC="nt98533" diff --git a/openipc/nt98560.dts b/openipc/nt98560.dts new file mode 100644 index 000000000000..655ebb596683 --- /dev/null +++ b/openipc/nt98560.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98560: the NA51089 die with external DDR3, 512 MiB on the SDK's board + * (cfg_560_IPCAM1_EVB), which gives Linux the first 256 MiB and the media + * pool the rest. U-Boot stays where the NT98562 has it, below 64 MiB. + */ +/dts-v1/; + +/include/ "na51089.dtsi" + +/ { + nvt_memory_cfg { + dram { + reg = <0x00 0x20000000>; + }; + }; + + memory { + reg = <0x00 0x10000000>; + }; + + hdal-memory { + media { + reg = <0x10000000 0x10000000>; + }; + }; + + hdal-maxpath-cfg { + vdocap_active_list = <0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00>; + vdoprc_maxdevice = <0x02>; + vdoenc_maxpath = <0x08>; + vdodec_maxpath = <0x02>; + }; + + nvt_info { + BIN_NAME = "FW98560A"; + BIN_NAME_T = "FW98560T"; + }; +}; diff --git a/openipc/nt98560_config b/openipc/nt98560_config new file mode 100644 index 000000000000..cce946df6eb3 --- /dev/null +++ b/openipc/nt98560_config @@ -0,0 +1,2 @@ +CONFIG_TARGET_NT98560=y +CONFIG_PRODUCT_SOC="nt98560" diff --git a/openipc/nt98561.dts b/openipc/nt98561.dts new file mode 100644 index 000000000000..22a6597a7a27 --- /dev/null +++ b/openipc/nt98561.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98561: the NT98562's die and 64 MiB DDR2 package; the SDK's + * cfg_561_IPCAM1_EVB differs from cfg_562_IPCAM1_EVB in the firmware's + * name alone. + */ +/dts-v1/; + +/include/ "na51089.dtsi" + +/ { + nvt_info { + BIN_NAME = "FW98561A"; + BIN_NAME_T = "FW98561T"; + }; +}; diff --git a/openipc/nt98561_config b/openipc/nt98561_config new file mode 100644 index 000000000000..340492e55cbd --- /dev/null +++ b/openipc/nt98561_config @@ -0,0 +1,2 @@ +CONFIG_TARGET_NT98561=y +CONFIG_PRODUCT_SOC="nt98561" diff --git a/openipc/nt98633.dts b/openipc/nt98633.dts new file mode 100644 index 000000000000..c5772b92d59e --- /dev/null +++ b/openipc/nt98633.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NT98633 (NA51090) NVR: the part of the board's device tree U-Boot + * reads, after the N2032-8HDD NVR (FW98633A). Not flashed to boards: + * there the board's own tree stays at 0x40000 (partition_fdt), and the + * vendor kernels need all of it. This one is for the emulator's stand-in + * loader (qemu-hisilicon nt98633 with -smp 4), which reads the tree from + * NAND block 2 (0x40000) and unpacks U-Boot from partition_uboot: CI's + * smoke test. + */ + +/dts-v1/; + +/ { + model = "Novatek NA51090"; + compatible = "novatek,na51090"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x57600000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf@0x01F00000 { + reg = <0x0 0x1f00000 0x0 0x100000>; + no-map; + }; + }; + + hdal-memory { + #address-cells = <4>; + #size-cells = <2>; + + media { + reg = <0x0 0x0 0x0 0x57600000 0x0 0x28a00000>; + }; + }; + + nvt_memory_cfg { + #address-cells = <1>; + #size-cells = <1>; + + dram { + reg = <0x00000000 0x80000000>; + }; + + fdt { + reg = <0x00100000 0x00100000>; + }; + + loader { + reg = <0x00200000 0x00800000>; + }; + + shmem { + reg = <0x00a00000 0x00100000>; + }; + + atf { + reg = <0x01f00000 0x00100000>; + }; + + linuxtmp { + reg = <0x02000000 0x3c000000>; + }; + + uboot { + reg = <0x3e000000 0x02000000>; + }; + }; + + uart@2,f0280000 { + compatible = "ns16550a"; + reg = <0x2 0xf0280000 0x0 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <48000000>; + }; + + top@f0010000 { + compatible = "nvt,nvt_top"; + reg = <0x2 0xf0010000 0x0 0x2000>; + + spi { + pinmux = <0x11>; + }; + + eth { + pinmux = <0x502501>; + }; + }; + + eth0@2,f0210000 { + compatible = "nvt,synopsys_eth"; + reg = <0x2 0xf0210000 0x0 0x10000>; + sp-clk = <1>; + ref-clk-out = <0>; + }; + + nand@f0180000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "nvt,nvt_spinand"; + reg = <0x2 0xf0180000 0x0 0x1000>; + clock-frequency = <24000000>; + nvt-devname = "spi_nand.0"; + + /* The board's boot area; OpenIPC's env and UBI follow */ + partition_loader { + label = "loader"; + reg = <0x0 0x0 0x0 0x40000>; + }; + + partition_fdt { + label = "fdt"; + reg = <0x0 0x40000 0x0 0x40000>; + }; + + partition_atf { + label = "atf"; + reg = <0x0 0x80000 0x0 0x40000>; + }; + + partition_uboot { + label = "uboot"; + reg = <0x0 0xc0000 0x0 0xe0000>; + }; + + nvtpack { + ver = "NVTPACK_FW_INI_16072017"; + method = <1>; + + index { + id0 { + partition_name = "loader"; + source_file = ""; + }; + + id1 { + partition_name = "fdt"; + source_file = ""; + }; + + id2 { + partition_name = "atf"; + source_file = ""; + }; + + id3 { + partition_name = "uboot"; + source_file = "u-boot.lz.bin"; + }; + }; + }; + }; + + nvt_info { + BIN_NAME = "FW98633A"; + EMBMEM = "EMBMEM_SPINAND"; + NVT_LINUX_SMP = "NVT_LINUX_SMP_ON"; + }; +}; diff --git a/openipc/nt98633_config b/openipc/nt98633_config new file mode 100644 index 000000000000..46e316ece1f8 --- /dev/null +++ b/openipc/nt98633_config @@ -0,0 +1,39 @@ +CONFIG_TARGET_NT98633=y +CONFIG_PRODUCT_SOC="nt98633" +# Where the loader's device tree (/nvt_memory_cfg/uboot) has U-Boot +# unpacked and BL31 starts it: the HEADINFO's CodeEntry says the same +CONFIG_SYS_TEXT_BASE=0x3E000000 +# AArch64 runs with the MMU and caches on (arch/arm/mach-novatek/soc.c) +# CONFIG_SYS_DCACHE_OFF is not set +# Past BL31 (0x1F00000, secure) and the loader's areas, as the vendor +CONFIG_SYS_LOAD_ADDR=0x02000000 +# DRAM + 0x1e20000: the other families' 0x1f20000 is in BL31 here +CONFIG_SYS_BOOTCOUNT_ADDR=0x01E20000 +CONFIG_SYS_MALLOC_LEN=0x1000000 +# No SD slot on the NVRs (and no SDIO driver for these dies) +# CONFIG_MMC is not set +# CONFIG_CMD_MMC is not set +# CONFIG_CMD_FAT is not set +# CONFIG_FS_FAT is not set + +# SPI NAND, not NOR: the environment in the board's uenv partition, two +# blocks for one bad, and UBI after it (include/configs/novatek.h) +# CONFIG_NVT_SFLASH is not set +# CONFIG_CMD_SF is not set +# CONFIG_ENV_IS_IN_SPI_FLASH is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_NVT_SPI=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_OFFSET=0x1A0000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_RANGE=0x40000 +CONFIG_MTD_PARTITIONS=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_LZO=y diff --git a/openipc/nvt-image.py b/openipc/nvt-image.py index 5d42c043865e..fe0f06c1acf1 100644 --- a/openipc/nvt-image.py +++ b/openipc/nvt-image.py @@ -1,18 +1,25 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: GPL-2.0+ # -# Build the boot partition image of a Novatek NA51089 camera: +# Build the boot partition image of a Novatek NA51089 camera, or of an +# NA51068 (NT98321 / NT98323) DVR/NVR board: # # 0x00000 the loader (it trains the DDR; the mask ROM starts it) # 0x10000 the device tree the loader reads, then hands to U-Boot # 0x20000 U-Boot, in an LZMA BCL1 container # # up to the environment at 0x40000. The loader finds U-Boot through the -# device tree's /nor/partition_uboot, unpacks it with the mask ROM's LZMA -# decoder to /nvt_memory_cfg/uboot and starts it at the HEADINFO's -# CodeEntry, once the checksum over the unpacked image adds up. +# device tree's /nor/partition_uboot, unpacks it with an LZMA decoder +# (NA51089's mask ROM's, the one the NA51068 loader's Compress.a has, or +# the NA51055 / NS02501 loaders' own) to /nvt_memory_cfg/uboot and starts +# it at the HEADINFO's CodeEntry, once the checksum over the unpacked +# image adds up. # -# usage: nvt-image.py LOADER DTB U-BOOT.BIN TEXT_BASE OUTPUT +# With --fdt-lzma the device tree goes in an LZMA BCL1 container too: the +# NS02501 trees (~95 KiB) do not fit their 64 KiB plain, and that loader +# (board/novatek/ns02501/loader) unpacks one. +# +# usage: nvt-image.py [--fdt-lzma] LOADER DTB U-BOOT.BIN TEXT_BASE OUTPUT import lzma import struct @@ -78,13 +85,20 @@ def bcl1_lzma(data): def main(): - if len(sys.argv) != 6: - sys.exit(__doc__ or 'usage: nvt-image.py LOADER DTB U-BOOT.BIN ' - 'TEXT_BASE OUTPUT') - loader = open(sys.argv[1], 'rb').read() - dtb = open(sys.argv[2], 'rb').read() - uboot = open(sys.argv[3], 'rb').read() - text_base = int(sys.argv[4], 0) + args = sys.argv[1:] + fdt_lzma = args[:1] == ['--fdt-lzma'] + if fdt_lzma: + args = args[1:] + if len(args) != 5: + sys.exit(__doc__ or 'usage: nvt-image.py [--fdt-lzma] LOADER DTB ' + 'U-BOOT.BIN TEXT_BASE OUTPUT') + loader = open(args[0], 'rb').read() + dtb = open(args[1], 'rb').read() + uboot = open(args[2], 'rb').read() + text_base = int(args[3], 0) + dtb_len = len(dtb) + if fdt_lzma: + dtb = bcl1_lzma(dtb) bcl = bcl1_lzma(headinfo(uboot, text_base)) for name, blob, room in (('loader', loader, FDT_OFFSET), @@ -98,9 +112,11 @@ def main(): img[0:len(loader)] = loader img[FDT_OFFSET:FDT_OFFSET + len(dtb)] = dtb img[UBOOT_OFFSET:UBOOT_OFFSET + len(bcl)] = bcl - open(sys.argv[5], 'wb').write(img) - print('%s: loader %d, device tree %d, U-Boot %d packed (%d)' % - (sys.argv[5], len(loader), len(dtb), len(bcl), len(uboot))) + open(args[4], 'wb').write(img) + print('%s: loader %d, device tree %d%s, U-Boot %d packed (%d)' % + (args[4], len(loader), len(dtb), + ' packed (%d)' % dtb_len if fdt_lzma else '', len(bcl), + len(uboot))) if __name__ == '__main__': diff --git a/openipc/nvt-nvr-image.py b/openipc/nvt-nvr-image.py new file mode 100644 index 000000000000..beae714381ba --- /dev/null +++ b/openipc/nvt-nvr-image.py @@ -0,0 +1,125 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0+ +# +# Build the U-Boot slot image of a Novatek NVR die, NA51103 (NT98332) or +# NA51090 (NT98633). The board's own loader (DDR training, BL31) and its +# device tree stay in the flash: only the U-Boot slot is OpenIPC's. +# +# nt98332 SPI NOR, Xiongmai's FW98332A loader: the device tree's +# partition_boot (0x20000) holds U-Boot as a bare LZMA stream +# ("compress header 0x5D"); OpenIPC's environment follows at +# 0x40000, so the slot is 128 KiB. +# nt98633 SPI NAND, the SDK's loader: partition_uboot (0xC0000, +# 0xE0000 long) holds a BCL1 LZMA container. +# +# The loader unpacks it to /nvt_memory_cfg/uboot and BL31 enters it at +# the HEADINFO's CodeEntry, in AArch64 at EL2. +# +# usage: nvt-nvr-image.py SOC U-BOOT.BIN TEXT_BASE OUTPUT [FLASH] +# +# With FLASH (a dump of the board's flash, NOR as read, or NAND data +# without OOB) the slot is also written into a copy of it, OUTPUT.flash, +# for an external programmer. + +import lzma +import struct +import sys + +HEADINFO = 0x300 +HI_CODE_ENTRY = HEADINFO + 0x00 +HI_BIN_LENGTH = HEADINFO + 0x68 +HI_CHECKSUM = HEADINFO + 0x6C + +BCL1_LZMA = 11 + +SOCS = { + # slot offset, slot size, container + 'nt98332': (0x20000, 0x20000, 'lzma'), + 'nt98633': (0xC0000, 0xE0000, 'bcl1'), +} + + +def nvt_sum(data): + """The Novatek checksum: sum of each 16-bit word plus its index""" + words = struct.unpack('<%dH' % (len(data) // 2), data[:len(data) & ~1]) + return (sum(words) + sum(range(len(words)))) & 0xffff + + +def headinfo(uboot, text_base): + """Fill in the length and the checksum, as for the NA51089 loader""" + img = bytearray(uboot) + if len(img) & 1: + img += b'\0' + entry = struct.unpack_from('HHII', 0, BCL1_LZMA, + len(data), len(packed))) + bcl += packed + struct.pack_into(' size: + sys.exit('U-Boot is %d bytes packed, %d too many for its %d KiB slot' + % (len(blob), len(blob) - size, size >> 10)) + slot = blob + b'\xff' * (size - len(blob)) + open(sys.argv[4], 'wb').write(slot) + print('%s: U-Boot %d packed (%d), for flash %#x..%#x' % + (sys.argv[4], len(blob), len(uboot), offset, offset + size)) + + if len(sys.argv) == 6: + flash = bytearray(open(sys.argv[5], 'rb').read()) + if len(flash) < offset + size: + sys.exit('%s is too small' % sys.argv[5]) + flash[offset:offset + size] = slot + open(sys.argv[4] + '.flash', 'wb').write(flash) + print('%s.flash: %s with this U-Boot' % (sys.argv[4], sys.argv[5])) + + +if __name__ == '__main__': + main() diff --git a/openipc/openipc_config b/openipc/openipc_config index 5e5d216274f5..67d44654a7ca 100644 --- a/openipc/openipc_config +++ b/openipc/openipc_config @@ -6,7 +6,13 @@ CONFIG_ARCH_NOVATEK=y # Where the loader's device tree (/nvt_memory_cfg/uboot) has U-Boot # unpacked and started: the HEADINFO's CodeEntry must say the same CONFIG_SYS_TEXT_BASE=0x03900000 -CONFIG_SKIP_LOWLEVEL_INIT=y +# The loader has the clocks and the DDR up: no lowlevel_init. But it +# starts U-Boot with its MMU and caches on (its table at 0x1018000 maps +# the DDR write-back), and this U-Boot runs with the data cache off and +# no cache maintenance: cpu_init_cp15 turns them off, as the vendor +# U-Boot's start does. +# CONFIG_SKIP_LOWLEVEL_INIT is not set +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_DM is not set CONFIG_SYS_DCACHE_OFF=y