From 884f6578059a7daaf0fc4cfe0ac1f9a0db2c205b Mon Sep 17 00:00:00 2001
From: klin02 <youkunlin20@mails.ucas.ac.cn>
Date: Thu, 21 May 2026 17:55:59 +0800
Subject: [PATCH] wip: expose cpu and mem AXI4 for fpgadiff

---
 difftest                             | 2 +-
 src/main/scala/sim/NutShellSim.scala | 4 +++-
 src/test/scala/TopMain.scala         | 5 +++--
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/difftest b/difftest
index 63418607..01c19be2 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit 63418607e927b6e9bb1b92c1d814eecea7c8676f
+Subproject commit 01c19be28cfc9f717522846e2d7b246c8df0fb6f
diff --git a/src/main/scala/sim/NutShellSim.scala b/src/main/scala/sim/NutShellSim.scala
index 51b84872..ed6ec884 100644
--- a/src/main/scala/sim/NutShellSim.scala
+++ b/src/main/scala/sim/NutShellSim.scala
@@ -20,6 +20,7 @@ import bus.axi4._
 import chisel3._
 import device.AXI4RAM
 import difftest._
+import difftest.fpga.DifftestMemCtrl
 import nutcore.NutCoreConfig
 import system._
 
@@ -35,13 +36,14 @@ class NutShellSim extends Module with HasDiffTestInterfaces {
   soc.io.frontend <> mmio.io.dma
 
   memdelay.io.in <> soc.io.mem
-  mem.io.in <> memdelay.io.out
 
   mmio.io.rw <> soc.io.mmio
 
   soc.io.meip := mmio.io.meip
 
   override def cpuName: Option[String] = Some("NutShell")
+  val memIO = DifftestMemCtrl.exposeIO(memdelay.io.out, mem.io.in)
+  override def difftestMemIO: Option[DifftestMemIO] = Some(memIO)
 
   val uart = IO(new UARTIO)
   uart <> mmio.io.uart
diff --git a/src/test/scala/TopMain.scala b/src/test/scala/TopMain.scala
index 72c0b4cc..7ff3535e 100644
--- a/src/test/scala/TopMain.scala
+++ b/src/test/scala/TopMain.scala
@@ -20,7 +20,7 @@ import chisel3._
 import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage._
 import device.AXI4VGA
-import difftest.{DifftestModule, DifftestTopIO, HasDiffTestInterfaces}
+import difftest.{DifftestMemIO, DifftestModule, DifftestTopIO, HasDiffTestInterfaces}
 import nutcore.NutCoreConfig
 import sim.NutShellSim
 import system.NutShell
@@ -39,6 +39,7 @@ class Top extends Module {
 class FpgaDiffTop extends NutShell()(NutCoreConfig(FPGADifftest = true)) with HasDiffTestInterfaces {
   override def desiredName: String = "NutShell"
   override def cpuName: Option[String] = Some("NutShell")
+  override def difftestMemIO: Option[DifftestMemIO] = Some(DifftestMemIO(io.mem))
 }
 
 object TopMain extends App {
@@ -88,4 +89,4 @@ object TopMain extends App {
     :+ FirtoolOption("--disable-annotation-unknown")
     :+ FirtoolOption("--default-layer-specialization=enable")
   )
-}
\ No newline at end of file
+}