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2167 lines (2090 loc) · 98.7 KB
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#include "X86/NativeBuiltinFixture.h"
#include <iterator>
#include <regex>
#include <tuple>
class X86PrivilegedIntrinTest : public X86NativeBuiltinTest {};
TEST_F(X86PrivilegedIntrinTest,
IntrinsicRenumberingPreservesChainlessPatterns) {
constexpr const char *Source = R"(
typedef long long Pair __attribute__((vector_size(16)));
__attribute__((target("pclmul")))
Pair multiply(Pair x, Pair y) {
return __builtin_ia32_pclmulqdq128(x, y, 0);
}
__attribute__((target("crc32")))
unsigned int checksum(unsigned int x, unsigned int y) {
return __builtin_ia32_crc32si(x, y);
}
)";
for (const char *Opt : {"-O0", "-O2"}) {
SCOPED_TRACE(Opt);
auto [RC, Assembly] = compileToAsm(Source, "chainless_intrinsics", Opt);
ASSERT_EQ(RC, 0) << Assembly;
EXPECT_NE(Assembly.find("\tpclmulqdq"), std::string::npos) << Assembly;
EXPECT_NE(Assembly.find("\tcrc32"), std::string::npos) << Assembly;
EXPECT_EQ(Assembly.find("#APP"), std::string::npos) << Assembly;
}
}
TEST_F(X86PrivilegedIntrinTest,
APXNativeAtomicInterfacesKeepEncodingAndEffects) {
const auto Source = tmpFile("apx_native.c");
writeFile(Source, R"(
#if !defined(__NEVERC_X86_APX_ATOMIC__)
#error Missing APX native atomic capability
#endif
unsigned long long probe(unsigned long long address, unsigned long long a,
unsigned long long b) {
__builtin_ia32_aadd32_address(address, (unsigned)a, 32, 0x64);
__builtin_ia32_aadd64_address(address, a, 64, 0);
__builtin_ia32_aand32_address(address, (unsigned)a, 64, 0);
__builtin_ia32_aand64_address(address, a, 64, 0);
__builtin_ia32_aor32_address(address, (unsigned)a, 64, 0);
__builtin_ia32_aor64_address(address, a, 64, 0);
__builtin_ia32_axor32_address(address, (unsigned)a, 64, 0);
__builtin_ia32_axor64_address(address, a, 64, 0);
(void)__builtin_ia32_cmpccxadd32_address(address, a, b, 4, 32, 0x65);
(void)__builtin_ia32_cmpccxadd32_address(address, a, b, 4, 32, 0x65);
return __builtin_ia32_cmpccxadd64_address(address, a, b, 15, 64, 0);
}
)");
for (const char *Target : {"x86_64-unknown-linux-gnu",
"x86_64-pc-windows-msvc", "x86_64-apple-darwin"})
for (const char *Opt : {"-O0", "-O2"})
for (bool IR : {true, false}) {
SCOPED_TRACE(Target);
SCOPED_TRACE(Opt);
const auto Output = tmpFile(IR ? "apx_native.ll" : "apx_native.s");
std::vector<std::string> Args = {std::string("--target=") + Target,
Opt,
"-ffreestanding",
"-fno-builtin-mimalloc",
"-fno-lto",
"-masm=att",
"-mllvm",
"-verify-machineinstrs",
"-S",
Source.string(),
"-o",
Output.string()};
if (IR)
Args.push_back("-emit-llvm");
const auto R = ncc(Args);
ASSERT_EQ(R.exitCode, 0) << R.err;
const auto Text = readFile(Output);
EXPECT_EQ(Text.find(IR ? " asm " : "#APP"), std::string::npos);
for (const char *Op : {"aadd", "aand", "aor", "axor", "cmpccxadd"})
for (unsigned Bits : {32u, 64u})
if (IR)
EXPECT_NE(Text.find("@llvm.x86." + std::string(Op) +
std::to_string(Bits) + ".address("),
std::string::npos)
<< Text;
if (!IR) {
EXPECT_NE(Text.find("{evex}"), std::string::npos) << Text;
EXPECT_TRUE(hasDataAddress(Text, "fs:", 32, false)) << Text;
EXPECT_TRUE(hasDataAddress(Text, "gs:", 32, false)) << Text;
const std::regex Query("cmpexadd");
EXPECT_EQ(std::distance(
std::sregex_iterator(Text.begin(), Text.end(), Query),
std::sregex_iterator()),
2)
<< Text;
}
}
}
TEST_F(X86PrivilegedIntrinTest, APXNativeAtomicRejectsInvalidControls) {
for (const char *Call :
{"__builtin_ia32_aadd32_address(a, b, 16, 0)",
"__builtin_ia32_aadd64_address(a, b, 64, 99)",
"__builtin_ia32_axor64_address(a, b, n, 0)",
"__builtin_ia32_cmpccxadd32_address(a, b, b, 16, 64, 0)",
"__builtin_ia32_cmpccxadd64_address(a, b, b, n, 64, 0)",
"__builtin_ia32_cmpccxadd64_address(a, b, b, 0, 64, n)"}) {
const auto Source = "void f(unsigned long long a, unsigned long long b, "
"unsigned n) { (void)" +
std::string(Call) + "; }";
const auto [Status, Error] = compileToAsm(Source.c_str(), "invalid_apx");
EXPECT_NE(Status, 0) << Call << "\n" << Error;
EXPECT_TRUE(Error.find("constant integer") != std::string::npos ||
Error.find("outside the valid range") != std::string::npos ||
Error.find("memory address") != std::string::npos)
<< Error;
}
}
TEST_F(X86PrivilegedIntrinTest, PortableScalarSystemBuiltinsKeepNativeEffects) {
const auto Source = tmpFile("scalar_system.c");
writeFile(Source, R"(
unsigned long long io(unsigned short port, unsigned index,
unsigned long long value) {
__builtin_ia32_wrmsr(index, value);
__builtin_ia32_outbyte(port, value);
__builtin_ia32_outword(port, value);
__builtin_ia32_outdword(port, value);
return __builtin_ia32_rdmsr(index) ^ __builtin_ia32_inbyte(port) ^
__builtin_ia32_inword(port) ^ __builtin_ia32_indword(port);
}
void unused(void) {
__builtin_ia32_rdmsr(0xc0000080);
__builtin_ia32_inbyte(0x1234);
__builtin_ia32_inbyte(0x1234);
}
)");
for (const char *Target : {"x86_64-unknown-linux-gnu",
"x86_64-pc-windows-msvc", "x86_64-apple-darwin"})
for (const char *Opt : {"-O0", "-O2"}) {
SCOPED_TRACE(Target);
SCOPED_TRACE(Opt);
for (bool EmitIR : {true, false}) {
auto Output = tmpFile(EmitIR ? "scalar_system.ll" : "scalar_system.s");
std::vector<std::string> Args = {std::string("--target=") + Target,
"-std=c23",
"-ffreestanding",
"-fno-builtin-mimalloc",
"-fno-lto",
"-mllvm",
"-verify-machineinstrs",
Opt,
"-S",
Source.string(),
"-o",
Output.string()};
if (EmitIR)
Args.push_back("-emit-llvm");
auto Result = ncc(Args);
ASSERT_EQ(Result.exitCode, 0) << Result.err;
const auto Text = readFile(Output);
if (EmitIR) {
for (const char *Name : {"rdmsr", "wrmsr", "inbyte", "inword",
"indword", "outbyte", "outword", "outdword"})
EXPECT_NE(Text.find(std::string("@llvm.x86.") + Name + "("),
std::string::npos)
<< Text;
const std::regex Read("call i8 @llvm\\.x86\\.inbyte\\(i16 4660\\)");
EXPECT_EQ(std::distance(
std::sregex_iterator(Text.begin(), Text.end(), Read),
std::sregex_iterator()),
2)
<< Text;
EXPECT_EQ(Text.find(" asm "), std::string::npos) << Text;
} else {
EXPECT_NE(Text.find("\trdmsr"), std::string::npos) << Text;
EXPECT_NE(Text.find("\twrmsr"), std::string::npos) << Text;
EXPECT_EQ(Text.find("#APP"), std::string::npos) << Text;
}
}
}
}
TEST_F(X86PrivilegedIntrinTest, MpxUsesNativeBoundsBankAndPreservesBranches) {
constexpr const char *Source = R"(
void bounds(unsigned long long base, unsigned long long value,
volatile unsigned *predicate) {
__builtin_ia32_bndmk(0, base, value, 32, 0x64);
__builtin_ia32_bndmov_load(1, base, 64, 0x65);
__builtin_ia32_bndmov_reg(2, 1);
__builtin_ia32_bndcl_reg(2, value);
__builtin_ia32_bndcu_reg(2, value);
__builtin_ia32_bndcn_reg(2, value);
__builtin_ia32_bndcl_address(2, base, 32, 0x26);
__builtin_ia32_bndcu_address(2, base, 64, 0x36);
__builtin_ia32_bndcn_address(2, base, 64, 0x3e);
__builtin_ia32_bndldx(3, base, value, 64, 0);
__builtin_ia32_bndstx(3, base, value, 64, 0);
if (*predicate) __builtin_ia32_bndmov_reg(2, 0);
__builtin_ia32_bndmov_store(2, base, 64, 0);
__builtin_ia32_bndmov_store_lock(2, base, 64, 0);
}
)";
for (const char *Opt : {"-O0", "-O2"}) {
SCOPED_TRACE(Opt);
auto [RC, Assembly] = compileToAsm(Source, "mpx_native", Opt);
ASSERT_EQ(RC, 0) << Assembly;
for (const char *Name :
{"bndmk", "bndmov", "bndcl", "bndcu", "bndcn", "bndldx", "bndstx"})
EXPECT_NE(Assembly.find(std::string("\t") + Name + "\t"),
std::string::npos)
<< Assembly;
EXPECT_NE(Assembly.find("lock"), std::string::npos) << Assembly;
EXPECT_TRUE(std::regex_search(Assembly, std::regex("repne[ \\t]+j")))
<< Assembly;
EXPECT_TRUE(std::regex_search(Assembly, std::regex("repne[ \\t]+ret")))
<< Assembly;
EXPECT_EQ(Assembly.find("#APP"), std::string::npos) << Assembly;
EXPECT_FALSE(std::regex_search(Assembly, std::regex("\\bxmm[0-9]+\\b")))
<< Assembly;
}
}
TEST_F(X86PrivilegedIntrinTest, MpxRejectsInvalidBankAndAddressControls) {
for (const char *Call :
{"bnd_branch(2)", "bnd_branch(-1)", "bnd_branch(index)",
"bndmk(4, base, base, 64, 0)", "bndmov_reg(0, 4)",
"bndmov_reg(index, 0)", "bndcl_reg(256, base)", "bndcu_reg(-1, base)",
"bndcn_reg(index, base)", "bndmov_load(0, base, 16, 0)",
"bndmov_store(0, base, 0, 0)", "bndmov_store_lock(0, base, 64, 0xf0)",
"bndcl_address(0, base, 64, 0x67)", "bndcu_address(0, base, 64, index)",
"bndcn_address(0, base, index, 0)", "bndldx(0, base, base, 128, 0)",
"bndstx(0, base, base, 64, -1)"}) {
SCOPED_TRACE(Call);
const std::string Source =
"void bad(unsigned index, unsigned long long base) { __builtin_ia32_" +
std::string(Call) + "; }";
auto [RC, Error] = compileToAsm(Source.c_str(), "mpx_invalid");
EXPECT_NE(RC, 0) << Error;
EXPECT_TRUE(Error.find("outside the valid range") != std::string::npos ||
Error.find("constant integer") != std::string::npos ||
Error.find("native memory addressing") != std::string::npos)
<< Error;
}
}
TEST_F(X86PrivilegedIntrinTest, MpxOriginalBranchEffectsSurviveOptimization) {
constexpr const char *Source = R"(
void preserve(void) { __builtin_ia32_bnd_branch(1); }
void initialize(volatile unsigned *memory) {
*memory = 1;
__builtin_ia32_bnd_branch(0);
__builtin_ia32_bnd_branch(0);
*memory = 2;
}
)";
for (const char *Opt : {"-O0", "-O2"}) {
SCOPED_TRACE(Opt);
const auto [RC, Assembly] = compileToAsm(Source, "mpx_branch", Opt);
ASSERT_EQ(RC, 0) << Assembly;
const auto First = Assembly.find("{disp32}");
const auto Last = Assembly.rfind("{disp32}");
ASSERT_NE(First, std::string::npos) << Assembly;
EXPECT_NE(First, Last) << Assembly;
EXPECT_LT(Assembly.find("], 1"), First) << Assembly;
EXPECT_GT(Assembly.find("], 2"), Last) << Assembly;
EXPECT_TRUE(
std::regex_search(Assembly.substr(Assembly.find("preserve:"),
Assembly.find("initialize:") -
Assembly.find("preserve:")),
std::regex("repne[ \\t]+ret")))
<< Assembly;
EXPECT_EQ(Assembly.find("#APP"), std::string::npos) << Assembly;
}
}
TEST_F(X86PrivilegedIntrinTest, MpxChecksCannotBeEliminatedOrReordered) {
constexpr const char *Source = R"(
void checks(unsigned long long value, unsigned *memory) {
*memory = 1;
__builtin_ia32_bndcl_reg(3, value);
__builtin_ia32_bndcl_reg(3, value);
*memory = 2;
}
)";
auto [RC, Assembly] = compileToAsm(Source, "mpx_order");
ASSERT_EQ(RC, 0) << Assembly;
const std::regex Instruction("\\tbndcl\\t");
EXPECT_EQ(std::distance(std::sregex_iterator(Assembly.begin(), Assembly.end(),
Instruction),
std::sregex_iterator()),
2)
<< Assembly;
const auto First = Assembly.find("\tbndcl\t");
const auto Last = Assembly.rfind("\tbndcl\t");
EXPECT_LT(Assembly.find("], 1"), First) << Assembly;
EXPECT_GT(Assembly.find("], 2"), Last) << Assembly;
}
TEST_F(X86PrivilegedIntrinTest, AmxPublicHeaderExposesPhysicalTileInterfaces) {
auto Source = tmpFile("amx_header.c");
auto Assembly = tmpFile("amx_header.s");
writeFile(Source, R"(
#include <immintrin.h>
void f(void *out, const void *config, unsigned long long stride,
unsigned row) {
_tile_loadconfig(config);
_tile_storeconfig(out);
_tile_zero(0);
_tile_loadd(1, config, stride);
_tile_stream_loadd(2, config, stride);
_tile_loaddrs(3, config, stride);
_tile_stream_loaddrs(4, config, stride);
_tile_dpbssd(0, 1, 2);
_tile_dpbsud(0, 1, 2);
_tile_dpbusd(0, 1, 2);
_tile_dpbuud(0, 1, 2);
_tile_dpbf16ps(0, 1, 2);
_tile_dpfp16ps(0, 1, 2);
_tile_cmmimfp16ps(0, 1, 2);
_tile_cmmrlfp16ps(0, 1, 2);
_tile_dpbf8ps(0, 1, 2);
_tile_dpbhf8ps(0, 1, 2);
_tile_dphbf8ps(0, 1, 2);
_tile_dphf8ps(0, 1, 2);
_tile_mmultf32ps(0, 1, 2);
((__m512 *)out)[0] = _tile_cvtrowd2ps(0, row);
((__m512 *)out)[1] = _tile_cvtrowd2psi(1, 255);
((__m512bh *)out)[2] = _tile_cvtrowps2bf16h(2, row);
((__m512bh *)out)[3] = _tile_cvtrowps2bf16hi(3, 255);
((__m512bh *)out)[4] = _tile_cvtrowps2bf16l(4, row);
((__m512bh *)out)[5] = _tile_cvtrowps2bf16li(5, 255);
((__m512h *)out)[6] = _tile_cvtrowps2phh(6, row);
((__m512h *)out)[7] = _tile_cvtrowps2phhi(7, 255);
((__m512h *)out)[8] = _tile_cvtrowps2phl(0, row);
((__m512h *)out)[9] = _tile_cvtrowps2phli(1, 255);
((__m512i *)out)[10] = _tile_movrow(2, row);
((__m512i *)out)[11] = _tile_movrowi(3, 255);
_tile_stored(0, out, stride);
_tile_loadconfig_address(config, 32, 100, 0);
_tile_storeconfig_address(out, 64, 101, 1);
_tile_loadd_address(0, config, stride, 32, 54, 1);
_tile_stream_loadd_address(1, config, stride, 64, 62, 0);
_tile_loaddrs_address(2, config, stride, 32, 0, 0);
_tile_stream_loaddrs_address(3, config, stride, 64, 0, 1);
_tile_stored_address(4, out, stride, 32, 100, 0);
((__m512i *)out)[0] = _tile_movrow_reg(5, row, 1);
((__m512 *)out)[1] = _tile_cvtrowd2ps_reg(6, row, 0);
((__m512bh *)out)[2] = _tile_cvtrowps2bf16h_reg(7, row, 1);
((__m512bh *)out)[3] = _tile_cvtrowps2bf16l_reg(0, row, 0);
((__m512h *)out)[4] = _tile_cvtrowps2phh_reg(1, row, 1);
((__m512h *)out)[5] = _tile_cvtrowps2phl_reg(2, row, 0);
_tile_release();
}
)");
for (const char *Triple :
{"x86_64-pc-windows-msvc", "x86_64-unknown-linux-gnu",
"x86_64-apple-darwin"}) {
for (const char *Opt : {"-O0", "-O2"}) {
SCOPED_TRACE(Triple);
SCOPED_TRACE(Opt);
auto Result = ncc({std::string("--target=") + Triple,
"-ffreestanding",
"-fno-builtin-mimalloc",
"-fno-lto",
"-Werror",
"-mamx-avx512",
"-mavx10.2",
"-mamx-int8",
"-mamx-bf16",
"-mamx-fp16",
"-mamx-complex",
"-mamx-fp8",
"-mamx-movrs",
"-mamx-tf32",
"-mapx-features=egpr",
"-mllvm",
"-verify-machineinstrs",
Opt,
"-S",
Source.string(),
"-o",
Assembly.string()});
ASSERT_EQ(Result.exitCode, 0) << Result.err;
const auto Text = readFile(Assembly);
EXPECT_EQ(Text.find("#APP"), std::string::npos) << Text;
EXPECT_NE(Text.find("\ttdpbf8ps\t"), std::string::npos) << Text;
EXPECT_NE(Text.find("\ttcvtrowps2phl\t"), std::string::npos) << Text;
EXPECT_NE(Text.find("\ttileloaddrst1\t"), std::string::npos) << Text;
}
}
}
TEST_F(X86PrivilegedIntrinTest, AmxComputeAndMovrsUseNativeInstructions) {
constexpr const char *Source = R"(
__attribute__((target("amx-fp8,amx-movrs,amx-tf32")))
void compute(const void *source, unsigned long long stride) {
__builtin_ia32_tileloaddrs64(3, source, stride);
__builtin_ia32_tileloaddrst164(4, source, stride);
__builtin_ia32_tdpbf8ps(0, 1, 2);
__builtin_ia32_tdpbhf8ps(3, 4, 5);
__builtin_ia32_tdphbf8ps(6, 7, 0);
__builtin_ia32_tdphf8ps(7, 2, 1);
__builtin_ia32_tmmultf32ps(5, 6, 4);
}
)";
for (const char *Opt : {"-O0", "-O2"}) {
SCOPED_TRACE(Opt);
auto [RC, Assembly] = compileToAsm(Source, "amx_compute", Opt);
ASSERT_EQ(RC, 0) << Assembly;
for (const char *Name :
{"tileloaddrs", "tileloaddrst1", "tdpbf8ps", "tdpbhf8ps", "tdphbf8ps",
"tdphf8ps", "tmmultf32ps"})
EXPECT_NE(Assembly.find(std::string("\t") + Name + "\t"),
std::string::npos)
<< Assembly;
EXPECT_EQ(Assembly.find("#APP"), std::string::npos) << Assembly;
}
}
TEST_F(X86PrivilegedIntrinTest, AmxExplicitAddressesAndRowsRemainNative) {
constexpr const char *Source = R"(
#if !defined(__NEVERC_X86_AMX_CONTROLS__) || __NEVERC_X86_AMX_CONTROLS__ != 1
#error missing compiler AMX control capability
#endif
#if defined(__AMX_TILE__) || defined(__AMX_AVX512__)
#error compiler capability must not change baseline CPU features
#endif
__attribute__((target("amx-tile,amx-movrs,amx-avx512,avx10.2,egpr")))
void controls(unsigned long long base, unsigned long long stride, unsigned row) {
__builtin_ia32_ldtilecfg_address(base, 32, 100, 0);
__builtin_ia32_sttilecfg_address(base, 64, 101, 1);
__builtin_ia32_tileloadd64_address(7, base, stride, 32, 54, 1);
__builtin_ia32_tileloaddt164_address(6, base, stride, 64, 62, 0);
__builtin_ia32_tileloaddrs64_address(5, base, stride, 32, 0, 0);
__builtin_ia32_tileloaddrst164_address(4, base, stride, 64, 0, 1);
__builtin_ia32_tilestored64_address(3, base, stride, 32, 100, 0);
__builtin_ia32_tilemovrow_reg(7, row, 1);
__builtin_ia32_tcvtrowd2ps_reg(6, row, 0);
__builtin_ia32_tcvtrowps2bf16h_reg(5, row, 1);
__builtin_ia32_tcvtrowps2bf16l_reg(4, row, 0);
__builtin_ia32_tcvtrowps2phh_reg(3, row, 1);
__builtin_ia32_tcvtrowps2phl_reg(2, row, 0);
}
)";
for (const char *Opt : {"-O0", "-O2"}) {
auto [RC, Assembly] = compileToAsm(Source, "amx_controls", Opt);
ASSERT_EQ(RC, 0) << Assembly;
EXPECT_NE(Assembly.find("{evex}"), std::string::npos) << Assembly;
EXPECT_NE(Assembly.find("{vex}"), std::string::npos) << Assembly;
EXPECT_NE(Assembly.find("r16d"), std::string::npos) << Assembly;
for (const char *Name :
{"ldtilecfg", "sttilecfg", "tileloadd", "tileloaddt1", "tileloaddrs",
"tileloaddrst1", "tilestored", "tilemovrow", "tcvtrowd2ps",
"tcvtrowps2bf16h", "tcvtrowps2bf16l", "tcvtrowps2phh",
"tcvtrowps2phl"})
EXPECT_NE(Assembly.find(Name), std::string::npos) << Assembly;
EXPECT_EQ(Assembly.find("#APP"), std::string::npos) << Assembly;
}
}
TEST_F(X86PrivilegedIntrinTest, AmxExtendedConstantRowsSurviveOptimization) {
const auto Source = tmpFile("amx_constant_rows.c");
std::string Text;
for (const char *Name : {"tilemovrow", "tcvtrowd2ps", "tcvtrowps2bf16h",
"tcvtrowps2bf16l", "tcvtrowps2phh", "tcvtrowps2phl"})
for (const char *Row : {"0", "1", "0x80000000", "0xffffffff"}) {
Text += "__attribute__((target(\"amx-avx512,avx10.2,egpr\"))) void f_";
Text += std::string(Name) + "_" + Row + "(void) { __builtin_ia32_";
Text += std::string(Name) + "_reg(0, " + Row + ", 1); }\n";
}
writeFile(Source, Text);
for (const char *Target : {"x86_64-unknown-linux-gnu",
"x86_64-pc-windows-msvc", "x86_64-apple-darwin"})
for (const char *Opt : {"-O0", "-O2"}) {
SCOPED_TRACE(Target);
SCOPED_TRACE(Opt);
const auto Object = tmpFile("amx_constant_rows.o");
const auto Result =
ncc({std::string("--target=") + Target, "-ffreestanding", "-fno-lto",
"-fno-builtin-mimalloc", "-mllvm", "-verify-machineinstrs", Opt,
"-c", Source.string(), "-o", Object.string()});
ASSERT_EQ(Result.exitCode, 0) << Result.err;
EXPECT_FALSE(readFile(Object).empty());
}
}
TEST_F(X86PrivilegedIntrinTest, AmxExplicitControlsRejectInvalidContracts) {
for (const char *Call :
{"__builtin_ia32_ldtilecfg_address(base, 16, 0, 0)",
"__builtin_ia32_ldtilecfg_address(base, 64, 1, 0)",
"__builtin_ia32_sttilecfg_address(base, 64, 0, 2)",
"__builtin_ia32_ldtilecfg_address(base, row, 0, 0)",
"__builtin_ia32_tileloadd64_address(8, base, base, 64, 0, 0)",
"__builtin_ia32_tileloadd64_address(row, base, base, 64, 0, 0)",
"__builtin_ia32_tilemovrow_reg(8, row, 0)",
"__builtin_ia32_tilemovrow_reg(0, row, 2)",
"__builtin_ia32_tilemovrow_reg(0, row, row)"}) {
SCOPED_TRACE(Call);
const auto Source =
std::string(
"__attribute__((target(\"amx-tile,amx-avx512,avx10.2,egpr\"))) ") +
"void bad(unsigned long long base, unsigned row) { " + Call + "; }";
auto [RC, Error] = compileToAsm(Source.c_str(), "invalid_amx_controls");
EXPECT_NE(RC, 0) << Error;
EXPECT_NE(Error.find("error:"), std::string::npos) << Error;
}
for (const char *Call : {"__builtin_ia32_ldtilecfg_address(base, 64, 0, 1)",
"__builtin_ia32_tilemovrow_reg(0, row, 1)"}) {
const auto Source =
std::string(
"__attribute__((target(\"amx-tile,amx-avx512,avx10.2\"))) ") +
"void bad(unsigned long long base, unsigned row) { " + Call + "; }";
auto [RC, Error] = compileToAsm(Source.c_str(), "missing_amx_egpr");
EXPECT_NE(RC, 0) << Error;
EXPECT_NE(Error.find("requires egpr"), std::string::npos) << Error;
}
}
TEST_F(X86PrivilegedIntrinTest, AmxRowsReturnNative512BitVectors) {
constexpr const char *Source = R"(
typedef float FloatRow __attribute__((vector_size(64)));
typedef __bf16 BfloatRow __attribute__((vector_size(64)));
typedef _Float16 HalfRow __attribute__((vector_size(64)));
typedef int IntRow __attribute__((vector_size(64)));
__attribute__((target("amx-avx512,avx10.2")))
void rows(unsigned row, FloatRow *f, BfloatRow *b, HalfRow *h, IntRow *i) {
f[0] = __builtin_ia32_tcvtrowd2ps(0, row);
f[1] = __builtin_ia32_tcvtrowd2psi(7, 255);
b[0] = __builtin_ia32_tcvtrowps2bf16h(1, row);
b[1] = __builtin_ia32_tcvtrowps2bf16hi(6, 0);
b[2] = __builtin_ia32_tcvtrowps2bf16l(2, row);
b[3] = __builtin_ia32_tcvtrowps2bf16li(5, 15);
h[0] = __builtin_ia32_tcvtrowps2phh(3, row);
h[1] = __builtin_ia32_tcvtrowps2phhi(4, 16);
h[2] = __builtin_ia32_tcvtrowps2phl(4, row);
h[3] = __builtin_ia32_tcvtrowps2phli(3, 31);
i[0] = __builtin_ia32_tilemovrow(5, row);
i[1] = __builtin_ia32_tilemovrowi(2, 1);
(void)__builtin_ia32_tilemovrow(5, row);
(void)__builtin_ia32_tilemovrow(5, row);
}
)";
for (const char *Opt : {"-O0", "-O2"}) {
SCOPED_TRACE(Opt);
auto [RC, Assembly] = compileToAsm(Source, "amx_rows", Opt);
ASSERT_EQ(RC, 0) << Assembly;
for (const char *Name :
{"tcvtrowd2ps", "tcvtrowps2bf16h", "tcvtrowps2bf16l", "tcvtrowps2phh",
"tcvtrowps2phl", "tilemovrow"}) {
const std::regex Instruction(std::string("\\t") + Name + "\\t");
const auto Count = std::distance(
std::sregex_iterator(Assembly.begin(), Assembly.end(), Instruction),
std::sregex_iterator());
EXPECT_EQ(Count, std::string(Name) == "tilemovrow" ? 4 : 2) << Assembly;
}
EXPECT_EQ(Assembly.find("#APP"), std::string::npos) << Assembly;
}
}
TEST_F(X86PrivilegedIntrinTest, AmxRowFeaturesAndImmediateOperandsAreChecked) {
for (const char *Call : {"__builtin_ia32_tilemovrow(8, row)",
"__builtin_ia32_tcvtrowd2ps(row, row)",
"__builtin_ia32_tcvtrowps2bf16hi(0, row)",
"__builtin_ia32_tcvtrowps2phli(0, 256)",
"__builtin_ia32_tilemovrowi(0, -1)"}) {
const std::string Source =
"__attribute__((target(\"amx-avx512,avx10.2\"))) "
"void f(unsigned row) { (void)" +
std::string(Call) + "; }";
auto [RC, Error] = compileToAsm(Source.c_str(), "amx_invalid_row");
EXPECT_NE(RC, 0) << Call << '\n' << Error;
EXPECT_TRUE(Error.find("outside the valid range") != std::string::npos ||
Error.find("constant integer") != std::string::npos)
<< Error;
}
for (const char *Features : {"amx-avx512", "avx10.2"}) {
const std::string Source = "__attribute__((target(\"" +
std::string(Features) +
"\"))) void f(unsigned row) { "
"(void)__builtin_ia32_tilemovrow(0, row); }";
auto [RC, Error] = compileToAsm(Source.c_str(), "amx_missing_row_feature");
EXPECT_NE(RC, 0) << Error;
EXPECT_NE(Error.find("needs target feature"), std::string::npos) << Error;
}
}
TEST_F(X86PrivilegedIntrinTest, AmxRowDriverFlagsControlFeaturesAndMacros) {
auto Source = tmpFile("amx_row_features.c");
auto Object = tmpFile("amx_row_features.obj");
writeFile(Source, R"(
#if !defined(__AMX_AVX512__) || !defined(__AMX_TILE__) || \
!defined(__AVX10_2__) || !defined(__AVX10_2_512__)
#error missing row features
#endif
void f(unsigned row) { (void)__builtin_ia32_tilemovrow(0, row); }
)");
for (const char *Feature : {"amx-avx512", "avx10.2"}) {
for (bool Enabled : {false, true}) {
const std::string Enable = std::string("-m") + Feature;
const std::string Disable = std::string("-mno-") + Feature;
auto Result = ncc({"--target=x86_64-pc-windows-msvc", "-ffreestanding",
"-fno-builtin-mimalloc", "-fno-lto", "-c",
"-mamx-avx512", "-mavx10.2",
Enabled ? Disable : Enable, Enabled ? Enable : Disable,
Source.string(), "-o", Object.string()});
EXPECT_EQ(Result.exitCode == 0, Enabled) << Result.err;
if (!Enabled)
EXPECT_NE(Result.err.find("missing row features"), std::string::npos)
<< Result.err;
}
}
}
TEST_F(X86PrivilegedIntrinTest, AmxFeaturesAndTileIndicesAreChecked) {
for (const char *Call :
{"__builtin_ia32_tdpbf8ps(0, 0, 1)", "__builtin_ia32_tdpbhf8ps(0, 1, 1)",
"__builtin_ia32_tdphbf8ps(8, 1, 2)", "__builtin_ia32_tdphf8ps(n, 1, 2)",
"__builtin_ia32_tmmultf32ps(0, 1, 8)",
"__builtin_ia32_tileloaddrs64(8, p, 64)",
"__builtin_ia32_tileloaddrst164(n, p, 64)"}) {
const std::string Source =
"__attribute__((target(\"amx-fp8,amx-movrs,amx-tf32\"))) "
"void f(unsigned n, const void *p) { " +
std::string(Call) + "; }";
auto [RC, Error] = compileToAsm(Source.c_str(), "invalid_amx_operand");
EXPECT_NE(RC, 0) << Call << '\n' << Error;
EXPECT_TRUE(Error.find("different tiles") != std::string::npos ||
Error.find("outside the valid range") != std::string::npos ||
Error.find("constant integer") != std::string::npos)
<< Error;
}
for (const char *Call : {"__builtin_ia32_tdpbf8ps(0, 1, 2)",
"__builtin_ia32_tmmultf32ps(0, 1, 2)",
"__builtin_ia32_tileloaddrs64(0, p, 64)"}) {
const std::string Source =
"void f(const void *p) { " + std::string(Call) + "; }";
auto [RC, Error] = compileToAsm(Source.c_str(), "missing_amx_feature");
EXPECT_NE(RC, 0) << Error;
EXPECT_NE(Error.find("needs target feature"), std::string::npos) << Error;
}
}
TEST_F(X86PrivilegedIntrinTest, AmxPhysicalAndManagedTilesCannotBeMixed) {
for (const char *Call : {"__builtin_ia32_tdpbf8ps(0, 1, 2)",
"__builtin_ia32_tilemovrow(0, 1)"}) {
const std::string Source =
"typedef int Tile __attribute__((vector_size(1024))); "
"__attribute__((target(\"amx-fp8,amx-avx512,avx10.2\"))) "
"void f(const void *p, void *q) { "
"Tile t = __builtin_ia32_tileloadd64_internal(2, 16, p, 64); "
"(void)" +
std::string(Call) +
"; "
"__builtin_ia32_tilestored64_internal(2, 16, q, 64, t); }";
for (const char *Opt : {"-O0", "-O2"}) {
auto [RC, Error] = compileToAsm(Source.c_str(), "mixed_amx_models", Opt);
EXPECT_NE(RC, 0) << Error;
EXPECT_NE(Error.find("cannot mix physical AMX tile intrinsics"),
std::string::npos)
<< Error;
}
}
}
TEST_F(X86PrivilegedIntrinTest,
AmxCommandLineFeaturesControlBuiltinsAndMacros) {
for (const auto &[Feature, Macro, Call] :
{std::tuple{"amx-fp8", "__AMX_FP8__",
"__builtin_ia32_tdpbf8ps(0, 1, 2)"},
std::tuple{"amx-movrs", "__AMX_MOVRS__",
"__builtin_ia32_tileloaddrs64(0, p, 64)"},
std::tuple{"amx-tf32", "__AMX_TF32__",
"__builtin_ia32_tmmultf32ps(0, 1, 2)"}}) {
SCOPED_TRACE(Feature);
auto Source = tmpFile("amx_feature.c");
auto Object = tmpFile("amx_feature.obj");
writeFile(Source, std::string("#if !defined(") + Macro +
") || !defined(__AMX_TILE__)\n#error missing "
"requested feature\n#endif\n"
"void f(const void *p) { " +
Call + "; }\n");
const std::string Enable = std::string("-m") + Feature;
const std::string Disable = std::string("-mno-") + Feature;
for (bool Enabled : {true, false}) {
auto Result = ncc({"--target=x86_64-pc-windows-msvc", "-ffreestanding",
"-fno-builtin-mimalloc", "-fno-lto", "-c",
Enabled ? Disable : Enable, Enabled ? Enable : Disable,
Source.string(), "-o", Object.string()});
EXPECT_EQ(Result.exitCode == 0, Enabled) << Result.err;
if (!Enabled)
EXPECT_NE(Result.err.find("missing requested feature"),
std::string::npos)
<< Result.err;
}
}
}
// ---------------------------------------------------------------------------
// MSR: rdmsr / wrmsr — true intrinsic lowering (no InlineAsm markers)
// ---------------------------------------------------------------------------
TEST_F(X86PrivilegedIntrinTest, MsrIntrinsicsLowerCorrectly) {
auto [rc, s] = compileToAsm(R"(
unsigned __int64 read_msr(unsigned int addr) { return __readmsr(addr); }
void write_msr(unsigned int addr, unsigned __int64 val) { __writemsr(addr, val); }
void write_nonserializing(unsigned int addr, unsigned __int64 val) {
__builtin_ia32_wrmsrns(addr, val);
}
void clear_task_switched(void) { __builtin_ia32_clts(); }
)",
"msr");
ASSERT_EQ(rc, 0) << s;
EXPECT_NE(s.find("rdmsr"), std::string::npos) << "expected rdmsr\n" << s;
EXPECT_NE(s.find("wrmsr"), std::string::npos) << "expected wrmsr\n" << s;
EXPECT_NE(s.find("\twrmsrns"), std::string::npos) << s;
EXPECT_NE(s.find("\tclts"), std::string::npos) << s;
EXPECT_EQ(s.find("#APP"), std::string::npos) << "intrinsic path must not use InlineAsm\n" << s;
}
// ---------------------------------------------------------------------------
// CR registers: read + write — write must NOT be DCE'd
// ---------------------------------------------------------------------------
TEST_F(X86PrivilegedIntrinTest, CrRegisterReadsLowerCorrectly) {
auto [rc, s] = compileToAsm(R"(
unsigned __int64 read_cr0(void) { return __readcr0(); }
unsigned __int64 read_cr3(void) { return __readcr3(); }
unsigned __int64 read_cr4(void) { return __readcr4(); }
unsigned __int64 read_cr8(void) { return __readcr8(); }
)", "cr_read");
ASSERT_EQ(rc, 0) << s;
EXPECT_NE(s.find("mov\trax, cr0"), std::string::npos) << "expected mov rax, cr0\n" << s;
EXPECT_NE(s.find("mov\trax, cr3"), std::string::npos) << "expected mov rax, cr3\n" << s;
EXPECT_NE(s.find("mov\trax, cr4"), std::string::npos) << "expected mov rax, cr4\n" << s;
EXPECT_NE(s.find("mov\trax, cr8"), std::string::npos) << "expected mov rax, cr8\n" << s;
}
TEST_F(X86PrivilegedIntrinTest, CrRegisterWritesNotDCEd) {
auto [rc, s] = compileToAsm(R"(
void write_cr0(unsigned __int64 v) { __writecr0(v); }
void write_cr3(unsigned __int64 v) { __writecr3(v); }
void write_cr4(unsigned __int64 v) { __writecr4(v); }
void write_cr8(unsigned __int64 v) { __writecr8(v); }
)", "cr_write");
ASSERT_EQ(rc, 0) << s;
EXPECT_NE(s.find("mov\tcr0, rcx"), std::string::npos) << "write_cr0 DCE'd or wrong\n" << s;
EXPECT_NE(s.find("mov\tcr3, rcx"), std::string::npos) << "write_cr3 DCE'd or wrong\n" << s;
EXPECT_NE(s.find("mov\tcr4, rcx"), std::string::npos) << "write_cr4 DCE'd or wrong\n" << s;
EXPECT_NE(s.find("mov\tcr8, rcx"), std::string::npos) << "write_cr8 DCE'd or wrong\n" << s;
}
// ---------------------------------------------------------------------------
// DR registers: read + write — write must NOT be DCE'd
// ---------------------------------------------------------------------------
TEST_F(X86PrivilegedIntrinTest, DrRegisterOpsLowerCorrectly) {
auto [rc, s] = compileToAsm(R"(
unsigned __int64 read_dr0(void) { return __readdr(0); }
unsigned __int64 read_dr7(void) { return __readdr(7); }
void write_dr0(unsigned __int64 v) { __writedr(0, v); }
void write_dr7(unsigned __int64 v) { __writedr(7, v); }
)", "dr");
ASSERT_EQ(rc, 0) << s;
EXPECT_NE(s.find("mov\trax, dr0"), std::string::npos) << "expected mov rax, dr0\n" << s;
EXPECT_NE(s.find("mov\trax, dr7"), std::string::npos) << "expected mov rax, dr7\n" << s;
EXPECT_NE(s.find("mov\tdr0, rcx"), std::string::npos) << "write_dr0 DCE'd or wrong\n" << s;
EXPECT_NE(s.find("mov\tdr7, rcx"), std::string::npos) << "write_dr7 DCE'd or wrong\n" << s;
}
TEST_F(X86PrivilegedIntrinTest, SystemRegisterReadsRemainObservable) {
constexpr const char *Source = R"(
void discard(void) {
__readcr3();
__readcr3();
__readdr(4);
__readdr(4);
}
unsigned long long repeated(void) {
unsigned long long first = __builtin_ia32_readcr(8);
return first ^ __builtin_ia32_readcr(8);
}
)";
for (const char *Opt : {"-O0", "-O2"}) {
SCOPED_TRACE(Opt);
auto [RC, Assembly] = compileToAsm(Source, "system_reads", Opt);
ASSERT_EQ(RC, 0) << Assembly;
for (const char *Register : {"cr3", "cr8", "dr4"}) {
const std::regex Read(std::string("\\tmov\\t[^,\\n]+, ") + Register);
EXPECT_EQ(std::distance(std::sregex_iterator(Assembly.begin(),
Assembly.end(), Read),
std::sregex_iterator()),
2)
<< Assembly;
}
EXPECT_EQ(Assembly.find("#APP"), std::string::npos) << Assembly;
}
}
TEST_F(X86PrivilegedIntrinTest, SystemRegisterIndicesAreChecked) {
for (const char *Source : {"void f(void) { __builtin_ia32_readcr(1); }",
"void f(void) { __builtin_ia32_writecr(7, 0); }",
"void f(void) { __builtin_ia32_readdr(8); }",
"void f(void) { __builtin_ia32_writedr(9, 0); }",
"void f(unsigned n) { __readdr(n); }",
"void f(void) { __writedr(8, 0); }"}) {
SCOPED_TRACE(Source);
auto [RC, Error] = compileToAsm(Source, "invalid_system_register");
EXPECT_NE(RC, 0) << Error;
EXPECT_TRUE(Error.find("control register index must be") !=
std::string::npos ||
Error.find("outside the valid range") != std::string::npos ||
Error.find("constant integer") != std::string::npos)
<< Error;
}
}
// ---------------------------------------------------------------------------
// Port I/O: in/out 8/16/32 — true intrinsic lowering
// ---------------------------------------------------------------------------
TEST_F(X86PrivilegedIntrinTest, PortIoIntrinsicsLowerCorrectly) {
auto [rc, s] = compileToAsm(R"(
unsigned char in8 (unsigned short p) { return __inbyte(p); }
unsigned short in16(unsigned short p) { return __inword(p); }
unsigned int in32(unsigned short p) { return __indword(p); }
void out8 (unsigned short p, unsigned char v) { __outbyte(p, v); }
void out16(unsigned short p, unsigned short v) { __outword(p, v); }
void out32(unsigned short p, unsigned int v) { __outdword(p, v); }
)", "portio");
ASSERT_EQ(rc, 0) << s;
EXPECT_NE(s.find("in\tal, dx"), std::string::npos) << "expected in al, dx\n" << s;
EXPECT_NE(s.find("in\tax, dx"), std::string::npos) << "expected in ax, dx\n" << s;
EXPECT_NE(s.find("in\teax, dx"), std::string::npos) << "expected in eax, dx\n" << s;
EXPECT_NE(s.find("out\tdx, al"), std::string::npos) << "expected out dx, al\n" << s;
EXPECT_NE(s.find("out\tdx, ax"), std::string::npos) << "expected out dx, ax\n" << s;
EXPECT_NE(s.find("out\tdx, eax"), std::string::npos) << "expected out dx, eax\n" << s;
EXPECT_EQ(s.find("#APP"), std::string::npos) << "intrinsic path must not use InlineAsm\n" << s;
}
// ---------------------------------------------------------------------------
// TLB flush: invlpg
// ---------------------------------------------------------------------------
TEST_F(X86PrivilegedIntrinTest, InvlpgLowersCorrectly) {
auto [rc, s] = compileToAsm(
"void flush_page(void *addr) { __invlpg(addr); }\n", "invlpg");
ASSERT_EQ(rc, 0) << s;
EXPECT_NE(s.find("invlpg"), std::string::npos) << "expected invlpg\n" << s;
}
// ---------------------------------------------------------------------------
// CLI / STI
// ---------------------------------------------------------------------------
TEST_F(X86PrivilegedIntrinTest, CliStiLowerCorrectly) {
auto [rc, s] = compileToAsm(R"(
void do_cli(void) { _disable(); }
void do_sti(void) { _enable(); }
)", "clisti");
ASSERT_EQ(rc, 0) << s;
EXPECT_NE(s.find("cli"), std::string::npos) << "expected cli\n" << s;
EXPECT_NE(s.find("sti"), std::string::npos) << "expected sti\n" << s;
}
// ---------------------------------------------------------------------------
// Descriptor table ops: sidt/lidt/sgdt/lgdt
// ---------------------------------------------------------------------------
TEST_F(X86PrivilegedIntrinTest,
DescriptorAddressesKeepNativeEffectsAndControls) {
std::string Source = "void probe(unsigned long long offset) {\n";
const std::vector<std::string> Names = {
"verr_mem_address", "verw_mem_address", "sldt_mem_address",
"str_mem_address", "smsw_mem_address", "lldt_mem_address",
"ltr_mem_address", "lmsw_mem_address", "sgdt_address",
"sidt_address", "lgdt_address", "lidt_address",
"invlpg_address"};
for (const auto &Name : Names)
for (const auto &Controls : {"64, 0", "32, 100", "32, 101"})
Source +=
" (void)__builtin_ia32_" + Name + "(offset, " + Controls + ");\n";
Source += "}\n";
const auto File = tmpFile("descriptor_addresses.c");
writeFile(File, Source);
for (const char *Target : {"x86_64-unknown-linux-gnu",
"x86_64-pc-windows-msvc", "x86_64-apple-darwin"})
for (const char *Opt : {"-O0", "-O2"}) {
SCOPED_TRACE(Target);
SCOPED_TRACE(Opt);
for (bool EmitIR : {true, false}) {
const auto Output = tmpFile(EmitIR ? "descriptor_addresses.ll"
: "descriptor_addresses.s");
std::vector<std::string> Args = {std::string("--target=") + Target,
"-std=c23",
"-ffreestanding",
"-fno-builtin-mimalloc",
"-fno-lto",
"-mllvm",
"-verify-machineinstrs",
Opt,
"-S",
File.string(),
"-o",
Output.string()};
if (EmitIR)
Args.push_back("-emit-llvm");
const auto Result = ncc(Args);
ASSERT_EQ(Result.exitCode, 0) << Result.err;
const auto Text = readFile(Output);
for (auto Name : Names) {
if (EmitIR) {
std::replace(Name.begin(), Name.end(), '_', '.');
EXPECT_NE(Text.find("@llvm.x86." + Name + "("), std::string::npos)
<< Text;
} else {
Name = Name.substr(0, Name.find('_'));
const std::regex Pattern("\\t" + Name + "[a-z]*[\\t ]+");
EXPECT_EQ(std::distance(std::sregex_iterator(Text.begin(),
Text.end(), Pattern),
std::sregex_iterator()),
3)
<< Text;
}
}
EXPECT_EQ(Text.find(EmitIR ? " asm " : "#APP"), std::string::npos)
<< Text;
if (!EmitIR) {
const bool Intel = Text.find(".intel_syntax") != std::string::npos;
EXPECT_TRUE(hasDataAddress(Text, "fs:", 32, Intel)) << Text;
EXPECT_TRUE(hasDataAddress(Text, "gs:", 32, Intel)) << Text;
}
}
}
for (const auto &Name : Names)
for (const auto &Controls : {"16, 0", "64, 1", "offset, 0", "64, offset"}) {
writeFile(File,
"void invalid(unsigned long long offset) { __builtin_ia32_" +
Name + "(offset, " + Controls + "); }");
const auto Result =
ncc({"--target=x86_64-unknown-linux-gnu", "-ffreestanding",
"-fno-builtin-mimalloc", "-fsyntax-only", File.string()});
EXPECT_NE(Result.exitCode, 0) << Name << " " << Controls;
}
}
TEST_F(X86PrivilegedIntrinTest, DescriptorTableOpsLowerCorrectly) {
auto [rc, s] = compileToAsm(R"(
void do_sidt(void *p) { __sidt(p); }
void do_lidt(void *p) { __lidt(p); }
void do_sgdt(void *p) { _sgdt(p); }
void do_lgdt(void *p) { _lgdt(p); }
)", "desctable");
ASSERT_EQ(rc, 0) << s;
EXPECT_NE(s.find("sidt"), std::string::npos) << "expected sidt\n" << s;
EXPECT_NE(s.find("lidt"), std::string::npos) << "expected lidt\n" << s;
EXPECT_NE(s.find("sgdt"), std::string::npos) << "expected sgdt\n" << s;
EXPECT_NE(s.find("lgdt"), std::string::npos) << "expected lgdt\n" << s;
}
// ---------------------------------------------------------------------------
// WBINVD
// ---------------------------------------------------------------------------
TEST_F(X86PrivilegedIntrinTest, WbinvdLowersCorrectly) {
auto [rc, s] = compileToAsm(
"void do_wbinvd(void) { __wbinvd(); }\n", "wbinvd");
ASSERT_EQ(rc, 0) << s;
EXPECT_NE(s.find("wbinvd"), std::string::npos) << "expected wbinvd\n" << s;
}
// ---------------------------------------------------------------------------
// Segment limit (LSL)
// ---------------------------------------------------------------------------
TEST_F(X86PrivilegedIntrinTest,
DescriptorQueriesUseNativeResultAndStatusPairs) {
std::string Source;
for (const char *Operation : {"lar", "lsl"}) {
for (const auto &[Bits, Type] :
{std::pair{16, "unsigned short"}, std::pair{32, "unsigned int"},
std::pair{64, "unsigned long long"}}) {
for (bool Memory : {false, true}) {
const std::string Name = std::string(Operation) +
(Memory ? "_mem" : "_reg") +
std::to_string(Bits);
Source += std::string(Type) + " " + Name + "(" +
(Memory ? "const void *" : "unsigned short ") + "selector, " +
Type + " prior, unsigned char *zf) { " + Type +
" first = __builtin_ia32_" + Name +
"(selector, prior, zf); return first ^ __builtin_ia32_" +
Name + "(selector, prior, zf + 1); }\n";
}
}
}
for (const char *Opt : {"-O0", "-O2"}) {
auto [RC, Assembly] =
compileToAsm(Source.c_str(), "descriptor_queries", Opt);
ASSERT_EQ(RC, 0) << Assembly;
for (const char *Operation : {"lar", "lsl"}) {
const std::regex Instruction(std::string("\\t") + Operation + "\\t");
EXPECT_EQ(std::distance(std::sregex_iterator(Assembly.begin(),
Assembly.end(), Instruction),
std::sregex_iterator()),
12)
<< Assembly;
}
EXPECT_EQ(Assembly.find("#APP"), std::string::npos) << Assembly;
}