From 6d139b7845f9996ef638728d91561d81ec90b74a Mon Sep 17 00:00:00 2001 From: "Sam, Joochul Chang" Date: Sun, 30 Aug 2026 15:07:56 +0530 Subject: [PATCH 1/5] feat(intrinsics): admit ordered sparse Ampere floating MMA (f16/bf16/tf32, sm_80+) Add the eight PTX 8.5 mma.sp::ordered_metadata floating forms through the catalog/generator pipeline, symmetric to the ordered integer sparse family: - m16n8k8 f32.tf32 - m16n8k16 f32.tf32 - m16n8k16 f32.bf16 - m16n8k32 f32.bf16 - m16n8k16 f16.f16/f32.f16 - m16n8k32 f16.f16/f32.f16 Contracts follow the PTX ISA exactly: operand order d,a,b,c,metadata,selector; selector as an "n" immediate with domain 0-3 for the 2-register carriers (k8, k16-f16/bf16) and 0-1 for the 4-register carriers (k32, k16-tf32); metadata codes 0x4/0x8/0x9/0xc/0xd/0xe (tf32: 0x4/0xe only, with its own reference rule text). The f16/bf16 forms carry <2 x half> multiplicands in LLVM; tf32 carries packed i32. Ported from PR #1139 onto the split resolve/model/render module layout and the ledger-bound blank-ABI-id convention (the shard carries no first_abi_id or product_count; identity binds from intrinsics/abi-v1.toml by catalog id). Evidence identity fields are rebound to the pinned LLVM 23.1.0 backend, matching how all recorded evidence was migrated in the LLVM 23 bump. Signed-off-by: Sam, Joochul Chang Signed-off-by: nihalpasham --- .../src/model/contracts/matrix.rs | 16 + .../cuda-intrinsics-gen/src/model/overlay.rs | 34 ++- crates/cuda-intrinsics-gen/src/probe.rs | 1 + .../src/render/collector_targets.rs | 14 +- .../cuda-intrinsics-gen/src/render/compat.rs | 4 +- .../src/render/dialect/mma.rs | 7 +- .../src/render/families/mma.rs | 34 ++- .../src/render/importer.rs | 6 + .../src/render/tests/mma.rs | 73 ++++- .../src/resolve/families/mma/sparse.rs | 288 +++++++++++++++++- .../src/resolve/overlay.rs | 20 +- .../src/resolve/tests/misc_families.rs | 2 + .../src/resolve/tests/mma.rs | 135 +++++++- .../src/resolve/tests/overlay_schema.rs | 33 +- .../src/resolve/tests/sreg_threadfence.rs | 1 + .../src/resolve/tests/tcgen05.rs | 1 + .../src/resolve/tests/tma_clc_cluster.rs | 3 + .../sparse_mma_ordered_float/Cargo.toml | 17 ++ .../sparse_mma_ordered_float/src/main.rs | 230 ++++++++++++++ ....9.86-sparse-mma-ordered-ampere-float.json | 32 ++ ...96adc-sparse-mma-ordered-ampere-float.json | 28 ++ intrinsics/overlay.toml | 1 + .../sparse_mma_ordered_ampere_float.toml | 49 +++ 23 files changed, 979 insertions(+), 50 deletions(-) create mode 100644 crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.toml create mode 100644 crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs create mode 100644 intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json create mode 100644 intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json create mode 100644 intrinsics/overlay/sparse_mma_ordered_ampere_float.toml diff --git a/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs b/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs index d62f5562d1..52398b3382 100644 --- a/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs +++ b/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs @@ -296,6 +296,8 @@ pub struct SparseMma { #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] #[serde(rename_all = "snake_case")] pub enum SparseMmaShape { + M16n8k8, + M16n8k16, M16n8k32, M16n8k64, M16n8k128, @@ -312,6 +314,9 @@ pub enum SparseMmaAccumulator { #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] #[serde(rename_all = "snake_case")] pub enum SparseMmaElement { + F16, + Bf16, + Tf32, E2m1, E2m3, E3m2, @@ -347,7 +352,10 @@ pub enum SparseMmaMetadata { #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] #[serde(rename_all = "snake_case")] +// The shared prefix makes each variant's accepted immediate range explicit in catalog data. +#[allow(clippy::enum_variant_names)] pub enum SparseMmaSelector { + ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero, } @@ -362,7 +370,9 @@ pub enum SparseMmaParticipation { #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] #[serde(rename_all = "snake_case")] pub enum SparseMmaAdapter { + C2U32A2U32B2U32MetadataU32SelectorU32ToD2U32, C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32, + C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32, C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32, C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32, C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32, @@ -372,7 +382,13 @@ pub enum SparseMmaAdapter { #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] #[serde(rename_all = "snake_case")] pub enum SparseMmaLlvmAdapter { + A2V2F16B2V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16, + A4V2F16B4V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16, + A2V2F16B2V2F16C4F32MetadataI32SelectorI32ToD4F32, + A4V2F16B4V2F16C4F32MetadataI32SelectorI32ToD4F32, + A2I32B2I32C2V2F16MetadataI32SelectorI32ToD2V2F16, A4I32B4I32C2V2F16MetadataI32SelectorI32ToD2V2F16, + A2I32B2I32C4F32MetadataI32SelectorI32ToD4F32, A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32, A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32, A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32, diff --git a/crates/cuda-intrinsics-gen/src/model/overlay.rs b/crates/cuda-intrinsics-gen/src/model/overlay.rs index 60b1b6e351..b69c3e4885 100644 --- a/crates/cuda-intrinsics-gen/src/model/overlay.rs +++ b/crates/cuda-intrinsics-gen/src/model/overlay.rs @@ -16,12 +16,12 @@ use super::contracts::{ ScalarArithmetic, ScalarArithmeticFormat, ScalarArithmeticOperation, ScalarArithmeticRounding, ScalarArithmeticSaturation, ScalarArithmeticSubnormal, ScalarConversion, ScalarConversionRounding, ScalarConversionSaturation, ScalarMath, ScalarMathFormat, - ScalarMathOperation, ScalarMathPrecision, ScalarMathSubnormal, SparseMma, SparseMmaElement, - SparseMmaMetadata, SparseMmaOverflow, SparseMmaShape, SpecialRegister, SpecialRegisterKind, - StmatrixLayout, StmatrixMultiplicity, Tcgen05, Tcgen05CpGroup, Tcgen05CpMember, - Tcgen05LdMultiplicity, Tcgen05LdShape, Tcgen05MmaAlias, Tcgen05MmaForm, Tcgen05Operation, Tma, - TmaOperation, TmaReductionLoadMode, TmaReductionOperation, Vote, WarpBarrier, WarpMatch, - WarpShuffle, WgmmaControl, WgmmaControlMode, + ScalarMathOperation, ScalarMathPrecision, ScalarMathSubnormal, SparseMma, SparseMmaAccumulator, + SparseMmaElement, SparseMmaMetadata, SparseMmaOverflow, SparseMmaShape, SpecialRegister, + SpecialRegisterKind, StmatrixLayout, StmatrixMultiplicity, Tcgen05, Tcgen05CpGroup, + Tcgen05CpMember, Tcgen05LdMultiplicity, Tcgen05LdShape, Tcgen05MmaAlias, Tcgen05MmaForm, + Tcgen05Operation, Tma, TmaOperation, TmaReductionLoadMode, TmaReductionOperation, Vote, + WarpBarrier, WarpMatch, WarpShuffle, WgmmaControl, WgmmaControlMode, }; use super::core::{BackendLoweringMechanism, IntrinsicBackend, IntrinsicSource, RuntimeValidation}; use super::imported::ImportedAddressSpace; @@ -73,6 +73,8 @@ pub struct OverlayShardFile { #[serde(default)] pub sparse_mma_f8f6f4_f16: Option, #[serde(default)] + pub sparse_mma_ordered_ampere_float: Option, + #[serde(default)] pub prmt: Option, #[serde(default)] pub packed_conversion_fp8: Option, @@ -727,6 +729,26 @@ pub struct SparseMmaF8F6F4F16Admission { pub product_count: usize, } +/// Compact admission for the reviewed ordered-metadata Ampere floating sparse MMA forms. +#[derive(Debug, Clone, Deserialize)] +#[serde(deny_unknown_fields)] +pub struct SparseMmaOrderedAmpereFloatAdmission { + pub llvm_evidence_profile: String, + pub libnvvm_evidence_profile: String, + pub runtime_validation: RuntimeValidation, + #[serde(rename = "variant")] + pub variants: Vec, +} + +/// One reviewed ordered-metadata Ampere floating sparse MMA form. +#[derive(Debug, Clone, Copy, PartialEq, Eq, Deserialize)] +#[serde(deny_unknown_fields)] +pub struct SparseMmaOrderedAmpereFloatVariant { + pub shape: SparseMmaShape, + pub accumulator: SparseMmaAccumulator, + pub element: SparseMmaElement, +} + #[derive(Debug, Clone, Deserialize)] #[serde(deny_unknown_fields)] pub struct OverlayIntrinsic { diff --git a/crates/cuda-intrinsics-gen/src/probe.rs b/crates/cuda-intrinsics-gen/src/probe.rs index 7ab3ccab50..bda616c38d 100644 --- a/crates/cuda-intrinsics-gen/src/probe.rs +++ b/crates/cuda-intrinsics-gen/src/probe.rs @@ -884,6 +884,7 @@ fn validate_probe_instructions(record: &CatalogIntrinsic, ptx: &str) -> Result<( } if let Some(mma) = &record.sparse_mma { let selectors: &[u32] = match mma.selector { + SparseMmaSelector::ImmediateZeroThroughThree => &[0, 1, 2, 3], SparseMmaSelector::ImmediateZeroOrOne => &[0, 1], SparseMmaSelector::ImmediateZero => &[0], }; diff --git a/crates/cuda-intrinsics-gen/src/render/collector_targets.rs b/crates/cuda-intrinsics-gen/src/render/collector_targets.rs index de065ddffb..213bec7e94 100644 --- a/crates/cuda-intrinsics-gen/src/render/collector_targets.rs +++ b/crates/cuda-intrinsics-gen/src/render/collector_targets.rs @@ -233,6 +233,8 @@ pub(super) fn generated_intrinsic_variant(record: &CatalogIntrinsic) -> String { } if let Some(mma) = &record.sparse_mma { let shape = match mma.shape { + SparseMmaShape::M16n8k8 => "GeneratedSparseMmaShape::M16n8k8", + SparseMmaShape::M16n8k16 => "GeneratedSparseMmaShape::M16n8k16", SparseMmaShape::M16n8k32 => "GeneratedSparseMmaShape::M16n8k32", SparseMmaShape::M16n8k64 => "GeneratedSparseMmaShape::M16n8k64", SparseMmaShape::M16n8k128 => "GeneratedSparseMmaShape::M16n8k128", @@ -243,6 +245,9 @@ pub(super) fn generated_intrinsic_variant(record: &CatalogIntrinsic) -> String { SparseMmaAccumulator::S32 => "GeneratedSparseMmaAccumulator::S32", }; let element = |element| match element { + SparseMmaElement::F16 => "GeneratedSparseMmaElement::F16", + SparseMmaElement::Bf16 => "GeneratedSparseMmaElement::Bf16", + SparseMmaElement::Tf32 => "GeneratedSparseMmaElement::Tf32", SparseMmaElement::E2m1 => "GeneratedSparseMmaElement::E2m1", SparseMmaElement::E2m3 => "GeneratedSparseMmaElement::E2m3", SparseMmaElement::E3m2 => "GeneratedSparseMmaElement::E3m2", @@ -267,6 +272,9 @@ pub(super) fn generated_intrinsic_variant(record: &CatalogIntrinsic) -> String { SparseMmaMetadata::Ordered => "GeneratedSparseMmaMetadata::Ordered", }; let selector = match mma.selector { + SparseMmaSelector::ImmediateZeroThroughThree => { + "GeneratedSparseMmaSelector::ImmediateZeroThroughThree" + } SparseMmaSelector::ImmediateZeroOrOne => { "GeneratedSparseMmaSelector::ImmediateZeroOrOne" } @@ -573,7 +581,7 @@ impl GeneratedIntrinsicTarget { replace_exact_render_fragment( &mut output, "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {", - "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaShape { M16n8k32, M16n8k64, M16n8k128 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaAccumulator { F16, F32, S32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaElement { E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaLayout { Row, Col }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaOverflow { NotApplicable, Wrapping, Satfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaMetadata { Standard, Ordered }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaSelector { ImmediateZeroOrOne, ImmediateZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedPrmtMode { Generic, F4e, B4e, Rc8, Ecl, Ecr, Rc16 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedClusterBarrierMode { Arrive, ArriveAligned, ArriveRelaxed, ArriveRelaxedAligned, Wait, WaitAligned }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionRounding { NearestAway, NearestEven, TowardZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionSaturation { None, Relu, Satfinite, ReluSatfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {", + "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaShape { M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaAccumulator { F16, F32, S32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaElement { F16, Bf16, Tf32, E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaLayout { Row, Col }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaOverflow { NotApplicable, Wrapping, Satfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaMetadata { Standard, Ordered }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\n#[allow(clippy::enum_variant_names)]\npub enum GeneratedSparseMmaSelector { ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedPrmtMode { Generic, F4e, B4e, Rc8, Ecl, Ecr, Rc16 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedClusterBarrierMode { Arrive, ArriveAligned, ArriveRelaxed, ArriveRelaxedAligned, Wait, WaitAligned }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionRounding { NearestAway, NearestEven, TowardZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionSaturation { None, Relu, Satfinite, ReluSatfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {", ); replace_exact_render_fragment( &mut output, @@ -784,12 +792,12 @@ impl GeneratedIntrinsicTarget { replace_exact_render_fragment( &mut output, " && overflow_matches\n }\n }\n}\n", - " && overflow_matches\n }\n GeneratedIntrinsicVariant::SparseMma { shape, accumulator, a_element, b_element, a_layout, b_layout, overflow, metadata, selector } => {\n let Some(op) = Operation::get_op::(operation, ctx) else { return false; };\n let element_matches = |expected, actual: Option<&SparseMmaElementAttr>| match expected {\n GeneratedSparseMmaElement::E2m1 => actual == Some(&SparseMmaElementAttr::E2m1),\n GeneratedSparseMmaElement::E2m3 => actual == Some(&SparseMmaElementAttr::E2m3),\n GeneratedSparseMmaElement::E3m2 => actual == Some(&SparseMmaElementAttr::E3m2),\n GeneratedSparseMmaElement::E4m3 => actual == Some(&SparseMmaElementAttr::E4m3),\n GeneratedSparseMmaElement::E5m2 => actual == Some(&SparseMmaElementAttr::E5m2),\n GeneratedSparseMmaElement::S4 => actual == Some(&SparseMmaElementAttr::S4),\n GeneratedSparseMmaElement::U4 => actual == Some(&SparseMmaElementAttr::U4),\n GeneratedSparseMmaElement::S8 => actual == Some(&SparseMmaElementAttr::S8),\n GeneratedSparseMmaElement::U8 => actual == Some(&SparseMmaElementAttr::U8),\n };\n let layout_matches = |expected, actual: Option<&SparseMmaLayoutAttr>| match expected {\n GeneratedSparseMmaLayout::Row => actual == Some(&SparseMmaLayoutAttr::Row),\n GeneratedSparseMmaLayout::Col => actual == Some(&SparseMmaLayoutAttr::Col),\n };\n let overflow_matches = match overflow {\n GeneratedSparseMmaOverflow::NotApplicable => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::NotApplicable),\n GeneratedSparseMmaOverflow::Wrapping => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Wrapping),\n GeneratedSparseMmaOverflow::Satfinite => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Satfinite),\n };\n let metadata_matches = match metadata {\n GeneratedSparseMmaMetadata::Standard => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Standard),\n GeneratedSparseMmaMetadata::Ordered => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Ordered),\n };\n matches!(shape, GeneratedSparseMmaShape::M16n8k32)\n && op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32)\n && matches!(accumulator, GeneratedSparseMmaAccumulator::S32)\n && op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32)\n && element_matches(a_element, op.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref())\n && element_matches(b_element, op.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref())\n && layout_matches(a_layout, op.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref())\n && layout_matches(b_layout, op.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref())\n && overflow_matches\n && metadata_matches\n && matches!(selector, GeneratedSparseMmaSelector::ImmediateZeroOrOne)\n && op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne)\n }\n }\n}\n", + " && overflow_matches\n }\n GeneratedIntrinsicVariant::SparseMma { shape, accumulator, a_element, b_element, a_layout, b_layout, overflow, metadata, selector } => {\n let Some(op) = Operation::get_op::(operation, ctx) else { return false; };\n let element_matches = |expected, actual: Option<&SparseMmaElementAttr>| match expected {\n GeneratedSparseMmaElement::F16 => actual == Some(&SparseMmaElementAttr::F16),\n GeneratedSparseMmaElement::Bf16 => actual == Some(&SparseMmaElementAttr::Bf16),\n GeneratedSparseMmaElement::Tf32 => actual == Some(&SparseMmaElementAttr::Tf32),\n GeneratedSparseMmaElement::E2m1 => actual == Some(&SparseMmaElementAttr::E2m1),\n GeneratedSparseMmaElement::E2m3 => actual == Some(&SparseMmaElementAttr::E2m3),\n GeneratedSparseMmaElement::E3m2 => actual == Some(&SparseMmaElementAttr::E3m2),\n GeneratedSparseMmaElement::E4m3 => actual == Some(&SparseMmaElementAttr::E4m3),\n GeneratedSparseMmaElement::E5m2 => actual == Some(&SparseMmaElementAttr::E5m2),\n GeneratedSparseMmaElement::S4 => actual == Some(&SparseMmaElementAttr::S4),\n GeneratedSparseMmaElement::U4 => actual == Some(&SparseMmaElementAttr::U4),\n GeneratedSparseMmaElement::S8 => actual == Some(&SparseMmaElementAttr::S8),\n GeneratedSparseMmaElement::U8 => actual == Some(&SparseMmaElementAttr::U8),\n };\n let layout_matches = |expected, actual: Option<&SparseMmaLayoutAttr>| match expected {\n GeneratedSparseMmaLayout::Row => actual == Some(&SparseMmaLayoutAttr::Row),\n GeneratedSparseMmaLayout::Col => actual == Some(&SparseMmaLayoutAttr::Col),\n };\n let overflow_matches = match overflow {\n GeneratedSparseMmaOverflow::NotApplicable => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::NotApplicable),\n GeneratedSparseMmaOverflow::Wrapping => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Wrapping),\n GeneratedSparseMmaOverflow::Satfinite => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Satfinite),\n };\n let metadata_matches = match metadata {\n GeneratedSparseMmaMetadata::Standard => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Standard),\n GeneratedSparseMmaMetadata::Ordered => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Ordered),\n };\n matches!(shape, GeneratedSparseMmaShape::M16n8k32)\n && op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32)\n && matches!(accumulator, GeneratedSparseMmaAccumulator::S32)\n && op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32)\n && element_matches(a_element, op.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref())\n && element_matches(b_element, op.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref())\n && layout_matches(a_layout, op.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref())\n && layout_matches(b_layout, op.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref())\n && overflow_matches\n && metadata_matches\n && matches!(selector, GeneratedSparseMmaSelector::ImmediateZeroOrOne)\n && op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne)\n }\n }\n}\n", ); replace_exact_render_fragment( &mut output, " matches!(shape, GeneratedSparseMmaShape::M16n8k32)\n && op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32)\n && matches!(accumulator, GeneratedSparseMmaAccumulator::S32)\n && op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32)", - " let shape_matches = match shape {\n GeneratedSparseMmaShape::M16n8k32 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32),\n GeneratedSparseMmaShape::M16n8k64 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k64),\n GeneratedSparseMmaShape::M16n8k128 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k128),\n };\n let accumulator_matches = match accumulator {\n GeneratedSparseMmaAccumulator::F16 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F16),\n GeneratedSparseMmaAccumulator::F32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F32),\n GeneratedSparseMmaAccumulator::S32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32),\n };\n let selector_matches = match selector {\n GeneratedSparseMmaSelector::ImmediateZeroOrOne => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),\n GeneratedSparseMmaSelector::ImmediateZero => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZero),\n };\n shape_matches\n && accumulator_matches", + " let shape_matches = match shape {\n GeneratedSparseMmaShape::M16n8k8 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k8),\n GeneratedSparseMmaShape::M16n8k16 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k16),\n GeneratedSparseMmaShape::M16n8k32 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32),\n GeneratedSparseMmaShape::M16n8k64 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k64),\n GeneratedSparseMmaShape::M16n8k128 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k128),\n };\n let accumulator_matches = match accumulator {\n GeneratedSparseMmaAccumulator::F16 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F16),\n GeneratedSparseMmaAccumulator::F32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F32),\n GeneratedSparseMmaAccumulator::S32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32),\n };\n let selector_matches = match selector {\n GeneratedSparseMmaSelector::ImmediateZeroThroughThree => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree),\n GeneratedSparseMmaSelector::ImmediateZeroOrOne => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),\n GeneratedSparseMmaSelector::ImmediateZero => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZero),\n };\n shape_matches\n && accumulator_matches", ); replace_exact_render_fragment( &mut output, diff --git a/crates/cuda-intrinsics-gen/src/render/compat.rs b/crates/cuda-intrinsics-gen/src/render/compat.rs index 979f9445fa..85ffd95098 100644 --- a/crates/cuda-intrinsics-gen/src/render/compat.rs +++ b/crates/cuda-intrinsics-gen/src/render/compat.rs @@ -205,7 +205,9 @@ pub(super) fn render_compat_sparse_mma(catalog: &CatalogFile, hash: &str) -> Str assert_eq!(path, &format!("cuda_device::wmma::{}", record.rust.name)); assert!(matches!( mma.adapter, - SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 + SparseMmaAdapter::C2U32A2U32B2U32MetadataU32SelectorU32ToD2U32 + | SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 + | SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32 | SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32 | SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32 | SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32 diff --git a/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs b/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs index bd793ae84d..e93f0300b8 100644 --- a/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs +++ b/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs @@ -776,7 +776,7 @@ use pliron_derive::{pliron_attr, pliron_op}; #[pliron_attr(name = "nvvm.sparse_mma_shape", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] -pub enum SparseMmaShapeAttr { M16n8k32, M16n8k64, M16n8k128 } +pub enum SparseMmaShapeAttr { M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128 } #[pliron_attr(name = "nvvm.sparse_mma_accumulator", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] @@ -784,7 +784,7 @@ pub enum SparseMmaAccumulatorAttr { F16, F32, S32 } #[pliron_attr(name = "nvvm.sparse_mma_element", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] -pub enum SparseMmaElementAttr { E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 } +pub enum SparseMmaElementAttr { F16, Bf16, Tf32, E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 } #[pliron_attr(name = "nvvm.sparse_mma_layout", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] @@ -800,7 +800,8 @@ pub enum SparseMmaMetadataAttr { Standard, Ordered } #[pliron_attr(name = "nvvm.sparse_mma_selector", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] -pub enum SparseMmaSelectorAttr { ImmediateZeroOrOne, ImmediateZero } +#[allow(clippy::enum_variant_names)] +pub enum SparseMmaSelectorAttr { ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero } #[pliron_op( name = "nvvm.sparse_mma", diff --git a/crates/cuda-intrinsics-gen/src/render/families/mma.rs b/crates/cuda-intrinsics-gen/src/render/families/mma.rs index 42aebc76c0..f2de275c66 100644 --- a/crates/cuda-intrinsics-gen/src/render/families/mma.rs +++ b/crates/cuda-intrinsics-gen/src/render/families/mma.rs @@ -316,7 +316,9 @@ pub(in crate::render) fn sparse_mma_fragment_counts( record: &CatalogIntrinsic, ) -> (usize, usize, usize, usize) { match record.sparse_mma.as_ref().unwrap().adapter { + SparseMmaAdapter::C2U32A2U32B2U32MetadataU32SelectorU32ToD2U32 => (2, 2, 2, 2), SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 => (2, 4, 4, 2), + SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32 => (4, 2, 2, 4), SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32 | SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32 => (4, 4, 4, 4), SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32 => (4, 2, 2, 4), @@ -325,6 +327,7 @@ pub(in crate::render) fn sparse_mma_fragment_counts( pub(in crate::render) fn sparse_mma_selector_values(record: &CatalogIntrinsic) -> &'static [u32] { match record.sparse_mma.as_ref().unwrap().selector { + SparseMmaSelector::ImmediateZeroThroughThree => &[0, 1, 2, 3], SparseMmaSelector::ImmediateZeroOrOne => &[0, 1], SparseMmaSelector::ImmediateZero => &[0], } @@ -334,6 +337,9 @@ pub(in crate::render) fn sparse_mma_selector_description( record: &CatalogIntrinsic, ) -> &'static str { match record.sparse_mma.as_ref().unwrap().selector { + SparseMmaSelector::ImmediateZeroThroughThree => { + "the compile-time constant `0`, `1`, `2`, or `3`" + } SparseMmaSelector::ImmediateZeroOrOne => "the compile-time constant `0` or `1`", SparseMmaSelector::ImmediateZero => "the compile-time constant `0`", } @@ -341,6 +347,9 @@ pub(in crate::render) fn sparse_mma_selector_description( pub(in crate::render) fn sparse_mma_selector_error(record: &CatalogIntrinsic) -> &'static str { match record.sparse_mma.as_ref().unwrap().selector { + SparseMmaSelector::ImmediateZeroThroughThree => { + "sparse MMA selector must be the compile-time constant 0, 1, 2, or 3" + } SparseMmaSelector::ImmediateZeroOrOne => { "sparse MMA selector must be the compile-time constant 0 or 1" } @@ -352,19 +361,30 @@ pub(in crate::render) fn sparse_mma_selector_error(record: &CatalogIntrinsic) -> pub(in crate::render) const SPARSE_MMA_STANDARD_METADATA_RULE: &str = "Every 4-bit metadata group must encode two distinct 2-bit indices; `0x0`, `0x5`, `0xa`, and `0xf` are undefined behavior."; pub(in crate::render) const SPARSE_MMA_ORDERED_METADATA_RULE: &str = "Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior."; +pub(in crate::render) const SPARSE_MMA_ORDERED_TF32_METADATA_RULE: &str = + "Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior."; pub(in crate::render) fn sparse_mma_metadata_rule(mma: &SparseMma) -> &'static str { - match mma.metadata { - SparseMmaMetadata::Standard => SPARSE_MMA_STANDARD_METADATA_RULE, - SparseMmaMetadata::Ordered => SPARSE_MMA_ORDERED_METADATA_RULE, + match (mma.metadata, mma.a_element) { + (SparseMmaMetadata::Standard, _) => SPARSE_MMA_STANDARD_METADATA_RULE, + (SparseMmaMetadata::Ordered, SparseMmaElement::Tf32) => { + SPARSE_MMA_ORDERED_TF32_METADATA_RULE + } + (SparseMmaMetadata::Ordered, _) => SPARSE_MMA_ORDERED_METADATA_RULE, } } pub(in crate::render) fn sparse_mma_import_adapter(record: &CatalogIntrinsic) -> &'static str { match record.sparse_mma.as_ref().unwrap().adapter { + SparseMmaAdapter::C2U32A2U32B2U32MetadataU32SelectorU32ToD2U32 => { + "GeneratedMmaImportAdapter::C2U32A2U32B2U32ToD2U32" + } SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 => { "GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32" } + SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32 => { + "GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32" + } SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32 => { "GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32" } @@ -392,6 +412,8 @@ pub(in crate::render) fn sparse_mma_attr_variants( ) { let mma = record.sparse_mma.as_ref().expect("sparse-MMA record"); let shape = match mma.shape { + SparseMmaShape::M16n8k8 => "SparseMmaShapeAttr::M16n8k8", + SparseMmaShape::M16n8k16 => "SparseMmaShapeAttr::M16n8k16", SparseMmaShape::M16n8k32 => "SparseMmaShapeAttr::M16n8k32", SparseMmaShape::M16n8k64 => "SparseMmaShapeAttr::M16n8k64", SparseMmaShape::M16n8k128 => "SparseMmaShapeAttr::M16n8k128", @@ -402,6 +424,9 @@ pub(in crate::render) fn sparse_mma_attr_variants( SparseMmaAccumulator::S32 => "SparseMmaAccumulatorAttr::S32", }; let element = |element| match element { + SparseMmaElement::F16 => "SparseMmaElementAttr::F16", + SparseMmaElement::Bf16 => "SparseMmaElementAttr::Bf16", + SparseMmaElement::Tf32 => "SparseMmaElementAttr::Tf32", SparseMmaElement::E2m1 => "SparseMmaElementAttr::E2m1", SparseMmaElement::E2m3 => "SparseMmaElementAttr::E2m3", SparseMmaElement::E3m2 => "SparseMmaElementAttr::E3m2", @@ -426,6 +451,9 @@ pub(in crate::render) fn sparse_mma_attr_variants( SparseMmaMetadata::Ordered => "SparseMmaMetadataAttr::Ordered", }; let selector = match mma.selector { + SparseMmaSelector::ImmediateZeroThroughThree => { + "SparseMmaSelectorAttr::ImmediateZeroThroughThree" + } SparseMmaSelector::ImmediateZeroOrOne => "SparseMmaSelectorAttr::ImmediateZeroOrOne", SparseMmaSelector::ImmediateZero => "SparseMmaSelectorAttr::ImmediateZero", }; diff --git a/crates/cuda-intrinsics-gen/src/render/importer.rs b/crates/cuda-intrinsics-gen/src/render/importer.rs index d6f860d1f6..c1fbf97dd7 100644 --- a/crates/cuda-intrinsics-gen/src/render/importer.rs +++ b/crates/cuda-intrinsics-gen/src/render/importer.rs @@ -2616,9 +2616,11 @@ pub(super) fn import_generated_tcgen05_store_operands( #[derive(Clone, Copy)] pub(super) enum GeneratedMmaImportAdapter { C2U32A2U32B1U32ToD2U32, + C2U32A2U32B2U32ToD2U32, C2U32A4U32B2U32ToD2U32, C2U32A4U32B4U32ToD2U32, C4F32A2U32B1U32ToD4F32, + C4F32A2U32B2U32ToD4F32, C4F32A4U32B2U32ToD4F32, C4F32A4U32B4U32ToD4F32, C2F64A1F64B1F64ToD2F64, @@ -2695,12 +2697,16 @@ pub(super) fn import_generated_mma_operands( match adapter { GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32 => (u32_ty, 2, u32_ty, 2, true, u32_ty, 1, false, u32_ty, 2), + GeneratedMmaImportAdapter::C2U32A2U32B2U32ToD2U32 => + (u32_ty, 2, u32_ty, 2, true, u32_ty, 2, true, u32_ty, 2), GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32 => (u32_ty, 2, u32_ty, 4, true, u32_ty, 2, true, u32_ty, 2), GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32 => (u32_ty, 2, u32_ty, 4, true, u32_ty, 4, true, u32_ty, 2), GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32 => (f32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, f32_ty, 4), + GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32 => + (f32_ty, 4, u32_ty, 2, true, u32_ty, 2, true, f32_ty, 4), GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32 => (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4), GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32 => diff --git a/crates/cuda-intrinsics-gen/src/render/tests/mma.rs b/crates/cuda-intrinsics-gen/src/render/tests/mma.rs index 5b1d4c4570..400b3e13df 100644 --- a/crates/cuda-intrinsics-gen/src/render/tests/mma.rs +++ b/crates/cuda-intrinsics-gen/src/render/tests/mma.rs @@ -13,9 +13,10 @@ use crate::render::collector_targets::generated_intrinsic_variant; use crate::render::common::intrinsic_marker; use crate::render::families::{ BLACKWELL_LDMATRIX_EFFECTIVE_FLOORS, SPARSE_MMA_ORDERED_METADATA_RULE, - SPARSE_MMA_STANDARD_METADATA_RULE, ldmatrix, register_mma_attr_variants, - register_mma_constraints, register_mma_template, register_mmas, sparse_mma_carriers, - sparse_mma_constraints, sparse_mma_fragment_counts, sparse_mma_selector_values, + SPARSE_MMA_ORDERED_TF32_METADATA_RULE, SPARSE_MMA_STANDARD_METADATA_RULE, ldmatrix, + register_mma_attr_variants, register_mma_constraints, register_mma_template, register_mmas, + sparse_mma_carriers, sparse_mma_constraints, sparse_mma_fragment_counts, + sparse_mma_metadata_rule, sparse_mma_selector_description, sparse_mma_selector_values, sparse_mma_template, sparse_mmas, }; use crate::util::read_json; @@ -344,7 +345,7 @@ fn register_mma_rendering_preserves_apis_order_convergence_and_variants() { let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../.."); let catalog = crate::resolve::resolve(&repo_root).unwrap(); validate_renderable(&catalog).unwrap(); - assert_eq!(catalog.intrinsics.len(), 1016); + assert_eq!(catalog.intrinsics.len(), 1024); let records: Vec<_> = register_mmas(&catalog).collect(); assert_eq!(records.len(), 154); let generated_records = records @@ -808,7 +809,7 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { .iter() .filter(|record| record.sparse_mma.as_ref().unwrap().shape == SparseMmaShape::M16n8k128) .count(); - assert_eq!((records.len(), k32, k64, k128), (114, 16, 82, 16)); + assert_eq!((records.len(), k32, k64, k128), (122, 19, 82, 16)); let standard_k64 = records .iter() .copied() @@ -970,7 +971,7 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { } let compatibility = render_compat_sparse_mma(&catalog, "test-hash"); - assert_eq!(compatibility.matches("pub unsafe fn ").count(), 114); + assert_eq!(compatibility.matches("pub unsafe fn ").count(), 122); assert!( compatibility .contains("c: [i32; 4], a: [u32; 2], b: [u32; 2], metadata: u32, selector: u32") @@ -994,9 +995,13 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { assert!(dialect.contains("MmaCarrier::I32")); assert!(dialect.contains("MmaCarrier::U32")); assert!(dialect.contains("operands.len() != expected_operands")); - assert!(dialect.contains("SparseMmaShapeAttr { M16n8k32, M16n8k64, M16n8k128 }")); + assert!( + dialect.contains("SparseMmaShapeAttr { M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128 }") + ); assert!(dialect.contains("SparseMmaAccumulatorAttr { F16, F32, S32 }")); - assert!(dialect.contains("SparseMmaSelectorAttr { ImmediateZeroOrOne, ImmediateZero }")); + assert!(dialect.contains( + "SparseMmaSelectorAttr { ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero }" + )); assert!(dialect.contains("SparseMmaElementAttr::E2m1")); assert!(dialect.contains("SparseMmaElementAttr::E2m3")); assert!(dialect.contains("SparseMmaElementAttr::E3m2")); @@ -1068,7 +1073,11 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { assert!(targets.contains("GeneratedHardwareAlternative::ExactArchitecture(120)")); assert_eq!(raw.matches(SPARSE_MMA_STANDARD_METADATA_RULE).count(), 32); - assert_eq!(raw.matches(SPARSE_MMA_ORDERED_METADATA_RULE).count(), 82); + assert_eq!(raw.matches(SPARSE_MMA_ORDERED_METADATA_RULE).count(), 88); + assert_eq!( + raw.matches(SPARSE_MMA_ORDERED_TF32_METADATA_RULE).count(), + 2 + ); assert_eq!( compatibility .matches(SPARSE_MMA_STANDARD_METADATA_RULE) @@ -1079,7 +1088,13 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { compatibility .matches(SPARSE_MMA_ORDERED_METADATA_RULE) .count(), - 82 + 88 + ); + assert_eq!( + compatibility + .matches(SPARSE_MMA_ORDERED_TF32_METADATA_RULE) + .count(), + 2 ); assert!( lowering.contains("mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32") @@ -1135,7 +1150,37 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { ); assert_eq!( reference.matches(SPARSE_MMA_ORDERED_METADATA_RULE).count(), - 82 + 88 + ); + assert_eq!( + reference + .matches(SPARSE_MMA_ORDERED_TF32_METADATA_RULE) + .count(), + 2 + ); + let tf32_k8 = records + .iter() + .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k8_f32_tf32") + .unwrap(); + let tf32_k16 = records + .iter() + .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k16_f32_tf32") + .unwrap(); + assert_eq!( + sparse_mma_metadata_rule(tf32_k8.sparse_mma.as_ref().unwrap()), + SPARSE_MMA_ORDERED_TF32_METADATA_RULE + ); + assert_eq!( + sparse_mma_selector_description(tf32_k8), + "the compile-time constant `0`, `1`, `2`, or `3`" + ); + assert_eq!( + sparse_mma_metadata_rule(tf32_k16.sparse_mma.as_ref().unwrap()), + SPARSE_MMA_ORDERED_TF32_METADATA_RULE + ); + assert_eq!( + sparse_mma_selector_description(tf32_k16), + "the compile-time constant `0` or `1`" ); let sparse_reference = reference .split("## Sparse-MMA contracts") @@ -1147,7 +1192,11 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { assert!(sparse_reference.contains("Overflow mode is not applicable.")); assert!(!sparse_reference.contains("Integer overflow is not applicable")); for record in &records { - assert!(reference.contains(&format!("- `{}`: runtime `unexecuted`", record.id))); + let runtime = match record.sparse_mma.as_ref().unwrap().runtime_validation { + RuntimeValidation::Unexecuted => "unexecuted", + RuntimeValidation::Executed => "executed", + }; + assert!(reference.contains(&format!("- `{}`: runtime `{runtime}`", record.id))); } let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap(); diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs b/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs index 4749642eb8..f7247af07f 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs @@ -8,8 +8,8 @@ use crate::model::{ OverlayIntrinsic, RuntimeValidation, SparseMma, SparseMmaAccumulator, SparseMmaAdapter, SparseMmaCompatibilitySource, SparseMmaElement, SparseMmaF8F6F4Admission, SparseMmaF8F6F4F16Admission, SparseMmaIntegerAdmission, SparseMmaLayout, SparseMmaLlvmAdapter, - SparseMmaMetadata, SparseMmaOverflow, SparseMmaParticipation, SparseMmaSelector, - SparseMmaShape, + SparseMmaMetadata, SparseMmaOrderedAmpereFloatAdmission, SparseMmaOrderedAmpereFloatVariant, + SparseMmaOverflow, SparseMmaParticipation, SparseMmaSelector, SparseMmaShape, }; use crate::ptx::{InstructionPattern, OperandPattern}; use anyhow::{Context, Result, ensure}; @@ -46,6 +46,7 @@ impl SparseMmaCarrierRecipe { fn selector_upper_exclusive(self) -> u8 { match self.selector { + SparseMmaSelector::ImmediateZeroThroughThree => 4, SparseMmaSelector::ImmediateZeroOrOne => 2, SparseMmaSelector::ImmediateZero => 1, } @@ -87,7 +88,20 @@ impl SparseMmaCarrierRecipe { SparseMmaAccumulator::F32 => "f32", SparseMmaAccumulator::S32 => "i32", }; - std::iter::repeat_n("i32".to_owned(), self.a_registers + self.b_registers) + // Ampere f16/bf16 forms carry their multiplicands as <2 x half> + // vectors in LLVM; every other family carries packed i32. + let multiplicand = if matches!( + self.llvm_adapter, + SparseMmaLlvmAdapter::A2V2F16B2V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16 + | SparseMmaLlvmAdapter::A4V2F16B4V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16 + | SparseMmaLlvmAdapter::A2V2F16B2V2F16C4F32MetadataI32SelectorI32ToD4F32 + | SparseMmaLlvmAdapter::A4V2F16B4V2F16C4F32MetadataI32SelectorI32ToD4F32 + ) { + "v2f16" + } else { + "i32" + }; + std::iter::repeat_n(multiplicand.to_owned(), self.a_registers + self.b_registers) .chain(std::iter::repeat_n( accumulator.to_owned(), self.accumulator_registers(), @@ -223,6 +237,63 @@ pub(in crate::resolve) fn sparse_mma_f8f6f4_f16_carrier_recipe( }) } +fn sparse_mma_ampere_float_carrier_recipe(mma: &SparseMma) -> Option { + use SparseMmaAccumulator::{F16 as AccF16, F32 as AccF32}; + use SparseMmaElement::{Bf16, F16, Tf32}; + use SparseMmaShape::{M16n8k8, M16n8k16, M16n8k32}; + + // Register width decides the selector domain (PTX 9.7.15.6.1): + // 2-reg forms (k8 tf32, k16 f16/bf16) -> one thread per quad, selector 0-3 + // 4-reg forms (k16 tf32, k32 f16/bf16) -> thread pair, selector 0-1 + let (a_registers, b_registers, selector) = match (mma.shape, (mma.a_element, mma.b_element)) { + (M16n8k8, (Tf32, Tf32)) => (2, 2, SparseMmaSelector::ImmediateZeroThroughThree), + (M16n8k16, (Tf32, Tf32)) => (4, 4, SparseMmaSelector::ImmediateZeroOrOne), + (M16n8k16, (Bf16, Bf16) | (F16, F16)) => { + (2, 2, SparseMmaSelector::ImmediateZeroThroughThree) + } + (M16n8k32, (Bf16, Bf16) | (F16, F16)) => (4, 4, SparseMmaSelector::ImmediateZeroOrOne), + _ => return None, + }; + let (adapter, llvm_adapter) = match (mma.accumulator, mma.a_element, a_registers) { + (AccF16, F16, 2) => ( + SparseMmaAdapter::C2U32A2U32B2U32MetadataU32SelectorU32ToD2U32, + SparseMmaLlvmAdapter::A2V2F16B2V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16, + ), + (AccF16, F16, 4) => ( + SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32, + SparseMmaLlvmAdapter::A4V2F16B4V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16, + ), + (AccF32, F16, 2) => ( + SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32, + SparseMmaLlvmAdapter::A2V2F16B2V2F16C4F32MetadataI32SelectorI32ToD4F32, + ), + (AccF32, F16, 4) => ( + SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32, + SparseMmaLlvmAdapter::A4V2F16B4V2F16C4F32MetadataI32SelectorI32ToD4F32, + ), + (AccF32, _, 2) => ( + SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32, + SparseMmaLlvmAdapter::A2I32B2I32C4F32MetadataI32SelectorI32ToD4F32, + ), + (AccF32, _, 4) => ( + SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32, + SparseMmaLlvmAdapter::A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32, + ), + _ => return None, + }; + if mma.accumulator == AccF16 && mma.a_element != F16 { + return None; + } + Some(SparseMmaCarrierRecipe { + adapter, + llvm_adapter, + accumulator: mma.accumulator, + selector, + a_registers, + b_registers, + }) +} + pub(in crate::resolve) struct SparseMmaIdentity { pub(in crate::resolve) id: String, pub(in crate::resolve) operation_key: String, @@ -238,6 +309,8 @@ pub(in crate::resolve) struct SparseMmaRecipe { pub(in crate::resolve) fn sparse_mma_shape_name(shape: SparseMmaShape) -> &'static str { match shape { + SparseMmaShape::M16n8k8 => "m16n8k8", + SparseMmaShape::M16n8k16 => "m16n8k16", SparseMmaShape::M16n8k32 => "m16n8k32", SparseMmaShape::M16n8k64 => "m16n8k64", SparseMmaShape::M16n8k128 => "m16n8k128", @@ -246,6 +319,9 @@ pub(in crate::resolve) fn sparse_mma_shape_name(shape: SparseMmaShape) -> &'stat pub(in crate::resolve) fn sparse_mma_element_name(element: SparseMmaElement) -> &'static str { match element { + SparseMmaElement::F16 => "f16", + SparseMmaElement::Bf16 => "bf16", + SparseMmaElement::Tf32 => "tf32", SparseMmaElement::E2m1 => "e2m1", SparseMmaElement::E2m3 => "e2m3", SparseMmaElement::E3m2 => "e3m2", @@ -262,10 +338,20 @@ pub(in crate::resolve) fn sparse_mma_identity(mma: &SparseMma) -> SparseMmaIdent let shape = sparse_mma_shape_name(mma.shape); let a_element = sparse_mma_element_name(mma.a_element); let b_element = sparse_mma_element_name(mma.b_element); - if matches!( - mma.accumulator, - SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 - ) { + let f8f6f4 = matches!( + mma.a_element, + SparseMmaElement::E2m1 + | SparseMmaElement::E2m3 + | SparseMmaElement::E3m2 + | SparseMmaElement::E4m3 + | SparseMmaElement::E5m2 + ); + if f8f6f4 + && matches!( + mma.accumulator, + SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 + ) + { let scalar = match mma.accumulator { SparseMmaAccumulator::F16 => "f16", SparseMmaAccumulator::F32 => "f32", @@ -299,6 +385,48 @@ pub(in crate::resolve) fn sparse_mma_identity(mma: &SparseMma) -> SparseMmaIdent ], }; } + if matches!( + mma.a_element, + SparseMmaElement::F16 | SparseMmaElement::Bf16 | SparseMmaElement::Tf32 + ) { + let accumulator = match mma.accumulator { + SparseMmaAccumulator::F16 => "f16", + SparseMmaAccumulator::F32 => "f32", + SparseMmaAccumulator::S32 => unreachable!("Ampere float sparse MMA is not integer"), + }; + // LLVM's symbol tail differs per format family: + // f16 -> . pair (f16.f16 / f32.f32); bf16/tf32 -> bare element + let llvm_suffix = match (mma.accumulator, mma.a_element) { + (SparseMmaAccumulator::F16, SparseMmaElement::F16) => "f16.f16", + (SparseMmaAccumulator::F32, SparseMmaElement::F16) => "f32.f32", + (SparseMmaAccumulator::F32, SparseMmaElement::Bf16) => "bf16", + (SparseMmaAccumulator::F32, SparseMmaElement::Tf32) => "tf32", + _ => unreachable!("closed Ampere float recipe rejects this combination"), + }; + return SparseMmaIdentity { + id: format!("mma_sp_ordered_metadata_{shape}_{accumulator}_{a_element}"), + operation_key: format!( + "matrix.mma.sp.{shape}.row.col.{accumulator}.{a_element}.{b_element}.{accumulator}.not_applicable.ordered_metadata" + ), + source_record: format!( + "int_nvvm_mma_sp_ordered_metadata_{shape}_row_col_{}", + llvm_suffix.replace('.', "_") + ), + llvm_symbol: format!("llvm.nvvm.mma.sp.ordered.metadata.{shape}.row.col.{llvm_suffix}"), + ptx_modifiers: vec![ + "sp::ordered_metadata", + "sync", + "aligned", + shape, + "row", + "col", + accumulator, + a_element, + b_element, + accumulator, + ], + }; + } let compact_elements = if mma.a_element == mma.b_element { a_element.to_owned() } else { @@ -377,7 +505,13 @@ pub(in crate::resolve) fn sparse_mma_identity(mma: &SparseMma) -> SparseMmaIdent } pub(in crate::resolve) fn sparse_mma_recipe(mma: &SparseMma) -> Option { - let carrier = if mma.accumulator == SparseMmaAccumulator::F16 { + let ampere_float = matches!( + mma.a_element, + SparseMmaElement::F16 | SparseMmaElement::Bf16 | SparseMmaElement::Tf32 + ); + let carrier = if ampere_float { + sparse_mma_ampere_float_carrier_recipe(mma)? + } else if mma.accumulator == SparseMmaAccumulator::F16 { sparse_mma_f8f6f4_f16_carrier_recipe(mma.shape, mma.a_element, mma.b_element)? } else { sparse_mma_carrier_recipe(mma.shape, mma.a_element, mma.b_element)? @@ -417,6 +551,12 @@ pub(in crate::resolve) fn sparse_mma_recipe(mma: &SparseMma) -> Option &'static str { + if matches!( + mma.a_element, + SparseMmaElement::F16 | SparseMmaElement::Bf16 | SparseMmaElement::Tf32 + ) { + return "8.5"; + } if matches!( mma.accumulator, SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 @@ -432,6 +572,12 @@ pub(in crate::resolve) fn sparse_mma_minimum_ptx(mma: &SparseMma) -> &'static st pub(in crate::resolve) fn sparse_mma_hardware( mma: &SparseMma, ) -> (&'static str, Option<&'static str>) { + if matches!( + mma.a_element, + SparseMmaElement::F16 | SparseMmaElement::Bf16 | SparseMmaElement::Tf32 + ) { + return ("all", Some("sm_80")); + } match mma.accumulator { SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 => (SPARSE_MMA_F8F6F4_TARGETS, None), SparseMmaAccumulator::S32 => ("all", Some("sm_80")), @@ -442,6 +588,115 @@ pub(in crate::resolve) fn sparse_mma_ptx_section(_: SparseMmaMetadata) -> &'stat "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp" } +// The eight reviewed forms in ledger order (i1017..i1024). The admission +// must list exactly these, in this order, so ABI identity stays stable. +pub(in crate::resolve) const SPARSE_MMA_ORDERED_AMPERE_FLOAT_VARIANTS: + [SparseMmaOrderedAmpereFloatVariant; 8] = [ + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k8, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::Tf32, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k16, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::Tf32, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k16, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::Bf16, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k16, + accumulator: SparseMmaAccumulator::F16, + element: SparseMmaElement::F16, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k16, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::F16, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k32, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::Bf16, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k32, + accumulator: SparseMmaAccumulator::F16, + element: SparseMmaElement::F16, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k32, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::F16, + }, +]; + +pub(in crate::resolve) fn expand_sparse_mma_ordered_ampere_float_admission( + admission: &SparseMmaOrderedAmpereFloatAdmission, +) -> Result> { + ensure!( + !admission.llvm_evidence_profile.trim().is_empty() + && !admission.libnvvm_evidence_profile.trim().is_empty(), + "ordered Ampere floating sparse MMA admission requires both backend evidence profiles" + ); + ensure!( + admission.variants == SPARSE_MMA_ORDERED_AMPERE_FLOAT_VARIANTS, + "ordered Ampere floating sparse MMA admission must retain the eight reviewed variants in ABI order" + ); + + admission + .variants + .iter() + .map(|variant| { + let mut mma = SparseMma { + shape: variant.shape, + accumulator: variant.accumulator, + a_element: variant.element, + b_element: variant.element, + a_layout: SparseMmaLayout::Row, + b_layout: SparseMmaLayout::Col, + overflow: SparseMmaOverflow::NotApplicable, + metadata: SparseMmaMetadata::Ordered, + selector: SparseMmaSelector::ImmediateZero, + participation: + SparseMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes, + adapter: SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32, + llvm_adapter: SparseMmaLlvmAdapter::A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32, + compatibility_source: SparseMmaCompatibilitySource::GeneratedStub, + runtime_validation: admission.runtime_validation, + }; + let carrier = sparse_mma_ampere_float_carrier_recipe(&mma).context( + "ordered Ampere floating sparse MMA admission uses an unsupported carrier", + )?; + mma.selector = carrier.selector; + mma.adapter = carrier.adapter; + mma.llvm_adapter = carrier.llvm_adapter; + let recipe = sparse_mma_recipe(&mma).context( + "ordered Ampere floating sparse MMA admission requests a variant outside the closed recipe set", + )?; + Ok(sparse_mma_overlay_record( + String::new(), + mma, + recipe, + &admission.llvm_evidence_profile, + &admission.libnvvm_evidence_profile, + format!( + "Multiplies warp-distributed ordered sparse {} A and B fragments and adds a {} accumulator.", + sparse_mma_element_name(variant.element), + match variant.accumulator { + SparseMmaAccumulator::F16 => "packed f16", + SparseMmaAccumulator::F32 => "f32", + SparseMmaAccumulator::S32 => unreachable!(), + }, + ), + )) + }) + .collect() +} + pub(in crate::resolve) fn expand_sparse_mma_integer_admission( admission: &SparseMmaIntegerAdmission, ) -> Result> { @@ -879,10 +1134,23 @@ pub(in crate::resolve) fn validate_sparse_mma_policy( declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA_SP"] && declaration.properties == recipe.carrier.imported_properties() && declaration.selections.len() == 1 - && (!matches!( + && (if matches!( + mma.a_element, + SparseMmaElement::F16 | SparseMmaElement::Bf16 | SparseMmaElement::Tf32 + ) { + declaration.selections[0].predicates + == [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ] + } else if matches!( mma.accumulator, SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 - ) || declaration.selections[0].predicates == ["Subtarget->hasMMABlockScale()"]) + ) { + declaration.selections[0].predicates == ["Subtarget->hasMMABlockScale()"] + } else { + true + }) && selection_matches_policy(policy, &declaration.selections[0])?, "{} imported sparse MMA declaration changed its class, immediate range, properties, or exact selection contract", policy.id diff --git a/crates/cuda-intrinsics-gen/src/resolve/overlay.rs b/crates/cuda-intrinsics-gen/src/resolve/overlay.rs index 88d9f637c7..f077a848fb 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/overlay.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/overlay.rs @@ -19,7 +19,7 @@ use super::guards::*; pub(super) const OVERLAY_SCHEMA: u32 = 44; pub(super) const MINIMUM_OVERLAY_SHARD_SCHEMA: u32 = 26; -pub(super) const OVERLAY_SHARD_SCHEMA: u32 = 62; +pub(super) const OVERLAY_SHARD_SCHEMA: u32 = 63; pub(super) const REGISTER_MMA_F8F6F4_SHARD_SCHEMA: u32 = 46; pub(super) const REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA: u32 = 47; pub(super) const REGISTER_MMA_MXF8F6F4_SHARD_SCHEMA: u32 = 60; @@ -27,6 +27,7 @@ pub(super) const REGISTER_MMA_FP8_SHARD_SCHEMA: u32 = 48; pub(super) const REGISTER_MMA_AMPERE_FLOAT_SHARD_SCHEMA: u32 = 49; pub(super) const SPARSE_MMA_F8F6F4_SHARD_SCHEMA: u32 = 27; pub(super) const SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA: u32 = 50; +pub(super) const SPARSE_MMA_AMPERE_FLOAT_SHARD_SCHEMA: u32 = 63; pub(super) const PRMT_SHARD_SCHEMA: u32 = 28; pub(super) const PACKED_CONVERSION_FP8_SHARD_SCHEMA: u32 = 29; pub(super) const PACKED_CONVERSION_FP8_F16X2_SHARD_SCHEMA: u32 = 59; @@ -108,6 +109,7 @@ pub(super) fn read_overlay( let sparse_mma_admission = shard.sparse_mma_integer.take(); let sparse_mma_f8f6f4_admission = shard.sparse_mma_f8f6f4_f32.take(); let sparse_mma_f8f6f4_f16_admission = shard.sparse_mma_f8f6f4_f16.take(); + let sparse_mma_ampere_float_admission = shard.sparse_mma_ordered_ampere_float.take(); let prmt_admission = shard.prmt.take(); let packed_conversion_fp8_admission = shard.packed_conversion_fp8.take(); let packed_conversion_fp8_f16x2_admission = shard.packed_conversion_fp8_f16x2.take(); @@ -137,7 +139,8 @@ pub(super) fn read_overlay( + usize::from(ampere_float_mma_admission.is_some()) + usize::from(sparse_mma_admission.is_some()) + usize::from(sparse_mma_f8f6f4_admission.is_some()) - + usize::from(sparse_mma_f8f6f4_f16_admission.is_some()); + + usize::from(sparse_mma_f8f6f4_f16_admission.is_some()) + + usize::from(sparse_mma_ampere_float_admission.is_some()); ensure!( compact_mma_count <= 1, "overlay shard {} contains more than one compact MMA admission", @@ -220,6 +223,13 @@ pub(super) fn read_overlay( ); shard.intrinsics = expand_sparse_mma_f8f6f4_f16_admission(&admission)?; } + if let Some(admission) = sparse_mma_ampere_float_admission { + ensure!( + shard.family == "sparse_mma" && shard.intrinsics.is_empty(), + "compact ordered Ampere floating sparse MMA admission must be the only content of a sparse_mma shard" + ); + shard.intrinsics = expand_sparse_mma_ordered_ampere_float_admission(&admission)?; + } if let Some(admission) = prmt_admission { ensure!( shard.family == "prmt" && shard.intrinsics.is_empty(), @@ -407,6 +417,12 @@ pub(super) fn validate_overlay_shard_schema_with_max( "compact sparse f8f6f4 F16 MMA admission requires overlay shard schema {}", SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA ); + ensure!( + shard.sparse_mma_ordered_ampere_float.is_none() + || shard.schema >= SPARSE_MMA_AMPERE_FLOAT_SHARD_SCHEMA, + "compact ordered Ampere floating sparse MMA admission requires overlay shard schema {}", + SPARSE_MMA_AMPERE_FLOAT_SHARD_SCHEMA + ); ensure!( shard.register_mma_f8f6f4_f32.is_none() || shard.schema >= REGISTER_MMA_F8F6F4_SHARD_SCHEMA, "compact dense f8f6f4 MMA admission requires overlay shard schema {}", diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs index 3c8f431546..302b0215ab 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs @@ -187,6 +187,7 @@ fn debug_control_compact_schema_is_reserved_for_aggregation() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, @@ -454,6 +455,7 @@ fn wgmma_control_compact_schema_is_reserved_for_aggregation() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs index ae75b96be1..d86dded211 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs @@ -284,6 +284,105 @@ fn compact_sparse_f8f6f4_f16_admission_is_closed_and_ordered() { assert!(expand_sparse_mma_f8f6f4_f16_admission(&executed).is_err()); } +#[test] +fn compact_sparse_ordered_ampere_float_admission_is_closed_and_ledger_bound() { + let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../.."); + let path = repo_root.join("intrinsics/overlay/sparse_mma_ordered_ampere_float.toml"); + let bytes = fs::read(&path).unwrap(); + let shard: OverlayShardFile = toml::from_slice(&bytes).unwrap(); + let admission = shard.sparse_mma_ordered_ampere_float.unwrap(); + + // Executed runtime validation is admitted for this family (GPU evidence backs it). + assert_eq!(admission.runtime_validation, RuntimeValidation::Executed); + let records = expand_sparse_mma_ordered_ampere_float_admission(&admission).unwrap(); + assert_eq!(records.len(), 8); + assert!(records.iter().all(|record| record.abi_id.is_empty())); + assert!(records.iter().all(|record| { + record + .sparse_mma + .as_ref() + .is_some_and(|mma| mma.runtime_validation == RuntimeValidation::Executed) + })); + + let mut bound = overlay_file(records.clone()); + bind_pinned_abi_ids(&repo_root, &mut bound); + assert_eq!( + bound + .intrinsics + .iter() + .map(|record| record.abi_id.clone()) + .collect::>(), + (1017..=1024) + .map(|id| format!("i{id:04}")) + .collect::>() + ); + + // First form: m16n8k8 tf32 (2-reg carrier, selector 0-3). + let first = &records[0]; + assert_eq!(first.id, "mma_sp_ordered_metadata_m16n8k8_f32_tf32"); + assert_eq!( + first.source_record.as_deref(), + Some("int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32") + ); + assert_eq!( + first.llvm_symbol.as_deref(), + Some("llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32") + ); + assert_eq!( + first.rust_arguments, + ["[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32"] + ); + assert_eq!(first.rust_result, "[f32; 4]"); + assert_eq!( + first.llvm_arguments, + [ + "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32", "i32", "i32" + ] + ); + assert_eq!(first.minimum_ptx, "8.5"); + assert_eq!(first.minimum_sm.as_deref(), Some("sm_80")); + assert_eq!(first.targets, "all"); + let mma = first.sparse_mma.as_ref().unwrap(); + assert_eq!(mma.selector, SparseMmaSelector::ImmediateZeroThroughThree); + assert_eq!( + mma.adapter, + SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32 + ); + assert_eq!( + mma.llvm_adapter, + SparseMmaLlvmAdapter::A2I32B2I32C4F32MetadataI32SelectorI32ToD4F32 + ); + + // f16 forms carry <2 x half> multiplicands; k32 pairs drop to selector 0-1. + let k32_f16 = &records[6]; + assert_eq!(k32_f16.id, "mma_sp_ordered_metadata_m16n8k32_f16_f16"); + assert_eq!( + k32_f16.llvm_arguments, + [ + "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", + "v2f16", "i32", "i32" + ] + ); + let k32_mma = k32_f16.sparse_mma.as_ref().unwrap(); + assert_eq!(k32_mma.selector, SparseMmaSelector::ImmediateZeroOrOne); + assert_eq!( + k32_mma.adapter, + SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 + ); + + let mut reordered = admission.clone(); + reordered.variants.swap(0, 1); + assert!(expand_sparse_mma_ordered_ampere_float_admission(&reordered).is_err()); + + let mut missing = admission.clone(); + missing.variants.pop(); + assert!(expand_sparse_mma_ordered_ampere_float_admission(&missing).is_err()); + + let mut missing_evidence = admission; + missing_evidence.llvm_evidence_profile.clear(); + assert!(expand_sparse_mma_ordered_ampere_float_admission(&missing_evidence).is_err()); +} + #[test] fn sparse_f8f6f4_f16_candidate_floor_uses_the_resolved_policy() { let policy = expand_sparse_mma_f8f6f4_f16_admission(&test_sparse_mma_f8f6f4_f16_admission()) @@ -1458,7 +1557,7 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { .iter() .filter(|record| record.family == "sparse_mma") .collect::>(); - assert_eq!(records.len(), 114); + assert_eq!(records.len(), 122); assert_eq!( records .iter() @@ -1466,6 +1565,7 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { .collect::>(), (163..=251) .chain(525..=549) + .chain(1017..=1024) .map(|id| format!("i{id:04}")) .collect::>() ); @@ -1494,10 +1594,10 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { assert!(derived_source_records.insert(identity.source_record.clone())); assert!(derived_llvm_symbols.insert(identity.llvm_symbol.clone())); } - assert_eq!(derived_ids.len(), 114); - assert_eq!(derived_operation_keys.len(), 114); - assert_eq!(derived_source_records.len(), 114); - assert_eq!(derived_llvm_symbols.len(), 114); + assert_eq!(derived_ids.len(), 122); + assert_eq!(derived_operation_keys.len(), 122); + assert_eq!(derived_source_records.len(), 122); + assert_eq!(derived_llvm_symbols.len(), 122); let integer_records = records .iter() @@ -1511,7 +1611,16 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { .iter() .copied() .filter(|record| { - record.sparse_mma.as_ref().unwrap().accumulator == SparseMmaAccumulator::F32 + let mma = record.sparse_mma.as_ref().unwrap(); + mma.accumulator == SparseMmaAccumulator::F32 + && matches!( + mma.a_element, + SparseMmaElement::E2m1 + | SparseMmaElement::E2m3 + | SparseMmaElement::E3m2 + | SparseMmaElement::E4m3 + | SparseMmaElement::E5m2 + ) }) .collect::>(); assert_eq!(f32_records.len(), 25); @@ -1519,7 +1628,16 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { .iter() .copied() .filter(|record| { - record.sparse_mma.as_ref().unwrap().accumulator == SparseMmaAccumulator::F16 + let mma = record.sparse_mma.as_ref().unwrap(); + mma.accumulator == SparseMmaAccumulator::F16 + && matches!( + mma.a_element, + SparseMmaElement::E2m1 + | SparseMmaElement::E2m3 + | SparseMmaElement::E3m2 + | SparseMmaElement::E4m3 + | SparseMmaElement::E5m2 + ) }) .collect::>(); assert_eq!(f16_records.len(), 25); @@ -1566,6 +1684,9 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { let mut expected_variants = BTreeSet::new(); for shape in [SparseMmaShape::M16n8k32, SparseMmaShape::M16n8k64] { let metadata = match shape { + SparseMmaShape::M16n8k8 | SparseMmaShape::M16n8k16 => { + unreachable!("integer sparse-MMA test does not enumerate float shapes") + } SparseMmaShape::M16n8k32 => [ Some(SparseMmaMetadata::Standard), Some(SparseMmaMetadata::Ordered), diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs index 946333f7cf..244e1ab97e 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs @@ -48,8 +48,8 @@ fn overlay_manifest_loads_sorted_family_shards() { let (overlay, hash) = read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap(); assert_eq!(overlay.schema, OVERLAY_SCHEMA); - assert_eq!(overlay.shards.len(), 64); - assert_eq!(overlay.intrinsics.len(), 1016); + assert_eq!(overlay.shards.len(), 65); + assert_eq!(overlay.intrinsics.len(), 1024); assert_eq!( overlay .intrinsics @@ -144,7 +144,7 @@ fn overlay_manifest_loads_sorted_family_shards() { .iter() .filter(|record| record.family == "sparse_mma") .count(), - 114 + 122 ); assert_eq!( overlay @@ -264,6 +264,7 @@ fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, @@ -353,6 +354,29 @@ fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() { .contains("requires overlay shard schema 50") ); + let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../.."); + let ampere_float_bytes = + std::fs::read(repo_root.join("intrinsics/overlay/sparse_mma_ordered_ampere_float.toml")) + .unwrap(); + let mut sparse_ampere_float: OverlayShardFile = toml::from_slice(&ere_float_bytes).unwrap(); + assert!( + sparse_ampere_float + .sparse_mma_ordered_ampere_float + .is_some() + ); + assert_eq!( + sparse_ampere_float.schema, + SPARSE_MMA_AMPERE_FLOAT_SHARD_SCHEMA + ); + validate_overlay_shard_schema(&sparse_ampere_float, path).unwrap(); + sparse_ampere_float.schema -= 1; + assert!( + validate_overlay_shard_schema(&sparse_ampere_float, path) + .unwrap_err() + .to_string() + .contains("requires overlay shard schema 63") + ); + let mut standard_fp8_mma = shard(REGISTER_MMA_FP8_SHARD_SCHEMA, None, None); standard_fp8_mma.family = "register_mma".into(); standard_fp8_mma.register_mma_fp8 = Some(test_register_mma_fp8_admission()); @@ -380,6 +404,7 @@ fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: Some(test_fp8_conversion_admission()), packed_conversion_fp8_f16x2: None, @@ -424,6 +449,7 @@ fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, @@ -469,6 +495,7 @@ fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs index 083dc8992e..4b7395a66c 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs @@ -112,6 +112,7 @@ fn special_register_admission_is_closed_and_schema_gated() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs index 811c6abfea..94b14d1877 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs @@ -1184,6 +1184,7 @@ fn tcgen05_compact_schema_is_reserved_for_aggregation() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs index d009b8c020..3ee6c335b2 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs @@ -112,6 +112,7 @@ fn clc_compact_schema_is_reserved_for_aggregation() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, @@ -343,6 +344,7 @@ fn tma_compact_schema_is_reserved_for_aggregation() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, @@ -418,6 +420,7 @@ fn cluster_memory_compact_schema_is_reserved_and_fail_closed() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, diff --git a/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.toml b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.toml new file mode 100644 index 0000000000..c630a4371d --- /dev/null +++ b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.toml @@ -0,0 +1,17 @@ +# SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +[package] +name = "sparse_mma_ordered_float" +version = "0.1.0" +edition = "2024" +authors = ["NVIDIA Corporation"] +license = "Apache-2.0" + +[workspace] + +[dependencies] +cuda-device = { path = "../../../cuda-device" } +cuda-host = { path = "../../../cuda-host" } +cuda-core = { path = "../../../cuda-core" } +half = "2" diff --git a/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs new file mode 100644 index 0000000000..e2e2e55e62 --- /dev/null +++ b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs @@ -0,0 +1,230 @@ +/* SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 */ +//! Nonzero all-lane oracle for all eight ordered sparse floating MMA forms. +use cuda_core::{CudaContext, DeviceBuffer, LaunchConfig}; +use cuda_device::{DisjointSlice, cuda_module, kernel, thread, wmma}; +const META: u32 = 0x4444_4444; +const fn val(x: u32, y: u32) -> u32 { + 1 + ((x + y) & 1) +} +const fn h(x: u32) -> u32 { + if x == 1 { 0x3c00 } else { 0x4000 } +} +const fn b(x: u32) -> u32 { + if x == 1 { 0x3f80 } else { 0x4000 } +} +const fn t(x: u32) -> u32 { + if x == 1 { 0x3f80_0000 } else { 0x4000_0000 } +} +const fn pk(x: u32, y: u32) -> u32 { + x | (y << 16) +} + +#[cuda_module] +mod kernels { + use super::*; + fn aa(l: u32, n: u32, bf: u32) -> u32 { + let r = l / 4 + 8 * (n & 1); + let q = (l & 3) * 2 + 8 * (n / 2); + let x = val(r, q); + let y = val(r, q + 1); + if bf == 0 { + pk(h(x), h(y)) + } else { + pk(b(x), b(y)) + } + } + fn bb(l: u32, n: u32, bf: u32) -> u32 { + let c = l / 4; + let k = (l & 3) * 2 + 8 * n; + let x = val(k, c); + let y = val(k + 1, c); + if bf == 0 { + pk(h(x), h(y)) + } else { + pk(b(x), b(y)) + } + } + fn at(l: u32, n: u32) -> u32 { + let r = l / 4 + 8 * (n & 1); + let q = (l & 3) + 4 * (n / 2); + t(val(r, q)) + } + fn bt(l: u32, n: u32) -> u32 { + t(val((l & 3) + 4 * n, l / 4)) + } + fn cp(l: u32, n: u32) -> u32 { + let r = l / 4 + 8 * n; + let c = (l & 3) * 2; + pk(h(val(r, c)), h(val(r, c + 1))) + } + fn cf(l: u32) -> [f32; 4] { + let r = l / 4; + let c = (l & 3) * 2; + [ + val(r, c) as f32, + val(r, c + 1) as f32, + val(r + 8, c) as f32, + val(r + 8, c + 1) as f32, + ] + } + #[kernel] + pub fn oracle(mut po: DisjointSlice, mut fo: DisjointSlice) { + let l = thread::threadIdx_x(); + let c = [cp(l, 0), cp(l, 1)]; + let f = cf(l); + let (h16, h32, x16, x32, y16, y32, z8, z16) = unsafe { + ( + wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16( + c, + [aa(l, 0, 0), aa(l, 1, 0)], + [bb(l, 0, 0), bb(l, 1, 0)], + META, + 0, + ), + wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16( + c, + [aa(l, 0, 0), aa(l, 1, 0), aa(l, 2, 0), aa(l, 3, 0)], + [bb(l, 0, 0), bb(l, 1, 0), bb(l, 2, 0), bb(l, 3, 0)], + META, + 0, + ), + wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16( + f, + [aa(l, 0, 0), aa(l, 1, 0)], + [bb(l, 0, 0), bb(l, 1, 0)], + META, + 0, + ), + wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16( + f, + [aa(l, 0, 0), aa(l, 1, 0), aa(l, 2, 0), aa(l, 3, 0)], + [bb(l, 0, 0), bb(l, 1, 0), bb(l, 2, 0), bb(l, 3, 0)], + META, + 0, + ), + wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16( + f, + [aa(l, 0, 1), aa(l, 1, 1)], + [bb(l, 0, 1), bb(l, 1, 1)], + META, + 0, + ), + wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16( + f, + [aa(l, 0, 1), aa(l, 1, 1), aa(l, 2, 1), aa(l, 3, 1)], + [bb(l, 0, 1), bb(l, 1, 1), bb(l, 2, 1), bb(l, 3, 1)], + META, + 0, + ), + wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32( + f, + [at(l, 0), at(l, 1)], + [bt(l, 0), bt(l, 1)], + META, + 0, + ), + wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32( + f, + [at(l, 0), at(l, 1), at(l, 2), at(l, 3)], + [bt(l, 0), bt(l, 1), bt(l, 2), bt(l, 3)], + META, + 0, + ), + ) + }; + let p = l as usize * 4; + for (i, v) in h16.into_iter().chain(h32).enumerate() { + unsafe { *po.get_unchecked_mut(p + i) = v } + } + let p = l as usize * 24; + for (i, v) in x16 + .into_iter() + .chain(x32) + .chain(y16) + .chain(y32) + .chain(z8) + .chain(z16) + .enumerate() + { + unsafe { *fo.get_unchecked_mut(p + i) = v } + } + } +} +fn rc(l: usize, r: usize) -> (usize, usize) { + (l / 4 + 8 * (r / 2), (l % 4) * 2 + r % 2) +} +fn reference(r: usize, c: usize, kdim: usize) -> u32 { + let mut s = val(r as u32, c as u32); + for k in 0..kdim { + if k % 4 < 2 { + let q = (k / 4) * 2 + k % 4; + s += val(r as u32, q as u32) * val(k as u32, c as u32) + } + } + s +} +fn reference_tf32(r: usize, c: usize, kdim: usize) -> u32 { + let mut s = val(r as u32, c as u32); + for k in 0..kdim { + if k % 2 == 0 { + s += val(r as u32, (k / 2) as u32) * val(k as u32, c as u32) + } + } + s +} +fn main() { + let ctx = CudaContext::new(0).expect("CUDA context"); + let (major, minor) = ctx.compute_capability().unwrap(); + if major < 8 { + println!("skip sm_{major}{minor}"); + return; + } + let s = ctx.default_stream(); + let m = kernels::load(&ctx).expect("module"); + let mut pd = DeviceBuffer::::zeroed(&s, 128).unwrap(); + let mut fd = DeviceBuffer::::zeroed(&s, 768).unwrap(); + let cfg = LaunchConfig { + block_dim: (32, 1, 1), + grid_dim: (1, 1, 1), + shared_mem_bytes: 0, + }; + unsafe { m.oracle(&s, cfg, &mut pd, &mut fd) }.unwrap(); + let p = pd.to_host_vec(&s).unwrap(); + let f = fd.to_host_vec(&s).unwrap(); + let mut bad = 0; + for l in 0..32 { + for v in 0..2 { + for r in 0..4 { + let w = p[l * 4 + v * 2 + r / 2]; + let got = if r % 2 == 0 { w & 0xffff } else { w >> 16 }; + let (x, y) = rc(l, r); + let want = + half::f16::from_f32(reference(x, y, [16, 32][v]) as f32).to_bits() as u32; + if got != want { + eprintln!("f16 variant {v} lane {l} reg {r}: {got:#x} != {want:#x}"); + bad += 1 + } + } + } + for v in 0..6 { + for r in 0..4 { + let got = f[l * 24 + v * 4 + r]; + let (x, y) = rc(l, r); + let want = if v < 4 { + reference(x, y, [16, 32, 16, 32][v]) + } else { + reference_tf32(x, y, [8, 16][v - 4]) + } as f32; + if got != want { + eprintln!("f32 variant {v} lane {l} reg {r}: {got} != {want}"); + bad += 1 + } + } + } + } + assert_eq!(bad, 0, "accumulator mismatches"); + println!( + "SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM" + ) +} diff --git a/intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json b/intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json new file mode 100644 index 0000000000..5b8d1a927e --- /dev/null +++ b/intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json @@ -0,0 +1,32 @@ +{ + "schema": 6, + "backend_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", + "backend_kind": "lib_nvvm", + "llvm_revision": "not-applicable-libnvvm-ir-2.0", + "backend_version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", + "backend_sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", + "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", + "nvvm_ir_version": "2.0", + "debug_ir_version": "3.1", + "defaults": {"target_triple":"nvptx64-nvidia-cuda","gpu_target":"compute_80","ptx_feature":"CUDA 12.9 emits PTX ISA 8.8; reviewed forms require PTX 8.5","status":"executed","runtime_validation":"executed"}, + "fixtures": [{ + "id": "ordered_ampere_float_all", + "coverage_count": 8, + "stages": [ + {"targets":["compute_80","ptx88"],"representation":"eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0","stage":"backend_codegen","mechanism":"inline_ptx","outcome":"succeeded","detail":"CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987)."}, + {"targets":["sm_80","ptx88"],"representation":"CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms","stage":"ptx_assembly","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.","tool_path":"/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas","tool_version":"CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0","tool_sha256":"fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73"}, + {"targets":["sm_80","ptx88"],"representation":"the 4,740-byte all-variant libNVVM LTOIR linked for sm_80","stage":"device_link","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.","tool_path":"/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86","tool_version":"CUDA 12.9 nvJitLink V12.9.86","tool_sha256":"71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622"}, + {"targets":["sm_120","ptx88"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Measured on NVIDIA GeForce RTX 5080 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 12.9 V12.9.86. Command: CUDA_TOOLKIT_PATH=/home/sam/Workspaces/dinov3-candle/.pixi/envs/default cargo oxide run sparse_mma_ordered_float --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM."} + ] + }], + "matrices": [ + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k8_f32_tf32"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k8","row","col","f32","tf32","tf32","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f32_tf32"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_tf32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.tf32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f32","tf32","tf32","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f32_bf16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_bf16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.bf16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f32","bf16","bf16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f16_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f16_f16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f16.f16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f16","f16","f16","f16"],"operands":[{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","i32","i32"],"llvm_results":["v2f16","v2f16"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f32_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f32_f32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f32.f32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f32","f16","f16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f32_bf16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f32","bf16","bf16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f16_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f16","f16","f16","f16"],"operands":[{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","i32","i32"],"llvm_results":["v2f16","v2f16"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f32_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f32","f16","f16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}} + ] +} diff --git a/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json b/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json new file mode 100644 index 0000000000..c361a7377e --- /dev/null +++ b/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json @@ -0,0 +1,28 @@ +{ + "schema": 6, + "backend_profile": "rust-llvm-23.1.0-16696adc", + "backend_kind": "llvm_nvptx", + "llvm_revision": "16696adcd119e6ba9cc175207d984d7021211acb", + "backend_version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "backend_sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "defaults": {"target_triple":"nvptx64-nvidia-cuda","gpu_target":"sm_80","ptx_feature":"+ptx85","status":"executed","runtime_validation":"executed"}, + "fixtures": [{ + "id": "ordered_ampere_float_all", + "coverage_count": 8, + "stages": [ + {"targets":["sm_80","ptx85"],"representation":"eight typed LLVM declarations lowered through the selected convergent inline-PTX route","stage":"backend_codegen","mechanism":"inline_ptx","outcome":"succeeded","detail":"Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded."}, + {"targets":["sm_80","ptx85"],"representation":"exact-floor PTX containing all eight ordered sparse floating MMA forms","stage":"ptx_assembly","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.","tool_path":"/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas","tool_version":"CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0","tool_sha256":"fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73"}, + {"targets":["sm_120","ptx85"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Measured on NVIDIA GeForce RTX 5080 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 12.9 V12.9.86. Command: CUDA_TOOLKIT_PATH=/home/sam/Workspaces/dinov3-candle/.pixi/envs/default cargo oxide run sparse_mma_ordered_float --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM."} + ] + }], + "matrices": [ + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k8_f32_tf32"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k8","row","col","f32","tf32","tf32","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f32_tf32"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_tf32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.tf32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f32","tf32","tf32","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f32_bf16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_bf16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.bf16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f32","bf16","bf16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f16_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f16_f16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f16.f16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f16","f16","f16","f16"],"operands":[{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","i32","i32"],"llvm_results":["v2f16","v2f16"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f32_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f32_f32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f32.f32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f32","f16","f16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f32_bf16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f32","bf16","bf16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f16_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f16","f16","f16","f16"],"operands":[{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","i32","i32"],"llvm_results":["v2f16","v2f16"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f32_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f32","f16","f16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}} + ] +} diff --git a/intrinsics/overlay.toml b/intrinsics/overlay.toml index 35e5442674..17d0d32670 100644 --- a/intrinsics/overlay.toml +++ b/intrinsics/overlay.toml @@ -48,6 +48,7 @@ shards = [ "overlay/sparse_mma_int4_m16n8k64.toml", "overlay/sparse_mma_int8.toml", "overlay/sparse_mma_int8_m16n8k64.toml", + "overlay/sparse_mma_ordered_ampere_float.toml", "overlay/sparse_mma_ordered_f8f6f4_f16.toml", "overlay/sparse_mma_ordered_f8f6f4_f32.toml", "overlay/sparse_mma_ordered_int4_m16n8k128.toml", diff --git a/intrinsics/overlay/sparse_mma_ordered_ampere_float.toml b/intrinsics/overlay/sparse_mma_ordered_ampere_float.toml new file mode 100644 index 0000000000..58b3280a6e --- /dev/null +++ b/intrinsics/overlay/sparse_mma_ordered_ampere_float.toml @@ -0,0 +1,49 @@ +# Reviewed ordered-metadata sparse Ampere floating-point register-MMA family. + +schema = 63 +family = "sparse_mma" + +[sparse_mma_ordered_ampere_float] +llvm_evidence_profile = "rust-llvm-23.1.0-16696adc" +libnvvm_evidence_profile = "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float" +runtime_validation = "executed" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k8" +accumulator = "f32" +element = "tf32" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k16" +accumulator = "f32" +element = "tf32" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k16" +accumulator = "f32" +element = "bf16" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k16" +accumulator = "f16" +element = "f16" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k16" +accumulator = "f32" +element = "f16" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k32" +accumulator = "f32" +element = "bf16" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k32" +accumulator = "f16" +element = "f16" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k32" +accumulator = "f32" +element = "f16" From d8f8ede9273f82d5579bc50169ab39ede1eb8ec1 Mon Sep 17 00:00:00 2001 From: nihalpasham Date: Sun, 30 Aug 2026 15:11:10 +0530 Subject: [PATCH 2/5] test(sparse-mma): make the float oracle asymmetric, selector-routed, and multi-code The ported oracle was parity-degenerate: val(x,y) = 1 + ((x+y) & 1) made the A and B fragments bitwise identical in every lane across all eight variants, metadata was the single code 0x4 repeated, and the selector was always 0. An a<->b template swap, a hardwired selector, or a metadata misroute all still passed. Rework: - A, B, C are positionally distinct and asymmetric (A = 1+(3r+5j)%7, B = 1+(2k+3c)%8, C = (5r+7c)%32), small enough that f16/bf16/tf32 accumulation stays exact and the host reference is pure integer math - every valid ordered metadata code executes (0x4/0x8/0x9/0xc/0xd/0xe cycling by row+chunk; tf32 alternates 0x4/0xe with an aperiodic index so no wrong (lane, nibble) -> (row, chunk) reading aliases to the truth) - each selector domain runs a nonzero selector (2/1/3 in the 0-3 domain, 1 in the 0-1 domain) and non-selected lanes carry a valid decoy pattern, so selector misrouting changes the result - pair-selector shapes (k32 f16/bf16, k16 tf32) split the K dimension across the thread pair while keeping the [row g | row g+8] register halves; verified against sm_120 hardware, where a row-per-thread split fails the oracle - the sub-sm_80 skip message now uses the harness "skipping: ..." form Mutation check on an RTX 5090 (cc 12.0): swapping the a/b arguments of one variant fails 127 of its 128 checked accumulators; reverted, all 8 variants pass and compute-sanitizer memcheck reports 0 errors. The evidence runtime stages now record this re-measured run. Signed-off-by: nihalpasham --- .../sparse_mma_ordered_float/Cargo.lock | 558 ++++++++++++++++++ .../sparse_mma_ordered_float/Cargo.toml | 1 - .../sparse_mma_ordered_float/src/main.rs | 285 ++++++--- ....9.86-sparse-mma-ordered-ampere-float.json | 2 +- ...96adc-sparse-mma-ordered-ampere-float.json | 2 +- 5 files changed, 763 insertions(+), 85 deletions(-) create mode 100644 crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.lock diff --git a/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.lock b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.lock new file mode 100644 index 0000000000..18dd218e61 --- /dev/null +++ b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.lock @@ -0,0 +1,558 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 4 + +[[package]] +name = "aho-corasick" +version = "1.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c982642fa9e8606056828ee9a8505737230110bb1099153c79efe865c59d12ba" +dependencies = [ + "memchr", +] + +[[package]] +name = "anyhow" +version = "1.0.104" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "330a5ed07fa54e4702c9d6c4174f74427fc0ef6e214bbd677ae50a5099946470" + +[[package]] +name = "bindgen" +version = "0.71.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5f58bf3d7db68cfbac37cfc485a8d711e87e064c3d0fe0435b92f7a407f9d6b3" +dependencies = [ + "bitflags", + "cexpr", + "clang-sys", + "itertools", + "log", + "prettyplease", + "proc-macro2", + "quote", + "regex", + "rustc-hash", + "shlex", + "syn 2.0.119", +] + +[[package]] +name = "bitflags" +version = "2.13.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b588b76d00fde79687d7646a9b5bdf3cc0f655e0bbd080335a95d7e96f3587da" + +[[package]] +name = "block-buffer" +version = "0.10.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3078c7629b62d3f0439517fa394996acacc5cbc91c5a20d8c658e77abd503a71" +dependencies = [ + "generic-array", +] + +[[package]] +name = "cexpr" +version = "0.6.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6fac387a98bb7c37292057cffc56d62ecb629900026402633ae9160df93a8766" +dependencies = [ + "nom", +] + +[[package]] +name = "cfg-if" +version = "1.0.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" + +[[package]] +name = "clang-sys" +version = "1.9.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "157a8ba7b480713b56f4c09fd13fc3e0a22a5dfab8097ba61cbc5feef950788a" +dependencies = [ + "glob", + "libc", + "libloading", +] + +[[package]] +name = "cpufeatures" +version = "0.2.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "59ed5838eebb26a2bb2e58f6d5b5316989ae9d08bab10e0e6d103e656d1b0280" +dependencies = [ + "libc", +] + +[[package]] +name = "crc32fast" +version = "1.5.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8498c871161e1742aaa9d52551b2d6ebdd4c3d45a3be423e3728f33b955be550" +dependencies = [ + "cfg-if", +] + +[[package]] +name = "crunchy" +version = "0.2.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "460fbee9c2c2f33933d720630a6a0bac33ba7053db5344fac858d4b8952d77d5" + +[[package]] +name = "crypto-common" +version = "0.1.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "78c8292055d1c1df0cce5d180393dc8cce0abec0a7102adb6c7b1eef6016d60a" +dependencies = [ + "generic-array", + "typenum", +] + +[[package]] +name = "cuda-artifact-finalizer" +version = "0.2.1" +dependencies = [ + "libnvvm-sys", + "nvjitlink-sys", + "serde", + "sha2", + "thiserror", +] + +[[package]] +name = "cuda-bindings" +version = "0.2.1" +dependencies = [ + "bindgen", +] + +[[package]] +name = "cuda-core" +version = "0.2.1" +dependencies = [ + "anyhow", + "cuda-bindings", + "cuda-macros", + "half", + "oxide-artifacts", +] + +[[package]] +name = "cuda-device" +version = "0.2.1" +dependencies = [ + "cuda-macros", +] + +[[package]] +name = "cuda-host" +version = "0.2.1" +dependencies = [ + "cuda-artifact-finalizer", + "cuda-core", + "cuda-macros", + "half", + "ptx-parse", + "sha2", + "thiserror", +] + +[[package]] +name = "cuda-macros" +version = "0.2.1" +dependencies = [ + "proc-macro2", + "quote", + "reserved-oxide-symbols", + "syn 2.0.119", +] + +[[package]] +name = "cuda-target-spec" +version = "0.1.0" + +[[package]] +name = "digest" +version = "0.10.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9ed9a281f7bc9b7576e61468ba615a66a5c8cfdff42420a70aa82701a3b1e292" +dependencies = [ + "block-buffer", + "crypto-common", +] + +[[package]] +name = "either" +version = "1.18.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "252afb9ae5eaa683babdc6a068b3f5726eb19e05070c731f9b2a23a7c3e8ed34" + +[[package]] +name = "equivalent" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f" + +[[package]] +name = "foldhash" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2" + +[[package]] +name = "generic-array" +version = "0.14.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "85649ca51fd72272d7821adaf274ad91c288277713d9c18820d8499a7ff69e9a" +dependencies = [ + "typenum", + "version_check", +] + +[[package]] +name = "glob" +version = "0.3.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e4eba85ea1d0a966a983acd07deee566e67395d2d96b6fb39e62b5a833f1eb0b" + +[[package]] +name = "half" +version = "2.7.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6ea2d84b969582b4b1864a92dc5d27cd2b77b622a8d79306834f1be5ba20d84b" +dependencies = [ + "cfg-if", + "crunchy", + "zerocopy", +] + +[[package]] +name = "hashbrown" +version = "0.15.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9229cfe53dfd69f0609a49f65461bd93001ea1ef889cd5529dd176593f5338a1" +dependencies = [ + "foldhash", +] + +[[package]] +name = "hashbrown" +version = "0.17.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ed5909b6e89a2db4456e54cd5f673791d7eca6732202bbf2a9cc504fe2f9b84a" + +[[package]] +name = "indexmap" +version = "2.14.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "07aa2048142242915a31d35844fb311e0e53fcca590c3a0a40dcf1b841fa09eb" +dependencies = [ + "equivalent", + "hashbrown 0.17.1", +] + +[[package]] +name = "itertools" +version = "0.13.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "413ee7dfc52ee1a4949ceeb7dbc8a33f2d6c088194d9f922fb8318faf1f01186" +dependencies = [ + "either", +] + +[[package]] +name = "libc" +version = "0.2.189" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3eaf3ede3fee6db1a4c2ee091bf8a8b4dccdc6d17f656fb07896ee72867612f2" + +[[package]] +name = "libloading" +version = "0.8.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d7c4b02199fee7c5d21a5ae7d8cfa79a6ef5bb2fc834d6e9058e89c825efdc55" +dependencies = [ + "cfg-if", + "windows-link", +] + +[[package]] +name = "libnvvm-sys" +version = "0.2.1" +dependencies = [ + "cuda-target-spec", + "libloading", + "thiserror", +] + +[[package]] +name = "log" +version = "0.4.34" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f9f8bd3e56ce4dfc153cf470fffbfa98c7620958b312ca5c3a4b8d5181fd13c6" + +[[package]] +name = "memchr" +version = "2.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cf8baf1c55e62ffcace7a9f06f4bd9cd3f0c4beb022d3b367256b91b87513d98" + +[[package]] +name = "minimal-lexical" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "68354c5c6bd36d73ff3feceb05efa59b6acb7626617f4962be322a825e61f79a" + +[[package]] +name = "nom" +version = "7.1.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d273983c5a657a70a3e8f2a01329822f3b8c8172b73826411a55751e404a0a4a" +dependencies = [ + "memchr", + "minimal-lexical", +] + +[[package]] +name = "nvjitlink-sys" +version = "0.2.1" +dependencies = [ + "libloading", + "thiserror", +] + +[[package]] +name = "object" +version = "0.36.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "62948e14d923ea95ea2c7c86c71013138b66525b86bdc08d2dcc262bdb497b87" +dependencies = [ + "crc32fast", + "hashbrown 0.15.5", + "indexmap", + "memchr", +] + +[[package]] +name = "oxide-artifacts" +version = "0.2.1" +dependencies = [ + "object", +] + +[[package]] +name = "prettyplease" +version = "0.2.37" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "479ca8adacdd7ce8f1fb39ce9ecccbfe93a3f1344b3d0d97f20bc0196208f62b" +dependencies = [ + "proc-macro2", + "syn 2.0.119", +] + +[[package]] +name = "proc-macro2" +version = "1.0.107" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "985e7ec9bb745e6ce6535b544d84d6cd6f7ad8bd711c398938ae983b91a766d9" +dependencies = [ + "unicode-ident", +] + +[[package]] +name = "ptx-parse" +version = "0.1.0" + +[[package]] +name = "quote" +version = "1.0.47" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1fbf4db142a473a8d80c26bbf18454ed458bf8d26c8219c331daecfdbd079001" +dependencies = [ + "proc-macro2", +] + +[[package]] +name = "regex" +version = "1.13.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f020237b6c8eed93db2e2cb53c00c60a8e1bc73da7d073199a1180401450218d" +dependencies = [ + "aho-corasick", + "memchr", + "regex-automata", + "regex-syntax", +] + +[[package]] +name = "regex-automata" +version = "0.4.18" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ad8553b9b26413251cbf30e620595c7a41b3887f03da04579c0e6b0d6a06b4b2" +dependencies = [ + "aho-corasick", + "memchr", + "regex-syntax", +] + +[[package]] +name = "regex-syntax" +version = "0.8.11" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d6f6ff9a378485b298a5286656da665ba74413d36db0979633275d2e708145d4" + +[[package]] +name = "reserved-oxide-symbols" +version = "0.2.1" + +[[package]] +name = "rustc-hash" +version = "2.1.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6b1e7f9a428571be2dc5bc0505c13fb6bf936822b894ec87abf8a08a4e51742d" + +[[package]] +name = "serde" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "4148590afebada386688f18773da617792bf2ef03ffc1e4cbd2b1d45b023e0ba" +dependencies = [ + "serde_core", + "serde_derive", +] + +[[package]] +name = "serde_core" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "67dca2c9c51e58a4791a4b1ed58308b39c64224d349a935ab5039aa360942a48" +dependencies = [ + "serde_derive", +] + +[[package]] +name = "serde_derive" +version = "1.0.229" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e7a5d71263a5a7d47b41f6b3f06ba276f10cc18b0931f1799f710578e2309348" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.4", +] + +[[package]] +name = "sha2" +version = "0.10.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a7507d819769d01a365ab707794a4084392c824f54a7a6a7862f8c3d0892b283" +dependencies = [ + "cfg-if", + "cpufeatures", + "digest", +] + +[[package]] +name = "shlex" +version = "1.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64" + +[[package]] +name = "sparse_mma_ordered_float" +version = "0.1.0" +dependencies = [ + "cuda-core", + "cuda-device", + "cuda-host", +] + +[[package]] +name = "syn" +version = "2.0.119" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "872831b642d1a07999a962a351ed35b955ea2cfc8f3862091e2a240a84f17297" +dependencies = [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name = "syn" +version = "3.0.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e6275cddf4610d1775e6d1fe9469b2e77d0f39fd98fb7450901b821e0c53649f" +dependencies = [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name = "thiserror" +version = "2.0.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ec86235f5fcc2a73650310756d2ac5b138a5780bbbdfae3eeccec992c435ba4f" +dependencies = [ + "thiserror-impl", +] + +[[package]] +name = "thiserror-impl" +version = "2.0.20" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bc04cd3e1236dd4a98afca4569f2deb3f120e5422a4023be2cb683f8486292af" +dependencies = [ + "proc-macro2", + "quote", + "syn 3.0.4", +] + +[[package]] +name = "typenum" +version = "1.20.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b6f5e870be6c3b371b77fe0ee0bafb859fa4964b4404c27de1d380043c4dda20" + +[[package]] +name = "unicode-ident" +version = "1.0.24" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75" + +[[package]] +name = "version_check" +version = "0.9.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0b928f33d975fc6ad9f86c8f283853ad26bdd5b10b7f1542aa2fa15e2289105a" + +[[package]] +name = "windows-link" +version = "0.2.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5" + +[[package]] +name = "zerocopy" +version = "0.8.56" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "556764e583adb45a9f8d413c2a147fa7e8d821e48e12b14fd560b607998b75eb" +dependencies = [ + "zerocopy-derive", +] + +[[package]] +name = "zerocopy-derive" +version = "0.8.56" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f2ab42fc20575779bd240faa45f94a74256f755c0fa9e89f0ede20d91d0cdfc1" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.119", +] diff --git a/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.toml b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.toml index c630a4371d..2fec903d7c 100644 --- a/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.toml +++ b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/Cargo.toml @@ -14,4 +14,3 @@ license = "Apache-2.0" cuda-device = { path = "../../../cuda-device" } cuda-host = { path = "../../../cuda-host" } cuda-core = { path = "../../../cuda-core" } -half = "2" diff --git a/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs index e2e2e55e62..68086277eb 100644 --- a/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs +++ b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs @@ -1,73 +1,180 @@ /* SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: Apache-2.0 */ -//! Nonzero all-lane oracle for all eight ordered sparse floating MMA forms. +//! GPU oracle for all eight ordered sparse floating MMA forms. +//! +//! Why the inputs look the way they do: +//! - the first cut of this oracle used val(x,y) = 1 + ((x+y) & 1); that +//! parity pattern made the A and B fragments bitwise IDENTICAL in every +//! lane, so an a<->b swap in the lowering still passed: +//! +//! ```text +//! old: A[r][q] = f(r+q) B[k][c] = f(k+c) -> same lane bytes +//! new: A[r][j] = 1+(3r+5j)%7, B[k][c] = 1+(2k+3c)%8 -> distinct +//! ``` +//! +//! - metadata is no longer the single code 0x4: every valid ordered code +//! (0x4 0x8 0x9 0xc 0xd 0xe; tf32: 0x4 0xe) cycles by (row+chunk), so a +//! metadata misroute picks different B rows and the sum changes; +//! - each selector domain runs a NONZERO selector (2/1/3 for the 0-3 forms, +//! 1 for the 0-1 forms), and non-selected lanes carry a valid DECOY +//! pattern (every code bumped one table slot), so reading the wrong +//! lane's metadata register also changes the result; +//! - values stay small (A<=7, B<=8, C<=31, sums < 1024) so f16, bf16, and +//! tf32 all accumulate exactly and the host reference is integer math. use cuda_core::{CudaContext, DeviceBuffer, LaunchConfig}; use cuda_device::{DisjointSlice, cuda_module, kernel, thread, wmma}; -const META: u32 = 0x4444_4444; -const fn val(x: u32, y: u32) -> u32 { - 1 + ((x + y) & 1) + +// Positionally distinct inputs: A over compressed (row, j), B over (k, col). +const fn a_val(r: u32, j: u32) -> u32 { + 1 + ((3 * r + 5 * j) % 7) } -const fn h(x: u32) -> u32 { - if x == 1 { 0x3c00 } else { 0x4000 } +const fn b_val(k: u32, c: u32) -> u32 { + 1 + ((2 * k + 3 * c) % 8) } -const fn b(x: u32) -> u32 { - if x == 1 { 0x3f80 } else { 0x4000 } +const fn c_val(r: u32, c: u32) -> u32 { + (5 * r + 7 * c) % 32 } -const fn t(x: u32) -> u32 { - if x == 1 { 0x3f80_0000 } else { 0x4000_0000 } + +// Ordered metadata code for (row, chunk); bump=1 yields the decoy pattern +// (next code in the table) handed to non-selected lanes. +// tf=0: f16/bf16 6-code table; tf=1: tf32 2-code table. +// The tf32 index mixes r/8 and g/3 so no wrong (lane, nibble) -> (row, chunk) +// reading can reproduce the true pattern by periodicity (rows 8 apart and +// chunks 4 apart would otherwise alias under a plain (r+g) parity). +const fn meta_code(r: u32, g: u32, bump: u32, tf: u32) -> u32 { + if tf == 1 { + if (r + r / 8 + g + g / 3 + bump) & 1 == 0 { + 0x4 + } else { + 0xe + } + } else { + match (r + g + bump) % 6 { + 0 => 0x4, + 1 => 0x8, + 2 => 0x9, + 3 => 0xc, + 4 => 0xd, + _ => 0xe, + } + } } -const fn pk(x: u32, y: u32) -> u32 { - x | (y << 16) + +// Exact bit patterns for small integers (all values here fit losslessly). +const fn f32_bits(x: u32) -> u32 { + if x == 0 { + return 0; + } + let mut e = 0; + while (x >> e) > 1 { + e += 1; + } + ((127 + e) << 23) | ((x << (23 - e)) & 0x007f_ffff) +} +const fn f16_bits(x: u32) -> u32 { + if x == 0 { + return 0; + } + let mut e = 0; + while (x >> e) > 1 { + e += 1; + } + ((15 + e) << 10) | ((x << (10 - e)) & 0x03ff) +} +const fn bf16_bits(x: u32) -> u32 { + f32_bits(x) >> 16 +} +const fn pack(lo: u32, hi: u32) -> u32 { + lo | (hi << 16) } #[cuda_module] mod kernels { use super::*; - fn aa(l: u32, n: u32, bf: u32) -> u32 { + + // f16/bf16 A fragment register n: row l/4 (+8 for odd n), + // compressed cols (l%4)*2 + 8*(n/2) and +1, packed lo/hi. + fn af(l: u32, n: u32, bf: u32) -> u32 { let r = l / 4 + 8 * (n & 1); - let q = (l & 3) * 2 + 8 * (n / 2); - let x = val(r, q); - let y = val(r, q + 1); - if bf == 0 { - pk(h(x), h(y)) + let j = (l & 3) * 2 + 8 * (n / 2); + if bf == 1 { + pack(bf16_bits(a_val(r, j)), bf16_bits(a_val(r, j + 1))) } else { - pk(b(x), b(y)) + pack(f16_bits(a_val(r, j)), f16_bits(a_val(r, j + 1))) } } - fn bb(l: u32, n: u32, bf: u32) -> u32 { + // f16/bf16 B fragment register n: col l/4, rows (l%4)*2 + 8n and +1. + fn bf(l: u32, n: u32, b16: u32) -> u32 { let c = l / 4; let k = (l & 3) * 2 + 8 * n; - let x = val(k, c); - let y = val(k + 1, c); - if bf == 0 { - pk(h(x), h(y)) + if b16 == 1 { + pack(bf16_bits(b_val(k, c)), bf16_bits(b_val(k + 1, c))) } else { - pk(b(x), b(y)) + pack(f16_bits(b_val(k, c)), f16_bits(b_val(k + 1, c))) } } + // tf32 A fragment register n: row l/4 (+8 odd n), compressed col (l%4)+4*(n/2). fn at(l: u32, n: u32) -> u32 { - let r = l / 4 + 8 * (n & 1); - let q = (l & 3) + 4 * (n / 2); - t(val(r, q)) + f32_bits(a_val(l / 4 + 8 * (n & 1), (l & 3) + 4 * (n / 2))) } + // tf32 B fragment register n: row (l%4)+4n, col l/4. fn bt(l: u32, n: u32) -> u32 { - t(val((l & 3) + 4 * n, l / 4)) - } - fn cp(l: u32, n: u32) -> u32 { - let r = l / 4 + 8 * n; - let c = (l & 3) * 2; - pk(h(val(r, c)), h(val(r, c + 1))) + f32_bits(b_val((l & 3) + 4 * n, l / 4)) } + // f32 accumulator quad: rows l/4, l/4+8; cols (l%4)*2, +1. fn cf(l: u32) -> [f32; 4] { let r = l / 4; let c = (l & 3) * 2; [ - val(r, c) as f32, - val(r, c + 1) as f32, - val(r + 8, c) as f32, - val(r + 8, c + 1) as f32, + c_val(r, c) as f32, + c_val(r, c + 1) as f32, + c_val(r + 8, c) as f32, + c_val(r + 8, c + 1) as f32, ] } + // packed f16 accumulator register n: row l/4+8n, cols (l%4)*2, +1. + fn cp(l: u32, n: u32) -> u32 { + let r = l / 4 + 8 * n; + let c = (l & 3) * 2; + pack(f16_bits(c_val(r, c)), f16_bits(c_val(r, c + 1))) + } + // One metadata thread per quad (k16 f16/bf16, k8 tf32; 4 chunks/row): + // bits [15:0] row g, bits [31:16] row g+8, nibble j = chunk j. + // Only lane l%4 == sel carries the real pattern; the rest carry the decoy. + fn meta_one(l: u32, sel: u32, tf: u32) -> u32 { + let g = l / 4; + let bump = if l % 4 == sel { 0 } else { 1 }; + let mut m = 0; + let mut j = 0; + while j < 4 { + m |= meta_code(g, j, bump, tf) << (4 * j); + m |= meta_code(g + 8, j, bump, tf) << (16 + 4 * j); + j += 1; + } + m + } + // Metadata thread pair per quad (k32 f16/bf16, k16 tf32; 8 chunks/row): + // selector s picks lanes {2s, 2s+1} of the quad, and the pair splits + // the K dimension, keeping the one-thread [row g | row g+8] register + // split (verified against sm_120 hardware; a row-per-thread split + // fails the oracle): + // + // lane 2s+t: bits [15:0] row g chunks 4t..4t+3 + // bits [31:16] row g+8 chunks 4t..4t+3 + fn meta_pair(l: u32, sel: u32, tf: u32) -> u32 { + let g = l / 4; + let t = (l & 3) % 2; + let bump = if (l & 3) / 2 == sel { 0 } else { 1 }; + let mut m = 0; + let mut j = 0; + while j < 4 { + m |= meta_code(g, 4 * t + j, bump, tf) << (4 * j); + m |= meta_code(g + 8, 4 * t + j, bump, tf) << (16 + 4 * j); + j += 1; + } + m + } + #[kernel] pub fn oracle(mut po: DisjointSlice, mut fo: DisjointSlice) { let l = thread::threadIdx_x(); @@ -75,61 +182,63 @@ mod kernels { let f = cf(l); let (h16, h32, x16, x32, y16, y32, z8, z16) = unsafe { ( + // selector domains: k16 f16/bf16 and k8 tf32 accept 0-3, + // k32 and k16 tf32 accept 0-1; every domain runs a nonzero one. wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16( c, - [aa(l, 0, 0), aa(l, 1, 0)], - [bb(l, 0, 0), bb(l, 1, 0)], - META, - 0, + [af(l, 0, 0), af(l, 1, 0)], + [bf(l, 0, 0), bf(l, 1, 0)], + meta_one(l, 2, 0), + 2, ), wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16( c, - [aa(l, 0, 0), aa(l, 1, 0), aa(l, 2, 0), aa(l, 3, 0)], - [bb(l, 0, 0), bb(l, 1, 0), bb(l, 2, 0), bb(l, 3, 0)], - META, + [af(l, 0, 0), af(l, 1, 0), af(l, 2, 0), af(l, 3, 0)], + [bf(l, 0, 0), bf(l, 1, 0), bf(l, 2, 0), bf(l, 3, 0)], + meta_pair(l, 0, 0), 0, ), wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16( f, - [aa(l, 0, 0), aa(l, 1, 0)], - [bb(l, 0, 0), bb(l, 1, 0)], - META, - 0, + [af(l, 0, 0), af(l, 1, 0)], + [bf(l, 0, 0), bf(l, 1, 0)], + meta_one(l, 1, 0), + 1, ), wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16( f, - [aa(l, 0, 0), aa(l, 1, 0), aa(l, 2, 0), aa(l, 3, 0)], - [bb(l, 0, 0), bb(l, 1, 0), bb(l, 2, 0), bb(l, 3, 0)], - META, - 0, + [af(l, 0, 0), af(l, 1, 0), af(l, 2, 0), af(l, 3, 0)], + [bf(l, 0, 0), bf(l, 1, 0), bf(l, 2, 0), bf(l, 3, 0)], + meta_pair(l, 1, 0), + 1, ), wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16( f, - [aa(l, 0, 1), aa(l, 1, 1)], - [bb(l, 0, 1), bb(l, 1, 1)], - META, - 0, + [af(l, 0, 1), af(l, 1, 1)], + [bf(l, 0, 1), bf(l, 1, 1)], + meta_one(l, 3, 0), + 3, ), wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16( f, - [aa(l, 0, 1), aa(l, 1, 1), aa(l, 2, 1), aa(l, 3, 1)], - [bb(l, 0, 1), bb(l, 1, 1), bb(l, 2, 1), bb(l, 3, 1)], - META, + [af(l, 0, 1), af(l, 1, 1), af(l, 2, 1), af(l, 3, 1)], + [bf(l, 0, 1), bf(l, 1, 1), bf(l, 2, 1), bf(l, 3, 1)], + meta_pair(l, 0, 0), 0, ), wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32( f, [at(l, 0), at(l, 1)], [bt(l, 0), bt(l, 1)], - META, - 0, + meta_one(l, 3, 1), + 3, ), wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32( f, [at(l, 0), at(l, 1), at(l, 2), at(l, 3)], [bt(l, 0), bt(l, 1), bt(l, 2), bt(l, 3)], - META, - 0, + meta_pair(l, 1, 1), + 1, ), ) }; @@ -151,33 +260,43 @@ mod kernels { } } } + +/// Register slot -> (row, col) for one lane's four logical accumulators. fn rc(l: usize, r: usize) -> (usize, usize) { (l / 4 + 8 * (r / 2), (l % 4) * 2 + r % 2) } -fn reference(r: usize, c: usize, kdim: usize) -> u32 { - let mut s = val(r as u32, c as u32); - for k in 0..kdim { - if k % 4 < 2 { - let q = (k / 4) * 2 + k % 4; - s += val(r as u32, q as u32) * val(k as u32, c as u32) - } + +/// Host GEMM for the f16/bf16 forms: per 4-wide chunk g the ordered code +/// (r,g) keeps columns 4g+i0 and 4g+i1 of logical A. +fn expect_h(r: usize, c: usize, kdim: usize) -> u32 { + let (r, c) = (r as u32, c as u32); + let mut s = c_val(r, c); + for g in 0..(kdim as u32) / 4 { + let m = meta_code(r, g, 0, 0); + let (i0, i1) = (m & 3, (m >> 2) & 3); + s += a_val(r, 2 * g) * b_val(4 * g + i0, c); + s += a_val(r, 2 * g + 1) * b_val(4 * g + i1, c); } s } -fn reference_tf32(r: usize, c: usize, kdim: usize) -> u32 { - let mut s = val(r as u32, c as u32); - for k in 0..kdim { - if k % 2 == 0 { - s += val(r as u32, (k / 2) as u32) * val(k as u32, c as u32) - } + +/// Host GEMM for the tf32 forms: per 2-wide chunk g, 0x4 keeps column 2g +/// and 0xe keeps column 2g+1. +fn expect_t(r: usize, c: usize, kdim: usize) -> u32 { + let (r, c) = (r as u32, c as u32); + let mut s = c_val(r, c); + for g in 0..(kdim as u32) / 2 { + let e = if meta_code(r, g, 0, 1) == 0x4 { 0 } else { 1 }; + s += a_val(r, g) * b_val(2 * g + e, c); } s } + fn main() { let ctx = CudaContext::new(0).expect("CUDA context"); let (major, minor) = ctx.compute_capability().unwrap(); if major < 8 { - println!("skip sm_{major}{minor}"); + println!("skipping: ordered sparse MMA requires sm_80+, found sm_{major}{minor}"); return; } let s = ctx.default_stream(); @@ -194,27 +313,29 @@ fn main() { let f = fd.to_host_vec(&s).unwrap(); let mut bad = 0; for l in 0..32 { + // packed-f16 accumulators: [k16_f16_f16, k32_f16_f16] for v in 0..2 { for r in 0..4 { let w = p[l * 4 + v * 2 + r / 2]; let got = if r % 2 == 0 { w & 0xffff } else { w >> 16 }; let (x, y) = rc(l, r); - let want = - half::f16::from_f32(reference(x, y, [16, 32][v]) as f32).to_bits() as u32; + let want = f16_bits(expect_h(x, y, [16, 32][v])); if got != want { eprintln!("f16 variant {v} lane {l} reg {r}: {got:#x} != {want:#x}"); bad += 1 } } } + // f32 accumulators: [k16_f32_f16, k32_f32_f16, k16_f32_bf16, + // k32_f32_bf16, k8_f32_tf32, k16_f32_tf32] for v in 0..6 { for r in 0..4 { let got = f[l * 24 + v * 4 + r]; let (x, y) = rc(l, r); let want = if v < 4 { - reference(x, y, [16, 32, 16, 32][v]) + expect_h(x, y, [16, 32, 16, 32][v]) } else { - reference_tf32(x, y, [8, 16][v - 4]) + expect_t(x, y, [8, 16][v - 4]) } as f32; if got != want { eprintln!("f32 variant {v} lane {l} reg {r}: {got} != {want}"); diff --git a/intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json b/intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json index 5b8d1a927e..141f9b9c02 100644 --- a/intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json +++ b/intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json @@ -16,7 +16,7 @@ {"targets":["compute_80","ptx88"],"representation":"eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0","stage":"backend_codegen","mechanism":"inline_ptx","outcome":"succeeded","detail":"CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987)."}, {"targets":["sm_80","ptx88"],"representation":"CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms","stage":"ptx_assembly","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.","tool_path":"/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas","tool_version":"CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0","tool_sha256":"fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73"}, {"targets":["sm_80","ptx88"],"representation":"the 4,740-byte all-variant libNVVM LTOIR linked for sm_80","stage":"device_link","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.","tool_path":"/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86","tool_version":"CUDA 12.9 nvJitLink V12.9.86","tool_sha256":"71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622"}, - {"targets":["sm_120","ptx88"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Measured on NVIDIA GeForce RTX 5080 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 12.9 V12.9.86. Command: CUDA_TOOLKIT_PATH=/home/sam/Workspaces/dinov3-candle/.pixi/envs/default cargo oxide run sparse_mma_ordered_float --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM."} + {"targets":["sm_120","ptx88"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors."} ] }], "matrices": [ diff --git a/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json b/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json index c361a7377e..318b25770d 100644 --- a/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json +++ b/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json @@ -12,7 +12,7 @@ "stages": [ {"targets":["sm_80","ptx85"],"representation":"eight typed LLVM declarations lowered through the selected convergent inline-PTX route","stage":"backend_codegen","mechanism":"inline_ptx","outcome":"succeeded","detail":"Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded."}, {"targets":["sm_80","ptx85"],"representation":"exact-floor PTX containing all eight ordered sparse floating MMA forms","stage":"ptx_assembly","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.","tool_path":"/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas","tool_version":"CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0","tool_sha256":"fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73"}, - {"targets":["sm_120","ptx85"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Measured on NVIDIA GeForce RTX 5080 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 12.9 V12.9.86. Command: CUDA_TOOLKIT_PATH=/home/sam/Workspaces/dinov3-candle/.pixi/envs/default cargo oxide run sparse_mma_ordered_float --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM."} + {"targets":["sm_120","ptx85"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors."} ] }], "matrices": [ From 95f3d1356ee7669b89ba04fb4688531678c1da77 Mon Sep 17 00:00:00 2001 From: nihalpasham Date: Sun, 30 Aug 2026 15:11:47 +0530 Subject: [PATCH 3/5] chore(intrinsics): bind i1017-i1024 in the ABI ledger and regenerate Append the eight ordered Ampere float sparse-MMA entries to intrinsics/abi-v1.toml (catalog ids, operation keys, and raw Rust signatures derived from the closed recipe; blank shard ids bind to them by catalog id) and regenerate every catalog-stamped output: - intrinsics/catalog.json, generated-reference.md, and the 8 new selector-swept probe fixtures (plus the stamp header in every probe) - generated sources across cuda-device, dialect-nvvm, mir-importer, mir-lower, and the collector targets - the book's catalog stamp and 1016 -> 1024 record count Gates run on this tree: cargo run -p cuda-intrinsics-gen -- generate / check / check-abi-history --base-ref origin/main (1016 base entries preserved, 1024 total); probe --all --skip-terminal --per-target (2373 target configurations across all 1024 routes, pinned LLVM 23.1.0); cargo test -p cuda-intrinsics-gen -p dialect-nvvm -p mir-importer -p mir-lower; fmt + clippy -D warnings for the workspace and the new example; scripts/sync-example-locks.sh --check. Signed-off-by: nihalpasham --- .../cuda-device/src/generated/async_copy.rs | 2 +- crates/cuda-device/src/generated/atomic.rs | 2 +- crates/cuda-device/src/generated/bf16.rs | 2 +- crates/cuda-device/src/generated/bf16x2.rs | 2 +- crates/cuda-device/src/generated/clc.rs | 2 +- .../src/generated/cluster_barrier.rs | 2 +- .../src/generated/cluster_memory.rs | 2 +- .../cuda-device/src/generated/cluster_sreg.rs | 2 +- crates/cuda-device/src/generated/convert.rs | 2 +- .../src/generated/counted_barrier.rs | 2 +- .../src/generated/debug_control.rs | 2 +- .../cuda-device/src/generated/debug_sreg.rs | 2 +- crates/cuda-device/src/generated/dotprod.rs | 2 +- crates/cuda-device/src/generated/f16.rs | 2 +- crates/cuda-device/src/generated/f16x2.rs | 2 +- crates/cuda-device/src/generated/f32x2.rs | 2 +- crates/cuda-device/src/generated/fence.rs | 2 +- crates/cuda-device/src/generated/float.rs | 2 +- .../src/generated/grid_dependency.rs | 2 +- crates/cuda-device/src/generated/grid_sreg.rs | 2 +- crates/cuda-device/src/generated/i16x2.rs | 2 +- crates/cuda-device/src/generated/int.rs | 2 +- crates/cuda-device/src/generated/ldmatrix.rs | 2 +- .../src/generated/mbarrier_basic.rs | 2 +- .../src/generated/mbarrier_extended.rs | 2 +- crates/cuda-device/src/generated/movmatrix.rs | 2 +- crates/cuda-device/src/generated/prmt.rs | 2 +- .../src/generated/register_control.rs | 2 +- .../cuda-device/src/generated/register_mma.rs | 2 +- .../cuda-device/src/generated/shared_sreg.rs | 2 +- .../cuda-device/src/generated/sparse_mma.rs | 194 +- crates/cuda-device/src/generated/sreg.rs | 2 +- crates/cuda-device/src/generated/stmatrix.rs | 2 +- crates/cuda-device/src/generated/tcgen05.rs | 2 +- crates/cuda-device/src/generated/tma.rs | 2 +- crates/cuda-device/src/generated/warp_sreg.rs | 2 +- .../src/generated/wgmma_control.rs | 2 +- .../cuda-intrinsics/src/generated/abi_v1.rs | 210 +- crates/cuda-intrinsics/src/generated/mod.rs | 74 +- .../active_mask.rs | 2 +- .../src/generated_intrinsic_targets/clc.rs | 2 +- .../cluster_barrier.rs | 2 +- .../cluster_memory.rs | 2 +- .../generated_intrinsic_targets/cp_async.rs | 2 +- .../debug_control.rs | 2 +- .../generated_intrinsic_targets/dotprod.rs | 2 +- .../src/generated_intrinsic_targets/elect.rs | 2 +- .../execution_control.rs | 2 +- .../extended_minmax.rs | 2 +- .../integer_minmax.rs | 2 +- .../generated_intrinsic_targets/ldmatrix.rs | 2 +- .../mbarrier_basic.rs | 2 +- .../mbarrier_extended.rs | 2 +- .../src/generated_intrinsic_targets/mod.rs | 24 +- .../generated_intrinsic_targets/movmatrix.rs | 2 +- .../generated_intrinsic_targets/packed_alu.rs | 2 +- .../packed_atomic.rs | 2 +- .../packed_conversion.rs | 2 +- .../src/generated_intrinsic_targets/prmt.rs | 2 +- .../src/generated_intrinsic_targets/redux.rs | 2 +- .../register_mma.rs | 2 +- .../scalar_arithmetic.rs | 2 +- .../scalar_conversion.rs | 2 +- .../scalar_math.rs | 2 +- .../generated_intrinsic_targets/sparse_mma.rs | 522 +- .../src/generated_intrinsic_targets/sreg.rs | 2 +- .../generated_intrinsic_targets/stmatrix.rs | 2 +- .../src/generated_intrinsic_targets/sync.rs | 2 +- .../generated_intrinsic_targets/tcgen05_cp.rs | 2 +- .../generated_intrinsic_targets/tcgen05_ld.rs | 2 +- .../tcgen05_mma.rs | 2 +- .../tcgen05_mma_ws.rs | 2 +- .../tcgen05_other.rs | 2 +- .../generated_intrinsic_targets/tcgen05_st.rs | 2 +- .../tests/active_mask.rs | 2 +- .../generated_intrinsic_targets/tests/clc.rs | 2 +- .../tests/cluster_barrier.rs | 2 +- .../tests/cluster_memory.rs | 2 +- .../tests/cp_async.rs | 2 +- .../tests/debug_control.rs | 2 +- .../tests/dotprod.rs | 2 +- .../tests/elect.rs | 2 +- .../tests/execution_control.rs | 2 +- .../tests/extended_minmax.rs | 2 +- .../tests/integer_minmax.rs | 2 +- .../tests/ldmatrix.rs | 2 +- .../tests/mbarrier_basic.rs | 2 +- .../tests/mbarrier_extended.rs | 2 +- .../generated_intrinsic_targets/tests/mod.rs | 2 +- .../tests/movmatrix.rs | 2 +- .../tests/packed_alu.rs | 2 +- .../tests/packed_atomic.rs | 2 +- .../tests/packed_conversion.rs | 2 +- .../generated_intrinsic_targets/tests/prmt.rs | 2 +- .../tests/redux.rs | 2 +- .../tests/register_mma_float.rs | 2 +- .../tests/register_mma_s32.rs | 2 +- .../tests/scalar_arithmetic.rs | 2 +- .../tests/scalar_conversion.rs | 2 +- .../tests/scalar_math.rs | 2 +- .../tests/sparse_mma.rs | 610 +- .../generated_intrinsic_targets/tests/sreg.rs | 2 +- .../tests/stmatrix.rs | 2 +- .../generated_intrinsic_targets/tests/sync.rs | 2 +- .../tests/tcgen05_cp.rs | 2 +- .../tests/tcgen05_ld.rs | 2 +- .../tests/tcgen05_mma.rs | 2 +- .../tests/tcgen05_mma_ws.rs | 2 +- .../tests/tcgen05_other.rs | 2 +- .../tests/tcgen05_st.rs | 2 +- .../generated_intrinsic_targets/tests/tma.rs | 2 +- .../generated_intrinsic_targets/tests/vote.rs | 2 +- .../tests/warp_barrier.rs | 2 +- .../tests/warp_match.rs | 2 +- .../tests/warp_shuffle.rs | 2 +- .../tests/wgmma_control.rs | 2 +- .../src/generated_intrinsic_targets/tma.rs | 2 +- .../src/generated_intrinsic_targets/vote.rs | 2 +- .../warp_barrier.rs | 2 +- .../generated_intrinsic_targets/warp_match.rs | 2 +- .../warp_shuffle.rs | 2 +- .../wgmma_control.rs | 2 +- .../src/ops/generated/active_mask.rs | 2 +- crates/dialect-nvvm/src/ops/generated/clc.rs | 2 +- .../src/ops/generated/cluster_barrier.rs | 2 +- .../src/ops/generated/cluster_memory.rs | 2 +- .../src/ops/generated/cp_async.rs | 2 +- .../src/ops/generated/debug_control.rs | 2 +- .../dialect-nvvm/src/ops/generated/dotprod.rs | 2 +- .../dialect-nvvm/src/ops/generated/elect.rs | 2 +- .../src/ops/generated/execution_control.rs | 2 +- .../src/ops/generated/extended_minmax.rs | 2 +- .../src/ops/generated/integer_minmax.rs | 2 +- .../src/ops/generated/ldmatrix.rs | 2 +- .../src/ops/generated/mbarrier_basic.rs | 2 +- .../src/ops/generated/mbarrier_extended.rs | 2 +- crates/dialect-nvvm/src/ops/generated/mod.rs | 2 +- .../src/ops/generated/movmatrix.rs | 2 +- .../src/ops/generated/packed_alu.rs | 2 +- .../src/ops/generated/packed_atomic.rs | 2 +- .../src/ops/generated/packed_conversion.rs | 2 +- crates/dialect-nvvm/src/ops/generated/prmt.rs | 2 +- .../dialect-nvvm/src/ops/generated/redux.rs | 2 +- .../src/ops/generated/register_mma.rs | 2 +- .../src/ops/generated/scalar_arithmetic.rs | 2 +- .../src/ops/generated/scalar_conversion.rs | 2 +- .../src/ops/generated/scalar_math.rs | 2 +- .../src/ops/generated/sparse_mma.rs | 259 +- crates/dialect-nvvm/src/ops/generated/sreg.rs | 2 +- .../src/ops/generated/stmatrix.rs | 2 +- crates/dialect-nvvm/src/ops/generated/sync.rs | 2 +- .../dialect-nvvm/src/ops/generated/tcgen05.rs | 2 +- crates/dialect-nvvm/src/ops/generated/tma.rs | 2 +- crates/dialect-nvvm/src/ops/generated/vote.rs | 2 +- .../src/ops/generated/warp_barrier.rs | 2 +- .../src/ops/generated/warp_match.rs | 2 +- .../src/ops/generated/warp_shuffle.rs | 2 +- .../src/ops/generated/wgmma_control.rs | 2 +- .../intrinsics/generated/active_mask.rs | 2 +- .../terminator/intrinsics/generated/clc.rs | 2 +- .../intrinsics/generated/cluster_barrier.rs | 2 +- .../intrinsics/generated/cluster_memory.rs | 2 +- .../intrinsics/generated/cp_async.rs | 2 +- .../intrinsics/generated/debug_control.rs | 2 +- .../intrinsics/generated/dotprod.rs | 2 +- .../terminator/intrinsics/generated/elect.rs | 2 +- .../intrinsics/generated/execution_control.rs | 2 +- .../intrinsics/generated/extended_minmax.rs | 2 +- .../intrinsics/generated/helpers.rs | 10 +- .../intrinsics/generated/integer_minmax.rs | 2 +- .../intrinsics/generated/ldmatrix.rs | 2 +- .../intrinsics/generated/mbarrier_basic.rs | 2 +- .../intrinsics/generated/mbarrier_extended.rs | 2 +- .../terminator/intrinsics/generated/mod.rs | 42 +- .../intrinsics/generated/movmatrix.rs | 2 +- .../intrinsics/generated/packed_alu.rs | 2 +- .../intrinsics/generated/packed_atomic.rs | 2 +- .../intrinsics/generated/packed_conversion.rs | 2 +- .../terminator/intrinsics/generated/prmt.rs | 2 +- .../terminator/intrinsics/generated/redux.rs | 2 +- .../intrinsics/generated/register_mma.rs | 2 +- .../intrinsics/generated/scalar_arithmetic.rs | 2 +- .../intrinsics/generated/scalar_conversion.rs | 2 +- .../intrinsics/generated/scalar_math.rs | 2 +- .../intrinsics/generated/sparse_mma.rs | 642 +- .../terminator/intrinsics/generated/sreg.rs | 2 +- .../intrinsics/generated/stmatrix.rs | 2 +- .../terminator/intrinsics/generated/sync.rs | 2 +- .../intrinsics/generated/tcgen05_cp.rs | 2 +- .../intrinsics/generated/tcgen05_ld.rs | 2 +- .../intrinsics/generated/tcgen05_mma.rs | 2 +- .../intrinsics/generated/tcgen05_other.rs | 2 +- .../intrinsics/generated/tcgen05_st.rs | 2 +- .../intrinsics/generated/tests/active_mask.rs | 2 +- .../intrinsics/generated/tests/clc.rs | 2 +- .../generated/tests/cluster_barrier.rs | 2 +- .../generated/tests/cluster_memory.rs | 2 +- .../intrinsics/generated/tests/cp_async.rs | 2 +- .../generated/tests/debug_control.rs | 2 +- .../intrinsics/generated/tests/dotprod.rs | 2 +- .../intrinsics/generated/tests/elect.rs | 2 +- .../generated/tests/execution_control.rs | 2 +- .../generated/tests/extended_minmax.rs | 2 +- .../generated/tests/integer_minmax.rs | 2 +- .../intrinsics/generated/tests/ldmatrix.rs | 2 +- .../generated/tests/mbarrier_basic.rs | 2 +- .../generated/tests/mbarrier_extended.rs | 2 +- .../intrinsics/generated/tests/mod.rs | 2 +- .../intrinsics/generated/tests/movmatrix.rs | 2 +- .../intrinsics/generated/tests/packed_alu.rs | 2 +- .../generated/tests/packed_atomic.rs | 2 +- .../generated/tests/packed_conversion.rs | 2 +- .../intrinsics/generated/tests/prmt.rs | 2 +- .../intrinsics/generated/tests/redux.rs | 2 +- .../generated/tests/register_mma.rs | 2 +- .../generated/tests/scalar_arithmetic.rs | 2 +- .../generated/tests/scalar_conversion.rs | 2 +- .../intrinsics/generated/tests/scalar_math.rs | 2 +- .../intrinsics/generated/tests/sparse_mma.rs | 290 +- .../intrinsics/generated/tests/sreg.rs | 2 +- .../intrinsics/generated/tests/stmatrix.rs | 2 +- .../intrinsics/generated/tests/sync.rs | 2 +- .../intrinsics/generated/tests/tcgen05.rs | 2 +- .../intrinsics/generated/tests/tma.rs | 2 +- .../intrinsics/generated/tests/vote.rs | 2 +- .../generated/tests/warp_barrier.rs | 2 +- .../intrinsics/generated/tests/warp_match.rs | 2 +- .../generated/tests/warp_shuffle.rs | 2 +- .../generated/tests/wgmma_control.rs | 2 +- .../terminator/intrinsics/generated/tma.rs | 2 +- .../terminator/intrinsics/generated/vote.rs | 2 +- .../intrinsics/generated/warp_barrier.rs | 2 +- .../intrinsics/generated/warp_match.rs | 2 +- .../intrinsics/generated/warp_shuffle.rs | 2 +- .../intrinsics/generated/wgmma_control.rs | 2 +- .../generated_intrinsics/active_mask.rs | 2 +- .../src/convert/generated_intrinsics/clc.rs | 2 +- .../generated_intrinsics/cluster_barrier.rs | 2 +- .../generated_intrinsics/cluster_memory.rs | 2 +- .../convert/generated_intrinsics/cp_async.rs | 2 +- .../generated_intrinsics/debug_control.rs | 2 +- .../convert/generated_intrinsics/dotprod.rs | 2 +- .../src/convert/generated_intrinsics/elect.rs | 2 +- .../generated_intrinsics/execution_control.rs | 2 +- .../generated_intrinsics/extended_minmax.rs | 2 +- .../generated_intrinsics/integer_minmax.rs | 2 +- .../convert/generated_intrinsics/ldmatrix.rs | 2 +- .../generated_intrinsics/mbarrier_basic.rs | 2 +- .../generated_intrinsics/mbarrier_extended.rs | 2 +- .../src/convert/generated_intrinsics/mod.rs | 2 +- .../convert/generated_intrinsics/movmatrix.rs | 2 +- .../generated_intrinsics/packed_alu.rs | 2 +- .../generated_intrinsics/packed_atomic.rs | 2 +- .../generated_intrinsics/packed_conversion.rs | 2 +- .../src/convert/generated_intrinsics/prmt.rs | 2 +- .../src/convert/generated_intrinsics/redux.rs | 2 +- .../generated_intrinsics/register_mma.rs | 2 +- .../generated_intrinsics/scalar_arithmetic.rs | 2 +- .../generated_intrinsics/scalar_conversion.rs | 2 +- .../generated_intrinsics/scalar_math.rs | 2 +- .../generated_intrinsics/sparse_mma.rs | 138 +- .../src/convert/generated_intrinsics/sreg.rs | 2 +- .../convert/generated_intrinsics/stmatrix.rs | 2 +- .../src/convert/generated_intrinsics/sync.rs | 2 +- .../convert/generated_intrinsics/tcgen05.rs | 2 +- .../src/convert/generated_intrinsics/tma.rs | 2 +- .../src/convert/generated_intrinsics/vote.rs | 2 +- .../generated_intrinsics/warp_barrier.rs | 2 +- .../generated_intrinsics/warp_match.rs | 2 +- .../generated_intrinsics/warp_shuffle.rs | 2 +- .../generated_intrinsics/wgmma_control.rs | 2 +- .../src/generated_intrinsics.rs | 34 +- cuda-oxide-book/compiler/mlir-dialects.md | 6 +- intrinsics/abi-v1.toml | 56 + intrinsics/catalog.json | 7304 +++++++++++------ intrinsics/generated-reference.md | 138 +- intrinsics/probes/abs_bf16x2.ll | 2 +- intrinsics/probes/abs_f16x2.ll | 2 +- intrinsics/probes/active_mask.ll | 2 +- intrinsics/probes/add_bf16x2.ll | 2 +- intrinsics/probes/add_f16x2.ll | 2 +- intrinsics/probes/add_f32x2.ll | 2 +- intrinsics/probes/add_ftz_f32x2.ll | 2 +- intrinsics/probes/add_rm_f32.ll | 2 +- intrinsics/probes/add_rm_f64.ll | 2 +- intrinsics/probes/add_rm_ftz_f32.ll | 2 +- intrinsics/probes/add_rm_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rm_sat_f32.ll | 2 +- intrinsics/probes/add_rn_f32.ll | 2 +- intrinsics/probes/add_rn_f64.ll | 2 +- intrinsics/probes/add_rn_ftz_f32.ll | 2 +- intrinsics/probes/add_rn_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rn_sat_f32.ll | 2 +- intrinsics/probes/add_rp_f32.ll | 2 +- intrinsics/probes/add_rp_f64.ll | 2 +- intrinsics/probes/add_rp_ftz_f32.ll | 2 +- intrinsics/probes/add_rp_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rp_sat_f32.ll | 2 +- intrinsics/probes/add_rz_f32.ll | 2 +- intrinsics/probes/add_rz_f64.ll | 2 +- intrinsics/probes/add_rz_ftz_f32.ll | 2 +- intrinsics/probes/add_rz_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rz_sat_f32.ll | 2 +- intrinsics/probes/all_sync.ll | 2 +- intrinsics/probes/any_sync.ll | 2 +- intrinsics/probes/ballot_sync.ll | 2 +- intrinsics/probes/barrier_cluster_arrive.ll | 2 +- .../probes/barrier_cluster_arrive_aligned.ll | 2 +- .../probes/barrier_cluster_arrive_relaxed.ll | 2 +- .../barrier_cluster_arrive_relaxed_aligned.ll | 2 +- intrinsics/probes/barrier_cluster_wait.ll | 2 +- .../probes/barrier_cluster_wait_aligned.ll | 2 +- intrinsics/probes/barrier_cta_arrive.ll | 2 +- .../probes/barrier_cta_arrive_aligned.ll | 2 +- intrinsics/probes/barrier_cta_sync.ll | 2 +- intrinsics/probes/barrier_cta_sync_aligned.ll | 2 +- intrinsics/probes/block_dim_x.ll | 2 +- intrinsics/probes/block_dim_y.ll | 2 +- intrinsics/probes/block_dim_z.ll | 2 +- intrinsics/probes/block_idx_x.ll | 2 +- intrinsics/probes/block_idx_y.ll | 2 +- intrinsics/probes/block_idx_z.ll | 2 +- intrinsics/probes/breakpoint.ll | 2 +- .../probes/clc_query_get_first_ctaid_x.ll | 2 +- .../probes/clc_query_get_first_ctaid_y.ll | 2 +- .../probes/clc_query_get_first_ctaid_z.ll | 2 +- intrinsics/probes/clc_query_is_canceled.ll | 2 +- intrinsics/probes/clc_try_cancel.ll | 2 +- intrinsics/probes/clc_try_cancel_multicast.ll | 2 +- intrinsics/probes/clock.lib_nvvm.ll | 2 +- intrinsics/probes/clock.llvm_nvptx.ll | 2 +- intrinsics/probes/clock64.lib_nvvm.ll | 2 +- intrinsics/probes/clock64.llvm_nvptx.ll | 2 +- intrinsics/probes/cluster_block_count.ll | 2 +- intrinsics/probes/cluster_block_idx_x.ll | 2 +- intrinsics/probes/cluster_block_idx_y.ll | 2 +- intrinsics/probes/cluster_block_idx_z.ll | 2 +- intrinsics/probes/cluster_block_rank.ll | 2 +- intrinsics/probes/cluster_dim_x.ll | 2 +- intrinsics/probes/cluster_dim_y.ll | 2 +- intrinsics/probes/cluster_dim_z.ll | 2 +- intrinsics/probes/cluster_grid_dim_x.ll | 2 +- intrinsics/probes/cluster_grid_dim_y.ll | 2 +- intrinsics/probes/cluster_grid_dim_z.ll | 2 +- intrinsics/probes/cluster_idx_x.ll | 2 +- intrinsics/probes/cluster_idx_y.ll | 2 +- intrinsics/probes/cluster_idx_z.ll | 2 +- intrinsics/probes/cos_approx_f32.ll | 2 +- intrinsics/probes/cos_approx_ftz_f32.ll | 2 +- .../probes/cp_async_bulk_commit_group.ll | 2 +- .../cp_async_bulk_prefetch_tensor_1d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_1d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_2d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_2d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_3d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_3d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_4d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_4d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_5d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_5d_l2_cache_hint.ll | 2 +- ...sync_bulk_prefetch_tensor_gather4_2d_l2.ll | 2 +- ...refetch_tensor_gather4_2d_l2_cache_hint.ll | 2 +- .../probes/cp_async_bulk_tensor_1d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_1d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_2d_g2s.ll | 2 +- .../cp_async_bulk_tensor_2d_g2s_multicast.ll | 2 +- ..._async_bulk_tensor_2d_g2s_multicast_cg2.ll | 2 +- .../probes/cp_async_bulk_tensor_2d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_3d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_3d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_4d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_4d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_5d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_5d_s2g.ll | 2 +- ..._async_bulk_tensor_reduce_add_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_add_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_add_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_and_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_and_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_and_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_dec_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_dec_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_dec_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_inc_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_inc_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_inc_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_max_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_max_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_max_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_min_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_min_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_min_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_5d.ll | 2 +- ...p_async_bulk_tensor_reduce_or_im2col_3d.ll | 2 +- ...p_async_bulk_tensor_reduce_or_im2col_4d.ll | 2 +- ...p_async_bulk_tensor_reduce_or_im2col_5d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_1d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_2d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_3d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_4d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_xor_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_xor_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_xor_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_5d.ll | 2 +- intrinsics/probes/cp_async_bulk_wait_group.ll | 2 +- .../probes/cp_async_bulk_wait_group_read.ll | 2 +- intrinsics/probes/cp_async_ca_16.ll | 2 +- intrinsics/probes/cp_async_ca_4.ll | 2 +- intrinsics/probes/cp_async_ca_8.ll | 2 +- intrinsics/probes/cp_async_ca_zfill_16.ll | 2 +- intrinsics/probes/cp_async_ca_zfill_4.ll | 2 +- intrinsics/probes/cp_async_ca_zfill_8.ll | 2 +- intrinsics/probes/cp_async_cg_16.ll | 2 +- intrinsics/probes/cp_async_cg_zfill_16.ll | 2 +- intrinsics/probes/cp_async_commit_group.ll | 2 +- intrinsics/probes/cp_async_mbarrier_arrive.ll | 2 +- .../probes/cp_async_mbarrier_arrive_noinc.ll | 2 +- .../cp_async_mbarrier_arrive_noinc_shared.ll | 2 +- .../probes/cp_async_mbarrier_arrive_shared.ll | 2 +- intrinsics/probes/cp_async_wait_all.ll | 2 +- intrinsics/probes/cp_async_wait_group.ll | 2 +- intrinsics/probes/cvt_f16x2_f32.ll | 2 +- intrinsics/probes/cvt_f32x2_bf16x2.ll | 2 +- intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll | 2 +- intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll | 2 +- intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll | 2 +- intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll | 2 +- intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll | 2 +- intrinsics/probes/cvt_rn_relu_f16x2_f32.ll | 2 +- .../probes/cvt_rn_relu_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rn_relu_tf32_f32.ll | 2 +- .../probes/cvt_rn_satfinite_e4m3x2_f16x2.ll | 2 +- .../probes/cvt_rn_satfinite_e4m3x2_f32.ll | 2 +- .../probes/cvt_rn_satfinite_e5m2x2_f16x2.ll | 2 +- .../probes/cvt_rn_satfinite_e5m2x2_f32.ll | 2 +- .../cvt_rn_satfinite_relu_e4m3x2_f16x2.ll | 2 +- .../cvt_rn_satfinite_relu_e4m3x2_f32.ll | 2 +- .../cvt_rn_satfinite_relu_e5m2x2_f16x2.ll | 2 +- .../cvt_rn_satfinite_relu_e5m2x2_f32.ll | 2 +- .../probes/cvt_rn_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rn_tf32_f32.ll | 2 +- .../probes/cvt_rna_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rna_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rz_bf16x2_f32.ll | 2 +- intrinsics/probes/cvt_rz_f16x2_f32.ll | 2 +- .../probes/cvt_rz_relu_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rz_relu_tf32_f32.ll | 2 +- .../probes/cvt_rz_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rz_tf32_f32.ll | 2 +- intrinsics/probes/div_rm_f32.ll | 2 +- intrinsics/probes/div_rm_f64.ll | 2 +- intrinsics/probes/div_rm_ftz_f32.ll | 2 +- intrinsics/probes/div_rn_f32.ll | 2 +- intrinsics/probes/div_rn_f64.ll | 2 +- intrinsics/probes/div_rn_ftz_f32.ll | 2 +- intrinsics/probes/div_rp_f32.ll | 2 +- intrinsics/probes/div_rp_f64.ll | 2 +- intrinsics/probes/div_rp_ftz_f32.ll | 2 +- intrinsics/probes/div_rz_f32.ll | 2 +- intrinsics/probes/div_rz_f64.ll | 2 +- intrinsics/probes/div_rz_ftz_f32.ll | 2 +- intrinsics/probes/dp2a_s32.ll | 2 +- intrinsics/probes/dp2a_u32.ll | 2 +- intrinsics/probes/dp4a_s32.ll | 2 +- intrinsics/probes/dp4a_u32.ll | 2 +- intrinsics/probes/dsmem_read_u32.ll | 2 +- .../probes/dynamic_smem_size.lib_nvvm.ll | 2 +- .../probes/dynamic_smem_size.llvm_nvptx.ll | 2 +- intrinsics/probes/elect_sync.lib_nvvm.ll | 2 +- intrinsics/probes/elect_sync.llvm_nvptx.ll | 2 +- intrinsics/probes/envreg1.lib_nvvm.ll | 2 +- intrinsics/probes/envreg1.llvm_nvptx.ll | 2 +- intrinsics/probes/envreg2.lib_nvvm.ll | 2 +- intrinsics/probes/envreg2.llvm_nvptx.ll | 2 +- intrinsics/probes/ex2_approx_f16.ll | 2 +- intrinsics/probes/ex2_approx_f32.ll | 2 +- intrinsics/probes/ex2_approx_ftz_f32.ll | 2 +- .../fence_mbarrier_init_release_cluster.ll | 2 +- ..._generic_acquire_shared_cluster_cluster.ll | 2 +- ...sync_generic_release_shared_cta_cluster.ll | 2 +- .../probes/fence_proxy_async_shared_cta.ll | 2 +- ...proxy_tensormap_generic_acquire_cluster.ll | 2 +- ...nce_proxy_tensormap_generic_acquire_cta.ll | 2 +- ...nce_proxy_tensormap_generic_acquire_gpu.ll | 2 +- ..._proxy_tensormap_generic_acquire_system.ll | 2 +- ...proxy_tensormap_generic_release_cluster.ll | 2 +- ...nce_proxy_tensormap_generic_release_cta.ll | 2 +- ...nce_proxy_tensormap_generic_release_gpu.ll | 2 +- ..._proxy_tensormap_generic_release_system.ll | 2 +- intrinsics/probes/fma_bf16x2.ll | 2 +- intrinsics/probes/fma_f16x2.ll | 2 +- intrinsics/probes/fma_f32x2.ll | 2 +- intrinsics/probes/fma_ftz_f16x2.ll | 2 +- intrinsics/probes/fma_ftz_f32x2.ll | 2 +- intrinsics/probes/fma_ftz_relu_f16x2.ll | 2 +- intrinsics/probes/fma_ftz_sat_f16x2.ll | 2 +- intrinsics/probes/fma_relu_bf16x2.ll | 2 +- intrinsics/probes/fma_relu_f16x2.ll | 2 +- intrinsics/probes/fma_rm_f32.ll | 2 +- intrinsics/probes/fma_rm_f64.ll | 2 +- intrinsics/probes/fma_rm_ftz_f32.ll | 2 +- intrinsics/probes/fma_rm_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rm_sat_f32.ll | 2 +- intrinsics/probes/fma_rn_f32.ll | 2 +- intrinsics/probes/fma_rn_f64.ll | 2 +- intrinsics/probes/fma_rn_ftz_f32.ll | 2 +- intrinsics/probes/fma_rn_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rn_sat_f32.ll | 2 +- intrinsics/probes/fma_rp_f32.ll | 2 +- intrinsics/probes/fma_rp_f64.ll | 2 +- intrinsics/probes/fma_rp_ftz_f32.ll | 2 +- intrinsics/probes/fma_rp_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rp_sat_f32.ll | 2 +- intrinsics/probes/fma_rz_f32.ll | 2 +- intrinsics/probes/fma_rz_f64.ll | 2 +- intrinsics/probes/fma_rz_ftz_f32.ll | 2 +- intrinsics/probes/fma_rz_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rz_sat_f32.ll | 2 +- intrinsics/probes/fma_sat_f16x2.ll | 2 +- intrinsics/probes/globaltimer.lib_nvvm.ll | 2 +- intrinsics/probes/globaltimer.llvm_nvptx.ll | 2 +- .../grid_dependency_launch_dependents.ll | 2 +- intrinsics/probes/grid_dependency_wait.ll | 2 +- intrinsics/probes/grid_dim_x.ll | 2 +- intrinsics/probes/grid_dim_y.ll | 2 +- intrinsics/probes/grid_dim_z.ll | 2 +- intrinsics/probes/gridid.lib_nvvm.ll | 2 +- intrinsics/probes/gridid.llvm_nvptx.ll | 2 +- intrinsics/probes/lane_id.ll | 2 +- intrinsics/probes/lanemask_eq.ll | 2 +- intrinsics/probes/lanemask_ge.ll | 2 +- intrinsics/probes/lanemask_gt.ll | 2 +- intrinsics/probes/lanemask_le.ll | 2 +- intrinsics/probes/lanemask_lt.ll | 2 +- .../probes/ldmatrix_m16n16_x1_trans_b8.ll | 2 +- ...dmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll | 2 +- ...dmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll | 2 +- .../probes/ldmatrix_m16n16_x2_trans_b8.ll | 2 +- ...dmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll | 2 +- ...dmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll | 2 +- .../ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll | 2 +- .../ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll | 2 +- .../ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll | 2 +- .../ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll | 2 +- .../ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll | 2 +- .../ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll | 2 +- intrinsics/probes/ldmatrix_m8n8_x1_b16.ll | 2 +- .../probes/ldmatrix_m8n8_x1_trans_b16.ll | 2 +- intrinsics/probes/ldmatrix_m8n8_x2_b16.ll | 2 +- .../probes/ldmatrix_m8n8_x2_trans_b16.ll | 2 +- intrinsics/probes/ldmatrix_m8n8_x4_b16.ll | 2 +- .../probes/ldmatrix_m8n8_x4_trans_b16.ll | 2 +- intrinsics/probes/lg2_approx_f32.ll | 2 +- intrinsics/probes/lg2_approx_ftz_f32.ll | 2 +- intrinsics/probes/map_shared_rank.ll | 2 +- intrinsics/probes/match_all_i64_sync.ll | 2 +- intrinsics/probes/match_all_sync.ll | 2 +- intrinsics/probes/match_any_i64_sync.ll | 2 +- intrinsics/probes/match_any_sync.ll | 2 +- intrinsics/probes/max_bf16.ll | 2 +- intrinsics/probes/max_bf16x2.ll | 2 +- intrinsics/probes/max_f16.ll | 2 +- intrinsics/probes/max_f16x2.ll | 2 +- intrinsics/probes/max_ftz_f16.ll | 2 +- intrinsics/probes/max_ftz_f16x2.ll | 2 +- intrinsics/probes/max_ftz_nan_f16.ll | 2 +- intrinsics/probes/max_ftz_nan_f16x2.ll | 2 +- .../probes/max_ftz_nan_xorsign_abs_f16.ll | 2 +- .../probes/max_ftz_nan_xorsign_abs_f16x2.ll | 2 +- .../probes/max_ftz_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/max_ftz_xorsign_abs_f16.ll | 2 +- .../probes/max_ftz_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/max_ftz_xorsign_abs_f32.ll | 2 +- intrinsics/probes/max_nan_bf16.ll | 2 +- intrinsics/probes/max_nan_bf16x2.ll | 2 +- intrinsics/probes/max_nan_f16.ll | 2 +- intrinsics/probes/max_nan_f16x2.ll | 2 +- intrinsics/probes/max_nan_xorsign_abs_bf16.ll | 2 +- .../probes/max_nan_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/max_nan_xorsign_abs_f16.ll | 2 +- .../probes/max_nan_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/max_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/max_relu_s16x2.ll | 2 +- intrinsics/probes/max_relu_s32.ll | 2 +- intrinsics/probes/max_s16x2.ll | 2 +- intrinsics/probes/max_u16x2.ll | 2 +- intrinsics/probes/max_xorsign_abs_bf16.ll | 2 +- intrinsics/probes/max_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/max_xorsign_abs_f16.ll | 2 +- intrinsics/probes/max_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/max_xorsign_abs_f32.ll | 2 +- intrinsics/probes/mbarrier_arrive.ll | 2 +- intrinsics/probes/mbarrier_arrive_cluster.ll | 2 +- .../probes/mbarrier_arrive_expect_tx.ll | 2 +- .../mbarrier_arrive_expect_tx_cluster.ll | 2 +- intrinsics/probes/mbarrier_init.ll | 2 +- intrinsics/probes/mbarrier_inval.ll | 2 +- intrinsics/probes/mbarrier_test_wait.ll | 2 +- intrinsics/probes/mbarrier_try_wait.ll | 2 +- intrinsics/probes/mbarrier_try_wait_parity.ll | 2 +- .../mbarrier_try_wait_parity_cluster.ll | 2 +- intrinsics/probes/min_bf16.ll | 2 +- intrinsics/probes/min_bf16x2.ll | 2 +- intrinsics/probes/min_f16.ll | 2 +- intrinsics/probes/min_f16x2.ll | 2 +- intrinsics/probes/min_ftz_f16.ll | 2 +- intrinsics/probes/min_ftz_f16x2.ll | 2 +- intrinsics/probes/min_ftz_nan_f16.ll | 2 +- intrinsics/probes/min_ftz_nan_f16x2.ll | 2 +- .../probes/min_ftz_nan_xorsign_abs_f16.ll | 2 +- .../probes/min_ftz_nan_xorsign_abs_f16x2.ll | 2 +- .../probes/min_ftz_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/min_ftz_xorsign_abs_f16.ll | 2 +- .../probes/min_ftz_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/min_ftz_xorsign_abs_f32.ll | 2 +- intrinsics/probes/min_nan_bf16.ll | 2 +- intrinsics/probes/min_nan_bf16x2.ll | 2 +- intrinsics/probes/min_nan_f16.ll | 2 +- intrinsics/probes/min_nan_f16x2.ll | 2 +- intrinsics/probes/min_nan_xorsign_abs_bf16.ll | 2 +- .../probes/min_nan_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/min_nan_xorsign_abs_f16.ll | 2 +- .../probes/min_nan_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/min_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/min_relu_s16x2.ll | 2 +- intrinsics/probes/min_relu_s32.ll | 2 +- intrinsics/probes/min_s16x2.ll | 2 +- intrinsics/probes/min_u16x2.ll | 2 +- intrinsics/probes/min_xorsign_abs_bf16.ll | 2 +- intrinsics/probes/min_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/min_xorsign_abs_f16.ll | 2 +- intrinsics/probes/min_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/min_xorsign_abs_f32.ll | 2 +- .../probes/mma_m16n8k128_s32_b1_and_popc.ll | 2 +- .../probes/mma_m16n8k128_s32_b1_xor_popc.ll | 2 +- intrinsics/probes/mma_m16n8k16_f16_f16.ll | 2 +- intrinsics/probes/mma_m16n8k16_f32_bf16.ll | 2 +- intrinsics/probes/mma_m16n8k16_f32_f16.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_s8.ll | 2 +- .../probes/mma_m16n8k16_s32_s8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll | 2 +- .../mma_m16n8k16_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_u8.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll | 2 +- .../mma_m16n8k16_s32_u8_s8_satfinite.ll | 2 +- .../probes/mma_m16n8k16_s32_u8_satfinite.ll | 2 +- .../probes/mma_m16n8k256_s32_b1_and_popc.ll | 2 +- .../probes/mma_m16n8k256_s32_b1_xor_popc.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s4.ll | 2 +- .../probes/mma_m16n8k32_s32_s4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll | 2 +- .../mma_m16n8k32_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s8.ll | 2 +- .../probes/mma_m16n8k32_s32_s8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll | 2 +- .../mma_m16n8k32_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u4.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll | 2 +- .../mma_m16n8k32_s32_u4_s4_satfinite.ll | 2 +- .../probes/mma_m16n8k32_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u8.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll | 2 +- .../mma_m16n8k32_s32_u8_s8_satfinite.ll | 2 +- .../probes/mma_m16n8k32_s32_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k4_f32_tf32.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_s4.ll | 2 +- .../probes/mma_m16n8k64_s32_s4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll | 2 +- .../mma_m16n8k64_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_u4.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll | 2 +- .../mma_m16n8k64_s32_u4_s4_satfinite.ll | 2 +- .../probes/mma_m16n8k64_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k8_f16_f16.ll | 2 +- intrinsics/probes/mma_m16n8k8_f32_bf16.ll | 2 +- intrinsics/probes/mma_m16n8k8_f32_f16.ll | 2 +- intrinsics/probes/mma_m16n8k8_f32_tf32.ll | 2 +- .../probes/mma_m8n8k128_s32_b1_and_popc.ll | 2 +- .../probes/mma_m8n8k128_s32_b1_xor_popc.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_s8.ll | 2 +- .../probes/mma_m8n8k16_s32_s8_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll | 2 +- .../probes/mma_m8n8k16_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_u8.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll | 2 +- .../probes/mma_m8n8k16_s32_u8_s8_satfinite.ll | 2 +- .../probes/mma_m8n8k16_s32_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_s4.ll | 2 +- .../probes/mma_m8n8k32_s32_s4_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll | 2 +- .../probes/mma_m8n8k32_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_u4.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll | 2 +- .../probes/mma_m8n8k32_s32_u4_s4_satfinite.ll | 2 +- .../probes/mma_m8n8k32_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k4_f64.ll | 2 +- intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll | 2 +- .../mma_sp_m16n8k128_s32_s4_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k128_s32_s4_u4.ll | 2 +- .../mma_sp_m16n8k128_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll | 2 +- .../probes/mma_sp_m16n8k128_s32_u4_s4.ll | 2 +- .../mma_sp_m16n8k128_s32_u4_s4_satfinite.ll | 2 +- .../mma_sp_m16n8k128_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll | 2 +- .../mma_sp_m16n8k32_s32_s8_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k32_s32_s8_u8.ll | 2 +- .../mma_sp_m16n8k32_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll | 2 +- .../probes/mma_sp_m16n8k32_s32_u8_s8.ll | 2 +- .../mma_sp_m16n8k32_s32_u8_s8_satfinite.ll | 2 +- .../mma_sp_m16n8k32_s32_u8_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll | 2 +- .../mma_sp_m16n8k64_s32_s4_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_s4_u4.ll | 2 +- .../mma_sp_m16n8k64_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll | 2 +- .../mma_sp_m16n8k64_s32_s8_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_s8_u8.ll | 2 +- .../mma_sp_m16n8k64_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_u4_s4.ll | 2 +- .../mma_sp_m16n8k64_s32_u4_s4_satfinite.ll | 2 +- .../mma_sp_m16n8k64_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_u8_s8.ll | 2 +- .../mma_sp_m16n8k64_s32_u8_s8_satfinite.ll | 2 +- .../mma_sp_m16n8k64_s32_u8_satfinite.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k128_s32_s4.ll | 2 +- ...red_metadata_m16n8k128_s32_s4_satfinite.ll | 2 +- ...sp_ordered_metadata_m16n8k128_s32_s4_u4.ll | 2 +- ..._metadata_m16n8k128_s32_s4_u4_satfinite.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k128_s32_u4.ll | 2 +- ...sp_ordered_metadata_m16n8k128_s32_u4_s4.ll | 2 +- ..._metadata_m16n8k128_s32_u4_s4_satfinite.ll | 2 +- ...red_metadata_m16n8k128_s32_u4_satfinite.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k16_f16_f16.ll | 26 + ...a_sp_ordered_metadata_m16n8k16_f32_bf16.ll | 26 + ...ma_sp_ordered_metadata_m16n8k16_f32_f16.ll | 26 + ...a_sp_ordered_metadata_m16n8k16_f32_tf32.ll | 18 + ...ma_sp_ordered_metadata_m16n8k32_f16_f16.ll | 18 + ...a_sp_ordered_metadata_m16n8k32_f32_bf16.ll | 18 + ...ma_sp_ordered_metadata_m16n8k32_f32_f16.ll | 18 + ...mma_sp_ordered_metadata_m16n8k32_s32_s8.ll | 2 +- ...ered_metadata_m16n8k32_s32_s8_satfinite.ll | 2 +- ..._sp_ordered_metadata_m16n8k32_s32_s8_u8.ll | 2 +- ...d_metadata_m16n8k32_s32_s8_u8_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k32_s32_u8.ll | 2 +- ..._sp_ordered_metadata_m16n8k32_s32_u8_s8.ll | 2 +- ...d_metadata_m16n8k32_s32_u8_s8_satfinite.ll | 2 +- ...ered_metadata_m16n8k32_s32_u8_satfinite.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_s4.ll | 2 +- ...ered_metadata_m16n8k64_s32_s4_satfinite.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_s4_u4.ll | 2 +- ...d_metadata_m16n8k64_s32_s4_u4_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_s8.ll | 2 +- ...ered_metadata_m16n8k64_s32_s8_satfinite.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_s8_u8.ll | 2 +- ...d_metadata_m16n8k64_s32_s8_u8_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_u4.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_u4_s4.ll | 2 +- ...d_metadata_m16n8k64_s32_u4_s4_satfinite.ll | 2 +- ...ered_metadata_m16n8k64_s32_u4_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_u8.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_u8_s8.ll | 2 +- ...d_metadata_m16n8k64_s32_u8_s8_satfinite.ll | 2 +- ...ered_metadata_m16n8k64_s32_u8_satfinite.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k8_f32_tf32.ll | 26 + intrinsics/probes/movmatrix_trans_b16.ll | 2 +- intrinsics/probes/mul_bf16x2.ll | 2 +- intrinsics/probes/mul_f16x2.ll | 2 +- intrinsics/probes/mul_f32x2.ll | 2 +- intrinsics/probes/mul_ftz_f32x2.ll | 2 +- intrinsics/probes/mul_rm_f32.ll | 2 +- intrinsics/probes/mul_rm_f64.ll | 2 +- intrinsics/probes/mul_rm_ftz_f32.ll | 2 +- intrinsics/probes/mul_rn_f32.ll | 2 +- intrinsics/probes/mul_rn_f64.ll | 2 +- intrinsics/probes/mul_rn_ftz_f32.ll | 2 +- intrinsics/probes/mul_rp_f32.ll | 2 +- intrinsics/probes/mul_rp_f64.ll | 2 +- intrinsics/probes/mul_rp_ftz_f32.ll | 2 +- intrinsics/probes/mul_rz_f32.ll | 2 +- intrinsics/probes/mul_rz_f64.ll | 2 +- intrinsics/probes/mul_rz_ftz_f32.ll | 2 +- intrinsics/probes/nanosleep.ll | 2 +- intrinsics/probes/neg_bf16x2.ll | 2 +- intrinsics/probes/neg_f16x2.ll | 2 +- intrinsics/probes/nsmid.lib_nvvm.ll | 2 +- intrinsics/probes/nsmid.llvm_nvptx.ll | 2 +- intrinsics/probes/nwarpid.lib_nvvm.ll | 2 +- intrinsics/probes/nwarpid.llvm_nvptx.ll | 2 +- intrinsics/probes/packed_atomic_add_bf16x2.ll | 2 +- intrinsics/probes/packed_atomic_add_f16x2.ll | 2 +- intrinsics/probes/pmevent.ll | 2 +- intrinsics/probes/prefetch_tma_descriptor.ll | 2 +- intrinsics/probes/prmt.ll | 2 +- intrinsics/probes/prmt_b4e.ll | 2 +- intrinsics/probes/prmt_ecl.ll | 2 +- intrinsics/probes/prmt_ecr.ll | 2 +- intrinsics/probes/prmt_f4e.ll | 2 +- intrinsics/probes/prmt_rc16.ll | 2 +- intrinsics/probes/prmt_rc8.ll | 2 +- intrinsics/probes/rcp_approx_ftz_f32.ll | 2 +- intrinsics/probes/rcp_approx_ftz_f64.ll | 2 +- intrinsics/probes/rcp_rm_f32.ll | 2 +- intrinsics/probes/rcp_rm_f64.ll | 2 +- intrinsics/probes/rcp_rm_ftz_f32.ll | 2 +- intrinsics/probes/rcp_rn_f32.ll | 2 +- intrinsics/probes/rcp_rn_f64.ll | 2 +- intrinsics/probes/rcp_rn_ftz_f32.ll | 2 +- intrinsics/probes/rcp_rp_f32.ll | 2 +- intrinsics/probes/rcp_rp_f64.ll | 2 +- intrinsics/probes/rcp_rp_ftz_f32.ll | 2 +- intrinsics/probes/rcp_rz_f32.ll | 2 +- intrinsics/probes/rcp_rz_f64.ll | 2 +- intrinsics/probes/rcp_rz_ftz_f32.ll | 2 +- intrinsics/probes/redux_sync_add.ll | 2 +- intrinsics/probes/redux_sync_and.ll | 2 +- intrinsics/probes/redux_sync_max_abs_f32.ll | 2 +- .../probes/redux_sync_max_abs_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_max_f32.ll | 2 +- intrinsics/probes/redux_sync_max_i32.ll | 2 +- intrinsics/probes/redux_sync_max_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_max_u32.ll | 2 +- intrinsics/probes/redux_sync_min_abs_f32.ll | 2 +- .../probes/redux_sync_min_abs_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_min_f32.ll | 2 +- intrinsics/probes/redux_sync_min_i32.ll | 2 +- intrinsics/probes/redux_sync_min_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_min_u32.ll | 2 +- intrinsics/probes/redux_sync_or.ll | 2 +- intrinsics/probes/redux_sync_xor.ll | 2 +- intrinsics/probes/rsqrt_approx_f32.ll | 2 +- intrinsics/probes/rsqrt_approx_f64.ll | 2 +- intrinsics/probes/rsqrt_approx_ftz_f32.ll | 2 +- intrinsics/probes/setmaxnreg_dec.ll | 2 +- intrinsics/probes/setmaxnreg_inc.ll | 2 +- intrinsics/probes/shuffle_down_f32_sync.ll | 2 +- intrinsics/probes/shuffle_down_sync.ll | 2 +- intrinsics/probes/shuffle_down_u64_sync.ll | 2 +- intrinsics/probes/shuffle_f32_sync.ll | 2 +- intrinsics/probes/shuffle_sync.ll | 2 +- intrinsics/probes/shuffle_u64_sync.ll | 2 +- intrinsics/probes/shuffle_up_f32_sync.ll | 2 +- intrinsics/probes/shuffle_up_sync.ll | 2 +- intrinsics/probes/shuffle_up_u64_sync.ll | 2 +- intrinsics/probes/shuffle_xor_f32_sync.ll | 2 +- intrinsics/probes/shuffle_xor_sync.ll | 2 +- intrinsics/probes/shuffle_xor_u64_sync.ll | 2 +- intrinsics/probes/sin_approx_f32.ll | 2 +- intrinsics/probes/sin_approx_ftz_f32.ll | 2 +- intrinsics/probes/smid.lib_nvvm.ll | 2 +- intrinsics/probes/smid.llvm_nvptx.ll | 2 +- intrinsics/probes/sqrt_approx_f32.ll | 2 +- intrinsics/probes/sqrt_approx_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rm_f32.ll | 2 +- intrinsics/probes/sqrt_rm_f64.ll | 2 +- intrinsics/probes/sqrt_rm_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rn_f32.ll | 2 +- intrinsics/probes/sqrt_rn_f64.ll | 2 +- intrinsics/probes/sqrt_rn_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rp_f32.ll | 2 +- intrinsics/probes/sqrt_rp_f64.ll | 2 +- intrinsics/probes/sqrt_rp_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rz_f32.ll | 2 +- intrinsics/probes/sqrt_rz_f64.ll | 2 +- intrinsics/probes/sqrt_rz_ftz_f32.ll | 2 +- intrinsics/probes/stmatrix_m8n8_x2_b16.ll | 2 +- .../probes/stmatrix_m8n8_x2_trans_b16.ll | 2 +- intrinsics/probes/stmatrix_m8n8_x4_b16.ll | 2 +- .../probes/stmatrix_m8n8_x4_trans_b16.ll | 2 +- intrinsics/probes/sub_bf16x2.ll | 2 +- intrinsics/probes/sub_f16x2.ll | 2 +- intrinsics/probes/sub_f32x2.ll | 2 +- intrinsics/probes/sub_ftz_f32x2.ll | 2 +- intrinsics/probes/sync_mask.ll | 2 +- intrinsics/probes/sync_threads.ll | 2 +- intrinsics/probes/tanh_approx_f32.ll | 2 +- intrinsics/probes/tcgen05_alloc.ll | 2 +- intrinsics/probes/tcgen05_alloc_cg2.ll | 2 +- intrinsics/probes/tcgen05_commit.ll | 2 +- intrinsics/probes/tcgen05_commit_cg2.ll | 2 +- intrinsics/probes/tcgen05_commit_multicast.ll | 2 +- .../probes/tcgen05_commit_multicast_cg2.ll | 2 +- .../probes/tcgen05_commit_shared_cluster.ll | 2 +- .../tcgen05_commit_shared_cluster_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_128x128b.ll | 2 +- .../probes/tcgen05_cp_128x128b_b4x16_p64.ll | 2 +- .../tcgen05_cp_128x128b_b4x16_p64_cg2.ll | 2 +- .../probes/tcgen05_cp_128x128b_b6x16_p32.ll | 2 +- .../tcgen05_cp_128x128b_b6x16_p32_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_128x128b_cg2.ll | 2 +- .../probes/tcgen05_cp_128x256b_b4x16_p64.ll | 2 +- .../tcgen05_cp_128x256b_b4x16_p64_cg2.ll | 2 +- .../probes/tcgen05_cp_128x256b_b6x16_p32.ll | 2 +- .../tcgen05_cp_128x256b_b6x16_p32_cg2.ll | 2 +- .../probes/tcgen05_cp_32x128b_warpx4.ll | 2 +- .../tcgen05_cp_32x128b_warpx4_b4x16_p64.ll | 2 +- ...tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll | 2 +- .../tcgen05_cp_32x128b_warpx4_b6x16_p32.ll | 2 +- ...tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll | 2 +- .../probes/tcgen05_cp_32x128b_warpx4_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_4x256b.ll | 2 +- .../probes/tcgen05_cp_4x256b_b4x16_p64.ll | 2 +- .../probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll | 2 +- .../probes/tcgen05_cp_4x256b_b6x16_p32.ll | 2 +- .../probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_4x256b_cg2.ll | 2 +- .../probes/tcgen05_cp_64x128b_warpx2_01_23.ll | 2 +- ...gen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll | 2 +- ...5_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll | 2 +- ...gen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll | 2 +- ...5_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll | 2 +- .../tcgen05_cp_64x128b_warpx2_01_23_cg2.ll | 2 +- .../probes/tcgen05_cp_64x128b_warpx2_02_13.ll | 2 +- ...gen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll | 2 +- ...5_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll | 2 +- ...gen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll | 2 +- ...5_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll | 2 +- .../tcgen05_cp_64x128b_warpx2_02_13_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_smem_to_tmem.ll | 2 +- .../probes/tcgen05_cp_smem_to_tmem_cg2.ll | 2 +- intrinsics/probes/tcgen05_dealloc.ll | 2 +- intrinsics/probes/tcgen05_dealloc_cg2.ll | 2 +- .../probes/tcgen05_fence_after_thread_sync.ll | 2 +- .../tcgen05_fence_before_thread_sync.ll | 2 +- .../probes/tcgen05_ld_16x128b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x1_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x2_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x4_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x64_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x8_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x8_raw.ll | 2 +- intrinsics/probes/tcgen05_ld_16x256b_pure.ll | 2 +- .../probes/tcgen05_ld_16x256b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x1_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x2_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x4_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x8_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x8_pure.ll | 2 +- .../probes/tcgen05_ld_16x256b_x8_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x128_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x128_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x1_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x2_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x4_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x64_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x8_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x8_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x128_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x128_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x1_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x2_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x4_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x64_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x8_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x128_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x128_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x1_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x2_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x4_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x64_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x8_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll | 2 +- intrinsics/probes/tcgen05_load_wait.ll | 2 +- intrinsics/probes/tcgen05_mma_e2m1.ll | 2 +- intrinsics/probes/tcgen05_mma_e2m3.ll | 2 +- intrinsics/probes/tcgen05_mma_e3m2.ll | 2 +- intrinsics/probes/tcgen05_mma_e4m3.ll | 2 +- intrinsics/probes/tcgen05_mma_e5m2.ll | 2 +- intrinsics/probes/tcgen05_mma_f16.ll | 2 +- intrinsics/probes/tcgen05_mma_f16_cg2.ll | 2 +- intrinsics/probes/tcgen05_mma_shared.ll | 2 +- intrinsics/probes/tcgen05_mma_sp_shared.ll | 2 +- intrinsics/probes/tcgen05_mma_sp_tensor.ll | 2 +- .../probes/tcgen05_mma_sp_tensor_ashift.ll | 2 +- intrinsics/probes/tcgen05_mma_tensor.ll | 2 +- .../probes/tcgen05_mma_tensor_ashift.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_bf16.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e2m1.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e2m3.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e3m2.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e4m3.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e5m2.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_f16.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_shared.ll | 2 +- .../tcgen05_mma_ws_shared_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_sp_shared.ll | 2 +- .../tcgen05_mma_ws_sp_shared_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll | 2 +- .../tcgen05_mma_ws_sp_tensor_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_tensor.ll | 2 +- .../tcgen05_mma_ws_tensor_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_tf32.ll | 2 +- .../probes/tcgen05_relinquish_alloc_permit.ll | 2 +- .../tcgen05_relinquish_alloc_permit_cg2.ll | 2 +- intrinsics/probes/tcgen05_shift_down.ll | 2 +- intrinsics/probes/tcgen05_shift_down_cg2.ll | 2 +- .../probes/tcgen05_st_16x128b_x16_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x16_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x1_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x32_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x32_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x64_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x64_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x16_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x16_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x1_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x32_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x32_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x128_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x128_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x16_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x16_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x1_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x32_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x32_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x64_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x64_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x128_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x128_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x16_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x16_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x1_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x32_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x32_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x64_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x64_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x128_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x128_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x16_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x16_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x1_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x32_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x32_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x64_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x64_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x8_unpack16.ll | 2 +- intrinsics/probes/tcgen05_store_wait.ll | 2 +- .../probes/tensormap_replace_box_dim.ll | 2 +- .../tensormap_replace_element_stride.ll | 2 +- .../probes/tensormap_replace_element_type.ll | 2 +- .../probes/tensormap_replace_fill_mode.ll | 2 +- .../tensormap_replace_global_address.ll | 2 +- .../probes/tensormap_replace_global_dim.ll | 2 +- .../probes/tensormap_replace_global_stride.ll | 2 +- .../tensormap_replace_interleave_layout.ll | 2 +- intrinsics/probes/tensormap_replace_rank.ll | 2 +- .../tensormap_replace_swizzle_atomicity.ll | 2 +- .../probes/tensormap_replace_swizzle_mode.ll | 2 +- intrinsics/probes/thread_idx_x.ll | 2 +- intrinsics/probes/thread_idx_y.ll | 2 +- intrinsics/probes/thread_idx_z.ll | 2 +- intrinsics/probes/threadfence.ll | 2 +- intrinsics/probes/threadfence_block.ll | 2 +- intrinsics/probes/threadfence_system.ll | 2 +- intrinsics/probes/total_smem_size.lib_nvvm.ll | 2 +- .../probes/total_smem_size.llvm_nvptx.ll | 2 +- intrinsics/probes/trap.ll | 2 +- intrinsics/probes/uni_sync.ll | 2 +- intrinsics/probes/warpid.lib_nvvm.ll | 2 +- intrinsics/probes/warpid.llvm_nvptx.ll | 2 +- intrinsics/probes/wgmma_commit_group.ll | 2 +- intrinsics/probes/wgmma_fence.ll | 2 +- intrinsics/probes/wgmma_wait_group.ll | 2 +- 1313 files changed, 9705 insertions(+), 3600 deletions(-) create mode 100644 intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll create mode 100644 intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll create mode 100644 intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll create mode 100644 intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll create mode 100644 intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll create mode 100644 intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll create mode 100644 intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll create mode 100644 intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll diff --git a/crates/cuda-device/src/generated/async_copy.rs b/crates/cuda-device/src/generated/async_copy.rs index 5b508d9b83..d809303ec0 100644 --- a/crates/cuda-device/src/generated/async_copy.rs +++ b/crates/cuda-device/src/generated/async_copy.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::async_copy` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/atomic.rs b/crates/cuda-device/src/generated/atomic.rs index c407b87745..53ae318ebb 100644 --- a/crates/cuda-device/src/generated/atomic.rs +++ b/crates/cuda-device/src/generated/atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::atomic` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/bf16.rs b/crates/cuda-device/src/generated/bf16.rs index 97607004c0..14b3f41c2b 100644 --- a/crates/cuda-device/src/generated/bf16.rs +++ b/crates/cuda-device/src/generated/bf16.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::bf16` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/bf16x2.rs b/crates/cuda-device/src/generated/bf16x2.rs index 2b740f3e29..d2cff751b1 100644 --- a/crates/cuda-device/src/generated/bf16x2.rs +++ b/crates/cuda-device/src/generated/bf16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::bf16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/clc.rs b/crates/cuda-device/src/generated/clc.rs index 865d31a218..956c76e059 100644 --- a/crates/cuda-device/src/generated/clc.rs +++ b/crates/cuda-device/src/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::clc` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/cluster_barrier.rs b/crates/cuda-device/src/generated/cluster_barrier.rs index b77f697b82..06bc450ee1 100644 --- a/crates/cuda-device/src/generated/cluster_barrier.rs +++ b/crates/cuda-device/src/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::cluster` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/cluster_memory.rs b/crates/cuda-device/src/generated/cluster_memory.rs index 0a515fe0a7..88a6303130 100644 --- a/crates/cuda-device/src/generated/cluster_memory.rs +++ b/crates/cuda-device/src/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::cluster` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/cluster_sreg.rs b/crates/cuda-device/src/generated/cluster_sreg.rs index c476eef84a..196f93d1ce 100644 --- a/crates/cuda-device/src/generated/cluster_sreg.rs +++ b/crates/cuda-device/src/generated/cluster_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // This file is included inside `cuda_device::cluster`. diff --git a/crates/cuda-device/src/generated/convert.rs b/crates/cuda-device/src/generated/convert.rs index a66c6cffff..958965b171 100644 --- a/crates/cuda-device/src/generated/convert.rs +++ b/crates/cuda-device/src/generated/convert.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::convert`. diff --git a/crates/cuda-device/src/generated/counted_barrier.rs b/crates/cuda-device/src/generated/counted_barrier.rs index 37ffc1a1d7..189a1aeba0 100644 --- a/crates/cuda-device/src/generated/counted_barrier.rs +++ b/crates/cuda-device/src/generated/counted_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::barrier` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/debug_control.rs b/crates/cuda-device/src/generated/debug_control.rs index 050415fa81..2de9de5b20 100644 --- a/crates/cuda-device/src/generated/debug_control.rs +++ b/crates/cuda-device/src/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::debug` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/debug_sreg.rs b/crates/cuda-device/src/generated/debug_sreg.rs index 6d26289eb9..d8e4136bb4 100644 --- a/crates/cuda-device/src/generated/debug_sreg.rs +++ b/crates/cuda-device/src/generated/debug_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::debug` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/dotprod.rs b/crates/cuda-device/src/generated/dotprod.rs index 328eb61bfc..7d35a4fdbc 100644 --- a/crates/cuda-device/src/generated/dotprod.rs +++ b/crates/cuda-device/src/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::dotprod` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f16.rs b/crates/cuda-device/src/generated/f16.rs index 843889baa1..b9dd89fc75 100644 --- a/crates/cuda-device/src/generated/f16.rs +++ b/crates/cuda-device/src/generated/f16.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::f16` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f16x2.rs b/crates/cuda-device/src/generated/f16x2.rs index dcd9d60c81..b505506b3f 100644 --- a/crates/cuda-device/src/generated/f16x2.rs +++ b/crates/cuda-device/src/generated/f16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::f16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f32x2.rs b/crates/cuda-device/src/generated/f32x2.rs index 4d5e12f0e8..ce8aebc9d4 100644 --- a/crates/cuda-device/src/generated/f32x2.rs +++ b/crates/cuda-device/src/generated/f32x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::f32x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/fence.rs b/crates/cuda-device/src/generated/fence.rs index 74bf16e640..d92cd22c1d 100644 --- a/crates/cuda-device/src/generated/fence.rs +++ b/crates/cuda-device/src/generated/fence.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // This file is included inside `cuda_device::fence` so existing paths stay stable. diff --git a/crates/cuda-device/src/generated/float.rs b/crates/cuda-device/src/generated/float.rs index 900c4c7a6d..a750a7cc9a 100644 --- a/crates/cuda-device/src/generated/float.rs +++ b/crates/cuda-device/src/generated/float.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::float`. diff --git a/crates/cuda-device/src/generated/grid_dependency.rs b/crates/cuda-device/src/generated/grid_dependency.rs index bf2648336a..ca5049aed1 100644 --- a/crates/cuda-device/src/generated/grid_dependency.rs +++ b/crates/cuda-device/src/generated/grid_dependency.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::grid` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/grid_sreg.rs b/crates/cuda-device/src/generated/grid_sreg.rs index a2b0bb7afa..c821995683 100644 --- a/crates/cuda-device/src/generated/grid_sreg.rs +++ b/crates/cuda-device/src/generated/grid_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::grid` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/i16x2.rs b/crates/cuda-device/src/generated/i16x2.rs index 5ce2d9a8f1..11aa22604c 100644 --- a/crates/cuda-device/src/generated/i16x2.rs +++ b/crates/cuda-device/src/generated/i16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::i16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/int.rs b/crates/cuda-device/src/generated/int.rs index 7ee9625bda..869f7fee07 100644 --- a/crates/cuda-device/src/generated/int.rs +++ b/crates/cuda-device/src/generated/int.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::int` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/ldmatrix.rs b/crates/cuda-device/src/generated/ldmatrix.rs index 40b6eebb02..424e3d01e0 100644 --- a/crates/cuda-device/src/generated/ldmatrix.rs +++ b/crates/cuda-device/src/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/mbarrier_basic.rs b/crates/cuda-device/src/generated/mbarrier_basic.rs index 2442da327e..251de4f219 100644 --- a/crates/cuda-device/src/generated/mbarrier_basic.rs +++ b/crates/cuda-device/src/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::barrier` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/mbarrier_extended.rs b/crates/cuda-device/src/generated/mbarrier_extended.rs index fcec31901c..a1323b63a2 100644 --- a/crates/cuda-device/src/generated/mbarrier_extended.rs +++ b/crates/cuda-device/src/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::barrier` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/movmatrix.rs b/crates/cuda-device/src/generated/movmatrix.rs index 6ba07c94b4..a3bd62ae27 100644 --- a/crates/cuda-device/src/generated/movmatrix.rs +++ b/crates/cuda-device/src/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/prmt.rs b/crates/cuda-device/src/generated/prmt.rs index a797af9b9e..3b33a18d50 100644 --- a/crates/cuda-device/src/generated/prmt.rs +++ b/crates/cuda-device/src/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::prmt` to keep the public paths stable. diff --git a/crates/cuda-device/src/generated/register_control.rs b/crates/cuda-device/src/generated/register_control.rs index 9f3828f068..13de40fca2 100644 --- a/crates/cuda-device/src/generated/register_control.rs +++ b/crates/cuda-device/src/generated/register_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::thread` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/register_mma.rs b/crates/cuda-device/src/generated/register_mma.rs index a67c039f49..43b07e3057 100644 --- a/crates/cuda-device/src/generated/register_mma.rs +++ b/crates/cuda-device/src/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/shared_sreg.rs b/crates/cuda-device/src/generated/shared_sreg.rs index b2fbf3a4f0..228299f88b 100644 --- a/crates/cuda-device/src/generated/shared_sreg.rs +++ b/crates/cuda-device/src/generated/shared_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::shared` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/sparse_mma.rs b/crates/cuda-device/src/generated/sparse_mma.rs index d2f7b3ee30..7ec6f7685e 100644 --- a/crates/cuda-device/src/generated/sparse_mma.rs +++ b/crates/cuda-device/src/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep public paths stable. @@ -1017,6 +1017,174 @@ pub unsafe fn mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite( ) } +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 2-, 2-, and 2-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k16_f16_f16( + c: [u32; 2], + a: [u32; 2], + b: [u32; 2], + metadata: u32, + selector: u32, +) -> [u32; 2] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k16_f16_f16 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 2-, and 2-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k16_f32_bf16( + c: [f32; 4], + a: [u32; 2], + b: [u32; 2], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k16_f32_bf16 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 2-, and 2-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k16_f32_f16( + c: [f32; 4], + a: [u32; 2], + b: [u32; 2], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k16_f32_f16 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 4-, and 4-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0` or `1`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k16_f32_tf32( + c: [f32; 4], + a: [u32; 4], + b: [u32; 4], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k16_f32_tf32 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 2-, 4-, and 4-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0` or `1`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k32_f16_f16( + c: [u32; 2], + a: [u32; 4], + b: [u32; 4], + metadata: u32, + selector: u32, +) -> [u32; 2] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k32_f16_f16 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 4-, and 4-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0` or `1`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k32_f32_bf16( + c: [f32; 4], + a: [u32; 4], + b: [u32; 4], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k32_f32_bf16 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 4-, and 4-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0` or `1`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k32_f32_f16( + c: [f32; 4], + a: [u32; 4], + b: [u32; 4], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k32_f32_f16 called outside CUDA kernel context") +} + /// Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator. /// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32`. C, A, B, and metadata are this lane's PTX fragments. /// Requires PTX 8.5 and `sm_80+`. @@ -2940,3 +3108,27 @@ pub unsafe fn mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite( "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite called outside CUDA kernel context" ) } + +/// Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 2-, and 2-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k8_f32_tf32( + c: [f32; 4], + a: [u32; 2], + b: [u32; 2], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k8_f32_tf32 called outside CUDA kernel context") +} diff --git a/crates/cuda-device/src/generated/sreg.rs b/crates/cuda-device/src/generated/sreg.rs index ce8d20a6d0..a6d2733352 100644 --- a/crates/cuda-device/src/generated/sreg.rs +++ b/crates/cuda-device/src/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // This file is included lexically inside `cuda_device::thread` so existing diff --git a/crates/cuda-device/src/generated/stmatrix.rs b/crates/cuda-device/src/generated/stmatrix.rs index 7d12c086fa..cb0fa5713b 100644 --- a/crates/cuda-device/src/generated/stmatrix.rs +++ b/crates/cuda-device/src/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::tcgen05` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/tcgen05.rs b/crates/cuda-device/src/generated/tcgen05.rs index 8e50f3bb60..966af0f0c9 100644 --- a/crates/cuda-device/src/generated/tcgen05.rs +++ b/crates/cuda-device/src/generated/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::tcgen05` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/tma.rs b/crates/cuda-device/src/generated/tma.rs index eb0fea83c1..d53825a7ab 100644 --- a/crates/cuda-device/src/generated/tma.rs +++ b/crates/cuda-device/src/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::tma` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/warp_sreg.rs b/crates/cuda-device/src/generated/warp_sreg.rs index 1ab897c920..710e58b035 100644 --- a/crates/cuda-device/src/generated/warp_sreg.rs +++ b/crates/cuda-device/src/generated/warp_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::warp` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/wgmma_control.rs b/crates/cuda-device/src/generated/wgmma_control.rs index beeb5c5aab..c4ac3a1112 100644 --- a/crates/cuda-device/src/generated/wgmma_control.rs +++ b/crates/cuda-device/src/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wgmma` to keep its public API stable. diff --git a/crates/cuda-intrinsics/src/generated/abi_v1.rs b/crates/cuda-intrinsics/src/generated/abi_v1.rs index aaac70addb..6706b27320 100644 --- a/crates/cuda-intrinsics/src/generated/abi_v1.rs +++ b/crates/cuda-intrinsics/src/generated/abi_v1.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Raw ABI functions recognized by cuda-oxide. @@ -9869,6 +9869,188 @@ pub unsafe fn i0209( ) } +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k16_f16_f16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f16.f16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f16_f16`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 2-register C, 2-register A, and 2-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1020( + _arg0: [u32; 2], + _arg1: [u32; 2], + _arg2: [u32; 2], + _arg3: u32, + _arg4: u32, +) -> [u32; 2] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k16_f32_bf16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.bf16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_bf16`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 2-register A, and 2-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1019( + _arg0: [f32; 4], + _arg1: [u32; 2], + _arg2: [u32; 2], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k16_f32_f16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f32.f32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f32_f32`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 2-register A, and 2-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1021( + _arg0: [f32; 4], + _arg1: [u32; 2], + _arg2: [u32; 2], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k16_f32_tf32`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.tf32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_tf32`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 4-register A, and 4-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0` or `1`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1018( + _arg0: [f32; 4], + _arg1: [u32; 4], + _arg2: [u32; 4], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k32_f16_f16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 2-register C, 4-register A, and 4-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0` or `1`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1023( + _arg0: [u32; 2], + _arg1: [u32; 4], + _arg2: [u32; 4], + _arg3: u32, + _arg4: u32, +) -> [u32; 2] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k32_f32_bf16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 4-register A, and 4-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0` or `1`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1022( + _arg0: [f32; 4], + _arg1: [u32; 4], + _arg2: [u32; 4], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k32_f32_f16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 4-register A, and 4-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0` or `1`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1024( + _arg0: [f32; 4], + _arg1: [u32; 4], + _arg2: [u32; 4], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024` executed outside device compilation" + ) +} + /// Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator. /// /// Catalog ID: `mma_sp_ordered_metadata_m16n8k32_s32_s8`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 , , , , , ;`. @@ -11817,6 +11999,32 @@ pub unsafe fn i0185( ) } +/// Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k8_f32_tf32`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 2-register A, and 2-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1017( + _arg0: [f32; 4], + _arg1: [u32; 2], + _arg2: [u32; 2], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017` executed outside device compilation" + ) +} + /// Transposes one packed b16 matrix fragment across a warp. /// /// Catalog ID: `movmatrix_trans_b16`. Source: PTX-native `movmatrix.sync.aligned.m8n8.trans.b16`; expects PTX `movmatrix.sync.aligned.m8n8.trans.b16 , ;`. diff --git a/crates/cuda-intrinsics/src/generated/mod.rs b/crates/cuda-intrinsics/src/generated/mod.rs index dd25bf996b..1f346dcc91 100644 --- a/crates/cuda-intrinsics/src/generated/mod.rs +++ b/crates/cuda-intrinsics/src/generated/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. #[doc(hidden)] @@ -666,6 +666,14 @@ pub mod matrix { pub use crate::__cuda_oxide_intrinsic_abi_v1::i0880 as mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2; pub use crate::__cuda_oxide_intrinsic_abi_v1::i0881 as mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3; pub use crate::__cuda_oxide_intrinsic_abi_v1::i0882 as mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1017 as mma_sp_ordered_metadata_m16n8k8_f32_tf32; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1018 as mma_sp_ordered_metadata_m16n8k16_f32_tf32; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1019 as mma_sp_ordered_metadata_m16n8k16_f32_bf16; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1020 as mma_sp_ordered_metadata_m16n8k16_f16_f16; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1021 as mma_sp_ordered_metadata_m16n8k16_f32_f16; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1022 as mma_sp_ordered_metadata_m16n8k32_f32_bf16; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1023 as mma_sp_ordered_metadata_m16n8k32_f16_f16; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1024 as mma_sp_ordered_metadata_m16n8k32_f32_f16; } /// Generated `prmt` intrinsic source API. @@ -5664,6 +5672,62 @@ mod tests { assert_eq!(public as usize, canonical as usize); } #[test] + fn public_mma_sp_ordered_metadata_m16n8k16_f16_f16_reexports_abi_i1020() { + let public: unsafe fn([u32; 2], [u32; 2], [u32; 2], u32, u32) -> [u32; 2] = + super::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16; + let canonical: unsafe fn([u32; 2], [u32; 2], [u32; 2], u32, u32) -> [u32; 2] = + super::__cuda_oxide_intrinsic_abi_v1::i1020; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k16_f32_bf16_reexports_abi_i1019() { + let public: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16; + let canonical: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1019; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k16_f32_f16_reexports_abi_i1021() { + let public: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16; + let canonical: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1021; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k16_f32_tf32_reexports_abi_i1018() { + let public: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32; + let canonical: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1018; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k32_f16_f16_reexports_abi_i1023() { + let public: unsafe fn([u32; 2], [u32; 4], [u32; 4], u32, u32) -> [u32; 2] = + super::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16; + let canonical: unsafe fn([u32; 2], [u32; 4], [u32; 4], u32, u32) -> [u32; 2] = + super::__cuda_oxide_intrinsic_abi_v1::i1023; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k32_f32_bf16_reexports_abi_i1022() { + let public: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16; + let canonical: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1022; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k32_f32_f16_reexports_abi_i1024() { + let public: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16; + let canonical: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1024; + assert_eq!(public as usize, canonical as usize); + } + #[test] fn public_mma_sp_ordered_metadata_m16n8k32_s32_s8_reexports_abi_i0171() { let public: unsafe fn([i32; 4], [u32; 2], [u32; 2], u32, u32) -> [i32; 4] = super::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8; @@ -6256,6 +6320,14 @@ mod tests { assert_eq!(public as usize, canonical as usize); } #[test] + fn public_mma_sp_ordered_metadata_m16n8k8_f32_tf32_reexports_abi_i1017() { + let public: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32; + let canonical: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1017; + assert_eq!(public as usize, canonical as usize); + } + #[test] fn public_movmatrix_trans_b16_reexports_abi_i0305() { let public: unsafe fn(u32) -> u32 = super::matrix::movmatrix_trans_b16; let canonical: unsafe fn(u32) -> u32 = super::__cuda_oxide_intrinsic_abi_v1::i0305; diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs index cc313d534d..4452cdd310 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `active_mask` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs index 1165570a1e..efe32a089e 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `clc` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs index b99f29d63f..f7d083bd51 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `cluster_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs index f161d32855..1a5f55d68c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `cluster_memory` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs index 35b0f971a4..bfa39aace8 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `cp_async` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs index 5c17afc9c7..208847e73e 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `debug_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs index d6331cff1a..867f65e587 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `dotprod` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs index bd0c854d1e..f11304e19a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `elect` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs index 5d0dcb40c1..478ada7cd7 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `execution_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs index b71439c1ca..360407531b 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `extended_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs index 9c91ca6532..7edf70caf4 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `integer_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs index b016f78aaa..ba088d72dd 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `ldmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs index af515c2086..247f6bf958 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `mbarrier_basic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs index e687b5197f..22355ec7d2 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `mbarrier_extended` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs index 19ba2e0f5f..771e7b9c58 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated target requirements and separately imported LLVM/selection facts. @@ -200,6 +200,8 @@ pub enum GeneratedRegisterMmaOverflow { } #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum GeneratedSparseMmaShape { + M16n8k8, + M16n8k16, M16n8k32, M16n8k64, M16n8k128, @@ -212,6 +214,9 @@ pub enum GeneratedSparseMmaAccumulator { } #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum GeneratedSparseMmaElement { + F16, + Bf16, + Tf32, E2m1, E2m3, E3m2, @@ -239,7 +244,9 @@ pub enum GeneratedSparseMmaMetadata { Ordered, } #[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[allow(clippy::enum_variant_names)] pub enum GeneratedSparseMmaSelector { + ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero, } @@ -951,6 +958,9 @@ pub fn generated_intrinsic_operation_matches( return false; }; let element_matches = |expected, actual: Option<&SparseMmaElementAttr>| match expected { + GeneratedSparseMmaElement::F16 => actual == Some(&SparseMmaElementAttr::F16), + GeneratedSparseMmaElement::Bf16 => actual == Some(&SparseMmaElementAttr::Bf16), + GeneratedSparseMmaElement::Tf32 => actual == Some(&SparseMmaElementAttr::Tf32), GeneratedSparseMmaElement::E2m1 => actual == Some(&SparseMmaElementAttr::E2m1), GeneratedSparseMmaElement::E2m3 => actual == Some(&SparseMmaElementAttr::E2m3), GeneratedSparseMmaElement::E3m2 => actual == Some(&SparseMmaElementAttr::E3m2), @@ -990,6 +1000,14 @@ pub fn generated_intrinsic_operation_matches( } }; let shape_matches = match shape { + GeneratedSparseMmaShape::M16n8k8 => { + op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() + == Some(&SparseMmaShapeAttr::M16n8k8) + } + GeneratedSparseMmaShape::M16n8k16 => { + op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() + == Some(&SparseMmaShapeAttr::M16n8k16) + } GeneratedSparseMmaShape::M16n8k32 => { op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32) @@ -1018,6 +1036,10 @@ pub fn generated_intrinsic_operation_matches( } }; let selector_matches = match selector { + GeneratedSparseMmaSelector::ImmediateZeroThroughThree => { + op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() + == Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree) + } GeneratedSparseMmaSelector::ImmediateZeroOrOne => { op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne) diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs index b7b28dd2da..9c149147f0 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `movmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs index 3a1bbe0d4f..b93e05f539 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `packed_alu` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs index b61350a981..6e1842da36 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `packed_atomic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs index 29fd039e6c..1ffe5949b6 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `packed_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs index e91f1a961c..1280c0f953 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `prmt` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs index 9bd4f05520..1c8bdfb8a3 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `redux` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs index cc9d32838b..954ca92338 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `register_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs index db5607725d..fed6b09751 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `scalar_arithmetic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs index 66f9a8ddff..970bc3bec3 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `scalar_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs index c7efffde47..6712670994 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `scalar_math` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs index 81b6240f76..eb6355564b 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `sparse_mma` intrinsics. @@ -7729,4 +7729,524 @@ pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[ result_range: None, }), }, + GeneratedIntrinsicTarget { + marker: "v1:i1017", + id: "mma_sp_ordered_metadata_m16n8k8_f32_tf32", + abi_id: "i1017", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k8, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Tf32, + b_element: GeneratedSparseMmaElement::Tf32, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19540", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1018", + id: "mma_sp_ordered_metadata_m16n8k16_f32_tf32", + abi_id: "i1018", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Tf32, + b_element: GeneratedSparseMmaElement::Tf32, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19546", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1019", + id: "mma_sp_ordered_metadata_m16n8k16_f32_bf16", + abi_id: "i1019", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Bf16, + b_element: GeneratedSparseMmaElement::Bf16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19524", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1020", + id: "mma_sp_ordered_metadata_m16n8k16_f16_f16", + abi_id: "i1020", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F16, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19554", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1021", + id: "mma_sp_ordered_metadata_m16n8k16_f32_f16", + abi_id: "i1021", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19558", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1022", + id: "mma_sp_ordered_metadata_m16n8k32_f32_bf16", + abi_id: "i1022", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Bf16, + b_element: GeneratedSparseMmaElement::Bf16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19532", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1023", + id: "mma_sp_ordered_metadata_m16n8k32_f16_f16", + abi_id: "i1023", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F16, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19566", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1024", + id: "mma_sp_ordered_metadata_m16n8k32_f32_f16", + abi_id: "i1024", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19570", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, ]; diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs index 31a77fa5c0..453094de29 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `sreg` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs index 8af308f35d..f2fa8c0411 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `stmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs index 630c9002ab..76f9bfee96 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `sync` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs index 48f7f50559..5668e14e28 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_cp` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs index 1df2e42a4a..be96fb2ed6 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_ld` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs index 76a909de5a..5d37618ee7 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs index 79c86338bf..3b7af9f86c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_mma_ws` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs index 6c3e4c125c..edaa24339f 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_other` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs index 06c3f729a9..7b3565c80a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_st` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs index e2bfdcce71..5b1b5ab644 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `active_mask` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs index f9b9d0b890..e3bb07ec3c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `clc` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs index 6ea5496d07..7af81ce5dc 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `cluster_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs index bab3b796ed..73429ba98c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `cluster_memory` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs index bbe81adc80..ef68da93b6 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `cp_async` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs index 01a6a06455..f862027b33 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `debug_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs index 73cf056f15..0c583b6a5a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `dotprod` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs index 28f616c1d8..8dd307559c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `elect` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs index 3c1d3d59ce..8db207fcb0 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `execution_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs index e8255b28d9..8ef8fa6abd 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `extended_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs index 848156590c..b996f82984 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `integer_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs index b23416e8d4..915114064d 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `ldmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs index 4878cb4148..bc6d183d3a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `mbarrier_basic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs index 3d9f19d008..a7e217421d 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `mbarrier_extended` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs index 2c468eef12..bee3a334c8 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests, grouped per family shard. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs index a85e12d291..5dcc670118 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `movmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs index f7b6efecce..d72d6a6015 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `packed_alu` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs index d3c5160448..d8bcda0c47 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `packed_atomic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs index a475c56890..17a58067a9 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `packed_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs index e1a90d4a3d..da8f75709b 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `prmt` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs index b93f878c69..33ce92f3d1 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `redux` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs index a0c3421ea3..6096e75d87 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `register_mma_float` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs index 6170288a07..99d7ccf69d 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `register_mma_s32` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs index 1b8de4ad0b..eb559797a0 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `scalar_arithmetic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs index 89948f1903..8971f26cf9 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `scalar_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs index 18ed5d285f..e210ba4716 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `scalar_math` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs index b77e9f114e..89e157a6f3 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `sparse_mma` intrinsics. @@ -9372,3 +9372,611 @@ fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16_target_matches ] as &[&str] ); } + +#[test] +fn mma_sp_ordered_metadata_m16n8k8_f32_tf32_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1017").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k8_f32_tf32"); + assert_eq!(target.abi_id, "i1017"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k8, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Tf32, + b_element: GeneratedSparseMmaElement::Tf32, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19540", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_tf32_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1018").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k16_f32_tf32"); + assert_eq!(target.abi_id, "i1018"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Tf32, + b_element: GeneratedSparseMmaElement::Tf32, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19546", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_bf16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1019").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k16_f32_bf16"); + assert_eq!(target.abi_id, "i1019"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Bf16, + b_element: GeneratedSparseMmaElement::Bf16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19524", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f16_f16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1020").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k16_f16_f16"); + assert_eq!(target.abi_id, "i1020"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F16, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19554", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_f16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1021").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k16_f32_f16"); + assert_eq!(target.abi_id, "i1021"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19558", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f32_bf16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1022").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_f32_bf16"); + assert_eq!(target.abi_id, "i1022"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Bf16, + b_element: GeneratedSparseMmaElement::Bf16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19532", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f16_f16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1023").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_f16_f16"); + assert_eq!(target.abi_id, "i1023"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F16, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19566", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f32_f16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1024").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_f32_f16"); + assert_eq!(target.abi_id, "i1024"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19570", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs index 9e37d97c62..0383030ee5 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `sreg` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs index fe0ea22183..8f195314bf 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `stmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs index 4db496f265..3c27a0bc55 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `sync` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs index 0a7d0a8f7a..7a426078c9 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_cp` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs index f9aed014a8..dc89cd7db6 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_ld` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs index 22d628f0b2..c54a0d9dfb 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs index 808aa83a49..0cda2c16ea 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_mma_ws` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs index df45f043c6..bb715975d9 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_other` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs index 3d9892b84b..3991ace838 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_st` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs index c59271a5b0..e28b23b2de 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs index bde698d0c5..618ac1d220 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `vote` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs index 98537a1458..fb0472de5f 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `warp_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs index 6433246bd7..10e97c540b 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `warp_match` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs index c3ab9f3ff9..dca676d6d4 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `warp_shuffle` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs index 3f50d610d0..5439f27534 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `wgmma_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs index 8a980ccb15..2faa9f4706 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs index 5055d736ff..dbc1456ce6 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `vote` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs index f499220c51..a32f187d9a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `warp_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs index 0d1e510c3c..89b7eb16d6 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `warp_match` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs index 5b5699e1ce..4fdeff1822 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `warp_shuffle` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs index 64d794178b..cf249df41a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `wgmma_control` intrinsics. diff --git a/crates/dialect-nvvm/src/ops/generated/active_mask.rs b/crates/dialect-nvvm/src/ops/generated/active_mask.rs index 02e85137ea..6fd36c46e0 100644 --- a/crates/dialect-nvvm/src/ops/generated/active_mask.rs +++ b/crates/dialect-nvvm/src/ops/generated/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for the generated active warp mask. diff --git a/crates/dialect-nvvm/src/ops/generated/clc.rs b/crates/dialect-nvvm/src/ops/generated/clc.rs index 84ec931bf3..719587a8ea 100644 --- a/crates/dialect-nvvm/src/ops/generated/clc.rs +++ b/crates/dialect-nvvm/src/ops/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated Cluster Launch Control operations. diff --git a/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs b/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs index 3fde45d4bb..2abf87634f 100644 --- a/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs +++ b/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated operations for the closed cluster-barrier family. diff --git a/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs b/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs index 81592ff3d1..a0094b3b58 100644 --- a/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs +++ b/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for cluster address mapping and remote shared reads. diff --git a/crates/dialect-nvvm/src/ops/generated/cp_async.rs b/crates/dialect-nvvm/src/ops/generated/cp_async.rs index 52daf2d1d1..bfdf7df1ef 100644 --- a/crates/dialect-nvvm/src/ops/generated/cp_async.rs +++ b/crates/dialect-nvvm/src/ops/generated/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for classic `cp.async` instructions. diff --git a/crates/dialect-nvvm/src/ops/generated/debug_control.rs b/crates/dialect-nvvm/src/ops/generated/debug_control.rs index 19317c7e8f..839430981f 100644 --- a/crates/dialect-nvvm/src/ops/generated/debug_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated PTX debug controls. diff --git a/crates/dialect-nvvm/src/ops/generated/dotprod.rs b/crates/dialect-nvvm/src/ops/generated/dotprod.rs index 40ec5ac867..dcf7c5540d 100644 --- a/crates/dialect-nvvm/src/ops/generated/dotprod.rs +++ b/crates/dialect-nvvm/src/ops/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated packed integer dot products. diff --git a/crates/dialect-nvvm/src/ops/generated/elect.rs b/crates/dialect-nvvm/src/ops/generated/elect.rs index 7b0bcd7f80..7ea74086fb 100644 --- a/crates/dialect-nvvm/src/ops/generated/elect.rs +++ b/crates/dialect-nvvm/src/ops/generated/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated warp leader-election operation. diff --git a/crates/dialect-nvvm/src/ops/generated/execution_control.rs b/crates/dialect-nvvm/src/ops/generated/execution_control.rs index 43fc403653..bd9b471375 100644 --- a/crates/dialect-nvvm/src/ops/generated/execution_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated counted-barrier, grid-dependency, and register-control operations. diff --git a/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs b/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs index 6e036f91bd..0ad3ccaee6 100644 --- a/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs +++ b/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for extended floating-point min/max. diff --git a/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs b/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs index 9d7928eaf4..91dfd9f3cc 100644 --- a/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs +++ b/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated extended integer min/max. diff --git a/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs b/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs index 336af324b9..502a277900 100644 --- a/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation and compatibility carriers for generated `ldmatrix`. diff --git a/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs b/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs index 6aa1f62b1a..cdc1a745b0 100644 --- a/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs +++ b/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the basic shared-memory mbarrier lifecycle. diff --git a/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs b/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs index 2347d51072..25f2e928e8 100644 --- a/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs +++ b/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for extended mbarrier and async-proxy instructions. diff --git a/crates/dialect-nvvm/src/ops/generated/mod.rs b/crates/dialect-nvvm/src/ops/generated/mod.rs index 3f4f637b53..fceec69a6b 100644 --- a/crates/dialect-nvvm/src/ops/generated/mod.rs +++ b/crates/dialect-nvvm/src/ops/generated/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. mod active_mask; diff --git a/crates/dialect-nvvm/src/ops/generated/movmatrix.rs b/crates/dialect-nvvm/src/ops/generated/movmatrix.rs index 278419a6ad..3f9dfc3062 100644 --- a/crates/dialect-nvvm/src/ops/generated/movmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated in-register matrix transpose. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_alu.rs b/crates/dialect-nvvm/src/ops/generated/packed_alu.rs index 6a65a36a58..747341c533 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_alu.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated packed floating-point arithmetic. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs b/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs index 6d6379159f..ed4f3bd28d 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for the closed generated packed-atomic family. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs b/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs index 7ca226ea7b..c86238ed69 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated packed conversion. diff --git a/crates/dialect-nvvm/src/ops/generated/prmt.rs b/crates/dialect-nvvm/src/ops/generated/prmt.rs index 77fc3f4888..0867dc0b28 100644 --- a/crates/dialect-nvvm/src/ops/generated/prmt.rs +++ b/crates/dialect-nvvm/src/ops/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for the closed generated `prmt` family. diff --git a/crates/dialect-nvvm/src/ops/generated/redux.rs b/crates/dialect-nvvm/src/ops/generated/redux.rs index ed8cb6122c..bf37c7c519 100644 --- a/crates/dialect-nvvm/src/ops/generated/redux.rs +++ b/crates/dialect-nvvm/src/ops/generated/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural NVVM operations for the closed generated `redux.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/register_mma.rs b/crates/dialect-nvvm/src/ops/generated/register_mma.rs index 2f03347ce3..fb53aab546 100644 --- a/crates/dialect-nvvm/src/ops/generated/register_mma.rs +++ b/crates/dialect-nvvm/src/ops/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated register-only `mma.sync` variants. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs b/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs index 07ed1b904b..b39c85afe9 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated scalar arithmetic. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs b/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs index 366d3732f9..6e26abcae5 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated `f32` to TF32 conversions. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_math.rs b/crates/dialect-nvvm/src/ops/generated/scalar_math.rs index 762ca9ecad..7d09d1d353 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_math.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated scalar math. diff --git a/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs b/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs index ac88cf0715..133bbf4c6c 100644 --- a/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs +++ b/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated sparse MMA variants. @@ -32,6 +32,8 @@ use pliron_derive::{pliron_attr, pliron_op}; #[pliron_attr(name = "nvvm.sparse_mma_shape", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] pub enum SparseMmaShapeAttr { + M16n8k8, + M16n8k16, M16n8k32, M16n8k64, M16n8k128, @@ -48,6 +50,9 @@ pub enum SparseMmaAccumulatorAttr { #[pliron_attr(name = "nvvm.sparse_mma_element", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] pub enum SparseMmaElementAttr { + F16, + Bf16, + Tf32, E2m1, E2m3, E3m2, @@ -83,7 +88,9 @@ pub enum SparseMmaMetadataAttr { #[pliron_attr(name = "nvvm.sparse_mma_selector", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] +#[allow(clippy::enum_variant_names)] pub enum SparseMmaSelectorAttr { + ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero, } @@ -1502,6 +1509,225 @@ impl Verify for SparseMmaOp { ], 1, ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + &[ + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[MmaCarrier::U32, MmaCarrier::U32], + 4, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 4, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 4, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 2, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + &[ + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[MmaCarrier::U32, MmaCarrier::U32], + 2, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 2, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 2, + ), ( Some(&SparseMmaShapeAttr::M16n8k32), Some(&SparseMmaAccumulatorAttr::S32), @@ -3853,6 +4079,37 @@ impl Verify for SparseMmaOp { ], 1, ), + ( + Some(&SparseMmaShapeAttr::M16n8k8), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 4, + ), _ => { return verify_err!( op.loc(), diff --git a/crates/dialect-nvvm/src/ops/generated/sreg.rs b/crates/dialect-nvvm/src/ops/generated/sreg.rs index f1eaa8d6fa..9f390fef7b 100644 --- a/crates/dialect-nvvm/src/ops/generated/sreg.rs +++ b/crates/dialect-nvvm/src/ops/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural NVVM operations for generated special-register reads. diff --git a/crates/dialect-nvvm/src/ops/generated/stmatrix.rs b/crates/dialect-nvvm/src/ops/generated/stmatrix.rs index 93f8e3345b..b1c78acdc8 100644 --- a/crates/dialect-nvvm/src/ops/generated/stmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the four generated `stmatrix` stores. diff --git a/crates/dialect-nvvm/src/ops/generated/sync.rs b/crates/dialect-nvvm/src/ops/generated/sync.rs index 1e2636b3a6..6ce7490d94 100644 --- a/crates/dialect-nvvm/src/ops/generated/sync.rs +++ b/crates/dialect-nvvm/src/ops/generated/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated CTA synchronization. diff --git a/crates/dialect-nvvm/src/ops/generated/tcgen05.rs b/crates/dialect-nvvm/src/ops/generated/tcgen05.rs index 8f823f2635..d36204155e 100644 --- a/crates/dialect-nvvm/src/ops/generated/tcgen05.rs +++ b/crates/dialect-nvvm/src/ops/generated/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated Tensor Core Generation 5 operations. diff --git a/crates/dialect-nvvm/src/ops/generated/tma.rs b/crates/dialect-nvvm/src/ops/generated/tma.rs index ba0846ae8c..0e49d1d159 100644 --- a/crates/dialect-nvvm/src/ops/generated/tma.rs +++ b/crates/dialect-nvvm/src/ops/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated Tensor Memory Accelerator operations. diff --git a/crates/dialect-nvvm/src/ops/generated/vote.rs b/crates/dialect-nvvm/src/ops/generated/vote.rs index 9b49c05fdb..7fd6b7fd5f 100644 --- a/crates/dialect-nvvm/src/ops/generated/vote.rs +++ b/crates/dialect-nvvm/src/ops/generated/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the generated `vote.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs b/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs index 98cb1f2ee6..a5561906a0 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated warp synchronization. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_match.rs b/crates/dialect-nvvm/src/ops/generated/warp_match.rs index ed238b70fc..7d9efee361 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_match.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the generated `match.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs b/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs index 2be9829bc3..811d3595a0 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the generated `shfl.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs b/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs index f6cded3be4..e9e15cd722 100644 --- a/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated WGMMA controls. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs index fa3d0ee436..98376900d4 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `active_mask` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs index b2b49b1210..6c3107f469 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `clc` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs index e284705fd4..7afac1b083 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `cluster_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs index fbfc12ac7b..ff5a48b819 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `cluster_memory` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs index 3312f8e893..907375e555 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `cp_async` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs index c672535cea..718a16aa35 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `debug_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs index f99923ce34..fe038ceb3a 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `dotprod` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs index eb655c16d3..f49b75a9ee 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `elect` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs index 155ff85762..f557543c85 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `execution_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs index b7bfdf7123..146dff1407 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `extended_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs index 744eca8fd4..cee1b74fc8 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Shared glue for the generated intrinsic dispatch shards. @@ -215,9 +215,11 @@ pub(super) fn import_generated_tcgen05_store_operands( #[derive(Clone, Copy)] pub(super) enum GeneratedMmaImportAdapter { C2U32A2U32B1U32ToD2U32, + C2U32A2U32B2U32ToD2U32, C2U32A4U32B2U32ToD2U32, C2U32A4U32B4U32ToD2U32, C4F32A2U32B1U32ToD4F32, + C4F32A2U32B2U32ToD4F32, C4F32A4U32B2U32ToD4F32, C4F32A4U32B4U32ToD4F32, C2F64A1F64B1F64ToD2F64, @@ -297,6 +299,9 @@ pub(super) fn import_generated_mma_operands( GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32 => { (u32_ty, 2, u32_ty, 2, true, u32_ty, 1, false, u32_ty, 2) } + GeneratedMmaImportAdapter::C2U32A2U32B2U32ToD2U32 => { + (u32_ty, 2, u32_ty, 2, true, u32_ty, 2, true, u32_ty, 2) + } GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32 => { (u32_ty, 2, u32_ty, 4, true, u32_ty, 2, true, u32_ty, 2) } @@ -306,6 +311,9 @@ pub(super) fn import_generated_mma_operands( GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32 => { (f32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, f32_ty, 4) } + GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32 => { + (f32_ty, 4, u32_ty, 2, true, u32_ty, 2, true, f32_ty, 4) + } GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32 => { (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4) } diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs index f7ad73a9b1..007a5bfeca 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `integer_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs index 62ccfecfcc..4506e61541 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `ldmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs index 60da8cafb9..7f461f2f0b 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `mbarrier_basic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs index 03eb80c0d8..ed0755db6a 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `mbarrier_extended` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs index a012876910..bfbfa19c18 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility path dispatch for CUDA intrinsics. @@ -1292,6 +1292,20 @@ pub fn is_generated_intrinsic_path(name: &str) -> bool { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175" @@ -1440,6 +1454,8 @@ pub fn is_generated_intrinsic_path(name: &str) -> bool { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305" | "cuda_device::wmma::movmatrix_trans_b16" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066" @@ -2761,6 +2777,13 @@ pub fn is_raw_generated_intrinsic_path(name: &str) -> bool { | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172" @@ -2835,6 +2858,7 @@ pub fn is_raw_generated_intrinsic_path(name: &str) -> bool { | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076" @@ -4384,6 +4408,20 @@ pub fn generated_intrinsic_marker(name: &str) -> Option<&'static str> { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite" => { Some("v1:i0209") } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" => Some("v1:i1020"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" => Some("v1:i1019"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" => Some("v1:i1021"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" => Some("v1:i1018"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" => Some("v1:i1023"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" => Some("v1:i1022"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" => Some("v1:i1024"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" => Some("v1:i0171"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175" @@ -4656,6 +4694,8 @@ pub fn generated_intrinsic_marker(name: &str) -> Option<&'static str> { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" => { Some("v1:i0185") } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" => Some("v1:i1017"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305" | "cuda_device::wmma::movmatrix_trans_b16" => Some("v1:i0305"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066" diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs index 353c51d0a9..c6487d688d 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `movmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs index 5918b8cbca..6373a8154c 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `packed_alu` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs index 7c74299f56..b4ad73e560 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `packed_atomic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs index 8dfde47605..4ae8d720ca 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `packed_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs index 91bea14f05..4f79483938 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `prmt` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs index 1d61bd50ca..a8e4ec8242 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `redux` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs index 82400b4c54..dd9098d421 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `register_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs index 2f4574dd7d..8cf21fc103 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `scalar_arithmetic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs index feb2c7d15a..4c251b7fd5 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `scalar_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs index cdd47c43be..3c374d1d41 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `scalar_math` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs index 3bd564342f..720c8e8357 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `sparse_mma` intrinsics. @@ -3162,6 +3162,564 @@ pub(super) fn try_dispatch( "mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite call without target block", )?)) } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0, 1, 2, or 3" + .to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C2U32A2U32B2U32ToD2U32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k16); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector( + ctx, + SparseMmaSelectorAttr::ImmediateZeroThroughThree, + ); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1020"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k16_f16_f16 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0, 1, 2, or 3" + .to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k16); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::Bf16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::Bf16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector( + ctx, + SparseMmaSelectorAttr::ImmediateZeroThroughThree, + ); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1019"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k16_f32_bf16 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0, 1, 2, or 3" + .to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k16); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector( + ctx, + SparseMmaSelectorAttr::ImmediateZeroThroughThree, + ); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1021"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k16_f32_f16 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0 or 1".to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k16); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::Tf32); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::Tf32); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1018"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k16_f32_tf32 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0 or 1".to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1023"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k32_f16_f16 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0 or 1".to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::Bf16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::Bf16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1022"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k32_f32_bf16 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0 or 1".to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1024"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k32_f32_f16 call without target block", + )?)) + } "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" => { require_arity(name, args.len(), 5, &loc)?; @@ -8934,6 +9492,88 @@ pub(super) fn try_dispatch( "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite call without target block", )?)) } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0, 1, 2, or 3" + .to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k8); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::Tf32); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::Tf32); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector( + ctx, + SparseMmaSelectorAttr::ImmediateZeroThroughThree, + ); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1017"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k8_f32_tf32 call without target block", + )?)) + } _ => Ok(None), } } diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs index 8e3576ffd3..d2a6576737 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `sreg` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs index 3352271bd4..f4b571eb28 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `stmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs index d35695c57b..018622d7cf 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `sync` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs index a075a65096..163c885263 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_cp` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs index a82de565eb..32b6a87bcb 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_ld` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs index 41d1e9c5db..3d49a32cd2 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs index 362d43b105..73097ee6af 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_other` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs index 8fdad16382..3d93bebb7f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_st` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs index e4fded9f3e..5248333ba4 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `active_mask` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs index 73b30c9fa8..a81a9d5d71 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `clc` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs index da61e70d23..840acbc0a0 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `cluster_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs index 7f6a16a5f3..7f62f58ae9 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `cluster_memory` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs index 7df312dd29..9651e805a2 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `cp_async` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs index 7043806e67..39bfcb80ab 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `debug_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs index f1da330a2f..0351348557 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `dotprod` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs index c53a1ebe5d..a5b8498067 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `elect` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs index 0bea23c8ee..61becaa954 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `execution_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs index fd1405a771..2f16ab8353 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `extended_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs index 5accc84f18..fe30da783e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `integer_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs index 64707bc938..16fc05b41b 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `ldmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs index 68c0171120..f6cf0946b7 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `mbarrier_basic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs index 28a9b32861..9de6a60fee 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `mbarrier_extended` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs index a1277f2019..ea8bff99de 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests, grouped per intrinsic family. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs index cf14870621..da2e2a458c 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `movmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs index 2072756df0..fb99c93ea1 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `packed_alu` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs index 3255a8a089..52de1ee35e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `packed_atomic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs index 3238d02ed1..49736da09b 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `packed_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs index cadcfb43e2..622815069f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `prmt` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs index b9747fd15d..9d8db61a8e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `redux` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs index 4b3a1164ec..ba34805dfc 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `register_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs index 8afdd2425b..2a3fd204ac 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `scalar_arithmetic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs index fddcc72473..4aa5faeea3 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `scalar_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs index 8ccba24380..6fa7f61514 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `scalar_math` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs index d900dde27c..db1822c891 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `sparse_mma` intrinsics. @@ -1468,6 +1468,258 @@ fn mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite_uses_only_canonical_or_com )); } #[test] +fn mma_sp_ordered_metadata_m16n8k16_f16_f16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020"), + Some("v1:i1020") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16"), + Some("v1:i1020") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1020" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_bf16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019"), + Some("v1:i1019") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16"), + Some("v1:i1019") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1019" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_f16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021"), + Some("v1:i1021") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16"), + Some("v1:i1021") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1021" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_tf32_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018"), + Some("v1:i1018") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32"), + Some("v1:i1018") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1018" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f16_f16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023"), + Some("v1:i1023") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16"), + Some("v1:i1023") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1023" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f32_bf16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022"), + Some("v1:i1022") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16"), + Some("v1:i1022") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1022" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f32_f16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024"), + Some("v1:i1024") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16"), + Some("v1:i1024") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1024" + )); +} +#[test] fn mma_sp_ordered_metadata_m16n8k32_s32_s8_uses_only_canonical_or_compatibility_defpaths() { assert!(is_generated_intrinsic_path( "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" @@ -4317,3 +4569,39 @@ fn mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite_uses_only_canonical_or_comp "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0185" )); } +#[test] +fn mma_sp_ordered_metadata_m16n8k8_f32_tf32_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017"), + Some("v1:i1017") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32"), + Some("v1:i1017") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1017" + )); +} diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs index d57afaf8b9..41faf00891 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `sreg` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs index 123dea71ef..9feaabb655 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `stmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs index 1d2f004eca..6fdbaed674 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `sync` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs index 3bf7e002b4..7fe9b0ed5c 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `tcgen05` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs index d90232c026..09ca7969b1 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `tma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs index 24097d3a3b..26becc17bd 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `vote` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs index a9a50e0428..f6c38de911 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `warp_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs index b6adbc4004..c45993fe17 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `warp_match` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs index 175497d691..4bb99e9f0f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `warp_shuffle` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs index ff47bb5e12..7f58427bb9 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `wgmma_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs index ce6ba88de9..603f0ada10 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs index daf2d731f1..b7540bf6c9 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `vote` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs index 6806b68f7c..95d14cc4c1 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `warp_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs index 0044599892..c5ffb8c2a2 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `warp_match` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs index 40b2953eb3..162643e718 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `warp_shuffle` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs index 123b91f453..bf09f709d3 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `wgmma_control` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs b/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs index a38a785133..1119572917 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `active_mask` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/clc.rs b/crates/mir-lower/src/convert/generated_intrinsics/clc.rs index 42c76a4b6d..b7b984700e 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/clc.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `clc` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs b/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs index bbb06ae711..20dfdc1efa 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `cluster_barrier` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs b/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs index be9fcf6d05..c146e2c014 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `cluster_memory` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs b/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs index 177f784c52..118476117b 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `cp_async` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs index fbee4caa2a..50d71b8cfa 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `debug_control` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs b/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs index 10e3fbdd09..8f0323e5b2 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `dotprod` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/elect.rs b/crates/mir-lower/src/convert/generated_intrinsics/elect.rs index 4897239e2c..400042282c 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/elect.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `elect` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs index b26d04999d..0d8f898f47 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `execution_control` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs b/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs index d2b58ec384..2d0734ce54 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `extended_minmax` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs b/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs index 181de5993a..bcd696270f 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `integer_minmax` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs index 97835198f7..dd95ff8a84 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `ldmatrix` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs index 0dbd6e975a..5da32ca804 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `mbarrier_basic` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs index 05eb706c8a..bcd24eb824 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `mbarrier_extended` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mod.rs b/crates/mir-lower/src/convert/generated_intrinsics/mod.rs index d274b6ba2f..40d7656ef6 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/mod.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces for admitted CUDA intrinsic families. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs index 9944c97e71..02db8175b4 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `movmatrix` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs index 0b525a39f5..5a6b3c6ae4 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `packed_alu` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs index 3f8a901f19..dabbf20f69 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `packed_atomic` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs index d704c656c7..12114930bf 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `packed_conversion` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs b/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs index 073f9ac51c..69b59d384e 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `prmt` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/redux.rs b/crates/mir-lower/src/convert/generated_intrinsics/redux.rs index 8a6c3aa4f9..d8c765a644 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/redux.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `redux` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs b/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs index 3da91c5498..260aaca47c 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `register_mma` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs index 94a7806a9e..1a591cb172 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `scalar_arithmetic` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs index 78326c3a6b..b9b1926978 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `scalar_conversion` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs index 8cc762f837..9479653ac9 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `scalar_math` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs b/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs index 7137face5d..923e38fe2a 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `sparse_mma` intrinsics. @@ -723,6 +723,125 @@ impl MirToLlvmConversion for SparseMmaOp { "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n", ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + GeneratedMmaResultType::I32, + 2, + 8, + "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6, $7}, {$2, $3}, $8, $9;", + "=r,=r,r,r,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + GeneratedMmaResultType::F32, + 4, + 10, + "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + GeneratedMmaResultType::F32, + 4, + 10, + "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + GeneratedMmaResultType::F32, + 4, + 14, + "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + GeneratedMmaResultType::I32, + 2, + 12, + "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;", + "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + GeneratedMmaResultType::F32, + 4, + 14, + "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + GeneratedMmaResultType::F32, + 4, + 14, + "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n", + ), ( Some(&SparseMmaShapeAttr::M16n8k32), Some(&SparseMmaAccumulatorAttr::S32), @@ -1981,6 +2100,23 @@ impl MirToLlvmConversion for SparseMmaOp { "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n", ), + ( + Some(&SparseMmaShapeAttr::M16n8k8), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + GeneratedMmaResultType::F32, + 4, + 10, + "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n", + ), _ => { return pliron::input_err!( self.get_operation().deref(ctx).loc(), diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs b/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs index 65b1c2cb69..ee1fc507d8 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `sreg` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs index c5a7cca232..006f257558 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `stmatrix` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sync.rs b/crates/mir-lower/src/convert/generated_intrinsics/sync.rs index 953db0ff0a..c2d971d71d 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/sync.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `sync` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs b/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs index eb67c06d49..81eccd2611 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `tcgen05` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/tma.rs b/crates/mir-lower/src/convert/generated_intrinsics/tma.rs index f97729a5cd..68bfdc4373 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/tma.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `tma` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/vote.rs b/crates/mir-lower/src/convert/generated_intrinsics/vote.rs index be32d42082..5fb5cffedd 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/vote.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `vote` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs index b5b7fcd732..9cfb177f8b 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `warp_barrier` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs index 218a200470..17eb1fe0c6 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `warp_match` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs index 803dbef152..1513a08a2c 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `warp_shuffle` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs index 7a1fc426e5..c1d4ff45c1 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `wgmma_control` intrinsics. diff --git a/crates/rustc-codegen-cuda/src/generated_intrinsics.rs b/crates/rustc-codegen-cuda/src/generated_intrinsics.rs index 3e4381babb..ce111f6bfc 100644 --- a/crates/rustc-codegen-cuda/src/generated_intrinsics.rs +++ b/crates/rustc-codegen-cuda/src/generated_intrinsics.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated collector predicates for intrinsic placeholder functions. @@ -591,6 +591,13 @@ pub(crate) const GENERATED_INTRINSIC_CANONICAL_PATHS: &[&str] = &[ "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172", @@ -665,6 +672,7 @@ pub(crate) const GENERATED_INTRINSIC_CANONICAL_PATHS: &[&str] = &[ "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076", @@ -1610,6 +1618,13 @@ pub(crate) const GENERATED_INTRINSIC_PUBLIC_PATHS: &[&str] = &[ "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", @@ -1684,6 +1699,7 @@ pub(crate) const GENERATED_INTRINSIC_PUBLIC_PATHS: &[&str] = &[ "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32", "cuda_intrinsics::matrix::movmatrix_trans_b16", "cuda_intrinsics::bf16x2::mul_bf16x2", "cuda_intrinsics::f16x2::mul_f16x2", @@ -2635,6 +2651,13 @@ pub(crate) fn is_generated_intrinsic_canonical_path(path: &str) -> bool { | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172" @@ -2709,6 +2732,7 @@ pub(crate) fn is_generated_intrinsic_canonical_path(path: &str) -> bool { | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076" @@ -3656,6 +3680,13 @@ pub(crate) fn is_generated_intrinsic_compatibility_path(path: &str) -> bool { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8" @@ -3730,6 +3761,7 @@ pub(crate) fn is_generated_intrinsic_compatibility_path(path: &str) -> bool { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" | "cuda_device::wmma::movmatrix_trans_b16" | "cuda_device::bf16x2::mul_bf16x2" | "cuda_device::f16x2::mul_f16x2" diff --git a/cuda-oxide-book/compiler/mlir-dialects.md b/cuda-oxide-book/compiler/mlir-dialects.md index fb19382e58..af51fbfd29 100644 --- a/cuda-oxide-book/compiler/mlir-dialects.md +++ b/cuda-oxide-book/compiler/mlir-dialects.md @@ -296,11 +296,11 @@ they become `call` instructions to `@llvm.nvvm.*` intrinsics. ### Architecture Coverage -At catalog SHA-256 `49bcd626` (the stamp in every `ops/generated/` file +At catalog SHA-256 `a6962ae6` (the stamp in every `ops/generated/` file header), the dialect holds 575 operations across 42 modules, and they come from two different places. The split is the first thing to know about it, because it decides where -- and whether -- you would add one. If the header -stamp no longer starts with `49bcd626`, the counts on this page predate the +stamp no longer starts with `a6962ae6`, the counts on this page predate the catalog you are reading. **Hand-written**, directly under `crates/dialect-nvvm/src/ops/`. These are the @@ -320,7 +320,7 @@ describe. There are seven modules and 26 operations: **Generated**, under `ops/generated/`, from `intrinsics/catalog.json` by `cuda-intrinsics-gen`. Every file there opens with `// @generated ... DO NOT EDIT.`, and editing one by hand is undone by the next generator run. This is -the large majority -- 35 modules and 549 operations, resolved from 1016 catalog +the large majority -- 35 modules and 549 operations, resolved from 1024 catalog entries, since several intrinsics can share one structural op: | Area | Modules | Ops | diff --git a/intrinsics/abi-v1.toml b/intrinsics/abi-v1.toml index 9722a224b2..d9a24131d8 100644 --- a/intrinsics/abi-v1.toml +++ b/intrinsics/abi-v1.toml @@ -7082,3 +7082,59 @@ status = "active" catalog_id = "ex2_approx_f16" operation_key = "scalar.math.ex2.approx.f16" raw_rust_signature = { safe = true, arguments = ["u16"], result = "u16" } + +[[entry]] +abi_id = "i1017" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k8_f32_tf32" +operation_key = "matrix.mma.sp.m16n8k8.row.col.f32.tf32.tf32.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32"], result = "[f32; 4]" } + +[[entry]] +abi_id = "i1018" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k16_f32_tf32" +operation_key = "matrix.mma.sp.m16n8k16.row.col.f32.tf32.tf32.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 4]", "[u32; 4]", "u32", "u32"], result = "[f32; 4]" } + +[[entry]] +abi_id = "i1019" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k16_f32_bf16" +operation_key = "matrix.mma.sp.m16n8k16.row.col.f32.bf16.bf16.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32"], result = "[f32; 4]" } + +[[entry]] +abi_id = "i1020" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k16_f16_f16" +operation_key = "matrix.mma.sp.m16n8k16.row.col.f16.f16.f16.f16.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[u32; 2]", "[u32; 2]", "[u32; 2]", "u32", "u32"], result = "[u32; 2]" } + +[[entry]] +abi_id = "i1021" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k16_f32_f16" +operation_key = "matrix.mma.sp.m16n8k16.row.col.f32.f16.f16.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32"], result = "[f32; 4]" } + +[[entry]] +abi_id = "i1022" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k32_f32_bf16" +operation_key = "matrix.mma.sp.m16n8k32.row.col.f32.bf16.bf16.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 4]", "[u32; 4]", "u32", "u32"], result = "[f32; 4]" } + +[[entry]] +abi_id = "i1023" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k32_f16_f16" +operation_key = "matrix.mma.sp.m16n8k32.row.col.f16.f16.f16.f16.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[u32; 2]", "[u32; 4]", "[u32; 4]", "u32", "u32"], result = "[u32; 2]" } + +[[entry]] +abi_id = "i1024" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k32_f32_f16" +operation_key = "matrix.mma.sp.m16n8k32.row.col.f32.f16.f16.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 4]", "[u32; 4]", "u32", "u32"], result = "[f32; 4]" } diff --git a/intrinsics/catalog.json b/intrinsics/catalog.json index 9eb7f586a3..f3e5a9bd4f 100644 --- a/intrinsics/catalog.json +++ b/intrinsics/catalog.json @@ -11,11 +11,12 @@ }, "inputs": { "imported_sha256": "3f54245b231a5b6e19f3225710c3865b7e1a106242cce873250ef5fdc32e532e", - "overlay_sha256": "8efecd8698b59175e08f188d8a187766d7fa2201f6cbb2370b2d9a6dae7f4cad", - "abi_ledger_sha256": "598477ba5afa075a76df9e1fd907885e6251649b061cdc1f1f578b7b0d951678", + "overlay_sha256": "79ed6245b63d59adf0d8255e692bb3f1715c130e0bcd17bf46660a5d079eb71e", + "abi_ledger_sha256": "a9092483a256cb48c4dc6ef98a15bb7568dad8f0586aa35866c0318d2e9ffafd", "evidence_sha256": [ "cuda-12.0-libnvvm-12.0.140-ex2-f16.json:7102ea7d567ff2d2eb75a0384148d2e5eb6e605c26a5b98c71371fa3c46adef6", "cuda-12.9-libnvvm-12.9.86-f32x2.json:bc5bb505677989affa9ac1044da772b4eb349700dc65e16f09fffffa1f5c493e", + "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json:083fc9da4b1049abecde81cbb9739578d8a9e19eaca416b1ff6f4c5a80b04042", "cuda-13.3-libnvvm-13.3.33-blackwell-ldmatrix.json:806155f5468d672b6bd969b72d9821155cc6a1c4422eb210ca0fc0a78eb295fb", "cuda-13.3-libnvvm-13.3.33-clc.json:0a3e049a8b606276302acf6d2f3dd1d41b632b04dd72799a7def8ebbec414752", "cuda-13.3-libnvvm-13.3.33-cluster-barrier.json:069e53acf46319a89ea69de86225724c8193d84a54df3c179818d8f2c782f4cc", @@ -106,6 +107,7 @@ "rust-llvm-23.1.0-16696adc-scalar-math.json:1a9e7994e07b5b53390df11a7e1805aa46176d21c8ed7e988433aee578c4dd47", "rust-llvm-23.1.0-16696adc-sparse-mma-int8-m16n8k64.json:2c0588c11569a4057647c099cfca9adfc449f3b3aea4e387f440a47e79d9b241", "rust-llvm-23.1.0-16696adc-sparse-mma-int8.json:9023c5c47bf1ad7266a13be8c4024d34e4e7d1efed6582affbbb9cdcdcfbea01", + "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json:4c80351dd79d8a04c87779cdf21542b7e11182b198b0b2b39e220157f45501a1", "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-f8f6f4-f16.json:8569d7303b1a5af418214f2548e4b10c825c06c524dbecbc35b8ab0d4e2cf7ba", "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-f8f6f4-f32.json:d6b99f5f4fb88b145f24dba9da662e052137b05a6d2616731d08ab858a4e0541", "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-int4-m16n8k128.json:3a65cb8976f0fb35ca50a7e58943ed092d4e33a8dba84b637402bd3224d7ef21", @@ -189467,17 +189469,17 @@ "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.s8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k16_f16_f16", + "operation_key": "matrix.mma.sp.m16n8k16.row.col.f16.f16.f16.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f16_f16" }, "selections": [ { - "source_record": "anonymous_19644", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19554", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -189485,32 +189487,30 @@ } ], "rust": { - "abi_id": "i0171", + "abi_id": "i1020", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8", + "name": "mma_sp_ordered_metadata_m16n8k16_f16_f16", "arguments": [ - "[i32; 4]", + "[u32; 2]", "[u32; 2]", "[u32; 2]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[u32; 2]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", "i32", "i32", "u32", @@ -189521,37 +189521,31 @@ "u32" ], "results": [ - "i32", - "i32", "i32", "i32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f16.f16", "arguments": [ - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "v2f16", + "v2f16" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -189575,7 +189569,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[u32; 2]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -189585,7 +189579,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -189611,18 +189605,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 signed INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -189633,22 +189627,37 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", "target": { "minimum_ptx": "8.5", "hardware": { @@ -189661,22 +189670,22 @@ ] } }, - "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", - "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", - "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", - "build_id_prefix": "2330c0", - "status": "validated", + "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", + "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", + "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", + "build_id_prefix": null, + "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx93" + "ptx88" ], - "representation": "convergent ordered-metadata sparse m16n8k32 signed INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -189685,36 +189694,66 @@ { "targets": [ "sm_80", - "ptx93" + "ptx88" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_80", + "ptx88" + ], + "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", + "tool_version": "CUDA 12.9 nvJitLink V12.9.86", + "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + }, + { + "targets": [ + "sm_120", + "ptx88" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { - "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "s8", - "b_element": "s8", + "shape": "m16n8k16", + "accumulator": "f16", + "a_element": "f16", + "b_element": "f16", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "not_applicable", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero_through_three", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c2_u32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d2_u32", + "llvm_adapter": "a2_v2_f16_b2_v2_f16_c2_v2_f16_metadata_i32_selector_i32_to_d2_v2_f16", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -189723,18 +189762,18 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k32", + "m16n8k16", "row", "col", - "s32", - "s8", - "s8", - "s32" + "f16", + "f16", + "f16", + "f16" ], "operands": [ { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", @@ -189746,7 +189785,7 @@ }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register" @@ -189756,20 +189795,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.s8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k16_f32_bf16", + "operation_key": "matrix.mma.sp.m16n8k16.row.col.f32.bf16.bf16.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_bf16" }, "selections": [ { - "source_record": "anonymous_19705", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19524", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -189777,34 +189816,34 @@ } ], "rust": { - "abi_id": "i0175", + "abi_id": "i1019", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k16_f32_bf16", "arguments": [ - "[i32; 4]", + "[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", "u32", "u32", "u32", @@ -189813,37 +189852,37 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.bf16", "arguments": [ "i32", "i32", "i32", "i32", - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -189867,7 +189906,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -189877,7 +189916,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -189903,18 +189942,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 signed saturating INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -189925,22 +189964,37 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", "target": { "minimum_ptx": "8.5", "hardware": { @@ -189953,22 +190007,22 @@ ] } }, - "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", - "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", - "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", - "build_id_prefix": "2330c0", - "status": "validated", + "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", + "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", + "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", + "build_id_prefix": null, + "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx93" + "ptx88" ], - "representation": "convergent ordered-metadata sparse m16n8k32 signed saturating INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -189977,36 +190031,66 @@ { "targets": [ "sm_80", - "ptx93" + "ptx88" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_80", + "ptx88" + ], + "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", + "tool_version": "CUDA 12.9 nvJitLink V12.9.86", + "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + }, + { + "targets": [ + "sm_120", + "ptx88" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { - "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "s8", - "b_element": "s8", + "shape": "m16n8k16", + "accumulator": "f32", + "a_element": "bf16", + "b_element": "bf16", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "not_applicable", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero_through_three", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a2_i32_b2_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -190015,14 +190099,13 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k32", + "m16n8k16", "row", "col", - "satfinite", - "s32", - "s8", - "s8", - "s32" + "f32", + "bf16", + "bf16", + "f32" ], "operands": [ { @@ -190049,20 +190132,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.u8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k16_f32_f16", + "operation_key": "matrix.mma.sp.m16n8k16.row.col.f32.f16.f16.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f32_f32" }, "selections": [ { - "source_record": "anonymous_19649", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19558", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -190070,34 +190153,34 @@ } ], "rust": { - "abi_id": "i0172", + "abi_id": "i1021", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", + "name": "mma_sp_ordered_metadata_m16n8k16_f32_f16", "arguments": [ - "[i32; 4]", + "[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", "u32", "u32", "u32", @@ -190106,37 +190189,37 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f32.f32", "arguments": [ - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -190160,7 +190243,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -190170,7 +190253,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -190196,18 +190279,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190218,22 +190301,37 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", "target": { "minimum_ptx": "8.5", "hardware": { @@ -190246,22 +190344,22 @@ ] } }, - "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", - "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", - "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", - "build_id_prefix": "2330c0", - "status": "validated", + "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", + "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", + "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", + "build_id_prefix": null, + "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx93" + "ptx88" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190270,36 +190368,66 @@ { "targets": [ "sm_80", - "ptx93" + "ptx88" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_80", + "ptx88" + ], + "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", + "tool_version": "CUDA 12.9 nvJitLink V12.9.86", + "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + }, + { + "targets": [ + "sm_120", + "ptx88" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { - "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "s8", - "b_element": "u8", + "shape": "m16n8k16", + "accumulator": "f32", + "a_element": "f16", + "b_element": "f16", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "not_applicable", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero_through_three", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a2_v2_f16_b2_v2_f16_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -190308,13 +190436,13 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k32", + "m16n8k16", "row", "col", - "s32", - "s8", - "u8", - "s32" + "f32", + "f16", + "f16", + "f32" ], "operands": [ { @@ -190341,20 +190469,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.u8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k16_f32_tf32", + "operation_key": "matrix.mma.sp.m16n8k16.row.col.f32.tf32.tf32.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_tf32" }, "selections": [ { - "source_record": "anonymous_19708", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19546", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -190362,34 +190490,38 @@ } ], "rust": { - "abi_id": "i0176", + "abi_id": "i1018", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k16_f32_tf32", "arguments": [ - "[i32; 4]", - "[u32; 2]", - "[u32; 2]", + "[f32; 4]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", + "u32", + "u32", + "u32", + "u32", "u32", "u32", "u32", @@ -190398,14 +190530,14 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.tf32", "arguments": [ "i32", "i32", @@ -190415,20 +190547,24 @@ "i32", "i32", "i32", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -190452,7 +190588,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -190462,7 +190598,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -190488,18 +190624,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190510,22 +190646,37 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", "target": { "minimum_ptx": "8.5", "hardware": { @@ -190538,22 +190689,22 @@ ] } }, - "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", - "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", - "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", - "build_id_prefix": "2330c0", - "status": "validated", + "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", + "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", + "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", + "build_id_prefix": null, + "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx93" + "ptx88" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190562,36 +190713,66 @@ { "targets": [ "sm_80", - "ptx93" + "ptx88" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_80", + "ptx88" + ], + "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", + "tool_version": "CUDA 12.9 nvJitLink V12.9.86", + "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + }, + { + "targets": [ + "sm_120", + "ptx88" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { - "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "s8", - "b_element": "u8", + "shape": "m16n8k16", + "accumulator": "f32", + "a_element": "tf32", + "b_element": "tf32", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "not_applicable", "metadata": "ordered", "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -190600,14 +190781,13 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k32", + "m16n8k16", "row", "col", - "satfinite", - "s32", - "s8", - "u8", - "s32" + "f32", + "tf32", + "tf32", + "f32" ], "operands": [ { @@ -190616,11 +190796,11 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -190634,20 +190814,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.u8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k32_f16_f16", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.f16.f16.f16.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16" }, "selections": [ { - "source_record": "anonymous_19658", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19566", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -190655,24 +190835,24 @@ } ], "rust": { - "abi_id": "i0173", + "abi_id": "i1023", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8", + "name": "mma_sp_ordered_metadata_m16n8k32_f16_f16", "arguments": [ - "[i32; 4]", - "[u32; 2]", "[u32; 2]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[u32; 2]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" ] }, "dialect": { @@ -190681,8 +190861,10 @@ "operands": [ "i32", "i32", - "i32", - "i32", + "u32", + "u32", + "u32", + "u32", "u32", "u32", "u32", @@ -190691,37 +190873,35 @@ "u32" ], "results": [ - "i32", - "i32", "i32", "i32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16", "arguments": [ - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "v2f16", + "v2f16" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -190745,7 +190925,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[u32; 2]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -190755,7 +190935,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -190781,18 +190961,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 unsigned INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190803,22 +190983,37 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", "target": { "minimum_ptx": "8.5", "hardware": { @@ -190831,22 +191026,22 @@ ] } }, - "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", - "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", - "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", - "build_id_prefix": "2330c0", - "status": "validated", + "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", + "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", + "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", + "build_id_prefix": null, + "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx93" + "ptx88" ], - "representation": "convergent ordered-metadata sparse m16n8k32 unsigned INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190855,36 +191050,66 @@ { "targets": [ "sm_80", - "ptx93" + "ptx88" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_80", + "ptx88" + ], + "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", + "tool_version": "CUDA 12.9 nvJitLink V12.9.86", + "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + }, + { + "targets": [ + "sm_120", + "ptx88" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "u8", - "b_element": "u8", + "accumulator": "f16", + "a_element": "f16", + "b_element": "f16", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "not_applicable", "metadata": "ordered", "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c2_u32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d2_u32", + "llvm_adapter": "a4_v2_f16_b4_v2_f16_c2_v2_f16_metadata_i32_selector_i32_to_d2_v2_f16", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -190896,27 +191121,27 @@ "m16n8k32", "row", "col", - "s32", - "u8", - "u8", - "s32" + "f16", + "f16", + "f16", + "f16" ], "operands": [ { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register" @@ -190926,20 +191151,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.s8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k32_f32_bf16", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.f32.bf16.bf16.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_u8_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16" }, "selections": [ { - "source_record": "anonymous_19654", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19532", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -190947,34 +191172,38 @@ } ], "rust": { - "abi_id": "i0174", + "abi_id": "i1022", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", + "name": "mma_sp_ordered_metadata_m16n8k32_f32_bf16", "arguments": [ - "[i32; 4]", - "[u32; 2]", - "[u32; 2]", + "[f32; 4]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", + "u32", + "u32", + "u32", + "u32", "u32", "u32", "u32", @@ -190983,14 +191212,14 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.u8.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16", "arguments": [ "i32", "i32", @@ -191000,20 +191229,24 @@ "i32", "i32", "i32", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -191037,7 +191270,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -191047,7 +191280,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -191073,18 +191306,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191095,22 +191328,37 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", "target": { "minimum_ptx": "8.5", "hardware": { @@ -191123,22 +191371,22 @@ ] } }, - "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", - "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", - "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", - "build_id_prefix": "2330c0", - "status": "validated", + "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", + "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", + "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", + "build_id_prefix": null, + "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx93" + "ptx88" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191147,36 +191395,66 @@ { "targets": [ "sm_80", - "ptx93" + "ptx88" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_80", + "ptx88" + ], + "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", + "tool_version": "CUDA 12.9 nvJitLink V12.9.86", + "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + }, + { + "targets": [ + "sm_120", + "ptx88" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "u8", - "b_element": "s8", + "accumulator": "f32", + "a_element": "bf16", + "b_element": "bf16", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "not_applicable", "metadata": "ordered", "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -191188,10 +191466,10 @@ "m16n8k32", "row", "col", - "s32", - "u8", - "s8", - "s32" + "f32", + "bf16", + "bf16", + "f32" ], "operands": [ { @@ -191200,11 +191478,11 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -191218,20 +191496,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.s8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k32_f32_f16", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.f32.f16.f16.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_u8_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32" }, "selections": [ { - "source_record": "anonymous_19711", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19570", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -191239,34 +191517,38 @@ } ], "rust": { - "abi_id": "i0178", + "abi_id": "i1024", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k32_f32_f16", "arguments": [ - "[i32; 4]", - "[u32; 2]", - "[u32; 2]", + "[f32; 4]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", + "u32", + "u32", + "u32", + "u32", "u32", "u32", "u32", @@ -191275,37 +191557,41 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.u8.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32", "arguments": [ - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -191329,7 +191615,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -191339,7 +191625,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -191365,18 +191651,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191387,22 +191673,37 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", "target": { "minimum_ptx": "8.5", "hardware": { @@ -191415,22 +191716,22 @@ ] } }, - "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", - "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", - "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", - "build_id_prefix": "2330c0", - "status": "validated", + "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", + "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", + "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", + "build_id_prefix": null, + "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx93" + "ptx88" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191439,36 +191740,66 @@ { "targets": [ "sm_80", - "ptx93" + "ptx88" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_80", + "ptx88" + ], + "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", + "tool_version": "CUDA 12.9 nvJitLink V12.9.86", + "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + }, + { + "targets": [ + "sm_120", + "ptx88" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "u8", - "b_element": "s8", + "accumulator": "f32", + "a_element": "f16", + "b_element": "f16", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "not_applicable", "metadata": "ordered", "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a4_v2_f16_b4_v2_f16_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -191480,11 +191811,10 @@ "m16n8k32", "row", "col", - "satfinite", - "s32", - "u8", - "s8", - "s32" + "f32", + "f16", + "f16", + "f32" ], "operands": [ { @@ -191493,11 +191823,11 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -191511,20 +191841,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.u8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.s8.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8" }, "selections": [ { - "source_record": "anonymous_19714", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19644", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -191532,9 +191862,9 @@ } ], "rust": { - "abi_id": "i0177", + "abi_id": "i0171", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -191546,10 +191876,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" ] }, "dialect": { @@ -191575,7 +191905,2054 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 signed INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 signed INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "s8", + "b_element": "s8", + "a_layout": "row", + "b_layout": "col", + "overflow": "wrapping", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "s32", + "s8", + "s8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.s8.s32.satfinite.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8" + }, + "selections": [ + { + "source_record": "anonymous_19705", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0175", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 signed saturating INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 signed saturating INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "s8", + "b_element": "s8", + "a_layout": "row", + "b_layout": "col", + "overflow": "satfinite", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "satfinite", + "s32", + "s8", + "s8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.u8.s32.wrapping.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8_u8" + }, + "selections": [ + { + "source_record": "anonymous_19649", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0172", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8.u8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "s8", + "b_element": "u8", + "a_layout": "row", + "b_layout": "col", + "overflow": "wrapping", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "s32", + "s8", + "u8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.u8.s32.satfinite.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8_u8" + }, + "selections": [ + { + "source_record": "anonymous_19708", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0176", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8.u8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "s8", + "b_element": "u8", + "a_layout": "row", + "b_layout": "col", + "overflow": "satfinite", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "satfinite", + "s32", + "s8", + "u8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.u8.s32.wrapping.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_u8" + }, + "selections": [ + { + "source_record": "anonymous_19658", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0173", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.u8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 unsigned INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 unsigned INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "u8", + "b_element": "u8", + "a_layout": "row", + "b_layout": "col", + "overflow": "wrapping", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "s32", + "u8", + "u8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.s8.s32.wrapping.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_u8_s8" + }, + "selections": [ + { + "source_record": "anonymous_19654", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0174", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.u8.s8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "u8", + "b_element": "s8", + "a_layout": "row", + "b_layout": "col", + "overflow": "wrapping", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "s32", + "u8", + "s8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.s8.s32.satfinite.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_u8_s8" + }, + "selections": [ + { + "source_record": "anonymous_19711", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0178", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.u8.s8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "u8", + "b_element": "s8", + "a_layout": "row", + "b_layout": "col", + "overflow": "satfinite", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "satfinite", + "s32", + "u8", + "s8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.u8.s32.satfinite.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_u8" + }, + "selections": [ + { + "source_record": "anonymous_19714", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0177", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.u8", "arguments": [ "i32", "i32", @@ -194691,7 +197068,590 @@ "kind::f8f6f4", "f16", "e2m1", - "e5m2", + "e5m2", + "f16" + ], + "operands": [ + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse e2m1 A and e5m2 B fragments and adds a packed F16 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e2m1.f16.not_applicable.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e2m1_f16" + }, + "selections": [ + { + "source_record": "anonymous_19895", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->hasMMABlockScale()" + ] + } + ], + "rust": { + "abi_id": "i0530", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", + "arguments": [ + "[u32; 2]", + "[u32; 4]", + "[u32; 4]", + "u32", + "u32" + ], + "result": "[u32; 2]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e2m1.f16", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "v2f16", + "v2f16", + "i32", + "i32" + ], + "results": [ + "v2f16", + "v2f16" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.7", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "exact_architecture", + "sm": 120 + }, + { + "kind": "family_target", + "sm": 120 + }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 + } + ] + }, + "ptx_result": "[u32; 2]", + "targets": "sm_120a|sm_120f|sm_121a|sm_121f", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_120a", + "ptx_feature": "+ptx87" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.7", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "exact_architecture", + "sm": 120 + }, + { + "kind": "family_target", + "sm": 120 + }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_120a", + "ptx87" + ], + "representation": "typed declaration and convergence comparison", + "stage": "declaration_canonicalization", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "The 23,732-byte typed source (SHA-256 ce6f6e73ffd41f5f6c6cf658ff41ce903b7c90afaca38a6279281d2ee8ff60e0) confirmed the imported A4, B4, C2-v2f16, metadata, selector signature. All 25 declarations canonicalized to nocallback nounwind memory(none), with selector immarg range [0,1), and without convergent. Optimization retained only 25 of 50 duplicate typed calls, so this is comparison evidence and not the selected production carrier.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_120a", + "ptx87" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX in public C, A, B, metadata, selector order", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Pinned LLVM lowered the 18,084-byte all-forms source (SHA-256 cf0e3082d15b64340dab3480ede99adff7d8bada7b8cdfec2fa91e990562ca5e) to 8,991-byte PTX (SHA-256 fc0b67574e5ed2b3cab9a6cdd97d86cd0574c4704f35b0fb73ebaea5acbcb725) containing the exact 25-form matrix. The convergent inline duplicate fixture retained all 50 calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_120a", + "ptx87" + ], + "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 560446ab6b41e45ca208fddc2c1439d9e851b1b67a9de920e6e81026863352b2); its 27,724-byte SASS dump (SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270) retains 25 unique QMMA forms. PTX 8.6, sm_120, sm_100a, selector 1, and dynamic selectors were rejected.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120f", + "ptx88" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 08692523a26e16fd8a05a2646f71a3ade9e95aa2c3f41028f870d7c9bcab999b) containing the exact 25-form matrix with no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_120f", + "ptx88" + ], + "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 90a0b9bf02df8ca3cb34f867b29b56a65d79a5c9033ea9dc5084ee210b5f6f1d); its 27,701-byte SASS dump (SHA-256 80831cd9a7cde8fd67343302591ea08a30327606719fb232d8e28e812d9c5e46) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_121a", + "ptx88" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 afec2d0be50c3984867f5402585ba0dbd4f3fe3ac74e6527ab47628ebefd2be4) containing the exact 25-form matrix with no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_121a", + "ptx88" + ], + "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 acd74cced6969aaf6f09afb935d33978ed2753a7f1558240dc4607027b15d502); its 27,724-byte SASS dump (SHA-256 16087533ef8f20e8804dda13de37ea8fce10b505d82ca7c93c5d9d484b0b26e9) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_121f", + "ptx88" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 fae27977151c805ee3bc805a88241f4d4318f0575c558106ed9ba6a0a94f0699) containing the exact 25-form matrix with no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_121f", + "ptx88" + ], + "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 501b5715323e83c1543a76999f6fb747c6ce1ab0be09aeb637fb95ce69cb28da); its 27,701-byte SASS dump (SHA-256 677ac56dab06986c7ec8938dcc82e23d3637bca8f58282140d0fbce8f483d353) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.7", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "exact_architecture", + "sm": 120 + }, + { + "kind": "family_target", + "sm": 120 + }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_120a", + "ptx93" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX in public C, A, B, metadata, selector order", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 fe613b565fd6028eaaff9b7df078c93af5b47163f19a9685a43bd6dee28fea6d), produced 11,504-byte LTOIR (SHA-256 aac8c70c26474ccd692e45a453d9f7236c8e040d66dd47047b582524d9deff4c), and emitted no unresolved llvm.nvvm calls or extern declarations.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_120a", + "ptx93" + ], + "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 560446ab6b41e45ca208fddc2c1439d9e851b1b67a9de920e6e81026863352b2) retaining all 25 unique QMMA forms; the 27,724-byte SASS dump has SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120a", + "ptx93" + ], + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 a7acfd0a342d4b87745305a9c0eb0b7fc1a4e6a8afffdd63bfcbc6a9188a35fb); its 27,724-byte SASS dump (SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "compute_120f", + "ptx93" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 51f4c9986dc2523a8745ee1a131c400b87b714f44c881d6d102b363529e1b429), produced 11,500-byte LTOIR (SHA-256 678e88e228100ca0802c84918f31d08c024a76e9078074fc6e8671b342d27a6e), and emitted no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_120f", + "ptx93" + ], + "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 90a0b9bf02df8ca3cb34f867b29b56a65d79a5c9033ea9dc5084ee210b5f6f1d); its 27,701-byte SASS dump (SHA-256 80831cd9a7cde8fd67343302591ea08a30327606719fb232d8e28e812d9c5e46) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120f", + "ptx93" + ], + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 e3da7f6df18cbc6f195ebf2127f542d93d22301d33406ad9fc86209583209b1b); its terminal SASS matches the 27,701-byte ptxas result and retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "compute_121a", + "ptx93" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 d667d6730fb487ff7b7812afbb66ca3ddc3ece9ee59230883d91a7286fb8cf35), produced 11,504-byte LTOIR (SHA-256 2c1de19d40ea54c10e3f7f9c5fdad148f8fed26db5a775c63301e695d4a486b8), and emitted no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_121a", + "ptx93" + ], + "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 acd74cced6969aaf6f09afb935d33978ed2753a7f1558240dc4607027b15d502); its 27,724-byte SASS dump (SHA-256 16087533ef8f20e8804dda13de37ea8fce10b505d82ca7c93c5d9d484b0b26e9) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_121a", + "ptx93" + ], + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 5686bd4d7d44b05d50052c4e12c6385af60430e6717e53c535acc7e5b17daac6); its terminal SASS matches the 27,724-byte ptxas result and retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "compute_121f", + "ptx93" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 8a939f3816e414a14d24fe9e2bcb28b97f30db931b2c71c6c0e1c2c793329855), produced 11,500-byte LTOIR (SHA-256 778bc963dbd6301055eaf20892234aea60113ca053682d6c6010b1f1b915bcbe), and emitted no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_121f", + "ptx93" + ], + "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 501b5715323e83c1543a76999f6fb747c6ce1ab0be09aeb637fb95ce69cb28da); its 27,701-byte SASS dump (SHA-256 677ac56dab06986c7ec8938dcc82e23d3637bca8f58282140d0fbce8f483d353) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_121f", + "ptx93" + ], + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 7dbcfbe36d9fca5c8916689289754c0041ace50971ff0f9a337c649bc326e2f5); its terminal SASS matches the 27,701-byte ptxas result and retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k64", + "accumulator": "f16", + "a_element": "e2m3", + "b_element": "e2m1", + "a_layout": "row", + "b_layout": "col", + "overflow": "not_applicable", + "metadata": "ordered", + "selector": "immediate_zero", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c2_u32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d2_u32", + "llvm_adapter": "a4_i32_b4_i32_c2_v2_f16_metadata_i32_selector_i32_to_d2_v2_f16", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k64", + "row", + "col", + "kind::f8f6f4", + "f16", + "e2m3", + "e2m1", "f16" ], "operands": [ @@ -194719,29 +197679,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e5m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e2m1 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e2m1.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e2m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e2m1_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e2m3_f16" }, "selections": [ { - "source_record": "anonymous_19895", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19887", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0530", + "abi_id": "i0531", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -194753,10 +197713,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16" ] }, "dialect": { @@ -194782,7 +197742,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e2m1.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e2m3.f16", "arguments": [ "i32", "i32", @@ -195249,7 +198209,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m3", - "b_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -195274,7 +198234,7 @@ "kind::f8f6f4", "f16", "e2m3", - "e2m1", + "e2m3", "f16" ], "operands": [ @@ -195302,29 +198262,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e2m1 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e2m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e2m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e3m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e2m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e3m2_f16" }, "selections": [ { - "source_record": "anonymous_19887", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19879", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0531", + "abi_id": "i0532", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -195336,10 +198296,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16" ] }, "dialect": { @@ -195365,7 +198325,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e2m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e3m2.f16", "arguments": [ "i32", "i32", @@ -195832,7 +198792,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m3", - "b_element": "e2m3", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -195857,7 +198817,7 @@ "kind::f8f6f4", "f16", "e2m3", - "e2m3", + "e3m2", "f16" ], "operands": [ @@ -195885,29 +198845,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e2m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e3m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e3m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e4m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e3m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e4m3_f16" }, "selections": [ { - "source_record": "anonymous_19879", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19863", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0532", + "abi_id": "i0533", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -195919,10 +198879,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16" ] }, "dialect": { @@ -195948,7 +198908,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e3m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e4m3.f16", "arguments": [ "i32", "i32", @@ -196415,7 +199375,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m3", - "b_element": "e3m2", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -196440,7 +199400,7 @@ "kind::f8f6f4", "f16", "e2m3", - "e3m2", + "e4m3", "f16" ], "operands": [ @@ -196468,29 +199428,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e3m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e4m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e4m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e5m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e4m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e5m2_f16" }, "selections": [ { - "source_record": "anonymous_19863", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19871", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0533", + "abi_id": "i0534", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -196502,10 +199462,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16" ] }, "dialect": { @@ -196531,7 +199491,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e4m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e5m2.f16", "arguments": [ "i32", "i32", @@ -196998,7 +199958,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m3", - "b_element": "e4m3", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -197023,7 +199983,7 @@ "kind::f8f6f4", "f16", "e2m3", - "e4m3", + "e5m2", "f16" ], "operands": [ @@ -197051,29 +200011,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e4m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e5m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e5m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e2m1.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e5m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e2m1_f16" }, "selections": [ { - "source_record": "anonymous_19871", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19854", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0534", + "abi_id": "i0535", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -197085,10 +200045,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16" ] }, "dialect": { @@ -197114,7 +200074,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e5m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e2m1.f16", "arguments": [ "i32", "i32", @@ -197580,8 +200540,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f16", - "a_element": "e2m3", - "b_element": "e5m2", + "a_element": "e3m2", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -197605,8 +200565,8 @@ "col", "kind::f8f6f4", "f16", - "e2m3", - "e5m2", + "e3m2", + "e2m1", "f16" ], "operands": [ @@ -197634,29 +200594,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e5m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e2m1 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e2m1.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e2m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e2m1_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e2m3_f16" }, "selections": [ { - "source_record": "anonymous_19854", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19846", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0535", + "abi_id": "i0536", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -197668,10 +200628,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16" ] }, "dialect": { @@ -197697,7 +200657,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e2m1.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e2m3.f16", "arguments": [ "i32", "i32", @@ -198164,7 +201124,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e3m2", - "b_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -198189,7 +201149,7 @@ "kind::f8f6f4", "f16", "e3m2", - "e2m1", + "e2m3", "f16" ], "operands": [ @@ -198217,29 +201177,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e2m1 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e2m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e2m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e3m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e2m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e3m2_f16" }, "selections": [ { - "source_record": "anonymous_19846", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19838", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0536", + "abi_id": "i0537", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -198251,10 +201211,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16" ] }, "dialect": { @@ -198280,7 +201240,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e2m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e3m2.f16", "arguments": [ "i32", "i32", @@ -198747,7 +201707,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e3m2", - "b_element": "e2m3", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -198772,7 +201732,7 @@ "kind::f8f6f4", "f16", "e3m2", - "e2m3", + "e3m2", "f16" ], "operands": [ @@ -198800,29 +201760,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e2m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e3m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e3m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e4m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e3m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e4m3_f16" }, "selections": [ { - "source_record": "anonymous_19838", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19822", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0537", + "abi_id": "i0538", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -198834,10 +201794,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16" ] }, "dialect": { @@ -198863,7 +201823,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e3m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e4m3.f16", "arguments": [ "i32", "i32", @@ -199330,7 +202290,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e3m2", - "b_element": "e3m2", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -199355,7 +202315,7 @@ "kind::f8f6f4", "f16", "e3m2", - "e3m2", + "e4m3", "f16" ], "operands": [ @@ -199383,29 +202343,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e3m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e4m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e4m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e5m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e4m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e5m2_f16" }, "selections": [ { - "source_record": "anonymous_19822", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19830", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0538", + "abi_id": "i0539", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -199417,10 +202377,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16" ] }, "dialect": { @@ -199446,7 +202406,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e4m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e5m2.f16", "arguments": [ "i32", "i32", @@ -199913,7 +202873,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e3m2", - "b_element": "e4m3", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -199938,7 +202898,7 @@ "kind::f8f6f4", "f16", "e3m2", - "e4m3", + "e5m2", "f16" ], "operands": [ @@ -199966,29 +202926,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e4m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e5m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e5m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e2m1.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e5m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e2m1_f16" }, "selections": [ { - "source_record": "anonymous_19830", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19772", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0539", + "abi_id": "i0540", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -200000,10 +202960,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16" ] }, "dialect": { @@ -200029,7 +202989,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e5m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e2m1.f16", "arguments": [ "i32", "i32", @@ -200495,8 +203455,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f16", - "a_element": "e3m2", - "b_element": "e5m2", + "a_element": "e4m3", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -200520,8 +203480,8 @@ "col", "kind::f8f6f4", "f16", - "e3m2", - "e5m2", + "e4m3", + "e2m1", "f16" ], "operands": [ @@ -200549,29 +203509,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e5m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e2m1 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e2m1.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e2m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e2m1_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e2m3_f16" }, "selections": [ { - "source_record": "anonymous_19772", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19763", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0540", + "abi_id": "i0541", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -200583,10 +203543,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16" ] }, "dialect": { @@ -200612,7 +203572,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e2m1.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e2m3.f16", "arguments": [ "i32", "i32", @@ -201079,7 +204039,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e4m3", - "b_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -201104,7 +204064,7 @@ "kind::f8f6f4", "f16", "e4m3", - "e2m1", + "e2m3", "f16" ], "operands": [ @@ -201132,29 +204092,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e2m1 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e2m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e2m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e3m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e2m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e3m2_f16" }, "selections": [ { - "source_record": "anonymous_19763", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19754", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0541", + "abi_id": "i0542", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -201166,10 +204126,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16" ] }, "dialect": { @@ -201195,7 +204155,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e2m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e3m2.f16", "arguments": [ "i32", "i32", @@ -201662,7 +204622,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e4m3", - "b_element": "e2m3", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -201687,7 +204647,7 @@ "kind::f8f6f4", "f16", "e4m3", - "e2m3", + "e3m2", "f16" ], "operands": [ @@ -201715,29 +204675,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e2m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e3m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e3m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e4m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e3m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e4m3_f16" }, "selections": [ { - "source_record": "anonymous_19754", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19734", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0542", + "abi_id": "i0543", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -201749,10 +204709,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16" ] }, "dialect": { @@ -201778,7 +204738,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e3m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e4m3.f16", "arguments": [ "i32", "i32", @@ -202245,7 +205205,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e4m3", - "b_element": "e3m2", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -202270,7 +205230,7 @@ "kind::f8f6f4", "f16", "e4m3", - "e3m2", + "e4m3", "f16" ], "operands": [ @@ -202298,29 +205258,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e3m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e4m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e4m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e5m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e4m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e5m2_f16" }, "selections": [ { - "source_record": "anonymous_19734", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19745", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0543", + "abi_id": "i0544", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -202332,10 +205292,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16" ] }, "dialect": { @@ -202361,7 +205321,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e4m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e5m2.f16", "arguments": [ "i32", "i32", @@ -202828,7 +205788,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e4m3", - "b_element": "e4m3", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -202853,7 +205813,7 @@ "kind::f8f6f4", "f16", "e4m3", - "e4m3", + "e5m2", "f16" ], "operands": [ @@ -202881,29 +205841,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e4m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e5m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e5m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e2m1.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e5m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e2m1_f16" }, "selections": [ { - "source_record": "anonymous_19745", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19813", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0544", + "abi_id": "i0545", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -202915,10 +205875,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16" ] }, "dialect": { @@ -202944,7 +205904,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e5m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e2m1.f16", "arguments": [ "i32", "i32", @@ -203410,8 +206370,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f16", - "a_element": "e4m3", - "b_element": "e5m2", + "a_element": "e5m2", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -203435,8 +206395,8 @@ "col", "kind::f8f6f4", "f16", - "e4m3", "e5m2", + "e2m1", "f16" ], "operands": [ @@ -203464,29 +206424,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e5m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e2m1 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e2m1.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e2m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e2m1_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e2m3_f16" }, "selections": [ { - "source_record": "anonymous_19813", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19805", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0545", + "abi_id": "i0546", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -203498,10 +206458,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16" ] }, "dialect": { @@ -203527,7 +206487,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e2m1.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e2m3.f16", "arguments": [ "i32", "i32", @@ -203994,7 +206954,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e5m2", - "b_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -204019,7 +206979,7 @@ "kind::f8f6f4", "f16", "e5m2", - "e2m1", + "e2m3", "f16" ], "operands": [ @@ -204047,29 +207007,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e2m1 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e2m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e2m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e3m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e2m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e3m2_f16" }, "selections": [ { - "source_record": "anonymous_19805", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19797", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0546", + "abi_id": "i0547", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -204081,10 +207041,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16" ] }, "dialect": { @@ -204110,7 +207070,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e2m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e3m2.f16", "arguments": [ "i32", "i32", @@ -204577,7 +207537,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e5m2", - "b_element": "e2m3", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -204602,7 +207562,7 @@ "kind::f8f6f4", "f16", "e5m2", - "e2m3", + "e3m2", "f16" ], "operands": [ @@ -204630,29 +207590,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e2m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e3m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e3m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e4m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e3m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e4m3_f16" }, "selections": [ { - "source_record": "anonymous_19797", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19781", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0547", + "abi_id": "i0548", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -204664,10 +207624,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16" ] }, "dialect": { @@ -204693,7 +207653,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e3m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e4m3.f16", "arguments": [ "i32", "i32", @@ -205160,7 +208120,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e5m2", - "b_element": "e3m2", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -205185,7 +208145,7 @@ "kind::f8f6f4", "f16", "e5m2", - "e3m2", + "e4m3", "f16" ], "operands": [ @@ -205213,29 +208173,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e3m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e4m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e4m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e5m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e4m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e5m2_f16" }, "selections": [ { - "source_record": "anonymous_19781", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19789", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0548", + "abi_id": "i0549", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -205247,10 +208207,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16" ] }, "dialect": { @@ -205276,7 +208236,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e4m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e5m2.f16", "arguments": [ "i32", "i32", @@ -205743,7 +208703,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e5m2", - "b_element": "e4m3", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -205768,7 +208728,7 @@ "kind::f8f6f4", "f16", "e5m2", - "e4m3", + "e5m2", "f16" ], "operands": [ @@ -205796,52 +208756,54 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e4m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e5m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e5m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e2m1.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e5m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e2m1_f32" }, "selections": [ { - "source_record": "anonymous_19789", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19940", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0549", + "abi_id": "i0227", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", "arguments": [ - "[u32; 2]", + "[f32; 4]", "[u32; 4]", "[u32; 4]", "u32", "u32" ], - "result": "[u32; 2]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", "u32", "u32", "u32", @@ -205854,12 +208816,14 @@ "u32" ], "results": [ - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e5m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e2m1.f32", "arguments": [ "i32", "i32", @@ -205869,20 +208833,24 @@ "i32", "i32", "i32", - "v2f16", - "v2f16", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "v2f16", - "v2f16" + "f32", + "f32", + "f32", + "f32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -205918,7 +208886,7 @@ } ] }, - "ptx_result": "[u32; 2]", + "ptx_result": "[f32; 4]", "targets": "sm_120a|sm_120f|sm_121a|sm_121f", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -205973,26 +208941,11 @@ "sm_120a", "ptx87" ], - "representation": "typed declaration and convergence comparison", - "stage": "declaration_canonicalization", - "mechanism": "typed_nvvm", - "outcome": "succeeded", - "detail": "The 23,732-byte typed source (SHA-256 ce6f6e73ffd41f5f6c6cf658ff41ce903b7c90afaca38a6279281d2ee8ff60e0) confirmed the imported A4, B4, C2-v2f16, metadata, selector signature. All 25 declarations canonicalized to nocallback nounwind memory(none), with selector immarg range [0,1), and without convergent. Optimization retained only 25 of 50 duplicate typed calls, so this is comparison evidence and not the selected production carrier.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_120a", - "ptx87" - ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM lowered the 18,084-byte all-forms source (SHA-256 cf0e3082d15b64340dab3480ede99adff7d8bada7b8cdfec2fa91e990562ca5e) to 8,991-byte PTX (SHA-256 fc0b67574e5ed2b3cab9a6cdd97d86cd0574c4704f35b0fb73ebaea5acbcb725) containing the exact 25-form matrix. The convergent inline duplicate fixture retained all 50 calls.", + "detail": "Pinned LLVM lowered the 28,839-byte all-forms source (SHA-256 5518d5dfb092f5ae3ccefe1e7e66eb4df9db7da480722e390587490c6ce8832a) to 12,015-byte PTX (SHA-256 0d93ea01d39bc512b96becf2ad799522d9d5187c17d521294eecd4e69c055e66) containing the exact 25-form matrix at sm_120a and PTX 8.7.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -206003,26 +208956,62 @@ "sm_120a", "ptx87" ], - "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "representation": "exact-floor ordered kind::f8f6f4 F32 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 560446ab6b41e45ca208fddc2c1439d9e851b1b67a9de920e6e81026863352b2); its 27,724-byte SASS dump (SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270) retains 25 unique QMMA forms. PTX 8.6, sm_120, sm_100a, selector 1, and dynamic selectors were rejected.", + "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms. PTX 8.6, sm_120, selector 1, and dynamic selectors were rejected.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.7", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "exact_architecture", + "sm": 120 + }, + { + "kind": "family_target", + "sm": 120 + }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ { "targets": [ - "sm_120f", - "ptx88" + "compute_120a", + "ptx93" ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 08692523a26e16fd8a05a2646f71a3ade9e95aa2c3f41028f870d7c9bcab999b) containing the exact 25-form matrix with no unresolved calls.", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 11,910-byte PTX (SHA-256 a096494f6b066927107cf222f784d1a586ed1cf3ab766669b741e429f03f4427) and produced 14,052-byte LTOIR (SHA-256 99941daa24a78884788ed0908a3764f596c527e6ab621d6085c549aea9575377).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -206030,14 +209019,14 @@ }, { "targets": [ - "sm_120f", - "ptx88" + "sm_120a", + "ptx93" ], - "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "representation": "libNVVM-emitted ordered kind::f8f6f4 F32 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 90a0b9bf02df8ca3cb34f867b29b56a65d79a5c9033ea9dc5084ee210b5f6f1d); its 27,701-byte SASS dump (SHA-256 80831cd9a7cde8fd67343302591ea08a30327606719fb232d8e28e812d9c5e46) retains 25 unique QMMA forms.", + "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3) retaining all 25 unique QMMA forms.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -206045,44 +209034,269 @@ }, { "targets": [ - "sm_121a", - "ptx88" + "sm_120a", + "ptx93" ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", - "stage": "backend_codegen", + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 F32 matrix", + "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 afec2d0be50c3984867f5402585ba0dbd4f3fe3ac74e6527ab47628ebefd2be4) containing the exact 25-form matrix with no unresolved calls.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null + "detail": "CUDA 13.3 nvJitLink produced a 12,144-byte cubin (SHA-256 62457debbb99023b09b3701e14974a97cfc5761f931ebf9f0d9e2bada3e3a642); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k64", + "accumulator": "f32", + "a_element": "e2m1", + "b_element": "e2m1", + "a_layout": "row", + "b_layout": "col", + "overflow": "not_applicable", + "metadata": "ordered", + "selector": "immediate_zero", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k64", + "row", + "col", + "kind::f8f6f4", + "f32", + "e2m1", + "e2m1", + "f32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse e2m1 A and e2m1 B fragments and adds an f32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e2m3.f32.not_applicable.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e2m3_f32" + }, + "selections": [ + { + "source_record": "anonymous_19932", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->hasMMABlockScale()" + ] + } + ], + "rust": { + "abi_id": "i0228", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", + "arguments": [ + "[f32; 4]", + "[u32; 4]", + "[u32; 4]", + "u32", + "u32" + ], + "result": "[f32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "f32", + "f32", + "f32", + "f32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "f32", + "f32", + "f32", + "f32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e2m3.f32", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "f32", + "f32", + "f32", + "f32", + "i32", + "i32" + ], + "results": [ + "f32", + "f32", + "f32", + "f32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.7", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "exact_architecture", + "sm": 120 }, { - "targets": [ - "sm_121a", - "ptx88" - ], - "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 acd74cced6969aaf6f09afb935d33978ed2753a7f1558240dc4607027b15d502); its 27,724-byte SASS dump (SHA-256 16087533ef8f20e8804dda13de37ea8fce10b505d82ca7c93c5d9d484b0b26e9) retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + "kind": "family_target", + "sm": 120 }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 + } + ] + }, + "ptx_result": "[f32; 4]", + "targets": "sm_120a|sm_120f|sm_121a|sm_121f", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_120a", + "ptx_feature": "+ptx87" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.7", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "exact_architecture", + "sm": 120 + }, + { + "kind": "family_target", + "sm": 120 + }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ { "targets": [ - "sm_121f", - "ptx88" + "sm_120a", + "ptx87" ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 fae27977151c805ee3bc805a88241f4d4318f0575c558106ed9ba6a0a94f0699) containing the exact 25-form matrix with no unresolved calls.", + "detail": "Pinned LLVM lowered the 28,839-byte all-forms source (SHA-256 5518d5dfb092f5ae3ccefe1e7e66eb4df9db7da480722e390587490c6ce8832a) to 12,015-byte PTX (SHA-256 0d93ea01d39bc512b96becf2ad799522d9d5187c17d521294eecd4e69c055e66) containing the exact 25-form matrix at sm_120a and PTX 8.7.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -206090,14 +209304,14 @@ }, { "targets": [ - "sm_121f", - "ptx88" + "sm_120a", + "ptx87" ], - "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "representation": "exact-floor ordered kind::f8f6f4 F32 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 501b5715323e83c1543a76999f6fb747c6ce1ab0be09aeb637fb95ce69cb28da); its 27,701-byte SASS dump (SHA-256 677ac56dab06986c7ec8938dcc82e23d3637bca8f58282140d0fbce8f483d353) retains 25 unique QMMA forms.", + "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms. PTX 8.6, sm_120, selector 1, and dynamic selectors were rejected.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -206144,11 +209358,11 @@ "compute_120a", "ptx93" ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 fe613b565fd6028eaaff9b7df078c93af5b47163f19a9685a43bd6dee28fea6d), produced 11,504-byte LTOIR (SHA-256 aac8c70c26474ccd692e45a453d9f7236c8e040d66dd47047b582524d9deff4c), and emitted no unresolved llvm.nvvm calls or extern declarations.", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 11,910-byte PTX (SHA-256 a096494f6b066927107cf222f784d1a586ed1cf3ab766669b741e429f03f4427) and produced 14,052-byte LTOIR (SHA-256 99941daa24a78884788ed0908a3764f596c527e6ab621d6085c549aea9575377).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -206159,11 +209373,11 @@ "sm_120a", "ptx93" ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", + "representation": "libNVVM-emitted ordered kind::f8f6f4 F32 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 560446ab6b41e45ca208fddc2c1439d9e851b1b67a9de920e6e81026863352b2) retaining all 25 unique QMMA forms; the 27,724-byte SASS dump has SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270.", + "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3) retaining all 25 unique QMMA forms.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -206174,148 +209388,13 @@ "sm_120a", "ptx93" ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", - "stage": "device_link", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 a7acfd0a342d4b87745305a9c0eb0b7fc1a4e6a8afffdd63bfcbc6a9188a35fb); its 27,724-byte SASS dump (SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270) retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" - }, - { - "targets": [ - "compute_120f", - "ptx93" - ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", - "stage": "backend_codegen", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 51f4c9986dc2523a8745ee1a131c400b87b714f44c881d6d102b363529e1b429), produced 11,500-byte LTOIR (SHA-256 678e88e228100ca0802c84918f31d08c024a76e9078074fc6e8671b342d27a6e), and emitted no unresolved calls.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_120f", - "ptx93" - ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 90a0b9bf02df8ca3cb34f867b29b56a65d79a5c9033ea9dc5084ee210b5f6f1d); its 27,701-byte SASS dump (SHA-256 80831cd9a7cde8fd67343302591ea08a30327606719fb232d8e28e812d9c5e46) retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, - { - "targets": [ - "sm_120f", - "ptx93" - ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", - "stage": "device_link", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 e3da7f6df18cbc6f195ebf2127f542d93d22301d33406ad9fc86209583209b1b); its terminal SASS matches the 27,701-byte ptxas result and retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" - }, - { - "targets": [ - "compute_121a", - "ptx93" - ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", - "stage": "backend_codegen", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 d667d6730fb487ff7b7812afbb66ca3ddc3ece9ee59230883d91a7286fb8cf35), produced 11,504-byte LTOIR (SHA-256 2c1de19d40ea54c10e3f7f9c5fdad148f8fed26db5a775c63301e695d4a486b8), and emitted no unresolved calls.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_121a", - "ptx93" - ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 acd74cced6969aaf6f09afb935d33978ed2753a7f1558240dc4607027b15d502); its 27,724-byte SASS dump (SHA-256 16087533ef8f20e8804dda13de37ea8fce10b505d82ca7c93c5d9d484b0b26e9) retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, - { - "targets": [ - "sm_121a", - "ptx93" - ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", - "stage": "device_link", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 5686bd4d7d44b05d50052c4e12c6385af60430e6717e53c535acc7e5b17daac6); its terminal SASS matches the 27,724-byte ptxas result and retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" - }, - { - "targets": [ - "compute_121f", - "ptx93" - ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", - "stage": "backend_codegen", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 8a939f3816e414a14d24fe9e2bcb28b97f30db931b2c71c6c0e1c2c793329855), produced 11,500-byte LTOIR (SHA-256 778bc963dbd6301055eaf20892234aea60113ca053682d6c6010b1f1b915bcbe), and emitted no unresolved calls.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_121f", - "ptx93" - ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 501b5715323e83c1543a76999f6fb747c6ce1ab0be09aeb637fb95ce69cb28da); its 27,701-byte SASS dump (SHA-256 677ac56dab06986c7ec8938dcc82e23d3637bca8f58282140d0fbce8f483d353) retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, - { - "targets": [ - "sm_121f", - "ptx93" - ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 F32 matrix", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 7dbcfbe36d9fca5c8916689289754c0041ace50971ff0f9a337c649bc326e2f5); its terminal SASS matches the 27,701-byte ptxas result and retains 25 unique QMMA forms.", + "detail": "CUDA 13.3 nvJitLink produced a 12,144-byte cubin (SHA-256 62457debbb99023b09b3701e14974a97cfc5761f931ebf9f0d9e2bada3e3a642); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" } @@ -206324,17 +209403,17 @@ ], "sparse_mma": { "shape": "m16n8k64", - "accumulator": "f16", - "a_element": "e5m2", - "b_element": "e5m2", + "accumulator": "f32", + "a_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", "metadata": "ordered", "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c2_u32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d2_u32", - "llvm_adapter": "a4_i32_b4_i32_c2_v2_f16_metadata_i32_selector_i32_to_d2_v2_f16", + "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -206349,15 +209428,15 @@ "row", "col", "kind::f8f6f4", - "f16", - "e5m2", - "e5m2", - "f16" + "f32", + "e2m1", + "e2m3", + "f32" ], "operands": [ { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -206369,7 +209448,7 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register" @@ -206379,29 +209458,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e5m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e2m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e2m1.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e3m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e2m1_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e3m2_f32" }, "selections": [ { - "source_record": "anonymous_19940", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19924", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0227", + "abi_id": "i0229", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -206413,10 +209492,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32" ] }, "dialect": { @@ -206446,7 +209525,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e2m1.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e3m2.f32", "arguments": [ "i32", "i32", @@ -206677,7 +209756,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m1", - "b_element": "e2m1", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -206702,7 +209781,7 @@ "kind::f8f6f4", "f32", "e2m1", - "e2m1", + "e3m2", "f32" ], "operands": [ @@ -206730,29 +209809,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e2m1 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e3m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e2m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e4m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e2m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e4m3_f32" }, "selections": [ { - "source_record": "anonymous_19932", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19908", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0228", + "abi_id": "i0230", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -206764,10 +209843,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32" ] }, "dialect": { @@ -206797,7 +209876,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e2m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e4m3.f32", "arguments": [ "i32", "i32", @@ -207028,7 +210107,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m1", - "b_element": "e2m3", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -207053,7 +210132,7 @@ "kind::f8f6f4", "f32", "e2m1", - "e2m3", + "e4m3", "f32" ], "operands": [ @@ -207081,29 +210160,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e2m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e4m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e3m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e5m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e3m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e5m2_f32" }, "selections": [ { - "source_record": "anonymous_19924", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19916", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0229", + "abi_id": "i0231", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -207115,10 +210194,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32" ] }, "dialect": { @@ -207148,7 +210227,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e3m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e5m2.f32", "arguments": [ "i32", "i32", @@ -207379,7 +210458,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m1", - "b_element": "e3m2", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -207404,7 +210483,7 @@ "kind::f8f6f4", "f32", "e2m1", - "e3m2", + "e5m2", "f32" ], "operands": [ @@ -207432,29 +210511,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e3m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e5m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e4m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e2m1.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e4m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e2m1_f32" }, "selections": [ { - "source_record": "anonymous_19908", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19899", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0230", + "abi_id": "i0232", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -207466,10 +210545,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32" ] }, "dialect": { @@ -207499,7 +210578,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e4m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e2m1.f32", "arguments": [ "i32", "i32", @@ -207729,8 +210808,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e2m1", - "b_element": "e4m3", + "a_element": "e2m3", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -207754,8 +210833,8 @@ "col", "kind::f8f6f4", "f32", + "e2m3", "e2m1", - "e4m3", "f32" ], "operands": [ @@ -207783,29 +210862,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e4m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e2m1 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e5m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e2m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e5m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e2m3_f32" }, "selections": [ { - "source_record": "anonymous_19916", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19891", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0231", + "abi_id": "i0233", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -207817,10 +210896,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32" ] }, "dialect": { @@ -207850,7 +210929,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e5m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e2m3.f32", "arguments": [ "i32", "i32", @@ -208080,8 +211159,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e2m1", - "b_element": "e5m2", + "a_element": "e2m3", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -208105,8 +211184,8 @@ "col", "kind::f8f6f4", "f32", - "e2m1", - "e5m2", + "e2m3", + "e2m3", "f32" ], "operands": [ @@ -208134,29 +211213,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e5m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e2m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e2m1.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e3m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e2m1_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e3m2_f32" }, "selections": [ { - "source_record": "anonymous_19899", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19883", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0232", + "abi_id": "i0234", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -208168,10 +211247,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32" ] }, "dialect": { @@ -208201,7 +211280,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e2m1.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e3m2.f32", "arguments": [ "i32", "i32", @@ -208432,7 +211511,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m3", - "b_element": "e2m1", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -208457,7 +211536,7 @@ "kind::f8f6f4", "f32", "e2m3", - "e2m1", + "e3m2", "f32" ], "operands": [ @@ -208485,29 +211564,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e2m1 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e3m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e2m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e4m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e2m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e4m3_f32" }, "selections": [ { - "source_record": "anonymous_19891", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19867", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0233", + "abi_id": "i0235", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -208519,10 +211598,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32" ] }, "dialect": { @@ -208552,7 +211631,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e2m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e4m3.f32", "arguments": [ "i32", "i32", @@ -208783,7 +211862,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m3", - "b_element": "e2m3", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -208808,7 +211887,7 @@ "kind::f8f6f4", "f32", "e2m3", - "e2m3", + "e4m3", "f32" ], "operands": [ @@ -208836,29 +211915,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e2m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e4m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e3m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e5m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e3m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e5m2_f32" }, "selections": [ { - "source_record": "anonymous_19883", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19875", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0234", + "abi_id": "i0236", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -208870,10 +211949,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32" ] }, "dialect": { @@ -208903,7 +211982,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e3m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e5m2.f32", "arguments": [ "i32", "i32", @@ -209134,7 +212213,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m3", - "b_element": "e3m2", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -209159,7 +212238,7 @@ "kind::f8f6f4", "f32", "e2m3", - "e3m2", + "e5m2", "f32" ], "operands": [ @@ -209187,29 +212266,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e3m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e5m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e4m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e2m1.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e4m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e2m1_f32" }, "selections": [ { - "source_record": "anonymous_19867", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19858", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0235", + "abi_id": "i0237", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -209221,10 +212300,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32" ] }, "dialect": { @@ -209254,7 +212333,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e4m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e2m1.f32", "arguments": [ "i32", "i32", @@ -209484,8 +212563,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e2m3", - "b_element": "e4m3", + "a_element": "e3m2", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -209509,8 +212588,8 @@ "col", "kind::f8f6f4", "f32", - "e2m3", - "e4m3", + "e3m2", + "e2m1", "f32" ], "operands": [ @@ -209538,29 +212617,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e4m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e2m1 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e5m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e2m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e5m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e2m3_f32" }, "selections": [ { - "source_record": "anonymous_19875", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19850", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0236", + "abi_id": "i0238", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -209572,10 +212651,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32" ] }, "dialect": { @@ -209605,7 +212684,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e5m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e2m3.f32", "arguments": [ "i32", "i32", @@ -209835,8 +212914,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e2m3", - "b_element": "e5m2", + "a_element": "e3m2", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -209860,8 +212939,8 @@ "col", "kind::f8f6f4", "f32", + "e3m2", "e2m3", - "e5m2", "f32" ], "operands": [ @@ -209889,29 +212968,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e5m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e2m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e2m1.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e3m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e2m1_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e3m2_f32" }, "selections": [ { - "source_record": "anonymous_19858", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19842", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0237", + "abi_id": "i0239", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -209923,10 +213002,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32" ] }, "dialect": { @@ -209956,7 +213035,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e2m1.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e3m2.f32", "arguments": [ "i32", "i32", @@ -210187,7 +213266,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e3m2", - "b_element": "e2m1", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -210212,7 +213291,7 @@ "kind::f8f6f4", "f32", "e3m2", - "e2m1", + "e3m2", "f32" ], "operands": [ @@ -210240,29 +213319,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e2m1 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e3m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e2m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e4m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e2m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e4m3_f32" }, "selections": [ { - "source_record": "anonymous_19850", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19826", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0238", + "abi_id": "i0240", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -210274,10 +213353,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32" ] }, "dialect": { @@ -210307,7 +213386,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e2m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e4m3.f32", "arguments": [ "i32", "i32", @@ -210538,7 +213617,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e3m2", - "b_element": "e2m3", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -210563,7 +213642,7 @@ "kind::f8f6f4", "f32", "e3m2", - "e2m3", + "e4m3", "f32" ], "operands": [ @@ -210591,29 +213670,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e2m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e4m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e3m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e5m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e3m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e5m2_f32" }, "selections": [ { - "source_record": "anonymous_19842", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19834", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0239", + "abi_id": "i0241", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -210625,10 +213704,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32" ] }, "dialect": { @@ -210658,7 +213737,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e3m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e5m2.f32", "arguments": [ "i32", "i32", @@ -210889,7 +213968,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e3m2", - "b_element": "e3m2", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -210914,7 +213993,7 @@ "kind::f8f6f4", "f32", "e3m2", - "e3m2", + "e5m2", "f32" ], "operands": [ @@ -210942,29 +214021,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e3m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e5m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e4m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e2m1.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e4m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e2m1_f32" }, "selections": [ { - "source_record": "anonymous_19826", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19776", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0240", + "abi_id": "i0242", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -210976,10 +214055,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32" ] }, "dialect": { @@ -211009,7 +214088,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e4m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e2m1.f32", "arguments": [ "i32", "i32", @@ -211239,8 +214318,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e3m2", - "b_element": "e4m3", + "a_element": "e4m3", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -211264,8 +214343,8 @@ "col", "kind::f8f6f4", "f32", - "e3m2", "e4m3", + "e2m1", "f32" ], "operands": [ @@ -211293,29 +214372,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e4m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e2m1 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e5m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e2m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e5m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e2m3_f32" }, "selections": [ { - "source_record": "anonymous_19834", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19767", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0241", + "abi_id": "i0243", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -211327,10 +214406,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32" ] }, "dialect": { @@ -211360,7 +214439,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e5m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e2m3.f32", "arguments": [ "i32", "i32", @@ -211590,8 +214669,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e3m2", - "b_element": "e5m2", + "a_element": "e4m3", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -211615,8 +214694,8 @@ "col", "kind::f8f6f4", "f32", - "e3m2", - "e5m2", + "e4m3", + "e2m3", "f32" ], "operands": [ @@ -211644,29 +214723,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e5m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e2m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e2m1.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e3m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e2m1_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e3m2_f32" }, "selections": [ { - "source_record": "anonymous_19776", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19758", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0242", + "abi_id": "i0244", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -211678,10 +214757,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32" ] }, "dialect": { @@ -211711,7 +214790,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e2m1.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e3m2.f32", "arguments": [ "i32", "i32", @@ -211942,7 +215021,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e4m3", - "b_element": "e2m1", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -211967,7 +215046,7 @@ "kind::f8f6f4", "f32", "e4m3", - "e2m1", + "e3m2", "f32" ], "operands": [ @@ -211995,29 +215074,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e2m1 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e3m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e2m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e4m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e2m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e4m3_f32" }, "selections": [ { - "source_record": "anonymous_19767", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19740", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0243", + "abi_id": "i0245", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -212029,10 +215108,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32" ] }, "dialect": { @@ -212062,7 +215141,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e2m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e4m3.f32", "arguments": [ "i32", "i32", @@ -212293,7 +215372,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e4m3", - "b_element": "e2m3", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -212318,7 +215397,7 @@ "kind::f8f6f4", "f32", "e4m3", - "e2m3", + "e4m3", "f32" ], "operands": [ @@ -212346,29 +215425,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e2m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e4m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e3m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e5m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e3m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e5m2_f32" }, "selections": [ { - "source_record": "anonymous_19758", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19749", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0244", + "abi_id": "i0246", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -212380,10 +215459,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32" ] }, "dialect": { @@ -212413,7 +215492,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e3m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e5m2.f32", "arguments": [ "i32", "i32", @@ -212644,7 +215723,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e4m3", - "b_element": "e3m2", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -212669,7 +215748,7 @@ "kind::f8f6f4", "f32", "e4m3", - "e3m2", + "e5m2", "f32" ], "operands": [ @@ -212697,29 +215776,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e3m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e5m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e4m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e2m1.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e4m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e2m1_f32" }, "selections": [ { - "source_record": "anonymous_19740", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19817", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0245", + "abi_id": "i0247", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -212731,10 +215810,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32" ] }, "dialect": { @@ -212764,7 +215843,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e4m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e2m1.f32", "arguments": [ "i32", "i32", @@ -212994,8 +216073,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e4m3", - "b_element": "e4m3", + "a_element": "e5m2", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -213019,8 +216098,8 @@ "col", "kind::f8f6f4", "f32", - "e4m3", - "e4m3", + "e5m2", + "e2m1", "f32" ], "operands": [ @@ -213048,29 +216127,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e4m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e2m1 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e5m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e2m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e5m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e2m3_f32" }, "selections": [ { - "source_record": "anonymous_19749", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19809", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0246", + "abi_id": "i0248", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -213082,10 +216161,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32" ] }, "dialect": { @@ -213115,7 +216194,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e5m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e2m3.f32", "arguments": [ "i32", "i32", @@ -213345,8 +216424,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e4m3", - "b_element": "e5m2", + "a_element": "e5m2", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -213370,8 +216449,8 @@ "col", "kind::f8f6f4", "f32", - "e4m3", "e5m2", + "e2m3", "f32" ], "operands": [ @@ -213399,29 +216478,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e5m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e2m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e2m1.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e3m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e2m1_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e3m2_f32" }, "selections": [ { - "source_record": "anonymous_19817", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19801", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0247", + "abi_id": "i0249", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -213433,10 +216512,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32" ] }, "dialect": { @@ -213466,7 +216545,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e2m1.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e3m2.f32", "arguments": [ "i32", "i32", @@ -213697,7 +216776,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e5m2", - "b_element": "e2m1", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -213722,7 +216801,7 @@ "kind::f8f6f4", "f32", "e5m2", - "e2m1", + "e3m2", "f32" ], "operands": [ @@ -213750,29 +216829,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e2m1 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e3m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e2m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e4m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e2m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e4m3_f32" }, "selections": [ { - "source_record": "anonymous_19809", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19785", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0248", + "abi_id": "i0250", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -213784,10 +216863,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32" ] }, "dialect": { @@ -213817,7 +216896,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e2m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e4m3.f32", "arguments": [ "i32", "i32", @@ -214048,7 +217127,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e5m2", - "b_element": "e2m3", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -214073,7 +217152,7 @@ "kind::f8f6f4", "f32", "e5m2", - "e2m3", + "e4m3", "f32" ], "operands": [ @@ -214101,29 +217180,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e2m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e4m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e3m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e5m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e3m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e5m2_f32" }, "selections": [ { - "source_record": "anonymous_19801", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19793", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0249", + "abi_id": "i0251", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -214135,10 +217214,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32" ] }, "dialect": { @@ -214168,7 +217247,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e3m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e5m2.f32", "arguments": [ "i32", "i32", @@ -214399,7 +217478,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e5m2", - "b_element": "e3m2", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -214424,7 +217503,7 @@ "kind::f8f6f4", "f32", "e5m2", - "e3m2", + "e5m2", "f32" ], "operands": [ @@ -214452,58 +217531,55 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e3m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e5m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e4m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.s4.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e4m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s4" }, "selections": [ { - "source_record": "anonymous_19785", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19600", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ - "Subtarget->hasMMABlockScale()" + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" ] } ], "rust": { - "abi_id": "i0250", + "abi_id": "i0195", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4", "arguments": [ - "[f32; 4]", - "[u32; 4]", - "[u32; 4]", + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", "u32", "u32" ], - "result": "[f32; 4]", + "result": "[i32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "f32", - "f32", - "f32", - "f32", - "u32", - "u32", - "u32", - "u32", + "i32", + "i32", + "i32", + "i32", "u32", "u32", "u32", @@ -214512,14 +217588,14 @@ "u32" ], "results": [ - "f32", - "f32", - "f32", - "f32" + "i32", + "i32", + "i32", + "i32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e4m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s4", "arguments": [ "i32", "i32", @@ -214529,24 +217605,20 @@ "i32", "i32", "i32", - "f32", - "f32", - "f32", - "f32", "i32", "i32" ], "results": [ - "f32", - "f32", - "f32", - "f32" + "i32", + "i32", + "i32", + "i32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -214560,30 +217632,18 @@ "execution_scope": "warp" }, "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] }, - "ptx_result": "[f32; 4]", - "targets": "sm_120a|sm_120f|sm_121a|sm_121f", + "ptx_result": "[i32; 4]", + "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" @@ -214594,8 +217654,8 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "status": "validated", "target_triple": "nvptx64-nvidia-cuda", - "gpu_target": "sm_120a", - "ptx_feature": "+ptx87" + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" }, "backend_lowerings": [ { @@ -214603,25 +217663,13 @@ "mechanism": "inline_ptx", "evidence_profile": "rust-llvm-23.1.0-16696adc", "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] } @@ -214634,14 +217682,14 @@ "stages": [ { "targets": [ - "sm_120a", - "ptx87" + "sm_80", + "ptx85" ], - "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM lowered the 28,839-byte all-forms source (SHA-256 5518d5dfb092f5ae3ccefe1e7e66eb4df9db7da480722e390587490c6ce8832a) to 12,015-byte PTX (SHA-256 0d93ea01d39bc512b96becf2ad799522d9d5187c17d521294eecd4e69c055e66) containing the exact 25-form matrix at sm_120a and PTX 8.7.", + "detail": "The 8,107-byte combined inline-PTX probe (SHA-256 ce31bb4c5d7f083ae8e1293a0a3e5196575482427a041d549f9ecd3862e46942) used public C, A, B, metadata, selector order and covered all eight variants with both selector values. Pinned LLVM emitted 8,453-byte PTX (SHA-256 7a8bb0261fd16c1941b47500d70f3cff95a1acb95c51e52480af15a4effc8818) with exactly 16 ordered m16n8k64 INT4 instructions. An auxiliary 6,948-byte typed LLVM comparison (SHA-256 379488c94c4e3d6b1806928d72723845b7bd329857f4dfc3caf8f74d7a5c6649) used source A, B, C, metadata, selector order and emitted 22,330-byte PTX (SHA-256 913b74cc0dba68779655073b83e5a534bcf076fa5e6a1d1d6029ef951b0fc1cd) with the same 16 forms; this record retained wrapping s4-by-s4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -214649,14 +217697,14 @@ }, { "targets": [ - "sm_120a", - "ptx87" + "sm_80", + "ptx85" ], - "representation": "exact-floor ordered kind::f8f6f4 F32 PTX", + "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms. PTX 8.6, sm_120, selector 1, and dynamic selectors were rejected.", + "detail": "CUDA 13.3 ptxas accepted all 16 instructions and produced a 4,008-byte cubin with SHA-256 a6df23e0492e6f26ede3da7f7fab6c9fdab2693c5c2d6bda12339948cba640ec containing exactly 16 IMMA.SP.16864 instructions. LLVM and ptxas rejected selector 2 and dynamic selectors; ptxas also rejected PTX 8.4 and sm_75.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -214669,25 +217717,13 @@ "mechanism": "inline_ptx", "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] } @@ -214700,14 +217736,14 @@ "stages": [ { "targets": [ - "compute_120a", + "compute_80", "ptx93" ], - "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 11,910-byte PTX (SHA-256 a096494f6b066927107cf222f784d1a586ed1cf3ab766669b741e429f03f4427) and produced 14,052-byte LTOIR (SHA-256 99941daa24a78884788ed0908a3764f596c527e6ab621d6085c549aea9575377).", + "detail": "The production generated_intrinsics route produced 294,949-byte compute_80 NVVM IR with SHA-256 787025e167bb7bb790fab0af002f838502536834145304ce8df3fc75227059d2 and 82,648-byte LTOIR with SHA-256 eb6516ac258f3c70d20879de097822b13ab73e00288691ae9a13e17bc7fe0d1a. All eight raw variants use selectors 0 and 1. An auxiliary 8,107-byte combined probe with SHA-256 ce31bb4c5d7f083ae8e1293a0a3e5196575482427a041d549f9ecd3862e46942 separately covered every variant with both selectors.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -214715,29 +217751,14 @@ }, { "targets": [ - "sm_120a", - "ptx93" - ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 F32 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3) retaining all 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, - { - "targets": [ - "sm_120a", + "sm_80", "ptx93" ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 F32 matrix", + "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 12,144-byte cubin (SHA-256 62457debbb99023b09b3701e14974a97cfc5761f931ebf9f0d9e2bada3e3a642); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms.", + "detail": "nvJitLink produced a 26,600-byte cubin with SHA-256 1837a2742ce837ccf16b4900b50a72fb018a49bd1850bafe62b3a2a31f550406. Disassembly contained 50 IMMA.SP instructions in total, exactly 30 IMMA.SP.16864 instructions, and exactly 10 ordered m16n8k64 INT4 forms: all eight raw variants plus two compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -214748,17 +217769,17 @@ ], "sparse_mma": { "shape": "m16n8k64", - "accumulator": "f32", - "a_element": "e5m2", - "b_element": "e4m3", + "accumulator": "s32", + "a_element": "s4", + "b_element": "s4", "a_layout": "row", "b_layout": "col", - "overflow": "not_applicable", + "overflow": "wrapping", "metadata": "ordered", - "selector": "immediate_zero", + "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", - "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -214772,11 +217793,10 @@ "m16n8k64", "row", "col", - "kind::f8f6f4", - "f32", - "e5m2", - "e4m3", - "f32" + "s32", + "s4", + "s4", + "s32" ], "operands": [ { @@ -214785,11 +217805,11 @@ }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", @@ -214803,58 +217823,55 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e4m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and signed B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e5m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.s4.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e5m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s4" }, "selections": [ { - "source_record": "anonymous_19793", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19681", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ - "Subtarget->hasMMABlockScale()" + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" ] } ], "rust": { - "abi_id": "i0251", + "abi_id": "i0199", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", "arguments": [ - "[f32; 4]", - "[u32; 4]", - "[u32; 4]", + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", "u32", "u32" ], - "result": "[f32; 4]", + "result": "[i32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "f32", - "f32", - "f32", - "f32", - "u32", - "u32", - "u32", - "u32", + "i32", + "i32", + "i32", + "i32", "u32", "u32", "u32", @@ -214863,14 +217880,14 @@ "u32" ], "results": [ - "f32", - "f32", - "f32", - "f32" + "i32", + "i32", + "i32", + "i32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e5m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s4", "arguments": [ "i32", "i32", @@ -214880,24 +217897,20 @@ "i32", "i32", "i32", - "f32", - "f32", - "f32", - "f32", "i32", "i32" ], "results": [ - "f32", - "f32", - "f32", - "f32" + "i32", + "i32", + "i32", + "i32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -214911,30 +217924,18 @@ "execution_scope": "warp" }, "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] }, - "ptx_result": "[f32; 4]", - "targets": "sm_120a|sm_120f|sm_121a|sm_121f", + "ptx_result": "[i32; 4]", + "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" @@ -214945,8 +217946,8 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "status": "validated", "target_triple": "nvptx64-nvidia-cuda", - "gpu_target": "sm_120a", - "ptx_feature": "+ptx87" + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" }, "backend_lowerings": [ { @@ -214954,25 +217955,13 @@ "mechanism": "inline_ptx", "evidence_profile": "rust-llvm-23.1.0-16696adc", "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] } @@ -214985,14 +217974,14 @@ "stages": [ { "targets": [ - "sm_120a", - "ptx87" + "sm_80", + "ptx85" ], - "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM lowered the 28,839-byte all-forms source (SHA-256 5518d5dfb092f5ae3ccefe1e7e66eb4df9db7da480722e390587490c6ce8832a) to 12,015-byte PTX (SHA-256 0d93ea01d39bc512b96becf2ad799522d9d5187c17d521294eecd4e69c055e66) containing the exact 25-form matrix at sm_120a and PTX 8.7.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating s4-by-s4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215000,14 +217989,14 @@ }, { "targets": [ - "sm_120a", - "ptx87" + "sm_80", + "ptx85" ], - "representation": "exact-floor ordered kind::f8f6f4 F32 PTX", + "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms. PTX 8.6, sm_120, selector 1, and dynamic selectors were rejected.", + "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -215020,25 +218009,13 @@ "mechanism": "inline_ptx", "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] } @@ -215051,14 +218028,14 @@ "stages": [ { "targets": [ - "compute_120a", + "compute_80", "ptx93" ], - "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 11,910-byte PTX (SHA-256 a096494f6b066927107cf222f784d1a586ed1cf3ab766669b741e429f03f4427) and produced 14,052-byte LTOIR (SHA-256 99941daa24a78884788ed0908a3764f596c527e6ab621d6085c549aea9575377).", + "detail": "The production artifacts described by the first record retained saturating s4-by-s4 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215066,29 +218043,14 @@ }, { "targets": [ - "sm_120a", - "ptx93" - ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 F32 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3) retaining all 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, - { - "targets": [ - "sm_120a", + "sm_80", "ptx93" ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 F32 matrix", + "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 12,144-byte cubin (SHA-256 62457debbb99023b09b3701e14974a97cfc5761f931ebf9f0d9e2bada3e3a642); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms.", + "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -215099,17 +218061,17 @@ ], "sparse_mma": { "shape": "m16n8k64", - "accumulator": "f32", - "a_element": "e5m2", - "b_element": "e5m2", + "accumulator": "s32", + "a_element": "s4", + "b_element": "s4", "a_layout": "row", "b_layout": "col", - "overflow": "not_applicable", + "overflow": "satfinite", "metadata": "ordered", - "selector": "immediate_zero", + "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", - "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -215123,11 +218085,11 @@ "m16n8k64", "row", "col", - "kind::f8f6f4", - "f32", - "e5m2", - "e5m2", - "f32" + "satfinite", + "s32", + "s4", + "s4", + "s32" ], "operands": [ { @@ -215136,11 +218098,11 @@ }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", @@ -215154,20 +218116,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e5m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and signed B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.s4.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.u4.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s4_u4" }, "selections": [ { - "source_record": "anonymous_19600", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19605", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -215175,9 +218137,9 @@ } ], "rust": { - "abi_id": "i0195", + "abi_id": "i0196", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -215189,10 +218151,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4" ] }, "dialect": { @@ -215218,7 +218180,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s4.u4", "arguments": [ "i32", "i32", @@ -215312,7 +218274,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 8,107-byte combined inline-PTX probe (SHA-256 ce31bb4c5d7f083ae8e1293a0a3e5196575482427a041d549f9ecd3862e46942) used public C, A, B, metadata, selector order and covered all eight variants with both selector values. Pinned LLVM emitted 8,453-byte PTX (SHA-256 7a8bb0261fd16c1941b47500d70f3cff95a1acb95c51e52480af15a4effc8818) with exactly 16 ordered m16n8k64 INT4 instructions. An auxiliary 6,948-byte typed LLVM comparison (SHA-256 379488c94c4e3d6b1806928d72723845b7bd329857f4dfc3caf8f74d7a5c6649) used source A, B, C, metadata, selector order and emitted 22,330-byte PTX (SHA-256 913b74cc0dba68779655073b83e5a534bcf076fa5e6a1d1d6029ef951b0fc1cd) with the same 16 forms; this record retained wrapping s4-by-s4 PTX.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping s4-by-u4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215327,7 +218289,7 @@ "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted all 16 instructions and produced a 4,008-byte cubin with SHA-256 a6df23e0492e6f26ede3da7f7fab6c9fdab2693c5c2d6bda12339948cba640ec containing exactly 16 IMMA.SP.16864 instructions. LLVM and ptxas rejected selector 2 and dynamic selectors; ptxas also rejected PTX 8.4 and sm_75.", + "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -215366,7 +218328,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 294,949-byte compute_80 NVVM IR with SHA-256 787025e167bb7bb790fab0af002f838502536834145304ce8df3fc75227059d2 and 82,648-byte LTOIR with SHA-256 eb6516ac258f3c70d20879de097822b13ab73e00288691ae9a13e17bc7fe0d1a. All eight raw variants use selectors 0 and 1. An auxiliary 8,107-byte combined probe with SHA-256 ce31bb4c5d7f083ae8e1293a0a3e5196575482427a041d549f9ecd3862e46942 separately covered every variant with both selectors.", + "detail": "The production artifacts described by the first record retained wrapping s4-by-u4 PTX with selector 1.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215381,7 +218343,7 @@ "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 26,600-byte cubin with SHA-256 1837a2742ce837ccf16b4900b50a72fb018a49bd1850bafe62b3a2a31f550406. Disassembly contained 50 IMMA.SP instructions in total, exactly 30 IMMA.SP.16864 instructions, and exactly 10 ordered m16n8k64 INT4 forms: all eight raw variants plus two compatibility-path calls.", + "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -215394,7 +218356,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "s4", - "b_element": "s4", + "b_element": "u4", "a_layout": "row", "b_layout": "col", "overflow": "wrapping", @@ -215418,7 +218380,7 @@ "col", "s32", "s4", - "s4", + "u4", "s32" ], "operands": [ @@ -215446,20 +218408,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.s4.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.u4.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s4_u4" }, "selections": [ { - "source_record": "anonymous_19681", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19684", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -215467,9 +218429,9 @@ } ], "rust": { - "abi_id": "i0199", + "abi_id": "i0200", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -215481,10 +218443,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite" ] }, "dialect": { @@ -215510,7 +218472,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s4.u4", "arguments": [ "i32", "i32", @@ -215604,7 +218566,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating s4-by-s4 PTX.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating s4-by-u4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215658,7 +218620,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained saturating s4-by-s4 PTX with selector 0.", + "detail": "The production artifacts described by the first record retained saturating s4-by-u4 PTX with selector 1.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215686,7 +218648,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "s4", - "b_element": "s4", + "b_element": "u4", "a_layout": "row", "b_layout": "col", "overflow": "satfinite", @@ -215711,7 +218673,7 @@ "satfinite", "s32", "s4", - "s4", + "u4", "s32" ], "operands": [ @@ -215739,20 +218701,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.u4.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.s8.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s4_u4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s8" }, "selections": [ { - "source_record": "anonymous_19605", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19664", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -215760,13 +218722,13 @@ } ], "rust": { - "abi_id": "i0196", + "abi_id": "i0179", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8", "arguments": [ "[i32; 4]", - "[u32; 2]", - "[u32; 2]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], @@ -215774,10 +218736,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8" ] }, "dialect": { @@ -215793,294 +218755,6 @@ "u32", "u32", "u32", - "u32" - ], - "results": [ - "i32", - "i32", - "i32", - "i32" - ] - }, - "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s4.u4", - "arguments": [ - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32" - ], - "results": [ - "i32", - "i32", - "i32", - "i32" - ], - "properties": [ - "ImmArg", - "IntrNoCallback", - "IntrNoMem", - "Range" - ], - "result_facts": { - "no_undef": false, - "range": null - } - }, - "semantics": { - "pure": false, - "memory": "none", - "convergent": true, - "execution_scope": "warp" - }, - "target": { - "minimum_ptx": "8.5", - "hardware": { - "kind": "any_of", - "alternatives": [ - { - "kind": "minimum_sm", - "sm": 80 - } - ] - }, - "ptx_result": "[i32; 4]", - "targets": "all", - "ptx_isa_version": "9.3", - "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", - "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" - }, - "backend": { - "profile": "rust-llvm-23.1.0-16696adc", - "version": "LLVM version 23.1.0-rust-1.100.0-nightly", - "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", - "target_triple": "nvptx64-nvidia-cuda", - "gpu_target": "sm_80", - "ptx_feature": "+ptx85" - }, - "backend_lowerings": [ - { - "backend": "llvm_nvptx", - "mechanism": "inline_ptx", - "evidence_profile": "rust-llvm-23.1.0-16696adc", - "target": { - "minimum_ptx": "8.5", - "hardware": { - "kind": "any_of", - "alternatives": [ - { - "kind": "minimum_sm", - "sm": 80 - } - ] - } - }, - "version": "LLVM version 23.1.0-rust-1.100.0-nightly", - "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "artifact_path": null, - "build_id_prefix": null, - "status": "validated", - "stages": [ - { - "targets": [ - "sm_80", - "ptx85" - ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", - "stage": "backend_codegen", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping s4-by-u4 PTX.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_80", - "ptx85" - ], - "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - } - ] - }, - { - "backend": "lib_nvvm", - "mechanism": "inline_ptx", - "evidence_profile": "cuda-13.3-libnvvm-13.3.33", - "target": { - "minimum_ptx": "8.5", - "hardware": { - "kind": "any_of", - "alternatives": [ - { - "kind": "minimum_sm", - "sm": 80 - } - ] - } - }, - "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", - "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", - "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", - "build_id_prefix": "2330c0", - "status": "validated", - "stages": [ - { - "targets": [ - "compute_80", - "ptx93" - ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", - "stage": "backend_codegen", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained wrapping s4-by-u4 PTX with selector 1.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_80", - "ptx93" - ], - "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", - "stage": "device_link", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" - } - ] - } - ], - "sparse_mma": { - "shape": "m16n8k64", - "accumulator": "s32", - "a_element": "s4", - "b_element": "u4", - "a_layout": "row", - "b_layout": "col", - "overflow": "wrapping", - "metadata": "ordered", - "selector": "immediate_zero_or_one", - "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", - "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" - }, - "lowering": "generated_sparse_mma", - "expected_ptx": { - "mnemonic": "mma", - "modifiers": [ - "sp::ordered_metadata", - "sync", - "aligned", - "m16n8k64", - "row", - "col", - "s32", - "s4", - "u4", - "s32" - ], - "operands": [ - { - "kind": "register_list", - "length": 4 - }, - { - "kind": "register_list", - "length": 2 - }, - { - "kind": "register_list", - "length": 2 - }, - { - "kind": "register_list", - "length": 4 - }, - { - "kind": "register" - }, - { - "kind": "immediate" - } - ] - }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." - }, - { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.u4.s32.satfinite.ordered_metadata", - "family": "sparse_mma", - "source": { - "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s4_u4" - }, - "selections": [ - { - "source_record": "anonymous_19684", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", - "predicates": [ - "Subtarget->getSmVersion() >= 80", - "Subtarget->getPTXVersion() >= 85" - ] - } - ], - "rust": { - "abi_id": "i0200", - "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", - "arguments": [ - "[i32; 4]", - "[u32; 2]", - "[u32; 2]", - "u32", - "u32" - ], - "result": "[i32; 4]", - "safe": false, - "must_use": true, - "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", - "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite" - ] - }, - "dialect": { - "op_type": "SparseMmaOp", - "op_name": "nvvm.sparse_mma", - "operands": [ - "i32", - "i32", - "i32", - "i32", - "u32", "u32", "u32", "u32", @@ -216095,7 +218769,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s4.u4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s8", "arguments": [ "i32", "i32", @@ -216106,6 +218780,10 @@ "i32", "i32", "i32", + "i32", + "i32", + "i32", + "i32", "i32" ], "results": [ @@ -216115,10 +218793,10 @@ "i32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -216185,11 +218863,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", + "representation": "convergent ordered sparse m16n8k64 signed INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating s4-by-u4 PTX.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping s8-by-s8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -216200,12 +218878,12 @@ "sm_80", "ptx85" ], - "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", + "representation": "exact-floor ordered sparse m16n8k64 INT8 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", - "artifact_kind": "cubin", + "detail": "CUDA 13.3 ptxas accepted all eight exact instructions and produced a 1,464-byte cubin with SHA-256 6bcec1b1eab13da703fdade053704aa6ab00591a1b38dd7daf48ac0dec541df2. Because every probe function was unreferenced, ptxas removed their bodies; this proves assembly acceptance, not retained SASS.", + "artifact_kind": null, "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" @@ -216239,11 +218917,11 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", + "representation": "convergent ordered sparse m16n8k64 signed INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained saturating s4-by-u4 PTX with selector 1.", + "detail": "The production generated_intrinsics route produced 242,464-byte compute_80 NVVM IR with SHA-256 fcc2fe1a6200de7b5ab8a38cab847432669fe4d6ce823c81b73f9b18fa25144c and 68,600-byte LTOIR with SHA-256 aa011070e20cb91d99f0d6d41ffd3883f01031b44d171380f638e3674b2facf3. All eight raw variants use compile-time selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -216254,11 +218932,11 @@ "sm_80", "ptx93" ], - "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", + "representation": "combined sparse INT8 coverage kernel with ordered m16n8k64 calls", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", + "detail": "nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -216270,16 +218948,16 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "s32", - "a_element": "s4", - "b_element": "u4", + "a_element": "s8", + "b_element": "s8", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "wrapping", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -216293,10 +218971,9 @@ "m16n8k64", "row", "col", - "satfinite", "s32", - "s4", - "u4", + "s8", + "s8", "s32" ], "operands": [ @@ -216306,11 +218983,11 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -216324,20 +219001,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.s8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.s8.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s8" }, "selections": [ { - "source_record": "anonymous_19664", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19717", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -216345,9 +219022,9 @@ } ], "rust": { - "abi_id": "i0179", + "abi_id": "i0183", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -216359,10 +219036,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite" ] }, "dialect": { @@ -216392,7 +219069,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s8", "arguments": [ "i32", "i32", @@ -216486,11 +219163,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 signed INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 signed saturating INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping s8-by-s8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating s8-by-s8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -216540,7 +219217,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 signed INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 signed saturating INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -216575,7 +219252,7 @@ "b_element": "s8", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "satfinite", "metadata": "ordered", "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", @@ -216594,6 +219271,7 @@ "m16n8k64", "row", "col", + "satfinite", "s32", "s8", "s8", @@ -216624,20 +219302,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.s8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.u8.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s8_u8" }, "selections": [ { - "source_record": "anonymous_19717", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19669", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -216645,9 +219323,9 @@ } ], "rust": { - "abi_id": "i0183", + "abi_id": "i0180", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -216659,10 +219337,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8" ] }, "dialect": { @@ -216692,7 +219370,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s8.u8", "arguments": [ "i32", "i32", @@ -216786,11 +219464,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 signed saturating INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating s8-by-s8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping s8-by-u8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -216840,7 +219518,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 signed saturating INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -216872,10 +219550,10 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "s8", - "b_element": "s8", + "b_element": "u8", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "wrapping", "metadata": "ordered", "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", @@ -216894,10 +219572,9 @@ "m16n8k64", "row", "col", - "satfinite", "s32", "s8", - "s8", + "u8", "s32" ], "operands": [ @@ -216925,20 +219602,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.u8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.u8.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s8_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s8_u8" }, "selections": [ { - "source_record": "anonymous_19669", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19720", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -216946,9 +219623,9 @@ } ], "rust": { - "abi_id": "i0180", + "abi_id": "i0184", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -216960,10 +219637,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite" ] }, "dialect": { @@ -216993,7 +219670,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s8.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s8.u8", "arguments": [ "i32", "i32", @@ -217087,11 +219764,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping s8-by-u8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating s8-by-u8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -217141,7 +219818,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -217176,7 +219853,7 @@ "b_element": "u8", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "satfinite", "metadata": "ordered", "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", @@ -217195,6 +219872,7 @@ "m16n8k64", "row", "col", + "satfinite", "s32", "s8", "u8", @@ -217225,20 +219903,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.u8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.u4.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s8_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u4" }, "selections": [ { - "source_record": "anonymous_19720", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19614", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -217246,13 +219924,13 @@ } ], "rust": { - "abi_id": "i0184", + "abi_id": "i0197", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4", "arguments": [ "[i32; 4]", - "[u32; 4]", - "[u32; 4]", + "[u32; 2]", + "[u32; 2]", "u32", "u32" ], @@ -217260,10 +219938,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4" ] }, "dialect": { @@ -217279,10 +219957,6 @@ "u32", "u32", "u32", - "u32", - "u32", - "u32", - "u32", "u32" ], "results": [ @@ -217293,7 +219967,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s8.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u4", "arguments": [ "i32", "i32", @@ -217304,10 +219978,6 @@ "i32", "i32", "i32", - "i32", - "i32", - "i32", - "i32", "i32" ], "results": [ @@ -217317,10 +219987,10 @@ "i32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -217387,11 +220057,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating s8-by-u8 PTX with selector 0.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping u4-by-u4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -217402,12 +220072,12 @@ "sm_80", "ptx85" ], - "representation": "exact-floor ordered sparse m16n8k64 INT8 PTX", + "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted all eight exact instructions and produced a 1,464-byte cubin with SHA-256 6bcec1b1eab13da703fdade053704aa6ab00591a1b38dd7daf48ac0dec541df2. Because every probe function was unreferenced, ptxas removed their bodies; this proves assembly acceptance, not retained SASS.", - "artifact_kind": null, + "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", + "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" @@ -217441,11 +220111,11 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 242,464-byte compute_80 NVVM IR with SHA-256 fcc2fe1a6200de7b5ab8a38cab847432669fe4d6ce823c81b73f9b18fa25144c and 68,600-byte LTOIR with SHA-256 aa011070e20cb91d99f0d6d41ffd3883f01031b44d171380f638e3674b2facf3. All eight raw variants use compile-time selector 0.", + "detail": "The production artifacts described by the first record retained wrapping u4-by-u4 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -217456,11 +220126,11 @@ "sm_80", "ptx93" ], - "representation": "combined sparse INT8 coverage kernel with ordered m16n8k64 calls", + "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls.", + "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -217472,16 +220142,16 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "s32", - "a_element": "s8", - "b_element": "u8", + "a_element": "u4", + "b_element": "u4", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "wrapping", "metadata": "ordered", - "selector": "immediate_zero", + "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -217495,10 +220165,9 @@ "m16n8k64", "row", "col", - "satfinite", "s32", - "s8", - "u8", + "u4", + "u4", "s32" ], "operands": [ @@ -217508,11 +220177,11 @@ }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", @@ -217526,20 +220195,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.u4.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.s4.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u4_s4" }, "selections": [ { - "source_record": "anonymous_19614", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19610", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -217547,9 +220216,9 @@ } ], "rust": { - "abi_id": "i0197", + "abi_id": "i0198", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -217561,10 +220230,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4" ] }, "dialect": { @@ -217590,7 +220259,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u4.s4", "arguments": [ "i32", "i32", @@ -217684,7 +220353,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping u4-by-u4 PTX.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping u4-by-s4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -217738,7 +220407,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained wrapping u4-by-u4 PTX with selector 0.", + "detail": "The production artifacts described by the first record retained wrapping u4-by-s4 PTX with selector 1.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -217766,7 +220435,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "u4", - "b_element": "u4", + "b_element": "s4", "a_layout": "row", "b_layout": "col", "overflow": "wrapping", @@ -217790,7 +220459,7 @@ "col", "s32", "u4", - "u4", + "s4", "s32" ], "operands": [ @@ -217818,20 +220487,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.s4.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.s4.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u4_s4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u4_s4" }, "selections": [ { - "source_record": "anonymous_19610", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19687", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -217839,9 +220508,9 @@ } ], "rust": { - "abi_id": "i0198", + "abi_id": "i0202", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -217853,10 +220522,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite" ] }, "dialect": { @@ -217882,7 +220551,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u4.s4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u4.s4", "arguments": [ "i32", "i32", @@ -217976,7 +220645,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping u4-by-s4 PTX.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating u4-by-s4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218030,7 +220699,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained wrapping u4-by-s4 PTX with selector 1.", + "detail": "The production artifacts described by the first record retained saturating u4-by-s4 PTX with selector 1.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218061,7 +220730,7 @@ "b_element": "s4", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "satfinite", "metadata": "ordered", "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", @@ -218080,6 +220749,7 @@ "m16n8k64", "row", "col", + "satfinite", "s32", "u4", "s4", @@ -218110,20 +220780,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.s4.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.u4.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u4_s4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u4" }, "selections": [ { - "source_record": "anonymous_19687", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19690", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -218131,9 +220801,9 @@ } ], "rust": { - "abi_id": "i0202", + "abi_id": "i0201", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -218145,10 +220815,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite" ] }, "dialect": { @@ -218174,7 +220844,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u4.s4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u4", "arguments": [ "i32", "i32", @@ -218268,7 +220938,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating u4-by-s4 PTX.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating u4-by-u4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218322,7 +220992,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained saturating u4-by-s4 PTX with selector 1.", + "detail": "The production artifacts described by the first record retained saturating u4-by-u4 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218350,7 +221020,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "u4", - "b_element": "s4", + "b_element": "u4", "a_layout": "row", "b_layout": "col", "overflow": "satfinite", @@ -218375,7 +221045,7 @@ "satfinite", "s32", "u4", - "s4", + "u4", "s32" ], "operands": [ @@ -218403,20 +221073,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.u4.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.u8.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8" }, "selections": [ { - "source_record": "anonymous_19690", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19678", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -218424,13 +221094,13 @@ } ], "rust": { - "abi_id": "i0201", + "abi_id": "i0181", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8", "arguments": [ "[i32; 4]", - "[u32; 2]", - "[u32; 2]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], @@ -218438,10 +221108,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8" ] }, "dialect": { @@ -218457,6 +221127,10 @@ "u32", "u32", "u32", + "u32", + "u32", + "u32", + "u32", "u32" ], "results": [ @@ -218467,7 +221141,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8", "arguments": [ "i32", "i32", @@ -218478,6 +221152,10 @@ "i32", "i32", "i32", + "i32", + "i32", + "i32", + "i32", "i32" ], "results": [ @@ -218487,10 +221165,10 @@ "i32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -218557,11 +221235,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", + "representation": "convergent ordered sparse m16n8k64 unsigned INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating u4-by-u4 PTX.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping u8-by-u8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218572,12 +221250,12 @@ "sm_80", "ptx85" ], - "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", + "representation": "exact-floor ordered sparse m16n8k64 INT8 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", - "artifact_kind": "cubin", + "detail": "CUDA 13.3 ptxas accepted all eight exact instructions and produced a 1,464-byte cubin with SHA-256 6bcec1b1eab13da703fdade053704aa6ab00591a1b38dd7daf48ac0dec541df2. Because every probe function was unreferenced, ptxas removed their bodies; this proves assembly acceptance, not retained SASS.", + "artifact_kind": null, "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" @@ -218611,11 +221289,11 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", + "representation": "convergent ordered sparse m16n8k64 unsigned INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained saturating u4-by-u4 PTX with selector 0.", + "detail": "The production generated_intrinsics route produced 242,464-byte compute_80 NVVM IR with SHA-256 fcc2fe1a6200de7b5ab8a38cab847432669fe4d6ce823c81b73f9b18fa25144c and 68,600-byte LTOIR with SHA-256 aa011070e20cb91d99f0d6d41ffd3883f01031b44d171380f638e3674b2facf3. All eight raw variants use compile-time selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218626,11 +221304,11 @@ "sm_80", "ptx93" ], - "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", + "representation": "combined sparse INT8 coverage kernel with ordered m16n8k64 calls", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", + "detail": "nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -218642,16 +221320,16 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "s32", - "a_element": "u4", - "b_element": "u4", + "a_element": "u8", + "b_element": "u8", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "wrapping", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -218665,10 +221343,9 @@ "m16n8k64", "row", "col", - "satfinite", "s32", - "u4", - "u4", + "u8", + "u8", "s32" ], "operands": [ @@ -218678,11 +221355,11 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -218696,20 +221373,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.u8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.s8.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8_s8" }, "selections": [ { - "source_record": "anonymous_19678", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19674", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -218717,9 +221394,9 @@ } ], "rust": { - "abi_id": "i0181", + "abi_id": "i0182", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -218731,10 +221408,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8" ] }, "dialect": { @@ -218764,7 +221441,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8.s8", "arguments": [ "i32", "i32", @@ -218858,11 +221535,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 unsigned INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping u8-by-u8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping u8-by-s8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218912,7 +221589,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 unsigned INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -218944,7 +221621,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "u8", - "b_element": "u8", + "b_element": "s8", "a_layout": "row", "b_layout": "col", "overflow": "wrapping", @@ -218968,7 +221645,7 @@ "col", "s32", "u8", - "u8", + "s8", "s32" ], "operands": [ @@ -218996,20 +221673,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.s8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.s8.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8_s8" }, "selections": [ { - "source_record": "anonymous_19674", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19723", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -219017,9 +221694,9 @@ } ], "rust": { - "abi_id": "i0182", + "abi_id": "i0186", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -219031,10 +221708,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" ] }, "dialect": { @@ -219064,7 +221741,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8.s8", "arguments": [ "i32", "i32", @@ -219158,11 +221835,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping u8-by-s8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating u8-by-s8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -219212,7 +221889,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -219247,7 +221924,7 @@ "b_element": "s8", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "satfinite", "metadata": "ordered", "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", @@ -219266,6 +221943,7 @@ "m16n8k64", "row", "col", + "satfinite", "s32", "u8", "s8", @@ -219296,20 +221974,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.s8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.u8.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8" }, "selections": [ { - "source_record": "anonymous_19723", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19726", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -219317,9 +221995,9 @@ } ], "rust": { - "abi_id": "i0186", + "abi_id": "i0185", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -219331,10 +222009,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" ] }, "dialect": { @@ -219364,7 +222042,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8", "arguments": [ "i32", "i32", @@ -219458,11 +222136,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 unsigned saturating INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating u8-by-s8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating u8-by-u8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -219512,7 +222190,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 unsigned saturating INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -219544,7 +222222,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "u8", - "b_element": "s8", + "b_element": "u8", "a_layout": "row", "b_layout": "col", "overflow": "satfinite", @@ -219569,7 +222247,7 @@ "satfinite", "s32", "u8", - "s8", + "u8", "s32" ], "operands": [ @@ -219597,20 +222275,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.u8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k8_f32_tf32", + "operation_key": "matrix.mma.sp.m16n8k8.row.col.f32.tf32.tf32.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32" }, "selections": [ { - "source_record": "anonymous_19726", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19540", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -219618,38 +222296,34 @@ } ], "rust": { - "abi_id": "i0185", + "abi_id": "i1017", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k8_f32_tf32", "arguments": [ - "[i32; 4]", - "[u32; 4]", - "[u32; 4]", + "[f32; 4]", + "[u32; 2]", + "[u32; 2]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", - "u32", - "u32", - "u32", - "u32", + "f32", + "f32", + "f32", + "f32", "u32", "u32", "u32", @@ -219658,41 +222332,37 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32", "arguments": [ "i32", "i32", "i32", "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -219716,7 +222386,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -219726,7 +222396,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -219752,18 +222422,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 unsigned saturating INT8 inline PTX with selector 0", + "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating u8-by-u8 PTX with selector 0.", + "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -219774,22 +222444,37 @@ "sm_80", "ptx85" ], - "representation": "exact-floor ordered sparse m16n8k64 INT8 PTX", + "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted all eight exact instructions and produced a 1,464-byte cubin with SHA-256 6bcec1b1eab13da703fdade053704aa6ab00591a1b38dd7daf48ac0dec541df2. Because every probe function was unreferenced, ptxas removed their bodies; this proves assembly acceptance, not retained SASS.", + "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", "target": { "minimum_ptx": "8.5", "hardware": { @@ -219802,22 +222487,22 @@ ] } }, - "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", - "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", - "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", - "build_id_prefix": "2330c0", - "status": "validated", + "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", + "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", + "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", + "build_id_prefix": null, + "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx93" + "ptx88" ], - "representation": "convergent ordered sparse m16n8k64 unsigned saturating INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 242,464-byte compute_80 NVVM IR with SHA-256 fcc2fe1a6200de7b5ab8a38cab847432669fe4d6ce823c81b73f9b18fa25144c and 68,600-byte LTOIR with SHA-256 aa011070e20cb91d99f0d6d41ffd3883f01031b44d171380f638e3674b2facf3. All eight raw variants use compile-time selector 0.", + "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -219826,36 +222511,66 @@ { "targets": [ "sm_80", - "ptx93" + "ptx88" ], - "representation": "combined sparse INT8 coverage kernel with ordered m16n8k64 calls", + "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "artifact_kind": "cubin", + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", + "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", + "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + }, + { + "targets": [ + "sm_80", + "ptx88" + ], + "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls.", + "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", + "tool_version": "CUDA 12.9 nvJitLink V12.9.86", + "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + }, + { + "targets": [ + "sm_120", + "ptx88" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { - "shape": "m16n8k64", - "accumulator": "s32", - "a_element": "u8", - "b_element": "u8", + "shape": "m16n8k8", + "accumulator": "f32", + "a_element": "tf32", + "b_element": "tf32", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "not_applicable", "metadata": "ordered", - "selector": "immediate_zero", + "selector": "immediate_zero_through_three", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a2_i32_b2_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -219864,14 +222579,13 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k64", + "m16n8k8", "row", "col", - "satfinite", - "s32", - "u8", - "u8", - "s32" + "f32", + "tf32", + "tf32", + "f32" ], "operands": [ { @@ -219880,11 +222594,11 @@ }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", @@ -219898,7 +222612,7 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator." }, { "id": "movmatrix_trans_b16", diff --git a/intrinsics/generated-reference.md b/intrinsics/generated-reference.md index 6b2bfc3153..f6c5e0830e 100644 --- a/intrinsics/generated-reference.md +++ b/intrinsics/generated-reference.md @@ -2,7 +2,7 @@ SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0 @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. --> @@ -589,6 +589,13 @@ This table is generated from the resolved catalog. Evidence stages below disting | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.u4.s4` from `int_nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_u4_s4` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.satfinite.u4.s4` from `int_nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_satfinite_u4_s4` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.satfinite.u4` from `int_nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_satfinite_u4` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f16.f16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f16_f16` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.bf16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_bf16` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f32.f32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f32_f32` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.tf32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_tf32` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8.u8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8_u8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | @@ -663,6 +670,7 @@ This table is generated from the resolved catalog. Evidence stages below disting | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8.s8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8_s8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8.s8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8_s8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::movmatrix_trans_b16` | `nvvm.movmatrix_trans_b16` | PTX-native `movmatrix.sync.aligned.m8n8.trans.b16` | unsafe; scope warp; impure; memory inaccessible_read_write; convergent true | PTX 7.8 on sm_75+ ([PTX ISA 9.3, 9.7.15.5.17 Warp-level matrix transpose instruction: movmatrix](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-movmatrix)) | validated on `rust-llvm-23.1.0-16696adc`; expects `movmatrix.sync.aligned.m8n8.trans.b16 , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::bf16x2::mul_bf16x2` | `nvvm.mul_bf16x2` | PTX-native `mul.rn.bf16x2` | safe; scope thread; pure; memory none; convergent false | PTX 7.8 on sm_90+ ([PTX ISA 9.3, 9.7.4.3 Half Precision Floating Point Instructions: mul](https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-mul)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mul.rn.bf16x2 , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::f16x2::mul_f16x2` | `nvvm.mul_f16x2` | PTX-native `mul.rn.f16x2` | safe; scope thread; pure; memory none; convergent false | PTX 4.2 on sm_70+ ([PTX ISA 9.3, 9.7.4.3 Half Precision Floating Point Instructions: mul](https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-mul)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mul.rn.f16x2 , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | @@ -3338,6 +3346,34 @@ This table is generated from the resolved catalog. Evidence stages below disting - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209` - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite` - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite` +- `mma_sp_ordered_metadata_m16n8k16_f16_f16` (`i1020`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16` +- `mma_sp_ordered_metadata_m16n8k16_f32_bf16` (`i1019`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16` +- `mma_sp_ordered_metadata_m16n8k16_f32_f16` (`i1021`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16` +- `mma_sp_ordered_metadata_m16n8k16_f32_tf32` (`i1018`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32` +- `mma_sp_ordered_metadata_m16n8k32_f16_f16` (`i1023`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16` +- `mma_sp_ordered_metadata_m16n8k32_f32_bf16` (`i1022`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16` +- `mma_sp_ordered_metadata_m16n8k32_f32_f16` (`i1024`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16` - `mma_sp_ordered_metadata_m16n8k32_s32_s8` (`i0171`) - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171` - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8` @@ -3634,6 +3670,10 @@ This table is generated from the resolved catalog. Evidence stages below disting - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185` - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite` - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite` +- `mma_sp_ordered_metadata_m16n8k8_f32_tf32` (`i1017`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32` - `movmatrix_trans_b16` (`i0305`) - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305` - public source path: `cuda_intrinsics::matrix::movmatrix_trans_b16` @@ -5302,6 +5342,13 @@ This table is generated from the resolved catalog. Evidence stages below disting - `mma_sp_ordered_metadata_m16n8k128_s32_u4_s4` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow wraps. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow uses finite saturation. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow uses finite saturation. Runtime validation is not executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k16_f16_f16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`, `1`, `2`, or `3`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k16_f32_bf16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`, `1`, `2`, or `3`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k16_f32_f16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`, `1`, `2`, or `3`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k16_f32_tf32` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k32_f16_f16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k32_f32_bf16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k32_f32_f16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. - `mma_sp_ordered_metadata_m16n8k32_s32_s8` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow wraps. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow uses finite saturation. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k32_s32_s8_u8` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow wraps. Runtime validation is not executed on a GPU. @@ -5376,6 +5423,7 @@ This table is generated from the resolved catalog. Evidence stages below disting - `mma_sp_ordered_metadata_m16n8k64_s32_u8_s8` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow wraps. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow uses finite saturation. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow uses finite saturation. Runtime validation is not executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k8_f32_tf32` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`, `1`, `2`, or `3`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. ## Packed-atomic contracts @@ -6211,6 +6259,13 @@ This table is generated from the resolved catalog. Evidence stages below disting - `mma_sp_ordered_metadata_m16n8k128_s32_u4_s4`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19632`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19699`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19702`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k16_f16_f16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19554`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k16_f32_bf16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19524`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k16_f32_f16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19558`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k16_f32_tf32`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19546`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k32_f16_f16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19566`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k32_f32_bf16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19532`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k32_f32_f16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19570`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k32_s32_s8`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19644`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19705`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k32_s32_s8_u8`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19649`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` @@ -6285,6 +6340,7 @@ This table is generated from the resolved catalog. Evidence stages below disting - `mma_sp_ordered_metadata_m16n8k64_s32_u8_s8`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19674`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19723`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19726`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k8_f32_tf32`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19540`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `movmatrix_trans_b16`: PTX-native source; no LLVM record, symbol, properties, or selection facts. - `mul_bf16x2`: PTX-native source; no LLVM record, symbol, properties, or selection facts. - `mul_f16x2`: PTX-native source; no LLVM record, symbol, properties, or selection facts. @@ -13396,6 +13452,76 @@ This table is generated from the resolved catalog. Evidence stages below disting - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `validated` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) - backend codegen on `compute_80, ptx93`: `succeeded` — The production artifacts described by the first record retained saturating u4-by-u4 PTX with selector 0. - device link on `sm_80, ptx93`: `succeeded` — The 27,880-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. +- `mma_sp_ordered_metadata_m16n8k16_f16_f16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). + - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. + - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k16_f32_bf16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). + - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. + - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k16_f32_f16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). + - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. + - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k16_f32_tf32`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). + - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. + - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k32_f16_f16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). + - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. + - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k32_f32_bf16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). + - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. + - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k32_f32_f16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). + - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. + - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `mma_sp_ordered_metadata_m16n8k32_s32_s8`: runtime `unexecuted` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `validated` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - backend codegen on `sm_80, ptx85`: `succeeded` — The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80. @@ -14364,6 +14490,16 @@ This table is generated from the resolved catalog. Evidence stages below disting - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `validated` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) - backend codegen on `compute_80, ptx93`: `succeeded` — The production generated_intrinsics route produced 242,464-byte compute_80 NVVM IR with SHA-256 fcc2fe1a6200de7b5ab8a38cab847432669fe4d6ce823c81b73f9b18fa25144c and 68,600-byte LTOIR with SHA-256 aa011070e20cb91d99f0d6d41ffd3883f01031b44d171380f638e3674b2facf3. All eight raw variants use compile-time selector 0. - device link on `sm_80, ptx93`: `succeeded` — nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. +- `mma_sp_ordered_metadata_m16n8k8_f32_tf32`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). + - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. + - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `movmatrix_trans_b16`: runtime `unexecuted` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 7.8 / sm_75+: status `validated` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - backend codegen on `sm_75, ptx78`: `succeeded` — Pinned Rust LLVM emitted one exact movmatrix instruction; source SHA-256 b8776ed95d8c8e451deea02d8851a238cfcfe570e286a92c94e5971bf06db963, bitcode SHA-256 caf25ab44ed893d449343707f06af85395e86f41852c32ec1b577be184365aee, and PTX SHA-256 f1e1b7d8ad879abd120d6cb32a5999925af0ed77b3a7144a7dfd8db76ea18246. diff --git a/intrinsics/probes/abs_bf16x2.ll b/intrinsics/probes/abs_bf16x2.ll index d1e5f02253..e6fb799457 100644 --- a/intrinsics/probes/abs_bf16x2.ll +++ b/intrinsics/probes/abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/abs_f16x2.ll b/intrinsics/probes/abs_f16x2.ll index 47ae946cb4..c59cf11969 100644 --- a/intrinsics/probes/abs_f16x2.ll +++ b/intrinsics/probes/abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/active_mask.ll b/intrinsics/probes/active_mask.ll index 2d8590535d..2cf0f44f20 100644 --- a/intrinsics/probes/active_mask.ll +++ b/intrinsics/probes/active_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_bf16x2.ll b/intrinsics/probes/add_bf16x2.ll index 8dc93f5729..fe9baee1ae 100644 --- a/intrinsics/probes/add_bf16x2.ll +++ b/intrinsics/probes/add_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_f16x2.ll b/intrinsics/probes/add_f16x2.ll index 53e3da1686..5ed0b49a23 100644 --- a/intrinsics/probes/add_f16x2.ll +++ b/intrinsics/probes/add_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_f32x2.ll b/intrinsics/probes/add_f32x2.ll index 5b8a97e268..100f437c8f 100644 --- a/intrinsics/probes/add_f32x2.ll +++ b/intrinsics/probes/add_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_ftz_f32x2.ll b/intrinsics/probes/add_ftz_f32x2.ll index e7ffa59e04..407c6f7559 100644 --- a/intrinsics/probes/add_ftz_f32x2.ll +++ b/intrinsics/probes/add_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_f32.ll b/intrinsics/probes/add_rm_f32.ll index d61bdc8bdb..459e42ee06 100644 --- a/intrinsics/probes/add_rm_f32.ll +++ b/intrinsics/probes/add_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_f64.ll b/intrinsics/probes/add_rm_f64.ll index 9c3997e1c4..8fd3c7375e 100644 --- a/intrinsics/probes/add_rm_f64.ll +++ b/intrinsics/probes/add_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_ftz_f32.ll b/intrinsics/probes/add_rm_ftz_f32.ll index 140b92a61a..d871b073e0 100644 --- a/intrinsics/probes/add_rm_ftz_f32.ll +++ b/intrinsics/probes/add_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_ftz_sat_f32.ll b/intrinsics/probes/add_rm_ftz_sat_f32.ll index e6b92ddef0..385722bf09 100644 --- a/intrinsics/probes/add_rm_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rm_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_sat_f32.ll b/intrinsics/probes/add_rm_sat_f32.ll index 68a3734a97..784a29862e 100644 --- a/intrinsics/probes/add_rm_sat_f32.ll +++ b/intrinsics/probes/add_rm_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_f32.ll b/intrinsics/probes/add_rn_f32.ll index 65e6721beb..1d6ebadabd 100644 --- a/intrinsics/probes/add_rn_f32.ll +++ b/intrinsics/probes/add_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_f64.ll b/intrinsics/probes/add_rn_f64.ll index 57c4e7b726..71f4e2aa14 100644 --- a/intrinsics/probes/add_rn_f64.ll +++ b/intrinsics/probes/add_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_ftz_f32.ll b/intrinsics/probes/add_rn_ftz_f32.ll index 4ec19b5894..ee78a0e33d 100644 --- a/intrinsics/probes/add_rn_ftz_f32.ll +++ b/intrinsics/probes/add_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_ftz_sat_f32.ll b/intrinsics/probes/add_rn_ftz_sat_f32.ll index 899dca925b..44d9d79faf 100644 --- a/intrinsics/probes/add_rn_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rn_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_sat_f32.ll b/intrinsics/probes/add_rn_sat_f32.ll index e0b1f83682..b8931f0866 100644 --- a/intrinsics/probes/add_rn_sat_f32.ll +++ b/intrinsics/probes/add_rn_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_f32.ll b/intrinsics/probes/add_rp_f32.ll index 331ab84ef3..72cbcdddf4 100644 --- a/intrinsics/probes/add_rp_f32.ll +++ b/intrinsics/probes/add_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_f64.ll b/intrinsics/probes/add_rp_f64.ll index 0db2cd43dd..6e12d4f083 100644 --- a/intrinsics/probes/add_rp_f64.ll +++ b/intrinsics/probes/add_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_ftz_f32.ll b/intrinsics/probes/add_rp_ftz_f32.ll index 81dd6ba650..e49132c668 100644 --- a/intrinsics/probes/add_rp_ftz_f32.ll +++ b/intrinsics/probes/add_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_ftz_sat_f32.ll b/intrinsics/probes/add_rp_ftz_sat_f32.ll index 8d348c793f..c96ad0b225 100644 --- a/intrinsics/probes/add_rp_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rp_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_sat_f32.ll b/intrinsics/probes/add_rp_sat_f32.ll index 7c1f3f884b..d27771537c 100644 --- a/intrinsics/probes/add_rp_sat_f32.ll +++ b/intrinsics/probes/add_rp_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_f32.ll b/intrinsics/probes/add_rz_f32.ll index 629c3dba46..c9376f22de 100644 --- a/intrinsics/probes/add_rz_f32.ll +++ b/intrinsics/probes/add_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_f64.ll b/intrinsics/probes/add_rz_f64.ll index b82d78b959..6a16bf7ce8 100644 --- a/intrinsics/probes/add_rz_f64.ll +++ b/intrinsics/probes/add_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_ftz_f32.ll b/intrinsics/probes/add_rz_ftz_f32.ll index 10d52d5ed0..b122384f6a 100644 --- a/intrinsics/probes/add_rz_ftz_f32.ll +++ b/intrinsics/probes/add_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_ftz_sat_f32.ll b/intrinsics/probes/add_rz_ftz_sat_f32.ll index b9fbfb2cdb..d1523ce8cd 100644 --- a/intrinsics/probes/add_rz_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rz_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_sat_f32.ll b/intrinsics/probes/add_rz_sat_f32.ll index 634729b049..fc1ae831f5 100644 --- a/intrinsics/probes/add_rz_sat_f32.ll +++ b/intrinsics/probes/add_rz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/all_sync.ll b/intrinsics/probes/all_sync.ll index 30eaa55e8f..0853e51441 100644 --- a/intrinsics/probes/all_sync.ll +++ b/intrinsics/probes/all_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/any_sync.ll b/intrinsics/probes/any_sync.ll index cb63ce9b1e..38d345acdf 100644 --- a/intrinsics/probes/any_sync.ll +++ b/intrinsics/probes/any_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ballot_sync.ll b/intrinsics/probes/ballot_sync.ll index 663f08b094..e0d8b053db 100644 --- a/intrinsics/probes/ballot_sync.ll +++ b/intrinsics/probes/ballot_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive.ll b/intrinsics/probes/barrier_cluster_arrive.ll index 556960c72e..7cf7d7e200 100644 --- a/intrinsics/probes/barrier_cluster_arrive.ll +++ b/intrinsics/probes/barrier_cluster_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_aligned.ll b/intrinsics/probes/barrier_cluster_arrive_aligned.ll index 852b3a7999..bc2bdac9ea 100644 --- a/intrinsics/probes/barrier_cluster_arrive_aligned.ll +++ b/intrinsics/probes/barrier_cluster_arrive_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_relaxed.ll b/intrinsics/probes/barrier_cluster_arrive_relaxed.ll index 0d1d9ced94..b3f3c94676 100644 --- a/intrinsics/probes/barrier_cluster_arrive_relaxed.ll +++ b/intrinsics/probes/barrier_cluster_arrive_relaxed.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll b/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll index bc894a529f..467335b6ac 100644 --- a/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll +++ b/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_wait.ll b/intrinsics/probes/barrier_cluster_wait.ll index 403f1d8060..04c2b40735 100644 --- a/intrinsics/probes/barrier_cluster_wait.ll +++ b/intrinsics/probes/barrier_cluster_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_wait_aligned.ll b/intrinsics/probes/barrier_cluster_wait_aligned.ll index 304a1de4d8..0ee96d911b 100644 --- a/intrinsics/probes/barrier_cluster_wait_aligned.ll +++ b/intrinsics/probes/barrier_cluster_wait_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_arrive.ll b/intrinsics/probes/barrier_cta_arrive.ll index 5ac1d1d068..5a8f9aacb7 100644 --- a/intrinsics/probes/barrier_cta_arrive.ll +++ b/intrinsics/probes/barrier_cta_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_arrive_aligned.ll b/intrinsics/probes/barrier_cta_arrive_aligned.ll index 1a03463d7c..9e840a582b 100644 --- a/intrinsics/probes/barrier_cta_arrive_aligned.ll +++ b/intrinsics/probes/barrier_cta_arrive_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_sync.ll b/intrinsics/probes/barrier_cta_sync.ll index cf34136e0e..e3cf0f5eac 100644 --- a/intrinsics/probes/barrier_cta_sync.ll +++ b/intrinsics/probes/barrier_cta_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_sync_aligned.ll b/intrinsics/probes/barrier_cta_sync_aligned.ll index 1b535ade7b..0cc041bd50 100644 --- a/intrinsics/probes/barrier_cta_sync_aligned.ll +++ b/intrinsics/probes/barrier_cta_sync_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_x.ll b/intrinsics/probes/block_dim_x.ll index 6947929f43..2a6398b7ac 100644 --- a/intrinsics/probes/block_dim_x.ll +++ b/intrinsics/probes/block_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_y.ll b/intrinsics/probes/block_dim_y.ll index eea6ea890f..cc63ff9ef7 100644 --- a/intrinsics/probes/block_dim_y.ll +++ b/intrinsics/probes/block_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_z.ll b/intrinsics/probes/block_dim_z.ll index 73872c2881..2889ecfc57 100644 --- a/intrinsics/probes/block_dim_z.ll +++ b/intrinsics/probes/block_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_x.ll b/intrinsics/probes/block_idx_x.ll index 94576b081b..6a118597a3 100644 --- a/intrinsics/probes/block_idx_x.ll +++ b/intrinsics/probes/block_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_y.ll b/intrinsics/probes/block_idx_y.ll index d358f1a5dd..83a4db4ab8 100644 --- a/intrinsics/probes/block_idx_y.ll +++ b/intrinsics/probes/block_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_z.ll b/intrinsics/probes/block_idx_z.ll index 70cc490f93..4aa6383b50 100644 --- a/intrinsics/probes/block_idx_z.ll +++ b/intrinsics/probes/block_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/breakpoint.ll b/intrinsics/probes/breakpoint.ll index 45664bd8cd..f6e0c4a966 100644 --- a/intrinsics/probes/breakpoint.ll +++ b/intrinsics/probes/breakpoint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_x.ll b/intrinsics/probes/clc_query_get_first_ctaid_x.ll index dfc021c3b9..148a7033ed 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_x.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_y.ll b/intrinsics/probes/clc_query_get_first_ctaid_y.ll index 177ff28bbb..f2ae9380ca 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_y.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_z.ll b/intrinsics/probes/clc_query_get_first_ctaid_z.ll index 3b13fe0f7c..fced9cc0f0 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_z.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_is_canceled.ll b/intrinsics/probes/clc_query_is_canceled.ll index 939d44bf6d..9a3c3d509f 100644 --- a/intrinsics/probes/clc_query_is_canceled.ll +++ b/intrinsics/probes/clc_query_is_canceled.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_try_cancel.ll b/intrinsics/probes/clc_try_cancel.ll index 076d75210e..07288866d7 100644 --- a/intrinsics/probes/clc_try_cancel.ll +++ b/intrinsics/probes/clc_try_cancel.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_try_cancel_multicast.ll b/intrinsics/probes/clc_try_cancel_multicast.ll index 0bd6ba355d..3c209c045a 100644 --- a/intrinsics/probes/clc_try_cancel_multicast.ll +++ b/intrinsics/probes/clc_try_cancel_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock.lib_nvvm.ll b/intrinsics/probes/clock.lib_nvvm.ll index fc723028f5..3a1607fb56 100644 --- a/intrinsics/probes/clock.lib_nvvm.ll +++ b/intrinsics/probes/clock.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock.llvm_nvptx.ll b/intrinsics/probes/clock.llvm_nvptx.ll index 8f2ac6ee1c..5c18c50157 100644 --- a/intrinsics/probes/clock.llvm_nvptx.ll +++ b/intrinsics/probes/clock.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock64.lib_nvvm.ll b/intrinsics/probes/clock64.lib_nvvm.ll index 796bbaacb3..0707ff223c 100644 --- a/intrinsics/probes/clock64.lib_nvvm.ll +++ b/intrinsics/probes/clock64.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock64.llvm_nvptx.ll b/intrinsics/probes/clock64.llvm_nvptx.ll index ae162b6e4c..ef2efc7154 100644 --- a/intrinsics/probes/clock64.llvm_nvptx.ll +++ b/intrinsics/probes/clock64.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_count.ll b/intrinsics/probes/cluster_block_count.ll index f4837499bd..415815cfd4 100644 --- a/intrinsics/probes/cluster_block_count.ll +++ b/intrinsics/probes/cluster_block_count.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_x.ll b/intrinsics/probes/cluster_block_idx_x.ll index 7d09cbd46b..655c289cdd 100644 --- a/intrinsics/probes/cluster_block_idx_x.ll +++ b/intrinsics/probes/cluster_block_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_y.ll b/intrinsics/probes/cluster_block_idx_y.ll index 7fcfc691fb..f03730022c 100644 --- a/intrinsics/probes/cluster_block_idx_y.ll +++ b/intrinsics/probes/cluster_block_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_z.ll b/intrinsics/probes/cluster_block_idx_z.ll index 6324d18e45..9961c42479 100644 --- a/intrinsics/probes/cluster_block_idx_z.ll +++ b/intrinsics/probes/cluster_block_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_rank.ll b/intrinsics/probes/cluster_block_rank.ll index b072d4d33f..c06724178b 100644 --- a/intrinsics/probes/cluster_block_rank.ll +++ b/intrinsics/probes/cluster_block_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_x.ll b/intrinsics/probes/cluster_dim_x.ll index 8bb6a7638d..3ff053505d 100644 --- a/intrinsics/probes/cluster_dim_x.ll +++ b/intrinsics/probes/cluster_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_y.ll b/intrinsics/probes/cluster_dim_y.ll index c1430e8dd2..e0b35bd3c1 100644 --- a/intrinsics/probes/cluster_dim_y.ll +++ b/intrinsics/probes/cluster_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_z.ll b/intrinsics/probes/cluster_dim_z.ll index 5b957d9358..d51ba080db 100644 --- a/intrinsics/probes/cluster_dim_z.ll +++ b/intrinsics/probes/cluster_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_x.ll b/intrinsics/probes/cluster_grid_dim_x.ll index 1637291a9a..07d16a5ed3 100644 --- a/intrinsics/probes/cluster_grid_dim_x.ll +++ b/intrinsics/probes/cluster_grid_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_y.ll b/intrinsics/probes/cluster_grid_dim_y.ll index d3d5f145c9..f5caeb8b72 100644 --- a/intrinsics/probes/cluster_grid_dim_y.ll +++ b/intrinsics/probes/cluster_grid_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_z.ll b/intrinsics/probes/cluster_grid_dim_z.ll index 232a35851b..203083c277 100644 --- a/intrinsics/probes/cluster_grid_dim_z.ll +++ b/intrinsics/probes/cluster_grid_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_x.ll b/intrinsics/probes/cluster_idx_x.ll index 36c0e25436..c659e62ec5 100644 --- a/intrinsics/probes/cluster_idx_x.ll +++ b/intrinsics/probes/cluster_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_y.ll b/intrinsics/probes/cluster_idx_y.ll index f49d85d2ce..3015abe864 100644 --- a/intrinsics/probes/cluster_idx_y.ll +++ b/intrinsics/probes/cluster_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_z.ll b/intrinsics/probes/cluster_idx_z.ll index 4ad5c46452..4e719d1861 100644 --- a/intrinsics/probes/cluster_idx_z.ll +++ b/intrinsics/probes/cluster_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cos_approx_f32.ll b/intrinsics/probes/cos_approx_f32.ll index c0ba625c06..bfdd221a05 100644 --- a/intrinsics/probes/cos_approx_f32.ll +++ b/intrinsics/probes/cos_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cos_approx_ftz_f32.ll b/intrinsics/probes/cos_approx_ftz_f32.ll index 5afb1bb35a..b8b48bcb35 100644 --- a/intrinsics/probes/cos_approx_ftz_f32.ll +++ b/intrinsics/probes/cos_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_commit_group.ll b/intrinsics/probes/cp_async_bulk_commit_group.ll index 6a4a398dbf..7c801c462a 100644 --- a/intrinsics/probes/cp_async_bulk_commit_group.ll +++ b/intrinsics/probes/cp_async_bulk_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll index de9c3ef06f..9e19ef2f0e 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll index e60aab3a4c..76ccbfdc16 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll index 4d8b801606..99bea0526e 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll index a465a0ce97..0a624d9515 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll index 14768b8cfe..3c5d1f88c4 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll index e4a3a5be16..420a966a63 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll index 71fee6714b..3bd0181a27 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll index 2753b98543..6fc0e5963d 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll index 6974a419be..20003ca5f4 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll index 0515946aa9..02ec0be672 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll index 97198d2ec3..5d62ec7725 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll index 5eef8a82f6..0b059d0d47 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll index 33aee499a3..a3a991ba7f 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll index 4d68fab62a..9bb71fb5dc 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll index 5cd4c4eb77..e232956b3f 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll index ace8f67603..1348155d08 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll index cd518cc31d..64749dae1a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll index 4dd77c02fe..fee2c85363 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll index 1adde99fe3..2e3b2b5eb7 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll index 8e59aa47f5..5241db4709 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll index b6ce08a89e..b529afe4c2 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll index b2de7f404c..270fb918a6 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll index 4eb490424e..6755f3dabe 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll index 8af5c9d4a7..eda0a7fb46 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll index 97c125a911..915fdc7dbc 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll index cede3c738a..4fcbb9a19a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll index ecfc22cb0b..da0d2b7580 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll index 3159b0855e..6c1a28d076 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll index f35dfaee49..0d005487c6 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll index d637aa9825..c3833e7c8b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll index 993e458266..264d12afea 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll index ae6e601522..10ba6ae4b6 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll index aa9263bbd2..360077da2e 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll index cbb56c1ee2..01bed7b9a9 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll index c9cfdf63f3..e67c3402e8 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll index fdf9858720..19f2ca669b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll index f19e894ced..bef4763e87 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll index 289cd6289d..ba17af5ead 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll index 81d3865022..473383aab4 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll index a21b8af2c0..74e25727fe 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll index 8a31dc83b1..2d07b1047c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll index b345b702cd..2d879673af 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll index 003476924c..f09e81e6ab 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll index 8154ae9a42..50ef3e7026 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll index 796f747060..47af6e5c27 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll index 99b8b04a9c..bbe2abbbff 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll index c1cce4fa32..f860552451 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll index b345aaac10..8e922fe397 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll index daa6ad79b1..51322b4706 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll index 6ff318d15c..c5a4a9a142 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll index 7d07322e79..863a6b3270 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll index 6dd094bcfd..5c1446aed9 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll index 0c620050f6..94b05033d9 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll index 9deeca3970..89c59f1525 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll index 182956f879..c1885aeba7 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll index e38914fabe..d1cdcb688c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll index dd1c4719e5..1240bad8e9 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll index 6f3d76e002..925a4d8578 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll index 9745b0db96..7bc7e5f9c1 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll index e31b613b4f..732591672d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll index a43f95c447..a688418231 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll index 8a0e4e574f..a69b5bd2ee 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll index 8958c0d0cb..0499cc5635 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll index 58bfb4a9b1..8583c6fb41 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll index dd801209dc..6e644a15cc 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll index 9f3f568613..5b3cf19f85 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll index d491352aed..c586ed282b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll index cdcd68b9de..b7b3825501 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll index 3856120b1d..b1308b81be 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll index 4f9fc5b64c..6556cf3892 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll index 17dfade586..a264426df4 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll index 8a6ead8a40..79f19f327a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll index 88b452174b..b14af032e0 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll index 8b0f52b5b9..678000eb49 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll index a85cb05073..118f8d8d36 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll index 493b00f32f..74734ffd0f 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll index 3d62a36848..580c679b8a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll index 951f4d37d9..55c32cff7b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll index c90cd661d3..132292241b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll index 3dae744323..e12811a32b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll index 4c8e9bdb66..3b38d09e59 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll index 30c0e2102a..22e8c2e0e2 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll index 22646966b7..c7d22452af 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll index 839da2c0a1..07e22624c6 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll index 22df313382..287148569c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll index ff0f6c90c3..10dd041a9a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll index 38e826ab22..5c1f1bac1c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll index c16c1acfde..b031e9eeca 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_wait_group.ll b/intrinsics/probes/cp_async_bulk_wait_group.ll index 623dd8ce5e..cc655f0af5 100644 --- a/intrinsics/probes/cp_async_bulk_wait_group.ll +++ b/intrinsics/probes/cp_async_bulk_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_wait_group_read.ll b/intrinsics/probes/cp_async_bulk_wait_group_read.ll index 18fae66eb0..31b84429e2 100644 --- a/intrinsics/probes/cp_async_bulk_wait_group_read.ll +++ b/intrinsics/probes/cp_async_bulk_wait_group_read.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_16.ll b/intrinsics/probes/cp_async_ca_16.ll index ff0f19e9ef..9878bc1db0 100644 --- a/intrinsics/probes/cp_async_ca_16.ll +++ b/intrinsics/probes/cp_async_ca_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_4.ll b/intrinsics/probes/cp_async_ca_4.ll index 7ff86d597d..77f68e6d2e 100644 --- a/intrinsics/probes/cp_async_ca_4.ll +++ b/intrinsics/probes/cp_async_ca_4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_8.ll b/intrinsics/probes/cp_async_ca_8.ll index 5b8ebc7b26..ed48932575 100644 --- a/intrinsics/probes/cp_async_ca_8.ll +++ b/intrinsics/probes/cp_async_ca_8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_16.ll b/intrinsics/probes/cp_async_ca_zfill_16.ll index 37794beb34..6d8f828efe 100644 --- a/intrinsics/probes/cp_async_ca_zfill_16.ll +++ b/intrinsics/probes/cp_async_ca_zfill_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_4.ll b/intrinsics/probes/cp_async_ca_zfill_4.ll index de7c41cda4..73bb799348 100644 --- a/intrinsics/probes/cp_async_ca_zfill_4.ll +++ b/intrinsics/probes/cp_async_ca_zfill_4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_8.ll b/intrinsics/probes/cp_async_ca_zfill_8.ll index 52da88c802..1f76c5f957 100644 --- a/intrinsics/probes/cp_async_ca_zfill_8.ll +++ b/intrinsics/probes/cp_async_ca_zfill_8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_cg_16.ll b/intrinsics/probes/cp_async_cg_16.ll index da0d0a0364..ec0be2d203 100644 --- a/intrinsics/probes/cp_async_cg_16.ll +++ b/intrinsics/probes/cp_async_cg_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_cg_zfill_16.ll b/intrinsics/probes/cp_async_cg_zfill_16.ll index 6bc0a3dfc7..e9c1413da9 100644 --- a/intrinsics/probes/cp_async_cg_zfill_16.ll +++ b/intrinsics/probes/cp_async_cg_zfill_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_commit_group.ll b/intrinsics/probes/cp_async_commit_group.ll index edc1de534b..bdf0051c87 100644 --- a/intrinsics/probes/cp_async_commit_group.ll +++ b/intrinsics/probes/cp_async_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive.ll b/intrinsics/probes/cp_async_mbarrier_arrive.ll index a7b19e8e17..c5aa0a3417 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll b/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll index 2180e32920..8560ebfbff 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll b/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll index d3e18dbdf6..785f65460f 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll b/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll index b7865e9a1b..9b7b372217 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_wait_all.ll b/intrinsics/probes/cp_async_wait_all.ll index f707b1ccb1..0d66e4e8de 100644 --- a/intrinsics/probes/cp_async_wait_all.ll +++ b/intrinsics/probes/cp_async_wait_all.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_wait_group.ll b/intrinsics/probes/cp_async_wait_group.ll index 4f72447ccb..2f102d57c7 100644 --- a/intrinsics/probes/cp_async_wait_group.ll +++ b/intrinsics/probes/cp_async_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_f16x2_f32.ll b/intrinsics/probes/cvt_f16x2_f32.ll index 2537ccc7c6..8333b49986 100644 --- a/intrinsics/probes/cvt_f16x2_f32.ll +++ b/intrinsics/probes/cvt_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_f32x2_bf16x2.ll b/intrinsics/probes/cvt_f32x2_bf16x2.ll index ae6e098418..485ac6e630 100644 --- a/intrinsics/probes/cvt_f32x2_bf16x2.ll +++ b/intrinsics/probes/cvt_f32x2_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll b/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll index c3addf14c5..74478b7575 100644 --- a/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll +++ b/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll b/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll index c6a61859f2..8bf3313ef8 100644 --- a/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll +++ b/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll b/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll index 927463bba9..b214cca747 100644 --- a/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll b/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll index ba05ffb256..7a43e5878b 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll b/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll index 9389e9c403..d3f00598ab 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll b/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll index f74e285876..a25ce60678 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll index c53ca79610..1403f445c6 100644 --- a/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_tf32_f32.ll b/intrinsics/probes/cvt_rn_relu_tf32_f32.ll index 6b5ff413cc..c30ce68d6d 100644 --- a/intrinsics/probes/cvt_rn_relu_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll index 513b293b84..f8ada23376 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll index 763a6e49f4..f8ccbf7d94 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll index a9e4148e3a..81f3b26c11 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll index 314877ce9b..0004bec3f3 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll index 21363162ac..da82ae2ce1 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll index 42175a8cb6..6851724f0e 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll index 8348ef7ba8..21e76a91b2 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll index a227b06b8f..f6a2baf698 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll index cf25a878f0..e4a4c8ee2e 100644 --- a/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_tf32_f32.ll b/intrinsics/probes/cvt_rn_tf32_f32.ll index f46f631ef7..dad72f5c89 100644 --- a/intrinsics/probes/cvt_rn_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll index ea79a27dcd..f2f08234a6 100644 --- a/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rna_tf32_f32.ll b/intrinsics/probes/cvt_rna_tf32_f32.ll index 9754804dae..bfc8f18a9b 100644 --- a/intrinsics/probes/cvt_rna_tf32_f32.ll +++ b/intrinsics/probes/cvt_rna_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_bf16x2_f32.ll b/intrinsics/probes/cvt_rz_bf16x2_f32.ll index 4010cbfee0..6e7d27621f 100644 --- a/intrinsics/probes/cvt_rz_bf16x2_f32.ll +++ b/intrinsics/probes/cvt_rz_bf16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_f16x2_f32.ll b/intrinsics/probes/cvt_rz_f16x2_f32.ll index df4ecc954e..19c5e1df07 100644 --- a/intrinsics/probes/cvt_rz_f16x2_f32.ll +++ b/intrinsics/probes/cvt_rz_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll index e9026ca85c..b1c09fa641 100644 --- a/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_relu_tf32_f32.ll b/intrinsics/probes/cvt_rz_relu_tf32_f32.ll index 333f4e0b56..3caba1e0ba 100644 --- a/intrinsics/probes/cvt_rz_relu_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_relu_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll index 5eafe049ce..820b2ffbb0 100644 --- a/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_tf32_f32.ll b/intrinsics/probes/cvt_rz_tf32_f32.ll index 9cfa233682..25830799f4 100644 --- a/intrinsics/probes/cvt_rz_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_f32.ll b/intrinsics/probes/div_rm_f32.ll index a1ba8a11af..46e42dc2bd 100644 --- a/intrinsics/probes/div_rm_f32.ll +++ b/intrinsics/probes/div_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_f64.ll b/intrinsics/probes/div_rm_f64.ll index b9d7260b35..ab0cfdf057 100644 --- a/intrinsics/probes/div_rm_f64.ll +++ b/intrinsics/probes/div_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_ftz_f32.ll b/intrinsics/probes/div_rm_ftz_f32.ll index 06b17498ca..48097214a8 100644 --- a/intrinsics/probes/div_rm_ftz_f32.ll +++ b/intrinsics/probes/div_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_f32.ll b/intrinsics/probes/div_rn_f32.ll index 6fce68bc4e..88dc1c48c2 100644 --- a/intrinsics/probes/div_rn_f32.ll +++ b/intrinsics/probes/div_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_f64.ll b/intrinsics/probes/div_rn_f64.ll index 6d0a6b4b36..8aa2f6331a 100644 --- a/intrinsics/probes/div_rn_f64.ll +++ b/intrinsics/probes/div_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_ftz_f32.ll b/intrinsics/probes/div_rn_ftz_f32.ll index de768fe271..dc80a2b019 100644 --- a/intrinsics/probes/div_rn_ftz_f32.ll +++ b/intrinsics/probes/div_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_f32.ll b/intrinsics/probes/div_rp_f32.ll index a56470e7fe..5b7c737f97 100644 --- a/intrinsics/probes/div_rp_f32.ll +++ b/intrinsics/probes/div_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_f64.ll b/intrinsics/probes/div_rp_f64.ll index 5db7d1ea62..08b74a3b5f 100644 --- a/intrinsics/probes/div_rp_f64.ll +++ b/intrinsics/probes/div_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_ftz_f32.ll b/intrinsics/probes/div_rp_ftz_f32.ll index e60984da46..2ca2ac030e 100644 --- a/intrinsics/probes/div_rp_ftz_f32.ll +++ b/intrinsics/probes/div_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_f32.ll b/intrinsics/probes/div_rz_f32.ll index b485591930..2e42c78628 100644 --- a/intrinsics/probes/div_rz_f32.ll +++ b/intrinsics/probes/div_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_f64.ll b/intrinsics/probes/div_rz_f64.ll index bdc5c05810..95db78708c 100644 --- a/intrinsics/probes/div_rz_f64.ll +++ b/intrinsics/probes/div_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_ftz_f32.ll b/intrinsics/probes/div_rz_ftz_f32.ll index 72c351d70b..2863b39931 100644 --- a/intrinsics/probes/div_rz_ftz_f32.ll +++ b/intrinsics/probes/div_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp2a_s32.ll b/intrinsics/probes/dp2a_s32.ll index 7cbf520aae..b881991a41 100644 --- a/intrinsics/probes/dp2a_s32.ll +++ b/intrinsics/probes/dp2a_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp2a_u32.ll b/intrinsics/probes/dp2a_u32.ll index 74ad4f0f05..713e02c01b 100644 --- a/intrinsics/probes/dp2a_u32.ll +++ b/intrinsics/probes/dp2a_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp4a_s32.ll b/intrinsics/probes/dp4a_s32.ll index 63b2066a87..c7eac97056 100644 --- a/intrinsics/probes/dp4a_s32.ll +++ b/intrinsics/probes/dp4a_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp4a_u32.ll b/intrinsics/probes/dp4a_u32.ll index 07e228dbeb..d1df0d2551 100644 --- a/intrinsics/probes/dp4a_u32.ll +++ b/intrinsics/probes/dp4a_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dsmem_read_u32.ll b/intrinsics/probes/dsmem_read_u32.ll index bd20f71c52..ab4b2b9f76 100644 --- a/intrinsics/probes/dsmem_read_u32.ll +++ b/intrinsics/probes/dsmem_read_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll b/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll index e8e686c940..c5e2576c17 100644 --- a/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll +++ b/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll b/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll index 11d3655b87..a8f100f2fc 100644 --- a/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll +++ b/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/elect_sync.lib_nvvm.ll b/intrinsics/probes/elect_sync.lib_nvvm.ll index 42690a8c39..a3f00f5734 100644 --- a/intrinsics/probes/elect_sync.lib_nvvm.ll +++ b/intrinsics/probes/elect_sync.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/elect_sync.llvm_nvptx.ll b/intrinsics/probes/elect_sync.llvm_nvptx.ll index fbcb10cbf1..aa0c4da150 100644 --- a/intrinsics/probes/elect_sync.llvm_nvptx.ll +++ b/intrinsics/probes/elect_sync.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg1.lib_nvvm.ll b/intrinsics/probes/envreg1.lib_nvvm.ll index d2dbb36fdb..4429281334 100644 --- a/intrinsics/probes/envreg1.lib_nvvm.ll +++ b/intrinsics/probes/envreg1.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg1.llvm_nvptx.ll b/intrinsics/probes/envreg1.llvm_nvptx.ll index 7c4982f6c3..47c348142d 100644 --- a/intrinsics/probes/envreg1.llvm_nvptx.ll +++ b/intrinsics/probes/envreg1.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg2.lib_nvvm.ll b/intrinsics/probes/envreg2.lib_nvvm.ll index cc36ec7151..ba46be7a38 100644 --- a/intrinsics/probes/envreg2.lib_nvvm.ll +++ b/intrinsics/probes/envreg2.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg2.llvm_nvptx.ll b/intrinsics/probes/envreg2.llvm_nvptx.ll index 00e322a1df..677b208aae 100644 --- a/intrinsics/probes/envreg2.llvm_nvptx.ll +++ b/intrinsics/probes/envreg2.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_f16.ll b/intrinsics/probes/ex2_approx_f16.ll index 852afe04cc..b349b0b54e 100644 --- a/intrinsics/probes/ex2_approx_f16.ll +++ b/intrinsics/probes/ex2_approx_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_f32.ll b/intrinsics/probes/ex2_approx_f32.ll index f797b78319..9a3f1b06a1 100644 --- a/intrinsics/probes/ex2_approx_f32.ll +++ b/intrinsics/probes/ex2_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_ftz_f32.ll b/intrinsics/probes/ex2_approx_ftz_f32.ll index ceb213e091..a7238b053f 100644 --- a/intrinsics/probes/ex2_approx_ftz_f32.ll +++ b/intrinsics/probes/ex2_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_mbarrier_init_release_cluster.ll b/intrinsics/probes/fence_mbarrier_init_release_cluster.ll index b5d81c86f5..1d5a973876 100644 --- a/intrinsics/probes/fence_mbarrier_init_release_cluster.ll +++ b/intrinsics/probes/fence_mbarrier_init_release_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll b/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll index e7198d54fa..dedb0fe28c 100644 --- a/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll +++ b/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll b/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll index 99048ffa79..9c76be7cb6 100644 --- a/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll +++ b/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_shared_cta.ll b/intrinsics/probes/fence_proxy_async_shared_cta.ll index 18a13e093f..fdf3e012cd 100644 --- a/intrinsics/probes/fence_proxy_async_shared_cta.ll +++ b/intrinsics/probes/fence_proxy_async_shared_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll index cb87951a35..d759939635 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll index 2590c591af..8713b3c069 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll index 62109347bc..bcfd6e6125 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll index 39960b7812..63d03fa9e1 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll index fee44c3861..12859da7a3 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll index 3e4a4205e0..3c2c7ca725 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll index 5bc283d657..8306b2a37e 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll index fcf895348a..1b9f75a27e 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_bf16x2.ll b/intrinsics/probes/fma_bf16x2.ll index 284e5042a6..d6909d3938 100644 --- a/intrinsics/probes/fma_bf16x2.ll +++ b/intrinsics/probes/fma_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_f16x2.ll b/intrinsics/probes/fma_f16x2.ll index 3b61f20968..a3282e757d 100644 --- a/intrinsics/probes/fma_f16x2.ll +++ b/intrinsics/probes/fma_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_f32x2.ll b/intrinsics/probes/fma_f32x2.ll index cced238523..d1707300d6 100644 --- a/intrinsics/probes/fma_f32x2.ll +++ b/intrinsics/probes/fma_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_f16x2.ll b/intrinsics/probes/fma_ftz_f16x2.ll index feb35e787c..9592f11f75 100644 --- a/intrinsics/probes/fma_ftz_f16x2.ll +++ b/intrinsics/probes/fma_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_f32x2.ll b/intrinsics/probes/fma_ftz_f32x2.ll index 23353bf51e..cff8d6ff8c 100644 --- a/intrinsics/probes/fma_ftz_f32x2.ll +++ b/intrinsics/probes/fma_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_relu_f16x2.ll b/intrinsics/probes/fma_ftz_relu_f16x2.ll index bdb9a10cb9..58d7011173 100644 --- a/intrinsics/probes/fma_ftz_relu_f16x2.ll +++ b/intrinsics/probes/fma_ftz_relu_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_sat_f16x2.ll b/intrinsics/probes/fma_ftz_sat_f16x2.ll index 518fd20659..01690df283 100644 --- a/intrinsics/probes/fma_ftz_sat_f16x2.ll +++ b/intrinsics/probes/fma_ftz_sat_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_relu_bf16x2.ll b/intrinsics/probes/fma_relu_bf16x2.ll index 297803280a..75f5b8ed7a 100644 --- a/intrinsics/probes/fma_relu_bf16x2.ll +++ b/intrinsics/probes/fma_relu_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_relu_f16x2.ll b/intrinsics/probes/fma_relu_f16x2.ll index 5c61da3e46..7d11b5544a 100644 --- a/intrinsics/probes/fma_relu_f16x2.ll +++ b/intrinsics/probes/fma_relu_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_f32.ll b/intrinsics/probes/fma_rm_f32.ll index 67ab5c9cd0..8512f87b0f 100644 --- a/intrinsics/probes/fma_rm_f32.ll +++ b/intrinsics/probes/fma_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_f64.ll b/intrinsics/probes/fma_rm_f64.ll index 06a55cb7c3..9b24dd7ddb 100644 --- a/intrinsics/probes/fma_rm_f64.ll +++ b/intrinsics/probes/fma_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_ftz_f32.ll b/intrinsics/probes/fma_rm_ftz_f32.ll index b9c19bbae6..48e88ceed4 100644 --- a/intrinsics/probes/fma_rm_ftz_f32.ll +++ b/intrinsics/probes/fma_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_ftz_sat_f32.ll b/intrinsics/probes/fma_rm_ftz_sat_f32.ll index acae6a3886..2595443cdb 100644 --- a/intrinsics/probes/fma_rm_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rm_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_sat_f32.ll b/intrinsics/probes/fma_rm_sat_f32.ll index b7f86d1750..27c6297977 100644 --- a/intrinsics/probes/fma_rm_sat_f32.ll +++ b/intrinsics/probes/fma_rm_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_f32.ll b/intrinsics/probes/fma_rn_f32.ll index a1dfe99091..482c642d6d 100644 --- a/intrinsics/probes/fma_rn_f32.ll +++ b/intrinsics/probes/fma_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_f64.ll b/intrinsics/probes/fma_rn_f64.ll index 8668efffed..f2fa7f1805 100644 --- a/intrinsics/probes/fma_rn_f64.ll +++ b/intrinsics/probes/fma_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_ftz_f32.ll b/intrinsics/probes/fma_rn_ftz_f32.ll index 6a09a78a77..339df3409a 100644 --- a/intrinsics/probes/fma_rn_ftz_f32.ll +++ b/intrinsics/probes/fma_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_ftz_sat_f32.ll b/intrinsics/probes/fma_rn_ftz_sat_f32.ll index 4d3af310ec..a0a96e5a6c 100644 --- a/intrinsics/probes/fma_rn_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rn_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_sat_f32.ll b/intrinsics/probes/fma_rn_sat_f32.ll index 26180f337f..7dea1deda7 100644 --- a/intrinsics/probes/fma_rn_sat_f32.ll +++ b/intrinsics/probes/fma_rn_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_f32.ll b/intrinsics/probes/fma_rp_f32.ll index 27e5e0902c..f2019eaeca 100644 --- a/intrinsics/probes/fma_rp_f32.ll +++ b/intrinsics/probes/fma_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_f64.ll b/intrinsics/probes/fma_rp_f64.ll index 4173eea479..3366dc1e1b 100644 --- a/intrinsics/probes/fma_rp_f64.ll +++ b/intrinsics/probes/fma_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_ftz_f32.ll b/intrinsics/probes/fma_rp_ftz_f32.ll index 628de79672..94dcf0c343 100644 --- a/intrinsics/probes/fma_rp_ftz_f32.ll +++ b/intrinsics/probes/fma_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_ftz_sat_f32.ll b/intrinsics/probes/fma_rp_ftz_sat_f32.ll index 4827f43d45..bd68113921 100644 --- a/intrinsics/probes/fma_rp_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rp_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_sat_f32.ll b/intrinsics/probes/fma_rp_sat_f32.ll index 0de2ba9fc5..f39ead7fbc 100644 --- a/intrinsics/probes/fma_rp_sat_f32.ll +++ b/intrinsics/probes/fma_rp_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_f32.ll b/intrinsics/probes/fma_rz_f32.ll index aff6444e88..a92743f9d0 100644 --- a/intrinsics/probes/fma_rz_f32.ll +++ b/intrinsics/probes/fma_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_f64.ll b/intrinsics/probes/fma_rz_f64.ll index 6386a3fc94..b68b97c09b 100644 --- a/intrinsics/probes/fma_rz_f64.ll +++ b/intrinsics/probes/fma_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_ftz_f32.ll b/intrinsics/probes/fma_rz_ftz_f32.ll index f3c855f242..f16fcdd879 100644 --- a/intrinsics/probes/fma_rz_ftz_f32.ll +++ b/intrinsics/probes/fma_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_ftz_sat_f32.ll b/intrinsics/probes/fma_rz_ftz_sat_f32.ll index 0a702395cd..c33f317692 100644 --- a/intrinsics/probes/fma_rz_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rz_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_sat_f32.ll b/intrinsics/probes/fma_rz_sat_f32.ll index b232b324aa..4dd11f2255 100644 --- a/intrinsics/probes/fma_rz_sat_f32.ll +++ b/intrinsics/probes/fma_rz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_sat_f16x2.ll b/intrinsics/probes/fma_sat_f16x2.ll index 2a77d8edfc..c7f16702eb 100644 --- a/intrinsics/probes/fma_sat_f16x2.ll +++ b/intrinsics/probes/fma_sat_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/globaltimer.lib_nvvm.ll b/intrinsics/probes/globaltimer.lib_nvvm.ll index 7bfb5d0891..0e201e4d30 100644 --- a/intrinsics/probes/globaltimer.lib_nvvm.ll +++ b/intrinsics/probes/globaltimer.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/globaltimer.llvm_nvptx.ll b/intrinsics/probes/globaltimer.llvm_nvptx.ll index 0005508ee6..7e8a29d2e4 100644 --- a/intrinsics/probes/globaltimer.llvm_nvptx.ll +++ b/intrinsics/probes/globaltimer.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dependency_launch_dependents.ll b/intrinsics/probes/grid_dependency_launch_dependents.ll index 2b4efe5130..6b7bde10f0 100644 --- a/intrinsics/probes/grid_dependency_launch_dependents.ll +++ b/intrinsics/probes/grid_dependency_launch_dependents.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dependency_wait.ll b/intrinsics/probes/grid_dependency_wait.ll index f211708998..e4e2104d00 100644 --- a/intrinsics/probes/grid_dependency_wait.ll +++ b/intrinsics/probes/grid_dependency_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_x.ll b/intrinsics/probes/grid_dim_x.ll index 142fbda1db..343b8b0f43 100644 --- a/intrinsics/probes/grid_dim_x.ll +++ b/intrinsics/probes/grid_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_y.ll b/intrinsics/probes/grid_dim_y.ll index 86b4d069e1..94aceb5bef 100644 --- a/intrinsics/probes/grid_dim_y.ll +++ b/intrinsics/probes/grid_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_z.ll b/intrinsics/probes/grid_dim_z.ll index 7120224ea4..53b0fce13d 100644 --- a/intrinsics/probes/grid_dim_z.ll +++ b/intrinsics/probes/grid_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/gridid.lib_nvvm.ll b/intrinsics/probes/gridid.lib_nvvm.ll index 1bb33b131c..538ff1c488 100644 --- a/intrinsics/probes/gridid.lib_nvvm.ll +++ b/intrinsics/probes/gridid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/gridid.llvm_nvptx.ll b/intrinsics/probes/gridid.llvm_nvptx.ll index b09e500901..d534b3f0cf 100644 --- a/intrinsics/probes/gridid.llvm_nvptx.ll +++ b/intrinsics/probes/gridid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lane_id.ll b/intrinsics/probes/lane_id.ll index 70f717b189..7d247878c1 100644 --- a/intrinsics/probes/lane_id.ll +++ b/intrinsics/probes/lane_id.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_eq.ll b/intrinsics/probes/lanemask_eq.ll index 6e1614f64b..00138014c9 100644 --- a/intrinsics/probes/lanemask_eq.ll +++ b/intrinsics/probes/lanemask_eq.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_ge.ll b/intrinsics/probes/lanemask_ge.ll index 033ca12544..2ebf95d1ba 100644 --- a/intrinsics/probes/lanemask_ge.ll +++ b/intrinsics/probes/lanemask_ge.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_gt.ll b/intrinsics/probes/lanemask_gt.ll index 8b5d188db0..e8db3c8fa8 100644 --- a/intrinsics/probes/lanemask_gt.ll +++ b/intrinsics/probes/lanemask_gt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_le.ll b/intrinsics/probes/lanemask_le.ll index d0cfbbe118..55a505db3e 100644 --- a/intrinsics/probes/lanemask_le.ll +++ b/intrinsics/probes/lanemask_le.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_lt.ll b/intrinsics/probes/lanemask_lt.ll index f0f2ffb419..62d75dc764 100644 --- a/intrinsics/probes/lanemask_lt.ll +++ b/intrinsics/probes/lanemask_lt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll index 822e07214c..28e7b4fcaa 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll index 0217e47533..0cf573e489 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll index 89fdf1c396..c50c963a9a 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll index 724bf6e9f0..37eb6f73f8 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll index 6c4d2ae7b2..8491cbc23b 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll index 4e0d74117a..2ed76cad94 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll index 2c03876471..1df1ba8c59 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll index b05030260b..cd0c066b02 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll index 2622a59bcb..44dbb189c0 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll index cf2e67d8c7..172fbb6b99 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll index 0c74ffd67b..41dade35fc 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll index 584f3e5cbe..f25fd05e59 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll index 81c8c73887..41ecb108e3 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll index f77546bcc4..a857a1e019 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll index 4a5265c20c..04c7aa23b9 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll index 821155ea4e..6c7378e598 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll index 83af94909b..1afaf88b9d 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll index ee4cb93424..d2aed9031f 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lg2_approx_f32.ll b/intrinsics/probes/lg2_approx_f32.ll index 70de389ec1..bea1bca816 100644 --- a/intrinsics/probes/lg2_approx_f32.ll +++ b/intrinsics/probes/lg2_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lg2_approx_ftz_f32.ll b/intrinsics/probes/lg2_approx_ftz_f32.ll index bc3b938a31..d0a6fbf0f9 100644 --- a/intrinsics/probes/lg2_approx_ftz_f32.ll +++ b/intrinsics/probes/lg2_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/map_shared_rank.ll b/intrinsics/probes/map_shared_rank.ll index a1b3478cd5..47a23172e3 100644 --- a/intrinsics/probes/map_shared_rank.ll +++ b/intrinsics/probes/map_shared_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_all_i64_sync.ll b/intrinsics/probes/match_all_i64_sync.ll index 2029076adb..19a634eb5a 100644 --- a/intrinsics/probes/match_all_i64_sync.ll +++ b/intrinsics/probes/match_all_i64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_all_sync.ll b/intrinsics/probes/match_all_sync.ll index 239996e5fc..95b63bf26c 100644 --- a/intrinsics/probes/match_all_sync.ll +++ b/intrinsics/probes/match_all_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_any_i64_sync.ll b/intrinsics/probes/match_any_i64_sync.ll index c32b552c86..7fc4e72ce1 100644 --- a/intrinsics/probes/match_any_i64_sync.ll +++ b/intrinsics/probes/match_any_i64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_any_sync.ll b/intrinsics/probes/match_any_sync.ll index bda4562504..341eadbf1d 100644 --- a/intrinsics/probes/match_any_sync.ll +++ b/intrinsics/probes/match_any_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_bf16.ll b/intrinsics/probes/max_bf16.ll index 63a5f2a234..fe8336e91b 100644 --- a/intrinsics/probes/max_bf16.ll +++ b/intrinsics/probes/max_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_bf16x2.ll b/intrinsics/probes/max_bf16x2.ll index b530b70941..ea003438d7 100644 --- a/intrinsics/probes/max_bf16x2.ll +++ b/intrinsics/probes/max_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_f16.ll b/intrinsics/probes/max_f16.ll index 23e7f2edc8..13a9fd521d 100644 --- a/intrinsics/probes/max_f16.ll +++ b/intrinsics/probes/max_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_f16x2.ll b/intrinsics/probes/max_f16x2.ll index ed84502469..022fd4bfbe 100644 --- a/intrinsics/probes/max_f16x2.ll +++ b/intrinsics/probes/max_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_f16.ll b/intrinsics/probes/max_ftz_f16.ll index ae2b090272..5b07edb68b 100644 --- a/intrinsics/probes/max_ftz_f16.ll +++ b/intrinsics/probes/max_ftz_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_f16x2.ll b/intrinsics/probes/max_ftz_f16x2.ll index f9649e211a..057ab56fee 100644 --- a/intrinsics/probes/max_ftz_f16x2.ll +++ b/intrinsics/probes/max_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_f16.ll b/intrinsics/probes/max_ftz_nan_f16.ll index 579dd44669..7001566e36 100644 --- a/intrinsics/probes/max_ftz_nan_f16.ll +++ b/intrinsics/probes/max_ftz_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_f16x2.ll b/intrinsics/probes/max_ftz_nan_f16x2.ll index 1ddc27ad52..cbd7f3e9bf 100644 --- a/intrinsics/probes/max_ftz_nan_f16x2.ll +++ b/intrinsics/probes/max_ftz_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll index 0565a02c22..43230522f3 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll index 20fe8ab942..95384e2bf3 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll index e888ca247c..6eab78127c 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f16.ll b/intrinsics/probes/max_ftz_xorsign_abs_f16.ll index dc9a9fa6ad..15eec92890 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll b/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll index 2baa7c8444..2118f3d88f 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f32.ll b/intrinsics/probes/max_ftz_xorsign_abs_f32.ll index 5a29129a71..fcb22c694f 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_bf16.ll b/intrinsics/probes/max_nan_bf16.ll index a79d5371c7..f9f274d627 100644 --- a/intrinsics/probes/max_nan_bf16.ll +++ b/intrinsics/probes/max_nan_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_bf16x2.ll b/intrinsics/probes/max_nan_bf16x2.ll index a85efcd1d3..7827531d1a 100644 --- a/intrinsics/probes/max_nan_bf16x2.ll +++ b/intrinsics/probes/max_nan_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_f16.ll b/intrinsics/probes/max_nan_f16.ll index a6e3f2f15c..f28c3996bd 100644 --- a/intrinsics/probes/max_nan_f16.ll +++ b/intrinsics/probes/max_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_f16x2.ll b/intrinsics/probes/max_nan_f16x2.ll index 754ebaf608..079e47573c 100644 --- a/intrinsics/probes/max_nan_f16x2.ll +++ b/intrinsics/probes/max_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_bf16.ll b/intrinsics/probes/max_nan_xorsign_abs_bf16.ll index 6fa76cbde2..470c85d7df 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_bf16.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll b/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll index 90900103f5..04113f876e 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f16.ll b/intrinsics/probes/max_nan_xorsign_abs_f16.ll index b27fb74066..7bd1c5ff0b 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll index 1434e9204a..e1ef45fea4 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f32.ll b/intrinsics/probes/max_nan_xorsign_abs_f32.ll index 94aa0cd1b2..6fd1e23793 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_relu_s16x2.ll b/intrinsics/probes/max_relu_s16x2.ll index b782fddacc..dcb8aa6bf2 100644 --- a/intrinsics/probes/max_relu_s16x2.ll +++ b/intrinsics/probes/max_relu_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_relu_s32.ll b/intrinsics/probes/max_relu_s32.ll index 92d95c67c2..3862728f69 100644 --- a/intrinsics/probes/max_relu_s32.ll +++ b/intrinsics/probes/max_relu_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_s16x2.ll b/intrinsics/probes/max_s16x2.ll index d6144832cd..a906011a50 100644 --- a/intrinsics/probes/max_s16x2.ll +++ b/intrinsics/probes/max_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_u16x2.ll b/intrinsics/probes/max_u16x2.ll index 19e5bf16ef..41050f345e 100644 --- a/intrinsics/probes/max_u16x2.ll +++ b/intrinsics/probes/max_u16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_bf16.ll b/intrinsics/probes/max_xorsign_abs_bf16.ll index c6826abbb7..34e9abc3ce 100644 --- a/intrinsics/probes/max_xorsign_abs_bf16.ll +++ b/intrinsics/probes/max_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_bf16x2.ll b/intrinsics/probes/max_xorsign_abs_bf16x2.ll index 1583e2e621..784b2d785e 100644 --- a/intrinsics/probes/max_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/max_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f16.ll b/intrinsics/probes/max_xorsign_abs_f16.ll index 3c2bacff7b..1b8ad29e96 100644 --- a/intrinsics/probes/max_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f16x2.ll b/intrinsics/probes/max_xorsign_abs_f16x2.ll index 1f41a08d14..594133c8dd 100644 --- a/intrinsics/probes/max_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f32.ll b/intrinsics/probes/max_xorsign_abs_f32.ll index 2c352def86..9a62bb7f5b 100644 --- a/intrinsics/probes/max_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive.ll b/intrinsics/probes/mbarrier_arrive.ll index c309c19d34..812b544dad 100644 --- a/intrinsics/probes/mbarrier_arrive.ll +++ b/intrinsics/probes/mbarrier_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_cluster.ll b/intrinsics/probes/mbarrier_arrive_cluster.ll index 7ef3810734..1bc65e7ac3 100644 --- a/intrinsics/probes/mbarrier_arrive_cluster.ll +++ b/intrinsics/probes/mbarrier_arrive_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_expect_tx.ll b/intrinsics/probes/mbarrier_arrive_expect_tx.ll index 1015159f62..bc0b83b1a2 100644 --- a/intrinsics/probes/mbarrier_arrive_expect_tx.ll +++ b/intrinsics/probes/mbarrier_arrive_expect_tx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll b/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll index 776e0f2f26..cfa8bdced0 100644 --- a/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll +++ b/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_init.ll b/intrinsics/probes/mbarrier_init.ll index a55f31e1ae..ca0597355b 100644 --- a/intrinsics/probes/mbarrier_init.ll +++ b/intrinsics/probes/mbarrier_init.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_inval.ll b/intrinsics/probes/mbarrier_inval.ll index ab8453ab63..86ecca238d 100644 --- a/intrinsics/probes/mbarrier_inval.ll +++ b/intrinsics/probes/mbarrier_inval.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_test_wait.ll b/intrinsics/probes/mbarrier_test_wait.ll index a794ea541b..45165e6905 100644 --- a/intrinsics/probes/mbarrier_test_wait.ll +++ b/intrinsics/probes/mbarrier_test_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait.ll b/intrinsics/probes/mbarrier_try_wait.ll index d20544ae9f..1d8b1c2b7c 100644 --- a/intrinsics/probes/mbarrier_try_wait.ll +++ b/intrinsics/probes/mbarrier_try_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait_parity.ll b/intrinsics/probes/mbarrier_try_wait_parity.ll index 13aa861d8b..2701f0ba92 100644 --- a/intrinsics/probes/mbarrier_try_wait_parity.ll +++ b/intrinsics/probes/mbarrier_try_wait_parity.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll b/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll index e85d16233b..138697eaea 100644 --- a/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll +++ b/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_bf16.ll b/intrinsics/probes/min_bf16.ll index b7f2be5388..9418ae038e 100644 --- a/intrinsics/probes/min_bf16.ll +++ b/intrinsics/probes/min_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_bf16x2.ll b/intrinsics/probes/min_bf16x2.ll index 97a1b9466a..05308fee3e 100644 --- a/intrinsics/probes/min_bf16x2.ll +++ b/intrinsics/probes/min_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_f16.ll b/intrinsics/probes/min_f16.ll index c7046bb0e4..6f43194cd3 100644 --- a/intrinsics/probes/min_f16.ll +++ b/intrinsics/probes/min_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_f16x2.ll b/intrinsics/probes/min_f16x2.ll index ddeb11ac96..314038d475 100644 --- a/intrinsics/probes/min_f16x2.ll +++ b/intrinsics/probes/min_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_f16.ll b/intrinsics/probes/min_ftz_f16.ll index ee7521f182..ed6c06afb4 100644 --- a/intrinsics/probes/min_ftz_f16.ll +++ b/intrinsics/probes/min_ftz_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_f16x2.ll b/intrinsics/probes/min_ftz_f16x2.ll index 94e9ab1115..4f98f76ed1 100644 --- a/intrinsics/probes/min_ftz_f16x2.ll +++ b/intrinsics/probes/min_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_f16.ll b/intrinsics/probes/min_ftz_nan_f16.ll index 5e71a4cf23..a9b6c2afa5 100644 --- a/intrinsics/probes/min_ftz_nan_f16.ll +++ b/intrinsics/probes/min_ftz_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_f16x2.ll b/intrinsics/probes/min_ftz_nan_f16x2.ll index 446f7abe08..c83fc9dbeb 100644 --- a/intrinsics/probes/min_ftz_nan_f16x2.ll +++ b/intrinsics/probes/min_ftz_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll index 494f020b5b..9f539717db 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll index f9171d1ee3..47d1485bae 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll index 687bc9939d..8d2e1ab809 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f16.ll b/intrinsics/probes/min_ftz_xorsign_abs_f16.ll index d5f61225dc..df553bd8dd 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll b/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll index b4ea52b194..5cdec6b102 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f32.ll b/intrinsics/probes/min_ftz_xorsign_abs_f32.ll index feee2b7d7f..a6fb8808a4 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_bf16.ll b/intrinsics/probes/min_nan_bf16.ll index 7b77b05d41..7abba0f3e3 100644 --- a/intrinsics/probes/min_nan_bf16.ll +++ b/intrinsics/probes/min_nan_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_bf16x2.ll b/intrinsics/probes/min_nan_bf16x2.ll index f0c28799a3..b471fb1b36 100644 --- a/intrinsics/probes/min_nan_bf16x2.ll +++ b/intrinsics/probes/min_nan_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_f16.ll b/intrinsics/probes/min_nan_f16.ll index 93537ef7cc..1cfd453d63 100644 --- a/intrinsics/probes/min_nan_f16.ll +++ b/intrinsics/probes/min_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_f16x2.ll b/intrinsics/probes/min_nan_f16x2.ll index c533d3cc64..ac093967da 100644 --- a/intrinsics/probes/min_nan_f16x2.ll +++ b/intrinsics/probes/min_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_bf16.ll b/intrinsics/probes/min_nan_xorsign_abs_bf16.ll index 01fc528be8..4d330ddf60 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_bf16.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll b/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll index 8e0fde86e1..b1e322cec1 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f16.ll b/intrinsics/probes/min_nan_xorsign_abs_f16.ll index f173648154..a5e981124e 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll index 119c378fd8..ed8c199cbb 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f32.ll b/intrinsics/probes/min_nan_xorsign_abs_f32.ll index ba351a73a4..ecb73bf460 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_relu_s16x2.ll b/intrinsics/probes/min_relu_s16x2.ll index 372bb00c9a..ba5c6ff27d 100644 --- a/intrinsics/probes/min_relu_s16x2.ll +++ b/intrinsics/probes/min_relu_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_relu_s32.ll b/intrinsics/probes/min_relu_s32.ll index 768f6da6c3..bf6c29628c 100644 --- a/intrinsics/probes/min_relu_s32.ll +++ b/intrinsics/probes/min_relu_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_s16x2.ll b/intrinsics/probes/min_s16x2.ll index 1e54adab64..e55b538b76 100644 --- a/intrinsics/probes/min_s16x2.ll +++ b/intrinsics/probes/min_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_u16x2.ll b/intrinsics/probes/min_u16x2.ll index 68e18b28d9..2412f58717 100644 --- a/intrinsics/probes/min_u16x2.ll +++ b/intrinsics/probes/min_u16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_bf16.ll b/intrinsics/probes/min_xorsign_abs_bf16.ll index c9a6b969fe..16f9232ba8 100644 --- a/intrinsics/probes/min_xorsign_abs_bf16.ll +++ b/intrinsics/probes/min_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_bf16x2.ll b/intrinsics/probes/min_xorsign_abs_bf16x2.ll index e64cfb8c53..f9536a2e30 100644 --- a/intrinsics/probes/min_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/min_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f16.ll b/intrinsics/probes/min_xorsign_abs_f16.ll index 0d5cf3a30b..266e93aae9 100644 --- a/intrinsics/probes/min_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f16x2.ll b/intrinsics/probes/min_xorsign_abs_f16x2.ll index 0b73dd0706..f232d1d485 100644 --- a/intrinsics/probes/min_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f32.ll b/intrinsics/probes/min_xorsign_abs_f32.ll index c8d01aacbf..738fe1d28f 100644 --- a/intrinsics/probes/min_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll b/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll index 098a29bd91..9e62d21eb8 100644 --- a/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll index cad12c9c63..c08e480bf9 100644 --- a/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f16_f16.ll b/intrinsics/probes/mma_m16n8k16_f16_f16.ll index 331a947f88..453f5c0c56 100644 --- a/intrinsics/probes/mma_m16n8k16_f16_f16.ll +++ b/intrinsics/probes/mma_m16n8k16_f16_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f32_bf16.ll b/intrinsics/probes/mma_m16n8k16_f32_bf16.ll index 0b5b27e628..e4ef080226 100644 --- a/intrinsics/probes/mma_m16n8k16_f32_bf16.ll +++ b/intrinsics/probes/mma_m16n8k16_f32_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f32_f16.ll b/intrinsics/probes/mma_m16n8k16_f32_f16.ll index 912ca70215..47b6fdb9b2 100644 --- a/intrinsics/probes/mma_m16n8k16_f32_f16.ll +++ b/intrinsics/probes/mma_m16n8k16_f32_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll index 9f266e94a4..2de6dc2e57 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll index 369c8b490f..e753a9b7b5 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll index c1f0642883..d280bf6e55 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll index d9641582ac..f94facd4b6 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll index 3f1e4dea67..c3d2fccb52 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll index 569bae25d9..1c78c29d20 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll index 59f77af8b9..d465642ab7 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll index 1ac1256e87..0c4d888e0e 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8.ll b/intrinsics/probes/mma_m16n8k16_s32_s8.ll index 9584a4a766..679eef9ff0 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll index 289aed541a..f2e5a9bae7 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll index a4023bba4e..fc999ca787 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll index 9f98fe4e75..5b6235deeb 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8.ll b/intrinsics/probes/mma_m16n8k16_s32_u8.ll index 962e73e7e6..e62b4aee62 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll index e90a6dd437..a97a3b8529 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll index 2ea6035619..5208f101a6 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll index 58f686d033..a4a50d86ac 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll b/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll index c66cb1067a..f84ab96a5c 100644 --- a/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll index 083724501b..5a26b4e0a0 100644 --- a/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll index 1201d98b79..1f06e0d6b4 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll index 3ce2aa6b1a..8dbf112094 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll index e50d1133ac..5d219264ee 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll index dba6bc9dba..a22bda1f0c 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll index b5bd0390b8..8b0cc453ca 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll index df739fb59c..3443552ecc 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll index c2618485eb..b7b82c24ad 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll index 25b636aa0a..200850114d 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll index 9725971a88..5501ea9ab1 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll index e37752c142..0b7ddf7ead 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll index 4c01813b47..434f11c469 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll index 10c93dce4d..eefde9d925 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll index 4a1ca8af1f..2b785c57a4 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll index dc623135d3..300f385a29 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll index dff66ad715..ca62230a91 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll index 64984ebbc0..f49a0ee95a 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll index a98fcd21a0..0d35473eef 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll index fdce26febd..4de3e423c6 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll index 85b753c3bf..926ed81052 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll index 4a183c1111..90fd21ba6a 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll index c4c743bc7c..62c472efcc 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll index cf0e61868a..a571f6b4a8 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll index 10725b12f8..846c0a0490 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll index bfc601386a..7cd666c395 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll index 47988c6bd5..f774bba103 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll index 695e9e845e..2638b2a70b 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll index b2fc83b3fa..68b9561d8c 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll index 0a74311766..cb92d741c6 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll index 440a2d6fa6..2369c278b6 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll index 97bcea9449..49b1650617 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll index eb3a794062..a308681933 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll index 4df700b7fe..058e7b1c71 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll index 6ebfdd8e2f..c36a799cb6 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll index 96cc40ea4e..0df91cfa1d 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll index b3fd53700b..24aa20cbe6 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll index 1425aa6654..a57858a316 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll index f6745bebfc..ca4ac334fc 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll index 4fac0773d2..b315777713 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll index af43930245..3437e4a556 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll index eed2f6d914..73cdc4dadb 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll index 0252d7aaf3..5abe1d2f35 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll index 0e876541e5..5889c56b80 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll index 551484fa74..3b109a714b 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll index 8e88d4ee0b..5542473197 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll index bf4f524ffc..d69b824871 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll index ed0051e0f3..a9e0b871b8 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll index 426050f13e..e0a0f7823e 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll index 0ee30682d9..a853457615 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll index add8778326..3ab8311a1e 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll index 7fecd784a2..cc1056f2ce 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll index bb8e8c6606..4b2f5b1751 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll index f5d12ccfa1..7b3eb550b5 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll index 0901984bc6..9f0e84b2f6 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll index 6ca7abc3d9..ed96abd477 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll index 2d2bdee4e5..14ad8885d5 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll index 85741eb9d0..d34fd6f403 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll index 62d84075a3..64f038b7a0 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll index e4c7918aff..922705320b 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll index 2411ef1ff8..d46e3b53fd 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll index 19be1624e6..2c43f427f6 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll index 671ed0c4fc..c4073ec41b 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll index fb7f155097..5c5b69b37c 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll index d858c222dc..edc6a9bff7 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll index c999b3e01e..faf86f27f5 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll index 0f3d1bd78f..86ea27da3a 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll index dca5d72e7c..38ed851c0c 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll index d41281874c..f3147dfdc5 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll index 54988d023b..7f20654e60 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll index 947e00aefe..43eba7ee66 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll index c7284c7394..9ec2bb9893 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll index 9c25b1995c..1c1fba18f0 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll index cec3e5665a..aa720f76a3 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll index 03560a289c..ddcc3fe204 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll index e89129800d..dff71176ff 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll index 0d8adf17ea..fc17a7635d 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll index c6905f3ea7..90ad49bfe9 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll index 1aef9e1764..58d7a95bd1 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll index a8ba673439..d9980f42ab 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll index 1edfd5ecd4..e5acd27cac 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll index 5240ef6e2f..f740cf0caa 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll index ae5391e5db..28ae2ce0fe 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll index 7ae8cb4475..469a8b45cd 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll index 26b448b9cd..5a26a940f2 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4.ll b/intrinsics/probes/mma_m16n8k32_s32_s4.ll index 94acd9367f..41c1a53a55 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll index 193ee6e705..39b954eff2 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll index e94f5154fb..a0a86aa7cb 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll index 5aa93512fb..2d48bcd222 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_m16n8k32_s32_s8.ll index 6da28ceb85..78cda04b8c 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll index fe9ae0fd9c..44863e7267 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll index c39538ab76..a9413d1147 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll index 8a7f4602b7..5b2745ed3c 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4.ll b/intrinsics/probes/mma_m16n8k32_s32_u4.ll index ff1d27ee4d..6043905437 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll index f208eb3e9d..d2a56d30f7 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll index c0f5b72ebe..c8128f762a 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll index 2a44100903..1e66dda645 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_m16n8k32_s32_u8.ll index a5ef8b49d0..da93473494 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll index c403efce77..aecbb6655f 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll index 2e616a18ed..7fafd5a362 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll index 331e97746f..2cd234df4a 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k4_f32_tf32.ll b/intrinsics/probes/mma_m16n8k4_f32_tf32.ll index fb91f45aca..893776dd11 100644 --- a/intrinsics/probes/mma_m16n8k4_f32_tf32.ll +++ b/intrinsics/probes/mma_m16n8k4_f32_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_m16n8k64_s32_s4.ll index 0f6f972329..b615a63e2e 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll index 1a695e3fa9..32eabac6a4 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll index 046ffbcd24..71e33f799c 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll index dd9d7b25bd..048a4388d5 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_m16n8k64_s32_u4.ll index b21a1f4184..7ad488458f 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll index a5c660e8b1..a073c4cddd 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll index 1e89b6c2d7..1d95970e1b 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll index 1165f996f2..7998e2b4fc 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f16_f16.ll b/intrinsics/probes/mma_m16n8k8_f16_f16.ll index 4aa4681833..273df2e868 100644 --- a/intrinsics/probes/mma_m16n8k8_f16_f16.ll +++ b/intrinsics/probes/mma_m16n8k8_f16_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_bf16.ll b/intrinsics/probes/mma_m16n8k8_f32_bf16.ll index 5ce721539e..7b61c45e54 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_bf16.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_f16.ll b/intrinsics/probes/mma_m16n8k8_f32_f16.ll index 4ea22f54b5..7f575af76d 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_f16.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_tf32.ll b/intrinsics/probes/mma_m16n8k8_f32_tf32.ll index 33a0d02b9d..2e57642567 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_tf32.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll b/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll index e548cfbab1..c144ee0dd0 100644 --- a/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll index 3ebf8175ef..3b4e78cb51 100644 --- a/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8.ll b/intrinsics/probes/mma_m8n8k16_s32_s8.ll index 9e2515a42a..1ba0912e9e 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll index 7277626c04..9668dba974 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll index 089ac7903a..072492fc83 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll index fcae411cac..e9e5b79f36 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8.ll b/intrinsics/probes/mma_m8n8k16_s32_u8.ll index c44bd2ba94..51c744bdfc 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll index 3a0872413e..65a9723d88 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll index 13626a31b8..7c8f2be17b 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll index 7abc4ddab7..260d0a162a 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4.ll b/intrinsics/probes/mma_m8n8k32_s32_s4.ll index 86751eb923..43d5adb9f3 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll index 03fefb23fd..c67e49c247 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll index 5bf2774886..c23d047c78 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll index 4589100894..80958df336 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4.ll b/intrinsics/probes/mma_m8n8k32_s32_u4.ll index 5ca8b69950..683c524bdd 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll index ae539d3a41..16bfbad858 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll index 8e0a6edfdb..2a6d7f8f85 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll index 8756eec78d..01e8bd64f2 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k4_f64.ll b/intrinsics/probes/mma_m8n8k4_f64.ll index 3f03ab256c..2942231dfc 100644 --- a/intrinsics/probes/mma_m8n8k4_f64.ll +++ b/intrinsics/probes/mma_m8n8k4_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll index c8c45b7eea..18333bce92 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll index 34b025b077..7ffaff1ff7 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll index 5b75bccb2a..94078e592c 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll index eb97f53f20..aa7c2c8576 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll index c85c408e4a..ddb94dc615 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll index b5efd7ccd6..3acfe03695 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll index 87cb1c5ff2..b5bc486f2c 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll index 76a308b781..00e3290430 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll index 405f0e1f87..cd396a8b45 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll index 3d440c313f..0e28719d3e 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll index ba501cdd35..8bf57d0462 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll index 9ba7148aa9..42c0959f2b 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll index af95fef139..d527b7b781 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll index 6b594df1ec..e749cc7a04 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll index 8fd1499735..03cea41b8a 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll index 5bbda242b2..ba932b8223 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll index 06ac9b3268..a668c46d0c 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll index dd7576804f..dab7342dfe 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll index 68c2b8e2b8..33c6e33567 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll index 483772177f..608f26ef91 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll index d927dde5d9..67b8f7462c 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll index 1fce279274..30fc48f69b 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll index fe2cdb9134..711d9f662d 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll index 592365e3de..123ce12857 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll index fe6835aff6..0fae98426e 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll index b9baca8cc7..8fa4f58583 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll index 7f4d78b093..851b5af553 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll index 407141d43d..f97476ecff 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll index 1b1c999cd7..b58205ea1b 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll index 605e574b0c..61b7bfb2c1 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll index 360524961e..8ba6f5ff75 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll index 20d845819e..0abc6394ce 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll index 0f1089ecbc..2adfbd4448 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll index 212bf04b3e..5f3231a97d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll index b59af08756..9239a788fd 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll index 3f901ce70a..eb869c9f2e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll index 6b1ffa0ee2..ab4c42057e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll index 0095e3eb1d..205de81d2a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll index abddf99e68..c8ff2803c6 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll index 73f119da17..5c61435d90 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll new file mode 100644 index 0000000000..d8bf309bae --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll @@ -0,0 +1,26 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k16_f16_f16_selector_0(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6, $7}, {$2, $3}, $8, $9;", "=r,=r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 0) #0 + ret { i32, i32 } %result +} +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k16_f16_f16_selector_1(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6, $7}, {$2, $3}, $8, $9;", "=r,=r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 1) #0 + ret { i32, i32 } %result +} +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k16_f16_f16_selector_2(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6, $7}, {$2, $3}, $8, $9;", "=r,=r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 2) #0 + ret { i32, i32 } %result +} +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k16_f16_f16_selector_3(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6, $7}, {$2, $3}, $8, $9;", "=r,=r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 3) #0 + ret { i32, i32 } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll new file mode 100644 index 0000000000..790f3c6ecd --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll @@ -0,0 +1,26 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_bf16_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_bf16_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_bf16_selector_2(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 2) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_bf16_selector_3(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 3) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll new file mode 100644 index 0000000000..20a16046f6 --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll @@ -0,0 +1,26 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_f16_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_f16_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_f16_selector_2(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 2) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_f16_selector_3(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 3) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll new file mode 100644 index 0000000000..caa5b60714 --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll @@ -0,0 +1,18 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_tf32_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_tf32_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll new file mode 100644 index 0000000000..2ab771ade4 --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll @@ -0,0 +1,18 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k32_f16_f16_selector_0(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;", "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 0) #0 + ret { i32, i32 } %result +} +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k32_f16_f16_selector_1(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;", "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 1) #0 + ret { i32, i32 } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll new file mode 100644 index 0000000000..41498248cd --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll @@ -0,0 +1,18 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k32_f32_bf16_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k32_f32_bf16_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll new file mode 100644 index 0000000000..560a642062 --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll @@ -0,0 +1,18 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k32_f32_f16_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k32_f32_f16_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll index 23c69a2b3a..d0726c08a7 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll index 19832e3566..da039e975f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll index 6558ec6275..86a2fefa39 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll index 4ebaa8661a..79bd0a3faf 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll index cfb3dd1e11..b910376094 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll index f1f98c2fd8..2a7a27bb3d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll index 2ba3b257a0..91739fa237 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll index c97903baa6..2c0e6abea0 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll index 6839cdcf6f..e363f1b45c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll index 593fa1d363..1091bf9c78 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll index 9b8423de98..c819c39e81 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll index 77a10bb65c..de4cb989dc 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll index 9952880b2e..776f8f74b5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll index 2b558adf0d..91c9fac8bf 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll index 67bcec2d9d..0266ab7a54 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll index 0d35ebb79c..482a4720f7 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll index 92a9dac9d5..ce9d0a1bda 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll index 11ce52ecc2..b2e867a1ca 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll index 3d689cd4ba..00c1344735 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll index d2d8275b1b..a4fd87e088 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll index a1cf0b2c51..1998d39aa2 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll index 370034bc6d..33951a71b8 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll index a7de8ca7a7..818c187ee8 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll index 61b43919f2..f97e5eba95 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll index 37aa00b466..0977e00d51 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll index af544b2a90..5fb712650a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll index 631feb988d..68fb590108 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll index e7159e1f4c..554dd67bbd 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll index f81b4541bf..3c3b813a26 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll index 8cc07c3ed2..cd6829add3 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll index 0a0a1b517d..992e398e1c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll index 0b7bddc1cb..65b3287802 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll index a55e7c6d5e..8503224c23 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll index ca856095fb..b8a9c0b4f7 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll index 3389ff0e3d..fa8affa52b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll index 5768a1af98..80e3610f1a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll index 11fd1af2f4..c1ba304648 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll index 1ed5ead7b2..a7bc414791 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll index 8890c8669a..e04fc0d4c0 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll index d295b54e92..3b96d65cad 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll index d7d3e62856..d35e05e1d2 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll index 69b7c029b8..bd32fc589d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll index eeb11204df..5e47df8e05 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll index 000be5edd7..f28939cc99 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll index bb0ef55641..945eb412d5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll index 99d545ff1e..10b8494f2c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll index 7bc56bc46f..c1f0da385d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll index 2ab1ec7431..86a67d036a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll index 0938c06f0b..ed2a5f0087 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll index 853c3a0b24..6bea2e42ff 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll index 46858f0abd..b6e507974d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll index fbe0c06717..ebfb33f429 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll index 2a6f771857..9858438582 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll index 74af7ded9d..11696d9815 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll index ca78774d6b..32e4610819 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll index 26b4bd239b..c548e21caa 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll index 142210030e..28015c188c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll index 80a97b5fe0..30aabae5ba 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll index aa50191bd8..5410db6fcd 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll index 0ecb389130..fb5c81d688 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll index a5e89de89f..b18f70d932 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll index fb6fb46c8f..e503b45d9a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll index 88d07f0272..b38ad60a13 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll index e046529add..0b881a2749 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll index fcbd6f6539..72d230768e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll index 85f012259e..68afb06383 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll index 0cea2acf72..8383627cf8 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll index 77315e6958..622e6c031f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll index 2d0bd1990c..81e1a6345e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll index 7ed072ff64..bec156e306 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll index 614005667a..53d81a7fe1 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll index 5c6961e23d..e2254fa7ad 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll index 0ae2b379cb..0b7e6bf528 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll index 6189d6dff0..6d10cedb67 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll new file mode 100644 index 0000000000..5ce17bd0c8 --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll @@ -0,0 +1,26 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k8_f32_tf32_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k8_f32_tf32_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k8_f32_tf32_selector_2(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 2) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k8_f32_tf32_selector_3(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 3) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/movmatrix_trans_b16.ll b/intrinsics/probes/movmatrix_trans_b16.ll index 3f30143b08..cf3ec917d7 100644 --- a/intrinsics/probes/movmatrix_trans_b16.ll +++ b/intrinsics/probes/movmatrix_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_bf16x2.ll b/intrinsics/probes/mul_bf16x2.ll index 9d5f7fb8ba..3591e8ed24 100644 --- a/intrinsics/probes/mul_bf16x2.ll +++ b/intrinsics/probes/mul_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_f16x2.ll b/intrinsics/probes/mul_f16x2.ll index db16cd9bb1..3b5b3a01ad 100644 --- a/intrinsics/probes/mul_f16x2.ll +++ b/intrinsics/probes/mul_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_f32x2.ll b/intrinsics/probes/mul_f32x2.ll index 45df994b56..24d1bb27e2 100644 --- a/intrinsics/probes/mul_f32x2.ll +++ b/intrinsics/probes/mul_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_ftz_f32x2.ll b/intrinsics/probes/mul_ftz_f32x2.ll index 59ebb00b19..84de580269 100644 --- a/intrinsics/probes/mul_ftz_f32x2.ll +++ b/intrinsics/probes/mul_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_f32.ll b/intrinsics/probes/mul_rm_f32.ll index 79d65ac826..2a5f4660ea 100644 --- a/intrinsics/probes/mul_rm_f32.ll +++ b/intrinsics/probes/mul_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_f64.ll b/intrinsics/probes/mul_rm_f64.ll index b5a494c187..65d6ddcff7 100644 --- a/intrinsics/probes/mul_rm_f64.ll +++ b/intrinsics/probes/mul_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_ftz_f32.ll b/intrinsics/probes/mul_rm_ftz_f32.ll index d902a44361..abe2719caf 100644 --- a/intrinsics/probes/mul_rm_ftz_f32.ll +++ b/intrinsics/probes/mul_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_f32.ll b/intrinsics/probes/mul_rn_f32.ll index 7e25fac48b..c7215a1151 100644 --- a/intrinsics/probes/mul_rn_f32.ll +++ b/intrinsics/probes/mul_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_f64.ll b/intrinsics/probes/mul_rn_f64.ll index df6b0de0b8..299e91de54 100644 --- a/intrinsics/probes/mul_rn_f64.ll +++ b/intrinsics/probes/mul_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_ftz_f32.ll b/intrinsics/probes/mul_rn_ftz_f32.ll index e277d04b2e..cbb6c094cd 100644 --- a/intrinsics/probes/mul_rn_ftz_f32.ll +++ b/intrinsics/probes/mul_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_f32.ll b/intrinsics/probes/mul_rp_f32.ll index a00570e0d1..25f3e30cb8 100644 --- a/intrinsics/probes/mul_rp_f32.ll +++ b/intrinsics/probes/mul_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_f64.ll b/intrinsics/probes/mul_rp_f64.ll index 139b13f6ed..78e9ca222a 100644 --- a/intrinsics/probes/mul_rp_f64.ll +++ b/intrinsics/probes/mul_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_ftz_f32.ll b/intrinsics/probes/mul_rp_ftz_f32.ll index 2513c3bd53..ab5b7b0407 100644 --- a/intrinsics/probes/mul_rp_ftz_f32.ll +++ b/intrinsics/probes/mul_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_f32.ll b/intrinsics/probes/mul_rz_f32.ll index d70437826b..f5dc7928ea 100644 --- a/intrinsics/probes/mul_rz_f32.ll +++ b/intrinsics/probes/mul_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_f64.ll b/intrinsics/probes/mul_rz_f64.ll index f53c46c7a3..35d4d186f2 100644 --- a/intrinsics/probes/mul_rz_f64.ll +++ b/intrinsics/probes/mul_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_ftz_f32.ll b/intrinsics/probes/mul_rz_ftz_f32.ll index 8b7235528b..92ef5ea91c 100644 --- a/intrinsics/probes/mul_rz_ftz_f32.ll +++ b/intrinsics/probes/mul_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nanosleep.ll b/intrinsics/probes/nanosleep.ll index 31e0746677..58bf047598 100644 --- a/intrinsics/probes/nanosleep.ll +++ b/intrinsics/probes/nanosleep.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/neg_bf16x2.ll b/intrinsics/probes/neg_bf16x2.ll index c3df2a9490..0371541e57 100644 --- a/intrinsics/probes/neg_bf16x2.ll +++ b/intrinsics/probes/neg_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/neg_f16x2.ll b/intrinsics/probes/neg_f16x2.ll index 5fa0c3bb57..fd30e5a4bf 100644 --- a/intrinsics/probes/neg_f16x2.ll +++ b/intrinsics/probes/neg_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nsmid.lib_nvvm.ll b/intrinsics/probes/nsmid.lib_nvvm.ll index 319d7bc1da..9bd4674d53 100644 --- a/intrinsics/probes/nsmid.lib_nvvm.ll +++ b/intrinsics/probes/nsmid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nsmid.llvm_nvptx.ll b/intrinsics/probes/nsmid.llvm_nvptx.ll index ea147fe2b4..4e9b16eaa1 100644 --- a/intrinsics/probes/nsmid.llvm_nvptx.ll +++ b/intrinsics/probes/nsmid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nwarpid.lib_nvvm.ll b/intrinsics/probes/nwarpid.lib_nvvm.ll index 19b93589c8..40fd320553 100644 --- a/intrinsics/probes/nwarpid.lib_nvvm.ll +++ b/intrinsics/probes/nwarpid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nwarpid.llvm_nvptx.ll b/intrinsics/probes/nwarpid.llvm_nvptx.ll index 8307195b12..05cb134029 100644 --- a/intrinsics/probes/nwarpid.llvm_nvptx.ll +++ b/intrinsics/probes/nwarpid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/packed_atomic_add_bf16x2.ll b/intrinsics/probes/packed_atomic_add_bf16x2.ll index 95017afca3..85b23be099 100644 --- a/intrinsics/probes/packed_atomic_add_bf16x2.ll +++ b/intrinsics/probes/packed_atomic_add_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/packed_atomic_add_f16x2.ll b/intrinsics/probes/packed_atomic_add_f16x2.ll index d676859725..f2c423cc2b 100644 --- a/intrinsics/probes/packed_atomic_add_f16x2.ll +++ b/intrinsics/probes/packed_atomic_add_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/pmevent.ll b/intrinsics/probes/pmevent.ll index bb73857156..c3dec83a50 100644 --- a/intrinsics/probes/pmevent.ll +++ b/intrinsics/probes/pmevent.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prefetch_tma_descriptor.ll b/intrinsics/probes/prefetch_tma_descriptor.ll index 96ff15efd9..180a30f939 100644 --- a/intrinsics/probes/prefetch_tma_descriptor.ll +++ b/intrinsics/probes/prefetch_tma_descriptor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt.ll b/intrinsics/probes/prmt.ll index c12f0f1f1f..c0808f2b3b 100644 --- a/intrinsics/probes/prmt.ll +++ b/intrinsics/probes/prmt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_b4e.ll b/intrinsics/probes/prmt_b4e.ll index 9e47b0cad6..a940bbc120 100644 --- a/intrinsics/probes/prmt_b4e.ll +++ b/intrinsics/probes/prmt_b4e.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_ecl.ll b/intrinsics/probes/prmt_ecl.ll index 663e21d3f5..12b45c9b17 100644 --- a/intrinsics/probes/prmt_ecl.ll +++ b/intrinsics/probes/prmt_ecl.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_ecr.ll b/intrinsics/probes/prmt_ecr.ll index 1eaac5bf1f..9b77e8e1b8 100644 --- a/intrinsics/probes/prmt_ecr.ll +++ b/intrinsics/probes/prmt_ecr.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_f4e.ll b/intrinsics/probes/prmt_f4e.ll index 5968588a89..59b3cac57e 100644 --- a/intrinsics/probes/prmt_f4e.ll +++ b/intrinsics/probes/prmt_f4e.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_rc16.ll b/intrinsics/probes/prmt_rc16.ll index 0db643dad7..3723564a2b 100644 --- a/intrinsics/probes/prmt_rc16.ll +++ b/intrinsics/probes/prmt_rc16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_rc8.ll b/intrinsics/probes/prmt_rc8.ll index 62f855b4a8..5fade2061d 100644 --- a/intrinsics/probes/prmt_rc8.ll +++ b/intrinsics/probes/prmt_rc8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_approx_ftz_f32.ll b/intrinsics/probes/rcp_approx_ftz_f32.ll index 034f3cb4de..f6d516f73c 100644 --- a/intrinsics/probes/rcp_approx_ftz_f32.ll +++ b/intrinsics/probes/rcp_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_approx_ftz_f64.ll b/intrinsics/probes/rcp_approx_ftz_f64.ll index eb86737f14..03d79264d7 100644 --- a/intrinsics/probes/rcp_approx_ftz_f64.ll +++ b/intrinsics/probes/rcp_approx_ftz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_f32.ll b/intrinsics/probes/rcp_rm_f32.ll index 59460306d1..718bb5dd5a 100644 --- a/intrinsics/probes/rcp_rm_f32.ll +++ b/intrinsics/probes/rcp_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_f64.ll b/intrinsics/probes/rcp_rm_f64.ll index 27cb00ed50..5d285d4ec1 100644 --- a/intrinsics/probes/rcp_rm_f64.ll +++ b/intrinsics/probes/rcp_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_ftz_f32.ll b/intrinsics/probes/rcp_rm_ftz_f32.ll index 0c2b0e4241..88fe2c8df1 100644 --- a/intrinsics/probes/rcp_rm_ftz_f32.ll +++ b/intrinsics/probes/rcp_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_f32.ll b/intrinsics/probes/rcp_rn_f32.ll index 6665157684..187e5d1f23 100644 --- a/intrinsics/probes/rcp_rn_f32.ll +++ b/intrinsics/probes/rcp_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_f64.ll b/intrinsics/probes/rcp_rn_f64.ll index b7c8e1b002..8729c88a8d 100644 --- a/intrinsics/probes/rcp_rn_f64.ll +++ b/intrinsics/probes/rcp_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_ftz_f32.ll b/intrinsics/probes/rcp_rn_ftz_f32.ll index abb2ccf0c2..048b25a0e6 100644 --- a/intrinsics/probes/rcp_rn_ftz_f32.ll +++ b/intrinsics/probes/rcp_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_f32.ll b/intrinsics/probes/rcp_rp_f32.ll index 8e4ff5275f..5ea2b33844 100644 --- a/intrinsics/probes/rcp_rp_f32.ll +++ b/intrinsics/probes/rcp_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_f64.ll b/intrinsics/probes/rcp_rp_f64.ll index 07e06fbc64..8a904ff69f 100644 --- a/intrinsics/probes/rcp_rp_f64.ll +++ b/intrinsics/probes/rcp_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_ftz_f32.ll b/intrinsics/probes/rcp_rp_ftz_f32.ll index fa1a8cf1a9..76d538f10a 100644 --- a/intrinsics/probes/rcp_rp_ftz_f32.ll +++ b/intrinsics/probes/rcp_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_f32.ll b/intrinsics/probes/rcp_rz_f32.ll index 88487a0302..0ba6b79253 100644 --- a/intrinsics/probes/rcp_rz_f32.ll +++ b/intrinsics/probes/rcp_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_f64.ll b/intrinsics/probes/rcp_rz_f64.ll index 3c0cd5785c..c8347d4eaa 100644 --- a/intrinsics/probes/rcp_rz_f64.ll +++ b/intrinsics/probes/rcp_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_ftz_f32.ll b/intrinsics/probes/rcp_rz_ftz_f32.ll index 896ff4e3f1..1986fbb266 100644 --- a/intrinsics/probes/rcp_rz_ftz_f32.ll +++ b/intrinsics/probes/rcp_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_add.ll b/intrinsics/probes/redux_sync_add.ll index 9d01b30063..4e0704b440 100644 --- a/intrinsics/probes/redux_sync_add.ll +++ b/intrinsics/probes/redux_sync_add.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_and.ll b/intrinsics/probes/redux_sync_and.ll index 4150077a49..86457c7067 100644 --- a/intrinsics/probes/redux_sync_and.ll +++ b/intrinsics/probes/redux_sync_and.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_abs_f32.ll b/intrinsics/probes/redux_sync_max_abs_f32.ll index 8a07c470ea..6a1a36f3dd 100644 --- a/intrinsics/probes/redux_sync_max_abs_f32.ll +++ b/intrinsics/probes/redux_sync_max_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_abs_nan_f32.ll b/intrinsics/probes/redux_sync_max_abs_nan_f32.ll index 3ce5b69c03..84a27626f7 100644 --- a/intrinsics/probes/redux_sync_max_abs_nan_f32.ll +++ b/intrinsics/probes/redux_sync_max_abs_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_f32.ll b/intrinsics/probes/redux_sync_max_f32.ll index 96476dd5fd..d38044a441 100644 --- a/intrinsics/probes/redux_sync_max_f32.ll +++ b/intrinsics/probes/redux_sync_max_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_i32.ll b/intrinsics/probes/redux_sync_max_i32.ll index 2da32bbeeb..12c8729502 100644 --- a/intrinsics/probes/redux_sync_max_i32.ll +++ b/intrinsics/probes/redux_sync_max_i32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_nan_f32.ll b/intrinsics/probes/redux_sync_max_nan_f32.ll index 7b4709781e..38c67bcfb5 100644 --- a/intrinsics/probes/redux_sync_max_nan_f32.ll +++ b/intrinsics/probes/redux_sync_max_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_u32.ll b/intrinsics/probes/redux_sync_max_u32.ll index 86b6f79d6a..518e53d4b9 100644 --- a/intrinsics/probes/redux_sync_max_u32.ll +++ b/intrinsics/probes/redux_sync_max_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_abs_f32.ll b/intrinsics/probes/redux_sync_min_abs_f32.ll index 52382e238c..4cc74871ba 100644 --- a/intrinsics/probes/redux_sync_min_abs_f32.ll +++ b/intrinsics/probes/redux_sync_min_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_abs_nan_f32.ll b/intrinsics/probes/redux_sync_min_abs_nan_f32.ll index c5ec8174ed..1e6bc63537 100644 --- a/intrinsics/probes/redux_sync_min_abs_nan_f32.ll +++ b/intrinsics/probes/redux_sync_min_abs_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_f32.ll b/intrinsics/probes/redux_sync_min_f32.ll index 642291a5d3..8dbea8a7a8 100644 --- a/intrinsics/probes/redux_sync_min_f32.ll +++ b/intrinsics/probes/redux_sync_min_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_i32.ll b/intrinsics/probes/redux_sync_min_i32.ll index 850139c935..dd1636caba 100644 --- a/intrinsics/probes/redux_sync_min_i32.ll +++ b/intrinsics/probes/redux_sync_min_i32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_nan_f32.ll b/intrinsics/probes/redux_sync_min_nan_f32.ll index c9477b2e5b..79575d21bc 100644 --- a/intrinsics/probes/redux_sync_min_nan_f32.ll +++ b/intrinsics/probes/redux_sync_min_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_u32.ll b/intrinsics/probes/redux_sync_min_u32.ll index 6140e0ea15..607dee5aef 100644 --- a/intrinsics/probes/redux_sync_min_u32.ll +++ b/intrinsics/probes/redux_sync_min_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_or.ll b/intrinsics/probes/redux_sync_or.ll index a02772fa31..0810fa7800 100644 --- a/intrinsics/probes/redux_sync_or.ll +++ b/intrinsics/probes/redux_sync_or.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_xor.ll b/intrinsics/probes/redux_sync_xor.ll index d9a28793f8..8ee258414e 100644 --- a/intrinsics/probes/redux_sync_xor.ll +++ b/intrinsics/probes/redux_sync_xor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_f32.ll b/intrinsics/probes/rsqrt_approx_f32.ll index 78e1ca8322..e22a8a31fb 100644 --- a/intrinsics/probes/rsqrt_approx_f32.ll +++ b/intrinsics/probes/rsqrt_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_f64.ll b/intrinsics/probes/rsqrt_approx_f64.ll index 0f05e0cd32..1b9bf93289 100644 --- a/intrinsics/probes/rsqrt_approx_f64.ll +++ b/intrinsics/probes/rsqrt_approx_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_ftz_f32.ll b/intrinsics/probes/rsqrt_approx_ftz_f32.ll index 7872ff4e3b..4172cc059e 100644 --- a/intrinsics/probes/rsqrt_approx_ftz_f32.ll +++ b/intrinsics/probes/rsqrt_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/setmaxnreg_dec.ll b/intrinsics/probes/setmaxnreg_dec.ll index 2e9688fd10..26695e0023 100644 --- a/intrinsics/probes/setmaxnreg_dec.ll +++ b/intrinsics/probes/setmaxnreg_dec.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/setmaxnreg_inc.ll b/intrinsics/probes/setmaxnreg_inc.ll index 32c83ba94b..c8a7ce8e36 100644 --- a/intrinsics/probes/setmaxnreg_inc.ll +++ b/intrinsics/probes/setmaxnreg_inc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_f32_sync.ll b/intrinsics/probes/shuffle_down_f32_sync.ll index 5039192fc4..f4963ff3ca 100644 --- a/intrinsics/probes/shuffle_down_f32_sync.ll +++ b/intrinsics/probes/shuffle_down_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_sync.ll b/intrinsics/probes/shuffle_down_sync.ll index 42d3712dac..82b17eb8e6 100644 --- a/intrinsics/probes/shuffle_down_sync.ll +++ b/intrinsics/probes/shuffle_down_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_u64_sync.ll b/intrinsics/probes/shuffle_down_u64_sync.ll index 010a15e8c3..6cc42d5354 100644 --- a/intrinsics/probes/shuffle_down_u64_sync.ll +++ b/intrinsics/probes/shuffle_down_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_f32_sync.ll b/intrinsics/probes/shuffle_f32_sync.ll index bec62752f8..42682cf11a 100644 --- a/intrinsics/probes/shuffle_f32_sync.ll +++ b/intrinsics/probes/shuffle_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_sync.ll b/intrinsics/probes/shuffle_sync.ll index ecd8725b68..927a87a316 100644 --- a/intrinsics/probes/shuffle_sync.ll +++ b/intrinsics/probes/shuffle_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_u64_sync.ll b/intrinsics/probes/shuffle_u64_sync.ll index 8e195e1106..d3dcd2abbe 100644 --- a/intrinsics/probes/shuffle_u64_sync.ll +++ b/intrinsics/probes/shuffle_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_f32_sync.ll b/intrinsics/probes/shuffle_up_f32_sync.ll index 0466bb844d..319c2d11fb 100644 --- a/intrinsics/probes/shuffle_up_f32_sync.ll +++ b/intrinsics/probes/shuffle_up_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_sync.ll b/intrinsics/probes/shuffle_up_sync.ll index 74980f50d6..800c3b14e1 100644 --- a/intrinsics/probes/shuffle_up_sync.ll +++ b/intrinsics/probes/shuffle_up_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_u64_sync.ll b/intrinsics/probes/shuffle_up_u64_sync.ll index 1ad027e10c..fb3baefcb9 100644 --- a/intrinsics/probes/shuffle_up_u64_sync.ll +++ b/intrinsics/probes/shuffle_up_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_f32_sync.ll b/intrinsics/probes/shuffle_xor_f32_sync.ll index 9108023cef..2f5d56f6d7 100644 --- a/intrinsics/probes/shuffle_xor_f32_sync.ll +++ b/intrinsics/probes/shuffle_xor_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_sync.ll b/intrinsics/probes/shuffle_xor_sync.ll index 6fdaef54eb..861149d42e 100644 --- a/intrinsics/probes/shuffle_xor_sync.ll +++ b/intrinsics/probes/shuffle_xor_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_u64_sync.ll b/intrinsics/probes/shuffle_xor_u64_sync.ll index 328fd0ca98..e3f80f11e3 100644 --- a/intrinsics/probes/shuffle_xor_u64_sync.ll +++ b/intrinsics/probes/shuffle_xor_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sin_approx_f32.ll b/intrinsics/probes/sin_approx_f32.ll index ca6366e996..60a0d6ddfb 100644 --- a/intrinsics/probes/sin_approx_f32.ll +++ b/intrinsics/probes/sin_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sin_approx_ftz_f32.ll b/intrinsics/probes/sin_approx_ftz_f32.ll index 2c092a4283..6871d59f30 100644 --- a/intrinsics/probes/sin_approx_ftz_f32.ll +++ b/intrinsics/probes/sin_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/smid.lib_nvvm.ll b/intrinsics/probes/smid.lib_nvvm.ll index 6893bf8faa..951e4624a5 100644 --- a/intrinsics/probes/smid.lib_nvvm.ll +++ b/intrinsics/probes/smid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/smid.llvm_nvptx.ll b/intrinsics/probes/smid.llvm_nvptx.ll index 3df4a4f79b..09af421460 100644 --- a/intrinsics/probes/smid.llvm_nvptx.ll +++ b/intrinsics/probes/smid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_approx_f32.ll b/intrinsics/probes/sqrt_approx_f32.ll index 23b4f3a302..f70a7cd2a4 100644 --- a/intrinsics/probes/sqrt_approx_f32.ll +++ b/intrinsics/probes/sqrt_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_approx_ftz_f32.ll b/intrinsics/probes/sqrt_approx_ftz_f32.ll index 4d3f15ae3d..844c3f03ac 100644 --- a/intrinsics/probes/sqrt_approx_ftz_f32.ll +++ b/intrinsics/probes/sqrt_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_f32.ll b/intrinsics/probes/sqrt_rm_f32.ll index b677a2d84d..241f8e8aaf 100644 --- a/intrinsics/probes/sqrt_rm_f32.ll +++ b/intrinsics/probes/sqrt_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_f64.ll b/intrinsics/probes/sqrt_rm_f64.ll index 42f7ff1cdb..413063f878 100644 --- a/intrinsics/probes/sqrt_rm_f64.ll +++ b/intrinsics/probes/sqrt_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_ftz_f32.ll b/intrinsics/probes/sqrt_rm_ftz_f32.ll index b6d28583f5..a2af78ad00 100644 --- a/intrinsics/probes/sqrt_rm_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_f32.ll b/intrinsics/probes/sqrt_rn_f32.ll index de5ecfbb80..b431f31efe 100644 --- a/intrinsics/probes/sqrt_rn_f32.ll +++ b/intrinsics/probes/sqrt_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_f64.ll b/intrinsics/probes/sqrt_rn_f64.ll index f08fd2587b..c03107fb66 100644 --- a/intrinsics/probes/sqrt_rn_f64.ll +++ b/intrinsics/probes/sqrt_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_ftz_f32.ll b/intrinsics/probes/sqrt_rn_ftz_f32.ll index be49022029..212a3f064a 100644 --- a/intrinsics/probes/sqrt_rn_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_f32.ll b/intrinsics/probes/sqrt_rp_f32.ll index be3d691e99..24538afae1 100644 --- a/intrinsics/probes/sqrt_rp_f32.ll +++ b/intrinsics/probes/sqrt_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_f64.ll b/intrinsics/probes/sqrt_rp_f64.ll index ec84f718b9..23ba0fd921 100644 --- a/intrinsics/probes/sqrt_rp_f64.ll +++ b/intrinsics/probes/sqrt_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_ftz_f32.ll b/intrinsics/probes/sqrt_rp_ftz_f32.ll index 6f5c859e8f..f3bde884ec 100644 --- a/intrinsics/probes/sqrt_rp_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_f32.ll b/intrinsics/probes/sqrt_rz_f32.ll index 0e173444ae..39cbb582fe 100644 --- a/intrinsics/probes/sqrt_rz_f32.ll +++ b/intrinsics/probes/sqrt_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_f64.ll b/intrinsics/probes/sqrt_rz_f64.ll index 7d73dc526f..a257befb15 100644 --- a/intrinsics/probes/sqrt_rz_f64.ll +++ b/intrinsics/probes/sqrt_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_ftz_f32.ll b/intrinsics/probes/sqrt_rz_ftz_f32.ll index 12e7a8f1e5..8732e11e73 100644 --- a/intrinsics/probes/sqrt_rz_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x2_b16.ll b/intrinsics/probes/stmatrix_m8n8_x2_b16.ll index a409d06bbc..0c75e264fc 100644 --- a/intrinsics/probes/stmatrix_m8n8_x2_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x2_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll b/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll index ab08644dd2..c75f5c3fa7 100644 --- a/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x4_b16.ll b/intrinsics/probes/stmatrix_m8n8_x4_b16.ll index abd27d5e06..e834f54d6b 100644 --- a/intrinsics/probes/stmatrix_m8n8_x4_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x4_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll b/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll index a5edc9769b..0eaf9bb3c3 100644 --- a/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_bf16x2.ll b/intrinsics/probes/sub_bf16x2.ll index 2403a87e38..d7bf56de17 100644 --- a/intrinsics/probes/sub_bf16x2.ll +++ b/intrinsics/probes/sub_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_f16x2.ll b/intrinsics/probes/sub_f16x2.ll index 0abe33ae5f..9bed3028bf 100644 --- a/intrinsics/probes/sub_f16x2.ll +++ b/intrinsics/probes/sub_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_f32x2.ll b/intrinsics/probes/sub_f32x2.ll index 838269bb63..cba5949968 100644 --- a/intrinsics/probes/sub_f32x2.ll +++ b/intrinsics/probes/sub_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_ftz_f32x2.ll b/intrinsics/probes/sub_ftz_f32x2.ll index 71d9d14d3c..489c1952c9 100644 --- a/intrinsics/probes/sub_ftz_f32x2.ll +++ b/intrinsics/probes/sub_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sync_mask.ll b/intrinsics/probes/sync_mask.ll index d6a902cec7..d4b22549c7 100644 --- a/intrinsics/probes/sync_mask.ll +++ b/intrinsics/probes/sync_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sync_threads.ll b/intrinsics/probes/sync_threads.ll index 6d7d065ed9..3760eac08d 100644 --- a/intrinsics/probes/sync_threads.ll +++ b/intrinsics/probes/sync_threads.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tanh_approx_f32.ll b/intrinsics/probes/tanh_approx_f32.ll index ec8f479700..23f04cacc4 100644 --- a/intrinsics/probes/tanh_approx_f32.ll +++ b/intrinsics/probes/tanh_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_alloc.ll b/intrinsics/probes/tcgen05_alloc.ll index 1e062531ec..b25351c6d5 100644 --- a/intrinsics/probes/tcgen05_alloc.ll +++ b/intrinsics/probes/tcgen05_alloc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_alloc_cg2.ll b/intrinsics/probes/tcgen05_alloc_cg2.ll index 0784c76728..53694377a9 100644 --- a/intrinsics/probes/tcgen05_alloc_cg2.ll +++ b/intrinsics/probes/tcgen05_alloc_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit.ll b/intrinsics/probes/tcgen05_commit.ll index a036690b0f..bccdd1b046 100644 --- a/intrinsics/probes/tcgen05_commit.ll +++ b/intrinsics/probes/tcgen05_commit.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_cg2.ll b/intrinsics/probes/tcgen05_commit_cg2.ll index 69b6ef0c9e..9d84744578 100644 --- a/intrinsics/probes/tcgen05_commit_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_multicast.ll b/intrinsics/probes/tcgen05_commit_multicast.ll index a4763c2dd0..fa54ebfe86 100644 --- a/intrinsics/probes/tcgen05_commit_multicast.ll +++ b/intrinsics/probes/tcgen05_commit_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_multicast_cg2.ll b/intrinsics/probes/tcgen05_commit_multicast_cg2.ll index 62324539e7..ddf212137c 100644 --- a/intrinsics/probes/tcgen05_commit_multicast_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_multicast_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_shared_cluster.ll b/intrinsics/probes/tcgen05_commit_shared_cluster.ll index cdbe307c61..a9015ece25 100644 --- a/intrinsics/probes/tcgen05_commit_shared_cluster.ll +++ b/intrinsics/probes/tcgen05_commit_shared_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll b/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll index d625c5ee1f..5fe6f0a0d6 100644 --- a/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b.ll b/intrinsics/probes/tcgen05_cp_128x128b.ll index 761425ae15..684f847ab9 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll index 42bf400b19..f076c4a788 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll index feb4e65542..baa0eaa221 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll index 486dd5f1e3..d92561e885 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll index f88eebadbb..0807855f9e 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll index a76c7e7ee4..cd1578ba54 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll index 9a9bff02db..cbb2edd947 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll index 612f69f3d5..53a180a2f9 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll index a20c510dcc..1e2873149d 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll index 9054a2494d..99f14e26f1 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll index 6f9281f045..cfb41b89de 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll index d8fcc692e7..cb777dd00d 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll index d426ee8b51..40f93b1544 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll index ebdda59a7a..28fbe75c65 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll index 8b60d197c8..4f637d0ba6 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll index fb08f043d3..b369269f27 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b.ll b/intrinsics/probes/tcgen05_cp_4x256b.ll index ed64ab18f5..0e420c56bb 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll index 40d7f1fd3d..bea31a013a 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll index f17fbf25d7..a7c04ee28c 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll index b6c7515e4e..71830db275 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll index a6744d776d..7cd788e50c 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll index 2341f48966..b0d6b0b343 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll index 8eb38ee305..3b8d06917f 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll index 8592a38054..04ba0560f5 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll index cea46f95ff..d29f632056 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll index 0390970892..b858b3d73b 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll index 29466b34c3..5d3e6dfcb0 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll index a4fad16fbb..00dc573ebe 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll index 15ee41b47f..09de27398e 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll index 43c432ddce..2999d3a578 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll index 41d034c319..9576cc7137 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll index 77f3462d23..8bfaf0f1b1 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll index 4c7889a0c1..f91c7abeea 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll index 6b92e223c1..049379aada 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll b/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll index d794afe19d..501cbe2376 100644 --- a/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll +++ b/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll b/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll index 3daac6272a..e70671d475 100644 --- a/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_dealloc.ll b/intrinsics/probes/tcgen05_dealloc.ll index 825aee837f..bdf59f497f 100644 --- a/intrinsics/probes/tcgen05_dealloc.ll +++ b/intrinsics/probes/tcgen05_dealloc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_dealloc_cg2.ll b/intrinsics/probes/tcgen05_dealloc_cg2.ll index 0e583abc4f..a29eaa34a7 100644 --- a/intrinsics/probes/tcgen05_dealloc_cg2.ll +++ b/intrinsics/probes/tcgen05_dealloc_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_fence_after_thread_sync.ll b/intrinsics/probes/tcgen05_fence_after_thread_sync.ll index 4717b5d0a9..eb6b65e862 100644 --- a/intrinsics/probes/tcgen05_fence_after_thread_sync.ll +++ b/intrinsics/probes/tcgen05_fence_after_thread_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_fence_before_thread_sync.ll b/intrinsics/probes/tcgen05_fence_before_thread_sync.ll index 69d47c7c8e..c38cb00490 100644 --- a/intrinsics/probes/tcgen05_fence_before_thread_sync.ll +++ b/intrinsics/probes/tcgen05_fence_before_thread_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll index 5aa78e5ea0..49a1849bbb 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll index d5c80c69fb..8a27dccc63 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll index ca004ee8f9..5fabb1e916 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll index c32da8e97c..bd595692cf 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll index 63ecd59864..d6ce8ec218 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll index 1b8eb91e6d..3c76ec80d2 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll index f1d0164920..646a77e9de 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll index 734c60839c..2528486fdd 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll index e792d65dfa..c48e626118 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll index 1dad30e9cb..b51743c33b 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll index a61e1f8a3f..d3f8b76e0b 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll index d1f1c1313f..3c1f5bc0a7 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll index d9a446e838..f300e6be3a 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll index 160ae51b7f..f6daed2a07 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_pure.ll b/intrinsics/probes/tcgen05_ld_16x256b_pure.ll index 1a74affa98..fb413c9c1a 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_pure.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_pure.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll index ea19068c5c..d3c2b95178 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll index a1dc7a935d..783c171cab 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll index 8531d5bb3c..96700f5d21 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll index ae0a3fd8f9..6057656613 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll index bda085adc6..bb2312a801 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll index 05445c17b3..91d08665f8 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll index 897260ec88..cb72b64b65 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll index 743e0d822c..3007bc2f4a 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll index 8471ba0744..d1f4cd7970 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll index e7a8b82d1f..8b45e8b835 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll index b307dc6e5c..ec9bc98298 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll index 8f295e4fbd..7136a783a5 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll index 8389bea7f6..5eed13528b 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll index 48db75886f..db7a4c685b 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll index 7901402584..b6960e4253 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll index 7765bed746..10d1438a85 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll index 6d24a5cdf0..3be26f3137 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll index 75a1ba3627..0547d950f7 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll index 8dc00098a3..0666bfe13b 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll index ddc5f777b7..25ec3f4268 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll index 98e1e269a5..b36c54ede3 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll index 271beda0b1..07958d6c1f 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll index 2debd00812..f50419dbf8 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll index ecdfd6e83d..0944764a89 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll index 77d67affd7..fda73be654 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll index a1ac2f6554..25808070d0 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll index 2d79e5ec23..1d3c76e6b8 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll index 4bd68d55a4..325d99c566 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll index 2ffc27f817..1dc33edc32 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll index 3d44e2c612..854fc61cf2 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll index 7d5fb38234..95448b2ff8 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll index 0c06e95bf8..6066ccf4eb 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll index 0549a9480c..9d2d4d7eb7 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll index d230607c90..1ec0d1ed5a 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll index 80d1aacb50..8a6058b291 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll index 95737d3ef2..061946e407 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll index cbbd5ccc48..92626a7557 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll index 8ed51ecc40..2ae168a4e5 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll index 722423186f..4d2fc2cd53 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll index af9e38388a..12fcc00600 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll index f516bced7e..2218782930 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll index 93f551fd36..a0ee36924b 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll index 1c811b554d..0f0ba0218b 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll index 698023a91d..9b93fb33f1 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll index 697e0c4f19..6cd6058c61 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll index e1b6ae11e0..ae72dbc4be 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll index 6f5b332fa5..bbb92b200a 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll index 2a9e599fcd..9541c4c14e 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll index 760a9035a0..9430f93518 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll index 28d5dbdf60..40f7f4a333 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll index 373adff114..4c14670979 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll index 8cdf74ec4f..f3353b5146 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll index fe1c21211f..ea0df1505e 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll index 757e8be5a5..bfe8937bc6 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll index 6f19b8b94b..12ea1d89bd 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll index 2f02682a40..5832bff666 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll index bfab6e2de8..cfd6cc0d9a 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll index 31821af033..65fba3b12d 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll index 97227fbce5..cf69a3844f 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll index f9c79ad490..abaccdb81c 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll index 2115e16d4e..70a20b16ab 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_load_wait.ll b/intrinsics/probes/tcgen05_load_wait.ll index 89bc5fdf08..18020f4249 100644 --- a/intrinsics/probes/tcgen05_load_wait.ll +++ b/intrinsics/probes/tcgen05_load_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e2m1.ll b/intrinsics/probes/tcgen05_mma_e2m1.ll index 4c7afd73af..ed5fa22f7a 100644 --- a/intrinsics/probes/tcgen05_mma_e2m1.ll +++ b/intrinsics/probes/tcgen05_mma_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e2m3.ll b/intrinsics/probes/tcgen05_mma_e2m3.ll index 8be6ff83bc..1a74b52db3 100644 --- a/intrinsics/probes/tcgen05_mma_e2m3.ll +++ b/intrinsics/probes/tcgen05_mma_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e3m2.ll b/intrinsics/probes/tcgen05_mma_e3m2.ll index f616cdc2cb..321cd0c82c 100644 --- a/intrinsics/probes/tcgen05_mma_e3m2.ll +++ b/intrinsics/probes/tcgen05_mma_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e4m3.ll b/intrinsics/probes/tcgen05_mma_e4m3.ll index 593e963bc8..25447e7326 100644 --- a/intrinsics/probes/tcgen05_mma_e4m3.ll +++ b/intrinsics/probes/tcgen05_mma_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e5m2.ll b/intrinsics/probes/tcgen05_mma_e5m2.ll index 91a3f801fb..e51207ae66 100644 --- a/intrinsics/probes/tcgen05_mma_e5m2.ll +++ b/intrinsics/probes/tcgen05_mma_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_f16.ll b/intrinsics/probes/tcgen05_mma_f16.ll index e93e0d74d9..d032cb21dd 100644 --- a/intrinsics/probes/tcgen05_mma_f16.ll +++ b/intrinsics/probes/tcgen05_mma_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_f16_cg2.ll b/intrinsics/probes/tcgen05_mma_f16_cg2.ll index a90758954e..d312dd9fe0 100644 --- a/intrinsics/probes/tcgen05_mma_f16_cg2.ll +++ b/intrinsics/probes/tcgen05_mma_f16_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_shared.ll b/intrinsics/probes/tcgen05_mma_shared.ll index eb3d85e9b4..1a87fd6b7d 100644 --- a/intrinsics/probes/tcgen05_mma_shared.ll +++ b/intrinsics/probes/tcgen05_mma_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_shared.ll b/intrinsics/probes/tcgen05_mma_sp_shared.ll index c3cb1f9678..cd20c8dc1f 100644 --- a/intrinsics/probes/tcgen05_mma_sp_shared.ll +++ b/intrinsics/probes/tcgen05_mma_sp_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_tensor.ll b/intrinsics/probes/tcgen05_mma_sp_tensor.ll index 05d817be2e..70ab7aa3cd 100644 --- a/intrinsics/probes/tcgen05_mma_sp_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_sp_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll b/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll index 6a68a1cee9..26d94e9c97 100644 --- a/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll +++ b/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_tensor.ll b/intrinsics/probes/tcgen05_mma_tensor.ll index b1943669b7..63abf5092b 100644 --- a/intrinsics/probes/tcgen05_mma_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_tensor_ashift.ll b/intrinsics/probes/tcgen05_mma_tensor_ashift.ll index 5ff3d8140d..bf290a9297 100644 --- a/intrinsics/probes/tcgen05_mma_tensor_ashift.ll +++ b/intrinsics/probes/tcgen05_mma_tensor_ashift.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_bf16.ll b/intrinsics/probes/tcgen05_mma_ws_bf16.ll index f78aa651e7..dd3e1c552e 100644 --- a/intrinsics/probes/tcgen05_mma_ws_bf16.ll +++ b/intrinsics/probes/tcgen05_mma_ws_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e2m1.ll b/intrinsics/probes/tcgen05_mma_ws_e2m1.ll index 624f8bce7a..5362fc019f 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e2m1.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e2m3.ll b/intrinsics/probes/tcgen05_mma_ws_e2m3.ll index 61d646828b..12adfb2e23 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e2m3.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e3m2.ll b/intrinsics/probes/tcgen05_mma_ws_e3m2.ll index 8b2c0e2c60..37f28c454d 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e3m2.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e4m3.ll b/intrinsics/probes/tcgen05_mma_ws_e4m3.ll index ffe8cfa58a..e30c99b6de 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e4m3.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e5m2.ll b/intrinsics/probes/tcgen05_mma_ws_e5m2.ll index ba9093120f..1da1402cb9 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e5m2.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_f16.ll b/intrinsics/probes/tcgen05_mma_ws_f16.ll index 8790728e25..d248a566eb 100644 --- a/intrinsics/probes/tcgen05_mma_ws_f16.ll +++ b/intrinsics/probes/tcgen05_mma_ws_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_shared.ll b/intrinsics/probes/tcgen05_mma_ws_shared.ll index a37ab3607d..8244a42879 100644 --- a/intrinsics/probes/tcgen05_mma_ws_shared.ll +++ b/intrinsics/probes/tcgen05_mma_ws_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll index dbf2447977..90ddf7440b 100644 --- a/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll b/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll index 952ed981c6..762879f141 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll index 35c6facfc0..eea8a62ce7 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll b/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll index 92a94536d0..67275a5c16 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll index a648259324..eb7d01ce6e 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tensor.ll b/intrinsics/probes/tcgen05_mma_ws_tensor.ll index 0175203feb..0e06eb9814 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll index 81b835bc1f..529fedacf9 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tf32.ll b/intrinsics/probes/tcgen05_mma_ws_tf32.ll index 40cbe43302..3c09a39f9c 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tf32.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll b/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll index cbafde11cf..43eaf33685 100644 --- a/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll +++ b/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll b/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll index 25dc4f4ae2..6009623a2a 100644 --- a/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll +++ b/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_shift_down.ll b/intrinsics/probes/tcgen05_shift_down.ll index 1637452ea9..e41156b016 100644 --- a/intrinsics/probes/tcgen05_shift_down.ll +++ b/intrinsics/probes/tcgen05_shift_down.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_shift_down_cg2.ll b/intrinsics/probes/tcgen05_shift_down_cg2.ll index fe8013517c..6b5d08d581 100644 --- a/intrinsics/probes/tcgen05_shift_down_cg2.ll +++ b/intrinsics/probes/tcgen05_shift_down_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll index e5fcec5939..920c392202 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll index 7da13aa24b..790ca9e4d6 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll index 3c7e5ed740..22b6ec0b1a 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll index fe7e755952..09ed558cb2 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll index 4df530ec5c..92069ccdf8 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll index ae82488681..6d03e10ce3 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll index b9209d77ec..83362fa4eb 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll index 818a2d22ae..2dec484fd4 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll index f265df5a8e..4cd2ef2697 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll index 5403f9eaac..3b4095d458 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll index 54e27b0c2c..9f16e7053c 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll index 280af344c2..010a4546ca 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll index 280bd33176..06a8b4a532 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll index 48832b575c..0a38dd112a 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll index d14747c4f7..96edf5af61 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll index 995100d539..227fca6429 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll index 6a4fbc4fc3..c3c86b73a1 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll index 09caf2716a..4b2446e402 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll index d117162db3..c5491ded56 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll index 37bee869ef..d034156af4 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll index 27af9bd200..3030bfd9ab 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll index b495f5a455..444bef56fc 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll index 504e23ed84..a725764f7e 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll index 361cb98a65..3daf701f6e 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll index 371144a37f..f6541e7ed9 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll index 848a1c32d1..cdec1b413b 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll index c8475be460..969e5ae2a6 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll index b4830f261c..5dd8bd0882 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll index 9b03719978..3e02219269 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll index 89897e8b7b..2a38b72e7e 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll index 8cbb0993c9..9c1999d26a 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll index 75c3df089a..acb2aef351 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll index 1dd8177b48..74bb42f5dd 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll index c8a840f400..bc5bd36b6c 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll index a73d189876..1a8ede4067 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll index 561617d8c7..3c387b8a84 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll index 360542dd91..b4af7de601 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll index 092bbc3a08..f7a43c8dcb 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll index 40b412f1a3..520abde56a 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll index 683cc4cc1f..9cdd17fee4 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll index 6fa93fb36f..687677bbcb 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll index 215bdd842b..02b58ca2bf 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll index 7ba1dbcdec..2933850e4e 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll index 41da53872e..4137c5ba6e 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll index 1fe6f4b6cb..9087ef6bf1 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll index 00619c6e3e..2bccc5e87d 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll index de77b7e73c..18d3c28e71 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll index 4becf9e27b..e031bc14f7 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll index be9b60124d..296ab24a31 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll index 5e3e198c02..65a2ea3f81 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll index 1f86fecff4..949bba8fe3 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll index 40154a4d6f..3c657d8a8f 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll index 6928853d1c..5175fa5d6c 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll index 052e32f7ea..15c94408f5 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll index 3a45e84f4c..0962a04e07 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll index 58269e9f4a..b01d23d9ff 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll index 0a57994283..f1ee2b4949 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll index c172c91f28..e014ccb424 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll index d16facfadf..80f835d29e 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll index 9bac8505d7..e9a8979d3a 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll index 6e22d00ed6..54167a482b 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll index 967a3aecaa..f35f09d680 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll index d834bd9140..64b42a3e56 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll index 7eef6f84f8..fa1c300f4e 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll index d53f694bf7..b279705869 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll index 1983ef3640..184cf7d937 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll index 90c9625f58..199943c461 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll index d888977495..e067f41804 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll index b9c93b0e6a..bf7ebfc164 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll index 9c9170f95d..f2e7c8a5eb 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll index d8f1339b5b..547c182215 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll index 5f3005b610..e906017238 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll index 37b0dffb8e..28af65dc8c 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll index 6066a36350..48474297cf 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_store_wait.ll b/intrinsics/probes/tcgen05_store_wait.ll index e135cabea3..ce266a9a56 100644 --- a/intrinsics/probes/tcgen05_store_wait.ll +++ b/intrinsics/probes/tcgen05_store_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_box_dim.ll b/intrinsics/probes/tensormap_replace_box_dim.ll index dd0f4d0a64..bdbb1ce2f1 100644 --- a/intrinsics/probes/tensormap_replace_box_dim.ll +++ b/intrinsics/probes/tensormap_replace_box_dim.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_element_stride.ll b/intrinsics/probes/tensormap_replace_element_stride.ll index db87b7db8c..71306b0e4d 100644 --- a/intrinsics/probes/tensormap_replace_element_stride.ll +++ b/intrinsics/probes/tensormap_replace_element_stride.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_element_type.ll b/intrinsics/probes/tensormap_replace_element_type.ll index 10cacd7771..ee9e72e6ad 100644 --- a/intrinsics/probes/tensormap_replace_element_type.ll +++ b/intrinsics/probes/tensormap_replace_element_type.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_fill_mode.ll b/intrinsics/probes/tensormap_replace_fill_mode.ll index 29868188be..f5c8171578 100644 --- a/intrinsics/probes/tensormap_replace_fill_mode.ll +++ b/intrinsics/probes/tensormap_replace_fill_mode.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_address.ll b/intrinsics/probes/tensormap_replace_global_address.ll index 9e5a0a9d5f..b941d8912d 100644 --- a/intrinsics/probes/tensormap_replace_global_address.ll +++ b/intrinsics/probes/tensormap_replace_global_address.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_dim.ll b/intrinsics/probes/tensormap_replace_global_dim.ll index 476abb6c0e..dc9153a1a0 100644 --- a/intrinsics/probes/tensormap_replace_global_dim.ll +++ b/intrinsics/probes/tensormap_replace_global_dim.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_stride.ll b/intrinsics/probes/tensormap_replace_global_stride.ll index c75f364502..74aa264102 100644 --- a/intrinsics/probes/tensormap_replace_global_stride.ll +++ b/intrinsics/probes/tensormap_replace_global_stride.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_interleave_layout.ll b/intrinsics/probes/tensormap_replace_interleave_layout.ll index 25daa8bdb6..7699ee1ff4 100644 --- a/intrinsics/probes/tensormap_replace_interleave_layout.ll +++ b/intrinsics/probes/tensormap_replace_interleave_layout.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_rank.ll b/intrinsics/probes/tensormap_replace_rank.ll index df0c80c614..b2d296e16a 100644 --- a/intrinsics/probes/tensormap_replace_rank.ll +++ b/intrinsics/probes/tensormap_replace_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll b/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll index a99ef8e470..463270654d 100644 --- a/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll +++ b/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_swizzle_mode.ll b/intrinsics/probes/tensormap_replace_swizzle_mode.ll index bfd8e2013c..43766f3f7f 100644 --- a/intrinsics/probes/tensormap_replace_swizzle_mode.ll +++ b/intrinsics/probes/tensormap_replace_swizzle_mode.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_x.ll b/intrinsics/probes/thread_idx_x.ll index 52cdc908c0..d2351c570a 100644 --- a/intrinsics/probes/thread_idx_x.ll +++ b/intrinsics/probes/thread_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_y.ll b/intrinsics/probes/thread_idx_y.ll index 8993e69c87..dd644c2abf 100644 --- a/intrinsics/probes/thread_idx_y.ll +++ b/intrinsics/probes/thread_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_z.ll b/intrinsics/probes/thread_idx_z.ll index 571dca718e..5c1fc163f1 100644 --- a/intrinsics/probes/thread_idx_z.ll +++ b/intrinsics/probes/thread_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence.ll b/intrinsics/probes/threadfence.ll index 037bb41fef..071944d734 100644 --- a/intrinsics/probes/threadfence.ll +++ b/intrinsics/probes/threadfence.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence_block.ll b/intrinsics/probes/threadfence_block.ll index 512b521d1c..a6f595b6f8 100644 --- a/intrinsics/probes/threadfence_block.ll +++ b/intrinsics/probes/threadfence_block.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence_system.ll b/intrinsics/probes/threadfence_system.ll index 5cfd4922dc..8d81ee537e 100644 --- a/intrinsics/probes/threadfence_system.ll +++ b/intrinsics/probes/threadfence_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/total_smem_size.lib_nvvm.ll b/intrinsics/probes/total_smem_size.lib_nvvm.ll index 12d82c09c3..bdc60a9924 100644 --- a/intrinsics/probes/total_smem_size.lib_nvvm.ll +++ b/intrinsics/probes/total_smem_size.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/total_smem_size.llvm_nvptx.ll b/intrinsics/probes/total_smem_size.llvm_nvptx.ll index 800e879483..6b3f8c55fd 100644 --- a/intrinsics/probes/total_smem_size.llvm_nvptx.ll +++ b/intrinsics/probes/total_smem_size.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/trap.ll b/intrinsics/probes/trap.ll index b92054ebd4..81acd9e0fe 100644 --- a/intrinsics/probes/trap.ll +++ b/intrinsics/probes/trap.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/uni_sync.ll b/intrinsics/probes/uni_sync.ll index da626d4550..aa9a5ae28c 100644 --- a/intrinsics/probes/uni_sync.ll +++ b/intrinsics/probes/uni_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/warpid.lib_nvvm.ll b/intrinsics/probes/warpid.lib_nvvm.ll index 23aaa13594..b009ad1d2d 100644 --- a/intrinsics/probes/warpid.lib_nvvm.ll +++ b/intrinsics/probes/warpid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/warpid.llvm_nvptx.ll b/intrinsics/probes/warpid.llvm_nvptx.ll index b67646eab1..e1ab6cd11d 100644 --- a/intrinsics/probes/warpid.llvm_nvptx.ll +++ b/intrinsics/probes/warpid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_commit_group.ll b/intrinsics/probes/wgmma_commit_group.ll index 102fa7021b..495a977a43 100644 --- a/intrinsics/probes/wgmma_commit_group.ll +++ b/intrinsics/probes/wgmma_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_fence.ll b/intrinsics/probes/wgmma_fence.ll index 89db8e88d0..a901d9c947 100644 --- a/intrinsics/probes/wgmma_fence.ll +++ b/intrinsics/probes/wgmma_fence.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_wait_group.ll b/intrinsics/probes/wgmma_wait_group.ll index 2091c60904..77d9a540f2 100644 --- a/intrinsics/probes/wgmma_wait_group.ll +++ b/intrinsics/probes/wgmma_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 49bcd626b91f3261e80f77fb2817a54d96bddd6364f2564d113eee7ee62b8266. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" From 61c0b219ff77bec6819a9d2ef6f022147700157b Mon Sep 17 00:00:00 2001 From: nihalpasham Date: Sun, 30 Aug 2026 15:58:13 +0530 Subject: [PATCH 4/5] chore(intrinsics): re-attest sparse float MMA evidence on the local CUDA 13.3 toolchain Signed-off-by: nihalpasham --- .../cuda-device/src/generated/async_copy.rs | 2 +- crates/cuda-device/src/generated/atomic.rs | 2 +- crates/cuda-device/src/generated/bf16.rs | 2 +- crates/cuda-device/src/generated/bf16x2.rs | 2 +- crates/cuda-device/src/generated/clc.rs | 2 +- .../src/generated/cluster_barrier.rs | 2 +- .../src/generated/cluster_memory.rs | 2 +- .../cuda-device/src/generated/cluster_sreg.rs | 2 +- crates/cuda-device/src/generated/convert.rs | 2 +- .../src/generated/counted_barrier.rs | 2 +- .../src/generated/debug_control.rs | 2 +- .../cuda-device/src/generated/debug_sreg.rs | 2 +- crates/cuda-device/src/generated/dotprod.rs | 2 +- crates/cuda-device/src/generated/f16.rs | 2 +- crates/cuda-device/src/generated/f16x2.rs | 2 +- crates/cuda-device/src/generated/f32x2.rs | 2 +- crates/cuda-device/src/generated/fence.rs | 2 +- crates/cuda-device/src/generated/float.rs | 2 +- .../src/generated/grid_dependency.rs | 2 +- crates/cuda-device/src/generated/grid_sreg.rs | 2 +- crates/cuda-device/src/generated/i16x2.rs | 2 +- crates/cuda-device/src/generated/int.rs | 2 +- crates/cuda-device/src/generated/ldmatrix.rs | 2 +- .../src/generated/mbarrier_basic.rs | 2 +- .../src/generated/mbarrier_extended.rs | 2 +- crates/cuda-device/src/generated/movmatrix.rs | 2 +- crates/cuda-device/src/generated/prmt.rs | 2 +- .../src/generated/register_control.rs | 2 +- .../cuda-device/src/generated/register_mma.rs | 2 +- .../cuda-device/src/generated/shared_sreg.rs | 2 +- .../cuda-device/src/generated/sparse_mma.rs | 2 +- crates/cuda-device/src/generated/sreg.rs | 2 +- crates/cuda-device/src/generated/stmatrix.rs | 2 +- crates/cuda-device/src/generated/tcgen05.rs | 2 +- crates/cuda-device/src/generated/tma.rs | 2 +- crates/cuda-device/src/generated/warp_sreg.rs | 2 +- .../src/generated/wgmma_control.rs | 2 +- .../cuda-intrinsics/src/generated/abi_v1.rs | 2 +- crates/cuda-intrinsics/src/generated/mod.rs | 2 +- .../active_mask.rs | 2 +- .../src/generated_intrinsic_targets/clc.rs | 2 +- .../cluster_barrier.rs | 2 +- .../cluster_memory.rs | 2 +- .../generated_intrinsic_targets/cp_async.rs | 2 +- .../debug_control.rs | 2 +- .../generated_intrinsic_targets/dotprod.rs | 2 +- .../src/generated_intrinsic_targets/elect.rs | 2 +- .../execution_control.rs | 2 +- .../extended_minmax.rs | 2 +- .../integer_minmax.rs | 2 +- .../generated_intrinsic_targets/ldmatrix.rs | 2 +- .../mbarrier_basic.rs | 2 +- .../mbarrier_extended.rs | 2 +- .../src/generated_intrinsic_targets/mod.rs | 2 +- .../generated_intrinsic_targets/movmatrix.rs | 2 +- .../generated_intrinsic_targets/packed_alu.rs | 2 +- .../packed_atomic.rs | 2 +- .../packed_conversion.rs | 2 +- .../src/generated_intrinsic_targets/prmt.rs | 2 +- .../src/generated_intrinsic_targets/redux.rs | 2 +- .../register_mma.rs | 2 +- .../scalar_arithmetic.rs | 2 +- .../scalar_conversion.rs | 2 +- .../scalar_math.rs | 2 +- .../generated_intrinsic_targets/sparse_mma.rs | 2 +- .../src/generated_intrinsic_targets/sreg.rs | 2 +- .../generated_intrinsic_targets/stmatrix.rs | 2 +- .../src/generated_intrinsic_targets/sync.rs | 2 +- .../generated_intrinsic_targets/tcgen05_cp.rs | 2 +- .../generated_intrinsic_targets/tcgen05_ld.rs | 2 +- .../tcgen05_mma.rs | 2 +- .../tcgen05_mma_ws.rs | 2 +- .../tcgen05_other.rs | 2 +- .../generated_intrinsic_targets/tcgen05_st.rs | 2 +- .../tests/active_mask.rs | 2 +- .../generated_intrinsic_targets/tests/clc.rs | 2 +- .../tests/cluster_barrier.rs | 2 +- .../tests/cluster_memory.rs | 2 +- .../tests/cp_async.rs | 2 +- .../tests/debug_control.rs | 2 +- .../tests/dotprod.rs | 2 +- .../tests/elect.rs | 2 +- .../tests/execution_control.rs | 2 +- .../tests/extended_minmax.rs | 2 +- .../tests/integer_minmax.rs | 2 +- .../tests/ldmatrix.rs | 2 +- .../tests/mbarrier_basic.rs | 2 +- .../tests/mbarrier_extended.rs | 2 +- .../generated_intrinsic_targets/tests/mod.rs | 2 +- .../tests/movmatrix.rs | 2 +- .../tests/packed_alu.rs | 2 +- .../tests/packed_atomic.rs | 2 +- .../tests/packed_conversion.rs | 2 +- .../generated_intrinsic_targets/tests/prmt.rs | 2 +- .../tests/redux.rs | 2 +- .../tests/register_mma_float.rs | 2 +- .../tests/register_mma_s32.rs | 2 +- .../tests/scalar_arithmetic.rs | 2 +- .../tests/scalar_conversion.rs | 2 +- .../tests/scalar_math.rs | 2 +- .../tests/sparse_mma.rs | 2 +- .../generated_intrinsic_targets/tests/sreg.rs | 2 +- .../tests/stmatrix.rs | 2 +- .../generated_intrinsic_targets/tests/sync.rs | 2 +- .../tests/tcgen05_cp.rs | 2 +- .../tests/tcgen05_ld.rs | 2 +- .../tests/tcgen05_mma.rs | 2 +- .../tests/tcgen05_mma_ws.rs | 2 +- .../tests/tcgen05_other.rs | 2 +- .../tests/tcgen05_st.rs | 2 +- .../generated_intrinsic_targets/tests/tma.rs | 2 +- .../generated_intrinsic_targets/tests/vote.rs | 2 +- .../tests/warp_barrier.rs | 2 +- .../tests/warp_match.rs | 2 +- .../tests/warp_shuffle.rs | 2 +- .../tests/wgmma_control.rs | 2 +- .../src/generated_intrinsic_targets/tma.rs | 2 +- .../src/generated_intrinsic_targets/vote.rs | 2 +- .../warp_barrier.rs | 2 +- .../generated_intrinsic_targets/warp_match.rs | 2 +- .../warp_shuffle.rs | 2 +- .../wgmma_control.rs | 2 +- .../src/ops/generated/active_mask.rs | 2 +- crates/dialect-nvvm/src/ops/generated/clc.rs | 2 +- .../src/ops/generated/cluster_barrier.rs | 2 +- .../src/ops/generated/cluster_memory.rs | 2 +- .../src/ops/generated/cp_async.rs | 2 +- .../src/ops/generated/debug_control.rs | 2 +- .../dialect-nvvm/src/ops/generated/dotprod.rs | 2 +- .../dialect-nvvm/src/ops/generated/elect.rs | 2 +- .../src/ops/generated/execution_control.rs | 2 +- .../src/ops/generated/extended_minmax.rs | 2 +- .../src/ops/generated/integer_minmax.rs | 2 +- .../src/ops/generated/ldmatrix.rs | 2 +- .../src/ops/generated/mbarrier_basic.rs | 2 +- .../src/ops/generated/mbarrier_extended.rs | 2 +- crates/dialect-nvvm/src/ops/generated/mod.rs | 2 +- .../src/ops/generated/movmatrix.rs | 2 +- .../src/ops/generated/packed_alu.rs | 2 +- .../src/ops/generated/packed_atomic.rs | 2 +- .../src/ops/generated/packed_conversion.rs | 2 +- crates/dialect-nvvm/src/ops/generated/prmt.rs | 2 +- .../dialect-nvvm/src/ops/generated/redux.rs | 2 +- .../src/ops/generated/register_mma.rs | 2 +- .../src/ops/generated/scalar_arithmetic.rs | 2 +- .../src/ops/generated/scalar_conversion.rs | 2 +- .../src/ops/generated/scalar_math.rs | 2 +- .../src/ops/generated/sparse_mma.rs | 2 +- crates/dialect-nvvm/src/ops/generated/sreg.rs | 2 +- .../src/ops/generated/stmatrix.rs | 2 +- crates/dialect-nvvm/src/ops/generated/sync.rs | 2 +- .../dialect-nvvm/src/ops/generated/tcgen05.rs | 2 +- crates/dialect-nvvm/src/ops/generated/tma.rs | 2 +- crates/dialect-nvvm/src/ops/generated/vote.rs | 2 +- .../src/ops/generated/warp_barrier.rs | 2 +- .../src/ops/generated/warp_match.rs | 2 +- .../src/ops/generated/warp_shuffle.rs | 2 +- .../src/ops/generated/wgmma_control.rs | 2 +- .../intrinsics/generated/active_mask.rs | 2 +- .../terminator/intrinsics/generated/clc.rs | 2 +- .../intrinsics/generated/cluster_barrier.rs | 2 +- .../intrinsics/generated/cluster_memory.rs | 2 +- .../intrinsics/generated/cp_async.rs | 2 +- .../intrinsics/generated/debug_control.rs | 2 +- .../intrinsics/generated/dotprod.rs | 2 +- .../terminator/intrinsics/generated/elect.rs | 2 +- .../intrinsics/generated/execution_control.rs | 2 +- .../intrinsics/generated/extended_minmax.rs | 2 +- .../intrinsics/generated/helpers.rs | 2 +- .../intrinsics/generated/integer_minmax.rs | 2 +- .../intrinsics/generated/ldmatrix.rs | 2 +- .../intrinsics/generated/mbarrier_basic.rs | 2 +- .../intrinsics/generated/mbarrier_extended.rs | 2 +- .../terminator/intrinsics/generated/mod.rs | 2 +- .../intrinsics/generated/movmatrix.rs | 2 +- .../intrinsics/generated/packed_alu.rs | 2 +- .../intrinsics/generated/packed_atomic.rs | 2 +- .../intrinsics/generated/packed_conversion.rs | 2 +- .../terminator/intrinsics/generated/prmt.rs | 2 +- .../terminator/intrinsics/generated/redux.rs | 2 +- .../intrinsics/generated/register_mma.rs | 2 +- .../intrinsics/generated/scalar_arithmetic.rs | 2 +- .../intrinsics/generated/scalar_conversion.rs | 2 +- .../intrinsics/generated/scalar_math.rs | 2 +- .../intrinsics/generated/sparse_mma.rs | 2 +- .../terminator/intrinsics/generated/sreg.rs | 2 +- .../intrinsics/generated/stmatrix.rs | 2 +- .../terminator/intrinsics/generated/sync.rs | 2 +- .../intrinsics/generated/tcgen05_cp.rs | 2 +- .../intrinsics/generated/tcgen05_ld.rs | 2 +- .../intrinsics/generated/tcgen05_mma.rs | 2 +- .../intrinsics/generated/tcgen05_other.rs | 2 +- .../intrinsics/generated/tcgen05_st.rs | 2 +- .../intrinsics/generated/tests/active_mask.rs | 2 +- .../intrinsics/generated/tests/clc.rs | 2 +- .../generated/tests/cluster_barrier.rs | 2 +- .../generated/tests/cluster_memory.rs | 2 +- .../intrinsics/generated/tests/cp_async.rs | 2 +- .../generated/tests/debug_control.rs | 2 +- .../intrinsics/generated/tests/dotprod.rs | 2 +- .../intrinsics/generated/tests/elect.rs | 2 +- .../generated/tests/execution_control.rs | 2 +- .../generated/tests/extended_minmax.rs | 2 +- .../generated/tests/integer_minmax.rs | 2 +- .../intrinsics/generated/tests/ldmatrix.rs | 2 +- .../generated/tests/mbarrier_basic.rs | 2 +- .../generated/tests/mbarrier_extended.rs | 2 +- .../intrinsics/generated/tests/mod.rs | 2 +- .../intrinsics/generated/tests/movmatrix.rs | 2 +- .../intrinsics/generated/tests/packed_alu.rs | 2 +- .../generated/tests/packed_atomic.rs | 2 +- .../generated/tests/packed_conversion.rs | 2 +- .../intrinsics/generated/tests/prmt.rs | 2 +- .../intrinsics/generated/tests/redux.rs | 2 +- .../generated/tests/register_mma.rs | 2 +- .../generated/tests/scalar_arithmetic.rs | 2 +- .../generated/tests/scalar_conversion.rs | 2 +- .../intrinsics/generated/tests/scalar_math.rs | 2 +- .../intrinsics/generated/tests/sparse_mma.rs | 2 +- .../intrinsics/generated/tests/sreg.rs | 2 +- .../intrinsics/generated/tests/stmatrix.rs | 2 +- .../intrinsics/generated/tests/sync.rs | 2 +- .../intrinsics/generated/tests/tcgen05.rs | 2 +- .../intrinsics/generated/tests/tma.rs | 2 +- .../intrinsics/generated/tests/vote.rs | 2 +- .../generated/tests/warp_barrier.rs | 2 +- .../intrinsics/generated/tests/warp_match.rs | 2 +- .../generated/tests/warp_shuffle.rs | 2 +- .../generated/tests/wgmma_control.rs | 2 +- .../terminator/intrinsics/generated/tma.rs | 2 +- .../terminator/intrinsics/generated/vote.rs | 2 +- .../intrinsics/generated/warp_barrier.rs | 2 +- .../intrinsics/generated/warp_match.rs | 2 +- .../intrinsics/generated/warp_shuffle.rs | 2 +- .../intrinsics/generated/wgmma_control.rs | 2 +- .../generated_intrinsics/active_mask.rs | 2 +- .../src/convert/generated_intrinsics/clc.rs | 2 +- .../generated_intrinsics/cluster_barrier.rs | 2 +- .../generated_intrinsics/cluster_memory.rs | 2 +- .../convert/generated_intrinsics/cp_async.rs | 2 +- .../generated_intrinsics/debug_control.rs | 2 +- .../convert/generated_intrinsics/dotprod.rs | 2 +- .../src/convert/generated_intrinsics/elect.rs | 2 +- .../generated_intrinsics/execution_control.rs | 2 +- .../generated_intrinsics/extended_minmax.rs | 2 +- .../generated_intrinsics/integer_minmax.rs | 2 +- .../convert/generated_intrinsics/ldmatrix.rs | 2 +- .../generated_intrinsics/mbarrier_basic.rs | 2 +- .../generated_intrinsics/mbarrier_extended.rs | 2 +- .../src/convert/generated_intrinsics/mod.rs | 2 +- .../convert/generated_intrinsics/movmatrix.rs | 2 +- .../generated_intrinsics/packed_alu.rs | 2 +- .../generated_intrinsics/packed_atomic.rs | 2 +- .../generated_intrinsics/packed_conversion.rs | 2 +- .../src/convert/generated_intrinsics/prmt.rs | 2 +- .../src/convert/generated_intrinsics/redux.rs | 2 +- .../generated_intrinsics/register_mma.rs | 2 +- .../generated_intrinsics/scalar_arithmetic.rs | 2 +- .../generated_intrinsics/scalar_conversion.rs | 2 +- .../generated_intrinsics/scalar_math.rs | 2 +- .../generated_intrinsics/sparse_mma.rs | 2 +- .../src/convert/generated_intrinsics/sreg.rs | 2 +- .../convert/generated_intrinsics/stmatrix.rs | 2 +- .../src/convert/generated_intrinsics/sync.rs | 2 +- .../convert/generated_intrinsics/tcgen05.rs | 2 +- .../src/convert/generated_intrinsics/tma.rs | 2 +- .../src/convert/generated_intrinsics/vote.rs | 2 +- .../generated_intrinsics/warp_barrier.rs | 2 +- .../generated_intrinsics/warp_match.rs | 2 +- .../generated_intrinsics/warp_shuffle.rs | 2 +- .../generated_intrinsics/wgmma_control.rs | 2 +- .../src/generated_intrinsics.rs | 2 +- intrinsics/catalog.json | 470 +++++++++--------- ...3.33-sparse-mma-ordered-ampere-float.json} | 21 +- ...96adc-sparse-mma-ordered-ampere-float.json | 4 +- intrinsics/generated-reference.md | 114 ++--- .../sparse_mma_ordered_ampere_float.toml | 2 +- intrinsics/probes/abs_bf16x2.ll | 2 +- intrinsics/probes/abs_f16x2.ll | 2 +- intrinsics/probes/active_mask.ll | 2 +- intrinsics/probes/add_bf16x2.ll | 2 +- intrinsics/probes/add_f16x2.ll | 2 +- intrinsics/probes/add_f32x2.ll | 2 +- intrinsics/probes/add_ftz_f32x2.ll | 2 +- intrinsics/probes/add_rm_f32.ll | 2 +- intrinsics/probes/add_rm_f64.ll | 2 +- intrinsics/probes/add_rm_ftz_f32.ll | 2 +- intrinsics/probes/add_rm_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rm_sat_f32.ll | 2 +- intrinsics/probes/add_rn_f32.ll | 2 +- intrinsics/probes/add_rn_f64.ll | 2 +- intrinsics/probes/add_rn_ftz_f32.ll | 2 +- intrinsics/probes/add_rn_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rn_sat_f32.ll | 2 +- intrinsics/probes/add_rp_f32.ll | 2 +- intrinsics/probes/add_rp_f64.ll | 2 +- intrinsics/probes/add_rp_ftz_f32.ll | 2 +- intrinsics/probes/add_rp_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rp_sat_f32.ll | 2 +- intrinsics/probes/add_rz_f32.ll | 2 +- intrinsics/probes/add_rz_f64.ll | 2 +- intrinsics/probes/add_rz_ftz_f32.ll | 2 +- intrinsics/probes/add_rz_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rz_sat_f32.ll | 2 +- intrinsics/probes/all_sync.ll | 2 +- intrinsics/probes/any_sync.ll | 2 +- intrinsics/probes/ballot_sync.ll | 2 +- intrinsics/probes/barrier_cluster_arrive.ll | 2 +- .../probes/barrier_cluster_arrive_aligned.ll | 2 +- .../probes/barrier_cluster_arrive_relaxed.ll | 2 +- .../barrier_cluster_arrive_relaxed_aligned.ll | 2 +- intrinsics/probes/barrier_cluster_wait.ll | 2 +- .../probes/barrier_cluster_wait_aligned.ll | 2 +- intrinsics/probes/barrier_cta_arrive.ll | 2 +- .../probes/barrier_cta_arrive_aligned.ll | 2 +- intrinsics/probes/barrier_cta_sync.ll | 2 +- intrinsics/probes/barrier_cta_sync_aligned.ll | 2 +- intrinsics/probes/block_dim_x.ll | 2 +- intrinsics/probes/block_dim_y.ll | 2 +- intrinsics/probes/block_dim_z.ll | 2 +- intrinsics/probes/block_idx_x.ll | 2 +- intrinsics/probes/block_idx_y.ll | 2 +- intrinsics/probes/block_idx_z.ll | 2 +- intrinsics/probes/breakpoint.ll | 2 +- .../probes/clc_query_get_first_ctaid_x.ll | 2 +- .../probes/clc_query_get_first_ctaid_y.ll | 2 +- .../probes/clc_query_get_first_ctaid_z.ll | 2 +- intrinsics/probes/clc_query_is_canceled.ll | 2 +- intrinsics/probes/clc_try_cancel.ll | 2 +- intrinsics/probes/clc_try_cancel_multicast.ll | 2 +- intrinsics/probes/clock.lib_nvvm.ll | 2 +- intrinsics/probes/clock.llvm_nvptx.ll | 2 +- intrinsics/probes/clock64.lib_nvvm.ll | 2 +- intrinsics/probes/clock64.llvm_nvptx.ll | 2 +- intrinsics/probes/cluster_block_count.ll | 2 +- intrinsics/probes/cluster_block_idx_x.ll | 2 +- intrinsics/probes/cluster_block_idx_y.ll | 2 +- intrinsics/probes/cluster_block_idx_z.ll | 2 +- intrinsics/probes/cluster_block_rank.ll | 2 +- intrinsics/probes/cluster_dim_x.ll | 2 +- intrinsics/probes/cluster_dim_y.ll | 2 +- intrinsics/probes/cluster_dim_z.ll | 2 +- intrinsics/probes/cluster_grid_dim_x.ll | 2 +- intrinsics/probes/cluster_grid_dim_y.ll | 2 +- intrinsics/probes/cluster_grid_dim_z.ll | 2 +- intrinsics/probes/cluster_idx_x.ll | 2 +- intrinsics/probes/cluster_idx_y.ll | 2 +- intrinsics/probes/cluster_idx_z.ll | 2 +- intrinsics/probes/cos_approx_f32.ll | 2 +- intrinsics/probes/cos_approx_ftz_f32.ll | 2 +- .../probes/cp_async_bulk_commit_group.ll | 2 +- .../cp_async_bulk_prefetch_tensor_1d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_1d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_2d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_2d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_3d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_3d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_4d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_4d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_5d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_5d_l2_cache_hint.ll | 2 +- ...sync_bulk_prefetch_tensor_gather4_2d_l2.ll | 2 +- ...refetch_tensor_gather4_2d_l2_cache_hint.ll | 2 +- .../probes/cp_async_bulk_tensor_1d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_1d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_2d_g2s.ll | 2 +- .../cp_async_bulk_tensor_2d_g2s_multicast.ll | 2 +- ..._async_bulk_tensor_2d_g2s_multicast_cg2.ll | 2 +- .../probes/cp_async_bulk_tensor_2d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_3d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_3d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_4d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_4d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_5d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_5d_s2g.ll | 2 +- ..._async_bulk_tensor_reduce_add_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_add_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_add_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_and_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_and_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_and_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_dec_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_dec_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_dec_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_inc_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_inc_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_inc_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_max_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_max_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_max_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_min_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_min_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_min_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_5d.ll | 2 +- ...p_async_bulk_tensor_reduce_or_im2col_3d.ll | 2 +- ...p_async_bulk_tensor_reduce_or_im2col_4d.ll | 2 +- ...p_async_bulk_tensor_reduce_or_im2col_5d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_1d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_2d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_3d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_4d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_xor_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_xor_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_xor_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_5d.ll | 2 +- intrinsics/probes/cp_async_bulk_wait_group.ll | 2 +- .../probes/cp_async_bulk_wait_group_read.ll | 2 +- intrinsics/probes/cp_async_ca_16.ll | 2 +- intrinsics/probes/cp_async_ca_4.ll | 2 +- intrinsics/probes/cp_async_ca_8.ll | 2 +- intrinsics/probes/cp_async_ca_zfill_16.ll | 2 +- intrinsics/probes/cp_async_ca_zfill_4.ll | 2 +- intrinsics/probes/cp_async_ca_zfill_8.ll | 2 +- intrinsics/probes/cp_async_cg_16.ll | 2 +- intrinsics/probes/cp_async_cg_zfill_16.ll | 2 +- intrinsics/probes/cp_async_commit_group.ll | 2 +- intrinsics/probes/cp_async_mbarrier_arrive.ll | 2 +- .../probes/cp_async_mbarrier_arrive_noinc.ll | 2 +- .../cp_async_mbarrier_arrive_noinc_shared.ll | 2 +- .../probes/cp_async_mbarrier_arrive_shared.ll | 2 +- intrinsics/probes/cp_async_wait_all.ll | 2 +- intrinsics/probes/cp_async_wait_group.ll | 2 +- intrinsics/probes/cvt_f16x2_f32.ll | 2 +- intrinsics/probes/cvt_f32x2_bf16x2.ll | 2 +- intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll | 2 +- intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll | 2 +- intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll | 2 +- intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll | 2 +- intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll | 2 +- intrinsics/probes/cvt_rn_relu_f16x2_f32.ll | 2 +- .../probes/cvt_rn_relu_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rn_relu_tf32_f32.ll | 2 +- .../probes/cvt_rn_satfinite_e4m3x2_f16x2.ll | 2 +- .../probes/cvt_rn_satfinite_e4m3x2_f32.ll | 2 +- .../probes/cvt_rn_satfinite_e5m2x2_f16x2.ll | 2 +- .../probes/cvt_rn_satfinite_e5m2x2_f32.ll | 2 +- .../cvt_rn_satfinite_relu_e4m3x2_f16x2.ll | 2 +- .../cvt_rn_satfinite_relu_e4m3x2_f32.ll | 2 +- .../cvt_rn_satfinite_relu_e5m2x2_f16x2.ll | 2 +- .../cvt_rn_satfinite_relu_e5m2x2_f32.ll | 2 +- .../probes/cvt_rn_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rn_tf32_f32.ll | 2 +- .../probes/cvt_rna_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rna_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rz_bf16x2_f32.ll | 2 +- intrinsics/probes/cvt_rz_f16x2_f32.ll | 2 +- .../probes/cvt_rz_relu_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rz_relu_tf32_f32.ll | 2 +- .../probes/cvt_rz_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rz_tf32_f32.ll | 2 +- intrinsics/probes/div_rm_f32.ll | 2 +- intrinsics/probes/div_rm_f64.ll | 2 +- intrinsics/probes/div_rm_ftz_f32.ll | 2 +- intrinsics/probes/div_rn_f32.ll | 2 +- intrinsics/probes/div_rn_f64.ll | 2 +- intrinsics/probes/div_rn_ftz_f32.ll | 2 +- intrinsics/probes/div_rp_f32.ll | 2 +- intrinsics/probes/div_rp_f64.ll | 2 +- intrinsics/probes/div_rp_ftz_f32.ll | 2 +- intrinsics/probes/div_rz_f32.ll | 2 +- intrinsics/probes/div_rz_f64.ll | 2 +- intrinsics/probes/div_rz_ftz_f32.ll | 2 +- intrinsics/probes/dp2a_s32.ll | 2 +- intrinsics/probes/dp2a_u32.ll | 2 +- intrinsics/probes/dp4a_s32.ll | 2 +- intrinsics/probes/dp4a_u32.ll | 2 +- intrinsics/probes/dsmem_read_u32.ll | 2 +- .../probes/dynamic_smem_size.lib_nvvm.ll | 2 +- .../probes/dynamic_smem_size.llvm_nvptx.ll | 2 +- intrinsics/probes/elect_sync.lib_nvvm.ll | 2 +- intrinsics/probes/elect_sync.llvm_nvptx.ll | 2 +- intrinsics/probes/envreg1.lib_nvvm.ll | 2 +- intrinsics/probes/envreg1.llvm_nvptx.ll | 2 +- intrinsics/probes/envreg2.lib_nvvm.ll | 2 +- intrinsics/probes/envreg2.llvm_nvptx.ll | 2 +- intrinsics/probes/ex2_approx_f16.ll | 2 +- intrinsics/probes/ex2_approx_f32.ll | 2 +- intrinsics/probes/ex2_approx_ftz_f32.ll | 2 +- .../fence_mbarrier_init_release_cluster.ll | 2 +- ..._generic_acquire_shared_cluster_cluster.ll | 2 +- ...sync_generic_release_shared_cta_cluster.ll | 2 +- .../probes/fence_proxy_async_shared_cta.ll | 2 +- ...proxy_tensormap_generic_acquire_cluster.ll | 2 +- ...nce_proxy_tensormap_generic_acquire_cta.ll | 2 +- ...nce_proxy_tensormap_generic_acquire_gpu.ll | 2 +- ..._proxy_tensormap_generic_acquire_system.ll | 2 +- ...proxy_tensormap_generic_release_cluster.ll | 2 +- ...nce_proxy_tensormap_generic_release_cta.ll | 2 +- ...nce_proxy_tensormap_generic_release_gpu.ll | 2 +- ..._proxy_tensormap_generic_release_system.ll | 2 +- intrinsics/probes/fma_bf16x2.ll | 2 +- intrinsics/probes/fma_f16x2.ll | 2 +- intrinsics/probes/fma_f32x2.ll | 2 +- intrinsics/probes/fma_ftz_f16x2.ll | 2 +- intrinsics/probes/fma_ftz_f32x2.ll | 2 +- intrinsics/probes/fma_ftz_relu_f16x2.ll | 2 +- intrinsics/probes/fma_ftz_sat_f16x2.ll | 2 +- intrinsics/probes/fma_relu_bf16x2.ll | 2 +- intrinsics/probes/fma_relu_f16x2.ll | 2 +- intrinsics/probes/fma_rm_f32.ll | 2 +- intrinsics/probes/fma_rm_f64.ll | 2 +- intrinsics/probes/fma_rm_ftz_f32.ll | 2 +- intrinsics/probes/fma_rm_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rm_sat_f32.ll | 2 +- intrinsics/probes/fma_rn_f32.ll | 2 +- intrinsics/probes/fma_rn_f64.ll | 2 +- intrinsics/probes/fma_rn_ftz_f32.ll | 2 +- intrinsics/probes/fma_rn_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rn_sat_f32.ll | 2 +- intrinsics/probes/fma_rp_f32.ll | 2 +- intrinsics/probes/fma_rp_f64.ll | 2 +- intrinsics/probes/fma_rp_ftz_f32.ll | 2 +- intrinsics/probes/fma_rp_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rp_sat_f32.ll | 2 +- intrinsics/probes/fma_rz_f32.ll | 2 +- intrinsics/probes/fma_rz_f64.ll | 2 +- intrinsics/probes/fma_rz_ftz_f32.ll | 2 +- intrinsics/probes/fma_rz_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rz_sat_f32.ll | 2 +- intrinsics/probes/fma_sat_f16x2.ll | 2 +- intrinsics/probes/globaltimer.lib_nvvm.ll | 2 +- intrinsics/probes/globaltimer.llvm_nvptx.ll | 2 +- .../grid_dependency_launch_dependents.ll | 2 +- intrinsics/probes/grid_dependency_wait.ll | 2 +- intrinsics/probes/grid_dim_x.ll | 2 +- intrinsics/probes/grid_dim_y.ll | 2 +- intrinsics/probes/grid_dim_z.ll | 2 +- intrinsics/probes/gridid.lib_nvvm.ll | 2 +- intrinsics/probes/gridid.llvm_nvptx.ll | 2 +- intrinsics/probes/lane_id.ll | 2 +- intrinsics/probes/lanemask_eq.ll | 2 +- intrinsics/probes/lanemask_ge.ll | 2 +- intrinsics/probes/lanemask_gt.ll | 2 +- intrinsics/probes/lanemask_le.ll | 2 +- intrinsics/probes/lanemask_lt.ll | 2 +- .../probes/ldmatrix_m16n16_x1_trans_b8.ll | 2 +- ...dmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll | 2 +- ...dmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll | 2 +- .../probes/ldmatrix_m16n16_x2_trans_b8.ll | 2 +- ...dmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll | 2 +- ...dmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll | 2 +- .../ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll | 2 +- .../ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll | 2 +- .../ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll | 2 +- .../ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll | 2 +- .../ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll | 2 +- .../ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll | 2 +- intrinsics/probes/ldmatrix_m8n8_x1_b16.ll | 2 +- .../probes/ldmatrix_m8n8_x1_trans_b16.ll | 2 +- intrinsics/probes/ldmatrix_m8n8_x2_b16.ll | 2 +- .../probes/ldmatrix_m8n8_x2_trans_b16.ll | 2 +- intrinsics/probes/ldmatrix_m8n8_x4_b16.ll | 2 +- .../probes/ldmatrix_m8n8_x4_trans_b16.ll | 2 +- intrinsics/probes/lg2_approx_f32.ll | 2 +- intrinsics/probes/lg2_approx_ftz_f32.ll | 2 +- intrinsics/probes/map_shared_rank.ll | 2 +- intrinsics/probes/match_all_i64_sync.ll | 2 +- intrinsics/probes/match_all_sync.ll | 2 +- intrinsics/probes/match_any_i64_sync.ll | 2 +- intrinsics/probes/match_any_sync.ll | 2 +- intrinsics/probes/max_bf16.ll | 2 +- intrinsics/probes/max_bf16x2.ll | 2 +- intrinsics/probes/max_f16.ll | 2 +- intrinsics/probes/max_f16x2.ll | 2 +- intrinsics/probes/max_ftz_f16.ll | 2 +- intrinsics/probes/max_ftz_f16x2.ll | 2 +- intrinsics/probes/max_ftz_nan_f16.ll | 2 +- intrinsics/probes/max_ftz_nan_f16x2.ll | 2 +- .../probes/max_ftz_nan_xorsign_abs_f16.ll | 2 +- .../probes/max_ftz_nan_xorsign_abs_f16x2.ll | 2 +- .../probes/max_ftz_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/max_ftz_xorsign_abs_f16.ll | 2 +- .../probes/max_ftz_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/max_ftz_xorsign_abs_f32.ll | 2 +- intrinsics/probes/max_nan_bf16.ll | 2 +- intrinsics/probes/max_nan_bf16x2.ll | 2 +- intrinsics/probes/max_nan_f16.ll | 2 +- intrinsics/probes/max_nan_f16x2.ll | 2 +- intrinsics/probes/max_nan_xorsign_abs_bf16.ll | 2 +- .../probes/max_nan_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/max_nan_xorsign_abs_f16.ll | 2 +- .../probes/max_nan_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/max_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/max_relu_s16x2.ll | 2 +- intrinsics/probes/max_relu_s32.ll | 2 +- intrinsics/probes/max_s16x2.ll | 2 +- intrinsics/probes/max_u16x2.ll | 2 +- intrinsics/probes/max_xorsign_abs_bf16.ll | 2 +- intrinsics/probes/max_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/max_xorsign_abs_f16.ll | 2 +- intrinsics/probes/max_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/max_xorsign_abs_f32.ll | 2 +- intrinsics/probes/mbarrier_arrive.ll | 2 +- intrinsics/probes/mbarrier_arrive_cluster.ll | 2 +- .../probes/mbarrier_arrive_expect_tx.ll | 2 +- .../mbarrier_arrive_expect_tx_cluster.ll | 2 +- intrinsics/probes/mbarrier_init.ll | 2 +- intrinsics/probes/mbarrier_inval.ll | 2 +- intrinsics/probes/mbarrier_test_wait.ll | 2 +- intrinsics/probes/mbarrier_try_wait.ll | 2 +- intrinsics/probes/mbarrier_try_wait_parity.ll | 2 +- .../mbarrier_try_wait_parity_cluster.ll | 2 +- intrinsics/probes/min_bf16.ll | 2 +- intrinsics/probes/min_bf16x2.ll | 2 +- intrinsics/probes/min_f16.ll | 2 +- intrinsics/probes/min_f16x2.ll | 2 +- intrinsics/probes/min_ftz_f16.ll | 2 +- intrinsics/probes/min_ftz_f16x2.ll | 2 +- intrinsics/probes/min_ftz_nan_f16.ll | 2 +- intrinsics/probes/min_ftz_nan_f16x2.ll | 2 +- .../probes/min_ftz_nan_xorsign_abs_f16.ll | 2 +- .../probes/min_ftz_nan_xorsign_abs_f16x2.ll | 2 +- .../probes/min_ftz_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/min_ftz_xorsign_abs_f16.ll | 2 +- .../probes/min_ftz_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/min_ftz_xorsign_abs_f32.ll | 2 +- intrinsics/probes/min_nan_bf16.ll | 2 +- intrinsics/probes/min_nan_bf16x2.ll | 2 +- intrinsics/probes/min_nan_f16.ll | 2 +- intrinsics/probes/min_nan_f16x2.ll | 2 +- intrinsics/probes/min_nan_xorsign_abs_bf16.ll | 2 +- .../probes/min_nan_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/min_nan_xorsign_abs_f16.ll | 2 +- .../probes/min_nan_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/min_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/min_relu_s16x2.ll | 2 +- intrinsics/probes/min_relu_s32.ll | 2 +- intrinsics/probes/min_s16x2.ll | 2 +- intrinsics/probes/min_u16x2.ll | 2 +- intrinsics/probes/min_xorsign_abs_bf16.ll | 2 +- intrinsics/probes/min_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/min_xorsign_abs_f16.ll | 2 +- intrinsics/probes/min_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/min_xorsign_abs_f32.ll | 2 +- .../probes/mma_m16n8k128_s32_b1_and_popc.ll | 2 +- .../probes/mma_m16n8k128_s32_b1_xor_popc.ll | 2 +- intrinsics/probes/mma_m16n8k16_f16_f16.ll | 2 +- intrinsics/probes/mma_m16n8k16_f32_bf16.ll | 2 +- intrinsics/probes/mma_m16n8k16_f32_f16.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_s8.ll | 2 +- .../probes/mma_m16n8k16_s32_s8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll | 2 +- .../mma_m16n8k16_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_u8.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll | 2 +- .../mma_m16n8k16_s32_u8_s8_satfinite.ll | 2 +- .../probes/mma_m16n8k16_s32_u8_satfinite.ll | 2 +- .../probes/mma_m16n8k256_s32_b1_and_popc.ll | 2 +- .../probes/mma_m16n8k256_s32_b1_xor_popc.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s4.ll | 2 +- .../probes/mma_m16n8k32_s32_s4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll | 2 +- .../mma_m16n8k32_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s8.ll | 2 +- .../probes/mma_m16n8k32_s32_s8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll | 2 +- .../mma_m16n8k32_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u4.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll | 2 +- .../mma_m16n8k32_s32_u4_s4_satfinite.ll | 2 +- .../probes/mma_m16n8k32_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u8.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll | 2 +- .../mma_m16n8k32_s32_u8_s8_satfinite.ll | 2 +- .../probes/mma_m16n8k32_s32_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k4_f32_tf32.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_s4.ll | 2 +- .../probes/mma_m16n8k64_s32_s4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll | 2 +- .../mma_m16n8k64_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_u4.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll | 2 +- .../mma_m16n8k64_s32_u4_s4_satfinite.ll | 2 +- .../probes/mma_m16n8k64_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k8_f16_f16.ll | 2 +- intrinsics/probes/mma_m16n8k8_f32_bf16.ll | 2 +- intrinsics/probes/mma_m16n8k8_f32_f16.ll | 2 +- intrinsics/probes/mma_m16n8k8_f32_tf32.ll | 2 +- .../probes/mma_m8n8k128_s32_b1_and_popc.ll | 2 +- .../probes/mma_m8n8k128_s32_b1_xor_popc.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_s8.ll | 2 +- .../probes/mma_m8n8k16_s32_s8_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll | 2 +- .../probes/mma_m8n8k16_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_u8.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll | 2 +- .../probes/mma_m8n8k16_s32_u8_s8_satfinite.ll | 2 +- .../probes/mma_m8n8k16_s32_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_s4.ll | 2 +- .../probes/mma_m8n8k32_s32_s4_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll | 2 +- .../probes/mma_m8n8k32_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_u4.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll | 2 +- .../probes/mma_m8n8k32_s32_u4_s4_satfinite.ll | 2 +- .../probes/mma_m8n8k32_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k4_f64.ll | 2 +- intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll | 2 +- .../mma_sp_m16n8k128_s32_s4_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k128_s32_s4_u4.ll | 2 +- .../mma_sp_m16n8k128_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll | 2 +- .../probes/mma_sp_m16n8k128_s32_u4_s4.ll | 2 +- .../mma_sp_m16n8k128_s32_u4_s4_satfinite.ll | 2 +- .../mma_sp_m16n8k128_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll | 2 +- .../mma_sp_m16n8k32_s32_s8_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k32_s32_s8_u8.ll | 2 +- .../mma_sp_m16n8k32_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll | 2 +- .../probes/mma_sp_m16n8k32_s32_u8_s8.ll | 2 +- .../mma_sp_m16n8k32_s32_u8_s8_satfinite.ll | 2 +- .../mma_sp_m16n8k32_s32_u8_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll | 2 +- .../mma_sp_m16n8k64_s32_s4_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_s4_u4.ll | 2 +- .../mma_sp_m16n8k64_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll | 2 +- .../mma_sp_m16n8k64_s32_s8_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_s8_u8.ll | 2 +- .../mma_sp_m16n8k64_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_u4_s4.ll | 2 +- .../mma_sp_m16n8k64_s32_u4_s4_satfinite.ll | 2 +- .../mma_sp_m16n8k64_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_u8_s8.ll | 2 +- .../mma_sp_m16n8k64_s32_u8_s8_satfinite.ll | 2 +- .../mma_sp_m16n8k64_s32_u8_satfinite.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k128_s32_s4.ll | 2 +- ...red_metadata_m16n8k128_s32_s4_satfinite.ll | 2 +- ...sp_ordered_metadata_m16n8k128_s32_s4_u4.ll | 2 +- ..._metadata_m16n8k128_s32_s4_u4_satfinite.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k128_s32_u4.ll | 2 +- ...sp_ordered_metadata_m16n8k128_s32_u4_s4.ll | 2 +- ..._metadata_m16n8k128_s32_u4_s4_satfinite.ll | 2 +- ...red_metadata_m16n8k128_s32_u4_satfinite.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k16_f16_f16.ll | 2 +- ...a_sp_ordered_metadata_m16n8k16_f32_bf16.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k16_f32_f16.ll | 2 +- ...a_sp_ordered_metadata_m16n8k16_f32_tf32.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k32_f16_f16.ll | 2 +- ...a_sp_ordered_metadata_m16n8k32_f32_bf16.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k32_f32_f16.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k32_s32_s8.ll | 2 +- ...ered_metadata_m16n8k32_s32_s8_satfinite.ll | 2 +- ..._sp_ordered_metadata_m16n8k32_s32_s8_u8.ll | 2 +- ...d_metadata_m16n8k32_s32_s8_u8_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k32_s32_u8.ll | 2 +- ..._sp_ordered_metadata_m16n8k32_s32_u8_s8.ll | 2 +- ...d_metadata_m16n8k32_s32_u8_s8_satfinite.ll | 2 +- ...ered_metadata_m16n8k32_s32_u8_satfinite.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_s4.ll | 2 +- ...ered_metadata_m16n8k64_s32_s4_satfinite.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_s4_u4.ll | 2 +- ...d_metadata_m16n8k64_s32_s4_u4_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_s8.ll | 2 +- ...ered_metadata_m16n8k64_s32_s8_satfinite.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_s8_u8.ll | 2 +- ...d_metadata_m16n8k64_s32_s8_u8_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_u4.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_u4_s4.ll | 2 +- ...d_metadata_m16n8k64_s32_u4_s4_satfinite.ll | 2 +- ...ered_metadata_m16n8k64_s32_u4_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_u8.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_u8_s8.ll | 2 +- ...d_metadata_m16n8k64_s32_u8_s8_satfinite.ll | 2 +- ...ered_metadata_m16n8k64_s32_u8_satfinite.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k8_f32_tf32.ll | 2 +- intrinsics/probes/movmatrix_trans_b16.ll | 2 +- intrinsics/probes/mul_bf16x2.ll | 2 +- intrinsics/probes/mul_f16x2.ll | 2 +- intrinsics/probes/mul_f32x2.ll | 2 +- intrinsics/probes/mul_ftz_f32x2.ll | 2 +- intrinsics/probes/mul_rm_f32.ll | 2 +- intrinsics/probes/mul_rm_f64.ll | 2 +- intrinsics/probes/mul_rm_ftz_f32.ll | 2 +- intrinsics/probes/mul_rn_f32.ll | 2 +- intrinsics/probes/mul_rn_f64.ll | 2 +- intrinsics/probes/mul_rn_ftz_f32.ll | 2 +- intrinsics/probes/mul_rp_f32.ll | 2 +- intrinsics/probes/mul_rp_f64.ll | 2 +- intrinsics/probes/mul_rp_ftz_f32.ll | 2 +- intrinsics/probes/mul_rz_f32.ll | 2 +- intrinsics/probes/mul_rz_f64.ll | 2 +- intrinsics/probes/mul_rz_ftz_f32.ll | 2 +- intrinsics/probes/nanosleep.ll | 2 +- intrinsics/probes/neg_bf16x2.ll | 2 +- intrinsics/probes/neg_f16x2.ll | 2 +- intrinsics/probes/nsmid.lib_nvvm.ll | 2 +- intrinsics/probes/nsmid.llvm_nvptx.ll | 2 +- intrinsics/probes/nwarpid.lib_nvvm.ll | 2 +- intrinsics/probes/nwarpid.llvm_nvptx.ll | 2 +- intrinsics/probes/packed_atomic_add_bf16x2.ll | 2 +- intrinsics/probes/packed_atomic_add_f16x2.ll | 2 +- intrinsics/probes/pmevent.ll | 2 +- intrinsics/probes/prefetch_tma_descriptor.ll | 2 +- intrinsics/probes/prmt.ll | 2 +- intrinsics/probes/prmt_b4e.ll | 2 +- intrinsics/probes/prmt_ecl.ll | 2 +- intrinsics/probes/prmt_ecr.ll | 2 +- intrinsics/probes/prmt_f4e.ll | 2 +- intrinsics/probes/prmt_rc16.ll | 2 +- intrinsics/probes/prmt_rc8.ll | 2 +- intrinsics/probes/rcp_approx_ftz_f32.ll | 2 +- intrinsics/probes/rcp_approx_ftz_f64.ll | 2 +- intrinsics/probes/rcp_rm_f32.ll | 2 +- intrinsics/probes/rcp_rm_f64.ll | 2 +- intrinsics/probes/rcp_rm_ftz_f32.ll | 2 +- intrinsics/probes/rcp_rn_f32.ll | 2 +- intrinsics/probes/rcp_rn_f64.ll | 2 +- intrinsics/probes/rcp_rn_ftz_f32.ll | 2 +- intrinsics/probes/rcp_rp_f32.ll | 2 +- intrinsics/probes/rcp_rp_f64.ll | 2 +- intrinsics/probes/rcp_rp_ftz_f32.ll | 2 +- intrinsics/probes/rcp_rz_f32.ll | 2 +- intrinsics/probes/rcp_rz_f64.ll | 2 +- intrinsics/probes/rcp_rz_ftz_f32.ll | 2 +- intrinsics/probes/redux_sync_add.ll | 2 +- intrinsics/probes/redux_sync_and.ll | 2 +- intrinsics/probes/redux_sync_max_abs_f32.ll | 2 +- .../probes/redux_sync_max_abs_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_max_f32.ll | 2 +- intrinsics/probes/redux_sync_max_i32.ll | 2 +- intrinsics/probes/redux_sync_max_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_max_u32.ll | 2 +- intrinsics/probes/redux_sync_min_abs_f32.ll | 2 +- .../probes/redux_sync_min_abs_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_min_f32.ll | 2 +- intrinsics/probes/redux_sync_min_i32.ll | 2 +- intrinsics/probes/redux_sync_min_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_min_u32.ll | 2 +- intrinsics/probes/redux_sync_or.ll | 2 +- intrinsics/probes/redux_sync_xor.ll | 2 +- intrinsics/probes/rsqrt_approx_f32.ll | 2 +- intrinsics/probes/rsqrt_approx_f64.ll | 2 +- intrinsics/probes/rsqrt_approx_ftz_f32.ll | 2 +- intrinsics/probes/setmaxnreg_dec.ll | 2 +- intrinsics/probes/setmaxnreg_inc.ll | 2 +- intrinsics/probes/shuffle_down_f32_sync.ll | 2 +- intrinsics/probes/shuffle_down_sync.ll | 2 +- intrinsics/probes/shuffle_down_u64_sync.ll | 2 +- intrinsics/probes/shuffle_f32_sync.ll | 2 +- intrinsics/probes/shuffle_sync.ll | 2 +- intrinsics/probes/shuffle_u64_sync.ll | 2 +- intrinsics/probes/shuffle_up_f32_sync.ll | 2 +- intrinsics/probes/shuffle_up_sync.ll | 2 +- intrinsics/probes/shuffle_up_u64_sync.ll | 2 +- intrinsics/probes/shuffle_xor_f32_sync.ll | 2 +- intrinsics/probes/shuffle_xor_sync.ll | 2 +- intrinsics/probes/shuffle_xor_u64_sync.ll | 2 +- intrinsics/probes/sin_approx_f32.ll | 2 +- intrinsics/probes/sin_approx_ftz_f32.ll | 2 +- intrinsics/probes/smid.lib_nvvm.ll | 2 +- intrinsics/probes/smid.llvm_nvptx.ll | 2 +- intrinsics/probes/sqrt_approx_f32.ll | 2 +- intrinsics/probes/sqrt_approx_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rm_f32.ll | 2 +- intrinsics/probes/sqrt_rm_f64.ll | 2 +- intrinsics/probes/sqrt_rm_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rn_f32.ll | 2 +- intrinsics/probes/sqrt_rn_f64.ll | 2 +- intrinsics/probes/sqrt_rn_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rp_f32.ll | 2 +- intrinsics/probes/sqrt_rp_f64.ll | 2 +- intrinsics/probes/sqrt_rp_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rz_f32.ll | 2 +- intrinsics/probes/sqrt_rz_f64.ll | 2 +- intrinsics/probes/sqrt_rz_ftz_f32.ll | 2 +- intrinsics/probes/stmatrix_m8n8_x2_b16.ll | 2 +- .../probes/stmatrix_m8n8_x2_trans_b16.ll | 2 +- intrinsics/probes/stmatrix_m8n8_x4_b16.ll | 2 +- .../probes/stmatrix_m8n8_x4_trans_b16.ll | 2 +- intrinsics/probes/sub_bf16x2.ll | 2 +- intrinsics/probes/sub_f16x2.ll | 2 +- intrinsics/probes/sub_f32x2.ll | 2 +- intrinsics/probes/sub_ftz_f32x2.ll | 2 +- intrinsics/probes/sync_mask.ll | 2 +- intrinsics/probes/sync_threads.ll | 2 +- intrinsics/probes/tanh_approx_f32.ll | 2 +- intrinsics/probes/tcgen05_alloc.ll | 2 +- intrinsics/probes/tcgen05_alloc_cg2.ll | 2 +- intrinsics/probes/tcgen05_commit.ll | 2 +- intrinsics/probes/tcgen05_commit_cg2.ll | 2 +- intrinsics/probes/tcgen05_commit_multicast.ll | 2 +- .../probes/tcgen05_commit_multicast_cg2.ll | 2 +- .../probes/tcgen05_commit_shared_cluster.ll | 2 +- .../tcgen05_commit_shared_cluster_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_128x128b.ll | 2 +- .../probes/tcgen05_cp_128x128b_b4x16_p64.ll | 2 +- .../tcgen05_cp_128x128b_b4x16_p64_cg2.ll | 2 +- .../probes/tcgen05_cp_128x128b_b6x16_p32.ll | 2 +- .../tcgen05_cp_128x128b_b6x16_p32_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_128x128b_cg2.ll | 2 +- .../probes/tcgen05_cp_128x256b_b4x16_p64.ll | 2 +- .../tcgen05_cp_128x256b_b4x16_p64_cg2.ll | 2 +- .../probes/tcgen05_cp_128x256b_b6x16_p32.ll | 2 +- .../tcgen05_cp_128x256b_b6x16_p32_cg2.ll | 2 +- .../probes/tcgen05_cp_32x128b_warpx4.ll | 2 +- .../tcgen05_cp_32x128b_warpx4_b4x16_p64.ll | 2 +- ...tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll | 2 +- .../tcgen05_cp_32x128b_warpx4_b6x16_p32.ll | 2 +- ...tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll | 2 +- .../probes/tcgen05_cp_32x128b_warpx4_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_4x256b.ll | 2 +- .../probes/tcgen05_cp_4x256b_b4x16_p64.ll | 2 +- .../probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll | 2 +- .../probes/tcgen05_cp_4x256b_b6x16_p32.ll | 2 +- .../probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_4x256b_cg2.ll | 2 +- .../probes/tcgen05_cp_64x128b_warpx2_01_23.ll | 2 +- ...gen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll | 2 +- ...5_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll | 2 +- ...gen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll | 2 +- ...5_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll | 2 +- .../tcgen05_cp_64x128b_warpx2_01_23_cg2.ll | 2 +- .../probes/tcgen05_cp_64x128b_warpx2_02_13.ll | 2 +- ...gen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll | 2 +- ...5_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll | 2 +- ...gen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll | 2 +- ...5_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll | 2 +- .../tcgen05_cp_64x128b_warpx2_02_13_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_smem_to_tmem.ll | 2 +- .../probes/tcgen05_cp_smem_to_tmem_cg2.ll | 2 +- intrinsics/probes/tcgen05_dealloc.ll | 2 +- intrinsics/probes/tcgen05_dealloc_cg2.ll | 2 +- .../probes/tcgen05_fence_after_thread_sync.ll | 2 +- .../tcgen05_fence_before_thread_sync.ll | 2 +- .../probes/tcgen05_ld_16x128b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x1_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x2_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x4_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x64_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x8_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x8_raw.ll | 2 +- intrinsics/probes/tcgen05_ld_16x256b_pure.ll | 2 +- .../probes/tcgen05_ld_16x256b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x1_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x2_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x4_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x8_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x8_pure.ll | 2 +- .../probes/tcgen05_ld_16x256b_x8_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x128_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x128_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x1_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x2_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x4_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x64_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x8_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x8_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x128_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x128_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x1_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x2_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x4_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x64_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x8_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x128_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x128_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x1_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x2_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x4_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x64_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x8_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll | 2 +- intrinsics/probes/tcgen05_load_wait.ll | 2 +- intrinsics/probes/tcgen05_mma_e2m1.ll | 2 +- intrinsics/probes/tcgen05_mma_e2m3.ll | 2 +- intrinsics/probes/tcgen05_mma_e3m2.ll | 2 +- intrinsics/probes/tcgen05_mma_e4m3.ll | 2 +- intrinsics/probes/tcgen05_mma_e5m2.ll | 2 +- intrinsics/probes/tcgen05_mma_f16.ll | 2 +- intrinsics/probes/tcgen05_mma_f16_cg2.ll | 2 +- intrinsics/probes/tcgen05_mma_shared.ll | 2 +- intrinsics/probes/tcgen05_mma_sp_shared.ll | 2 +- intrinsics/probes/tcgen05_mma_sp_tensor.ll | 2 +- .../probes/tcgen05_mma_sp_tensor_ashift.ll | 2 +- intrinsics/probes/tcgen05_mma_tensor.ll | 2 +- .../probes/tcgen05_mma_tensor_ashift.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_bf16.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e2m1.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e2m3.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e3m2.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e4m3.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e5m2.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_f16.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_shared.ll | 2 +- .../tcgen05_mma_ws_shared_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_sp_shared.ll | 2 +- .../tcgen05_mma_ws_sp_shared_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll | 2 +- .../tcgen05_mma_ws_sp_tensor_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_tensor.ll | 2 +- .../tcgen05_mma_ws_tensor_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_tf32.ll | 2 +- .../probes/tcgen05_relinquish_alloc_permit.ll | 2 +- .../tcgen05_relinquish_alloc_permit_cg2.ll | 2 +- intrinsics/probes/tcgen05_shift_down.ll | 2 +- intrinsics/probes/tcgen05_shift_down_cg2.ll | 2 +- .../probes/tcgen05_st_16x128b_x16_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x16_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x1_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x32_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x32_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x64_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x64_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x16_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x16_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x1_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x32_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x32_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x128_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x128_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x16_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x16_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x1_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x32_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x32_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x64_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x64_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x128_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x128_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x16_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x16_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x1_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x32_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x32_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x64_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x64_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x128_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x128_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x16_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x16_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x1_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x32_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x32_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x64_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x64_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x8_unpack16.ll | 2 +- intrinsics/probes/tcgen05_store_wait.ll | 2 +- .../probes/tensormap_replace_box_dim.ll | 2 +- .../tensormap_replace_element_stride.ll | 2 +- .../probes/tensormap_replace_element_type.ll | 2 +- .../probes/tensormap_replace_fill_mode.ll | 2 +- .../tensormap_replace_global_address.ll | 2 +- .../probes/tensormap_replace_global_dim.ll | 2 +- .../probes/tensormap_replace_global_stride.ll | 2 +- .../tensormap_replace_interleave_layout.ll | 2 +- intrinsics/probes/tensormap_replace_rank.ll | 2 +- .../tensormap_replace_swizzle_atomicity.ll | 2 +- .../probes/tensormap_replace_swizzle_mode.ll | 2 +- intrinsics/probes/thread_idx_x.ll | 2 +- intrinsics/probes/thread_idx_y.ll | 2 +- intrinsics/probes/thread_idx_z.ll | 2 +- intrinsics/probes/threadfence.ll | 2 +- intrinsics/probes/threadfence_block.ll | 2 +- intrinsics/probes/threadfence_system.ll | 2 +- intrinsics/probes/total_smem_size.lib_nvvm.ll | 2 +- .../probes/total_smem_size.llvm_nvptx.ll | 2 +- intrinsics/probes/trap.ll | 2 +- intrinsics/probes/uni_sync.ll | 2 +- intrinsics/probes/warpid.lib_nvvm.ll | 2 +- intrinsics/probes/warpid.llvm_nvptx.ll | 2 +- intrinsics/probes/wgmma_commit_group.ll | 2 +- intrinsics/probes/wgmma_fence.ll | 2 +- intrinsics/probes/wgmma_wait_group.ll | 2 +- 1314 files changed, 1615 insertions(+), 1614 deletions(-) rename intrinsics/evidence/{cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json => cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-ampere-float.json} (67%) diff --git a/crates/cuda-device/src/generated/async_copy.rs b/crates/cuda-device/src/generated/async_copy.rs index d809303ec0..ab1f8a49d9 100644 --- a/crates/cuda-device/src/generated/async_copy.rs +++ b/crates/cuda-device/src/generated/async_copy.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::async_copy` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/atomic.rs b/crates/cuda-device/src/generated/atomic.rs index 53ae318ebb..e97ab82c90 100644 --- a/crates/cuda-device/src/generated/atomic.rs +++ b/crates/cuda-device/src/generated/atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::atomic` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/bf16.rs b/crates/cuda-device/src/generated/bf16.rs index 14b3f41c2b..4ef5d627c0 100644 --- a/crates/cuda-device/src/generated/bf16.rs +++ b/crates/cuda-device/src/generated/bf16.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::bf16` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/bf16x2.rs b/crates/cuda-device/src/generated/bf16x2.rs index d2cff751b1..e0c0e2b52c 100644 --- a/crates/cuda-device/src/generated/bf16x2.rs +++ b/crates/cuda-device/src/generated/bf16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::bf16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/clc.rs b/crates/cuda-device/src/generated/clc.rs index 956c76e059..1b088f2c1f 100644 --- a/crates/cuda-device/src/generated/clc.rs +++ b/crates/cuda-device/src/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::clc` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/cluster_barrier.rs b/crates/cuda-device/src/generated/cluster_barrier.rs index 06bc450ee1..617c83b9c4 100644 --- a/crates/cuda-device/src/generated/cluster_barrier.rs +++ b/crates/cuda-device/src/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::cluster` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/cluster_memory.rs b/crates/cuda-device/src/generated/cluster_memory.rs index 88a6303130..8805303983 100644 --- a/crates/cuda-device/src/generated/cluster_memory.rs +++ b/crates/cuda-device/src/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::cluster` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/cluster_sreg.rs b/crates/cuda-device/src/generated/cluster_sreg.rs index 196f93d1ce..644dff1ba7 100644 --- a/crates/cuda-device/src/generated/cluster_sreg.rs +++ b/crates/cuda-device/src/generated/cluster_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // This file is included inside `cuda_device::cluster`. diff --git a/crates/cuda-device/src/generated/convert.rs b/crates/cuda-device/src/generated/convert.rs index 958965b171..bcb55470be 100644 --- a/crates/cuda-device/src/generated/convert.rs +++ b/crates/cuda-device/src/generated/convert.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::convert`. diff --git a/crates/cuda-device/src/generated/counted_barrier.rs b/crates/cuda-device/src/generated/counted_barrier.rs index 189a1aeba0..78acdf1c22 100644 --- a/crates/cuda-device/src/generated/counted_barrier.rs +++ b/crates/cuda-device/src/generated/counted_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::barrier` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/debug_control.rs b/crates/cuda-device/src/generated/debug_control.rs index 2de9de5b20..969da8904b 100644 --- a/crates/cuda-device/src/generated/debug_control.rs +++ b/crates/cuda-device/src/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::debug` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/debug_sreg.rs b/crates/cuda-device/src/generated/debug_sreg.rs index d8e4136bb4..f2f9e20676 100644 --- a/crates/cuda-device/src/generated/debug_sreg.rs +++ b/crates/cuda-device/src/generated/debug_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::debug` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/dotprod.rs b/crates/cuda-device/src/generated/dotprod.rs index 7d35a4fdbc..8e57347978 100644 --- a/crates/cuda-device/src/generated/dotprod.rs +++ b/crates/cuda-device/src/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::dotprod` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f16.rs b/crates/cuda-device/src/generated/f16.rs index b9dd89fc75..b26ad5d631 100644 --- a/crates/cuda-device/src/generated/f16.rs +++ b/crates/cuda-device/src/generated/f16.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::f16` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f16x2.rs b/crates/cuda-device/src/generated/f16x2.rs index b505506b3f..edf33d262d 100644 --- a/crates/cuda-device/src/generated/f16x2.rs +++ b/crates/cuda-device/src/generated/f16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::f16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f32x2.rs b/crates/cuda-device/src/generated/f32x2.rs index ce8aebc9d4..dcfe84f5a5 100644 --- a/crates/cuda-device/src/generated/f32x2.rs +++ b/crates/cuda-device/src/generated/f32x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::f32x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/fence.rs b/crates/cuda-device/src/generated/fence.rs index d92cd22c1d..c986f3412a 100644 --- a/crates/cuda-device/src/generated/fence.rs +++ b/crates/cuda-device/src/generated/fence.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // This file is included inside `cuda_device::fence` so existing paths stay stable. diff --git a/crates/cuda-device/src/generated/float.rs b/crates/cuda-device/src/generated/float.rs index a750a7cc9a..4f32f1fcf6 100644 --- a/crates/cuda-device/src/generated/float.rs +++ b/crates/cuda-device/src/generated/float.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::float`. diff --git a/crates/cuda-device/src/generated/grid_dependency.rs b/crates/cuda-device/src/generated/grid_dependency.rs index ca5049aed1..81727168a4 100644 --- a/crates/cuda-device/src/generated/grid_dependency.rs +++ b/crates/cuda-device/src/generated/grid_dependency.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::grid` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/grid_sreg.rs b/crates/cuda-device/src/generated/grid_sreg.rs index c821995683..bb99c12e3a 100644 --- a/crates/cuda-device/src/generated/grid_sreg.rs +++ b/crates/cuda-device/src/generated/grid_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::grid` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/i16x2.rs b/crates/cuda-device/src/generated/i16x2.rs index 11aa22604c..65fce550a6 100644 --- a/crates/cuda-device/src/generated/i16x2.rs +++ b/crates/cuda-device/src/generated/i16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::i16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/int.rs b/crates/cuda-device/src/generated/int.rs index 869f7fee07..6e2067ae4f 100644 --- a/crates/cuda-device/src/generated/int.rs +++ b/crates/cuda-device/src/generated/int.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::int` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/ldmatrix.rs b/crates/cuda-device/src/generated/ldmatrix.rs index 424e3d01e0..3167086556 100644 --- a/crates/cuda-device/src/generated/ldmatrix.rs +++ b/crates/cuda-device/src/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/mbarrier_basic.rs b/crates/cuda-device/src/generated/mbarrier_basic.rs index 251de4f219..91166e2f3a 100644 --- a/crates/cuda-device/src/generated/mbarrier_basic.rs +++ b/crates/cuda-device/src/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::barrier` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/mbarrier_extended.rs b/crates/cuda-device/src/generated/mbarrier_extended.rs index a1323b63a2..ef1732931a 100644 --- a/crates/cuda-device/src/generated/mbarrier_extended.rs +++ b/crates/cuda-device/src/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::barrier` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/movmatrix.rs b/crates/cuda-device/src/generated/movmatrix.rs index a3bd62ae27..7968d986a7 100644 --- a/crates/cuda-device/src/generated/movmatrix.rs +++ b/crates/cuda-device/src/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/prmt.rs b/crates/cuda-device/src/generated/prmt.rs index 3b33a18d50..f22e051be3 100644 --- a/crates/cuda-device/src/generated/prmt.rs +++ b/crates/cuda-device/src/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::prmt` to keep the public paths stable. diff --git a/crates/cuda-device/src/generated/register_control.rs b/crates/cuda-device/src/generated/register_control.rs index 13de40fca2..d1edcc1813 100644 --- a/crates/cuda-device/src/generated/register_control.rs +++ b/crates/cuda-device/src/generated/register_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::thread` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/register_mma.rs b/crates/cuda-device/src/generated/register_mma.rs index 43b07e3057..a726ed6aa5 100644 --- a/crates/cuda-device/src/generated/register_mma.rs +++ b/crates/cuda-device/src/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/shared_sreg.rs b/crates/cuda-device/src/generated/shared_sreg.rs index 228299f88b..633a0cc57d 100644 --- a/crates/cuda-device/src/generated/shared_sreg.rs +++ b/crates/cuda-device/src/generated/shared_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::shared` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/sparse_mma.rs b/crates/cuda-device/src/generated/sparse_mma.rs index 7ec6f7685e..2e5de8ecda 100644 --- a/crates/cuda-device/src/generated/sparse_mma.rs +++ b/crates/cuda-device/src/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/sreg.rs b/crates/cuda-device/src/generated/sreg.rs index a6d2733352..13ffc21089 100644 --- a/crates/cuda-device/src/generated/sreg.rs +++ b/crates/cuda-device/src/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // This file is included lexically inside `cuda_device::thread` so existing diff --git a/crates/cuda-device/src/generated/stmatrix.rs b/crates/cuda-device/src/generated/stmatrix.rs index cb0fa5713b..f89eeedd01 100644 --- a/crates/cuda-device/src/generated/stmatrix.rs +++ b/crates/cuda-device/src/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::tcgen05` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/tcgen05.rs b/crates/cuda-device/src/generated/tcgen05.rs index 966af0f0c9..61afa50cef 100644 --- a/crates/cuda-device/src/generated/tcgen05.rs +++ b/crates/cuda-device/src/generated/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::tcgen05` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/tma.rs b/crates/cuda-device/src/generated/tma.rs index d53825a7ab..1a3fe30ace 100644 --- a/crates/cuda-device/src/generated/tma.rs +++ b/crates/cuda-device/src/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::tma` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/warp_sreg.rs b/crates/cuda-device/src/generated/warp_sreg.rs index 710e58b035..7d84a0d309 100644 --- a/crates/cuda-device/src/generated/warp_sreg.rs +++ b/crates/cuda-device/src/generated/warp_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::warp` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/wgmma_control.rs b/crates/cuda-device/src/generated/wgmma_control.rs index c4ac3a1112..3b56071d35 100644 --- a/crates/cuda-device/src/generated/wgmma_control.rs +++ b/crates/cuda-device/src/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wgmma` to keep its public API stable. diff --git a/crates/cuda-intrinsics/src/generated/abi_v1.rs b/crates/cuda-intrinsics/src/generated/abi_v1.rs index 6706b27320..0720148d23 100644 --- a/crates/cuda-intrinsics/src/generated/abi_v1.rs +++ b/crates/cuda-intrinsics/src/generated/abi_v1.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Raw ABI functions recognized by cuda-oxide. diff --git a/crates/cuda-intrinsics/src/generated/mod.rs b/crates/cuda-intrinsics/src/generated/mod.rs index 1f346dcc91..1ff3bdce66 100644 --- a/crates/cuda-intrinsics/src/generated/mod.rs +++ b/crates/cuda-intrinsics/src/generated/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. #[doc(hidden)] diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs index 4452cdd310..045bee3011 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `active_mask` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs index efe32a089e..b623a76957 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `clc` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs index f7d083bd51..b60ed211f4 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `cluster_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs index 1a5f55d68c..f2a1667584 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `cluster_memory` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs index bfa39aace8..8e9875f58d 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `cp_async` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs index 208847e73e..aa98ed8924 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `debug_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs index 867f65e587..36e63236cd 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `dotprod` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs index f11304e19a..4d89c014eb 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `elect` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs index 478ada7cd7..a1e7c39fb0 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `execution_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs index 360407531b..b88d25be5b 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `extended_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs index 7edf70caf4..0e292b5a76 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `integer_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs index ba088d72dd..2400dbc378 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `ldmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs index 247f6bf958..71aabb58c4 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `mbarrier_basic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs index 22355ec7d2..0d833f4041 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `mbarrier_extended` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs index 771e7b9c58..e110720cf1 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated target requirements and separately imported LLVM/selection facts. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs index 9c149147f0..28a413fd77 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `movmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs index b93e05f539..393d64e5fe 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `packed_alu` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs index 6e1842da36..bb233e749c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `packed_atomic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs index 1ffe5949b6..2b684588b4 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `packed_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs index 1280c0f953..7a19820dfe 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `prmt` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs index 1c8bdfb8a3..42bc16c3fc 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `redux` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs index 954ca92338..b3aadbd479 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `register_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs index fed6b09751..e67d465138 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `scalar_arithmetic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs index 970bc3bec3..720e3e2a29 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `scalar_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs index 6712670994..d748b6325c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `scalar_math` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs index eb6355564b..88e6ee6479 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `sparse_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs index 453094de29..0f2feaa2b2 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `sreg` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs index f2fa8c0411..c3bf01ff81 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `stmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs index 76f9bfee96..6e1ee345dc 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `sync` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs index 5668e14e28..a2c6fa453f 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_cp` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs index be96fb2ed6..1844c9eb7f 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_ld` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs index 5d37618ee7..9affb8db1b 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs index 3b7af9f86c..8557d1cd31 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_mma_ws` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs index edaa24339f..6d310def45 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_other` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs index 7b3565c80a..e14dab016f 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_st` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs index 5b1b5ab644..7b2b9c9f9f 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `active_mask` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs index e3bb07ec3c..b69a77e419 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `clc` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs index 7af81ce5dc..c430061934 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `cluster_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs index 73429ba98c..866c83ecaa 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `cluster_memory` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs index ef68da93b6..645a6370d9 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `cp_async` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs index f862027b33..e8d2ed9090 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `debug_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs index 0c583b6a5a..8a2310e50c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `dotprod` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs index 8dd307559c..cefbf418fa 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `elect` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs index 8db207fcb0..b5c4700973 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `execution_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs index 8ef8fa6abd..56202eb4da 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `extended_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs index b996f82984..c3a97a5c4d 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `integer_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs index 915114064d..bee122413a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `ldmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs index bc6d183d3a..f30e066ee7 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `mbarrier_basic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs index a7e217421d..cafc30d657 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `mbarrier_extended` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs index bee3a334c8..c47bb040e4 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests, grouped per family shard. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs index 5dcc670118..435eff8729 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `movmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs index d72d6a6015..5676725579 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `packed_alu` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs index d8bcda0c47..b391e5b40c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `packed_atomic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs index 17a58067a9..dd31617e84 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `packed_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs index da8f75709b..2d5e4e64af 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `prmt` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs index 33ce92f3d1..21235e1a83 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `redux` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs index 6096e75d87..d08dcd806b 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `register_mma_float` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs index 99d7ccf69d..7cf19135af 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `register_mma_s32` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs index eb559797a0..3eee784f4c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `scalar_arithmetic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs index 8971f26cf9..ad4b55b6e5 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `scalar_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs index e210ba4716..44b5a466e1 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `scalar_math` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs index 89e157a6f3..ec143311c8 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `sparse_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs index 0383030ee5..4935055b58 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `sreg` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs index 8f195314bf..9872e8dc96 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `stmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs index 3c27a0bc55..7fbe8e088c 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `sync` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs index 7a426078c9..83299630b9 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_cp` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs index dc89cd7db6..8f3c837b02 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_ld` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs index c54a0d9dfb..2ad4a1f1df 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs index 0cda2c16ea..5e0c43a620 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_mma_ws` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs index bb715975d9..2e7c7588a9 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_other` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs index 3991ace838..243f519b84 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_st` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs index e28b23b2de..d022246f40 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs index 618ac1d220..0d5cebbb32 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `vote` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs index fb0472de5f..a39f39db9f 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `warp_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs index 10e97c540b..e927ab8b5e 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `warp_match` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs index dca676d6d4..a8e00d18c8 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `warp_shuffle` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs index 5439f27534..05da3f71ea 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `wgmma_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs index 2faa9f4706..37e345df9a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs index dbc1456ce6..4f5e1ea462 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `vote` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs index a32f187d9a..9da97126d4 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `warp_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs index 89b7eb16d6..b624ec1917 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `warp_match` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs index 4fdeff1822..23d9c8eea3 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `warp_shuffle` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs index cf249df41a..c2aaaca1cd 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `wgmma_control` intrinsics. diff --git a/crates/dialect-nvvm/src/ops/generated/active_mask.rs b/crates/dialect-nvvm/src/ops/generated/active_mask.rs index 6fd36c46e0..f6de490716 100644 --- a/crates/dialect-nvvm/src/ops/generated/active_mask.rs +++ b/crates/dialect-nvvm/src/ops/generated/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for the generated active warp mask. diff --git a/crates/dialect-nvvm/src/ops/generated/clc.rs b/crates/dialect-nvvm/src/ops/generated/clc.rs index 719587a8ea..59c17af882 100644 --- a/crates/dialect-nvvm/src/ops/generated/clc.rs +++ b/crates/dialect-nvvm/src/ops/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated Cluster Launch Control operations. diff --git a/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs b/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs index 2abf87634f..b46c2793fe 100644 --- a/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs +++ b/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated operations for the closed cluster-barrier family. diff --git a/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs b/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs index a0094b3b58..aeb534c707 100644 --- a/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs +++ b/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for cluster address mapping and remote shared reads. diff --git a/crates/dialect-nvvm/src/ops/generated/cp_async.rs b/crates/dialect-nvvm/src/ops/generated/cp_async.rs index bfdf7df1ef..dd0c291866 100644 --- a/crates/dialect-nvvm/src/ops/generated/cp_async.rs +++ b/crates/dialect-nvvm/src/ops/generated/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for classic `cp.async` instructions. diff --git a/crates/dialect-nvvm/src/ops/generated/debug_control.rs b/crates/dialect-nvvm/src/ops/generated/debug_control.rs index 839430981f..38ab177b20 100644 --- a/crates/dialect-nvvm/src/ops/generated/debug_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated PTX debug controls. diff --git a/crates/dialect-nvvm/src/ops/generated/dotprod.rs b/crates/dialect-nvvm/src/ops/generated/dotprod.rs index dcf7c5540d..da00eb9297 100644 --- a/crates/dialect-nvvm/src/ops/generated/dotprod.rs +++ b/crates/dialect-nvvm/src/ops/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated packed integer dot products. diff --git a/crates/dialect-nvvm/src/ops/generated/elect.rs b/crates/dialect-nvvm/src/ops/generated/elect.rs index 7ea74086fb..c50afa9f41 100644 --- a/crates/dialect-nvvm/src/ops/generated/elect.rs +++ b/crates/dialect-nvvm/src/ops/generated/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated warp leader-election operation. diff --git a/crates/dialect-nvvm/src/ops/generated/execution_control.rs b/crates/dialect-nvvm/src/ops/generated/execution_control.rs index bd9b471375..7edcf75f6c 100644 --- a/crates/dialect-nvvm/src/ops/generated/execution_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated counted-barrier, grid-dependency, and register-control operations. diff --git a/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs b/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs index 0ad3ccaee6..07334a9d49 100644 --- a/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs +++ b/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for extended floating-point min/max. diff --git a/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs b/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs index 91dfd9f3cc..e8cc722499 100644 --- a/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs +++ b/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated extended integer min/max. diff --git a/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs b/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs index 502a277900..f24284ab72 100644 --- a/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation and compatibility carriers for generated `ldmatrix`. diff --git a/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs b/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs index cdc1a745b0..3baad76e3c 100644 --- a/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs +++ b/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the basic shared-memory mbarrier lifecycle. diff --git a/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs b/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs index 25f2e928e8..afa56ba14f 100644 --- a/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs +++ b/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for extended mbarrier and async-proxy instructions. diff --git a/crates/dialect-nvvm/src/ops/generated/mod.rs b/crates/dialect-nvvm/src/ops/generated/mod.rs index fceec69a6b..98d8b114ac 100644 --- a/crates/dialect-nvvm/src/ops/generated/mod.rs +++ b/crates/dialect-nvvm/src/ops/generated/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. mod active_mask; diff --git a/crates/dialect-nvvm/src/ops/generated/movmatrix.rs b/crates/dialect-nvvm/src/ops/generated/movmatrix.rs index 3f9dfc3062..1137dc5783 100644 --- a/crates/dialect-nvvm/src/ops/generated/movmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated in-register matrix transpose. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_alu.rs b/crates/dialect-nvvm/src/ops/generated/packed_alu.rs index 747341c533..6f4846d8af 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_alu.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated packed floating-point arithmetic. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs b/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs index ed4f3bd28d..294ddbcece 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for the closed generated packed-atomic family. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs b/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs index c86238ed69..f121a1e9b6 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated packed conversion. diff --git a/crates/dialect-nvvm/src/ops/generated/prmt.rs b/crates/dialect-nvvm/src/ops/generated/prmt.rs index 0867dc0b28..15deb4d130 100644 --- a/crates/dialect-nvvm/src/ops/generated/prmt.rs +++ b/crates/dialect-nvvm/src/ops/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for the closed generated `prmt` family. diff --git a/crates/dialect-nvvm/src/ops/generated/redux.rs b/crates/dialect-nvvm/src/ops/generated/redux.rs index bf37c7c519..01376d855b 100644 --- a/crates/dialect-nvvm/src/ops/generated/redux.rs +++ b/crates/dialect-nvvm/src/ops/generated/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural NVVM operations for the closed generated `redux.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/register_mma.rs b/crates/dialect-nvvm/src/ops/generated/register_mma.rs index fb53aab546..32bd8cec8b 100644 --- a/crates/dialect-nvvm/src/ops/generated/register_mma.rs +++ b/crates/dialect-nvvm/src/ops/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated register-only `mma.sync` variants. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs b/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs index b39c85afe9..a46cfa128e 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated scalar arithmetic. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs b/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs index 6e26abcae5..7071de6a0a 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated `f32` to TF32 conversions. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_math.rs b/crates/dialect-nvvm/src/ops/generated/scalar_math.rs index 7d09d1d353..a231e5e6bc 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_math.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated scalar math. diff --git a/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs b/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs index 133bbf4c6c..a383fac18e 100644 --- a/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs +++ b/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated sparse MMA variants. diff --git a/crates/dialect-nvvm/src/ops/generated/sreg.rs b/crates/dialect-nvvm/src/ops/generated/sreg.rs index 9f390fef7b..267ca8f475 100644 --- a/crates/dialect-nvvm/src/ops/generated/sreg.rs +++ b/crates/dialect-nvvm/src/ops/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural NVVM operations for generated special-register reads. diff --git a/crates/dialect-nvvm/src/ops/generated/stmatrix.rs b/crates/dialect-nvvm/src/ops/generated/stmatrix.rs index b1c78acdc8..ce0e56fe53 100644 --- a/crates/dialect-nvvm/src/ops/generated/stmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the four generated `stmatrix` stores. diff --git a/crates/dialect-nvvm/src/ops/generated/sync.rs b/crates/dialect-nvvm/src/ops/generated/sync.rs index 6ce7490d94..613513ec58 100644 --- a/crates/dialect-nvvm/src/ops/generated/sync.rs +++ b/crates/dialect-nvvm/src/ops/generated/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated CTA synchronization. diff --git a/crates/dialect-nvvm/src/ops/generated/tcgen05.rs b/crates/dialect-nvvm/src/ops/generated/tcgen05.rs index d36204155e..254e449396 100644 --- a/crates/dialect-nvvm/src/ops/generated/tcgen05.rs +++ b/crates/dialect-nvvm/src/ops/generated/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated Tensor Core Generation 5 operations. diff --git a/crates/dialect-nvvm/src/ops/generated/tma.rs b/crates/dialect-nvvm/src/ops/generated/tma.rs index 0e49d1d159..d6a45cf9ab 100644 --- a/crates/dialect-nvvm/src/ops/generated/tma.rs +++ b/crates/dialect-nvvm/src/ops/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated Tensor Memory Accelerator operations. diff --git a/crates/dialect-nvvm/src/ops/generated/vote.rs b/crates/dialect-nvvm/src/ops/generated/vote.rs index 7fd6b7fd5f..498c6ae005 100644 --- a/crates/dialect-nvvm/src/ops/generated/vote.rs +++ b/crates/dialect-nvvm/src/ops/generated/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the generated `vote.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs b/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs index a5561906a0..5e1f6d22ca 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated warp synchronization. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_match.rs b/crates/dialect-nvvm/src/ops/generated/warp_match.rs index 7d9efee361..f987662982 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_match.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the generated `match.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs b/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs index 811d3595a0..9881ffcc85 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the generated `shfl.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs b/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs index e9e15cd722..907bb02e85 100644 --- a/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated WGMMA controls. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs index 98376900d4..638e58693e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `active_mask` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs index 6c3107f469..80684c1cfb 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `clc` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs index 7afac1b083..4962aa17b9 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `cluster_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs index ff5a48b819..d92a20bbe8 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `cluster_memory` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs index 907375e555..3cf846714e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `cp_async` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs index 718a16aa35..1fc48fc170 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `debug_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs index fe038ceb3a..07beb03342 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `dotprod` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs index f49b75a9ee..20df425723 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `elect` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs index f557543c85..5f4a8c25b6 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `execution_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs index 146dff1407..31f17f3e9e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `extended_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs index cee1b74fc8..2bd401a617 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Shared glue for the generated intrinsic dispatch shards. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs index 007a5bfeca..c6e616f8d3 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `integer_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs index 4506e61541..01108c47f4 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `ldmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs index 7f461f2f0b..4e604253a3 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `mbarrier_basic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs index ed0755db6a..35e6bc8a78 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `mbarrier_extended` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs index bfbfa19c18..dbb0391cae 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility path dispatch for CUDA intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs index c6487d688d..a98eb14522 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `movmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs index 6373a8154c..e5c29cc334 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `packed_alu` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs index b4ad73e560..0e6c8896f3 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `packed_atomic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs index 4ae8d720ca..07cea60668 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `packed_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs index 4f79483938..6061619e12 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `prmt` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs index a8e4ec8242..4d450907fd 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `redux` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs index dd9098d421..15128ac5b7 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `register_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs index 8cf21fc103..5561066e1a 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `scalar_arithmetic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs index 4c251b7fd5..ab48e7338b 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `scalar_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs index 3c374d1d41..60636547ef 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `scalar_math` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs index 720c8e8357..f907b7687e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `sparse_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs index d2a6576737..8f8b84f194 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `sreg` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs index f4b571eb28..7dc3813bfd 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `stmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs index 018622d7cf..b04bd688f9 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `sync` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs index 163c885263..f304e4a6e3 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_cp` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs index 32b6a87bcb..b3473780f9 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_ld` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs index 3d49a32cd2..f0d6163cd6 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs index 73097ee6af..e10181cdc2 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_other` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs index 3d93bebb7f..70ec89788c 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_st` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs index 5248333ba4..7de7f5d4d3 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `active_mask` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs index a81a9d5d71..35c8ded641 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `clc` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs index 840acbc0a0..aaea97b609 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `cluster_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs index 7f62f58ae9..3feb77ffbe 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `cluster_memory` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs index 9651e805a2..45fcf8acb1 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `cp_async` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs index 39bfcb80ab..1c49b5e630 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `debug_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs index 0351348557..4f06ff727e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `dotprod` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs index a5b8498067..22b8344be6 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `elect` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs index 61becaa954..dcae3b562a 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `execution_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs index 2f16ab8353..ebe3aed75b 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `extended_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs index fe30da783e..3ccca5516d 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `integer_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs index 16fc05b41b..32de61a3aa 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `ldmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs index f6cf0946b7..49c0aba461 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `mbarrier_basic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs index 9de6a60fee..19a1ed5b98 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `mbarrier_extended` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs index ea8bff99de..583810dade 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests, grouped per intrinsic family. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs index da2e2a458c..c64c340ac4 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `movmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs index fb99c93ea1..db5aa8f8ce 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `packed_alu` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs index 52de1ee35e..a0f429369f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `packed_atomic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs index 49736da09b..cb4746115b 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `packed_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs index 622815069f..f22d6704b8 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `prmt` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs index 9d8db61a8e..344b6f702c 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `redux` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs index ba34805dfc..2cee3c5193 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `register_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs index 2a3fd204ac..9cc848015d 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `scalar_arithmetic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs index 4aa5faeea3..a941292085 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `scalar_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs index 6fa7f61514..3daf9ab262 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `scalar_math` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs index db1822c891..471f82633e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `sparse_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs index 41faf00891..a6ab343e53 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `sreg` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs index 9feaabb655..be5ba9c796 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `stmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs index 6fdbaed674..9834bf4c3c 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `sync` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs index 7fe9b0ed5c..84b115330c 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `tcgen05` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs index 09ca7969b1..316b869381 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `tma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs index 26becc17bd..b7df63bed8 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `vote` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs index f6c38de911..654ed6e05f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `warp_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs index c45993fe17..6517981a4f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `warp_match` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs index 4bb99e9f0f..cd7baa5894 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `warp_shuffle` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs index 7f58427bb9..7e36eaa9c1 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `wgmma_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs index 603f0ada10..d0ab93df94 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs index b7540bf6c9..40919ab552 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `vote` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs index 95d14cc4c1..17c21174f1 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `warp_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs index c5ffb8c2a2..091bad97d4 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `warp_match` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs index 162643e718..dfca76d17d 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `warp_shuffle` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs index bf09f709d3..5d69280854 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `wgmma_control` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs b/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs index 1119572917..ca950b990c 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `active_mask` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/clc.rs b/crates/mir-lower/src/convert/generated_intrinsics/clc.rs index b7b984700e..90351f6805 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/clc.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `clc` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs b/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs index 20dfdc1efa..1ef2131961 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `cluster_barrier` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs b/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs index c146e2c014..93153825f7 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `cluster_memory` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs b/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs index 118476117b..87b00ede20 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `cp_async` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs index 50d71b8cfa..eceab126ae 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `debug_control` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs b/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs index 8f0323e5b2..137d26465f 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `dotprod` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/elect.rs b/crates/mir-lower/src/convert/generated_intrinsics/elect.rs index 400042282c..f36bfb2ca1 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/elect.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `elect` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs index 0d8f898f47..da5ccc6ed9 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `execution_control` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs b/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs index 2d0734ce54..81132753d0 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `extended_minmax` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs b/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs index bcd696270f..f46e86ac33 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `integer_minmax` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs index dd95ff8a84..8b17f8f78d 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `ldmatrix` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs index 5da32ca804..c010c10881 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `mbarrier_basic` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs index bcd24eb824..8f44d6e95a 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `mbarrier_extended` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mod.rs b/crates/mir-lower/src/convert/generated_intrinsics/mod.rs index 40d7656ef6..d4d47342fd 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/mod.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces for admitted CUDA intrinsic families. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs index 02db8175b4..d568b4eacb 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `movmatrix` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs index 5a6b3c6ae4..b16c65fcb5 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `packed_alu` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs index dabbf20f69..52ce331ad2 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `packed_atomic` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs index 12114930bf..9a7029624f 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `packed_conversion` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs b/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs index 69b59d384e..3d29d73956 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `prmt` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/redux.rs b/crates/mir-lower/src/convert/generated_intrinsics/redux.rs index d8c765a644..d2087e10f4 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/redux.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `redux` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs b/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs index 260aaca47c..2bf4471f0b 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `register_mma` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs index 1a591cb172..a1961a1e29 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `scalar_arithmetic` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs index b9b1926978..12abaad9e3 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `scalar_conversion` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs index 9479653ac9..42ab60ce55 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `scalar_math` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs b/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs index 923e38fe2a..f1104718f9 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `sparse_mma` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs b/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs index ee1fc507d8..408ec4c55c 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `sreg` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs index 006f257558..37bb5a7c35 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `stmatrix` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sync.rs b/crates/mir-lower/src/convert/generated_intrinsics/sync.rs index c2d971d71d..5c6d2c7ad2 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/sync.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `sync` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs b/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs index 81eccd2611..4694cd43ac 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `tcgen05` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/tma.rs b/crates/mir-lower/src/convert/generated_intrinsics/tma.rs index 68bfdc4373..1d9b44c6c4 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/tma.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `tma` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/vote.rs b/crates/mir-lower/src/convert/generated_intrinsics/vote.rs index 5fb5cffedd..0e91b14b5e 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/vote.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `vote` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs index 9cfb177f8b..fb10df2055 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `warp_barrier` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs index 17eb1fe0c6..cb0dd57b1b 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `warp_match` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs index 1513a08a2c..1ee17bc284 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `warp_shuffle` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs index c1d4ff45c1..cef55837e7 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `wgmma_control` intrinsics. diff --git a/crates/rustc-codegen-cuda/src/generated_intrinsics.rs b/crates/rustc-codegen-cuda/src/generated_intrinsics.rs index ce111f6bfc..422a20e002 100644 --- a/crates/rustc-codegen-cuda/src/generated_intrinsics.rs +++ b/crates/rustc-codegen-cuda/src/generated_intrinsics.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated collector predicates for intrinsic placeholder functions. diff --git a/intrinsics/catalog.json b/intrinsics/catalog.json index f3e5a9bd4f..aff1c97136 100644 --- a/intrinsics/catalog.json +++ b/intrinsics/catalog.json @@ -11,12 +11,11 @@ }, "inputs": { "imported_sha256": "3f54245b231a5b6e19f3225710c3865b7e1a106242cce873250ef5fdc32e532e", - "overlay_sha256": "79ed6245b63d59adf0d8255e692bb3f1715c130e0bcd17bf46660a5d079eb71e", + "overlay_sha256": "40694465c7ce2c976800f5e80a5b08fe82ee9dd0df52e675e5f6d8c3cd94bd04", "abi_ledger_sha256": "a9092483a256cb48c4dc6ef98a15bb7568dad8f0586aa35866c0318d2e9ffafd", "evidence_sha256": [ "cuda-12.0-libnvvm-12.0.140-ex2-f16.json:7102ea7d567ff2d2eb75a0384148d2e5eb6e605c26a5b98c71371fa3c46adef6", "cuda-12.9-libnvvm-12.9.86-f32x2.json:bc5bb505677989affa9ac1044da772b4eb349700dc65e16f09fffffa1f5c493e", - "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json:083fc9da4b1049abecde81cbb9739578d8a9e19eaca416b1ff6f4c5a80b04042", "cuda-13.3-libnvvm-13.3.33-blackwell-ldmatrix.json:806155f5468d672b6bd969b72d9821155cc6a1c4422eb210ca0fc0a78eb295fb", "cuda-13.3-libnvvm-13.3.33-clc.json:0a3e049a8b606276302acf6d2f3dd1d41b632b04dd72799a7def8ebbec414752", "cuda-13.3-libnvvm-13.3.33-cluster-barrier.json:069e53acf46319a89ea69de86225724c8193d84a54df3c179818d8f2c782f4cc", @@ -47,6 +46,7 @@ "cuda-13.3-libnvvm-13.3.33-scalar-math.json:38afa3f8bf6588dfc1eafe90df3eee1c1bb953a5d4e58ca68a3b62df44289f0b", "cuda-13.3-libnvvm-13.3.33-sparse-mma-int8-m16n8k64.json:74b5dec9a9db352ea7eb1ee0b1470ba5a56f84f0ed55bf034a60fc29790b6d95", "cuda-13.3-libnvvm-13.3.33-sparse-mma-int8.json:ff0fd4a21e609d10993df1ce96a20e959dfbf2c9da0d397579957b18d2ad8a3f", + "cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-ampere-float.json:94d97593838d9c435ebdc0e0742c9267e72693c92fbcdae35504223cbb3c1515", "cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-f8f6f4-f16.json:a28dc4abd510e7c721fdcc1844f4d6f3c30b007ca0e6df77a51cbb2248d168c6", "cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-f8f6f4-f32.json:648cda8b8a673afaed08a7712f5e18272a5deb3c5a77214bc1f083cabc884b54", "cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-int4-m16n8k128.json:97d4924915387ce9852ad176d4e1264538f88fb6a20114cbf601297e0d089f32", @@ -107,7 +107,7 @@ "rust-llvm-23.1.0-16696adc-scalar-math.json:1a9e7994e07b5b53390df11a7e1805aa46176d21c8ed7e988433aee578c4dd47", "rust-llvm-23.1.0-16696adc-sparse-mma-int8-m16n8k64.json:2c0588c11569a4057647c099cfca9adfc449f3b3aea4e387f440a47e79d9b241", "rust-llvm-23.1.0-16696adc-sparse-mma-int8.json:9023c5c47bf1ad7266a13be8c4024d34e4e7d1efed6582affbbb9cdcdcfbea01", - "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json:4c80351dd79d8a04c87779cdf21542b7e11182b198b0b2b39e220157f45501a1", + "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json:c4356a2f779613e81041f257a2f976f3edf302be5b0445eab8888841cc89361f", "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-f8f6f4-f16.json:8569d7303b1a5af418214f2548e4b10c825c06c524dbecbc35b8ab0d4e2cf7ba", "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-f8f6f4-f32.json:d6b99f5f4fb88b145f24dba9da662e052137b05a6d2616731d08ab858a4e0541", "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-int4-m16n8k128.json:3a65cb8976f0fb35ca50a7e58943ed092d4e33a8dba84b637402bd3224d7ef21", @@ -189612,11 +189612,11 @@ "sm_80", "ptx85" ], - "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -189627,15 +189627,15 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ @@ -189657,7 +189657,7 @@ { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { "minimum_ptx": "8.5", "hardware": { @@ -189670,22 +189670,22 @@ ] } }, - "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", - "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", - "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", - "build_id_prefix": null, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx88" + "ptx93" ], - "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -189694,43 +189694,43 @@ { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", - "tool_version": "CUDA 12.9 nvJitLink V12.9.86", - "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" }, { "targets": [ "sm_120", - "ptx88" + "ptx93" ], "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", "stage": "runtime", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -189949,11 +189949,11 @@ "sm_80", "ptx85" ], - "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -189964,15 +189964,15 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ @@ -189994,7 +189994,7 @@ { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { "minimum_ptx": "8.5", "hardware": { @@ -190007,22 +190007,22 @@ ] } }, - "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", - "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", - "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", - "build_id_prefix": null, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx88" + "ptx93" ], - "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190031,43 +190031,43 @@ { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", - "tool_version": "CUDA 12.9 nvJitLink V12.9.86", - "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" }, { "targets": [ "sm_120", - "ptx88" + "ptx93" ], "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", "stage": "runtime", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190286,11 +190286,11 @@ "sm_80", "ptx85" ], - "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190301,15 +190301,15 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ @@ -190331,7 +190331,7 @@ { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { "minimum_ptx": "8.5", "hardware": { @@ -190344,22 +190344,22 @@ ] } }, - "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", - "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", - "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", - "build_id_prefix": null, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx88" + "ptx93" ], - "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190368,43 +190368,43 @@ { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", - "tool_version": "CUDA 12.9 nvJitLink V12.9.86", - "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" }, { "targets": [ "sm_120", - "ptx88" + "ptx93" ], "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", "stage": "runtime", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190631,11 +190631,11 @@ "sm_80", "ptx85" ], - "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190646,15 +190646,15 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ @@ -190676,7 +190676,7 @@ { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { "minimum_ptx": "8.5", "hardware": { @@ -190689,22 +190689,22 @@ ] } }, - "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", - "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", - "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", - "build_id_prefix": null, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx88" + "ptx93" ], - "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190713,43 +190713,43 @@ { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", - "tool_version": "CUDA 12.9 nvJitLink V12.9.86", - "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" }, { "targets": [ "sm_120", - "ptx88" + "ptx93" ], "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", "stage": "runtime", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190968,11 +190968,11 @@ "sm_80", "ptx85" ], - "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190983,15 +190983,15 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ @@ -191013,7 +191013,7 @@ { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { "minimum_ptx": "8.5", "hardware": { @@ -191026,22 +191026,22 @@ ] } }, - "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", - "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", - "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", - "build_id_prefix": null, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx88" + "ptx93" ], - "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191050,43 +191050,43 @@ { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", - "tool_version": "CUDA 12.9 nvJitLink V12.9.86", - "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" }, { "targets": [ "sm_120", - "ptx88" + "ptx93" ], "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", "stage": "runtime", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191313,11 +191313,11 @@ "sm_80", "ptx85" ], - "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191328,15 +191328,15 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ @@ -191358,7 +191358,7 @@ { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { "minimum_ptx": "8.5", "hardware": { @@ -191371,22 +191371,22 @@ ] } }, - "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", - "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", - "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", - "build_id_prefix": null, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx88" + "ptx93" ], - "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191395,43 +191395,43 @@ { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", - "tool_version": "CUDA 12.9 nvJitLink V12.9.86", - "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" }, { "targets": [ "sm_120", - "ptx88" + "ptx93" ], "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", "stage": "runtime", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191658,11 +191658,11 @@ "sm_80", "ptx85" ], - "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191673,15 +191673,15 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ @@ -191703,7 +191703,7 @@ { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { "minimum_ptx": "8.5", "hardware": { @@ -191716,22 +191716,22 @@ ] } }, - "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", - "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", - "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", - "build_id_prefix": null, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx88" + "ptx93" ], - "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191740,43 +191740,43 @@ { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", - "tool_version": "CUDA 12.9 nvJitLink V12.9.86", - "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" }, { "targets": [ "sm_120", - "ptx88" + "ptx93" ], "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", "stage": "runtime", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -222429,11 +222429,11 @@ "sm_80", "ptx85" ], - "representation": "eight typed LLVM declarations lowered through the selected convergent inline-PTX route", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -222444,15 +222444,15 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX containing all eight ordered sparse floating MMA forms", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ @@ -222474,7 +222474,7 @@ { "backend": "lib_nvvm", "mechanism": "inline_ptx", - "evidence_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { "minimum_ptx": "8.5", "hardware": { @@ -222487,22 +222487,22 @@ ] } }, - "version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", - "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", - "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", - "build_id_prefix": null, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", "status": "executed", "stages": [ { "targets": [ "compute_80", - "ptx88" + "ptx93" ], - "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987).", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -222511,43 +222511,43 @@ { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas", - "tool_version": "CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0", - "tool_sha256": "fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73" + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" }, { "targets": [ "sm_80", - "ptx88" + "ptx93" ], - "representation": "the 4,740-byte all-variant libNVVM LTOIR linked for sm_80", + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", - "tool_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86", - "tool_version": "CUDA 12.9 nvJitLink V12.9.86", - "tool_sha256": "71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622" + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" }, { "targets": [ "sm_120", - "ptx88" + "ptx93" ], "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", "stage": "runtime", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", "artifact_kind": null, "tool_path": null, "tool_version": null, diff --git a/intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json b/intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-ampere-float.json similarity index 67% rename from intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json rename to intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-ampere-float.json index 141f9b9c02..3f013f78b2 100644 --- a/intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float.json +++ b/intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-ampere-float.json @@ -1,22 +1,23 @@ { "schema": 6, - "backend_profile": "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float", + "backend_profile": "cuda-13.3-libnvvm-13.3.33", "backend_kind": "lib_nvvm", "llvm_revision": "not-applicable-libnvvm-ir-2.0", - "backend_version": "CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86", - "backend_sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", - "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4", + "backend_version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "backend_sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", "nvvm_ir_version": "2.0", - "debug_ir_version": "3.1", - "defaults": {"target_triple":"nvptx64-nvidia-cuda","gpu_target":"compute_80","ptx_feature":"CUDA 12.9 emits PTX ISA 8.8; reviewed forms require PTX 8.5","status":"executed","runtime_validation":"executed"}, + "debug_ir_version": "3.2", + "defaults": {"target_triple":"nvptx64-nvidia-cuda","gpu_target":"compute_80","ptx_feature":"PTX ISA 8.5 minimum; CUDA 13.3 emits PTX 9.3","status":"executed","runtime_validation":"executed"}, "fixtures": [{ "id": "ordered_ampere_float_all", "coverage_count": 8, "stages": [ - {"targets":["compute_80","ptx88"],"representation":"eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in NVVM IR 2.0","stage":"backend_codegen","mechanism":"inline_ptx","outcome":"succeeded","detail":"CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987)."}, - {"targets":["sm_80","ptx88"],"representation":"CUDA 12.9 libNVVM PTX containing all eight ordered sparse floating MMA forms","stage":"ptx_assembly","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.","tool_path":"/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas","tool_version":"CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0","tool_sha256":"fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73"}, - {"targets":["sm_80","ptx88"],"representation":"the 4,740-byte all-variant libNVVM LTOIR linked for sm_80","stage":"device_link","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.","tool_path":"/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86","tool_version":"CUDA 12.9 nvJitLink V12.9.86","tool_sha256":"71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622"}, - {"targets":["sm_120","ptx88"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors."} + {"targets":["compute_80","ptx93"],"representation":"eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel","stage":"backend_codegen","mechanism":"inline_ptx","outcome":"succeeded","detail":"The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant."}, + {"targets":["sm_80","ptx93"],"representation":"nvJitLink PTX containing all eight ordered sparse floating MMA forms","stage":"ptx_assembly","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.","tool_path":"/usr/local/cuda-13.3/bin/ptxas","tool_version":"CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0","tool_sha256":"7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb"}, + {"targets":["sm_80","ptx93"],"representation":"the 37,468-byte all-variant libNVVM LTOIR linked for sm_80","stage":"device_link","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.","tool_path":"/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33","tool_version":"V13.3.33","tool_sha256":"3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8"}, + {"targets":["sm_120","ptx93"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors."} ] }], "matrices": [ diff --git a/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json b/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json index 318b25770d..df9e933659 100644 --- a/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json +++ b/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json @@ -10,8 +10,8 @@ "id": "ordered_ampere_float_all", "coverage_count": 8, "stages": [ - {"targets":["sm_80","ptx85"],"representation":"eight typed LLVM declarations lowered through the selected convergent inline-PTX route","stage":"backend_codegen","mechanism":"inline_ptx","outcome":"succeeded","detail":"Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded."}, - {"targets":["sm_80","ptx85"],"representation":"exact-floor PTX containing all eight ordered sparse floating MMA forms","stage":"ptx_assembly","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375.","tool_path":"/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas","tool_version":"CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0","tool_sha256":"fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73"}, + {"targets":["sm_80","ptx85"],"representation":"eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate","stage":"backend_codegen","mechanism":"inline_ptx","outcome":"succeeded","detail":"Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86."}, + {"targets":["sm_80","ptx85"],"representation":"exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms","stage":"ptx_assembly","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.","tool_path":"/usr/local/cuda-13.3/bin/ptxas","tool_version":"CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0","tool_sha256":"7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb"}, {"targets":["sm_120","ptx85"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors."} ] }], diff --git a/intrinsics/generated-reference.md b/intrinsics/generated-reference.md index f6c5e0830e..afb8480aa5 100644 --- a/intrinsics/generated-reference.md +++ b/intrinsics/generated-reference.md @@ -2,7 +2,7 @@ SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0 @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. --> @@ -13454,74 +13454,74 @@ This table is generated from the resolved catalog. Evidence stages below disting - device link on `sm_80, ptx93`: `succeeded` — The 27,880-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. - `mma_sp_ordered_metadata_m16n8k16_f16_f16`: runtime `executed` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. - - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) - - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). - - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. - - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. - - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `mma_sp_ordered_metadata_m16n8k16_f32_bf16`: runtime `executed` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. - - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) - - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). - - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. - - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. - - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `mma_sp_ordered_metadata_m16n8k16_f32_f16`: runtime `executed` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. - - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) - - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). - - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. - - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. - - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `mma_sp_ordered_metadata_m16n8k16_f32_tf32`: runtime `executed` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. - - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) - - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). - - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. - - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. - - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `mma_sp_ordered_metadata_m16n8k32_f16_f16`: runtime `executed` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. - - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) - - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). - - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. - - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. - - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `mma_sp_ordered_metadata_m16n8k32_f32_bf16`: runtime `executed` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. - - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) - - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). - - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. - - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. - - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `mma_sp_ordered_metadata_m16n8k32_f32_f16`: runtime `executed` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. - - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) - - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). - - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. - - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. - - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `mma_sp_ordered_metadata_m16n8k32_s32_s8`: runtime `unexecuted` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `validated` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - backend codegen on `sm_80, ptx85`: `succeeded` — The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80. @@ -14492,14 +14492,14 @@ This table is generated from the resolved catalog. Evidence stages below disting - device link on `sm_80, ptx93`: `succeeded` — nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. - `mma_sp_ordered_metadata_m16n8k8_f32_tf32`: runtime `executed` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust emitted all eight exact ordered-metadata sparse floating MMA heads in 5,919-byte PTX (SHA-256 ad099cdc834110da56254abc01034b4d9284e33dc20f4f90f8d2afc079bf1c3b). sm_75/+ptx85 and sm_80/+ptx80 failed selection; sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86 succeeded. - - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 12.9.86 ptxas accepted the 5,919-byte PTX 8.5 fixture and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 12.9; libNVVM/ptxas release V12.9.86`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) - - backend codegen on `compute_80, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 4,379-byte IR fixture and emitted every reviewed instruction exactly once in 9,825-byte PTX (SHA-256 3bebcae52bbd17d0b2f1b9ff7630f6545623b1e95b5e430f442b29fd007c3264) plus 4,740-byte LTOIR (SHA-256 06bb14b236103564646bff3dfb6dd3099d911fa9631adeb38649b91f93fc2987). - - PTX assembly on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 ptxas accepted the 9,825-byte libNVVM PTX and produced a 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/bin/ptxas` reports `CUDA 12.9 V12.9.86 build cuda_12.9.r12.9/compiler.36037853_0` (SHA-256 `fb46c0843eba5215f909a6d279f4a25e34d0a48472c6d6f14e4711b00edf9b73`). Artifact `cubin`. - - device link on `sm_80, ptx88`: `succeeded` — CUDA 12.9.86 nvJitLink accepted the real libNVVM LTOIR and produced a valid 960-byte cubin with SHA-256 49ead52030d9bccae833c39468fe4e63c89fbedfcfc7e57d77f86d93033b6375. Tool `/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/lib/libnvJitLink.so.12.9.86` reports `CUDA 12.9 nvJitLink V12.9.86` (SHA-256 `71386c8355bddbdf428691f36ee31f462217b5054be1001170ed0c1ed0a70622`). Artifact `cubin`. - - runtime on `sm_120, ptx88`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `movmatrix_trans_b16`: runtime `unexecuted` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 7.8 / sm_75+: status `validated` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - backend codegen on `sm_75, ptx78`: `succeeded` — Pinned Rust LLVM emitted one exact movmatrix instruction; source SHA-256 b8776ed95d8c8e451deea02d8851a238cfcfe570e286a92c94e5971bf06db963, bitcode SHA-256 caf25ab44ed893d449343707f06af85395e86f41852c32ec1b577be184365aee, and PTX SHA-256 f1e1b7d8ad879abd120d6cb32a5999925af0ed77b3a7144a7dfd8db76ea18246. diff --git a/intrinsics/overlay/sparse_mma_ordered_ampere_float.toml b/intrinsics/overlay/sparse_mma_ordered_ampere_float.toml index 58b3280a6e..81c3e6a775 100644 --- a/intrinsics/overlay/sparse_mma_ordered_ampere_float.toml +++ b/intrinsics/overlay/sparse_mma_ordered_ampere_float.toml @@ -5,7 +5,7 @@ family = "sparse_mma" [sparse_mma_ordered_ampere_float] llvm_evidence_profile = "rust-llvm-23.1.0-16696adc" -libnvvm_evidence_profile = "cuda-12.9-libnvvm-12.9.86-sparse-mma-ordered-ampere-float" +libnvvm_evidence_profile = "cuda-13.3-libnvvm-13.3.33" runtime_validation = "executed" [[sparse_mma_ordered_ampere_float.variant]] diff --git a/intrinsics/probes/abs_bf16x2.ll b/intrinsics/probes/abs_bf16x2.ll index e6fb799457..9387924956 100644 --- a/intrinsics/probes/abs_bf16x2.ll +++ b/intrinsics/probes/abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/abs_f16x2.ll b/intrinsics/probes/abs_f16x2.ll index c59cf11969..c03b9bae53 100644 --- a/intrinsics/probes/abs_f16x2.ll +++ b/intrinsics/probes/abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/active_mask.ll b/intrinsics/probes/active_mask.ll index 2cf0f44f20..a55d939d54 100644 --- a/intrinsics/probes/active_mask.ll +++ b/intrinsics/probes/active_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_bf16x2.ll b/intrinsics/probes/add_bf16x2.ll index fe9baee1ae..61d22914d0 100644 --- a/intrinsics/probes/add_bf16x2.ll +++ b/intrinsics/probes/add_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_f16x2.ll b/intrinsics/probes/add_f16x2.ll index 5ed0b49a23..101260467c 100644 --- a/intrinsics/probes/add_f16x2.ll +++ b/intrinsics/probes/add_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_f32x2.ll b/intrinsics/probes/add_f32x2.ll index 100f437c8f..b44af263c3 100644 --- a/intrinsics/probes/add_f32x2.ll +++ b/intrinsics/probes/add_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_ftz_f32x2.ll b/intrinsics/probes/add_ftz_f32x2.ll index 407c6f7559..a10acd1922 100644 --- a/intrinsics/probes/add_ftz_f32x2.ll +++ b/intrinsics/probes/add_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_f32.ll b/intrinsics/probes/add_rm_f32.ll index 459e42ee06..9c5b79303e 100644 --- a/intrinsics/probes/add_rm_f32.ll +++ b/intrinsics/probes/add_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_f64.ll b/intrinsics/probes/add_rm_f64.ll index 8fd3c7375e..a4d1337334 100644 --- a/intrinsics/probes/add_rm_f64.ll +++ b/intrinsics/probes/add_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_ftz_f32.ll b/intrinsics/probes/add_rm_ftz_f32.ll index d871b073e0..e613fda3b9 100644 --- a/intrinsics/probes/add_rm_ftz_f32.ll +++ b/intrinsics/probes/add_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_ftz_sat_f32.ll b/intrinsics/probes/add_rm_ftz_sat_f32.ll index 385722bf09..363d3ecac6 100644 --- a/intrinsics/probes/add_rm_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rm_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_sat_f32.ll b/intrinsics/probes/add_rm_sat_f32.ll index 784a29862e..bbb1b5e840 100644 --- a/intrinsics/probes/add_rm_sat_f32.ll +++ b/intrinsics/probes/add_rm_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_f32.ll b/intrinsics/probes/add_rn_f32.ll index 1d6ebadabd..4f811d4c96 100644 --- a/intrinsics/probes/add_rn_f32.ll +++ b/intrinsics/probes/add_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_f64.ll b/intrinsics/probes/add_rn_f64.ll index 71f4e2aa14..7d24bf5376 100644 --- a/intrinsics/probes/add_rn_f64.ll +++ b/intrinsics/probes/add_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_ftz_f32.ll b/intrinsics/probes/add_rn_ftz_f32.ll index ee78a0e33d..9fc9d44d41 100644 --- a/intrinsics/probes/add_rn_ftz_f32.ll +++ b/intrinsics/probes/add_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_ftz_sat_f32.ll b/intrinsics/probes/add_rn_ftz_sat_f32.ll index 44d9d79faf..e896841f66 100644 --- a/intrinsics/probes/add_rn_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rn_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_sat_f32.ll b/intrinsics/probes/add_rn_sat_f32.ll index b8931f0866..54d817dd54 100644 --- a/intrinsics/probes/add_rn_sat_f32.ll +++ b/intrinsics/probes/add_rn_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_f32.ll b/intrinsics/probes/add_rp_f32.ll index 72cbcdddf4..3e08b6774a 100644 --- a/intrinsics/probes/add_rp_f32.ll +++ b/intrinsics/probes/add_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_f64.ll b/intrinsics/probes/add_rp_f64.ll index 6e12d4f083..96df50c59f 100644 --- a/intrinsics/probes/add_rp_f64.ll +++ b/intrinsics/probes/add_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_ftz_f32.ll b/intrinsics/probes/add_rp_ftz_f32.ll index e49132c668..4d29d313da 100644 --- a/intrinsics/probes/add_rp_ftz_f32.ll +++ b/intrinsics/probes/add_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_ftz_sat_f32.ll b/intrinsics/probes/add_rp_ftz_sat_f32.ll index c96ad0b225..68dad96365 100644 --- a/intrinsics/probes/add_rp_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rp_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_sat_f32.ll b/intrinsics/probes/add_rp_sat_f32.ll index d27771537c..0e9860dbb1 100644 --- a/intrinsics/probes/add_rp_sat_f32.ll +++ b/intrinsics/probes/add_rp_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_f32.ll b/intrinsics/probes/add_rz_f32.ll index c9376f22de..07ce1dfc9b 100644 --- a/intrinsics/probes/add_rz_f32.ll +++ b/intrinsics/probes/add_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_f64.ll b/intrinsics/probes/add_rz_f64.ll index 6a16bf7ce8..d42d34f90a 100644 --- a/intrinsics/probes/add_rz_f64.ll +++ b/intrinsics/probes/add_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_ftz_f32.ll b/intrinsics/probes/add_rz_ftz_f32.ll index b122384f6a..f91ca5298c 100644 --- a/intrinsics/probes/add_rz_ftz_f32.ll +++ b/intrinsics/probes/add_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_ftz_sat_f32.ll b/intrinsics/probes/add_rz_ftz_sat_f32.ll index d1523ce8cd..31edeb4546 100644 --- a/intrinsics/probes/add_rz_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rz_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_sat_f32.ll b/intrinsics/probes/add_rz_sat_f32.ll index fc1ae831f5..0868d4f58e 100644 --- a/intrinsics/probes/add_rz_sat_f32.ll +++ b/intrinsics/probes/add_rz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/all_sync.ll b/intrinsics/probes/all_sync.ll index 0853e51441..c01b43c3a1 100644 --- a/intrinsics/probes/all_sync.ll +++ b/intrinsics/probes/all_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/any_sync.ll b/intrinsics/probes/any_sync.ll index 38d345acdf..1be5b74231 100644 --- a/intrinsics/probes/any_sync.ll +++ b/intrinsics/probes/any_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ballot_sync.ll b/intrinsics/probes/ballot_sync.ll index e0d8b053db..205655f800 100644 --- a/intrinsics/probes/ballot_sync.ll +++ b/intrinsics/probes/ballot_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive.ll b/intrinsics/probes/barrier_cluster_arrive.ll index 7cf7d7e200..6dae66cd77 100644 --- a/intrinsics/probes/barrier_cluster_arrive.ll +++ b/intrinsics/probes/barrier_cluster_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_aligned.ll b/intrinsics/probes/barrier_cluster_arrive_aligned.ll index bc2bdac9ea..caae3a8900 100644 --- a/intrinsics/probes/barrier_cluster_arrive_aligned.ll +++ b/intrinsics/probes/barrier_cluster_arrive_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_relaxed.ll b/intrinsics/probes/barrier_cluster_arrive_relaxed.ll index b3f3c94676..4cb5800f2b 100644 --- a/intrinsics/probes/barrier_cluster_arrive_relaxed.ll +++ b/intrinsics/probes/barrier_cluster_arrive_relaxed.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll b/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll index 467335b6ac..c1ed13ba06 100644 --- a/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll +++ b/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_wait.ll b/intrinsics/probes/barrier_cluster_wait.ll index 04c2b40735..6a7495d7cd 100644 --- a/intrinsics/probes/barrier_cluster_wait.ll +++ b/intrinsics/probes/barrier_cluster_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_wait_aligned.ll b/intrinsics/probes/barrier_cluster_wait_aligned.ll index 0ee96d911b..2c4bc4e505 100644 --- a/intrinsics/probes/barrier_cluster_wait_aligned.ll +++ b/intrinsics/probes/barrier_cluster_wait_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_arrive.ll b/intrinsics/probes/barrier_cta_arrive.ll index 5a8f9aacb7..21b7622e7c 100644 --- a/intrinsics/probes/barrier_cta_arrive.ll +++ b/intrinsics/probes/barrier_cta_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_arrive_aligned.ll b/intrinsics/probes/barrier_cta_arrive_aligned.ll index 9e840a582b..d881620377 100644 --- a/intrinsics/probes/barrier_cta_arrive_aligned.ll +++ b/intrinsics/probes/barrier_cta_arrive_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_sync.ll b/intrinsics/probes/barrier_cta_sync.ll index e3cf0f5eac..275dce20d1 100644 --- a/intrinsics/probes/barrier_cta_sync.ll +++ b/intrinsics/probes/barrier_cta_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_sync_aligned.ll b/intrinsics/probes/barrier_cta_sync_aligned.ll index 0cc041bd50..5e3a9b05ba 100644 --- a/intrinsics/probes/barrier_cta_sync_aligned.ll +++ b/intrinsics/probes/barrier_cta_sync_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_x.ll b/intrinsics/probes/block_dim_x.ll index 2a6398b7ac..10b44bd903 100644 --- a/intrinsics/probes/block_dim_x.ll +++ b/intrinsics/probes/block_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_y.ll b/intrinsics/probes/block_dim_y.ll index cc63ff9ef7..82b7c36871 100644 --- a/intrinsics/probes/block_dim_y.ll +++ b/intrinsics/probes/block_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_z.ll b/intrinsics/probes/block_dim_z.ll index 2889ecfc57..be19e8a4ca 100644 --- a/intrinsics/probes/block_dim_z.ll +++ b/intrinsics/probes/block_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_x.ll b/intrinsics/probes/block_idx_x.ll index 6a118597a3..213e5b9a30 100644 --- a/intrinsics/probes/block_idx_x.ll +++ b/intrinsics/probes/block_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_y.ll b/intrinsics/probes/block_idx_y.ll index 83a4db4ab8..54ce78006a 100644 --- a/intrinsics/probes/block_idx_y.ll +++ b/intrinsics/probes/block_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_z.ll b/intrinsics/probes/block_idx_z.ll index 4aa6383b50..eec23f58d6 100644 --- a/intrinsics/probes/block_idx_z.ll +++ b/intrinsics/probes/block_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/breakpoint.ll b/intrinsics/probes/breakpoint.ll index f6e0c4a966..f43a3cda8c 100644 --- a/intrinsics/probes/breakpoint.ll +++ b/intrinsics/probes/breakpoint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_x.ll b/intrinsics/probes/clc_query_get_first_ctaid_x.ll index 148a7033ed..9cc91de908 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_x.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_y.ll b/intrinsics/probes/clc_query_get_first_ctaid_y.ll index f2ae9380ca..906ec0782b 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_y.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_z.ll b/intrinsics/probes/clc_query_get_first_ctaid_z.ll index fced9cc0f0..3ad99a7420 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_z.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_is_canceled.ll b/intrinsics/probes/clc_query_is_canceled.ll index 9a3c3d509f..8bc3a5085a 100644 --- a/intrinsics/probes/clc_query_is_canceled.ll +++ b/intrinsics/probes/clc_query_is_canceled.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_try_cancel.ll b/intrinsics/probes/clc_try_cancel.ll index 07288866d7..fc1d542c35 100644 --- a/intrinsics/probes/clc_try_cancel.ll +++ b/intrinsics/probes/clc_try_cancel.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_try_cancel_multicast.ll b/intrinsics/probes/clc_try_cancel_multicast.ll index 3c209c045a..0b07b1aaa1 100644 --- a/intrinsics/probes/clc_try_cancel_multicast.ll +++ b/intrinsics/probes/clc_try_cancel_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock.lib_nvvm.ll b/intrinsics/probes/clock.lib_nvvm.ll index 3a1607fb56..4a5d093493 100644 --- a/intrinsics/probes/clock.lib_nvvm.ll +++ b/intrinsics/probes/clock.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock.llvm_nvptx.ll b/intrinsics/probes/clock.llvm_nvptx.ll index 5c18c50157..7fa9a4bfd6 100644 --- a/intrinsics/probes/clock.llvm_nvptx.ll +++ b/intrinsics/probes/clock.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock64.lib_nvvm.ll b/intrinsics/probes/clock64.lib_nvvm.ll index 0707ff223c..1480ea0826 100644 --- a/intrinsics/probes/clock64.lib_nvvm.ll +++ b/intrinsics/probes/clock64.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock64.llvm_nvptx.ll b/intrinsics/probes/clock64.llvm_nvptx.ll index ef2efc7154..d2b26bd754 100644 --- a/intrinsics/probes/clock64.llvm_nvptx.ll +++ b/intrinsics/probes/clock64.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_count.ll b/intrinsics/probes/cluster_block_count.ll index 415815cfd4..5d7dc6fce3 100644 --- a/intrinsics/probes/cluster_block_count.ll +++ b/intrinsics/probes/cluster_block_count.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_x.ll b/intrinsics/probes/cluster_block_idx_x.ll index 655c289cdd..27a22b7139 100644 --- a/intrinsics/probes/cluster_block_idx_x.ll +++ b/intrinsics/probes/cluster_block_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_y.ll b/intrinsics/probes/cluster_block_idx_y.ll index f03730022c..0498caafda 100644 --- a/intrinsics/probes/cluster_block_idx_y.ll +++ b/intrinsics/probes/cluster_block_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_z.ll b/intrinsics/probes/cluster_block_idx_z.ll index 9961c42479..b69a6bee10 100644 --- a/intrinsics/probes/cluster_block_idx_z.ll +++ b/intrinsics/probes/cluster_block_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_rank.ll b/intrinsics/probes/cluster_block_rank.ll index c06724178b..5d20e60ec0 100644 --- a/intrinsics/probes/cluster_block_rank.ll +++ b/intrinsics/probes/cluster_block_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_x.ll b/intrinsics/probes/cluster_dim_x.ll index 3ff053505d..2aa147cc0c 100644 --- a/intrinsics/probes/cluster_dim_x.ll +++ b/intrinsics/probes/cluster_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_y.ll b/intrinsics/probes/cluster_dim_y.ll index e0b35bd3c1..5326567fe0 100644 --- a/intrinsics/probes/cluster_dim_y.ll +++ b/intrinsics/probes/cluster_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_z.ll b/intrinsics/probes/cluster_dim_z.ll index d51ba080db..f1a5448aed 100644 --- a/intrinsics/probes/cluster_dim_z.ll +++ b/intrinsics/probes/cluster_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_x.ll b/intrinsics/probes/cluster_grid_dim_x.ll index 07d16a5ed3..fdd2de6f9f 100644 --- a/intrinsics/probes/cluster_grid_dim_x.ll +++ b/intrinsics/probes/cluster_grid_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_y.ll b/intrinsics/probes/cluster_grid_dim_y.ll index f5caeb8b72..beb6946696 100644 --- a/intrinsics/probes/cluster_grid_dim_y.ll +++ b/intrinsics/probes/cluster_grid_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_z.ll b/intrinsics/probes/cluster_grid_dim_z.ll index 203083c277..33c2edecdb 100644 --- a/intrinsics/probes/cluster_grid_dim_z.ll +++ b/intrinsics/probes/cluster_grid_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_x.ll b/intrinsics/probes/cluster_idx_x.ll index c659e62ec5..ea32cd58cb 100644 --- a/intrinsics/probes/cluster_idx_x.ll +++ b/intrinsics/probes/cluster_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_y.ll b/intrinsics/probes/cluster_idx_y.ll index 3015abe864..953693079e 100644 --- a/intrinsics/probes/cluster_idx_y.ll +++ b/intrinsics/probes/cluster_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_z.ll b/intrinsics/probes/cluster_idx_z.ll index 4e719d1861..07c2f1ae66 100644 --- a/intrinsics/probes/cluster_idx_z.ll +++ b/intrinsics/probes/cluster_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cos_approx_f32.ll b/intrinsics/probes/cos_approx_f32.ll index bfdd221a05..2ed8f54cbe 100644 --- a/intrinsics/probes/cos_approx_f32.ll +++ b/intrinsics/probes/cos_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cos_approx_ftz_f32.ll b/intrinsics/probes/cos_approx_ftz_f32.ll index b8b48bcb35..7c56f49ea5 100644 --- a/intrinsics/probes/cos_approx_ftz_f32.ll +++ b/intrinsics/probes/cos_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_commit_group.ll b/intrinsics/probes/cp_async_bulk_commit_group.ll index 7c801c462a..7b5f71aacd 100644 --- a/intrinsics/probes/cp_async_bulk_commit_group.ll +++ b/intrinsics/probes/cp_async_bulk_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll index 9e19ef2f0e..b745094ec7 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll index 76ccbfdc16..7b0371f900 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll index 99bea0526e..0a4bcf20e4 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll index 0a624d9515..229a9b4569 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll index 3c5d1f88c4..239636e699 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll index 420a966a63..ca118cfe0f 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll index 3bd0181a27..21df914fbc 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll index 6fc0e5963d..5972ac6021 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll index 20003ca5f4..c8c5af9709 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll index 02ec0be672..bbd93f1c76 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll index 5d62ec7725..9a6ab00499 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll index 0b059d0d47..c0a3b9ef8f 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll index a3a991ba7f..8ce3df1dd0 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll index 9bb71fb5dc..0d33e536a1 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll index e232956b3f..ab64839fd5 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll index 1348155d08..af10c0d637 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll index 64749dae1a..2e4a7b1d74 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll index fee2c85363..8648b56888 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll index 2e3b2b5eb7..086672f55e 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll index 5241db4709..3066d2734b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll index b529afe4c2..9c19bb8c12 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll index 270fb918a6..c95471df14 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll index 6755f3dabe..0e35619389 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll index eda0a7fb46..612bbef147 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll index 915fdc7dbc..9569709628 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll index 4fcbb9a19a..dd848c92f9 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll index da0d2b7580..981f25f176 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll index 6c1a28d076..0f94138c23 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll index 0d005487c6..5d25bdaf85 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll index c3833e7c8b..048d643690 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll index 264d12afea..1c50f556bc 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll index 10ba6ae4b6..9ef2cb47e8 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll index 360077da2e..db0b4174de 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll index 01bed7b9a9..e64a040c7f 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll index e67c3402e8..95054612ae 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll index 19f2ca669b..109ab46ea7 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll index bef4763e87..f55c617373 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll index ba17af5ead..d39843da9c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll index 473383aab4..5bea2a07c5 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll index 74e25727fe..3ed8623707 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll index 2d07b1047c..e901109ab4 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll index 2d879673af..6930be114f 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll index f09e81e6ab..f128e3bdb3 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll index 50ef3e7026..e1c2af39da 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll index 47af6e5c27..423e10529d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll index bbe2abbbff..4c3f70e052 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll index f860552451..1169fc322a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll index 8e922fe397..8f2a9c42a5 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll index 51322b4706..7eb3bb7e28 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll index c5a4a9a142..72fea8c963 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll index 863a6b3270..05b0412246 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll index 5c1446aed9..fc3611fdbf 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll index 94b05033d9..f9d63bf4c5 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll index 89c59f1525..cbf03fce41 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll index c1885aeba7..d69f677aef 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll index d1cdcb688c..2eeb94fb42 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll index 1240bad8e9..3dd8d86563 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll index 925a4d8578..8e57b9ee7d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll index 7bc7e5f9c1..83ead7a53f 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll index 732591672d..6a4f4e3907 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll index a688418231..a8239e793c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll index a69b5bd2ee..7124fe637d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll index 0499cc5635..d8d883102e 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll index 8583c6fb41..1abc740cda 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll index 6e644a15cc..b18f5415eb 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll index 5b3cf19f85..04e32dbf64 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll index c586ed282b..fe0394b855 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll index b7b3825501..27fd897072 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll index b1308b81be..e68829dc73 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll index 6556cf3892..2a27c4bb97 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll index a264426df4..9767f3644f 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll index 79f19f327a..77574f7908 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll index b14af032e0..27e06336bb 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll index 678000eb49..bc5fd34533 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll index 118f8d8d36..3530c25f08 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll index 74734ffd0f..2a99a954a1 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll index 580c679b8a..1f69fa6ab1 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll index 55c32cff7b..af9f9ad37a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll index 132292241b..5fbd12b172 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll index e12811a32b..9e2b2ccce7 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll index 3b38d09e59..d370142560 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll index 22e8c2e0e2..9c72b35ef8 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll index c7d22452af..3fd99f5693 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll index 07e22624c6..3911457095 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll index 287148569c..9395d119fa 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll index 10dd041a9a..c6b18a17a4 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll index 5c1f1bac1c..f819849e5d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll index b031e9eeca..41b7019b36 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_wait_group.ll b/intrinsics/probes/cp_async_bulk_wait_group.ll index cc655f0af5..7b15b95f2e 100644 --- a/intrinsics/probes/cp_async_bulk_wait_group.ll +++ b/intrinsics/probes/cp_async_bulk_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_wait_group_read.ll b/intrinsics/probes/cp_async_bulk_wait_group_read.ll index 31b84429e2..ef72315516 100644 --- a/intrinsics/probes/cp_async_bulk_wait_group_read.ll +++ b/intrinsics/probes/cp_async_bulk_wait_group_read.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_16.ll b/intrinsics/probes/cp_async_ca_16.ll index 9878bc1db0..d442819fa9 100644 --- a/intrinsics/probes/cp_async_ca_16.ll +++ b/intrinsics/probes/cp_async_ca_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_4.ll b/intrinsics/probes/cp_async_ca_4.ll index 77f68e6d2e..fcc01d947a 100644 --- a/intrinsics/probes/cp_async_ca_4.ll +++ b/intrinsics/probes/cp_async_ca_4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_8.ll b/intrinsics/probes/cp_async_ca_8.ll index ed48932575..a6484879f6 100644 --- a/intrinsics/probes/cp_async_ca_8.ll +++ b/intrinsics/probes/cp_async_ca_8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_16.ll b/intrinsics/probes/cp_async_ca_zfill_16.ll index 6d8f828efe..e5c5307128 100644 --- a/intrinsics/probes/cp_async_ca_zfill_16.ll +++ b/intrinsics/probes/cp_async_ca_zfill_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_4.ll b/intrinsics/probes/cp_async_ca_zfill_4.ll index 73bb799348..d052350dba 100644 --- a/intrinsics/probes/cp_async_ca_zfill_4.ll +++ b/intrinsics/probes/cp_async_ca_zfill_4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_8.ll b/intrinsics/probes/cp_async_ca_zfill_8.ll index 1f76c5f957..67dedf0fd5 100644 --- a/intrinsics/probes/cp_async_ca_zfill_8.ll +++ b/intrinsics/probes/cp_async_ca_zfill_8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_cg_16.ll b/intrinsics/probes/cp_async_cg_16.ll index ec0be2d203..fc2fffb621 100644 --- a/intrinsics/probes/cp_async_cg_16.ll +++ b/intrinsics/probes/cp_async_cg_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_cg_zfill_16.ll b/intrinsics/probes/cp_async_cg_zfill_16.ll index e9c1413da9..60adc0b19c 100644 --- a/intrinsics/probes/cp_async_cg_zfill_16.ll +++ b/intrinsics/probes/cp_async_cg_zfill_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_commit_group.ll b/intrinsics/probes/cp_async_commit_group.ll index bdf0051c87..c54588d45c 100644 --- a/intrinsics/probes/cp_async_commit_group.ll +++ b/intrinsics/probes/cp_async_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive.ll b/intrinsics/probes/cp_async_mbarrier_arrive.ll index c5aa0a3417..fe8cf67fba 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll b/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll index 8560ebfbff..55878aca9f 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll b/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll index 785f65460f..675ca33a4c 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll b/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll index 9b7b372217..9d6a7c999d 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_wait_all.ll b/intrinsics/probes/cp_async_wait_all.ll index 0d66e4e8de..047dfac89a 100644 --- a/intrinsics/probes/cp_async_wait_all.ll +++ b/intrinsics/probes/cp_async_wait_all.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_wait_group.ll b/intrinsics/probes/cp_async_wait_group.ll index 2f102d57c7..1c56f56dc0 100644 --- a/intrinsics/probes/cp_async_wait_group.ll +++ b/intrinsics/probes/cp_async_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_f16x2_f32.ll b/intrinsics/probes/cvt_f16x2_f32.ll index 8333b49986..16369f8d87 100644 --- a/intrinsics/probes/cvt_f16x2_f32.ll +++ b/intrinsics/probes/cvt_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_f32x2_bf16x2.ll b/intrinsics/probes/cvt_f32x2_bf16x2.ll index 485ac6e630..9e04c3e223 100644 --- a/intrinsics/probes/cvt_f32x2_bf16x2.ll +++ b/intrinsics/probes/cvt_f32x2_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll b/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll index 74478b7575..1285464da5 100644 --- a/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll +++ b/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll b/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll index 8bf3313ef8..3485fbe220 100644 --- a/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll +++ b/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll b/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll index b214cca747..0c1bda4f50 100644 --- a/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll b/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll index 7a43e5878b..deedecd8f2 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll b/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll index d3f00598ab..34183dbcfd 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll b/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll index a25ce60678..2b910f05c9 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll index 1403f445c6..507b83b328 100644 --- a/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_tf32_f32.ll b/intrinsics/probes/cvt_rn_relu_tf32_f32.ll index c30ce68d6d..74082831d6 100644 --- a/intrinsics/probes/cvt_rn_relu_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll index f8ada23376..71e9323802 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll index f8ccbf7d94..dda12ffd5b 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll index 81f3b26c11..b58f80a85d 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll index 0004bec3f3..0d22fc06b4 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll index da82ae2ce1..5e327931c6 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll index 6851724f0e..ad99540311 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll index 21e76a91b2..92a638441d 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll index f6a2baf698..5428339d4d 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll index e4a4c8ee2e..616ea98828 100644 --- a/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_tf32_f32.ll b/intrinsics/probes/cvt_rn_tf32_f32.ll index dad72f5c89..5c3058c180 100644 --- a/intrinsics/probes/cvt_rn_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll index f2f08234a6..4fb90cadbe 100644 --- a/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rna_tf32_f32.ll b/intrinsics/probes/cvt_rna_tf32_f32.ll index bfc8f18a9b..9c3db649e5 100644 --- a/intrinsics/probes/cvt_rna_tf32_f32.ll +++ b/intrinsics/probes/cvt_rna_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_bf16x2_f32.ll b/intrinsics/probes/cvt_rz_bf16x2_f32.ll index 6e7d27621f..4b9504f02e 100644 --- a/intrinsics/probes/cvt_rz_bf16x2_f32.ll +++ b/intrinsics/probes/cvt_rz_bf16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_f16x2_f32.ll b/intrinsics/probes/cvt_rz_f16x2_f32.ll index 19c5e1df07..9e01d79bdd 100644 --- a/intrinsics/probes/cvt_rz_f16x2_f32.ll +++ b/intrinsics/probes/cvt_rz_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll index b1c09fa641..c6f08683e5 100644 --- a/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_relu_tf32_f32.ll b/intrinsics/probes/cvt_rz_relu_tf32_f32.ll index 3caba1e0ba..d75c3d151d 100644 --- a/intrinsics/probes/cvt_rz_relu_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_relu_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll index 820b2ffbb0..e5ebce1685 100644 --- a/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_tf32_f32.ll b/intrinsics/probes/cvt_rz_tf32_f32.ll index 25830799f4..bb78e1b58b 100644 --- a/intrinsics/probes/cvt_rz_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_f32.ll b/intrinsics/probes/div_rm_f32.ll index 46e42dc2bd..b3b25d668e 100644 --- a/intrinsics/probes/div_rm_f32.ll +++ b/intrinsics/probes/div_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_f64.ll b/intrinsics/probes/div_rm_f64.ll index ab0cfdf057..23c7253a52 100644 --- a/intrinsics/probes/div_rm_f64.ll +++ b/intrinsics/probes/div_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_ftz_f32.ll b/intrinsics/probes/div_rm_ftz_f32.ll index 48097214a8..9423440627 100644 --- a/intrinsics/probes/div_rm_ftz_f32.ll +++ b/intrinsics/probes/div_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_f32.ll b/intrinsics/probes/div_rn_f32.ll index 88dc1c48c2..57cdd67c3d 100644 --- a/intrinsics/probes/div_rn_f32.ll +++ b/intrinsics/probes/div_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_f64.ll b/intrinsics/probes/div_rn_f64.ll index 8aa2f6331a..09f1dbfe3f 100644 --- a/intrinsics/probes/div_rn_f64.ll +++ b/intrinsics/probes/div_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_ftz_f32.ll b/intrinsics/probes/div_rn_ftz_f32.ll index dc80a2b019..1ef6534da5 100644 --- a/intrinsics/probes/div_rn_ftz_f32.ll +++ b/intrinsics/probes/div_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_f32.ll b/intrinsics/probes/div_rp_f32.ll index 5b7c737f97..9665947c1f 100644 --- a/intrinsics/probes/div_rp_f32.ll +++ b/intrinsics/probes/div_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_f64.ll b/intrinsics/probes/div_rp_f64.ll index 08b74a3b5f..ff4efa5724 100644 --- a/intrinsics/probes/div_rp_f64.ll +++ b/intrinsics/probes/div_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_ftz_f32.ll b/intrinsics/probes/div_rp_ftz_f32.ll index 2ca2ac030e..7d1bf32292 100644 --- a/intrinsics/probes/div_rp_ftz_f32.ll +++ b/intrinsics/probes/div_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_f32.ll b/intrinsics/probes/div_rz_f32.ll index 2e42c78628..f88ffea3f9 100644 --- a/intrinsics/probes/div_rz_f32.ll +++ b/intrinsics/probes/div_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_f64.ll b/intrinsics/probes/div_rz_f64.ll index 95db78708c..3309640db6 100644 --- a/intrinsics/probes/div_rz_f64.ll +++ b/intrinsics/probes/div_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_ftz_f32.ll b/intrinsics/probes/div_rz_ftz_f32.ll index 2863b39931..964b417309 100644 --- a/intrinsics/probes/div_rz_ftz_f32.ll +++ b/intrinsics/probes/div_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp2a_s32.ll b/intrinsics/probes/dp2a_s32.ll index b881991a41..967e6bedec 100644 --- a/intrinsics/probes/dp2a_s32.ll +++ b/intrinsics/probes/dp2a_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp2a_u32.ll b/intrinsics/probes/dp2a_u32.ll index 713e02c01b..7c451ceb6b 100644 --- a/intrinsics/probes/dp2a_u32.ll +++ b/intrinsics/probes/dp2a_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp4a_s32.ll b/intrinsics/probes/dp4a_s32.ll index c7eac97056..7169771efa 100644 --- a/intrinsics/probes/dp4a_s32.ll +++ b/intrinsics/probes/dp4a_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp4a_u32.ll b/intrinsics/probes/dp4a_u32.ll index d1df0d2551..a43561009f 100644 --- a/intrinsics/probes/dp4a_u32.ll +++ b/intrinsics/probes/dp4a_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dsmem_read_u32.ll b/intrinsics/probes/dsmem_read_u32.ll index ab4b2b9f76..6f19826a13 100644 --- a/intrinsics/probes/dsmem_read_u32.ll +++ b/intrinsics/probes/dsmem_read_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll b/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll index c5e2576c17..c9bffa71e7 100644 --- a/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll +++ b/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll b/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll index a8f100f2fc..af5eed142d 100644 --- a/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll +++ b/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/elect_sync.lib_nvvm.ll b/intrinsics/probes/elect_sync.lib_nvvm.ll index a3f00f5734..ca3e580bb2 100644 --- a/intrinsics/probes/elect_sync.lib_nvvm.ll +++ b/intrinsics/probes/elect_sync.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/elect_sync.llvm_nvptx.ll b/intrinsics/probes/elect_sync.llvm_nvptx.ll index aa0c4da150..dd12ae4639 100644 --- a/intrinsics/probes/elect_sync.llvm_nvptx.ll +++ b/intrinsics/probes/elect_sync.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg1.lib_nvvm.ll b/intrinsics/probes/envreg1.lib_nvvm.ll index 4429281334..e1953a57b2 100644 --- a/intrinsics/probes/envreg1.lib_nvvm.ll +++ b/intrinsics/probes/envreg1.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg1.llvm_nvptx.ll b/intrinsics/probes/envreg1.llvm_nvptx.ll index 47c348142d..8dd5d4622d 100644 --- a/intrinsics/probes/envreg1.llvm_nvptx.ll +++ b/intrinsics/probes/envreg1.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg2.lib_nvvm.ll b/intrinsics/probes/envreg2.lib_nvvm.ll index ba46be7a38..e4563c6065 100644 --- a/intrinsics/probes/envreg2.lib_nvvm.ll +++ b/intrinsics/probes/envreg2.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg2.llvm_nvptx.ll b/intrinsics/probes/envreg2.llvm_nvptx.ll index 677b208aae..b94dc3b1c4 100644 --- a/intrinsics/probes/envreg2.llvm_nvptx.ll +++ b/intrinsics/probes/envreg2.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_f16.ll b/intrinsics/probes/ex2_approx_f16.ll index b349b0b54e..96762b9385 100644 --- a/intrinsics/probes/ex2_approx_f16.ll +++ b/intrinsics/probes/ex2_approx_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_f32.ll b/intrinsics/probes/ex2_approx_f32.ll index 9a3f1b06a1..3e2940e9e7 100644 --- a/intrinsics/probes/ex2_approx_f32.ll +++ b/intrinsics/probes/ex2_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_ftz_f32.ll b/intrinsics/probes/ex2_approx_ftz_f32.ll index a7238b053f..aeda3a6e42 100644 --- a/intrinsics/probes/ex2_approx_ftz_f32.ll +++ b/intrinsics/probes/ex2_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_mbarrier_init_release_cluster.ll b/intrinsics/probes/fence_mbarrier_init_release_cluster.ll index 1d5a973876..18befc6e5e 100644 --- a/intrinsics/probes/fence_mbarrier_init_release_cluster.ll +++ b/intrinsics/probes/fence_mbarrier_init_release_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll b/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll index dedb0fe28c..dbf14bf9a5 100644 --- a/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll +++ b/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll b/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll index 9c76be7cb6..1e333b04a2 100644 --- a/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll +++ b/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_shared_cta.ll b/intrinsics/probes/fence_proxy_async_shared_cta.ll index fdf3e012cd..e12f45f28f 100644 --- a/intrinsics/probes/fence_proxy_async_shared_cta.ll +++ b/intrinsics/probes/fence_proxy_async_shared_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll index d759939635..10d7b2d4b9 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll index 8713b3c069..6953b8d26d 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll index bcfd6e6125..5b691ccdb5 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll index 63d03fa9e1..77120d4533 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll index 12859da7a3..1033bc7704 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll index 3c2c7ca725..4653852b9e 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll index 8306b2a37e..8611b971b6 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll index 1b9f75a27e..ed3f8f087d 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_bf16x2.ll b/intrinsics/probes/fma_bf16x2.ll index d6909d3938..ed81e08b85 100644 --- a/intrinsics/probes/fma_bf16x2.ll +++ b/intrinsics/probes/fma_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_f16x2.ll b/intrinsics/probes/fma_f16x2.ll index a3282e757d..5f9c897005 100644 --- a/intrinsics/probes/fma_f16x2.ll +++ b/intrinsics/probes/fma_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_f32x2.ll b/intrinsics/probes/fma_f32x2.ll index d1707300d6..bc873d3c22 100644 --- a/intrinsics/probes/fma_f32x2.ll +++ b/intrinsics/probes/fma_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_f16x2.ll b/intrinsics/probes/fma_ftz_f16x2.ll index 9592f11f75..1b6a639888 100644 --- a/intrinsics/probes/fma_ftz_f16x2.ll +++ b/intrinsics/probes/fma_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_f32x2.ll b/intrinsics/probes/fma_ftz_f32x2.ll index cff8d6ff8c..e8cfd80d2f 100644 --- a/intrinsics/probes/fma_ftz_f32x2.ll +++ b/intrinsics/probes/fma_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_relu_f16x2.ll b/intrinsics/probes/fma_ftz_relu_f16x2.ll index 58d7011173..16dbcd4620 100644 --- a/intrinsics/probes/fma_ftz_relu_f16x2.ll +++ b/intrinsics/probes/fma_ftz_relu_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_sat_f16x2.ll b/intrinsics/probes/fma_ftz_sat_f16x2.ll index 01690df283..8ed3eaee8f 100644 --- a/intrinsics/probes/fma_ftz_sat_f16x2.ll +++ b/intrinsics/probes/fma_ftz_sat_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_relu_bf16x2.ll b/intrinsics/probes/fma_relu_bf16x2.ll index 75f5b8ed7a..3446d595e0 100644 --- a/intrinsics/probes/fma_relu_bf16x2.ll +++ b/intrinsics/probes/fma_relu_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_relu_f16x2.ll b/intrinsics/probes/fma_relu_f16x2.ll index 7d11b5544a..8e177dcdaf 100644 --- a/intrinsics/probes/fma_relu_f16x2.ll +++ b/intrinsics/probes/fma_relu_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_f32.ll b/intrinsics/probes/fma_rm_f32.ll index 8512f87b0f..e63d1df244 100644 --- a/intrinsics/probes/fma_rm_f32.ll +++ b/intrinsics/probes/fma_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_f64.ll b/intrinsics/probes/fma_rm_f64.ll index 9b24dd7ddb..81620a3bbf 100644 --- a/intrinsics/probes/fma_rm_f64.ll +++ b/intrinsics/probes/fma_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_ftz_f32.ll b/intrinsics/probes/fma_rm_ftz_f32.ll index 48e88ceed4..3081733044 100644 --- a/intrinsics/probes/fma_rm_ftz_f32.ll +++ b/intrinsics/probes/fma_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_ftz_sat_f32.ll b/intrinsics/probes/fma_rm_ftz_sat_f32.ll index 2595443cdb..b15d18ea29 100644 --- a/intrinsics/probes/fma_rm_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rm_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_sat_f32.ll b/intrinsics/probes/fma_rm_sat_f32.ll index 27c6297977..b1ec943268 100644 --- a/intrinsics/probes/fma_rm_sat_f32.ll +++ b/intrinsics/probes/fma_rm_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_f32.ll b/intrinsics/probes/fma_rn_f32.ll index 482c642d6d..524c1b08f7 100644 --- a/intrinsics/probes/fma_rn_f32.ll +++ b/intrinsics/probes/fma_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_f64.ll b/intrinsics/probes/fma_rn_f64.ll index f2fa7f1805..281f3e3ec8 100644 --- a/intrinsics/probes/fma_rn_f64.ll +++ b/intrinsics/probes/fma_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_ftz_f32.ll b/intrinsics/probes/fma_rn_ftz_f32.ll index 339df3409a..382f8a8e58 100644 --- a/intrinsics/probes/fma_rn_ftz_f32.ll +++ b/intrinsics/probes/fma_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_ftz_sat_f32.ll b/intrinsics/probes/fma_rn_ftz_sat_f32.ll index a0a96e5a6c..d0d853ea2a 100644 --- a/intrinsics/probes/fma_rn_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rn_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_sat_f32.ll b/intrinsics/probes/fma_rn_sat_f32.ll index 7dea1deda7..60c318e861 100644 --- a/intrinsics/probes/fma_rn_sat_f32.ll +++ b/intrinsics/probes/fma_rn_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_f32.ll b/intrinsics/probes/fma_rp_f32.ll index f2019eaeca..5426ea83ab 100644 --- a/intrinsics/probes/fma_rp_f32.ll +++ b/intrinsics/probes/fma_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_f64.ll b/intrinsics/probes/fma_rp_f64.ll index 3366dc1e1b..aa2a9765a7 100644 --- a/intrinsics/probes/fma_rp_f64.ll +++ b/intrinsics/probes/fma_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_ftz_f32.ll b/intrinsics/probes/fma_rp_ftz_f32.ll index 94dcf0c343..3d3300d2a1 100644 --- a/intrinsics/probes/fma_rp_ftz_f32.ll +++ b/intrinsics/probes/fma_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_ftz_sat_f32.ll b/intrinsics/probes/fma_rp_ftz_sat_f32.ll index bd68113921..39a76f1b1b 100644 --- a/intrinsics/probes/fma_rp_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rp_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_sat_f32.ll b/intrinsics/probes/fma_rp_sat_f32.ll index f39ead7fbc..54b094058b 100644 --- a/intrinsics/probes/fma_rp_sat_f32.ll +++ b/intrinsics/probes/fma_rp_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_f32.ll b/intrinsics/probes/fma_rz_f32.ll index a92743f9d0..04aa72dbf6 100644 --- a/intrinsics/probes/fma_rz_f32.ll +++ b/intrinsics/probes/fma_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_f64.ll b/intrinsics/probes/fma_rz_f64.ll index b68b97c09b..d40d2bf1f8 100644 --- a/intrinsics/probes/fma_rz_f64.ll +++ b/intrinsics/probes/fma_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_ftz_f32.ll b/intrinsics/probes/fma_rz_ftz_f32.ll index f16fcdd879..3bbef08a84 100644 --- a/intrinsics/probes/fma_rz_ftz_f32.ll +++ b/intrinsics/probes/fma_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_ftz_sat_f32.ll b/intrinsics/probes/fma_rz_ftz_sat_f32.ll index c33f317692..23500652b6 100644 --- a/intrinsics/probes/fma_rz_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rz_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_sat_f32.ll b/intrinsics/probes/fma_rz_sat_f32.ll index 4dd11f2255..c7910f1a90 100644 --- a/intrinsics/probes/fma_rz_sat_f32.ll +++ b/intrinsics/probes/fma_rz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_sat_f16x2.ll b/intrinsics/probes/fma_sat_f16x2.ll index c7f16702eb..1f27fc11cc 100644 --- a/intrinsics/probes/fma_sat_f16x2.ll +++ b/intrinsics/probes/fma_sat_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/globaltimer.lib_nvvm.ll b/intrinsics/probes/globaltimer.lib_nvvm.ll index 0e201e4d30..b80a000196 100644 --- a/intrinsics/probes/globaltimer.lib_nvvm.ll +++ b/intrinsics/probes/globaltimer.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/globaltimer.llvm_nvptx.ll b/intrinsics/probes/globaltimer.llvm_nvptx.ll index 7e8a29d2e4..c52819f587 100644 --- a/intrinsics/probes/globaltimer.llvm_nvptx.ll +++ b/intrinsics/probes/globaltimer.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dependency_launch_dependents.ll b/intrinsics/probes/grid_dependency_launch_dependents.ll index 6b7bde10f0..c0ecc21df5 100644 --- a/intrinsics/probes/grid_dependency_launch_dependents.ll +++ b/intrinsics/probes/grid_dependency_launch_dependents.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dependency_wait.ll b/intrinsics/probes/grid_dependency_wait.ll index e4e2104d00..3e3e9f7f13 100644 --- a/intrinsics/probes/grid_dependency_wait.ll +++ b/intrinsics/probes/grid_dependency_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_x.ll b/intrinsics/probes/grid_dim_x.ll index 343b8b0f43..021d4b4930 100644 --- a/intrinsics/probes/grid_dim_x.ll +++ b/intrinsics/probes/grid_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_y.ll b/intrinsics/probes/grid_dim_y.ll index 94aceb5bef..ba385df01b 100644 --- a/intrinsics/probes/grid_dim_y.ll +++ b/intrinsics/probes/grid_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_z.ll b/intrinsics/probes/grid_dim_z.ll index 53b0fce13d..c1ba6186bd 100644 --- a/intrinsics/probes/grid_dim_z.ll +++ b/intrinsics/probes/grid_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/gridid.lib_nvvm.ll b/intrinsics/probes/gridid.lib_nvvm.ll index 538ff1c488..dfd3b155d9 100644 --- a/intrinsics/probes/gridid.lib_nvvm.ll +++ b/intrinsics/probes/gridid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/gridid.llvm_nvptx.ll b/intrinsics/probes/gridid.llvm_nvptx.ll index d534b3f0cf..1cc00bc71d 100644 --- a/intrinsics/probes/gridid.llvm_nvptx.ll +++ b/intrinsics/probes/gridid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lane_id.ll b/intrinsics/probes/lane_id.ll index 7d247878c1..6ce2e6c010 100644 --- a/intrinsics/probes/lane_id.ll +++ b/intrinsics/probes/lane_id.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_eq.ll b/intrinsics/probes/lanemask_eq.ll index 00138014c9..4715f8beef 100644 --- a/intrinsics/probes/lanemask_eq.ll +++ b/intrinsics/probes/lanemask_eq.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_ge.ll b/intrinsics/probes/lanemask_ge.ll index 2ebf95d1ba..74f4cb05d7 100644 --- a/intrinsics/probes/lanemask_ge.ll +++ b/intrinsics/probes/lanemask_ge.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_gt.ll b/intrinsics/probes/lanemask_gt.ll index e8db3c8fa8..d051e6f22b 100644 --- a/intrinsics/probes/lanemask_gt.ll +++ b/intrinsics/probes/lanemask_gt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_le.ll b/intrinsics/probes/lanemask_le.ll index 55a505db3e..ac481c0dc8 100644 --- a/intrinsics/probes/lanemask_le.ll +++ b/intrinsics/probes/lanemask_le.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_lt.ll b/intrinsics/probes/lanemask_lt.ll index 62d75dc764..33884fcaac 100644 --- a/intrinsics/probes/lanemask_lt.ll +++ b/intrinsics/probes/lanemask_lt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll index 28e7b4fcaa..031926dd1e 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll index 0cf573e489..6577081f01 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll index c50c963a9a..62fbc878be 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll index 37eb6f73f8..96ccc4758d 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll index 8491cbc23b..ad5f04ddd1 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll index 2ed76cad94..d22fe81a77 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll index 1df1ba8c59..8154dccde0 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll index cd0c066b02..03b7528b36 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll index 44dbb189c0..a4d2aa9cd8 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll index 172fbb6b99..7323203f8a 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll index 41dade35fc..478ca9b810 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll index f25fd05e59..076082e129 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll index 41ecb108e3..158cc6a211 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll index a857a1e019..22fd2f7353 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll index 04c7aa23b9..d03f36823d 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll index 6c7378e598..fb6e9a10c1 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll index 1afaf88b9d..f4c78dec50 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll index d2aed9031f..5e3b152df2 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lg2_approx_f32.ll b/intrinsics/probes/lg2_approx_f32.ll index bea1bca816..801c96fa2c 100644 --- a/intrinsics/probes/lg2_approx_f32.ll +++ b/intrinsics/probes/lg2_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lg2_approx_ftz_f32.ll b/intrinsics/probes/lg2_approx_ftz_f32.ll index d0a6fbf0f9..6aa6a81f86 100644 --- a/intrinsics/probes/lg2_approx_ftz_f32.ll +++ b/intrinsics/probes/lg2_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/map_shared_rank.ll b/intrinsics/probes/map_shared_rank.ll index 47a23172e3..b29e20077f 100644 --- a/intrinsics/probes/map_shared_rank.ll +++ b/intrinsics/probes/map_shared_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_all_i64_sync.ll b/intrinsics/probes/match_all_i64_sync.ll index 19a634eb5a..4539401a92 100644 --- a/intrinsics/probes/match_all_i64_sync.ll +++ b/intrinsics/probes/match_all_i64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_all_sync.ll b/intrinsics/probes/match_all_sync.ll index 95b63bf26c..1abb8955d5 100644 --- a/intrinsics/probes/match_all_sync.ll +++ b/intrinsics/probes/match_all_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_any_i64_sync.ll b/intrinsics/probes/match_any_i64_sync.ll index 7fc4e72ce1..8e8a26f58d 100644 --- a/intrinsics/probes/match_any_i64_sync.ll +++ b/intrinsics/probes/match_any_i64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_any_sync.ll b/intrinsics/probes/match_any_sync.ll index 341eadbf1d..fdd5b17fc5 100644 --- a/intrinsics/probes/match_any_sync.ll +++ b/intrinsics/probes/match_any_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_bf16.ll b/intrinsics/probes/max_bf16.ll index fe8336e91b..3a86059b2e 100644 --- a/intrinsics/probes/max_bf16.ll +++ b/intrinsics/probes/max_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_bf16x2.ll b/intrinsics/probes/max_bf16x2.ll index ea003438d7..682308c492 100644 --- a/intrinsics/probes/max_bf16x2.ll +++ b/intrinsics/probes/max_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_f16.ll b/intrinsics/probes/max_f16.ll index 13a9fd521d..cace5d385e 100644 --- a/intrinsics/probes/max_f16.ll +++ b/intrinsics/probes/max_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_f16x2.ll b/intrinsics/probes/max_f16x2.ll index 022fd4bfbe..006782ea49 100644 --- a/intrinsics/probes/max_f16x2.ll +++ b/intrinsics/probes/max_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_f16.ll b/intrinsics/probes/max_ftz_f16.ll index 5b07edb68b..68ac866a62 100644 --- a/intrinsics/probes/max_ftz_f16.ll +++ b/intrinsics/probes/max_ftz_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_f16x2.ll b/intrinsics/probes/max_ftz_f16x2.ll index 057ab56fee..9d0f067f6a 100644 --- a/intrinsics/probes/max_ftz_f16x2.ll +++ b/intrinsics/probes/max_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_f16.ll b/intrinsics/probes/max_ftz_nan_f16.ll index 7001566e36..9691c848dd 100644 --- a/intrinsics/probes/max_ftz_nan_f16.ll +++ b/intrinsics/probes/max_ftz_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_f16x2.ll b/intrinsics/probes/max_ftz_nan_f16x2.ll index cbd7f3e9bf..4dc884d32f 100644 --- a/intrinsics/probes/max_ftz_nan_f16x2.ll +++ b/intrinsics/probes/max_ftz_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll index 43230522f3..27e56a9aea 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll index 95384e2bf3..f934ab80ce 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll index 6eab78127c..dd4f5f9a0e 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f16.ll b/intrinsics/probes/max_ftz_xorsign_abs_f16.ll index 15eec92890..054081a769 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll b/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll index 2118f3d88f..eb1b5bd378 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f32.ll b/intrinsics/probes/max_ftz_xorsign_abs_f32.ll index fcb22c694f..27b2acacb9 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_bf16.ll b/intrinsics/probes/max_nan_bf16.ll index f9f274d627..ae90e28299 100644 --- a/intrinsics/probes/max_nan_bf16.ll +++ b/intrinsics/probes/max_nan_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_bf16x2.ll b/intrinsics/probes/max_nan_bf16x2.ll index 7827531d1a..b593886079 100644 --- a/intrinsics/probes/max_nan_bf16x2.ll +++ b/intrinsics/probes/max_nan_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_f16.ll b/intrinsics/probes/max_nan_f16.ll index f28c3996bd..d7b328a84d 100644 --- a/intrinsics/probes/max_nan_f16.ll +++ b/intrinsics/probes/max_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_f16x2.ll b/intrinsics/probes/max_nan_f16x2.ll index 079e47573c..d6ba8a1949 100644 --- a/intrinsics/probes/max_nan_f16x2.ll +++ b/intrinsics/probes/max_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_bf16.ll b/intrinsics/probes/max_nan_xorsign_abs_bf16.ll index 470c85d7df..08c7910345 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_bf16.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll b/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll index 04113f876e..319f6ec6d1 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f16.ll b/intrinsics/probes/max_nan_xorsign_abs_f16.ll index 7bd1c5ff0b..12fc09d610 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll index e1ef45fea4..4e3cfa51f5 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f32.ll b/intrinsics/probes/max_nan_xorsign_abs_f32.ll index 6fd1e23793..774b9bda1a 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_relu_s16x2.ll b/intrinsics/probes/max_relu_s16x2.ll index dcb8aa6bf2..67d6f0de9e 100644 --- a/intrinsics/probes/max_relu_s16x2.ll +++ b/intrinsics/probes/max_relu_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_relu_s32.ll b/intrinsics/probes/max_relu_s32.ll index 3862728f69..75c5db8430 100644 --- a/intrinsics/probes/max_relu_s32.ll +++ b/intrinsics/probes/max_relu_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_s16x2.ll b/intrinsics/probes/max_s16x2.ll index a906011a50..c036efe51f 100644 --- a/intrinsics/probes/max_s16x2.ll +++ b/intrinsics/probes/max_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_u16x2.ll b/intrinsics/probes/max_u16x2.ll index 41050f345e..6290a4ee38 100644 --- a/intrinsics/probes/max_u16x2.ll +++ b/intrinsics/probes/max_u16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_bf16.ll b/intrinsics/probes/max_xorsign_abs_bf16.ll index 34e9abc3ce..237dacee2f 100644 --- a/intrinsics/probes/max_xorsign_abs_bf16.ll +++ b/intrinsics/probes/max_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_bf16x2.ll b/intrinsics/probes/max_xorsign_abs_bf16x2.ll index 784b2d785e..f56e5d5661 100644 --- a/intrinsics/probes/max_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/max_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f16.ll b/intrinsics/probes/max_xorsign_abs_f16.ll index 1b8ad29e96..e4f546912c 100644 --- a/intrinsics/probes/max_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f16x2.ll b/intrinsics/probes/max_xorsign_abs_f16x2.ll index 594133c8dd..115ddf19b3 100644 --- a/intrinsics/probes/max_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f32.ll b/intrinsics/probes/max_xorsign_abs_f32.ll index 9a62bb7f5b..e1771fe5ed 100644 --- a/intrinsics/probes/max_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive.ll b/intrinsics/probes/mbarrier_arrive.ll index 812b544dad..436f54963f 100644 --- a/intrinsics/probes/mbarrier_arrive.ll +++ b/intrinsics/probes/mbarrier_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_cluster.ll b/intrinsics/probes/mbarrier_arrive_cluster.ll index 1bc65e7ac3..282e39a58d 100644 --- a/intrinsics/probes/mbarrier_arrive_cluster.ll +++ b/intrinsics/probes/mbarrier_arrive_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_expect_tx.ll b/intrinsics/probes/mbarrier_arrive_expect_tx.ll index bc0b83b1a2..4194c87df4 100644 --- a/intrinsics/probes/mbarrier_arrive_expect_tx.ll +++ b/intrinsics/probes/mbarrier_arrive_expect_tx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll b/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll index cfa8bdced0..9304ef943f 100644 --- a/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll +++ b/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_init.ll b/intrinsics/probes/mbarrier_init.ll index ca0597355b..b516036b45 100644 --- a/intrinsics/probes/mbarrier_init.ll +++ b/intrinsics/probes/mbarrier_init.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_inval.ll b/intrinsics/probes/mbarrier_inval.ll index 86ecca238d..9931b0fa0f 100644 --- a/intrinsics/probes/mbarrier_inval.ll +++ b/intrinsics/probes/mbarrier_inval.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_test_wait.ll b/intrinsics/probes/mbarrier_test_wait.ll index 45165e6905..496ca5bbda 100644 --- a/intrinsics/probes/mbarrier_test_wait.ll +++ b/intrinsics/probes/mbarrier_test_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait.ll b/intrinsics/probes/mbarrier_try_wait.ll index 1d8b1c2b7c..dd7f8befa2 100644 --- a/intrinsics/probes/mbarrier_try_wait.ll +++ b/intrinsics/probes/mbarrier_try_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait_parity.ll b/intrinsics/probes/mbarrier_try_wait_parity.ll index 2701f0ba92..b97e381d47 100644 --- a/intrinsics/probes/mbarrier_try_wait_parity.ll +++ b/intrinsics/probes/mbarrier_try_wait_parity.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll b/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll index 138697eaea..b16f0f3dbb 100644 --- a/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll +++ b/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_bf16.ll b/intrinsics/probes/min_bf16.ll index 9418ae038e..5677a9093b 100644 --- a/intrinsics/probes/min_bf16.ll +++ b/intrinsics/probes/min_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_bf16x2.ll b/intrinsics/probes/min_bf16x2.ll index 05308fee3e..1de2e4187b 100644 --- a/intrinsics/probes/min_bf16x2.ll +++ b/intrinsics/probes/min_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_f16.ll b/intrinsics/probes/min_f16.ll index 6f43194cd3..d86ffe9ab4 100644 --- a/intrinsics/probes/min_f16.ll +++ b/intrinsics/probes/min_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_f16x2.ll b/intrinsics/probes/min_f16x2.ll index 314038d475..6692342cf5 100644 --- a/intrinsics/probes/min_f16x2.ll +++ b/intrinsics/probes/min_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_f16.ll b/intrinsics/probes/min_ftz_f16.ll index ed6c06afb4..74b8bc0fd5 100644 --- a/intrinsics/probes/min_ftz_f16.ll +++ b/intrinsics/probes/min_ftz_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_f16x2.ll b/intrinsics/probes/min_ftz_f16x2.ll index 4f98f76ed1..b56ca3b631 100644 --- a/intrinsics/probes/min_ftz_f16x2.ll +++ b/intrinsics/probes/min_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_f16.ll b/intrinsics/probes/min_ftz_nan_f16.ll index a9b6c2afa5..e900154728 100644 --- a/intrinsics/probes/min_ftz_nan_f16.ll +++ b/intrinsics/probes/min_ftz_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_f16x2.ll b/intrinsics/probes/min_ftz_nan_f16x2.ll index c83fc9dbeb..ce14a43621 100644 --- a/intrinsics/probes/min_ftz_nan_f16x2.ll +++ b/intrinsics/probes/min_ftz_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll index 9f539717db..5ebbc01df5 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll index 47d1485bae..0146f933f2 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll index 8d2e1ab809..fcaa78c648 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f16.ll b/intrinsics/probes/min_ftz_xorsign_abs_f16.ll index df553bd8dd..53d755b3e1 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll b/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll index 5cdec6b102..07116d3922 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f32.ll b/intrinsics/probes/min_ftz_xorsign_abs_f32.ll index a6fb8808a4..00fe845bee 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_bf16.ll b/intrinsics/probes/min_nan_bf16.ll index 7abba0f3e3..e498d26947 100644 --- a/intrinsics/probes/min_nan_bf16.ll +++ b/intrinsics/probes/min_nan_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_bf16x2.ll b/intrinsics/probes/min_nan_bf16x2.ll index b471fb1b36..e895a7fcca 100644 --- a/intrinsics/probes/min_nan_bf16x2.ll +++ b/intrinsics/probes/min_nan_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_f16.ll b/intrinsics/probes/min_nan_f16.ll index 1cfd453d63..3944ad31c5 100644 --- a/intrinsics/probes/min_nan_f16.ll +++ b/intrinsics/probes/min_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_f16x2.ll b/intrinsics/probes/min_nan_f16x2.ll index ac093967da..49a187fe60 100644 --- a/intrinsics/probes/min_nan_f16x2.ll +++ b/intrinsics/probes/min_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_bf16.ll b/intrinsics/probes/min_nan_xorsign_abs_bf16.ll index 4d330ddf60..856a2aa03d 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_bf16.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll b/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll index b1e322cec1..ebb284a636 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f16.ll b/intrinsics/probes/min_nan_xorsign_abs_f16.ll index a5e981124e..88e05ce753 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll index ed8c199cbb..5100652095 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f32.ll b/intrinsics/probes/min_nan_xorsign_abs_f32.ll index ecb73bf460..6451a7d39c 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_relu_s16x2.ll b/intrinsics/probes/min_relu_s16x2.ll index ba5c6ff27d..7d78f31221 100644 --- a/intrinsics/probes/min_relu_s16x2.ll +++ b/intrinsics/probes/min_relu_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_relu_s32.ll b/intrinsics/probes/min_relu_s32.ll index bf6c29628c..5a89ba3088 100644 --- a/intrinsics/probes/min_relu_s32.ll +++ b/intrinsics/probes/min_relu_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_s16x2.ll b/intrinsics/probes/min_s16x2.ll index e55b538b76..2f09081a28 100644 --- a/intrinsics/probes/min_s16x2.ll +++ b/intrinsics/probes/min_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_u16x2.ll b/intrinsics/probes/min_u16x2.ll index 2412f58717..3cfa159096 100644 --- a/intrinsics/probes/min_u16x2.ll +++ b/intrinsics/probes/min_u16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_bf16.ll b/intrinsics/probes/min_xorsign_abs_bf16.ll index 16f9232ba8..856fcdb4da 100644 --- a/intrinsics/probes/min_xorsign_abs_bf16.ll +++ b/intrinsics/probes/min_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_bf16x2.ll b/intrinsics/probes/min_xorsign_abs_bf16x2.ll index f9536a2e30..4584d7406c 100644 --- a/intrinsics/probes/min_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/min_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f16.ll b/intrinsics/probes/min_xorsign_abs_f16.ll index 266e93aae9..8220686047 100644 --- a/intrinsics/probes/min_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f16x2.ll b/intrinsics/probes/min_xorsign_abs_f16x2.ll index f232d1d485..7b5b97cfc4 100644 --- a/intrinsics/probes/min_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f32.ll b/intrinsics/probes/min_xorsign_abs_f32.ll index 738fe1d28f..1d51eedc2d 100644 --- a/intrinsics/probes/min_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll b/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll index 9e62d21eb8..4c35581f44 100644 --- a/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll index c08e480bf9..0215829970 100644 --- a/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f16_f16.ll b/intrinsics/probes/mma_m16n8k16_f16_f16.ll index 453f5c0c56..c9ef0bcde5 100644 --- a/intrinsics/probes/mma_m16n8k16_f16_f16.ll +++ b/intrinsics/probes/mma_m16n8k16_f16_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f32_bf16.ll b/intrinsics/probes/mma_m16n8k16_f32_bf16.ll index e4ef080226..6741950ebf 100644 --- a/intrinsics/probes/mma_m16n8k16_f32_bf16.ll +++ b/intrinsics/probes/mma_m16n8k16_f32_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f32_f16.ll b/intrinsics/probes/mma_m16n8k16_f32_f16.ll index 47b6fdb9b2..fc67dd702d 100644 --- a/intrinsics/probes/mma_m16n8k16_f32_f16.ll +++ b/intrinsics/probes/mma_m16n8k16_f32_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll index 2de6dc2e57..83ea34084a 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll index e753a9b7b5..86e0d1e57a 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll index d280bf6e55..baf48b8ce9 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll index f94facd4b6..d6e025728f 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll index c3d2fccb52..2058dd155f 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll index 1c78c29d20..82d221af39 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll index d465642ab7..18b9eec609 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll index 0c4d888e0e..5b60d9df54 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8.ll b/intrinsics/probes/mma_m16n8k16_s32_s8.ll index 679eef9ff0..e5eb64a7d7 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll index f2e5a9bae7..6dd650a7c8 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll index fc999ca787..cea4bb5db7 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll index 5b6235deeb..10db703ec6 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8.ll b/intrinsics/probes/mma_m16n8k16_s32_u8.ll index e62b4aee62..4fa416d4ac 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll index a97a3b8529..e19ff7c364 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll index 5208f101a6..512f9c87ac 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll index a4a50d86ac..8e00faa6c6 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll b/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll index f84ab96a5c..8ee2bb29a8 100644 --- a/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll index 5a26b4e0a0..02b9847895 100644 --- a/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll index 1f06e0d6b4..f9319e634f 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll index 8dbf112094..7cd5a284e4 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll index 5d219264ee..da3d82f0d9 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll index a22bda1f0c..24e0020e04 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll index 8b0cc453ca..bc648bdeee 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll index 3443552ecc..d05d8e3749 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll index b7b82c24ad..aa42606afe 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll index 200850114d..33d50e8f9c 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll index 5501ea9ab1..dd3ca8ba29 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll index 0b7ddf7ead..1aa7d23221 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll index 434f11c469..82ae549a97 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll index eefde9d925..30d119d3ea 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll index 2b785c57a4..a26da8fe36 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll index 300f385a29..d1e199db09 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll index ca62230a91..998df366ce 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll index f49a0ee95a..9d10e1568f 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll index 0d35473eef..c851db8f69 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll index 4de3e423c6..6efdbfc0dd 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll index 926ed81052..cdb94a9a01 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll index 90fd21ba6a..da2afd5f88 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll index 62c472efcc..c7a987b4f4 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll index a571f6b4a8..7185c6e20c 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll index 846c0a0490..0dd1ea8f30 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll index 7cd666c395..eee5c6be4a 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll index f774bba103..10e0041e45 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll index 2638b2a70b..b66f553f36 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll index 68b9561d8c..628a887ed5 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll index cb92d741c6..02bd5cda71 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll index 2369c278b6..8a0fa2ab54 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll index 49b1650617..d9d980756d 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll index a308681933..9bd7f75815 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll index 058e7b1c71..ef7049c062 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll index c36a799cb6..89d26c8f85 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll index 0df91cfa1d..e633dc3542 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll index 24aa20cbe6..7b3c13d6aa 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll index a57858a316..1d7852f32b 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll index ca4ac334fc..7d6b1b312c 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll index b315777713..ed4ff448e6 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll index 3437e4a556..8072874691 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll index 73cdc4dadb..896b05deb1 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll index 5abe1d2f35..aa92cf6ea8 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll index 5889c56b80..e4942034ac 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll index 3b109a714b..f931cb8fe4 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll index 5542473197..0a6a4e009e 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll index d69b824871..28d0e952b4 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll index a9e0b871b8..988de0edfc 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll index e0a0f7823e..4989b05c51 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll index a853457615..58446d29ad 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll index 3ab8311a1e..4673d78084 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll index cc1056f2ce..21074d00e9 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll index 4b2f5b1751..bca8a5d197 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll index 7b3eb550b5..7e8bd3152d 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll index 9f0e84b2f6..afa67556a3 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll index ed96abd477..cc980c3c53 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll index 14ad8885d5..382edf1487 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll index d34fd6f403..595b5fefce 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll index 64f038b7a0..279b7960e2 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll index 922705320b..30c97154d1 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll index d46e3b53fd..20dc4e6d01 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll index 2c43f427f6..9332421bad 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll index c4073ec41b..814095765f 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll index 5c5b69b37c..9b22600530 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll index edc6a9bff7..c836a6dd8c 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll index faf86f27f5..7522061901 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll index 86ea27da3a..44e56a00d9 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll index 38ed851c0c..b621933057 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll index f3147dfdc5..6483673f5a 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll index 7f20654e60..03f83694c1 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll index 43eba7ee66..9cd7d94b1f 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll index 9ec2bb9893..f81531c9ba 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll index 1c1fba18f0..dc951ecf30 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll index aa720f76a3..ff8bd23bef 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll index ddcc3fe204..b813956e47 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll index dff71176ff..cb83c3b4b5 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll index fc17a7635d..57d4516f27 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll index 90ad49bfe9..7fe28b2b6d 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll index 58d7a95bd1..73aeb03967 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll index d9980f42ab..3b3cd352af 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll index e5acd27cac..7469b973a0 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll index f740cf0caa..90fcb0dc46 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll index 28ae2ce0fe..cb6b1c3fd6 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll index 469a8b45cd..cf78d53946 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll index 5a26a940f2..7fbd0fa3c5 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4.ll b/intrinsics/probes/mma_m16n8k32_s32_s4.ll index 41c1a53a55..7bbe56b3f0 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll index 39b954eff2..bcd01ea59f 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll index a0a86aa7cb..b07a353b2d 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll index 2d48bcd222..33ec80744d 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_m16n8k32_s32_s8.ll index 78cda04b8c..640309be7f 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll index 44863e7267..04c0362580 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll index a9413d1147..b15a762fe1 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll index 5b2745ed3c..990a8d8934 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4.ll b/intrinsics/probes/mma_m16n8k32_s32_u4.ll index 6043905437..c62be215d6 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll index d2a56d30f7..927c8a33fa 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll index c8128f762a..90c005e532 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll index 1e66dda645..c47a042fa1 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_m16n8k32_s32_u8.ll index da93473494..e59acfe5e1 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll index aecbb6655f..d3a4ecc075 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll index 7fafd5a362..7e0443b778 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll index 2cd234df4a..8a4d6abb34 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k4_f32_tf32.ll b/intrinsics/probes/mma_m16n8k4_f32_tf32.ll index 893776dd11..213c65ce90 100644 --- a/intrinsics/probes/mma_m16n8k4_f32_tf32.ll +++ b/intrinsics/probes/mma_m16n8k4_f32_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_m16n8k64_s32_s4.ll index b615a63e2e..b8508b431c 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll index 32eabac6a4..685e559e7c 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll index 71e33f799c..406f5e4820 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll index 048a4388d5..2189ca51f5 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_m16n8k64_s32_u4.ll index 7ad488458f..bfe315b3d5 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll index a073c4cddd..020833ec3d 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll index 1d95970e1b..8cf1afdff0 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll index 7998e2b4fc..bd8dccd49f 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f16_f16.ll b/intrinsics/probes/mma_m16n8k8_f16_f16.ll index 273df2e868..86cacf0fcf 100644 --- a/intrinsics/probes/mma_m16n8k8_f16_f16.ll +++ b/intrinsics/probes/mma_m16n8k8_f16_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_bf16.ll b/intrinsics/probes/mma_m16n8k8_f32_bf16.ll index 7b61c45e54..7ec767505f 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_bf16.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_f16.ll b/intrinsics/probes/mma_m16n8k8_f32_f16.ll index 7f575af76d..56d6b896fb 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_f16.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_tf32.ll b/intrinsics/probes/mma_m16n8k8_f32_tf32.ll index 2e57642567..3ea6fcd9ef 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_tf32.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll b/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll index c144ee0dd0..dc286b62d0 100644 --- a/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll index 3b4e78cb51..5bfc03342e 100644 --- a/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8.ll b/intrinsics/probes/mma_m8n8k16_s32_s8.ll index 1ba0912e9e..c303d9002f 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll index 9668dba974..19aca70158 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll index 072492fc83..7f80f11e84 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll index e9e5b79f36..5328d7f70b 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8.ll b/intrinsics/probes/mma_m8n8k16_s32_u8.ll index 51c744bdfc..9267dd319a 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll index 65a9723d88..4a126eb520 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll index 7c8f2be17b..592a957326 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll index 260d0a162a..6619787639 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4.ll b/intrinsics/probes/mma_m8n8k32_s32_s4.ll index 43d5adb9f3..149b271fc9 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll index c67e49c247..737081a531 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll index c23d047c78..45bd04b208 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll index 80958df336..a99f57e8bb 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4.ll b/intrinsics/probes/mma_m8n8k32_s32_u4.ll index 683c524bdd..9ae5891b82 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll index 16bfbad858..19cce082dd 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll index 2a6d7f8f85..435d9546dd 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll index 01e8bd64f2..e851b21058 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k4_f64.ll b/intrinsics/probes/mma_m8n8k4_f64.ll index 2942231dfc..08412039d8 100644 --- a/intrinsics/probes/mma_m8n8k4_f64.ll +++ b/intrinsics/probes/mma_m8n8k4_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll index 18333bce92..96667f3d3d 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll index 7ffaff1ff7..df887d895f 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll index 94078e592c..441f824224 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll index aa7c2c8576..2667f95cb9 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll index ddb94dc615..7202919dae 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll index 3acfe03695..a08498a421 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll index b5bc486f2c..11b14b2d46 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll index 00e3290430..ead0b4c2e1 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll index cd396a8b45..403b76de79 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll index 0e28719d3e..9928a03d17 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll index 8bf57d0462..d9640e08f1 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll index 42c0959f2b..283203d9fe 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll index d527b7b781..46b9bb922a 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll index e749cc7a04..ecb293c0bd 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll index 03cea41b8a..173fa1b63b 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll index ba932b8223..29e1ec44e9 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll index a668c46d0c..0119cbbd90 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll index dab7342dfe..4f5521dc90 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll index 33c6e33567..56c1ecd6c0 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll index 608f26ef91..558ab063a8 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll index 67b8f7462c..67d16684bc 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll index 30fc48f69b..60753cc37b 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll index 711d9f662d..4e0f64658d 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll index 123ce12857..174b808cd5 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll index 0fae98426e..68d469bcee 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll index 8fa4f58583..99145b0285 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll index 851b5af553..c46921e487 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll index f97476ecff..aea0b9e78b 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll index b58205ea1b..61955f6903 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll index 61b7bfb2c1..83570d1dc3 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll index 8ba6f5ff75..59afec32ba 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll index 0abc6394ce..d2fcc01ed6 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll index 2adfbd4448..984c5cb89e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll index 5f3231a97d..f6400318c1 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll index 9239a788fd..fbda14fade 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll index eb869c9f2e..e7e23ce81a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll index ab4c42057e..9d32e58a6a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll index 205de81d2a..643019b2a5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll index c8ff2803c6..967ed2ee9f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll index 5c61435d90..00a79db7ff 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll index d8bf309bae..06b072b4e5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll index 790f3c6ecd..bbb267df8a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll index 20a16046f6..1de44a2664 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll index caa5b60714..f55b741c92 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll index 2ab771ade4..2def910dab 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll index 41498248cd..c32f090517 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll index 560a642062..703b47f172 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll index d0726c08a7..0b5b7b3b1e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll index da039e975f..8ce3e62e7c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll index 86a2fefa39..d433e31439 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll index 79bd0a3faf..f4a7fc31f6 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll index b910376094..ba1113edce 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll index 2a7a27bb3d..de17e3f4e2 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll index 91739fa237..b8ba5f5c23 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll index 2c0e6abea0..6ec5462cba 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll index e363f1b45c..b5eda5ad89 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll index 1091bf9c78..828f28734b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll index c819c39e81..1800bb5a6b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll index de4cb989dc..dde889867f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll index 776f8f74b5..cf082791ef 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll index 91c9fac8bf..0a10fe86ee 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll index 0266ab7a54..f440330005 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll index 482a4720f7..261e239d29 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll index ce9d0a1bda..cf60bcbd7f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll index b2e867a1ca..73ba34ea83 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll index 00c1344735..c670f041fa 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll index a4fd87e088..8cad42816e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll index 1998d39aa2..aea64a89d8 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll index 33951a71b8..9a29df3237 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll index 818c187ee8..efd09e750d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll index f97e5eba95..bb9dca093d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll index 0977e00d51..a48cc6b5da 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll index 5fb712650a..823dce168d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll index 68fb590108..fa88706b6e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll index 554dd67bbd..9ad900ace9 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll index 3c3b813a26..170cea20ae 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll index cd6829add3..ee489539fe 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll index 992e398e1c..b4d941d2bc 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll index 65b3287802..e028ac6296 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll index 8503224c23..0bbd1f96c4 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll index b8a9c0b4f7..8fc70e2dfc 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll index fa8affa52b..8167fbc057 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll index 80e3610f1a..77a8fd359b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll index c1ba304648..9b0e4ee6f3 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll index a7bc414791..4fe29dcb9c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll index e04fc0d4c0..20f6077e9b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll index 3b96d65cad..6c2e5266ed 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll index d35e05e1d2..5bc49f3414 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll index bd32fc589d..9b9be63e7b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll index 5e47df8e05..6e376280ba 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll index f28939cc99..769a78ad2c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll index 945eb412d5..8c70e773a9 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll index 10b8494f2c..b3d9c786a5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll index c1f0da385d..da1310d703 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll index 86a67d036a..c721feb387 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll index ed2a5f0087..f7b53607e9 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll index 6bea2e42ff..ddb4a40748 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll index b6e507974d..fa750c86dc 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll index ebfb33f429..23dfd8217c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll index 9858438582..768e5852cb 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll index 11696d9815..8a53a6925e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll index 32e4610819..36a876882c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll index c548e21caa..c837b9fa8e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll index 28015c188c..38339d1e7a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll index 30aabae5ba..fb14966040 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll index 5410db6fcd..7bc4e4fd37 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll index fb5c81d688..38b07038b2 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll index b18f70d932..3f59ef41cc 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll index e503b45d9a..aad0083dc1 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll index b38ad60a13..32cdb978f1 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll index 0b881a2749..263e8761b3 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll index 72d230768e..e6800cda66 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll index 68afb06383..c88e5c886a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll index 8383627cf8..f83c391104 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll index 622e6c031f..ba34d5c731 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll index 81e1a6345e..bd97d29a95 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll index bec156e306..772b5a718f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll index 53d81a7fe1..dfb369ffda 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll index e2254fa7ad..77bc70bef9 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll index 0b7e6bf528..3b3b8f751c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll index 6d10cedb67..017bdec0be 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll index 5ce17bd0c8..f22e8f891e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/movmatrix_trans_b16.ll b/intrinsics/probes/movmatrix_trans_b16.ll index cf3ec917d7..62c2e50758 100644 --- a/intrinsics/probes/movmatrix_trans_b16.ll +++ b/intrinsics/probes/movmatrix_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_bf16x2.ll b/intrinsics/probes/mul_bf16x2.ll index 3591e8ed24..b4281fcc47 100644 --- a/intrinsics/probes/mul_bf16x2.ll +++ b/intrinsics/probes/mul_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_f16x2.ll b/intrinsics/probes/mul_f16x2.ll index 3b5b3a01ad..47df7da974 100644 --- a/intrinsics/probes/mul_f16x2.ll +++ b/intrinsics/probes/mul_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_f32x2.ll b/intrinsics/probes/mul_f32x2.ll index 24d1bb27e2..ca3248caa4 100644 --- a/intrinsics/probes/mul_f32x2.ll +++ b/intrinsics/probes/mul_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_ftz_f32x2.ll b/intrinsics/probes/mul_ftz_f32x2.ll index 84de580269..1bde132cb4 100644 --- a/intrinsics/probes/mul_ftz_f32x2.ll +++ b/intrinsics/probes/mul_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_f32.ll b/intrinsics/probes/mul_rm_f32.ll index 2a5f4660ea..3284a8358e 100644 --- a/intrinsics/probes/mul_rm_f32.ll +++ b/intrinsics/probes/mul_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_f64.ll b/intrinsics/probes/mul_rm_f64.ll index 65d6ddcff7..2eeca8f2d4 100644 --- a/intrinsics/probes/mul_rm_f64.ll +++ b/intrinsics/probes/mul_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_ftz_f32.ll b/intrinsics/probes/mul_rm_ftz_f32.ll index abe2719caf..c6237f7244 100644 --- a/intrinsics/probes/mul_rm_ftz_f32.ll +++ b/intrinsics/probes/mul_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_f32.ll b/intrinsics/probes/mul_rn_f32.ll index c7215a1151..76e4539bbf 100644 --- a/intrinsics/probes/mul_rn_f32.ll +++ b/intrinsics/probes/mul_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_f64.ll b/intrinsics/probes/mul_rn_f64.ll index 299e91de54..e2e34ed800 100644 --- a/intrinsics/probes/mul_rn_f64.ll +++ b/intrinsics/probes/mul_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_ftz_f32.ll b/intrinsics/probes/mul_rn_ftz_f32.ll index cbb6c094cd..b4336ef028 100644 --- a/intrinsics/probes/mul_rn_ftz_f32.ll +++ b/intrinsics/probes/mul_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_f32.ll b/intrinsics/probes/mul_rp_f32.ll index 25f3e30cb8..1b5e87dd3d 100644 --- a/intrinsics/probes/mul_rp_f32.ll +++ b/intrinsics/probes/mul_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_f64.ll b/intrinsics/probes/mul_rp_f64.ll index 78e9ca222a..0bb8da0325 100644 --- a/intrinsics/probes/mul_rp_f64.ll +++ b/intrinsics/probes/mul_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_ftz_f32.ll b/intrinsics/probes/mul_rp_ftz_f32.ll index ab5b7b0407..ee0414ede7 100644 --- a/intrinsics/probes/mul_rp_ftz_f32.ll +++ b/intrinsics/probes/mul_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_f32.ll b/intrinsics/probes/mul_rz_f32.ll index f5dc7928ea..f0a8d1301a 100644 --- a/intrinsics/probes/mul_rz_f32.ll +++ b/intrinsics/probes/mul_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_f64.ll b/intrinsics/probes/mul_rz_f64.ll index 35d4d186f2..9c86333dd1 100644 --- a/intrinsics/probes/mul_rz_f64.ll +++ b/intrinsics/probes/mul_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_ftz_f32.ll b/intrinsics/probes/mul_rz_ftz_f32.ll index 92ef5ea91c..8053bd94b0 100644 --- a/intrinsics/probes/mul_rz_ftz_f32.ll +++ b/intrinsics/probes/mul_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nanosleep.ll b/intrinsics/probes/nanosleep.ll index 58bf047598..a3d5b59ba9 100644 --- a/intrinsics/probes/nanosleep.ll +++ b/intrinsics/probes/nanosleep.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/neg_bf16x2.ll b/intrinsics/probes/neg_bf16x2.ll index 0371541e57..ec4511cb7e 100644 --- a/intrinsics/probes/neg_bf16x2.ll +++ b/intrinsics/probes/neg_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/neg_f16x2.ll b/intrinsics/probes/neg_f16x2.ll index fd30e5a4bf..0a45000af4 100644 --- a/intrinsics/probes/neg_f16x2.ll +++ b/intrinsics/probes/neg_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nsmid.lib_nvvm.ll b/intrinsics/probes/nsmid.lib_nvvm.ll index 9bd4674d53..f639e451b3 100644 --- a/intrinsics/probes/nsmid.lib_nvvm.ll +++ b/intrinsics/probes/nsmid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nsmid.llvm_nvptx.ll b/intrinsics/probes/nsmid.llvm_nvptx.ll index 4e9b16eaa1..7bc95619cb 100644 --- a/intrinsics/probes/nsmid.llvm_nvptx.ll +++ b/intrinsics/probes/nsmid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nwarpid.lib_nvvm.ll b/intrinsics/probes/nwarpid.lib_nvvm.ll index 40fd320553..13f5142bcb 100644 --- a/intrinsics/probes/nwarpid.lib_nvvm.ll +++ b/intrinsics/probes/nwarpid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nwarpid.llvm_nvptx.ll b/intrinsics/probes/nwarpid.llvm_nvptx.ll index 05cb134029..57a05b0f95 100644 --- a/intrinsics/probes/nwarpid.llvm_nvptx.ll +++ b/intrinsics/probes/nwarpid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/packed_atomic_add_bf16x2.ll b/intrinsics/probes/packed_atomic_add_bf16x2.ll index 85b23be099..d71ac6b87d 100644 --- a/intrinsics/probes/packed_atomic_add_bf16x2.ll +++ b/intrinsics/probes/packed_atomic_add_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/packed_atomic_add_f16x2.ll b/intrinsics/probes/packed_atomic_add_f16x2.ll index f2c423cc2b..846b69aedf 100644 --- a/intrinsics/probes/packed_atomic_add_f16x2.ll +++ b/intrinsics/probes/packed_atomic_add_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/pmevent.ll b/intrinsics/probes/pmevent.ll index c3dec83a50..25f56b6a06 100644 --- a/intrinsics/probes/pmevent.ll +++ b/intrinsics/probes/pmevent.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prefetch_tma_descriptor.ll b/intrinsics/probes/prefetch_tma_descriptor.ll index 180a30f939..331098c30e 100644 --- a/intrinsics/probes/prefetch_tma_descriptor.ll +++ b/intrinsics/probes/prefetch_tma_descriptor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt.ll b/intrinsics/probes/prmt.ll index c0808f2b3b..f3c1e71c84 100644 --- a/intrinsics/probes/prmt.ll +++ b/intrinsics/probes/prmt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_b4e.ll b/intrinsics/probes/prmt_b4e.ll index a940bbc120..2386e3c5ec 100644 --- a/intrinsics/probes/prmt_b4e.ll +++ b/intrinsics/probes/prmt_b4e.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_ecl.ll b/intrinsics/probes/prmt_ecl.ll index 12b45c9b17..6667c9aad8 100644 --- a/intrinsics/probes/prmt_ecl.ll +++ b/intrinsics/probes/prmt_ecl.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_ecr.ll b/intrinsics/probes/prmt_ecr.ll index 9b77e8e1b8..bd774c930c 100644 --- a/intrinsics/probes/prmt_ecr.ll +++ b/intrinsics/probes/prmt_ecr.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_f4e.ll b/intrinsics/probes/prmt_f4e.ll index 59b3cac57e..ea7447f0e1 100644 --- a/intrinsics/probes/prmt_f4e.ll +++ b/intrinsics/probes/prmt_f4e.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_rc16.ll b/intrinsics/probes/prmt_rc16.ll index 3723564a2b..4ef38b1945 100644 --- a/intrinsics/probes/prmt_rc16.ll +++ b/intrinsics/probes/prmt_rc16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_rc8.ll b/intrinsics/probes/prmt_rc8.ll index 5fade2061d..e54a09db9f 100644 --- a/intrinsics/probes/prmt_rc8.ll +++ b/intrinsics/probes/prmt_rc8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_approx_ftz_f32.ll b/intrinsics/probes/rcp_approx_ftz_f32.ll index f6d516f73c..4099ae9b65 100644 --- a/intrinsics/probes/rcp_approx_ftz_f32.ll +++ b/intrinsics/probes/rcp_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_approx_ftz_f64.ll b/intrinsics/probes/rcp_approx_ftz_f64.ll index 03d79264d7..1346c27bd2 100644 --- a/intrinsics/probes/rcp_approx_ftz_f64.ll +++ b/intrinsics/probes/rcp_approx_ftz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_f32.ll b/intrinsics/probes/rcp_rm_f32.ll index 718bb5dd5a..b61d271cc3 100644 --- a/intrinsics/probes/rcp_rm_f32.ll +++ b/intrinsics/probes/rcp_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_f64.ll b/intrinsics/probes/rcp_rm_f64.ll index 5d285d4ec1..f0b8ca0e85 100644 --- a/intrinsics/probes/rcp_rm_f64.ll +++ b/intrinsics/probes/rcp_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_ftz_f32.ll b/intrinsics/probes/rcp_rm_ftz_f32.ll index 88fe2c8df1..8a26786075 100644 --- a/intrinsics/probes/rcp_rm_ftz_f32.ll +++ b/intrinsics/probes/rcp_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_f32.ll b/intrinsics/probes/rcp_rn_f32.ll index 187e5d1f23..835737f670 100644 --- a/intrinsics/probes/rcp_rn_f32.ll +++ b/intrinsics/probes/rcp_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_f64.ll b/intrinsics/probes/rcp_rn_f64.ll index 8729c88a8d..ee215a18d8 100644 --- a/intrinsics/probes/rcp_rn_f64.ll +++ b/intrinsics/probes/rcp_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_ftz_f32.ll b/intrinsics/probes/rcp_rn_ftz_f32.ll index 048b25a0e6..9dfa3d22fc 100644 --- a/intrinsics/probes/rcp_rn_ftz_f32.ll +++ b/intrinsics/probes/rcp_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_f32.ll b/intrinsics/probes/rcp_rp_f32.ll index 5ea2b33844..6c77397415 100644 --- a/intrinsics/probes/rcp_rp_f32.ll +++ b/intrinsics/probes/rcp_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_f64.ll b/intrinsics/probes/rcp_rp_f64.ll index 8a904ff69f..f36560ff79 100644 --- a/intrinsics/probes/rcp_rp_f64.ll +++ b/intrinsics/probes/rcp_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_ftz_f32.ll b/intrinsics/probes/rcp_rp_ftz_f32.ll index 76d538f10a..fb13b59de2 100644 --- a/intrinsics/probes/rcp_rp_ftz_f32.ll +++ b/intrinsics/probes/rcp_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_f32.ll b/intrinsics/probes/rcp_rz_f32.ll index 0ba6b79253..19cb3a08c2 100644 --- a/intrinsics/probes/rcp_rz_f32.ll +++ b/intrinsics/probes/rcp_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_f64.ll b/intrinsics/probes/rcp_rz_f64.ll index c8347d4eaa..2b6b92f8b0 100644 --- a/intrinsics/probes/rcp_rz_f64.ll +++ b/intrinsics/probes/rcp_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_ftz_f32.ll b/intrinsics/probes/rcp_rz_ftz_f32.ll index 1986fbb266..5f1041514d 100644 --- a/intrinsics/probes/rcp_rz_ftz_f32.ll +++ b/intrinsics/probes/rcp_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_add.ll b/intrinsics/probes/redux_sync_add.ll index 4e0704b440..cf967dbf88 100644 --- a/intrinsics/probes/redux_sync_add.ll +++ b/intrinsics/probes/redux_sync_add.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_and.ll b/intrinsics/probes/redux_sync_and.ll index 86457c7067..b141e11fc9 100644 --- a/intrinsics/probes/redux_sync_and.ll +++ b/intrinsics/probes/redux_sync_and.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_abs_f32.ll b/intrinsics/probes/redux_sync_max_abs_f32.ll index 6a1a36f3dd..c3421ef6f5 100644 --- a/intrinsics/probes/redux_sync_max_abs_f32.ll +++ b/intrinsics/probes/redux_sync_max_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_abs_nan_f32.ll b/intrinsics/probes/redux_sync_max_abs_nan_f32.ll index 84a27626f7..1cc6f80ebb 100644 --- a/intrinsics/probes/redux_sync_max_abs_nan_f32.ll +++ b/intrinsics/probes/redux_sync_max_abs_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_f32.ll b/intrinsics/probes/redux_sync_max_f32.ll index d38044a441..7befc9fb01 100644 --- a/intrinsics/probes/redux_sync_max_f32.ll +++ b/intrinsics/probes/redux_sync_max_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_i32.ll b/intrinsics/probes/redux_sync_max_i32.ll index 12c8729502..2feb4a537b 100644 --- a/intrinsics/probes/redux_sync_max_i32.ll +++ b/intrinsics/probes/redux_sync_max_i32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_nan_f32.ll b/intrinsics/probes/redux_sync_max_nan_f32.ll index 38c67bcfb5..e1e614afb7 100644 --- a/intrinsics/probes/redux_sync_max_nan_f32.ll +++ b/intrinsics/probes/redux_sync_max_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_u32.ll b/intrinsics/probes/redux_sync_max_u32.ll index 518e53d4b9..2dab9293a6 100644 --- a/intrinsics/probes/redux_sync_max_u32.ll +++ b/intrinsics/probes/redux_sync_max_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_abs_f32.ll b/intrinsics/probes/redux_sync_min_abs_f32.ll index 4cc74871ba..a91dcff20f 100644 --- a/intrinsics/probes/redux_sync_min_abs_f32.ll +++ b/intrinsics/probes/redux_sync_min_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_abs_nan_f32.ll b/intrinsics/probes/redux_sync_min_abs_nan_f32.ll index 1e6bc63537..949b25d6d9 100644 --- a/intrinsics/probes/redux_sync_min_abs_nan_f32.ll +++ b/intrinsics/probes/redux_sync_min_abs_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_f32.ll b/intrinsics/probes/redux_sync_min_f32.ll index 8dbea8a7a8..315190906c 100644 --- a/intrinsics/probes/redux_sync_min_f32.ll +++ b/intrinsics/probes/redux_sync_min_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_i32.ll b/intrinsics/probes/redux_sync_min_i32.ll index dd1636caba..32f1ef379e 100644 --- a/intrinsics/probes/redux_sync_min_i32.ll +++ b/intrinsics/probes/redux_sync_min_i32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_nan_f32.ll b/intrinsics/probes/redux_sync_min_nan_f32.ll index 79575d21bc..54c3b5e516 100644 --- a/intrinsics/probes/redux_sync_min_nan_f32.ll +++ b/intrinsics/probes/redux_sync_min_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_u32.ll b/intrinsics/probes/redux_sync_min_u32.ll index 607dee5aef..3230b92e0d 100644 --- a/intrinsics/probes/redux_sync_min_u32.ll +++ b/intrinsics/probes/redux_sync_min_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_or.ll b/intrinsics/probes/redux_sync_or.ll index 0810fa7800..932e87c0b7 100644 --- a/intrinsics/probes/redux_sync_or.ll +++ b/intrinsics/probes/redux_sync_or.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_xor.ll b/intrinsics/probes/redux_sync_xor.ll index 8ee258414e..77fefefd65 100644 --- a/intrinsics/probes/redux_sync_xor.ll +++ b/intrinsics/probes/redux_sync_xor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_f32.ll b/intrinsics/probes/rsqrt_approx_f32.ll index e22a8a31fb..74e7b8a18a 100644 --- a/intrinsics/probes/rsqrt_approx_f32.ll +++ b/intrinsics/probes/rsqrt_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_f64.ll b/intrinsics/probes/rsqrt_approx_f64.ll index 1b9bf93289..4c771d7bc9 100644 --- a/intrinsics/probes/rsqrt_approx_f64.ll +++ b/intrinsics/probes/rsqrt_approx_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_ftz_f32.ll b/intrinsics/probes/rsqrt_approx_ftz_f32.ll index 4172cc059e..d5aa5af696 100644 --- a/intrinsics/probes/rsqrt_approx_ftz_f32.ll +++ b/intrinsics/probes/rsqrt_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/setmaxnreg_dec.ll b/intrinsics/probes/setmaxnreg_dec.ll index 26695e0023..e29c8d1e44 100644 --- a/intrinsics/probes/setmaxnreg_dec.ll +++ b/intrinsics/probes/setmaxnreg_dec.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/setmaxnreg_inc.ll b/intrinsics/probes/setmaxnreg_inc.ll index c8a7ce8e36..efadae504f 100644 --- a/intrinsics/probes/setmaxnreg_inc.ll +++ b/intrinsics/probes/setmaxnreg_inc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_f32_sync.ll b/intrinsics/probes/shuffle_down_f32_sync.ll index f4963ff3ca..2b86455edd 100644 --- a/intrinsics/probes/shuffle_down_f32_sync.ll +++ b/intrinsics/probes/shuffle_down_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_sync.ll b/intrinsics/probes/shuffle_down_sync.ll index 82b17eb8e6..63d4b757d3 100644 --- a/intrinsics/probes/shuffle_down_sync.ll +++ b/intrinsics/probes/shuffle_down_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_u64_sync.ll b/intrinsics/probes/shuffle_down_u64_sync.ll index 6cc42d5354..6c02998eaa 100644 --- a/intrinsics/probes/shuffle_down_u64_sync.ll +++ b/intrinsics/probes/shuffle_down_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_f32_sync.ll b/intrinsics/probes/shuffle_f32_sync.ll index 42682cf11a..fdec2b670f 100644 --- a/intrinsics/probes/shuffle_f32_sync.ll +++ b/intrinsics/probes/shuffle_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_sync.ll b/intrinsics/probes/shuffle_sync.ll index 927a87a316..5882835f86 100644 --- a/intrinsics/probes/shuffle_sync.ll +++ b/intrinsics/probes/shuffle_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_u64_sync.ll b/intrinsics/probes/shuffle_u64_sync.ll index d3dcd2abbe..3a0d813c97 100644 --- a/intrinsics/probes/shuffle_u64_sync.ll +++ b/intrinsics/probes/shuffle_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_f32_sync.ll b/intrinsics/probes/shuffle_up_f32_sync.ll index 319c2d11fb..a28a3f4974 100644 --- a/intrinsics/probes/shuffle_up_f32_sync.ll +++ b/intrinsics/probes/shuffle_up_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_sync.ll b/intrinsics/probes/shuffle_up_sync.ll index 800c3b14e1..bd0b49520e 100644 --- a/intrinsics/probes/shuffle_up_sync.ll +++ b/intrinsics/probes/shuffle_up_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_u64_sync.ll b/intrinsics/probes/shuffle_up_u64_sync.ll index fb3baefcb9..e83132564a 100644 --- a/intrinsics/probes/shuffle_up_u64_sync.ll +++ b/intrinsics/probes/shuffle_up_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_f32_sync.ll b/intrinsics/probes/shuffle_xor_f32_sync.ll index 2f5d56f6d7..a12874eb3a 100644 --- a/intrinsics/probes/shuffle_xor_f32_sync.ll +++ b/intrinsics/probes/shuffle_xor_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_sync.ll b/intrinsics/probes/shuffle_xor_sync.ll index 861149d42e..f89a285cd4 100644 --- a/intrinsics/probes/shuffle_xor_sync.ll +++ b/intrinsics/probes/shuffle_xor_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_u64_sync.ll b/intrinsics/probes/shuffle_xor_u64_sync.ll index e3f80f11e3..d128021695 100644 --- a/intrinsics/probes/shuffle_xor_u64_sync.ll +++ b/intrinsics/probes/shuffle_xor_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sin_approx_f32.ll b/intrinsics/probes/sin_approx_f32.ll index 60a0d6ddfb..7fe5f38c4b 100644 --- a/intrinsics/probes/sin_approx_f32.ll +++ b/intrinsics/probes/sin_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sin_approx_ftz_f32.ll b/intrinsics/probes/sin_approx_ftz_f32.ll index 6871d59f30..8ac9967e43 100644 --- a/intrinsics/probes/sin_approx_ftz_f32.ll +++ b/intrinsics/probes/sin_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/smid.lib_nvvm.ll b/intrinsics/probes/smid.lib_nvvm.ll index 951e4624a5..cf3c526d6f 100644 --- a/intrinsics/probes/smid.lib_nvvm.ll +++ b/intrinsics/probes/smid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/smid.llvm_nvptx.ll b/intrinsics/probes/smid.llvm_nvptx.ll index 09af421460..1a82b657d9 100644 --- a/intrinsics/probes/smid.llvm_nvptx.ll +++ b/intrinsics/probes/smid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_approx_f32.ll b/intrinsics/probes/sqrt_approx_f32.ll index f70a7cd2a4..b0a4efee79 100644 --- a/intrinsics/probes/sqrt_approx_f32.ll +++ b/intrinsics/probes/sqrt_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_approx_ftz_f32.ll b/intrinsics/probes/sqrt_approx_ftz_f32.ll index 844c3f03ac..18a781e166 100644 --- a/intrinsics/probes/sqrt_approx_ftz_f32.ll +++ b/intrinsics/probes/sqrt_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_f32.ll b/intrinsics/probes/sqrt_rm_f32.ll index 241f8e8aaf..03061d9e76 100644 --- a/intrinsics/probes/sqrt_rm_f32.ll +++ b/intrinsics/probes/sqrt_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_f64.ll b/intrinsics/probes/sqrt_rm_f64.ll index 413063f878..6b7c59b7a3 100644 --- a/intrinsics/probes/sqrt_rm_f64.ll +++ b/intrinsics/probes/sqrt_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_ftz_f32.ll b/intrinsics/probes/sqrt_rm_ftz_f32.ll index a2af78ad00..11d72ca3c0 100644 --- a/intrinsics/probes/sqrt_rm_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_f32.ll b/intrinsics/probes/sqrt_rn_f32.ll index b431f31efe..5a336c65fc 100644 --- a/intrinsics/probes/sqrt_rn_f32.ll +++ b/intrinsics/probes/sqrt_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_f64.ll b/intrinsics/probes/sqrt_rn_f64.ll index c03107fb66..66a85c1c99 100644 --- a/intrinsics/probes/sqrt_rn_f64.ll +++ b/intrinsics/probes/sqrt_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_ftz_f32.ll b/intrinsics/probes/sqrt_rn_ftz_f32.ll index 212a3f064a..e8f1a532c4 100644 --- a/intrinsics/probes/sqrt_rn_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_f32.ll b/intrinsics/probes/sqrt_rp_f32.ll index 24538afae1..fe47142efd 100644 --- a/intrinsics/probes/sqrt_rp_f32.ll +++ b/intrinsics/probes/sqrt_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_f64.ll b/intrinsics/probes/sqrt_rp_f64.ll index 23ba0fd921..2423822cc7 100644 --- a/intrinsics/probes/sqrt_rp_f64.ll +++ b/intrinsics/probes/sqrt_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_ftz_f32.ll b/intrinsics/probes/sqrt_rp_ftz_f32.ll index f3bde884ec..8e26ebba6e 100644 --- a/intrinsics/probes/sqrt_rp_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_f32.ll b/intrinsics/probes/sqrt_rz_f32.ll index 39cbb582fe..a704e99485 100644 --- a/intrinsics/probes/sqrt_rz_f32.ll +++ b/intrinsics/probes/sqrt_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_f64.ll b/intrinsics/probes/sqrt_rz_f64.ll index a257befb15..93076f435a 100644 --- a/intrinsics/probes/sqrt_rz_f64.ll +++ b/intrinsics/probes/sqrt_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_ftz_f32.ll b/intrinsics/probes/sqrt_rz_ftz_f32.ll index 8732e11e73..6d04c2bd0c 100644 --- a/intrinsics/probes/sqrt_rz_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x2_b16.ll b/intrinsics/probes/stmatrix_m8n8_x2_b16.ll index 0c75e264fc..972b5f45ef 100644 --- a/intrinsics/probes/stmatrix_m8n8_x2_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x2_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll b/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll index c75f5c3fa7..eb20421427 100644 --- a/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x4_b16.ll b/intrinsics/probes/stmatrix_m8n8_x4_b16.ll index e834f54d6b..0678423ee0 100644 --- a/intrinsics/probes/stmatrix_m8n8_x4_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x4_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll b/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll index 0eaf9bb3c3..dab23947d8 100644 --- a/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_bf16x2.ll b/intrinsics/probes/sub_bf16x2.ll index d7bf56de17..9d07e9c9a5 100644 --- a/intrinsics/probes/sub_bf16x2.ll +++ b/intrinsics/probes/sub_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_f16x2.ll b/intrinsics/probes/sub_f16x2.ll index 9bed3028bf..5e9c81face 100644 --- a/intrinsics/probes/sub_f16x2.ll +++ b/intrinsics/probes/sub_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_f32x2.ll b/intrinsics/probes/sub_f32x2.ll index cba5949968..b5e340933a 100644 --- a/intrinsics/probes/sub_f32x2.ll +++ b/intrinsics/probes/sub_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_ftz_f32x2.ll b/intrinsics/probes/sub_ftz_f32x2.ll index 489c1952c9..fa145f6a21 100644 --- a/intrinsics/probes/sub_ftz_f32x2.ll +++ b/intrinsics/probes/sub_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sync_mask.ll b/intrinsics/probes/sync_mask.ll index d4b22549c7..6cabd40b8e 100644 --- a/intrinsics/probes/sync_mask.ll +++ b/intrinsics/probes/sync_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sync_threads.ll b/intrinsics/probes/sync_threads.ll index 3760eac08d..79844311b8 100644 --- a/intrinsics/probes/sync_threads.ll +++ b/intrinsics/probes/sync_threads.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tanh_approx_f32.ll b/intrinsics/probes/tanh_approx_f32.ll index 23f04cacc4..e5029383a5 100644 --- a/intrinsics/probes/tanh_approx_f32.ll +++ b/intrinsics/probes/tanh_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_alloc.ll b/intrinsics/probes/tcgen05_alloc.ll index b25351c6d5..9c1b5b7aaf 100644 --- a/intrinsics/probes/tcgen05_alloc.ll +++ b/intrinsics/probes/tcgen05_alloc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_alloc_cg2.ll b/intrinsics/probes/tcgen05_alloc_cg2.ll index 53694377a9..c8bcbd737d 100644 --- a/intrinsics/probes/tcgen05_alloc_cg2.ll +++ b/intrinsics/probes/tcgen05_alloc_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit.ll b/intrinsics/probes/tcgen05_commit.ll index bccdd1b046..24d68f7776 100644 --- a/intrinsics/probes/tcgen05_commit.ll +++ b/intrinsics/probes/tcgen05_commit.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_cg2.ll b/intrinsics/probes/tcgen05_commit_cg2.ll index 9d84744578..020d78f205 100644 --- a/intrinsics/probes/tcgen05_commit_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_multicast.ll b/intrinsics/probes/tcgen05_commit_multicast.ll index fa54ebfe86..f0b4007af1 100644 --- a/intrinsics/probes/tcgen05_commit_multicast.ll +++ b/intrinsics/probes/tcgen05_commit_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_multicast_cg2.ll b/intrinsics/probes/tcgen05_commit_multicast_cg2.ll index ddf212137c..e0607c97f0 100644 --- a/intrinsics/probes/tcgen05_commit_multicast_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_multicast_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_shared_cluster.ll b/intrinsics/probes/tcgen05_commit_shared_cluster.ll index a9015ece25..9676f4368a 100644 --- a/intrinsics/probes/tcgen05_commit_shared_cluster.ll +++ b/intrinsics/probes/tcgen05_commit_shared_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll b/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll index 5fe6f0a0d6..f1f30d7bf7 100644 --- a/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b.ll b/intrinsics/probes/tcgen05_cp_128x128b.ll index 684f847ab9..08434f6a5f 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll index f076c4a788..4fa70b6cda 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll index baa0eaa221..1a21c90283 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll index d92561e885..cbb6881d30 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll index 0807855f9e..3b761ef841 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll index cd1578ba54..f1fdcd550f 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll index cbb2edd947..7f68e8905b 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll index 53a180a2f9..ab9e8cca7c 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll index 1e2873149d..28385ecb38 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll index 99f14e26f1..a50a86d88d 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll index cfb41b89de..30f0e11f8d 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll index cb777dd00d..425fb63a25 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll index 40f93b1544..8872312a96 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll index 28fbe75c65..9711df5b39 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll index 4f637d0ba6..352ff7d732 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll index b369269f27..c1d83a2b78 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b.ll b/intrinsics/probes/tcgen05_cp_4x256b.ll index 0e420c56bb..e60130e5e2 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll index bea31a013a..1d9f8e3e58 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll index a7c04ee28c..1d68ccfeb8 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll index 71830db275..f7f6fd2ae9 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll index 7cd788e50c..b67a396e12 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll index b0d6b0b343..8428a09b00 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll index 3b8d06917f..89329facd7 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll index 04ba0560f5..3cf2fcbbcc 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll index d29f632056..847e4f8467 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll index b858b3d73b..fe68c9a3c0 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll index 5d3e6dfcb0..9bc527f007 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll index 00dc573ebe..673c1db44b 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll index 09de27398e..8744e23020 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll index 2999d3a578..3ec66fb1b9 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll index 9576cc7137..b32d0658ef 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll index 8bfaf0f1b1..d23f138ac3 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll index f91c7abeea..c0eaa30748 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll index 049379aada..256de748f4 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll b/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll index 501cbe2376..d4e50658a9 100644 --- a/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll +++ b/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll b/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll index e70671d475..09b0e29d07 100644 --- a/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_dealloc.ll b/intrinsics/probes/tcgen05_dealloc.ll index bdf59f497f..4af2175a49 100644 --- a/intrinsics/probes/tcgen05_dealloc.ll +++ b/intrinsics/probes/tcgen05_dealloc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_dealloc_cg2.ll b/intrinsics/probes/tcgen05_dealloc_cg2.ll index a29eaa34a7..36022bfb9c 100644 --- a/intrinsics/probes/tcgen05_dealloc_cg2.ll +++ b/intrinsics/probes/tcgen05_dealloc_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_fence_after_thread_sync.ll b/intrinsics/probes/tcgen05_fence_after_thread_sync.ll index eb6b65e862..08bdcbcf86 100644 --- a/intrinsics/probes/tcgen05_fence_after_thread_sync.ll +++ b/intrinsics/probes/tcgen05_fence_after_thread_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_fence_before_thread_sync.ll b/intrinsics/probes/tcgen05_fence_before_thread_sync.ll index c38cb00490..f9f35f9236 100644 --- a/intrinsics/probes/tcgen05_fence_before_thread_sync.ll +++ b/intrinsics/probes/tcgen05_fence_before_thread_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll index 49a1849bbb..70f1d365d7 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll index 8a27dccc63..6b823158c3 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll index 5fabb1e916..f6dad12606 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll index bd595692cf..42153d3d00 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll index d6ce8ec218..95651757fc 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll index 3c76ec80d2..a09e554702 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll index 646a77e9de..ca44aae2de 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll index 2528486fdd..86aeea6935 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll index c48e626118..ee3477f2da 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll index b51743c33b..301fb8ac09 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll index d3f8b76e0b..849cdc7968 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll index 3c1f5bc0a7..51d846a7b8 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll index f300e6be3a..6b8f2337fd 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll index f6daed2a07..c7d2bbaad2 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_pure.ll b/intrinsics/probes/tcgen05_ld_16x256b_pure.ll index fb413c9c1a..d89da94076 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_pure.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_pure.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll index d3c2b95178..52c83b2403 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll index 783c171cab..114bd3128d 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll index 96700f5d21..c7ad46852f 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll index 6057656613..7ded84027d 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll index bb2312a801..978ecb03a0 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll index 91d08665f8..5bb04664aa 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll index cb72b64b65..2975f519bc 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll index 3007bc2f4a..4d5efdb82d 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll index d1f4cd7970..df5ad07566 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll index 8b45e8b835..f3a7e41d24 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll index ec9bc98298..5cfaf0ae68 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll index 7136a783a5..a9f6e2d236 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll index 5eed13528b..7af60f1b46 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll index db7a4c685b..b12ee2ca72 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll index b6960e4253..e2811fbae8 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll index 10d1438a85..85dfd1dfa3 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll index 3be26f3137..f2e74b44c9 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll index 0547d950f7..ffb0c00c56 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll index 0666bfe13b..a1cffc48d5 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll index 25ec3f4268..2cb81fa6d3 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll index b36c54ede3..74de54a4ff 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll index 07958d6c1f..4a6bcf0662 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll index f50419dbf8..fa013c79c8 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll index 0944764a89..71070d73de 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll index fda73be654..727bc3db71 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll index 25808070d0..e22a7b36a0 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll index 1d3c76e6b8..68974b74ca 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll index 325d99c566..78f83dc38d 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll index 1dc33edc32..11e09dd621 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll index 854fc61cf2..2969ef21a1 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll index 95448b2ff8..a789fb9676 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll index 6066ccf4eb..84f72bce88 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll index 9d2d4d7eb7..b4ed4e6e73 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll index 1ec0d1ed5a..50bf144542 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll index 8a6058b291..cf8827facf 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll index 061946e407..3c7ed56dec 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll index 92626a7557..09b9580b2d 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll index 2ae168a4e5..d8ea7b21bf 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll index 4d2fc2cd53..d55852fc4e 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll index 12fcc00600..3ff9ebcdd2 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll index 2218782930..67ba5bfabb 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll index a0ee36924b..3d85cc714e 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll index 0f0ba0218b..e6cb760729 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll index 9b93fb33f1..9195f9ed36 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll index 6cd6058c61..e4c495bb66 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll index ae72dbc4be..d4f10f671a 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll index bbb92b200a..ca67045d56 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll index 9541c4c14e..7a35f01aae 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll index 9430f93518..0bc825115d 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll index 40f7f4a333..2a4f4019a6 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll index 4c14670979..9748d3ea28 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll index f3353b5146..6d9badd039 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll index ea0df1505e..221cb970ab 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll index bfe8937bc6..095cf6377e 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll index 12ea1d89bd..a244db01cb 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll index 5832bff666..8bb7cf16d9 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll index cfd6cc0d9a..b9e2e9e243 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll index 65fba3b12d..a6c1b96255 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll index cf69a3844f..4d9d73d5f7 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll index abaccdb81c..fb8a683ed5 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll index 70a20b16ab..241ed8ce55 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_load_wait.ll b/intrinsics/probes/tcgen05_load_wait.ll index 18020f4249..4e618c5fcd 100644 --- a/intrinsics/probes/tcgen05_load_wait.ll +++ b/intrinsics/probes/tcgen05_load_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e2m1.ll b/intrinsics/probes/tcgen05_mma_e2m1.ll index ed5fa22f7a..b054be7461 100644 --- a/intrinsics/probes/tcgen05_mma_e2m1.ll +++ b/intrinsics/probes/tcgen05_mma_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e2m3.ll b/intrinsics/probes/tcgen05_mma_e2m3.ll index 1a74b52db3..786d9db42e 100644 --- a/intrinsics/probes/tcgen05_mma_e2m3.ll +++ b/intrinsics/probes/tcgen05_mma_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e3m2.ll b/intrinsics/probes/tcgen05_mma_e3m2.ll index 321cd0c82c..e8761e65a1 100644 --- a/intrinsics/probes/tcgen05_mma_e3m2.ll +++ b/intrinsics/probes/tcgen05_mma_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e4m3.ll b/intrinsics/probes/tcgen05_mma_e4m3.ll index 25447e7326..3e1e10d498 100644 --- a/intrinsics/probes/tcgen05_mma_e4m3.ll +++ b/intrinsics/probes/tcgen05_mma_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e5m2.ll b/intrinsics/probes/tcgen05_mma_e5m2.ll index e51207ae66..47c67c339e 100644 --- a/intrinsics/probes/tcgen05_mma_e5m2.ll +++ b/intrinsics/probes/tcgen05_mma_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_f16.ll b/intrinsics/probes/tcgen05_mma_f16.ll index d032cb21dd..a106e9516e 100644 --- a/intrinsics/probes/tcgen05_mma_f16.ll +++ b/intrinsics/probes/tcgen05_mma_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_f16_cg2.ll b/intrinsics/probes/tcgen05_mma_f16_cg2.ll index d312dd9fe0..f302a326d6 100644 --- a/intrinsics/probes/tcgen05_mma_f16_cg2.ll +++ b/intrinsics/probes/tcgen05_mma_f16_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_shared.ll b/intrinsics/probes/tcgen05_mma_shared.ll index 1a87fd6b7d..b911fad2cb 100644 --- a/intrinsics/probes/tcgen05_mma_shared.ll +++ b/intrinsics/probes/tcgen05_mma_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_shared.ll b/intrinsics/probes/tcgen05_mma_sp_shared.ll index cd20c8dc1f..5cb565238d 100644 --- a/intrinsics/probes/tcgen05_mma_sp_shared.ll +++ b/intrinsics/probes/tcgen05_mma_sp_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_tensor.ll b/intrinsics/probes/tcgen05_mma_sp_tensor.ll index 70ab7aa3cd..429f35c439 100644 --- a/intrinsics/probes/tcgen05_mma_sp_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_sp_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll b/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll index 26d94e9c97..fe4152d30f 100644 --- a/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll +++ b/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_tensor.ll b/intrinsics/probes/tcgen05_mma_tensor.ll index 63abf5092b..15e63b4ea1 100644 --- a/intrinsics/probes/tcgen05_mma_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_tensor_ashift.ll b/intrinsics/probes/tcgen05_mma_tensor_ashift.ll index bf290a9297..e883c4b7fd 100644 --- a/intrinsics/probes/tcgen05_mma_tensor_ashift.ll +++ b/intrinsics/probes/tcgen05_mma_tensor_ashift.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_bf16.ll b/intrinsics/probes/tcgen05_mma_ws_bf16.ll index dd3e1c552e..954e634613 100644 --- a/intrinsics/probes/tcgen05_mma_ws_bf16.ll +++ b/intrinsics/probes/tcgen05_mma_ws_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e2m1.ll b/intrinsics/probes/tcgen05_mma_ws_e2m1.ll index 5362fc019f..bc028223ab 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e2m1.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e2m3.ll b/intrinsics/probes/tcgen05_mma_ws_e2m3.ll index 12adfb2e23..7d3ecc715f 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e2m3.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e3m2.ll b/intrinsics/probes/tcgen05_mma_ws_e3m2.ll index 37f28c454d..1046af45cf 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e3m2.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e4m3.ll b/intrinsics/probes/tcgen05_mma_ws_e4m3.ll index e30c99b6de..06251e9f54 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e4m3.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e5m2.ll b/intrinsics/probes/tcgen05_mma_ws_e5m2.ll index 1da1402cb9..c59fb86b2e 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e5m2.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_f16.ll b/intrinsics/probes/tcgen05_mma_ws_f16.ll index d248a566eb..50f66385b3 100644 --- a/intrinsics/probes/tcgen05_mma_ws_f16.ll +++ b/intrinsics/probes/tcgen05_mma_ws_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_shared.ll b/intrinsics/probes/tcgen05_mma_ws_shared.ll index 8244a42879..9f2a30ac95 100644 --- a/intrinsics/probes/tcgen05_mma_ws_shared.ll +++ b/intrinsics/probes/tcgen05_mma_ws_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll index 90ddf7440b..e11e780bb9 100644 --- a/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll b/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll index 762879f141..3ae1fcdcd5 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll index eea8a62ce7..9d7fb40282 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll b/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll index 67275a5c16..6393a5d105 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll index eb7d01ce6e..7510bd274f 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tensor.ll b/intrinsics/probes/tcgen05_mma_ws_tensor.ll index 0e06eb9814..0a333da335 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll index 529fedacf9..656266ffb8 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tf32.ll b/intrinsics/probes/tcgen05_mma_ws_tf32.ll index 3c09a39f9c..c919cd8868 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tf32.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll b/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll index 43eaf33685..64ef8c2fc7 100644 --- a/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll +++ b/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll b/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll index 6009623a2a..b71a8b7c72 100644 --- a/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll +++ b/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_shift_down.ll b/intrinsics/probes/tcgen05_shift_down.ll index e41156b016..15b7f00203 100644 --- a/intrinsics/probes/tcgen05_shift_down.ll +++ b/intrinsics/probes/tcgen05_shift_down.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_shift_down_cg2.ll b/intrinsics/probes/tcgen05_shift_down_cg2.ll index 6b5d08d581..3329d3eba4 100644 --- a/intrinsics/probes/tcgen05_shift_down_cg2.ll +++ b/intrinsics/probes/tcgen05_shift_down_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll index 920c392202..ee1bdce790 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll index 790ca9e4d6..20d00d1e4e 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll index 22b6ec0b1a..8ea569aba3 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll index 09ed558cb2..eb618352b9 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll index 92069ccdf8..fb4a039ae4 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll index 6d03e10ce3..958cfbb8c5 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll index 83362fa4eb..eb9f0c0f1f 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll index 2dec484fd4..eafd272780 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll index 4cd2ef2697..c2e1b8df90 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll index 3b4095d458..e54526d0cb 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll index 9f16e7053c..6c2df33931 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll index 010a4546ca..ca4788c6a8 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll index 06a8b4a532..e4e8fbc6c1 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll index 0a38dd112a..938182639d 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll index 96edf5af61..901e716625 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll index 227fca6429..e28545bc91 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll index c3c86b73a1..f1148b91a0 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll index 4b2446e402..65780a0abc 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll index c5491ded56..845c53a02c 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll index d034156af4..a376584495 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll index 3030bfd9ab..8f0162022e 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll index 444bef56fc..663c7f7bce 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll index a725764f7e..217f86bf3d 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll index 3daf701f6e..5203bc4d2c 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll index f6541e7ed9..db9648b7e6 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll index cdec1b413b..f98751e959 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll index 969e5ae2a6..4c82303c57 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll index 5dd8bd0882..ab429cb02b 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll index 3e02219269..49a1e20849 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll index 2a38b72e7e..e90f1d70e0 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll index 9c1999d26a..951c46bafc 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll index acb2aef351..8d933d2770 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll index 74bb42f5dd..75d4b9adb4 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll index bc5bd36b6c..5e934e41c1 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll index 1a8ede4067..ba2305b951 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll index 3c387b8a84..8975b052ef 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll index b4af7de601..c34893657f 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll index f7a43c8dcb..a22d349dc7 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll index 520abde56a..56afba5126 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll index 9cdd17fee4..0701f24c0b 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll index 687677bbcb..4ce344767c 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll index 02b58ca2bf..5ebf27987a 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll index 2933850e4e..b26df55339 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll index 4137c5ba6e..c291105d4a 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll index 9087ef6bf1..2b6d0d7dfb 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll index 2bccc5e87d..ea7fce01a1 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll index 18d3c28e71..0f37a2ef37 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll index e031bc14f7..f23681ba9f 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll index 296ab24a31..f75047a6f4 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll index 65a2ea3f81..42d38f5d3a 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll index 949bba8fe3..17fdd0eab3 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll index 3c657d8a8f..7ffa412d1c 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll index 5175fa5d6c..73e07c4c41 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll index 15c94408f5..0cfe1737df 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll index 0962a04e07..2ddb99874d 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll index b01d23d9ff..49fc505232 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll index f1ee2b4949..00a3f1f6ca 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll index e014ccb424..d60711cd6e 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll index 80f835d29e..44e6ab6d2f 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll index e9a8979d3a..91384d7cf6 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll index 54167a482b..89daffc9a3 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll index f35f09d680..bd3c71633d 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll index 64b42a3e56..698abcd109 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll index fa1c300f4e..87563ee328 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll index b279705869..42d30da76a 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll index 184cf7d937..c5a39147ab 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll index 199943c461..75b314035c 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll index e067f41804..fccc55dc02 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll index bf7ebfc164..9c431df6b9 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll index f2e7c8a5eb..177918b44d 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll index 547c182215..cabf8d6a00 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll index e906017238..536355c019 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll index 28af65dc8c..82ce7afe0d 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll index 48474297cf..4ab0d32145 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_store_wait.ll b/intrinsics/probes/tcgen05_store_wait.ll index ce266a9a56..c7b77c4456 100644 --- a/intrinsics/probes/tcgen05_store_wait.ll +++ b/intrinsics/probes/tcgen05_store_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_box_dim.ll b/intrinsics/probes/tensormap_replace_box_dim.ll index bdbb1ce2f1..85b489065a 100644 --- a/intrinsics/probes/tensormap_replace_box_dim.ll +++ b/intrinsics/probes/tensormap_replace_box_dim.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_element_stride.ll b/intrinsics/probes/tensormap_replace_element_stride.ll index 71306b0e4d..b4ba90c6ae 100644 --- a/intrinsics/probes/tensormap_replace_element_stride.ll +++ b/intrinsics/probes/tensormap_replace_element_stride.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_element_type.ll b/intrinsics/probes/tensormap_replace_element_type.ll index ee9e72e6ad..69b916261e 100644 --- a/intrinsics/probes/tensormap_replace_element_type.ll +++ b/intrinsics/probes/tensormap_replace_element_type.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_fill_mode.ll b/intrinsics/probes/tensormap_replace_fill_mode.ll index f5c8171578..3974180e60 100644 --- a/intrinsics/probes/tensormap_replace_fill_mode.ll +++ b/intrinsics/probes/tensormap_replace_fill_mode.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_address.ll b/intrinsics/probes/tensormap_replace_global_address.ll index b941d8912d..1c23cd9df9 100644 --- a/intrinsics/probes/tensormap_replace_global_address.ll +++ b/intrinsics/probes/tensormap_replace_global_address.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_dim.ll b/intrinsics/probes/tensormap_replace_global_dim.ll index dc9153a1a0..72757a1697 100644 --- a/intrinsics/probes/tensormap_replace_global_dim.ll +++ b/intrinsics/probes/tensormap_replace_global_dim.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_stride.ll b/intrinsics/probes/tensormap_replace_global_stride.ll index 74aa264102..42a27ff5db 100644 --- a/intrinsics/probes/tensormap_replace_global_stride.ll +++ b/intrinsics/probes/tensormap_replace_global_stride.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_interleave_layout.ll b/intrinsics/probes/tensormap_replace_interleave_layout.ll index 7699ee1ff4..4ac181b11b 100644 --- a/intrinsics/probes/tensormap_replace_interleave_layout.ll +++ b/intrinsics/probes/tensormap_replace_interleave_layout.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_rank.ll b/intrinsics/probes/tensormap_replace_rank.ll index b2d296e16a..532aa02861 100644 --- a/intrinsics/probes/tensormap_replace_rank.ll +++ b/intrinsics/probes/tensormap_replace_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll b/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll index 463270654d..503ecebaed 100644 --- a/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll +++ b/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_swizzle_mode.ll b/intrinsics/probes/tensormap_replace_swizzle_mode.ll index 43766f3f7f..b14e74b8df 100644 --- a/intrinsics/probes/tensormap_replace_swizzle_mode.ll +++ b/intrinsics/probes/tensormap_replace_swizzle_mode.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_x.ll b/intrinsics/probes/thread_idx_x.ll index d2351c570a..c6361ca94b 100644 --- a/intrinsics/probes/thread_idx_x.ll +++ b/intrinsics/probes/thread_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_y.ll b/intrinsics/probes/thread_idx_y.ll index dd644c2abf..66fe3ed667 100644 --- a/intrinsics/probes/thread_idx_y.ll +++ b/intrinsics/probes/thread_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_z.ll b/intrinsics/probes/thread_idx_z.ll index 5c1fc163f1..c2511dd6eb 100644 --- a/intrinsics/probes/thread_idx_z.ll +++ b/intrinsics/probes/thread_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence.ll b/intrinsics/probes/threadfence.ll index 071944d734..d175854397 100644 --- a/intrinsics/probes/threadfence.ll +++ b/intrinsics/probes/threadfence.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence_block.ll b/intrinsics/probes/threadfence_block.ll index a6f595b6f8..fc716dddc1 100644 --- a/intrinsics/probes/threadfence_block.ll +++ b/intrinsics/probes/threadfence_block.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence_system.ll b/intrinsics/probes/threadfence_system.ll index 8d81ee537e..7022353986 100644 --- a/intrinsics/probes/threadfence_system.ll +++ b/intrinsics/probes/threadfence_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/total_smem_size.lib_nvvm.ll b/intrinsics/probes/total_smem_size.lib_nvvm.ll index bdc60a9924..3e93b48ff4 100644 --- a/intrinsics/probes/total_smem_size.lib_nvvm.ll +++ b/intrinsics/probes/total_smem_size.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/total_smem_size.llvm_nvptx.ll b/intrinsics/probes/total_smem_size.llvm_nvptx.ll index 6b3f8c55fd..bd92e85694 100644 --- a/intrinsics/probes/total_smem_size.llvm_nvptx.ll +++ b/intrinsics/probes/total_smem_size.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/trap.ll b/intrinsics/probes/trap.ll index 81acd9e0fe..1bb4051a7d 100644 --- a/intrinsics/probes/trap.ll +++ b/intrinsics/probes/trap.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/uni_sync.ll b/intrinsics/probes/uni_sync.ll index aa9a5ae28c..754ee7b739 100644 --- a/intrinsics/probes/uni_sync.ll +++ b/intrinsics/probes/uni_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/warpid.lib_nvvm.ll b/intrinsics/probes/warpid.lib_nvvm.ll index b009ad1d2d..d6df043f05 100644 --- a/intrinsics/probes/warpid.lib_nvvm.ll +++ b/intrinsics/probes/warpid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/warpid.llvm_nvptx.ll b/intrinsics/probes/warpid.llvm_nvptx.ll index e1ab6cd11d..850cc34199 100644 --- a/intrinsics/probes/warpid.llvm_nvptx.ll +++ b/intrinsics/probes/warpid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_commit_group.ll b/intrinsics/probes/wgmma_commit_group.ll index 495a977a43..f394483839 100644 --- a/intrinsics/probes/wgmma_commit_group.ll +++ b/intrinsics/probes/wgmma_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_fence.ll b/intrinsics/probes/wgmma_fence.ll index a901d9c947..1d8a669d38 100644 --- a/intrinsics/probes/wgmma_fence.ll +++ b/intrinsics/probes/wgmma_fence.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_wait_group.ll b/intrinsics/probes/wgmma_wait_group.ll index 77d9a540f2..04acead748 100644 --- a/intrinsics/probes/wgmma_wait_group.ll +++ b/intrinsics/probes/wgmma_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: a6962ae6c56aec0716a291570b7ac8e02bd1e4052ee151affa72d372f17faf3a. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 91c449f0f24034cc5016145e0267208394a0863995da74ec41064fccdc87a82d. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" From a6dde6720139b0fd65fab3cabc8643fb993ce64b Mon Sep 17 00:00:00 2001 From: nihalpasham Date: Sun, 30 Aug 2026 16:28:12 +0530 Subject: [PATCH 5/5] docs(book): re-stamp the dialect page for the re-attested catalog The evidence re-attestation renamed the libNVVM evidence profile, which is recorded in intrinsics/catalog.json, so the catalog hash moved again after the page was stamped for the i1017-i1024 regeneration: stamp a6962ae6 -> 91c449f0 counts unchanged (the eight float forms resolve onto the shared sparse-MMA structural op; entries were already 1024) Signed-off-by: nihalpasham --- cuda-oxide-book/compiler/mlir-dialects.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cuda-oxide-book/compiler/mlir-dialects.md b/cuda-oxide-book/compiler/mlir-dialects.md index af51fbfd29..7e9e65a0e9 100644 --- a/cuda-oxide-book/compiler/mlir-dialects.md +++ b/cuda-oxide-book/compiler/mlir-dialects.md @@ -296,11 +296,11 @@ they become `call` instructions to `@llvm.nvvm.*` intrinsics. ### Architecture Coverage -At catalog SHA-256 `a6962ae6` (the stamp in every `ops/generated/` file +At catalog SHA-256 `91c449f0` (the stamp in every `ops/generated/` file header), the dialect holds 575 operations across 42 modules, and they come from two different places. The split is the first thing to know about it, because it decides where -- and whether -- you would add one. If the header -stamp no longer starts with `a6962ae6`, the counts on this page predate the +stamp no longer starts with `91c449f0`, the counts on this page predate the catalog you are reading. **Hand-written**, directly under `crates/dialect-nvvm/src/ops/`. These are the